[PATCH 05/14] UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiStack" with PatchInstructionX86()

[Laszlo Ersek <lersek@redhat.com>]

Rename the variable to "gPatchSmiStack" so that its association with
PatchInstructionX86() is clear from the declaration. Also change its type
to UINT8.

Unlike "gSmbase" in the previous patch, "gSmiStack"'s patched value is
also de-referenced by C code (in other words, it is read back after
patching): the InstallSmiHandler() function stores "CpuIndex" to the given
CPU's SMI stack through "gSmiStack". Introduce the local variable
"CpuSmiStack" in InstallSmiHandler() for calculating the stack location
separately, then use this variable for both patching into the assembly
code, and for storing "CpuIndex" through it.

It's assumed that "volatile" stood in the declaration of "gSmiStack"
because we used to read "gSmiStack" back for de-referencing; with that use
gone, we can remove "volatile" too. (Note that the *target* of the pointer
was never volatile-qualified.)

Finally, replace the binary (DB) encoding of "mov esp, imm32" in
"SmiEntry.nasm".

Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c   | 8 +++++---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 6 +++---
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm  | 6 +++---
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
index c13692127fcf..73253016060d 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
@@ -106,7 +106,7 @@ typedef struct {
 /// Variables from SMI Handler
 ///
 extern UINT8            gPatchSmbase;
-extern volatile UINT32  gSmiStack;
+extern UINT8            gPatchSmiStack;
 extern UINT32           gSmiCr3;
 extern volatile UINT8   gcSmiHandlerTemplate[];
 extern CONST UINT16     gcSmiHandlerSize;
@@ -686,6 +686,7 @@ InstallSmiHandler (
   )
 {
   PROCESSOR_SMM_DESCRIPTOR  *Psd;
+  UINT32                    CpuSmiStack;
 
   //
   // Initialize PROCESSOR_SMM_DESCRIPTOR
@@ -716,7 +717,8 @@ InstallSmiHandler (
   //
   // Initialize values in template before copy
   //
-  gSmiStack             = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN));
+  CpuSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN));
+  PatchInstructionX86 (&gPatchSmiStack, CpuSmiStack, 4);
   gSmiCr3               = Cr3;
   PatchInstructionX86 (&gPatchSmbase, SmBase, 4);
   gSmiHandlerIdtr.Base  = IdtBase;
@@ -725,7 +727,7 @@ InstallSmiHandler (
   //
   // Set the value at the top of the CPU stack to the CPU Index
   //
-  *(UINTN*)(UINTN)gSmiStack = CpuIndex;
+  *(UINTN*)(UINTN)CpuSmiStack = CpuIndex;
 
   //
   // Copy template to CPU specific SMI handler location
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index e6e29128e64e..0ea3c1e4498d 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -45,7 +45,7 @@ extern ASM_PFX(CpuSmmDebugExit)
 global ASM_PFX(gcSmiHandlerTemplate)
 global ASM_PFX(gcSmiHandlerSize)
 global ASM_PFX(gSmiCr3)
-global ASM_PFX(gSmiStack)
+global ASM_PFX(gPatchSmiStack)
 global ASM_PFX(gPatchSmbase)
 global ASM_PFX(mXdSupported)
 extern ASM_PFX(gSmiHandlerIdtr)
@@ -86,8 +86,8 @@ o16 mov     es, ax
 o16 mov     fs, ax
 o16 mov     gs, ax
 o16 mov     ss, ax
-    DB      0xbc                   ; mov esp, imm32
-ASM_PFX(gSmiStack): DD 0
+    mov esp, strict dword 0               ; source operand will be patched
+ASM_PFX(gPatchSmiStack):
     mov     eax, ASM_PFX(gSmiHandlerIdtr)
     lidt    [eax]
     jmp     ProtFlatMode
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index 0e314279a541..9cfa8e7fc8f4 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -55,7 +55,7 @@ extern ASM_PFX(CpuSmmDebugExit)
 
 global ASM_PFX(gPatchSmbase)
 global ASM_PFX(mXdSupported)
-global ASM_PFX(gSmiStack)
+global ASM_PFX(gPatchSmiStack)
 global ASM_PFX(gSmiCr3)
 global ASM_PFX(gcSmiHandlerTemplate)
 global ASM_PFX(gcSmiHandlerSize)
@@ -96,8 +96,8 @@ o16 mov     es, ax
 o16 mov     fs, ax
 o16 mov     gs, ax
 o16 mov     ss, ax
-    DB      0xbc                   ; mov esp, imm32
-ASM_PFX(gSmiStack): DD 0
+    mov esp, strict dword 0               ; source operand will be patched
+ASM_PFX(gPatchSmiStack):
     jmp     ProtFlatMode
 
 BITS 64
-- 
2.14.1.3.gb7cf6e02401b