From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=209.132.183.28; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 13FAF2215BD97 for ; Fri, 2 Feb 2018 06:34:39 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1E6CEC058ED8; Fri, 2 Feb 2018 14:40:17 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-121-50.rdu2.redhat.com [10.10.121.50]) by smtp.corp.redhat.com (Postfix) with ESMTP id 79D5017DEA; Fri, 2 Feb 2018 14:40:15 +0000 (UTC) From: Laszlo Ersek To: edk2-devel-01 Cc: Eric Dong , Jiewen Yao , Liming Gao , Michael D Kinney , Ruiyu Ni Date: Fri, 2 Feb 2018 15:39:45 +0100 Message-Id: <20180202143954.7357-6-lersek@redhat.com> In-Reply-To: <20180202143954.7357-1-lersek@redhat.com> References: <20180202143954.7357-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Fri, 02 Feb 2018 14:40:17 +0000 (UTC) Subject: [PATCH 05/14] UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiStack" with PatchInstructionX86() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Feb 2018 14:34:39 -0000 Rename the variable to "gPatchSmiStack" so that its association with PatchInstructionX86() is clear from the declaration. Also change its type to UINT8. Unlike "gSmbase" in the previous patch, "gSmiStack"'s patched value is also de-referenced by C code (in other words, it is read back after patching): the InstallSmiHandler() function stores "CpuIndex" to the given CPU's SMI stack through "gSmiStack". Introduce the local variable "CpuSmiStack" in InstallSmiHandler() for calculating the stack location separately, then use this variable for both patching into the assembly code, and for storing "CpuIndex" through it. It's assumed that "volatile" stood in the declaration of "gSmiStack" because we used to read "gSmiStack" back for de-referencing; with that use gone, we can remove "volatile" too. (Note that the *target* of the pointer was never volatile-qualified.) Finally, replace the binary (DB) encoding of "mov esp, imm32" in "SmiEntry.nasm". Cc: Eric Dong Cc: Jiewen Yao Cc: Liming Gao Cc: Michael D Kinney Cc: Ruiyu Ni Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek --- UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 8 +++++--- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 6 +++--- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 6 +++--- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c index c13692127fcf..73253016060d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c @@ -106,7 +106,7 @@ typedef struct { /// Variables from SMI Handler /// extern UINT8 gPatchSmbase; -extern volatile UINT32 gSmiStack; +extern UINT8 gPatchSmiStack; extern UINT32 gSmiCr3; extern volatile UINT8 gcSmiHandlerTemplate[]; extern CONST UINT16 gcSmiHandlerSize; @@ -686,6 +686,7 @@ InstallSmiHandler ( ) { PROCESSOR_SMM_DESCRIPTOR *Psd; + UINT32 CpuSmiStack; // // Initialize PROCESSOR_SMM_DESCRIPTOR @@ -716,7 +717,8 @@ InstallSmiHandler ( // // Initialize values in template before copy // - gSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN)); + CpuSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN)); + PatchInstructionX86 (&gPatchSmiStack, CpuSmiStack, 4); gSmiCr3 = Cr3; PatchInstructionX86 (&gPatchSmbase, SmBase, 4); gSmiHandlerIdtr.Base = IdtBase; @@ -725,7 +727,7 @@ InstallSmiHandler ( // // Set the value at the top of the CPU stack to the CPU Index // - *(UINTN*)(UINTN)gSmiStack = CpuIndex; + *(UINTN*)(UINTN)CpuSmiStack = CpuIndex; // // Copy template to CPU specific SMI handler location diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm index e6e29128e64e..0ea3c1e4498d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -45,7 +45,7 @@ extern ASM_PFX(CpuSmmDebugExit) global ASM_PFX(gcSmiHandlerTemplate) global ASM_PFX(gcSmiHandlerSize) global ASM_PFX(gSmiCr3) -global ASM_PFX(gSmiStack) +global ASM_PFX(gPatchSmiStack) global ASM_PFX(gPatchSmbase) global ASM_PFX(mXdSupported) extern ASM_PFX(gSmiHandlerIdtr) @@ -86,8 +86,8 @@ o16 mov es, ax o16 mov fs, ax o16 mov gs, ax o16 mov ss, ax - DB 0xbc ; mov esp, imm32 -ASM_PFX(gSmiStack): DD 0 + mov esp, strict dword 0 ; source operand will be patched +ASM_PFX(gPatchSmiStack): mov eax, ASM_PFX(gSmiHandlerIdtr) lidt [eax] jmp ProtFlatMode diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm index 0e314279a541..9cfa8e7fc8f4 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -55,7 +55,7 @@ extern ASM_PFX(CpuSmmDebugExit) global ASM_PFX(gPatchSmbase) global ASM_PFX(mXdSupported) -global ASM_PFX(gSmiStack) +global ASM_PFX(gPatchSmiStack) global ASM_PFX(gSmiCr3) global ASM_PFX(gcSmiHandlerTemplate) global ASM_PFX(gcSmiHandlerSize) @@ -96,8 +96,8 @@ o16 mov es, ax o16 mov fs, ax o16 mov gs, ax o16 mov ss, ax - DB 0xbc ; mov esp, imm32 -ASM_PFX(gSmiStack): DD 0 + mov esp, strict dword 0 ; source operand will be patched +ASM_PFX(gPatchSmiStack): jmp ProtFlatMode BITS 64 -- 2.14.1.3.gb7cf6e02401b