From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9F34822361E60 for ; Thu, 8 Feb 2018 02:16:16 -0800 (PST) Received: by mail-wr0-x243.google.com with SMTP id 111so1216757wrb.13 for ; Thu, 08 Feb 2018 02:22:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=5uudqqshM/5vLPL3u1tFuuWxIQJBWY56u3zAm7ti8As=; b=ZLU/Yp8l0gMZPhZ2QU2xIECbrhtOLDCyi1z+zvN9LnP0Q8Ufe7tATskV+eCyrQmFzF zvyWZYwZZPp+xY+RsNOzywEGBcNj/7dm/WnaKnyRLyEZzSQw4v5nPae9AteVS8Nad9Zc 11oykpL9iMbwyN+g0l0vTDbR6yzbGVqh830no= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=5uudqqshM/5vLPL3u1tFuuWxIQJBWY56u3zAm7ti8As=; b=kZT3tynFtpakOSsuevq8H7T3dydar4nariN11pFICj1xhBtqR8NZCulZJfs6i2X1ZT RHAB6XZKY9jro7fQHVPULDepEmrh+oMZ7794zM7C7Z2nspIJEPBhVxeoDY5NL8Ug5+m4 l7AcXsVaveHaSLjF5I2+mls+f821krCJlZdkszO1D+DAOcfvAx2tAuXMVrxVLfnVc6kx u5j4BQSBiXHcK2QXDU6V9aoJk7tKwi/RHMQSzZYO6Yne92Fc6mmasO4hFaMrEupcEHyz +uTe+3oGuKgMxecNwDdi+p8QwgJYDmsbOckCtSIsO8l73KQrZXyDwxkltlTc4tVYNZp2 p4bw== X-Gm-Message-State: APf1xPAO3nkIdBjgskpXdWE0SjW2UQzSQdjeeL0r3xaEs3CL8YCN+A2q shbsvthQvv9cBpiqyHZMdwAHmA== X-Google-Smtp-Source: AH8x227uJ5rOZhpA07Ae6xFPwVVCgVhSnUm+EsSLHJhzZml6uVSxqAxNgaOFkdoEx0ixKdBDAFdV3A== X-Received: by 10.223.131.133 with SMTP id 5mr184237wre.153.1518085320094; Thu, 08 Feb 2018 02:22:00 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id j126sm3243316wmj.44.2018.02.08.02.21.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Feb 2018 02:21:59 -0800 (PST) Date: Thu, 8 Feb 2018 10:21:57 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, masahisa.kojima@linaro.org Message-ID: <20180208102157.jabpvo6gbj6fozjl@bivouac.eciton.net> References: <20180208101812.4353-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180208101812.4353-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacer/PlatformDxe: disable eMMC DDR50 support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Feb 2018 10:16:17 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Feb 08, 2018 at 10:18:12AM +0000, Ard Biesheuvel wrote: > We already disable SDR104 support on the SynQuacer eMMC controller to > work around the need for a special tuning quirk that is difficult to > implement without modifying the generic driver, even in the presence > of a SD/MMC override protocol designed to carry such quirks. > > Unfortunately, as it turns out, DDR50 does not work either with the > particular 8 GB Kingston part that has been fitted on the rev0.2/0.3 > 96board samples. Since the mode UEFI drives the eMMC in is independent > from what the OS chooses, and the fact that you would not use eMMC in > the first place if performance was a major concern, let's just disable > DDR50 as well, and fall back to SDR50 mode. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c > index c40b30929d5d..6875dfe6b319 100644 > --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c > +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c > @@ -52,6 +52,7 @@ > #define SYNQUACER_CLOCK_CTRL_VAL 0xBC01 > > #define SD_HC_CAP_SDR104 BIT33 > +#define SD_HC_CAP_DDR50 BIT34 > > #define ESD_CONTROL_RESET_DELAY (20 * 1000) > #define IO_CONTROL2_SETTLE_US 3000 > @@ -95,7 +96,7 @@ SynQuacerSdMmcCapability ( > // quirk that is difficult to support using the generic driver. > // > Capability = ReadUnaligned64 (SdMmcHcSlotCapability); > - Capability &= ~(UINT64)SD_HC_CAP_SDR104; > + Capability &= ~(UINT64)(SD_HC_CAP_SDR104 | SD_HC_CAP_DDR50); > WriteUnaligned64 (SdMmcHcSlotCapability, Capability); > > return EFI_SUCCESS; > -- > 2.11.0 >