[PATCH 0/4] Add ARM64 support for VS2017

[PATCH 0/4] Add ARM64 support for VS2017

[Pete Batard]

This series completes VS2017 support by enabling AARCH64 compilation.
* PATCH 1 targets the disabling of VS Level 4 warnings. The disabled
  warnings for ARM64 are the same as the ones for IA32, X64 and ARM.
* PATCH 2 adds assembly source in MdePkg/Library/BaseLib for various low
  level required functions. These new assembly files were converted from
  their GCC version, with minor changes applied to make them palatable
  to the MSFT assembler.
* PATCH 3 adds variable argument handlers for print output. This is
  achieved without relying on any external toolchain headers. However
  a call to the __va_start() compiler intrinsic function is now being
  used for the VA_START macros, which we apply for ARM as well.
* PATCH 4 enables the selection of ARM64 in the conf templates.
  One item of note is that the build options for ARM64 are the same as
  for ARM, except for /BASE:0 which was removed to avoid error:
  'invalid base address 0x0; ARM64 image cannot have base address below 4GB'

With these patches, VS2017 toolchain users should be able to compile
regular UEFI ARM64 applications using EDK2.

Note however that ARM64 support requires the use of Visual Studio 2017
Update 4 or later (a.k.a. v15.4), as native ARM64 compilation was not
included in any version of Visual Studio prior to that.

Additional notes:

We tested compiling and running the full UEFI Shell with this series, as
well as a small set of applications and drivers, and saw no issues.
Since we also modified the VA_START() macro for ARM, we also re-ran
similar tests for ARM, to confirm that there was no regression there.

Finally, we did not test the generation of a complete QEMU ARM64 firmware
as it requires porting a handful of assembly sources, that don't exist
yet, and our focus is with the generation of working AARCH64 drivers or
applications. Hopefully, this can be tackled as VS2017/ARM64 sees more
usage...

Regards,

/Pete


Pete Batard (4):
  MdePkg: Disable some Level 4 warnings for VS2017/ARM64
  MdePkg/Library/BaseLib: Enable VS2017/ARM64 builds
  MdePkg/Include: Add VA list support for VS2017/ARM64
  BaseTools/Conf: Add VS2017/ARM64 support

 BaseTools/Conf/build_rule.template                    |   2 +-
 BaseTools/Conf/tools_def.template                     |  32 ++++++-
 MdePkg/Include/AArch64/ProcessorBind.h                |  53 +++++++++-
 MdePkg/Include/Base.h                                 |   7 +-
 MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm      |  39 ++++++++
 MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm  |  37 +++++++
 MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm   |  37 +++++++
 MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm |  49 ++++++++++
 MdePkg/Library/BaseLib/AArch64/MemoryFence.asm        |  38 ++++++++
 MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm    | 101 ++++++++++++++++++++
 MdePkg/Library/BaseLib/AArch64/SwitchStack.asm        |  69 +++++++++++++
 MdePkg/Library/BaseLib/BaseLib.inf                    |   8 ++
 12 files changed, 463 insertions(+), 9 deletions(-)
 create mode 100644 MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm
 create mode 100644 MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm
 create mode 100644 MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm
 create mode 100644 MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm
 create mode 100644 MdePkg/Library/BaseLib/AArch64/MemoryFence.asm
 create mode 100644 MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm
 create mode 100644 MdePkg/Library/BaseLib/AArch64/SwitchStack.asm

-- 
2.9.3.windows.2

[PATCH 1/4] MdePkg: Disable some Level 4 warnings for VS2017/ARM64

[Pete Batard]

We disable the exact same warnings as IA32 and X64.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Pete Batard <pete@akeo.ie>
---
 MdePkg/Include/AArch64/ProcessorBind.h | 53 +++++++++++++++++++-
 1 file changed, 51 insertions(+), 2 deletions(-)

diff --git a/MdePkg/Include/AArch64/ProcessorBind.h b/MdePkg/Include/AArch64/ProcessorBind.h
index bc473562f9e5..4f341ebeb03f 100644
--- a/MdePkg/Include/AArch64/ProcessorBind.h
+++ b/MdePkg/Include/AArch64/ProcessorBind.h
@@ -1,7 +1,7 @@
 /** @file
   Processor or Compiler specific defines and types for AArch64.
 
-  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
 
@@ -30,7 +30,56 @@
 #pragma pack()
 #endif
 
-#if _MSC_EXTENSIONS
+#if defined(_MSC_EXTENSIONS)
+
+//
+// Disable some level 4 compilation warnings (same as IA32 and X64)
+//
+
+//
+// Disabling bitfield type checking warnings.
+//
+#pragma warning ( disable : 4214 )
+
+//
+// Disabling the unreferenced formal parameter warnings.
+//
+#pragma warning ( disable : 4100 )
+
+//
+// Disable slightly different base types warning as CHAR8 * can not be set
+// to a constant string.
+//
+#pragma warning ( disable : 4057 )
+
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
+//
+#pragma warning ( disable : 4127 )
+
+//
+// This warning is caused by functions defined but not used. For precompiled header only.
+//
+#pragma warning ( disable : 4505 )
+
+//
+// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
+//
+#pragma warning ( disable : 4206 )
+
+//
+// Disable 'potentially uninitialized local variable X used' warnings
+//
+#pragma warning ( disable : 4701 )
+
+//
+// Disable 'potentially uninitialized local pointer variable X used' warnings
+//
+#pragma warning ( disable : 4703 )
+
+#endif
+
+#if defined(_MSC_EXTENSIONS)
   //
   // use Microsoft* C compiler dependent integer width types
   //
-- 
2.9.3.windows.2

[PATCH 2/4] MdePkg/Library/BaseLib: Enable VS2017/ARM64 builds

[Pete Batard]

Required GCC assembly files are converted for the MSFT assembler

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Pete Batard <pete@akeo.ie>
---
 MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm      |  39 ++++++++
 MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm  |  37 +++++++
 MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm   |  37 +++++++
 MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm |  49 ++++++++++
 MdePkg/Library/BaseLib/AArch64/MemoryFence.asm        |  38 ++++++++
 MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm    | 101 ++++++++++++++++++++
 MdePkg/Library/BaseLib/AArch64/SwitchStack.asm        |  69 +++++++++++++
 MdePkg/Library/BaseLib/BaseLib.inf                    |   8 ++
 8 files changed, 378 insertions(+)

diff --git a/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm b/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm
new file mode 100644
index 000000000000..17e993f5b77e
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm
@@ -0,0 +1,39 @@
+;------------------------------------------------------------------------------
+;
+; CpuBreakpoint() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+
+  EXPORT CpuBreakpoint
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+;  Generates a breakpoint on the CPU.
+;
+;  Generates a breakpoint on the CPU. The breakpoint must be implemented such
+;  that code can resume normal execution after the breakpoint.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuBreakpoint (
+;  VOID
+;  );
+;
+CpuBreakpoint
+    svc   0xdbdb    // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm b/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm
new file mode 100644
index 000000000000..498493454c7d
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------
+;
+; DisableInterrupts() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+  EXPORT DisableInterrupts
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_WR_IRQ_BIT     EQU     (1 << 1)
+
+;/**
+;  Disables CPU interrupts.
+;
+;**/
+;VOID
+;EFIAPI
+;DisableInterrupts (
+;  VOID
+;  );
+;
+DisableInterrupts
+    msr  daifset, #DAIF_WR_IRQ_BIT
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm b/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm
new file mode 100644
index 000000000000..ec3d6e45ff8a
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------
+;
+; EnableInterrupts() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+  EXPORT EnableInterrupts
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_WR_IRQ_BIT     EQU     (1 << 1)
+
+;/**
+;  Enables CPU interrupts.
+;
+;**/
+;VOID
+;EFIAPI
+;EnableInterrupts (
+;  VOID
+;  );
+;
+EnableInterrupts
+    msr  daifclr, #DAIF_WR_IRQ_BIT
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm b/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm
new file mode 100644
index 000000000000..d64b0d513ce3
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm
@@ -0,0 +1,49 @@
+;------------------------------------------------------------------------------
+;
+; GetInterruptState() function for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+  EXPORT GetInterruptState
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_RD_IRQ_BIT     EQU     (1 << 7)
+
+;/**
+;  Retrieves the current CPU interrupt state.
+;
+;  Returns TRUE is interrupts are currently enabled. Otherwise
+;  returns FALSE.
+;
+;  @retval TRUE  CPU interrupts are enabled.
+;  @retval FALSE CPU interrupts are disabled.
+;
+;**/
+;
+;BOOLEAN
+;EFIAPI
+;GetInterruptState (
+;  VOID
+; );
+;
+GetInterruptState
+    mrs    x0, daif
+    mov    w0, wzr
+    tst    x0, #DAIF_RD_IRQ_BIT   // Check IRQ mask; set Z=1 if clear/unmasked
+    bne    exit                   // if Z=1 (eq) return 1, else 0
+    mov    w0, #1
+exit
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm b/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm
new file mode 100644
index 000000000000..84dede698ee0
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm
@@ -0,0 +1,38 @@
+;------------------------------------------------------------------------------
+;
+; MemoryFence() for AArch64
+;
+; Copyright (c) 2013, ARM Ltd. All rights reserved.
+;
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+  EXPORT MemoryFence
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+;  Used to serialize load and store operations.
+;
+;  All loads and stores that proceed calls to this function are guaranteed to be
+;  globally visible when this function returns.
+;
+;**/
+;VOID
+;EFIAPI
+;MemoryFence (
+;  VOID
+;  );
+;
+MemoryFence
+    // System wide Data Memory Barrier.
+    dmb sy
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm b/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm
new file mode 100644
index 000000000000..e0a9715ff2d1
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm
@@ -0,0 +1,101 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2009-2013, ARM Ltd.  All rights reserved.
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+  EXPORT SetJump
+  EXPORT InternalLongJump
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+#define GPR_LAYOUT                          \
+        REG_PAIR (x19, x20,  #0);           \
+        REG_PAIR (x21, x22, #16);           \
+        REG_PAIR (x23, x24, #32);           \
+        REG_PAIR (x25, x26, #48);           \
+        REG_PAIR (x27, x28, #64);           \
+        REG_PAIR (x29, x30, #80);/*FP, LR*/ \
+        REG_ONE  (x16,      #96) /*IP0*/
+
+#define FPR_LAYOUT                       \
+        REG_PAIR ( d8,  d9, #112);       \
+        REG_PAIR (d10, d11, #128);       \
+        REG_PAIR (d12, d13, #144);       \
+        REG_PAIR (d14, d15, #160);
+
+;/**
+;  Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#
+;
+;  Saves the current CPU context in the buffer specified by JumpBuffer and returns 0.  The initial
+;  call to SetJump() must always return 0.  Subsequent calls to LongJump() cause a non-zero
+;  value to be returned by SetJump().
+;
+;  If JumpBuffer is NULL, then ASSERT().
+;  For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+;
+;  @param  JumpBuffer    A pointer to CPU context buffer.
+;
+;**/
+;
+;UINTN
+;EFIAPI
+;SetJump (
+;  IN      BASE_LIBRARY_JUMP_BUFFER  *JumpBuffer  // X0
+;  );
+;
+SetJump
+        mov     x16, sp // use IP0 so save SP
+#define REG_PAIR(REG1, REG2, OFFS)      stp REG1, REG2, [x0, OFFS]
+#define REG_ONE(REG1, OFFS)             str REG1, [x0, OFFS]
+        GPR_LAYOUT
+        FPR_LAYOUT
+#undef REG_PAIR
+#undef REG_ONE
+        mov     w0, #0
+        ret
+
+;/**
+;  Restores the CPU context that was saved with SetJump().#
+;
+;  Restores the CPU context from the buffer specified by JumpBuffer.
+;  This function never returns to the caller.
+;  Instead is resumes execution based on the state of JumpBuffer.
+;
+;  @param  JumpBuffer    A pointer to CPU context buffer.
+;  @param  Value         The value to return when the SetJump() context is restored.
+;
+;**/
+;VOID
+;EFIAPI
+;InternalLongJump (
+;  IN      BASE_LIBRARY_JUMP_BUFFER  *JumpBuffer,  // X0
+;  IN      UINTN                     Value         // X1
+;  );
+;
+InternalLongJump
+#define REG_PAIR(REG1, REG2, OFFS)      ldp REG1, REG2, [x0, OFFS]
+#define REG_ONE(REG1, OFFS)             ldr REG1, [x0, OFFS]
+        GPR_LAYOUT
+        FPR_LAYOUT
+#undef REG_PAIR
+#undef REG_ONE
+        mov     sp, x16
+        cmp     w1, #0
+        mov     w0, #1
+        beq     exit
+        mov     w0, w1
+exit
+        // use br not ret, as ret is guaranteed to mispredict
+        br      x30
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+
+  END
+
diff --git a/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm b/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm
new file mode 100644
index 000000000000..c1b2de07e205
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm
@@ -0,0 +1,69 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+// Portions copyright (c) 2011 - 2013, ARM Limited. All rights reserved.<BR>
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+  EXPORT InternalSwitchStackAsm
+  EXPORT CpuPause
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+/**
+//
+//  This allows the caller to switch the stack and goes to the new entry point
+//
+// @param      EntryPoint   The pointer to the location to enter
+// @param      Context      Parameter to pass in
+// @param      Context2     Parameter2 to pass in
+// @param      NewStack     New Location of the stack
+//
+// @return     Nothing. Goes to the Entry Point passing in the new parameters
+//
+VOID
+EFIAPI
+InternalSwitchStackAsm (
+  SWITCH_STACK_ENTRY_POINT EntryPoint,
+  VOID  *Context,
+  VOID  *Context2,
+  VOID  *NewStack
+  );
+**/
+InternalSwitchStackAsm
+    mov   x29, #0
+    mov   x30, x0
+    mov   sp, x3
+    mov   x0, x1
+    mov   x1, x2
+    ret
+
+/**
+//
+//  Requests CPU to pause for a short period of time.
+//
+//  Requests CPU to pause for a short period of time. Typically used in MP
+//  systems to prevent memory starvation while waiting for a spin lock.
+//
+VOID
+EFIAPI
+CpuPause (
+  VOID
+  )
+**/
+CpuPause
+    nop
+    nop
+    nop
+    nop
+    nop
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 3c07e6bad977..80d00ebed75b 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -867,6 +867,14 @@ [Sources.AARCH64]
   AArch64/SetJumpLongJump.S         | GCC
   AArch64/CpuBreakpoint.S           | GCC
 
+  AArch64/MemoryFence.asm           | MSFT
+  AArch64/SwitchStack.asm           | MSFT
+  AArch64/EnableInterrupts.asm      | MSFT
+  AArch64/DisableInterrupts.asm     | MSFT
+  AArch64/GetInterruptsState.asm    | MSFT
+  AArch64/SetJumpLongJump.asm       | MSFT
+  AArch64/CpuBreakpoint.asm         | MSFT
+
 [Packages]
   MdePkg/MdePkg.dec
 
-- 
2.9.3.windows.2

[PATCH 3/4] MdePkg/Include: Add VA list support for VS2017/ARM64

[Pete Batard]

We need to explicitly call the built-in __va_start() for ARM64, otherwise
the variable parameters are not properly enqueued for the next function
calls.
Also do the same for ARM, as as it doesn't harm us.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Pete Batard <pete@akeo.ie>
---
 MdePkg/Include/Base.h | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/MdePkg/Include/Base.h b/MdePkg/Include/Base.h
index a94182f08886..4f7bd4449c36 100644
--- a/MdePkg/Include/Base.h
+++ b/MdePkg/Include/Base.h
@@ -668,16 +668,15 @@ struct _LIST_ENTRY {
 
 #define VA_COPY(Dest, Start)          __va_copy (Dest, Start)
 
-#elif defined(_M_ARM)
+#elif defined(_M_ARM) || defined(_M_ARM64)
 //
 // MSFT ARM variable argument list support.
-// Same as the generic macros below, except for VA_ARG that needs extra adjustment.
 //
 
 typedef char* VA_LIST;
 
-#define VA_START(Marker, Parameter)     (Marker = (VA_LIST) ((UINTN) & (Parameter) + _INT_SIZE_OF(Parameter)))
-#define VA_ARG(Marker, TYPE)            (*(TYPE *) ((Marker += _INT_SIZE_OF(TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE)))
+#define VA_START(Marker, Parameter)     __va_start (&Marker, &Parameter, _INT_SIZE_OF (Parameter), __alignof(Parameter), &Parameter)
+#define VA_ARG(Marker, TYPE)            (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE)))
 #define VA_END(Marker)                  (Marker = (VA_LIST) 0)
 #define VA_COPY(Dest, Start)            ((void)((Dest) = (Start)))
 
-- 
2.9.3.windows.2

[PATCH 4/4] BaseTools/Conf: Add VS2017/ARM64 support

[Pete Batard]

Build options for ARM64 are the same as for ARM, except for /BASE:0
which is removed from DLINK flags to avoid LNK1355 error:
invalid base address 0x0; ARM64 image cannot have base address below 4GB

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Pete Batard <pete@akeo.ie>
---
 BaseTools/Conf/build_rule.template |  2 +-
 BaseTools/Conf/tools_def.template  | 32 ++++++++++++++++++--
 2 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/BaseTools/Conf/build_rule.template b/BaseTools/Conf/build_rule.template
index 77ed282e0311..308505b3dca5 100755
--- a/BaseTools/Conf/build_rule.template
+++ b/BaseTools/Conf/build_rule.template
@@ -206,7 +206,7 @@
         # For RVCTCYGWIN ASM_FLAGS must be first to work around pathing issues
         "$(ASM)" $(ASM_FLAGS) -o ${dst} $(INC) ${d_path}(+)${s_base}.iii
 
-[Assembly-Code-File.COMMON.ARM]
+[Assembly-Code-File.COMMON.ARM,Assembly-Code-File.COMMON.AARCH64]
     # Remove --convert-hex for ARM as it breaks MSFT assemblers
     <InputFile.MSFT, InputFile.INTEL, InputFile.RVCT>
         ?.asm, ?.Asm, ?.ASM
diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index 427ad60b0e26..703019129f79 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -80,6 +80,7 @@ DEFINE VS2017_BIN_HOST    = DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\DEF(VS2017_HOST
 DEFINE VS2017_BIN_IA32    = DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\x86
 DEFINE VS2017_BIN_X64     = DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\x64
 DEFINE VS2017_BIN_ARM     = DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\arm
+DEFINE VS2017_BIN_AARCH64 = DEF(VS2017_BIN)\HostDEF(VS2017_HOST)\arm64
 
 DEFINE WINSDK_BIN       = ENV(WINSDK_PREFIX)
 DEFINE WINSDKx86_BIN    = ENV(WINSDKx86_PREFIX)
@@ -329,7 +330,7 @@ DEFINE DTC_BIN                 = ENV(DTC_PREFIX)dtc
 #                               Intel(r) ACPI Compiler (iasl.exe) from
 #                               https://acpica.org/downloads
 #   VS2017      -win32-  Requires:
-#                             Microsoft Visual Studio 2017 version 15.2 or later
+#                             Microsoft Visual Studio 2017 version 15.2 (15.4 for ARM64) or later
 #                        Optional:
 #                             Required to build EBC drivers:
 #                               Intel(r) Compiler for Efi Byte Code (Intel(r) EBC Compiler)
@@ -337,7 +338,7 @@ DEFINE DTC_BIN                 = ENV(DTC_PREFIX)dtc
 #                               Intel(r) ACPI Compiler (iasl.exe) from
 #                               https://acpica.org/downloads
 #                        Note:
-#                             Building of XIP firmware images for ARM is not currently supported (only applications).
+#                             Building of XIP firmware images for ARM/ARM64 is not currently supported (only applications).
 #                             /FILEALIGN:4096 and other changes are needed for ARM firmware builds.
 #   DDK3790     -win32-  Requires:
 #                             Microsoft Windows Server 2003 Driver Development Kit (Microsoft WINDDK) version 3790.1830
@@ -4200,6 +4201,33 @@ NOOPT_VS2017_ARM_ASM_FLAGS        = /nologo
 RELEASE_VS2017_ARM_DLINK_FLAGS    = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:ARM /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata=.data
 NOOPT_VS2017_ARM_DLINK_FLAGS      = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:ARM /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG
 
+#####################
+# AARCH64 definitions
+#####################
+*_VS2017_AARCH64_CC_PATH           = DEF(VS2017_BIN_AARCH64)\cl.exe
+*_VS2017_AARCH64_VFRPP_PATH        = DEF(VS2017_BIN_AARCH64)\cl.exe
+*_VS2017_AARCH64_SLINK_PATH        = DEF(VS2017_BIN_AARCH64)\lib.exe
+*_VS2017_AARCH64_DLINK_PATH        = DEF(VS2017_BIN_AARCH64)\link.exe
+*_VS2017_AARCH64_APP_PATH          = DEF(VS2017_BIN_AARCH64)\cl.exe
+*_VS2017_AARCH64_PP_PATH           = DEF(VS2017_BIN_AARCH64)\cl.exe
+*_VS2017_AARCH64_ASM_PATH          = DEF(VS2017_BIN_AARCH64)\armasm64.exe
+*_VS2017_AARCH64_ASLCC_PATH        = DEF(VS2017_BIN_AARCH64)\cl.exe
+*_VS2017_AARCH64_ASLPP_PATH        = DEF(VS2017_BIN_AARCH64)\cl.exe
+*_VS2017_AARCH64_ASLDLINK_PATH     = DEF(VS2017_BIN_AARCH64)\link.exe
+
+      *_VS2017_AARCH64_MAKE_FLAGS  = /nologo
+  DEBUG_VS2017_AARCH64_CC_FLAGS    = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /Gw /Oi-
+RELEASE_VS2017_AARCH64_CC_FLAGS    = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gw /Oi-
+NOOPT_VS2017_AARCH64_CC_FLAGS      = /nologo /c /WX /GS- /W4 /Gs32768 /D UNICODE /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /Gm /Od /Oi-
+
+  DEBUG_VS2017_AARCH64_ASM_FLAGS   = /nologo /g
+RELEASE_VS2017_AARCH64_ASM_FLAGS   = /nologo
+NOOPT_VS2017_AARCH64_ASM_FLAGS     = /nologo
+
+  DEBUG_VS2017_AARCH64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:ARM64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /DRIVER /DEBUG
+RELEASE_VS2017_AARCH64_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:ARM64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /DRIVER /MERGE:.rdata=.data
+NOOPT_VS2017_AARCH64_DLINK_FLAGS   = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:REF /OPT:ICF=10 /MAP /SECTION:.xdata,D /SECTION:.pdata,D /MACHINE:ARM64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /DRIVER /DEBUG
+
 ##################
 # EBC definitions
 ##################
-- 
2.9.3.windows.2

Re: [PATCH 1/4] MdePkg: Disable some Level 4 warnings for VS2017/ARM64

[Ard Biesheuvel]

On 14 February 2018 at 13:08, Pete Batard <pete@akeo.ie> wrote:
> We disable the exact same warnings as IA32 and X64.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Pete Batard <pete@akeo.ie>
> ---
>  MdePkg/Include/AArch64/ProcessorBind.h | 53 +++++++++++++++++++-
>  1 file changed, 51 insertions(+), 2 deletions(-)
>
> diff --git a/MdePkg/Include/AArch64/ProcessorBind.h b/MdePkg/Include/AArch64/ProcessorBind.h
> index bc473562f9e5..4f341ebeb03f 100644
> --- a/MdePkg/Include/AArch64/ProcessorBind.h
> +++ b/MdePkg/Include/AArch64/ProcessorBind.h
> @@ -1,7 +1,7 @@
>  /** @file
>    Processor or Compiler specific defines and types for AArch64.
>
> -  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
> +  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
>    Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
>    Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
>
> @@ -30,7 +30,56 @@
>  #pragma pack()
>  #endif
>
> -#if _MSC_EXTENSIONS
> +#if defined(_MSC_EXTENSIONS)
> +
> +//
> +// Disable some level 4 compilation warnings (same as IA32 and X64)
> +//
> +
> +//
> +// Disabling bitfield type checking warnings.
> +//
> +#pragma warning ( disable : 4214 )
> +
> +//
> +// Disabling the unreferenced formal parameter warnings.
> +//
> +#pragma warning ( disable : 4100 )
> +
> +//
> +// Disable slightly different base types warning as CHAR8 * can not be set
> +// to a constant string.
> +//
> +#pragma warning ( disable : 4057 )
> +
> +//
> +// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
> +//
> +#pragma warning ( disable : 4127 )
> +
> +//
> +// This warning is caused by functions defined but not used. For precompiled header only.
> +//
> +#pragma warning ( disable : 4505 )
> +
> +//
> +// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
> +//
> +#pragma warning ( disable : 4206 )
> +
> +//
> +// Disable 'potentially uninitialized local variable X used' warnings
> +//
> +#pragma warning ( disable : 4701 )
> +
> +//
> +// Disable 'potentially uninitialized local pointer variable X used' warnings
> +//
> +#pragma warning ( disable : 4703 )
> +
> +#endif
> +
> +#if defined(_MSC_EXTENSIONS)

Can you drop the redundant #endif + #if please? Also, I take it
_MSC_EXTENSIONS will never be #defined to 0 ?


>    //
>    // use Microsoft* C compiler dependent integer width types
>    //
> --
> 2.9.3.windows.2
>

Re: [PATCH 1/4] MdePkg: Disable some Level 4 warnings for VS2017/ARM64

[Pete Batard]

Hi Ard,

On 2018.02.14 13:13, Ard Biesheuvel wrote:
> On 14 February 2018 at 13:08, Pete Batard <pete@akeo.ie> wrote:
>> We disable the exact same warnings as IA32 and X64.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Pete Batard <pete@akeo.ie>
>> ---
>>   MdePkg/Include/AArch64/ProcessorBind.h | 53 +++++++++++++++++++-
>>   1 file changed, 51 insertions(+), 2 deletions(-)
>>
>> diff --git a/MdePkg/Include/AArch64/ProcessorBind.h b/MdePkg/Include/AArch64/ProcessorBind.h
>> index bc473562f9e5..4f341ebeb03f 100644
>> --- a/MdePkg/Include/AArch64/ProcessorBind.h
>> +++ b/MdePkg/Include/AArch64/ProcessorBind.h
>> @@ -1,7 +1,7 @@
>>   /** @file
>>     Processor or Compiler specific defines and types for AArch64.
>>
>> -  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
>> +  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
>>     Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
>>     Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
>>
>> @@ -30,7 +30,56 @@
>>   #pragma pack()
>>   #endif
>>
>> -#if _MSC_EXTENSIONS
>> +#if defined(_MSC_EXTENSIONS)
>> +
>> +//
>> +// Disable some level 4 compilation warnings (same as IA32 and X64)
>> +//
>> +
>> +//
>> +// Disabling bitfield type checking warnings.
>> +//
>> +#pragma warning ( disable : 4214 )
>> +
>> +//
>> +// Disabling the unreferenced formal parameter warnings.
>> +//
>> +#pragma warning ( disable : 4100 )
>> +
>> +//
>> +// Disable slightly different base types warning as CHAR8 * can not be set
>> +// to a constant string.
>> +//
>> +#pragma warning ( disable : 4057 )
>> +
>> +//
>> +// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
>> +//
>> +#pragma warning ( disable : 4127 )
>> +
>> +//
>> +// This warning is caused by functions defined but not used. For precompiled header only.
>> +//
>> +#pragma warning ( disable : 4505 )
>> +
>> +//
>> +// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
>> +//
>> +#pragma warning ( disable : 4206 )
>> +
>> +//
>> +// Disable 'potentially uninitialized local variable X used' warnings
>> +//
>> +#pragma warning ( disable : 4701 )
>> +
>> +//
>> +// Disable 'potentially uninitialized local pointer variable X used' warnings
>> +//
>> +#pragma warning ( disable : 4703 )
>> +
>> +#endif
>> +
>> +#if defined(_MSC_EXTENSIONS)
> 
> Can you drop the redundant #endif + #if please?

Will do. I'll probably wait another week before sending a v2, since I 
expect some reviewers to be off for Chinese New Year.

> Also, I take it
> _MSC_EXTENSIONS will never be #defined to 0 ?

According to Microsoft [1]:

Defined as 1 if the /Ze (Enable Language Extensions) compiler option is 
set, which is the default. Otherwise, undefined.

> 
> 
>>     //
>>     // use Microsoft* C compiler dependent integer width types
>>     //
>> --
>> 2.9.3.windows.2
>>

Regards,

/Pete

[1] https://msdn.microsoft.com/en-us/library/b0084kay.aspx

[PATCH 2/4] MdePkg/Library/BaseLib: Enable VS2017/ARM64 builds

[Pete Batard]

Required GCC assembly files are converted for the MSFT assembler

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Pete Batard <pete@akeo.ie>
---
 MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm      |  39 ++++++++
 MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm  |  37 +++++++
 MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm   |  37 +++++++
 MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm |  49 ++++++++++
 MdePkg/Library/BaseLib/AArch64/MemoryFence.asm        |  38 ++++++++
 MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm    | 101 ++++++++++++++++++++
 MdePkg/Library/BaseLib/AArch64/SwitchStack.asm        |  69 +++++++++++++
 MdePkg/Library/BaseLib/BaseLib.inf                    |   8 ++
 8 files changed, 378 insertions(+)

diff --git a/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm b/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm
new file mode 100644
index 000000000000..17e993f5b77e
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm
@@ -0,0 +1,39 @@
+;------------------------------------------------------------------------------
+;
+; CpuBreakpoint() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+
+  EXPORT CpuBreakpoint
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+;  Generates a breakpoint on the CPU.
+;
+;  Generates a breakpoint on the CPU. The breakpoint must be implemented such
+;  that code can resume normal execution after the breakpoint.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuBreakpoint (
+;  VOID
+;  );
+;
+CpuBreakpoint
+    svc   0xdbdb    // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm b/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm
new file mode 100644
index 000000000000..498493454c7d
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------
+;
+; DisableInterrupts() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+  EXPORT DisableInterrupts
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_WR_IRQ_BIT     EQU     (1 << 1)
+
+;/**
+;  Disables CPU interrupts.
+;
+;**/
+;VOID
+;EFIAPI
+;DisableInterrupts (
+;  VOID
+;  );
+;
+DisableInterrupts
+    msr  daifset, #DAIF_WR_IRQ_BIT
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm b/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm
new file mode 100644
index 000000000000..ec3d6e45ff8a
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------
+;
+; EnableInterrupts() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+  EXPORT EnableInterrupts
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_WR_IRQ_BIT     EQU     (1 << 1)
+
+;/**
+;  Enables CPU interrupts.
+;
+;**/
+;VOID
+;EFIAPI
+;EnableInterrupts (
+;  VOID
+;  );
+;
+EnableInterrupts
+    msr  daifclr, #DAIF_WR_IRQ_BIT
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm b/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm
new file mode 100644
index 000000000000..d64b0d513ce3
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm
@@ -0,0 +1,49 @@
+;------------------------------------------------------------------------------
+;
+; GetInterruptState() function for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+  EXPORT GetInterruptState
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_RD_IRQ_BIT     EQU     (1 << 7)
+
+;/**
+;  Retrieves the current CPU interrupt state.
+;
+;  Returns TRUE is interrupts are currently enabled. Otherwise
+;  returns FALSE.
+;
+;  @retval TRUE  CPU interrupts are enabled.
+;  @retval FALSE CPU interrupts are disabled.
+;
+;**/
+;
+;BOOLEAN
+;EFIAPI
+;GetInterruptState (
+;  VOID
+; );
+;
+GetInterruptState
+    mrs    x0, daif
+    mov    w0, wzr
+    tst    x0, #DAIF_RD_IRQ_BIT   // Check IRQ mask; set Z=1 if clear/unmasked
+    bne    exit                   // if Z=1 (eq) return 1, else 0
+    mov    w0, #1
+exit
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm b/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm
new file mode 100644
index 000000000000..84dede698ee0
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm
@@ -0,0 +1,38 @@
+;------------------------------------------------------------------------------
+;
+; MemoryFence() for AArch64
+;
+; Copyright (c) 2013, ARM Ltd. All rights reserved.
+;
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+  EXPORT MemoryFence
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+;  Used to serialize load and store operations.
+;
+;  All loads and stores that proceed calls to this function are guaranteed to be
+;  globally visible when this function returns.
+;
+;**/
+;VOID
+;EFIAPI
+;MemoryFence (
+;  VOID
+;  );
+;
+MemoryFence
+    // System wide Data Memory Barrier.
+    dmb sy
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm b/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm
new file mode 100644
index 000000000000..e0a9715ff2d1
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm
@@ -0,0 +1,101 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2009-2013, ARM Ltd.  All rights reserved.
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+;------------------------------------------------------------------------------
+
+  EXPORT SetJump
+  EXPORT InternalLongJump
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+#define GPR_LAYOUT                          \
+        REG_PAIR (x19, x20,  #0);           \
+        REG_PAIR (x21, x22, #16);           \
+        REG_PAIR (x23, x24, #32);           \
+        REG_PAIR (x25, x26, #48);           \
+        REG_PAIR (x27, x28, #64);           \
+        REG_PAIR (x29, x30, #80);/*FP, LR*/ \
+        REG_ONE  (x16,      #96) /*IP0*/
+
+#define FPR_LAYOUT                       \
+        REG_PAIR ( d8,  d9, #112);       \
+        REG_PAIR (d10, d11, #128);       \
+        REG_PAIR (d12, d13, #144);       \
+        REG_PAIR (d14, d15, #160);
+
+;/**
+;  Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#
+;
+;  Saves the current CPU context in the buffer specified by JumpBuffer and returns 0.  The initial
+;  call to SetJump() must always return 0.  Subsequent calls to LongJump() cause a non-zero
+;  value to be returned by SetJump().
+;
+;  If JumpBuffer is NULL, then ASSERT().
+;  For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+;
+;  @param  JumpBuffer    A pointer to CPU context buffer.
+;
+;**/
+;
+;UINTN
+;EFIAPI
+;SetJump (
+;  IN      BASE_LIBRARY_JUMP_BUFFER  *JumpBuffer  // X0
+;  );
+;
+SetJump
+        mov     x16, sp // use IP0 so save SP
+#define REG_PAIR(REG1, REG2, OFFS)      stp REG1, REG2, [x0, OFFS]
+#define REG_ONE(REG1, OFFS)             str REG1, [x0, OFFS]
+        GPR_LAYOUT
+        FPR_LAYOUT
+#undef REG_PAIR
+#undef REG_ONE
+        mov     w0, #0
+        ret
+
+;/**
+;  Restores the CPU context that was saved with SetJump().#
+;
+;  Restores the CPU context from the buffer specified by JumpBuffer.
+;  This function never returns to the caller.
+;  Instead is resumes execution based on the state of JumpBuffer.
+;
+;  @param  JumpBuffer    A pointer to CPU context buffer.
+;  @param  Value         The value to return when the SetJump() context is restored.
+;
+;**/
+;VOID
+;EFIAPI
+;InternalLongJump (
+;  IN      BASE_LIBRARY_JUMP_BUFFER  *JumpBuffer,  // X0
+;  IN      UINTN                     Value         // X1
+;  );
+;
+InternalLongJump
+#define REG_PAIR(REG1, REG2, OFFS)      ldp REG1, REG2, [x0, OFFS]
+#define REG_ONE(REG1, OFFS)             ldr REG1, [x0, OFFS]
+        GPR_LAYOUT
+        FPR_LAYOUT
+#undef REG_PAIR
+#undef REG_ONE
+        mov     sp, x16
+        cmp     w1, #0
+        mov     w0, #1
+        beq     exit
+        mov     w0, w1
+exit
+        // use br not ret, as ret is guaranteed to mispredict
+        br      x30
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+
+  END
+
diff --git a/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm b/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm
new file mode 100644
index 000000000000..c1b2de07e205
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm
@@ -0,0 +1,69 @@
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+// Portions copyright (c) 2011 - 2013, ARM Limited. All rights reserved.<BR>
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+  EXPORT InternalSwitchStackAsm
+  EXPORT CpuPause
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+/**
+//
+//  This allows the caller to switch the stack and goes to the new entry point
+//
+// @param      EntryPoint   The pointer to the location to enter
+// @param      Context      Parameter to pass in
+// @param      Context2     Parameter2 to pass in
+// @param      NewStack     New Location of the stack
+//
+// @return     Nothing. Goes to the Entry Point passing in the new parameters
+//
+VOID
+EFIAPI
+InternalSwitchStackAsm (
+  SWITCH_STACK_ENTRY_POINT EntryPoint,
+  VOID  *Context,
+  VOID  *Context2,
+  VOID  *NewStack
+  );
+**/
+InternalSwitchStackAsm
+    mov   x29, #0
+    mov   x30, x0
+    mov   sp, x3
+    mov   x0, x1
+    mov   x1, x2
+    ret
+
+/**
+//
+//  Requests CPU to pause for a short period of time.
+//
+//  Requests CPU to pause for a short period of time. Typically used in MP
+//  systems to prevent memory starvation while waiting for a spin lock.
+//
+VOID
+EFIAPI
+CpuPause (
+  VOID
+  )
+**/
+CpuPause
+    nop
+    nop
+    nop
+    nop
+    nop
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 3c07e6bad977..80d00ebed75b 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -867,6 +867,14 @@ [Sources.AARCH64]
   AArch64/SetJumpLongJump.S         | GCC
   AArch64/CpuBreakpoint.S           | GCC
 
+  AArch64/MemoryFence.asm           | MSFT
+  AArch64/SwitchStack.asm           | MSFT
+  AArch64/EnableInterrupts.asm      | MSFT
+  AArch64/DisableInterrupts.asm     | MSFT
+  AArch64/GetInterruptsState.asm    | MSFT
+  AArch64/SetJumpLongJump.asm       | MSFT
+  AArch64/CpuBreakpoint.asm         | MSFT
+
 [Packages]
   MdePkg/MdePkg.dec
 
-- 
2.9.3.windows.2