From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=pete@akeo.ie; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4AF032216116A for ; Wed, 14 Feb 2018 05:03:21 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id 141so21801222wme.3 for ; Wed, 14 Feb 2018 05:09:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PA2g2fuVjVN5IaLa0SZkNagez51bRxvy8UI+Lv1iZPA=; b=iTkW9ZWiRvY3v9M9pzlexeBPP1ez7INRuPrCl02/xi8uAngoAcfjYi7OhA0ZQqqsLQ /0BN05CgGnAwxEwh6SohyyXWdviJ4TzRsxJ8dbCEWKSYcpQt9NVUCxzPbA+dmNwjHbhC RSl/p1Nrt5YKwVFLG+rlfhp/OJUQmOK9Zns0fOh9S2kYpohYjOEgAoRFAxRKg7FrPDPl Xmh5ScHI3CfPUpV4zHOP3jXb6iArUpbd1v8ODKYaPKIJksNpTghCmzMq3nJNYy+2Xuzx feuPeXN21mjH1PW4nO+WUXfNNXLp9Sr9iZ7q3M6POl4D3AESRHWhaa1shcEPF95eQIVR 8lRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PA2g2fuVjVN5IaLa0SZkNagez51bRxvy8UI+Lv1iZPA=; b=bpjcxmD3PHUxsmkUyadsYuiDN9IWQifayRAg6p2Ewbi8IIQtk0N8l5YOoS4UmqLw4Z r44SPyGYNhtHNXItnLSBmxxL3OdtX3zbJ9fuxmQxk+dMQPZn1zYGr2Yv3fxwWGJvm07K KxgQ/6HnItwKKOiqKq2rUTIBo6/7q1MU6SLsQyJB4nidxsacXhUvd6NPMDQ8ophu3KfB PtaVFB813TZfcIFC3ONg/JzdrUUuo6kvJUSTa5OYRmck78Kf3yCD/tpVEShiYdVjd2aI 3Etmv8GqzZjfLZLA1BN1/o5pFlmiTBfU2gWeKL4tRFqZGbbPktZ2iBtz65pkyicnoymS xb5Q== X-Gm-Message-State: APf1xPBOaaRtKMkfdeeRvJU+KghI1xDl8TPQyNdIQ5Nwsv4X6V4JGcy0 VZWl09TPbxZkimOiPhKSuIYV64MsnEg= X-Google-Smtp-Source: AH8x225GoH3ChHkeVnP4VeXaVjmA6CXUiy2B+h/6qLDCd2QPyjV7n3M7DyZiRNjB0mRY9KyO7guGpQ== X-Received: by 10.80.164.212 with SMTP id x20mr6931952edb.284.1518613751240; Wed, 14 Feb 2018 05:09:11 -0800 (PST) Received: from localhost.localdomain ([84.203.84.137]) by smtp.gmail.com with ESMTPSA id b13sm1262955edk.59.2018.02.14.05.09.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Feb 2018 05:09:10 -0800 (PST) From: Pete Batard To: edk2-devel@lists.01.org Cc: liming.gao@intel.com, ard.biesheuvel@linaro.org Date: Wed, 14 Feb 2018 13:08:55 +0000 Message-Id: <20180214130857.5020-3-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20180214130857.5020-1-pete@akeo.ie> References: <20180214130857.5020-1-pete@akeo.ie> Subject: [PATCH 2/4] MdePkg/Library/BaseLib: Enable VS2017/ARM64 builds X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Feb 2018 13:03:22 -0000 Required GCC assembly files are converted for the MSFT assembler Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm | 39 ++++++++ MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm | 37 +++++++ MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm | 37 +++++++ MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm | 49 ++++++++++ MdePkg/Library/BaseLib/AArch64/MemoryFence.asm | 38 ++++++++ MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm | 101 ++++++++++++++++++++ MdePkg/Library/BaseLib/AArch64/SwitchStack.asm | 69 +++++++++++++ MdePkg/Library/BaseLib/BaseLib.inf | 8 ++ 8 files changed, 378 insertions(+) diff --git a/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm b/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm new file mode 100644 index 000000000000..17e993f5b77e --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------ +; +; CpuBreakpoint() for AArch64 +; +; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + + + EXPORT CpuBreakpoint + AREA BaseLib_LowLevel, CODE, READONLY + +;/** +; Generates a breakpoint on the CPU. +; +; Generates a breakpoint on the CPU. The breakpoint must be implemented such +; that code can resume normal execution after the breakpoint. +; +;**/ +;VOID +;EFIAPI +;CpuBreakpoint ( +; VOID +; ); +; +CpuBreakpoint + svc 0xdbdb // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here. + ret + + END diff --git a/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm b/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm new file mode 100644 index 000000000000..498493454c7d --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------ +; +; DisableInterrupts() for AArch64 +; +; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + + EXPORT DisableInterrupts + AREA BaseLib_LowLevel, CODE, READONLY + +DAIF_WR_IRQ_BIT EQU (1 << 1) + +;/** +; Disables CPU interrupts. +; +;**/ +;VOID +;EFIAPI +;DisableInterrupts ( +; VOID +; ); +; +DisableInterrupts + msr daifset, #DAIF_WR_IRQ_BIT + ret + + END diff --git a/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm b/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm new file mode 100644 index 000000000000..ec3d6e45ff8a --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm @@ -0,0 +1,37 @@ +;------------------------------------------------------------------------------ +; +; EnableInterrupts() for AArch64 +; +; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + + EXPORT EnableInterrupts + AREA BaseLib_LowLevel, CODE, READONLY + +DAIF_WR_IRQ_BIT EQU (1 << 1) + +;/** +; Enables CPU interrupts. +; +;**/ +;VOID +;EFIAPI +;EnableInterrupts ( +; VOID +; ); +; +EnableInterrupts + msr daifclr, #DAIF_WR_IRQ_BIT + ret + + END diff --git a/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm b/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm new file mode 100644 index 000000000000..d64b0d513ce3 --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm @@ -0,0 +1,49 @@ +;------------------------------------------------------------------------------ +; +; GetInterruptState() function for AArch64 +; +; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + + EXPORT GetInterruptState + AREA BaseLib_LowLevel, CODE, READONLY + +DAIF_RD_IRQ_BIT EQU (1 << 7) + +;/** +; Retrieves the current CPU interrupt state. +; +; Returns TRUE is interrupts are currently enabled. Otherwise +; returns FALSE. +; +; @retval TRUE CPU interrupts are enabled. +; @retval FALSE CPU interrupts are disabled. +; +;**/ +; +;BOOLEAN +;EFIAPI +;GetInterruptState ( +; VOID +; ); +; +GetInterruptState + mrs x0, daif + mov w0, wzr + tst x0, #DAIF_RD_IRQ_BIT // Check IRQ mask; set Z=1 if clear/unmasked + bne exit // if Z=1 (eq) return 1, else 0 + mov w0, #1 +exit + ret + + END diff --git a/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm b/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm new file mode 100644 index 000000000000..84dede698ee0 --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm @@ -0,0 +1,38 @@ +;------------------------------------------------------------------------------ +; +; MemoryFence() for AArch64 +; +; Copyright (c) 2013, ARM Ltd. All rights reserved. +; +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + + EXPORT MemoryFence + AREA BaseLib_LowLevel, CODE, READONLY + +;/** +; Used to serialize load and store operations. +; +; All loads and stores that proceed calls to this function are guaranteed to be +; globally visible when this function returns. +; +;**/ +;VOID +;EFIAPI +;MemoryFence ( +; VOID +; ); +; +MemoryFence + // System wide Data Memory Barrier. + dmb sy + ret + + END diff --git a/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm b/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm new file mode 100644 index 000000000000..e0a9715ff2d1 --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm @@ -0,0 +1,101 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2009-2013, ARM Ltd. All rights reserved. +; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + + EXPORT SetJump + EXPORT InternalLongJump + AREA BaseLib_LowLevel, CODE, READONLY + +#define GPR_LAYOUT \ + REG_PAIR (x19, x20, #0); \ + REG_PAIR (x21, x22, #16); \ + REG_PAIR (x23, x24, #32); \ + REG_PAIR (x25, x26, #48); \ + REG_PAIR (x27, x28, #64); \ + REG_PAIR (x29, x30, #80);/*FP, LR*/ \ + REG_ONE (x16, #96) /*IP0*/ + +#define FPR_LAYOUT \ + REG_PAIR ( d8, d9, #112); \ + REG_PAIR (d10, d11, #128); \ + REG_PAIR (d12, d13, #144); \ + REG_PAIR (d14, d15, #160); + +;/** +; Saves the current CPU context that can be restored with a call to LongJump() and returns 0.# +; +; Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial +; call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero +; value to be returned by SetJump(). +; +; If JumpBuffer is NULL, then ASSERT(). +; For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT(). +; +; @param JumpBuffer A pointer to CPU context buffer. +; +;**/ +; +;UINTN +;EFIAPI +;SetJump ( +; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // X0 +; ); +; +SetJump + mov x16, sp // use IP0 so save SP +#define REG_PAIR(REG1, REG2, OFFS) stp REG1, REG2, [x0, OFFS] +#define REG_ONE(REG1, OFFS) str REG1, [x0, OFFS] + GPR_LAYOUT + FPR_LAYOUT +#undef REG_PAIR +#undef REG_ONE + mov w0, #0 + ret + +;/** +; Restores the CPU context that was saved with SetJump().# +; +; Restores the CPU context from the buffer specified by JumpBuffer. +; This function never returns to the caller. +; Instead is resumes execution based on the state of JumpBuffer. +; +; @param JumpBuffer A pointer to CPU context buffer. +; @param Value The value to return when the SetJump() context is restored. +; +;**/ +;VOID +;EFIAPI +;InternalLongJump ( +; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // X0 +; IN UINTN Value // X1 +; ); +; +InternalLongJump +#define REG_PAIR(REG1, REG2, OFFS) ldp REG1, REG2, [x0, OFFS] +#define REG_ONE(REG1, OFFS) ldr REG1, [x0, OFFS] + GPR_LAYOUT + FPR_LAYOUT +#undef REG_PAIR +#undef REG_ONE + mov sp, x16 + cmp w1, #0 + mov w0, #1 + beq exit + mov w0, w1 +exit + // use br not ret, as ret is guaranteed to mispredict + br x30 + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED + + END + diff --git a/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm b/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm new file mode 100644 index 000000000000..c1b2de07e205 --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm @@ -0,0 +1,69 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+// Portions copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
+// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php. +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +//------------------------------------------------------------------------------ + + EXPORT InternalSwitchStackAsm + EXPORT CpuPause + AREA BaseLib_LowLevel, CODE, READONLY + +/** +// +// This allows the caller to switch the stack and goes to the new entry point +// +// @param EntryPoint The pointer to the location to enter +// @param Context Parameter to pass in +// @param Context2 Parameter2 to pass in +// @param NewStack New Location of the stack +// +// @return Nothing. Goes to the Entry Point passing in the new parameters +// +VOID +EFIAPI +InternalSwitchStackAsm ( + SWITCH_STACK_ENTRY_POINT EntryPoint, + VOID *Context, + VOID *Context2, + VOID *NewStack + ); +**/ +InternalSwitchStackAsm + mov x29, #0 + mov x30, x0 + mov sp, x3 + mov x0, x1 + mov x1, x2 + ret + +/** +// +// Requests CPU to pause for a short period of time. +// +// Requests CPU to pause for a short period of time. Typically used in MP +// systems to prevent memory starvation while waiting for a spin lock. +// +VOID +EFIAPI +CpuPause ( + VOID + ) +**/ +CpuPause + nop + nop + nop + nop + nop + ret + + END diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 3c07e6bad977..80d00ebed75b 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -867,6 +867,14 @@ [Sources.AARCH64] AArch64/SetJumpLongJump.S | GCC AArch64/CpuBreakpoint.S | GCC + AArch64/MemoryFence.asm | MSFT + AArch64/SwitchStack.asm | MSFT + AArch64/EnableInterrupts.asm | MSFT + AArch64/DisableInterrupts.asm | MSFT + AArch64/GetInterruptsState.asm | MSFT + AArch64/SetJumpLongJump.asm | MSFT + AArch64/CpuBreakpoint.asm | MSFT + [Packages] MdePkg/MdePkg.dec -- 2.9.3.windows.2