From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8193121CF1CF3 for ; Sun, 18 Feb 2018 03:33:45 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id v71so10297442wmv.2 for ; Sun, 18 Feb 2018 03:39:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=WaQIrW3qKFQDumFTuoPrkGG0q+EzWY4Rxy68wAiofQQ=; b=hdtmXpVPf2VuE2MOVUwsyyd+PhcCgCvPm03ITwpuMcW+21nFWMwsmdqdaSu7JFS0Lz 1ALC6QSdXLTilQQKWiU67yyKz9+X0+BckZWd+YO+ha4Vp73q7/IfKjfZ9CkoDpb+pMUG +JQWSJFOTvZ+VNKSsdDekCj4vLEmFsNLRKhPc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=WaQIrW3qKFQDumFTuoPrkGG0q+EzWY4Rxy68wAiofQQ=; b=Tz7eUyX4tmEuiyAd+QKa69jDi0S++Ow9hR3uIZh2eukwd3lClhAncEfYXDx8bz4kpx z/m9JbEKaFk1DXvvqyJopO59KHnkWZ/eUEiX9HrZwunnKFfdFdM26fxo5hJJew2eKOZg Cf/y0RuvFxmv7bxQU2S/SOcSOhNpEYcB3U9AhK/u7MaXI37z4Jf3mox6ESJZr76+Iylo C1hqz1gg6LO0+SwmRZUYE8zqwOzPbTqJGEISyuoU9GQEb+3WUgV3zWoejp/VtPzhVNEh 8rgj25MOpfk94Lh+W9Z98KBxpXyW1aTia6ZzcVgvY8aTAaIQhI3LZ5ilTcU+lMO56+YX TGOw== X-Gm-Message-State: APf1xPAnuGz87uFBLQ0RO9X+u5M+fECCKGK9Zs69yUZIaTM+Axjio6Rk HCivb04b/P09qaQsqt/OpzmNzw== X-Google-Smtp-Source: AH8x224EVi+uOyEn3s0egwRHPj4n+Lhi21viYcIR5qgiarchwhSznilTMXOtVGAPRDuZ2UOW9zSB0g== X-Received: by 10.28.213.77 with SMTP id m74mr9461258wmg.137.1518953980463; Sun, 18 Feb 2018 03:39:40 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id b54sm29349391wrg.27.2018.02.18.03.39.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 18 Feb 2018 03:39:38 -0800 (PST) Date: Sun, 18 Feb 2018 11:39:36 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: "edk2-devel@lists.01.org" , Joakim Bech Message-ID: <20180218113936.6f4fdemn7yurjac3@bivouac.eciton.net> References: <20180215172054.27452-1-ard.biesheuvel@linaro.org> <20180215172054.27452-2-ard.biesheuvel@linaro.org> <20180216170020.inkadbvnr25zczhh@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 1/5] Silicon/SynQuaver/DeviceTree: add node for SPI controller X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 18 Feb 2018 11:33:47 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Feb 16, 2018 at 06:34:30PM +0000, Ard Biesheuvel wrote: > On 16 February 2018 at 17:00, Leif Lindholm wrote: > > On Thu, Feb 15, 2018 at 05:20:50PM +0000, Ard Biesheuvel wrote: > >> Add a node for the SPI controller to the device tree so the OS may > >> attach to it. This is the SPI controller that is attached to the > >> 96boards mezzanine connector on Developer Box. > > > > Just a generic question (which also applies to the subsequent patch): > > Are there any implications here with regards to this bus running in > > master or slave mode? > > > > Not really, since that depends entirely on the OS. We just assert the > presence of a certain IP block at a certain memory offset, and whether > the hardware supports slave mode is left unspecified. Whether the OS > supports slave mode (for this particular IP block) is not a property > of the hardware. I was thinking more along the lines of whether the hardware supports slave mode or not (perhaps as a synthesis option). But, fair enough. If you change SynQuaver -> SynQuacer in 1-2 subject lines, for the series: Reviewed-by: Leif Lindholm > >> Contributed-under: TianoCore Contribution Agreement 1.1 > >> Signed-off-by: Ard Biesheuvel > >> --- > >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 18 ++++++++++++++++++ > >> 1 file changed, 18 insertions(+) > >> > >> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > >> index 9085adb326ab..ba445a50f16f 100644 > >> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > >> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > >> @@ -538,4 +538,22 @@ > >> clock-names = "core", "iface"; > >> dma-coherent; > >> }; > >> + > >> + clk_alw_1_8: spi_ihclk { > >> + compatible = "fixed-clock"; > >> + #clock-cells = <0>; > >> + clock-frequency = <125000000>; > >> + clock-output-names = "iHCLK"; > >> + }; > >> + > >> + spi: spi@54810000 { > >> + compatible = "socionext,synquacer-spi"; > >> + reg = <0x0 0x54810000 0x0 0x1000>; > >> + clocks = <&clk_alw_1_8>; > >> + clock-names = "iHCLK"; > >> + socionext,use-rtm; > >> + socionext,set-aces; > >> + #address-cells = <1>; > >> + #size-cells = <0>; > >> + }; > >> }; > >> -- > >> 2.11.0 > >>