From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::230; helo=mail-wr0-x230.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x230.google.com (mail-wr0-x230.google.com [IPv6:2a00:1450:400c:c0c::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B760621FD73EE for ; Mon, 19 Feb 2018 03:42:39 -0800 (PST) Received: by mail-wr0-x230.google.com with SMTP id 34so9284688wre.13 for ; Mon, 19 Feb 2018 03:48:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=uurk1zPPHRYYZeiP/6qMfgzEWq79gekLt4Od5CJN0AI=; b=Fae/KTve5MMl0GV49g4mVYmh7xeRxxxwpE2WwdACpsA+ZK8YgMO5F86F0B9gWfiRpk 6mtUKdkHwxMjQ1V4yAHdA5W3YvlUfEFSvvCm8wW5h2qcknPYpXHml1hAjaYAAOICiHJW pSYUvhoxU3A65T7lDCef/S0jl0U90Z5oiCv40= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=uurk1zPPHRYYZeiP/6qMfgzEWq79gekLt4Od5CJN0AI=; b=eAAnUIhYYXXJdh5VUNL/p4domdQgfmw6L05c4xJTaOJMcnq+9Ijeknlfqok4/ziTcy XhxKr9igVmlcb5OZIXcexSRnAyJXwhb6sFcS2FcYRAxcYI3f1tnKJUyD+b/0n6Vp2Fa9 epPERQ0ls26ytk6qmDHPYqWmftVoLhvS4ecB4+VJ/fNYXTyy4n4zQ0Z0ejJcv9hP45YH w7CP4wvzdClxOlJltIk3GPEAZZGAhiIjoPXISuDP1m1c43pSQEc0rrpIO8MIfT3WhVm+ PlDEkN3psM0LdgwTOs4sLnDtktCK8N3kBhDV9UaSHlDUU5/qzdLEzB+VoREV+8OmW2W3 ickw== X-Gm-Message-State: APf1xPBlcf7emomRdGHxOiy3/Vd5yhEqu/anpa+gFnTmlhEOjQaYAP0R LWcbs73b9OefU+9I3P25zOzzukW15Wc= X-Google-Smtp-Source: AH8x2253CxkLpbac4isufomegDMLBi20yUgkJnucyX89sV1hu/OLUdje0rJGar0jIL1owuUffEDeHA== X-Received: by 10.223.182.65 with SMTP id i1mr12097892wre.24.1519040915058; Mon, 19 Feb 2018 03:48:35 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id v4sm2373051wme.43.2018.02.19.03.48.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Feb 2018 03:48:33 -0800 (PST) Date: Mon, 19 Feb 2018 11:48:32 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: "edk2-devel@lists.01.org" , Joakim Bech Message-ID: <20180219114831.4cpxcuseb25qotcn@bivouac.eciton.net> References: <20180215172054.27452-1-ard.biesheuvel@linaro.org> <20180215172054.27452-2-ard.biesheuvel@linaro.org> <20180216170020.inkadbvnr25zczhh@bivouac.eciton.net> <20180218113936.6f4fdemn7yurjac3@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 1/5] Silicon/SynQuaver/DeviceTree: add node for SPI controller X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Feb 2018 11:42:40 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Feb 19, 2018 at 08:20:28AM +0000, Ard Biesheuvel wrote: > >> Not really, since that depends entirely on the OS. We just assert the > >> presence of a certain IP block at a certain memory offset, and whether > >> the hardware supports slave mode is left unspecified. Whether the OS > >> supports slave mode (for this particular IP block) is not a property > >> of the hardware. > > > > I was thinking more along the lines of whether the hardware supports > > slave mode or not (perhaps as a synthesis option). > > > > But, fair enough. > > > > If you change SynQuaver -> SynQuacer in 1-2 subject lines, for the series: > > Reviewed-by: Leif Lindholm > > > > Excellent, thanks. However, I am going to respin this and make it much > more generic: > > - create a separate, generic MezzanineDxe driver (with its own HII menu option) > - redefine all GPIO, I2C and SPI references in terms of the 96boards > spec, e.g., GPIO-A, GPIO-B, GPIO-C > > That way, you can basically specify how the LS connector has been > integrated (which I2C/SPI/GPIO), and support anything that the generic > driver supports. Excellent - that sounds exactly like what I had been hoping for initially. > This is only up to a point, of course. Using the Secure96 RNG in UEFI > requires a UEFI driver, and some I2C plumbing, but I am trying to make > that generic as well (which is feasible if the I2C bus on the LS > connector does not contain anything else that UEFI cares about) I would hope that's generally the case, and otherwise we'd need to create some protocol that lets you mux? I.e., even if we do somethign crazy like support stacking mezzanine boards, an abstracted mezzanine driver should be able to deal with it - the only issue would come if there were on-board devices on the same bus? / Leif