From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::22c; helo=mail-wr0-x22c.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x22c.google.com (mail-wr0-x22c.google.com [IPv6:2a00:1450:400c:c0c::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F283520955F07 for ; Tue, 27 Feb 2018 01:14:24 -0800 (PST) Received: by mail-wr0-x22c.google.com with SMTP id w77so24019301wrc.6 for ; Tue, 27 Feb 2018 01:20:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=K6NrU9Xqq7WgSqpm5Sh10uTbRio/RioFTYTiCfRGfUk=; b=Yqt0NIpciLZ5VPf6kcvB7awstLxzrzttqskZ0N+HeHTM6mATIjQdmzXJGNA0b1RA1l eF8lnquqr/ZwHKwN7TzVTDKxvFBHbOgRwywKTQaj9EJRQQsZfIot50IZD97I4IYs0pjK uGslT2OAzHWlkm4ksbsWj+4XVqO4xpAKcYYrE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=K6NrU9Xqq7WgSqpm5Sh10uTbRio/RioFTYTiCfRGfUk=; b=kUC+6ifQ4PMZIjtAesgYxcP82h1KgGL6IPEQGESVS6xFRq/N+KSEHDtQQxONCDj0R0 YIy0eFFRPF2Ttk/fnMvhMuzU49qfb7FYBHTB5lNpjDJ0th2rsTAAANhyMGN0wmnvhj66 5z8u/dOnnV08PmBlRkmFF1uqXK5PEx3VdNmsUAPzq4i5qtotMduOVh41hAW9nfNGPz5F sl15gPb/dfE/yHf+43kGzMaSnyVRdPuQfCU+GF0B8R+R2lf7WO4a021SvuvxrexdBvYV ldzgevX058inPwJZgWb/XIY40t2xEl+Kv0Y1ZqRJ7axJWYdihuJQrAVj0hcl4Yl1s6Wr Lk5Q== X-Gm-Message-State: APf1xPCAncK9yqe3snDK+YxpyQsbRIkM/tsg+O0/YuHdYOeIOu2PRH7u oconOmatw2O+fNXEBk6zBZQK8uCLNhY= X-Google-Smtp-Source: AH8x224xLoyp5YvlP/2asSYhm+h84bJf3eJzY7ZeEpP/Qk6ZSREP2OOKpBqFrjVgy8wffj3EK8CnWw== X-Received: by 10.223.147.36 with SMTP id 33mr10993037wro.133.1519723228880; Tue, 27 Feb 2018 01:20:28 -0800 (PST) Received: from localhost.localdomain ([160.167.215.215]) by smtp.gmail.com with ESMTPSA id x190sm12549865wme.27.2018.02.27.01.20.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Feb 2018 01:20:27 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, graeme.gregory@linaro.org, masahisa.kojima@linaro.org, Ard Biesheuvel Date: Tue, 27 Feb 2018 09:20:12 +0000 Message-Id: <20180227092017.23617-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [PATCH edk2-platforms 0/5] SynQuacer ACPI support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Feb 2018 09:14:25 -0000 This implements ACPI support for the SynQuacer platforms. Note that supporting ACPI on this SoC is non-trivial, due to the quirky DesignWare RCs and the pre-ITS that sits between the PCIe RCs and the GICv3. However, the most important issue has been addressed by modifying the static SMMU mapping that sits between the CPUs and the PCIe config space, working around the ghosting issue that occurs on these RCs, due the complete lack of type 0 config TLP filtering by the [non-existent] root port. (This was tested using the 20180226-LB1.1-ACPI-ramfw.bin SCP firmware image, which is not [yet] installed by default on DeveloperBox hardware) That leaves the MSI issue, which is worked around by limiting MSI support to a single RC. In the presented configuration, this is RC #1, which connects to the x16 slot [and nothing else] on the DeveloperBox PCB. The onboard PCIe devices (XHCI + SATA) work without problem using wired interrupts only, and so RC #0 has MSI support disabled. This means cards that require MSI support should be inserted into the x16 slot, which is likely to be the preferred slot in such cases anwyay (e.g., when using NVME or high end networking plugin cards) Patch #1 fixes a minor issue in the slot-to-BDF mapping. Patch #2 modifies the static PCIe window configuration so it can be described using ACPI as well as DT. Patch #3 introduces the static ACPI tables that describe the fixed platform devices and peripherals to the OS. Patch #4 adds a menu option to the platform driver to make ACPI vs DT user selectable. Patch #5 adds support for describing the eMMC controller using a SSDT table which is only installed if eMMC support is enabled. Note that driver support for the eMMC and network controller only landed in v4.15, but when using a SATA driver and a plugin network card that does have driver support, these patches should allow the SynQuacer based platforms to boot stock Debian Stretch/Fedora/Centos etc installers. Ard Biesheuvel (5): Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support Silicon/SynQuacer: add ACPI drivers and tables Silicon/SynQuacer/PlatformDxe: add option to enable ACPI mode Silicon/SynQuacer/PlatformDxe: add ACPI description of eMMC Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 2 + Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 14 ++ Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 14 ++ Silicon/Socionext/SynQuacer/Acpi.dsc.inc | 48 ++++ Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl | 262 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h | 73 ++++++ Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf | 64 +++++ Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 187 ++++++++++++++ Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc | 91 +++++++ Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc | 93 +++++++ Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 101 ++++++++ Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc | 182 ++++++++++++++ Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc | 63 +++++ Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc | 128 ++++++++++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl | 41 +++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 55 ++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 32 ++- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 4 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 5 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni | 8 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr | 10 +- Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 22 +- Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h | 8 +- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 4 +- 26 files changed, 1490 insertions(+), 25 deletions(-) create mode 100644 Silicon/Socionext/SynQuacer/Acpi.dsc.inc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl -- 2.11.0