From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 659A120955F07 for ; Tue, 27 Feb 2018 01:14:26 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id u49so24026106wrc.10 for ; Tue, 27 Feb 2018 01:20:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AsiL/fQFxhJnta9aj4w3ba4pdzgXXIA+pZKn6+CgAIM=; b=P+vUyUYjhbdcl3F8gsfwJrKSOYcfcicc1DgTebav1EMbVjPHFLYWTfTuateXpzRefy KyQCIn2Qa57kWAI0JrMgQkjQ275ijGPv3rB4g+Vv3zAiYZS0YCz+TeDks+6upZA0JuEd Im+YR03RxQjMrc/FbYRzRw3qRJkgfmXIA4B3Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AsiL/fQFxhJnta9aj4w3ba4pdzgXXIA+pZKn6+CgAIM=; b=NhBBz6qkoanosmPIDvy8SQb7mxLchArivp97CgbgNyqemfIfck9T7JhEGSx2Y+0Rwu 44vUxuE4a34vCH+AgbK2ab1WAqO2f0Ie6WwdZwHzy91Ey1soFs4T8foYPx2sx+UPmWB3 fDmn5luxY5f6lOcH7kzrMD28UUpDw2DtvTDJgo80cS1Y5qobfb4ZCuKqtYXKh5ObEIKO Nwli69vHsmm5Pa8X5tEFRyPQRV9CXfkK/YJFv9Tr4pLdTZ19pETcGdgizM68ulCq1myN ZMVapDaHF2gMHt6rax0DG640qXOFPFd9K5DQRC5DevKYPGE6d8UVwbl/uP8CKr8LtaI2 Q7nQ== X-Gm-Message-State: APf1xPCglpzb5Abdf9QWlB7Lx9F7SU6le+u9/rB8eMi6i8/DjBXIybAS 549GyD5MmqXXIeuczz9m3EfSV/a9WO4= X-Google-Smtp-Source: AH8x224br9lNcz/sRrpOqFvYnB2hZvTmQeemyHbfPkXDQc1+Uh5KzDFSOkdhb2aJ2WnJDaTaR6LXjw== X-Received: by 10.223.174.194 with SMTP id y60mr11542705wrc.202.1519723230808; Tue, 27 Feb 2018 01:20:30 -0800 (PST) Received: from localhost.localdomain ([160.167.215.215]) by smtp.gmail.com with ESMTPSA id x190sm12549865wme.27.2018.02.27.01.20.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Feb 2018 01:20:29 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, graeme.gregory@linaro.org, masahisa.kojima@linaro.org, Ard Biesheuvel Date: Tue, 27 Feb 2018 09:20:13 +0000 Message-Id: <20180227092017.23617-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180227092017.23617-1-ard.biesheuvel@linaro.org> References: <20180227092017.23617-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms 1/5] Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Feb 2018 09:14:26 -0000 Fix the static B/D/F specifiers that refer to the pair of x1 PCIe slots on the DeveloperBox PCB. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h index ee2357be9a06..2d3d5cd91be0 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h @@ -62,7 +62,7 @@ #define SYNQUACER_PCI_LOCATION(s,b,d) (((s) << 16) | ((b) << 8) | (d)) #define SYNQUACER_PCI_SLOT0_LOCATION SYNQUACER_PCI_LOCATION(1, 0, 0) -#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) -#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) +#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) +#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) #endif -- 2.11.0