From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E971D21F0DA69 for ; Tue, 27 Feb 2018 01:14:34 -0800 (PST) Received: by mail-wm0-x244.google.com with SMTP id 139so9209996wmn.2 for ; Tue, 27 Feb 2018 01:20:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1Q8RGmW802i/qQTvZFtCqPGEOxI+LzZr2o4JQKzcqfA=; b=DWiNC4qrSwLtmlQRuZqJIgAVAl85oDVIx+OXFGCJQFG5j3mfoU6mRLf9PmR+lod8Py F1CGT+EWztZpPYwxtR3mjKF+Al2F9MthuD557kwcuuyVOWyZEDNhw4vJKvUTIPogjsXY nNfIt8IKHqHynJzXxKtNxULIxgVc2kK0rLHPA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1Q8RGmW802i/qQTvZFtCqPGEOxI+LzZr2o4JQKzcqfA=; b=TSXrFFgZ4ePNaBYvh0nvuj6eYh5YwlAsU/79rf9IZXk7eHMIt0Ltunq6Vo7fecy51Z MRX9QMlQBbAgm9GNFckpXgFKuwy3KKYq899eWaU9tqzKVpCNzaAfBAwC9d+1gtKP9S6i 5gAiB6zEwcu0lzA7qD7F4pQ/7fI7HMzq5AhbWlwjRW+v9cDAwPPqgKSd2kTgm9jANBsU hefR04nSN7M4AvwcldM/lGNs2FzY2Ogw7tuwwVGgfZ1n6TIm7EfrLbhzEEqAhJMOu5gr 73LU6T6Wr+lkkTRrc/zRTo4KKxnjgptIsXA/ZcpMKimxAPvlkwPWhEjpgKg6hUBV/cGg gFgw== X-Gm-Message-State: APf1xPCI42q0ciLzk1+H8SK90K6AOpluZJS9ICwHyBfudhiBXYB8/IKf 9PLOabxtpUpmJjDuG8KGD7RwklkdI+s= X-Google-Smtp-Source: AG47ELtRCPghcnndFPOwXwfMk0Omh3aWfu2vbt2BMnxKQc0/fs0KlG9IeqTZCeVExVMMeayS47d1Jw== X-Received: by 10.28.153.147 with SMTP id b141mr10414218wme.47.1519723239172; Tue, 27 Feb 2018 01:20:39 -0800 (PST) Received: from localhost.localdomain ([160.167.215.215]) by smtp.gmail.com with ESMTPSA id x190sm12549865wme.27.2018.02.27.01.20.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Feb 2018 01:20:38 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, graeme.gregory@linaro.org, masahisa.kojima@linaro.org, Ard Biesheuvel Date: Tue, 27 Feb 2018 09:20:17 +0000 Message-Id: <20180227092017.23617-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180227092017.23617-1-ard.biesheuvel@linaro.org> References: <20180227092017.23617-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms 5/5] Silicon/SynQuacer/PlatformDxe: add ACPI description of eMMC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Feb 2018 09:14:35 -0000 Expose a separate ACPI description of the SynQuacer eMMC controller when both ACPI and eMMC support have been enabled in the HII menu. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 1 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 1 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl | 41 +++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 55 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 4 ++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 4 ++ 6 files changed, 106 insertions(+) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf index 0d62f3d579cf..2be549027268 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf @@ -447,6 +447,7 @@ [Rule.Common.DXE_DRIVER] PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING="$(MODULE_NAME)" Optional RAW BIN Optional |.dtb + RAW ASL Optional |.aml } [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index 20d19120d1b7..3f47781fe979 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -419,6 +419,7 @@ [Rule.Common.DXE_DRIVER] DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING="$(MODULE_NAME)" Optional + RAW ASL Optional |.aml } [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl new file mode 100644 index 000000000000..4e371befc7b5 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl @@ -0,0 +1,41 @@ +/** @file + SSDT describing the SynQuacer eMMC controller + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +DefinitionBlock ("SsdtEmmc.aml", "SSDT", 1, "SNI", "SynQeMMC", + FixedPcdGet32 (PcdAcpiDefaultOemRevision)) { + Scope (_SB) { + Device (MMC0) { + Name (_HID, "SCX0002") + Name (_UID, Zero) + Name (_CCA, 1) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SYNQUACER_EMMC_BASE, SYNQUACER_EMMC_BASE_SZ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 184 } + }) + + Name (_DSD, Package () // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "bus-width", 8 }, + Package (2) { "cap-mmc-highspeed", 0x1 }, + Package (2) { "fujitsu,cmd-dat-delay-select", 0x1 }, + } + }) + } + } // Scope (_SB) +} diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c index 7284ea6a7cee..e0987c954c74 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c @@ -59,6 +59,10 @@ STATIC EFI_HANDLE mSdMmcControllerHandle; +STATIC EFI_ACPI_DESCRIPTION_HEADER *mSsdt; +STATIC UINTN mSsdtSize; +STATIC VOID *mEventRegistration; + /** Override function for SDHCI capability bits @@ -182,6 +186,31 @@ STATIC EDKII_SD_MMC_OVERRIDE mSdMmcOverride = { SynQuacerSdMmcNotifyPhase, }; +STATIC +VOID +EFIAPI +InstallAcpiTable ( + IN EFI_EVENT Event, + IN VOID* Context + ) +{ + UINTN TableKey; + EFI_STATUS Status; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, + (VOID **)&AcpiTable); + if (EFI_ERROR (Status)) { + return; + } + + Status = AcpiTable->InstallAcpiTable (AcpiTable, mSsdt, mSsdtSize, &TableKey); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to install SSDT table for eMMC - %r\n", + __FUNCTION__, Status)); + } +} + EFI_STATUS EFIAPI RegisterEmmc ( @@ -190,6 +219,32 @@ RegisterEmmc ( { EFI_STATUS Status; EFI_HANDLE Handle; + UINTN Index; + + if (mHiiSettings->AcpiPref == ACPIPREF_ACPI) { + // + // Load the SSDT table from a raw section in this FFS file. + // + for (Index = 0;; Index++) { + Status = GetSectionFromFv (&gEfiCallerIdGuid, EFI_SECTION_RAW, Index, + (VOID **)&mSsdt, &mSsdtSize); + if (EFI_ERROR (Status)) { + break; + } + + if (mSsdt->OemTableId != EMMC_TABLE_ID) { + continue; + } + + // + // Register for the ACPI table protocol + // + EfiCreateProtocolNotifyEvent (&gEfiAcpiTableProtocolGuid, TPL_CALLBACK, + InstallAcpiTable, NULL, &mEventRegistration); + + break; + } + } Status = RegisterNonDiscoverableMmioDevice ( NonDiscoverableDeviceTypeSdhci, diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h index a391d2f67c29..c25b7f168a37 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -35,10 +36,13 @@ #include #include #include +#include #include #include #include +#define EMMC_TABLE_ID SIGNATURE_64('S','y','n','Q','e','M','M','C') + extern UINT8 PlatformDxeHiiBin[]; extern UINT8 PlatformDxeStrings[]; diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index bef7feccd8b8..8df3073bf24b 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -23,6 +23,7 @@ [Defines] ENTRY_POINT = PlatformDxeEntryPoint [Sources] + Emmc.asl Emmc.c Pci.c PlatformDxe.c @@ -46,6 +47,7 @@ [LibraryClasses] DebugLib DevicePathLib DtPlatformDtbLoaderLib + DxeServicesLib HiiLib IoLib MemoryAllocationLib @@ -69,10 +71,12 @@ [Guids] [Protocols] gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES gEdkiiSdMmcOverrideProtocolGuid ## PRODUCES + gEfiAcpiTableProtocolGuid ## CONSUMES gEfiPciIoProtocolGuid ## CONSUMES gPcf8563RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES [FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress -- 2.11.0