* [PATCH edk2-platforms 0/5] SynQuacer ACPI support
@ 2018-02-27 9:20 Ard Biesheuvel
2018-02-27 9:20 ` [PATCH edk2-platforms 1/5] Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping Ard Biesheuvel
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Ard Biesheuvel @ 2018-02-27 9:20 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, graeme.gregory, masahisa.kojima, Ard Biesheuvel
This implements ACPI support for the SynQuacer platforms.
Note that supporting ACPI on this SoC is non-trivial, due to the quirky
DesignWare RCs and the pre-ITS that sits between the PCIe RCs and the GICv3.
However, the most important issue has been addressed by modifying the static
SMMU mapping that sits between the CPUs and the PCIe config space, working
around the ghosting issue that occurs on these RCs, due the complete lack of
type 0 config TLP filtering by the [non-existent] root port. (This was tested
using the 20180226-LB1.1-ACPI-ramfw.bin SCP firmware image, which is not [yet]
installed by default on DeveloperBox hardware)
That leaves the MSI issue, which is worked around by limiting MSI support to a
single RC. In the presented configuration, this is RC #1, which connects to the
x16 slot [and nothing else] on the DeveloperBox PCB. The onboard PCIe devices
(XHCI + SATA) work without problem using wired interrupts only, and so RC #0
has MSI support disabled. This means cards that require MSI support should
be inserted into the x16 slot, which is likely to be the preferred slot in
such cases anwyay (e.g., when using NVME or high end networking plugin cards)
Patch #1 fixes a minor issue in the slot-to-BDF mapping.
Patch #2 modifies the static PCIe window configuration so it can be described
using ACPI as well as DT.
Patch #3 introduces the static ACPI tables that describe the fixed platform
devices and peripherals to the OS.
Patch #4 adds a menu option to the platform driver to make ACPI vs DT user
selectable.
Patch #5 adds support for describing the eMMC controller using a SSDT table
which is only installed if eMMC support is enabled.
Note that driver support for the eMMC and network controller only landed in
v4.15, but when using a SATA driver and a plugin network card that does have
driver support, these patches should allow the SynQuacer based platforms to
boot stock Debian Stretch/Fedora/Centos etc installers.
Ard Biesheuvel (5):
Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping
Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support
Silicon/SynQuacer: add ACPI drivers and tables
Silicon/SynQuacer/PlatformDxe: add option to enable ACPI mode
Silicon/SynQuacer/PlatformDxe: add ACPI description of eMMC
Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 2 +
Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 14 ++
Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 +
Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 14 ++
Silicon/Socionext/SynQuacer/Acpi.dsc.inc | 48 ++++
Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl | 262 ++++++++++++++++++++
Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h | 73 ++++++
Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf | 64 +++++
Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 187 ++++++++++++++
Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc | 91 +++++++
Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc | 93 +++++++
Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 101 ++++++++
Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc | 182 ++++++++++++++
Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc | 63 +++++
Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc | 128 ++++++++++
Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 +-
Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl | 41 +++
Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 55 ++++
Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 32 ++-
Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 4 +
Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 5 +
Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni | 8 +-
Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr | 10 +-
Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 22 +-
Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h | 8 +-
Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 4 +-
26 files changed, 1490 insertions(+), 25 deletions(-)
create mode 100644 Silicon/Socionext/SynQuacer/Acpi.dsc.inc
create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl
create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h
create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf
create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl
create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc
create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc
create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc
create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc
create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc
create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc
create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl
--
2.11.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH edk2-platforms 1/5] Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping 2018-02-27 9:20 [PATCH edk2-platforms 0/5] SynQuacer ACPI support Ard Biesheuvel @ 2018-02-27 9:20 ` Ard Biesheuvel 2018-02-28 16:17 ` Leif Lindholm 2018-02-27 9:20 ` [PATCH edk2-platforms 2/5] Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support Ard Biesheuvel ` (3 subsequent siblings) 4 siblings, 1 reply; 14+ messages in thread From: Ard Biesheuvel @ 2018-02-27 9:20 UTC (permalink / raw) To: edk2-devel; +Cc: leif.lindholm, graeme.gregory, masahisa.kojima, Ard Biesheuvel Fix the static B/D/F specifiers that refer to the pair of x1 PCIe slots on the DeveloperBox PCB. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h index ee2357be9a06..2d3d5cd91be0 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h @@ -62,7 +62,7 @@ #define SYNQUACER_PCI_LOCATION(s,b,d) (((s) << 16) | ((b) << 8) | (d)) #define SYNQUACER_PCI_SLOT0_LOCATION SYNQUACER_PCI_LOCATION(1, 0, 0) -#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) -#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) +#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) +#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) #endif -- 2.11.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH edk2-platforms 1/5] Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping 2018-02-27 9:20 ` [PATCH edk2-platforms 1/5] Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping Ard Biesheuvel @ 2018-02-28 16:17 ` Leif Lindholm 2018-02-28 16:18 ` Ard Biesheuvel 0 siblings, 1 reply; 14+ messages in thread From: Leif Lindholm @ 2018-02-28 16:17 UTC (permalink / raw) To: Ard Biesheuvel; +Cc: edk2-devel, graeme.gregory, masahisa.kojima On Tue, Feb 27, 2018 at 09:20:13AM +0000, Ard Biesheuvel wrote: > Fix the static B/D/F specifiers that refer to the pair of x1 PCIe slots > on the DeveloperBox PCB. What is the user-observable problem that is addressed by this patch? > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > --- > Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > index ee2357be9a06..2d3d5cd91be0 100644 > --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > @@ -62,7 +62,7 @@ > > #define SYNQUACER_PCI_LOCATION(s,b,d) (((s) << 16) | ((b) << 8) | (d)) > #define SYNQUACER_PCI_SLOT0_LOCATION SYNQUACER_PCI_LOCATION(1, 0, 0) > -#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) > -#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) > +#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) > +#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) > > #endif > -- > 2.11.0 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH edk2-platforms 1/5] Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping 2018-02-28 16:17 ` Leif Lindholm @ 2018-02-28 16:18 ` Ard Biesheuvel 2018-02-28 16:39 ` Leif Lindholm 0 siblings, 1 reply; 14+ messages in thread From: Ard Biesheuvel @ 2018-02-28 16:18 UTC (permalink / raw) To: Leif Lindholm; +Cc: edk2-devel@lists.01.org, Graeme Gregory, Masahisa Kojima On 28 February 2018 at 16:17, Leif Lindholm <leif.lindholm@linaro.org> wrote: > On Tue, Feb 27, 2018 at 09:20:13AM +0000, Ard Biesheuvel wrote: >> Fix the static B/D/F specifiers that refer to the pair of x1 PCIe slots >> on the DeveloperBox PCB. > > What is the user-observable problem that is addressed by this patch? > That limiting the speed of slot 1 affects slot 2 >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> >> --- >> Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> index ee2357be9a06..2d3d5cd91be0 100644 >> --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> @@ -62,7 +62,7 @@ >> >> #define SYNQUACER_PCI_LOCATION(s,b,d) (((s) << 16) | ((b) << 8) | (d)) >> #define SYNQUACER_PCI_SLOT0_LOCATION SYNQUACER_PCI_LOCATION(1, 0, 0) >> -#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) >> -#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) >> +#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) >> +#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) >> >> #endif >> -- >> 2.11.0 >> ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH edk2-platforms 1/5] Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping 2018-02-28 16:18 ` Ard Biesheuvel @ 2018-02-28 16:39 ` Leif Lindholm 0 siblings, 0 replies; 14+ messages in thread From: Leif Lindholm @ 2018-02-28 16:39 UTC (permalink / raw) To: Ard Biesheuvel; +Cc: edk2-devel@lists.01.org, Graeme Gregory, Masahisa Kojima On Wed, Feb 28, 2018 at 04:18:50PM +0000, Ard Biesheuvel wrote: > On 28 February 2018 at 16:17, Leif Lindholm <leif.lindholm@linaro.org> wrote: > > On Tue, Feb 27, 2018 at 09:20:13AM +0000, Ard Biesheuvel wrote: > >> Fix the static B/D/F specifiers that refer to the pair of x1 PCIe slots > >> on the DeveloperBox PCB. > > > > What is the user-observable problem that is addressed by this patch? > > That limiting the speed of slot 1 affects slot 2 Could you add that to the commit message please? Something like "The current configuration caused user-configurable settings for slots 1/2 to apply to the incorrect one.". > >> Contributed-under: TianoCore Contribution Agreement 1.1 > >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > >> --- > >> Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 4 ++-- > >> 1 file changed, 2 insertions(+), 2 deletions(-) > >> > >> diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > >> index ee2357be9a06..2d3d5cd91be0 100644 > >> --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > >> +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > >> @@ -62,7 +62,7 @@ > >> > >> #define SYNQUACER_PCI_LOCATION(s,b,d) (((s) << 16) | ((b) << 8) | (d)) > >> #define SYNQUACER_PCI_SLOT0_LOCATION SYNQUACER_PCI_LOCATION(1, 0, 0) > >> -#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) > >> -#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) > >> +#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) > >> +#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) > >> > >> #endif > >> -- > >> 2.11.0 > >> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms 2/5] Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support 2018-02-27 9:20 [PATCH edk2-platforms 0/5] SynQuacer ACPI support Ard Biesheuvel 2018-02-27 9:20 ` [PATCH edk2-platforms 1/5] Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping Ard Biesheuvel @ 2018-02-27 9:20 ` Ard Biesheuvel 2018-02-28 16:26 ` Leif Lindholm 2018-02-27 9:20 ` [PATCH edk2-platforms 3/5] Silicon/SynQuacer: add ACPI drivers and tables Ard Biesheuvel ` (2 subsequent siblings) 4 siblings, 1 reply; 14+ messages in thread From: Ard Biesheuvel @ 2018-02-27 9:20 UTC (permalink / raw) To: edk2-devel; +Cc: leif.lindholm, graeme.gregory, masahisa.kojima, Ard Biesheuvel ACPI is not able to describe PCI resource windows that involve both type and address translation (i.e., for I/O windows on architectures that do not support port I/O natively), and so the ACPI/Linux code has a hard time performing the resource allocation in such cases. For instance, the secondary I/O window we implement on SynQuacer: I/O 0x10000 ... 0x1ffff -> 0x77f00000 is misinterpreted by Linux, and results in the MMIO range starting at 0x77f10000 to be mapped for I/O port access to this range. This can be mitigated by using the same PCI range for I/O port access on both RCs., i.e., 0x0 ... 0xffff. This configuration can be represented using both DT and ACPI, and will work as expected in Linux, since it only involves type translation and not address translation. However, there is a downside: EDK2 does not cope with I/O address translation in the generic PCI host bridge driver, and so it does not allow two regions 0x0 ... 0xffff to be configured. So in addition, let's reduce the windows declared to the UEFI PCI layer to 0x0 ... 0x7fff and 0x8000 ... 0xffff. This leaves ample room for I/O BARs (which nobody uses anymore anyway), and allows UEFI and the OS to share the same static configuration of the PCIe BAR windows. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Heyi Gui is currently implementing support for address translation in the generic PCI host bridge driver, so hopefully, limiting the I/O ranges in UEFI is something we can revert shortly. Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 +- Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 18 +++++++++++------- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 4 ++-- 3 files changed, 14 insertions(+), 10 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 05d1673a5c2b..6eb5fd9430cb 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -483,7 +483,7 @@ bus-range = <0x0 0x7e>; #address-cells = <3>; #size-cells = <2>; - ranges = <0x1000000 0x00 0x00010000 0x00 0x77f00000 0x0 0x00010000>, + ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>, <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>, <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h index 2d3d5cd91be0..ee57377ac3be 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h @@ -23,12 +23,12 @@ #define SYNQUACER_PCI_SEG0_BUSNUM_MIN 0x0 #define SYNQUACER_PCI_SEG0_BUSNUM_MAX 0x7e +#define SYNQUACER_PCI_SEG0_BUSNUM_RANGE 0x7f #define SYNQUACER_PCI_SEG0_PORTIO_MIN 0x0 -#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0xffff -#define SYNQUACER_PCI_SEG0_PORTIO_SIZE 0x10000 +#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0x7fff #define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE 0x67f00000 -#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE SYNQUACER_PCI_SEG0_PORTIO_SIZE +#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE 0x10000 #define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000 #define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff @@ -45,12 +45,12 @@ #define SYNQUACER_PCI_SEG1_BUSNUM_MIN 0x0 #define SYNQUACER_PCI_SEG1_BUSNUM_MAX 0x7e +#define SYNQUACER_PCI_SEG1_BUSNUM_RANGE 0x7f -#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x10000 -#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0x1ffff -#define SYNQUACER_PCI_SEG1_PORTIO_SIZE 0x10000 +#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x8000 +#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0xffff #define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE 0x77f00000 -#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE SYNQUACER_PCI_SEG1_PORTIO_SIZE +#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE 0x10000 #define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000 #define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff @@ -65,4 +65,8 @@ #define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) #define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) +#define SYNQUACER_PCI_OS_IO_BASE 0x0 +#define SYNQUACER_PCI_OS_IO_LIMIT 0xffff +#define SYNQUACER_PCI_OS_IO_RANGE 0x10000 + #endif diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index e4679543cc66..6a3b32f6ca55 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -348,8 +348,8 @@ PciInitControllerPost ( // Region 3: port I/O range ConfigureWindow (DbiBase, 3, IoMemBase, - RootBridge->Io.Base, - RootBridge->Io.Limit - RootBridge->Io.Base + 1, + SYNQUACER_PCI_OS_IO_BASE, + SYNQUACER_PCI_OS_IO_RANGE, IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO, 0); -- 2.11.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH edk2-platforms 2/5] Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support 2018-02-27 9:20 ` [PATCH edk2-platforms 2/5] Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support Ard Biesheuvel @ 2018-02-28 16:26 ` Leif Lindholm 2018-02-28 16:30 ` Ard Biesheuvel 0 siblings, 1 reply; 14+ messages in thread From: Leif Lindholm @ 2018-02-28 16:26 UTC (permalink / raw) To: Ard Biesheuvel; +Cc: edk2-devel, graeme.gregory, masahisa.kojima On Tue, Feb 27, 2018 at 09:20:14AM +0000, Ard Biesheuvel wrote: > ACPI is not able to describe PCI resource windows that involve both type > and address translation (i.e., for I/O windows on architectures that do > not support port I/O natively), and so the ACPI/Linux code has a hard > time performing the resource allocation in such cases. For instance, the > secondary I/O window we implement on SynQuacer: > > I/O 0x10000 ... 0x1ffff -> 0x77f00000 > > is misinterpreted by Linux, and results in the MMIO range starting at > 0x77f10000 to be mapped for I/O port access to this range. > > This can be mitigated by using the same PCI range for I/O port access > on both RCs., i.e., 0x0 ... 0xffff. This configuration can be represented > using both DT and ACPI, and will work as expected in Linux, since it only > involves type translation and not address translation. > > However, there is a downside: EDK2 does not cope with I/O address > translation in the generic PCI host bridge driver, and so it does > not allow two regions 0x0 ... 0xffff to be configured. > > So in addition, let's reduce the windows declared to the UEFI PCI layer > to 0x0 ... 0x7fff and 0x8000 ... 0xffff. ", able to cover windows witha single 64KB page."? > This leaves ample room for I/O > BARs (which nobody uses anymore anyway), and allows UEFI and the OS to > share the same static configuration of the PCIe BAR windows. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > --- > Heyi Gui is currently implementing support for address translation in > the generic PCI host bridge driver, so hopefully, limiting the I/O > ranges in UEFI is something we can revert shortly. > > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 +- > Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 18 +++++++++++------- > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 4 ++-- > 3 files changed, 14 insertions(+), 10 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > index 05d1673a5c2b..6eb5fd9430cb 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > @@ -483,7 +483,7 @@ > bus-range = <0x0 0x7e>; > #address-cells = <3>; > #size-cells = <2>; > - ranges = <0x1000000 0x00 0x00010000 0x00 0x77f00000 0x0 0x00010000>, > + ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>, > <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>, > <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; > > diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > index 2d3d5cd91be0..ee57377ac3be 100644 > --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > @@ -23,12 +23,12 @@ > > #define SYNQUACER_PCI_SEG0_BUSNUM_MIN 0x0 > #define SYNQUACER_PCI_SEG0_BUSNUM_MAX 0x7e > +#define SYNQUACER_PCI_SEG0_BUSNUM_RANGE 0x7f > > #define SYNQUACER_PCI_SEG0_PORTIO_MIN 0x0 > -#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0xffff > -#define SYNQUACER_PCI_SEG0_PORTIO_SIZE 0x10000 > +#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0x7fff > #define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE 0x67f00000 > -#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE SYNQUACER_PCI_SEG0_PORTIO_SIZE > +#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE 0x10000 > > #define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000 > #define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff > @@ -45,12 +45,12 @@ > > #define SYNQUACER_PCI_SEG1_BUSNUM_MIN 0x0 > #define SYNQUACER_PCI_SEG1_BUSNUM_MAX 0x7e > +#define SYNQUACER_PCI_SEG1_BUSNUM_RANGE 0x7f > > -#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x10000 > -#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0x1ffff > -#define SYNQUACER_PCI_SEG1_PORTIO_SIZE 0x10000 > +#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x8000 > +#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0xffff > #define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE 0x77f00000 > -#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE SYNQUACER_PCI_SEG1_PORTIO_SIZE > +#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE 0x10000 > > #define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000 > #define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff > @@ -65,4 +65,8 @@ > #define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) > #define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) > > +#define SYNQUACER_PCI_OS_IO_BASE 0x0 > +#define SYNQUACER_PCI_OS_IO_LIMIT 0xffff > +#define SYNQUACER_PCI_OS_IO_RANGE 0x10000 Would you be greatly opposed to describing these as #define SYNQUACER_PCI_OS_IO_BASE SYNQUACER_PCI_SEG0_PORTIO_MIN #define SYNQUACER_PCI_OS_IO_LIMIT SYNQUACER_PCI_SEG1_PORTIO_MAX #define SYNQUACER_PCI_OS_IO_RANGE SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE or #define SYNQUACER_PCI_OS_IO_RANGE SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE which aren't conceptually the same, but explicitly describe the desired configuration in this case? / Leif > + > #endif > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > index e4679543cc66..6a3b32f6ca55 100644 > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > @@ -348,8 +348,8 @@ PciInitControllerPost ( > // Region 3: port I/O range > ConfigureWindow (DbiBase, 3, > IoMemBase, > - RootBridge->Io.Base, > - RootBridge->Io.Limit - RootBridge->Io.Base + 1, > + SYNQUACER_PCI_OS_IO_BASE, > + SYNQUACER_PCI_OS_IO_RANGE, > IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO, > 0); > > -- > 2.11.0 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH edk2-platforms 2/5] Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support 2018-02-28 16:26 ` Leif Lindholm @ 2018-02-28 16:30 ` Ard Biesheuvel 2018-02-28 16:43 ` Leif Lindholm 0 siblings, 1 reply; 14+ messages in thread From: Ard Biesheuvel @ 2018-02-28 16:30 UTC (permalink / raw) To: Leif Lindholm; +Cc: edk2-devel@lists.01.org, Graeme Gregory, Masahisa Kojima On 28 February 2018 at 16:26, Leif Lindholm <leif.lindholm@linaro.org> wrote: > On Tue, Feb 27, 2018 at 09:20:14AM +0000, Ard Biesheuvel wrote: >> ACPI is not able to describe PCI resource windows that involve both type >> and address translation (i.e., for I/O windows on architectures that do >> not support port I/O natively), and so the ACPI/Linux code has a hard >> time performing the resource allocation in such cases. For instance, the >> secondary I/O window we implement on SynQuacer: >> >> I/O 0x10000 ... 0x1ffff -> 0x77f00000 >> >> is misinterpreted by Linux, and results in the MMIO range starting at >> 0x77f10000 to be mapped for I/O port access to this range. >> >> This can be mitigated by using the same PCI range for I/O port access >> on both RCs., i.e., 0x0 ... 0xffff. This configuration can be represented >> using both DT and ACPI, and will work as expected in Linux, since it only >> involves type translation and not address translation. >> >> However, there is a downside: EDK2 does not cope with I/O address >> translation in the generic PCI host bridge driver, and so it does >> not allow two regions 0x0 ... 0xffff to be configured. >> >> So in addition, let's reduce the windows declared to the UEFI PCI layer >> to 0x0 ... 0x7fff and 0x8000 ... 0xffff. > > ", able to cover windows witha single 64KB page."? > ?? >> This leaves ample room for I/O >> BARs (which nobody uses anymore anyway), and allows UEFI and the OS to >> share the same static configuration of the PCIe BAR windows. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> >> --- >> Heyi Gui is currently implementing support for address translation in >> the generic PCI host bridge driver, so hopefully, limiting the I/O >> ranges in UEFI is something we can revert shortly. >> >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 +- >> Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 18 +++++++++++------- >> Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 4 ++-- >> 3 files changed, 14 insertions(+), 10 deletions(-) >> >> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> index 05d1673a5c2b..6eb5fd9430cb 100644 >> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> @@ -483,7 +483,7 @@ >> bus-range = <0x0 0x7e>; >> #address-cells = <3>; >> #size-cells = <2>; >> - ranges = <0x1000000 0x00 0x00010000 0x00 0x77f00000 0x0 0x00010000>, >> + ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>, >> <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>, >> <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; >> >> diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> index 2d3d5cd91be0..ee57377ac3be 100644 >> --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> @@ -23,12 +23,12 @@ >> >> #define SYNQUACER_PCI_SEG0_BUSNUM_MIN 0x0 >> #define SYNQUACER_PCI_SEG0_BUSNUM_MAX 0x7e >> +#define SYNQUACER_PCI_SEG0_BUSNUM_RANGE 0x7f >> >> #define SYNQUACER_PCI_SEG0_PORTIO_MIN 0x0 >> -#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0xffff >> -#define SYNQUACER_PCI_SEG0_PORTIO_SIZE 0x10000 >> +#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0x7fff >> #define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE 0x67f00000 >> -#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE SYNQUACER_PCI_SEG0_PORTIO_SIZE >> +#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE 0x10000 >> >> #define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000 >> #define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff >> @@ -45,12 +45,12 @@ >> >> #define SYNQUACER_PCI_SEG1_BUSNUM_MIN 0x0 >> #define SYNQUACER_PCI_SEG1_BUSNUM_MAX 0x7e >> +#define SYNQUACER_PCI_SEG1_BUSNUM_RANGE 0x7f >> >> -#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x10000 >> -#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0x1ffff >> -#define SYNQUACER_PCI_SEG1_PORTIO_SIZE 0x10000 >> +#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x8000 >> +#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0xffff >> #define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE 0x77f00000 >> -#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE SYNQUACER_PCI_SEG1_PORTIO_SIZE >> +#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE 0x10000 >> >> #define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000 >> #define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff >> @@ -65,4 +65,8 @@ >> #define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) >> #define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) >> >> +#define SYNQUACER_PCI_OS_IO_BASE 0x0 >> +#define SYNQUACER_PCI_OS_IO_LIMIT 0xffff >> +#define SYNQUACER_PCI_OS_IO_RANGE 0x10000 > > Would you be greatly opposed to describing these as > > #define SYNQUACER_PCI_OS_IO_BASE SYNQUACER_PCI_SEG0_PORTIO_MIN > #define SYNQUACER_PCI_OS_IO_LIMIT SYNQUACER_PCI_SEG1_PORTIO_MAX > #define SYNQUACER_PCI_OS_IO_RANGE SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE > or > #define SYNQUACER_PCI_OS_IO_RANGE SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE > > which aren't conceptually the same, but explicitly describe the > desired configuration in this case? > Sure. And as a bonus, these will still be correct after Heyi's PciHostbridgeDxe patches get merged and we can move to 0x0..0xffff for both regions. ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH edk2-platforms 2/5] Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support 2018-02-28 16:30 ` Ard Biesheuvel @ 2018-02-28 16:43 ` Leif Lindholm 2018-02-28 16:46 ` Ard Biesheuvel 0 siblings, 1 reply; 14+ messages in thread From: Leif Lindholm @ 2018-02-28 16:43 UTC (permalink / raw) To: Ard Biesheuvel; +Cc: edk2-devel@lists.01.org, Graeme Gregory, Masahisa Kojima On Wed, Feb 28, 2018 at 04:30:50PM +0000, Ard Biesheuvel wrote: > On 28 February 2018 at 16:26, Leif Lindholm <leif.lindholm@linaro.org> wrote: > > On Tue, Feb 27, 2018 at 09:20:14AM +0000, Ard Biesheuvel wrote: > >> ACPI is not able to describe PCI resource windows that involve both type > >> and address translation (i.e., for I/O windows on architectures that do > >> not support port I/O natively), and so the ACPI/Linux code has a hard > >> time performing the resource allocation in such cases. For instance, the > >> secondary I/O window we implement on SynQuacer: > >> > >> I/O 0x10000 ... 0x1ffff -> 0x77f00000 > >> > >> is misinterpreted by Linux, and results in the MMIO range starting at > >> 0x77f10000 to be mapped for I/O port access to this range. > >> > >> This can be mitigated by using the same PCI range for I/O port access > >> on both RCs., i.e., 0x0 ... 0xffff. This configuration can be represented > >> using both DT and ACPI, and will work as expected in Linux, since it only > >> involves type translation and not address translation. > >> > >> However, there is a downside: EDK2 does not cope with I/O address > >> translation in the generic PCI host bridge driver, and so it does > >> not allow two regions 0x0 ... 0xffff to be configured. > >> > >> So in addition, let's reduce the windows declared to the UEFI PCI layer > >> to 0x0 ... 0x7fff and 0x8000 ... 0xffff. > > > > ", able to cover windows witha single 64KB page."? > > ?? Or why was that size picked? Seems consistent with our "no conflicting mappings within a 64KB region" rule. > >> This leaves ample room for I/O > >> BARs (which nobody uses anymore anyway), and allows UEFI and the OS to > >> share the same static configuration of the PCIe BAR windows. > >> > >> Contributed-under: TianoCore Contribution Agreement 1.1 > >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > >> --- > >> Heyi Gui is currently implementing support for address translation in > >> the generic PCI host bridge driver, so hopefully, limiting the I/O > >> ranges in UEFI is something we can revert shortly. > >> > >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 +- > >> Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 18 +++++++++++------- > >> Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 4 ++-- > >> 3 files changed, 14 insertions(+), 10 deletions(-) > >> > >> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > >> index 05d1673a5c2b..6eb5fd9430cb 100644 > >> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > >> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > >> @@ -483,7 +483,7 @@ > >> bus-range = <0x0 0x7e>; > >> #address-cells = <3>; > >> #size-cells = <2>; > >> - ranges = <0x1000000 0x00 0x00010000 0x00 0x77f00000 0x0 0x00010000>, > >> + ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>, > >> <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>, > >> <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; > >> > >> diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > >> index 2d3d5cd91be0..ee57377ac3be 100644 > >> --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > >> +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > >> @@ -23,12 +23,12 @@ > >> > >> #define SYNQUACER_PCI_SEG0_BUSNUM_MIN 0x0 > >> #define SYNQUACER_PCI_SEG0_BUSNUM_MAX 0x7e > >> +#define SYNQUACER_PCI_SEG0_BUSNUM_RANGE 0x7f > >> > >> #define SYNQUACER_PCI_SEG0_PORTIO_MIN 0x0 > >> -#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0xffff > >> -#define SYNQUACER_PCI_SEG0_PORTIO_SIZE 0x10000 > >> +#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0x7fff > >> #define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE 0x67f00000 > >> -#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE SYNQUACER_PCI_SEG0_PORTIO_SIZE > >> +#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE 0x10000 > >> > >> #define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000 > >> #define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff > >> @@ -45,12 +45,12 @@ > >> > >> #define SYNQUACER_PCI_SEG1_BUSNUM_MIN 0x0 > >> #define SYNQUACER_PCI_SEG1_BUSNUM_MAX 0x7e > >> +#define SYNQUACER_PCI_SEG1_BUSNUM_RANGE 0x7f > >> > >> -#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x10000 > >> -#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0x1ffff > >> -#define SYNQUACER_PCI_SEG1_PORTIO_SIZE 0x10000 > >> +#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x8000 > >> +#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0xffff > >> #define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE 0x77f00000 > >> -#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE SYNQUACER_PCI_SEG1_PORTIO_SIZE > >> +#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE 0x10000 > >> > >> #define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000 > >> #define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff > >> @@ -65,4 +65,8 @@ > >> #define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) > >> #define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) > >> > >> +#define SYNQUACER_PCI_OS_IO_BASE 0x0 > >> +#define SYNQUACER_PCI_OS_IO_LIMIT 0xffff > >> +#define SYNQUACER_PCI_OS_IO_RANGE 0x10000 > > > > Would you be greatly opposed to describing these as > > > > #define SYNQUACER_PCI_OS_IO_BASE SYNQUACER_PCI_SEG0_PORTIO_MIN > > #define SYNQUACER_PCI_OS_IO_LIMIT SYNQUACER_PCI_SEG1_PORTIO_MAX > > #define SYNQUACER_PCI_OS_IO_RANGE SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE > > or > > #define SYNQUACER_PCI_OS_IO_RANGE SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE > > > > which aren't conceptually the same, but explicitly describe the > > desired configuration in this case? > > Sure. And as a bonus, these will still be correct after Heyi's > PciHostbridgeDxe patches get merged and we can move to 0x0..0xffff for > both regions. \o/ / Leif ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH edk2-platforms 2/5] Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support 2018-02-28 16:43 ` Leif Lindholm @ 2018-02-28 16:46 ` Ard Biesheuvel 0 siblings, 0 replies; 14+ messages in thread From: Ard Biesheuvel @ 2018-02-28 16:46 UTC (permalink / raw) To: Leif Lindholm; +Cc: edk2-devel@lists.01.org, Graeme Gregory, Masahisa Kojima On 28 February 2018 at 16:43, Leif Lindholm <leif.lindholm@linaro.org> wrote: > On Wed, Feb 28, 2018 at 04:30:50PM +0000, Ard Biesheuvel wrote: >> On 28 February 2018 at 16:26, Leif Lindholm <leif.lindholm@linaro.org> wrote: >> > On Tue, Feb 27, 2018 at 09:20:14AM +0000, Ard Biesheuvel wrote: >> >> ACPI is not able to describe PCI resource windows that involve both type >> >> and address translation (i.e., for I/O windows on architectures that do >> >> not support port I/O natively), and so the ACPI/Linux code has a hard >> >> time performing the resource allocation in such cases. For instance, the >> >> secondary I/O window we implement on SynQuacer: >> >> >> >> I/O 0x10000 ... 0x1ffff -> 0x77f00000 >> >> >> >> is misinterpreted by Linux, and results in the MMIO range starting at >> >> 0x77f10000 to be mapped for I/O port access to this range. >> >> >> >> This can be mitigated by using the same PCI range for I/O port access >> >> on both RCs., i.e., 0x0 ... 0xffff. This configuration can be represented >> >> using both DT and ACPI, and will work as expected in Linux, since it only >> >> involves type translation and not address translation. >> >> >> >> However, there is a downside: EDK2 does not cope with I/O address >> >> translation in the generic PCI host bridge driver, and so it does >> >> not allow two regions 0x0 ... 0xffff to be configured. >> >> >> >> So in addition, let's reduce the windows declared to the UEFI PCI layer >> >> to 0x0 ... 0x7fff and 0x8000 ... 0xffff. >> > >> > ", able to cover windows witha single 64KB page."? >> >> ?? > > Or why was that size picked? > > Seems consistent with our "no conflicting mappings within a 64KB > region" rule. > Not really. I think 16 bits of I/O space is rather common, but we could also increase both I/O windows to 0x0 .. 0x1ffff, and split them into 0x0..0xffff and 0x10000..0x1ffff on the UEFI side. Also, they don't even have to be adjacent, as long as we use a 1:1 mapped slice for each. >> >> This leaves ample room for I/O >> >> BARs (which nobody uses anymore anyway), and allows UEFI and the OS to >> >> share the same static configuration of the PCIe BAR windows. >> >> >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> >> >> --- >> >> Heyi Gui is currently implementing support for address translation in >> >> the generic PCI host bridge driver, so hopefully, limiting the I/O >> >> ranges in UEFI is something we can revert shortly. >> >> >> >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 +- >> >> Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 18 +++++++++++------- >> >> Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 4 ++-- >> >> 3 files changed, 14 insertions(+), 10 deletions(-) >> >> >> >> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> >> index 05d1673a5c2b..6eb5fd9430cb 100644 >> >> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> >> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> >> @@ -483,7 +483,7 @@ >> >> bus-range = <0x0 0x7e>; >> >> #address-cells = <3>; >> >> #size-cells = <2>; >> >> - ranges = <0x1000000 0x00 0x00010000 0x00 0x77f00000 0x0 0x00010000>, >> >> + ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>, >> >> <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>, >> >> <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; >> >> >> >> diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> >> index 2d3d5cd91be0..ee57377ac3be 100644 >> >> --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> >> +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> >> @@ -23,12 +23,12 @@ >> >> >> >> #define SYNQUACER_PCI_SEG0_BUSNUM_MIN 0x0 >> >> #define SYNQUACER_PCI_SEG0_BUSNUM_MAX 0x7e >> >> +#define SYNQUACER_PCI_SEG0_BUSNUM_RANGE 0x7f >> >> >> >> #define SYNQUACER_PCI_SEG0_PORTIO_MIN 0x0 >> >> -#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0xffff >> >> -#define SYNQUACER_PCI_SEG0_PORTIO_SIZE 0x10000 >> >> +#define SYNQUACER_PCI_SEG0_PORTIO_MAX 0x7fff >> >> #define SYNQUACER_PCI_SEG0_PORTIO_MEMBASE 0x67f00000 >> >> -#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE SYNQUACER_PCI_SEG0_PORTIO_SIZE >> >> +#define SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE 0x10000 >> >> >> >> #define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000 >> >> #define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff >> >> @@ -45,12 +45,12 @@ >> >> >> >> #define SYNQUACER_PCI_SEG1_BUSNUM_MIN 0x0 >> >> #define SYNQUACER_PCI_SEG1_BUSNUM_MAX 0x7e >> >> +#define SYNQUACER_PCI_SEG1_BUSNUM_RANGE 0x7f >> >> >> >> -#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x10000 >> >> -#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0x1ffff >> >> -#define SYNQUACER_PCI_SEG1_PORTIO_SIZE 0x10000 >> >> +#define SYNQUACER_PCI_SEG1_PORTIO_MIN 0x8000 >> >> +#define SYNQUACER_PCI_SEG1_PORTIO_MAX 0xffff >> >> #define SYNQUACER_PCI_SEG1_PORTIO_MEMBASE 0x77f00000 >> >> -#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE SYNQUACER_PCI_SEG1_PORTIO_SIZE >> >> +#define SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE 0x10000 >> >> >> >> #define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000 >> >> #define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff >> >> @@ -65,4 +65,8 @@ >> >> #define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) >> >> #define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) >> >> >> >> +#define SYNQUACER_PCI_OS_IO_BASE 0x0 >> >> +#define SYNQUACER_PCI_OS_IO_LIMIT 0xffff >> >> +#define SYNQUACER_PCI_OS_IO_RANGE 0x10000 >> > >> > Would you be greatly opposed to describing these as >> > >> > #define SYNQUACER_PCI_OS_IO_BASE SYNQUACER_PCI_SEG0_PORTIO_MIN >> > #define SYNQUACER_PCI_OS_IO_LIMIT SYNQUACER_PCI_SEG1_PORTIO_MAX >> > #define SYNQUACER_PCI_OS_IO_RANGE SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE >> > or >> > #define SYNQUACER_PCI_OS_IO_RANGE SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE >> > >> > which aren't conceptually the same, but explicitly describe the >> > desired configuration in this case? >> >> Sure. And as a bonus, these will still be correct after Heyi's >> PciHostbridgeDxe patches get merged and we can move to 0x0..0xffff for >> both regions. > > \o/ > > / > Leif ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms 3/5] Silicon/SynQuacer: add ACPI drivers and tables 2018-02-27 9:20 [PATCH edk2-platforms 0/5] SynQuacer ACPI support Ard Biesheuvel 2018-02-27 9:20 ` [PATCH edk2-platforms 1/5] Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping Ard Biesheuvel 2018-02-27 9:20 ` [PATCH edk2-platforms 2/5] Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support Ard Biesheuvel @ 2018-02-27 9:20 ` Ard Biesheuvel 2018-02-27 9:20 ` [PATCH edk2-platforms 4/5] Silicon/SynQuacer/PlatformDxe: add option to enable ACPI mode Ard Biesheuvel 2018-02-27 9:20 ` [PATCH edk2-platforms 5/5] Silicon/SynQuacer/PlatformDxe: add ACPI description of eMMC Ard Biesheuvel 4 siblings, 0 replies; 14+ messages in thread From: Ard Biesheuvel @ 2018-02-27 9:20 UTC (permalink / raw) To: edk2-devel; +Cc: leif.lindholm, graeme.gregory, masahisa.kojima, Ard Biesheuvel Add the ACPI tables describing various parts of the SynQuacer SoC and its peripherals, and the drivers to expose them to the EvalBoard and DeveloperBox platforms. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 2 + Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 13 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 13 + Silicon/Socionext/SynQuacer/Acpi.dsc.inc | 48 ++++ Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl | 262 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h | 73 ++++++ Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf | 64 +++++ Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 187 ++++++++++++++ Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc | 91 +++++++ Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc | 93 +++++++ Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 101 ++++++++ Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc | 182 ++++++++++++++ Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc | 63 +++++ Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc | 128 ++++++++++ 15 files changed, 1322 insertions(+) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index 925ce36d278b..d2e358b7749d 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -686,3 +686,5 @@ [Components.common] MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf Platform/Socionext/DeveloperBox/OsInstallerMenuDxe/OsInstallerMenuDxe.inf + +!include Silicon/Socionext/SynQuacer/Acpi.dsc.inc diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf index edde1cfe3932..0d62f3d579cf 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf @@ -252,6 +252,13 @@ [FV.FvMain] INF Platform/Socionext/DeveloperBox/OsInstallerMenuDxe/OsInstallerMenuDxe.inf + # + # ACPI support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF RuleOverride = ACPITABLE Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf + !if $(DO_X86EMU) == TRUE # # x86 emulator @@ -489,3 +496,9 @@ [Rule.Common.PEIM.FMP_IMAGE_DESC] UI STRING="$(MODULE_NAME)" Optional VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index 2d5a94ed1dab..f2c6aa15fee4 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -638,3 +638,5 @@ [Components.common] MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf + +!include Silicon/Socionext/SynQuacer/Acpi.dsc.inc diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index ba2f32328c2b..20d19120d1b7 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -233,6 +233,13 @@ [FV.FvMain] SECTION UI = "Pkcs7TestRoot" } + # + # ACPI support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF RuleOverride = ACPITABLE Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf + [FV.FVMAIN_COMPACT] FvAlignment = 16 BlockSize = 0x10000 @@ -455,3 +462,9 @@ [Rule.Common.PEIM.FMP_IMAGE_DESC] UI STRING="$(MODULE_NAME)" Optional VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/Silicon/Socionext/SynQuacer/Acpi.dsc.inc b/Silicon/Socionext/SynQuacer/Acpi.dsc.inc new file mode 100644 index 000000000000..73a5ea40e313 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Acpi.dsc.inc @@ -0,0 +1,48 @@ +# +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials are licensed and made available +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + +[PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"SNI " + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x52434155514e5953 # SYNQUACR + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x20180226 + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c # LNRO + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ + +[Components.common] + # + # ACPI support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { + <LibraryClasses> + NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf + + <PcdsFixedAtBuild> + # support ACPI v5.0 or later + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + } + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl new file mode 100644 index 000000000000..1735264f09a3 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl @@ -0,0 +1,262 @@ +/** @file + Secondary System Description Table (SSDT) for SynQuacer PCIe RCs + + Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR> + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Platform/Pcie.h> + +#include "AcpiTables.h" + +DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR", + EFI_ACPI_OEM_REVISION) +{ + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, 0) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_CCA, 1) // Cache Coherency Attribute + + // PCI Routing Table + Name (_PRT, Package () { + Package () { 0xFFFF, 0, Zero, 222 }, // INTA + Package () { 0xFFFF, 1, Zero, 222 }, // INTB + Package () { 0xFFFF, 2, Zero, 222 }, // INTC + Package () { 0xFFFF, 3, Zero, 222 }, // INTD + }) + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + SYNQUACER_PCI_SEG0_BUSNUM_MIN, // Minimum Bus Number + SYNQUACER_PCI_SEG0_BUSNUM_MAX, // Maximum Bus Number + 0, // AddressTranslation + SYNQUACER_PCI_SEG0_BUSNUM_RANGE // RangeLength - # of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + SYNQUACER_PCI_SEG0_MMIO32_MIN, // Min Base Address + SYNQUACER_PCI_SEG0_MMIO32_MAX, // Max Base Address + 0x00000000, // Translate + SYNQUACER_PCI_SEG0_MMIO32_SIZE // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + SYNQUACER_PCI_SEG0_MMIO64_MIN, // Min Base Address + SYNQUACER_PCI_SEG0_MMIO64_MAX, // Max Base Address + 0x00000000, // Translate + SYNQUACER_PCI_SEG0_MMIO64_SIZE // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + SYNQUACER_PCI_OS_IO_BASE, // Min Base Address + SYNQUACER_PCI_OS_IO_LIMIT, // Max Base Address + SYNQUACER_PCI_SEG0_PORTIO_MEMBASE, // Translate + SYNQUACER_PCI_OS_IO_RANGE, // Length + , + , + , + TypeTranslation + ) + }) // Name (RBUF) + + Return (RBUF) + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + SYNQUACER_PCI_SEG0_CONFIG_BASE, + SYNQUACER_PCI_SEG0_CONFIG_SIZE) + }) + } + + // + // OS Control Handoff + // + Name (SUPP, Zero) // PCI _OSC Support Field value + Name (CTRL, Zero) // PCI _OSC Control Field value + + Method(_OSC,4) + { + // Check for proper UUID + If (LEqual (Arg0, ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3, 0, CDW1) + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // Save Capabilities DWord2 & 3 + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // Disable PCIe and SHPC hotplug, AER and PME + And (CTRL, 0x10, CTRL) + + // Capabilities bits were masked + Or (CDW1, 0x10, CDW1) + + // Update DWORD3 in the buffer + Store (CTRL, CDW3) + Return (Arg3) + } Else { + Or (CDW1, 4, CDW1) // Unrecognized UUID + Return (Arg3) + } + } // End _OSC + } // PCI0 + + Device (PCI1) + { + Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, 1) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_CCA, 1) // Cache Coherency Attribute + + // PCI Routing Table + Name (_PRT, Package () { + Package () { 0xFFFF, 0, Zero, 214 }, // INTA + Package () { 0xFFFF, 1, Zero, 214 }, // INTB + Package () { 0xFFFF, 2, Zero, 214 }, // INTC + Package () { 0xFFFF, 3, Zero, 214 }, // INTD + }) + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + SYNQUACER_PCI_SEG1_BUSNUM_MIN, // Minimum Bus Number + SYNQUACER_PCI_SEG1_BUSNUM_MAX, // Maximum Bus Number + 0, // AddressTranslation + SYNQUACER_PCI_SEG1_BUSNUM_RANGE // RangeLength - # of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + SYNQUACER_PCI_SEG1_MMIO32_MIN, // Min Base Address + SYNQUACER_PCI_SEG1_MMIO32_MAX, // Max Base Address + 0x00000000, // Translate + SYNQUACER_PCI_SEG1_MMIO32_SIZE // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + SYNQUACER_PCI_SEG1_MMIO64_MIN, // Min Base Address + SYNQUACER_PCI_SEG1_MMIO64_MAX, // Max Base Address + 0x00000000, // Translate + SYNQUACER_PCI_SEG1_MMIO64_SIZE // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + SYNQUACER_PCI_OS_IO_BASE, // Min Base Address + SYNQUACER_PCI_OS_IO_LIMIT, // Max Base Address + SYNQUACER_PCI_SEG1_PORTIO_MEMBASE, // Translate + SYNQUACER_PCI_OS_IO_RANGE, // Length + , + , + , + TypeTranslation + ) + }) // Name (RBUF) + + Return (RBUF) + } // Method(_CRS) + + Device (RES0) + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + SYNQUACER_PCI_SEG1_CONFIG_BASE, + SYNQUACER_PCI_SEG1_CONFIG_SIZE) + }) + } + + // + // OS Control Handoff + // + Name (SUPP, Zero) // PCI _OSC Support Field value + Name (CTRL, Zero) // PCI _OSC Control Field value + + Method(_OSC,4) + { + // Check for proper UUID + If (LEqual (Arg0, ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3, 0, CDW1) + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // Save Capabilities DWord2 & 3 + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // Disable PCIe and SHPC hotplug, AER and PME + And (CTRL, 0x10, CTRL) + + // Capabilities bits were masked + Or (CDW1, 0x10, CDW1) + + // Update DWORD3 in the buffer + Store (CTRL, CDW3) + Return (Arg3) + } Else { + Or (CDW1, 4, CDW1) // Unrecognized UUID + Return (Arg3) + } + } // End _OSC + } // PCI0 + } +} diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h new file mode 100644 index 000000000000..734a60a5b098 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h @@ -0,0 +1,73 @@ +/** @file +* +* Copyright (c) 2013-2014, ARM Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ACPITABLES_H__ +#define __ACPITABLES_H__ + +// +// ACPI table information used to initialize tables. +// +#define EFI_ACPI_OEM_ID 'S','N','I',' ',' ',' ' +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('S','Y','N','Q','U','A','C','R') +#define EFI_ACPI_OEM_REVISION FixedPcdGet32 (PcdAcpiDefaultOemRevision) +#define EFI_ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O') +#define EFI_ACPI_CREATOR_REVISION FixedPcdGet32 (PcdAcpiDefaultCreatorRevision) + +// A macro to initialise the common header part of EFI ACPI tables as defined by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define __ACPI_HEADER(Signature, Type, Revision) { \ + Signature, /* UINT32 Signature */ \ + sizeof (Type), /* UINT32 Length */ \ + Revision, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + { EFI_ACPI_OEM_ID }, /* UINT8 OemId[6] */ \ + EFI_ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + EFI_ACPI_OEM_REVISION, /* UINT32 OemRevision */ \ + EFI_ACPI_CREATOR_ID, /* UINT32 CreatorId */ \ + EFI_ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } + +#define EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \ + { \ + EFI_ACPI_6_0_GICR, \ + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), \ + 0, \ + RedisRegionAddr, \ + RedisDiscLength \ + } + +#define EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(Id, PhysAddress) \ + { \ + EFI_ACPI_6_0_GIC_ITS, \ + sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE), \ + 0, \ + Id, \ + PhysAddress, \ + 0 \ + } + +#define EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(RefreshFramePhys, \ + ControlFramePhys, WatchdogTimerGSIV, WatchdogTimerFlags) \ + { \ + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, \ + sizeof(EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), \ + EFI_ACPI_RESERVED_WORD, \ + RefreshFramePhys, \ + ControlFramePhys, \ + WatchdogTimerGSIV, \ + WatchdogTimerFlags \ + } + +#endif diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf new file mode 100644 index 000000000000..b1b6bbaa481d --- /dev/null +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf @@ -0,0 +1,64 @@ +## @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2014-2016, ARM Ltd. All rights reserved. +# Copyright (c) 2018, Linaro Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = SynQuacerAcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + AcpiTables.h + AcpiSsdtRootPci.asl + Dsdt.asl + Fadt.aslc + Gtdt.aslc + Iort.aslc + Madt.aslc + Mcfg.aslc + Spcr.aslc + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec + Silicon/Socionext/SynQuacer/SynQuacer.dec + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdClusterCount + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + + gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase + gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl new file mode 100644 index 000000000000..b6f6c4360029 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl @@ -0,0 +1,187 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2014-2016, ARM Ltd. All rights reserved.<BR> + Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR> + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "AcpiTables.h" + +#include <Platform/MemoryMap.h> + +DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", + EFI_ACPI_OEM_REVISION) { + Scope (_SB) { + // + // A53x4 Processor declaration + // + Device (CP00) { // A53-0: Cluster 0, Cpu 0 + Name (_HID, "ACPI0007") + Name (_UID, 0) + } + Device (CP01) { // A53-0: Cluster 0, Cpu 1 + Name (_HID, "ACPI0007") + Name (_UID, 1) + } + + Device (CP04) { // A53-0: Cluster 1, Cpu 0 + Name (_HID, "ACPI0007") + Name (_UID, 2) + } + Device (CP05) { // A53-0: Cluster 1, Cpu 1 + Name (_HID, "ACPI0007") + Name (_UID, 3) + } + + Device (CP08) { // A53-0: Cluster 2, Cpu 0 + Name (_HID, "ACPI0007") + Name (_UID, 4) + } + Device (CP09) { // A53-0: Cluster 2, Cpu 1 + Name (_HID, "ACPI0007") + Name (_UID, 5) + } + + Device (CP12) { // A53-0: Cluster 3, Cpu 0 + Name (_HID, "ACPI0007") + Name (_UID, 6) + } + Device (CP13) { // A53-0: Cluster 3, Cpu 1 + Name (_HID, "ACPI0007") + Name (_UID, 7) + } + + Device (CP16) { // A53-0: Cluster 4, Cpu 0 + Name (_HID, "ACPI0007") + Name (_UID, 8) + } + Device (CP17) { // A53-0: Cluster 4, Cpu 1 + Name (_HID, "ACPI0007") + Name (_UID, 9) + } + + Device (CP20) { // A53-0: Cluster 5, Cpu 0 + Name (_HID, "ACPI0007") + Name (_UID, 10) + } + Device (CP21) { // A53-0: Cluster 5, Cpu 1 + Name (_HID, "ACPI0007") + Name (_UID, 11) + } + + Device (CP24) { // A53-0: Cluster 6, Cpu 0 + Name (_HID, "ACPI0007") + Name (_UID, 12) + } + Device (CP25) { // A53-0: Cluster 6, Cpu 1 + Name (_HID, "ACPI0007") + Name (_UID, 13) + } + + Device (CP28) { // A53-0: Cluster 7, Cpu 0 + Name (_HID, "ACPI0007") + Name (_UID, 14) + } + Device (CP29) { // A53-0: Cluster 7, Cpu 1 + Name (_HID, "ACPI0007") + Name (_UID, 15) + } + + Device (CP32) { // A53-0: Cluster 8, Cpu 0 + Name (_HID, "ACPI0007") + Name (_UID, 16) + } + Device (CP33) { // A53-0: Cluster 8, Cpu 1 + Name (_HID, "ACPI0007") + Name (_UID, 17) + } + + Device (CP36) { // A53-0: Cluster 9, Cpu 0 + Name (_HID, "ACPI0007") + Name (_UID, 18) + } + Device (CP37) { // A53-0: Cluster 9, Cpu 1 + Name (_HID, "ACPI0007") + Name (_UID, 19) + } + + Device (CP40) { // A53-0: Cluster 10, Cpu 0 + Name (_HID, "ACPI0007") + Name (_UID, 20) + } + Device (CP41) { // A53-0: Cluster 10, Cpu 1 + Name (_HID, "ACPI0007") + Name (_UID, 21) + } + + Device (CP44) { // A53-0: Cluster 11, Cpu 0 + Name (_HID, "ACPI0007") + Name (_UID, 22) + } + Device (CP45) { // A53-0: Cluster 11, Cpu 1 + Name (_HID, "ACPI0007") + Name (_UID, 23) + } + + // UART PL011 + Device (COM0) { + Name (_HID, "ARMH0011") + Name (_CID, "PL011") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, FixedPcdGet32 (PcdSerialRegisterBase), 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 95 } + }) + } + + Device (NET0) { + Name (_HID, "SCX0001") + Name (_UID, Zero) + Name (_CCA, 1) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SYNQUACER_NETSEC1_BASE, + SYNQUACER_NETSEC1_BASE_SZ) + Memory32Fixed (ReadWrite, FixedPcdGet32 (PcdNetsecEepromBase), 0x10000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 208 } + }) + + Name (_DSD, Package () // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "phy-mode", "rgmii" }, + Package (2) { "phy-channel", FixedPcdGet32 (PcdNetsecPhyAddress) }, + Package (2) { "max-speed", 1000 }, + Package (2) { "max-frame-size", 9000 }, + Package (2) { "socionext,phy-clock-frequency", 125000000 }, + } + }) + } + + Device (I2C0) { + Name (_HID, "SCX0003") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SYNQUACER_I2C1_BASE, SYNQUACER_I2C1_SIZE) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 197 } + }) + + Name (_DSD, Package () // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "socionext,pclk-rate", 62500000 }, + } + }) + } + } // Scope (_SB) +} diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc b/Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc new file mode 100644 index 000000000000..0bc4c6a87b2c --- /dev/null +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc @@ -0,0 +1,91 @@ +/** @file +* Fixed ACPI Description Table (FADT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/AcpiLib.h> +#include <IndustryStandard/Acpi.h> + +#include "AcpiTables.h" + +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + __ACPI_HEADER ( + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + EFI_ACPI_6_0_HW_REDUCED_ACPI | + EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // GAS ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, + // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // GAS XPm1aEvtBlk + NULL_GAS, // GAS XPm1bEvtBlk + NULL_GAS, // GAS XPm1aCntBlk + NULL_GAS, // GAS XPm1bCntBlk + NULL_GAS, // GAS XPm2CntBlk + NULL_GAS, // GAS XPmTmrBlk + NULL_GAS, // GAS XGpe0Blk + NULL_GAS, // GAS XGpe1Blk + NULL_GAS, // GAS SleepControlReg + NULL_GAS, // GAS SleepStatusReg + 0 // UINT64 HypervisorVendorId +}; + +// +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc b/Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc new file mode 100644 index 000000000000..b7391990944f --- /dev/null +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc @@ -0,0 +1,93 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/AcpiLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h> + +#include "AcpiTables.h" + +#define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF + +#define GTDT_GLOBAL_FLAGS 0 +#define GTDT_GTIMER_FLAGS EFI_ACPI_6_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY + +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE TimerBase; + EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE TimerFrame; + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdog; +} EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES; + +#pragma pack () + +EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { + { + __ACPI_HEADER( + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress + 2, // UINT32 PlatformTimerCount + sizeof (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + }, + { + EFI_ACPI_6_0_GTDT_GT_BLOCK, // UINT8 Type + sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE) + + sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE), + // UINT16 Length + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved + 0x2A810000, // UINT64 CntCtlBase + 1, // UINT32 GTBlockTimerCount + sizeof (EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE) // UINT32 GTBlockTimerOffset + }, + { + 0, // UINT8 GTFrameNumber + {0, 0, 0}, // UINT8 Reserved[3] + 0x2A830000, // UINT64 CntBaseX + 0xFFFFFFFFFFFFFFFF, // UINT64 CntEL0BaseX + 92, // UINT32 GTxPhysicalTimerGSIV + 0, // UINT32 GTxPhysicalTimerFlags + 0, // UINT32 GTxVirtualTimerGSIV + 0, // UINT32 GTxVirtualTimerFlags + EFI_ACPI_6_0_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY + // UINT32 GTxCommonFlags + }, + EFI_ACPI_6_0_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT ( + FixedPcdGet32 (PcdGenericWatchdogRefreshBase), + FixedPcdGet32 (PcdGenericWatchdogControlBase), + 94, + 0), +}; + +// +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt; diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc new file mode 100644 index 000000000000..a40dd9d1f053 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc @@ -0,0 +1,101 @@ +/** @file + + Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR> + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <IndustryStandard/IoRemappingTable.h> + +#include "AcpiTables.h" + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Node; + UINT32 Identifiers[1]; +} SYNQUACER_ITS_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; +} SYNQUACER_RC_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; + SYNQUACER_ITS_NODE ItsNode; + SYNQUACER_RC_NODE RcNode; +} SYNQUACER_IO_REMAPPING_STRUCTURE; + +#define __SYNQUACER_ID_MAPPING(In, Num, Out, Ref, Flags) \ + { \ + In, \ + Num, \ + Out, \ + FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, Ref), \ + Flags \ + } + +STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = { + { + __ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, + SYNQUACER_IO_REMAPPING_STRUCTURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION), + 2, // NumNodes + sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset + 0 // Reserved + }, { + // ItsNode + { + { + EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type + sizeof(SYNQUACER_ITS_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x0, // NumIdMappings + 0x0, // IdReference + }, + 1, + }, { + 0x0 + }, + }, { + // PciRcNode + { + { + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type + sizeof(SYNQUACER_RC_NODE), // Length + 0x0, // Revision + 0x0, // Reserved + 0x1, // NumIdMappings + FIELD_OFFSET(SYNQUACER_RC_NODE, RcIdMapping), // IdReference + }, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent + 0x0, // AllocationHints + 0x0, // Reserved + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, // MemoryAccessFlags + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute + 0x1, // PciSegmentNumber + }, + // + // The SynQuacer pre-ITS cannot be modeled in ACPI, and all accesses to the + // GICv3 ITS doorbell register are reported as originating from device ID #0 + // So map all requester IDs to device ID #0 + // + __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE), + } +}; + +#pragma pack() + +VOID* CONST ReferenceAcpiTable = &Iort; diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc b/Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc new file mode 100644 index 000000000000..6bbf216d80d2 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc @@ -0,0 +1,182 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> +#include <IndustryStandard/Acpi.h> + +#include "AcpiTables.h" + +#define CORES (FixedPcdGet32 (PcdClusterCount) * \ + FixedPcdGet32 (PcdCoreCount)) +// +// Multiple APIC Description Table +// +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_0_GIC_STRUCTURE GicInterfaces[CORES]; + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_0_GICR_STRUCTURE GicRedistributor; + EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicIts; +} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + __ACPI_HEADER ( + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + // Format: EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, + // PmuIrq, GicBase, GicVBase, + // GicHBase, GsivId, GicRBase) + // Note: The GIC Structure of the primary CPU must be the first entry + // (see note in 5.2.12.14 GICC Structure of ACPI v6.0). + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-0 + 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-1 + 0, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-2 + 0, 2, GET_MPID(1, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-3 + 0, 3, GET_MPID(1, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-4 + 0, 4, GET_MPID(2, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-5 + 0, 5, GET_MPID(2, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-6 + 0, 6, GET_MPID(3, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-7 + 0, 7, GET_MPID(3, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-8 + 0, 8, GET_MPID(4, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-9 + 0, 9, GET_MPID(4, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-10 + 0, 10, GET_MPID(5, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-11 + 0, 11, GET_MPID(5, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-12 + 0, 12, GET_MPID(6, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-13 + 0, 13, GET_MPID(6, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-14 + 0, 14, GET_MPID(7, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-15 + 0, 15, GET_MPID(7, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-16 + 0, 16, GET_MPID(8, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-17 + 0, 17, GET_MPID(8, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-18 + 0, 18, GET_MPID(9, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-19 + 0, 19, GET_MPID(9, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-20 + 0, 20, GET_MPID(10, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-21 + 0, 21, GET_MPID(10, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-22 + 0, 22, GET_MPID(11, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A53-23 + 0, 23, GET_MPID(11, 1), EFI_ACPI_6_0_GIC_ENABLED, 23, + FixedPcdGet32 (PcdGicDistributorBase), + 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */), + }, + // GIC Distributor Entry + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (0, FixedPcdGet32 (PcdGicDistributorBase), + 0, 3), + // GIC Redistributor + EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT (FixedPcdGet32 (PcdGicRedistributorsBase), + 0x300000), + // GIC ITS + EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(0, 0x30020000) +}; + +// +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc b/Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc new file mode 100644 index 000000000000..089b9e95aff2 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc @@ -0,0 +1,63 @@ +/** @file + + ACPI Memory mapped configuration space base address Description Table (MCFG). + Implementation based on PCI Firmware Specification Revision 3.0 final draft, + downloadable at http://www.pcisig.com/home + + Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. + Copyright (c) 2018, Linaro Limited. All rights reserved. + + This program and the accompanying materials are licensed and + made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the + license may be found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <IndustryStandard/Acpi61.h> +#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h> +#include <Platform/Pcie.h> + +#include "AcpiTables.h" + +#pragma pack(push, 1) + +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[2]; +} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE; + +EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = { + { + __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION), + EFI_ACPI_RESERVED_QWORD + }, + { + { + SYNQUACER_PCI_SEG0_CONFIG_BASE, + 0, + SYNQUACER_PCI_SEG0_BUSNUM_MIN, + SYNQUACER_PCI_SEG0_BUSNUM_MAX, + EFI_ACPI_RESERVED_DWORD + }, { + SYNQUACER_PCI_SEG1_CONFIG_BASE, + 1, + SYNQUACER_PCI_SEG1_BUSNUM_MIN, + SYNQUACER_PCI_SEG1_BUSNUM_MAX, + EFI_ACPI_RESERVED_DWORD + } + } +}; + +#pragma pack(pop) + +// +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc b/Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc new file mode 100644 index 000000000000..699e79e1bf59 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc @@ -0,0 +1,128 @@ +/** @file + + Serial Port Console Redirection Table + (c) 2000 - 2014 Microsoft Corporation. All rights reserved. + http://go.microsoft.com/fwlink/?linkid=403368 + + Copyright (c) 2014 - 2016, AMD Inc. All rights reserved. + Copyright (c) 2018, Linaro Ltd. All rights reserved. + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <IndustryStandard/Acpi61.h> +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h> + +#include "AcpiTables.h" + +#pragma pack(push, 1) + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { + // + // Header + // + __ACPI_HEADER (EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + 2), /* New MS definition for PL011 support */ + // + // InterfaceType + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART, + // + // Reserved[3] + // + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, + // + // BaseAddress + // + { + EFI_ACPI_5_1_SYSTEM_MEMORY, + 32, + 0, + EFI_ACPI_5_1_DWORD, + FixedPcdGet32 (PcdSerialRegisterBase) + }, + // + // InterruptType + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, + // + // Irq + // + 0, + // + // GlobalSystemInterrupt + // + 95, + // + // BaudRate + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, + // + // Parity + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + // + // StopBits + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + // + // FlowControl + // + 0, + // + // TerminalType + // + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, + // + // Language + // + EFI_ACPI_RESERVED_BYTE, + // + // PciDeviceId + // + 0xFFFF, + // + // PciVendorId + // + 0xFFFF, + // + // PciBusNumber + // + 0x00, + // + // PciDeviceNumber + // + 0x00, + // + // PciFunctionNumber + // + 0x00, + // + // PciFlags + // + 0, + // + // PciSegment + // + 0, + // + // Reserved2 + // + EFI_ACPI_RESERVED_DWORD +}; + +#pragma pack(pop) + +// +// Reference the table being generated to prevent the optimizer from removing +// the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Spcr; -- 2.11.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms 4/5] Silicon/SynQuacer/PlatformDxe: add option to enable ACPI mode 2018-02-27 9:20 [PATCH edk2-platforms 0/5] SynQuacer ACPI support Ard Biesheuvel ` (2 preceding siblings ...) 2018-02-27 9:20 ` [PATCH edk2-platforms 3/5] Silicon/SynQuacer: add ACPI drivers and tables Ard Biesheuvel @ 2018-02-27 9:20 ` Ard Biesheuvel 2018-02-28 16:32 ` Leif Lindholm 2018-02-27 9:20 ` [PATCH edk2-platforms 5/5] Silicon/SynQuacer/PlatformDxe: add ACPI description of eMMC Ard Biesheuvel 4 siblings, 1 reply; 14+ messages in thread From: Ard Biesheuvel @ 2018-02-27 9:20 UTC (permalink / raw) To: edk2-devel; +Cc: leif.lindholm, graeme.gregory, masahisa.kojima, Ard Biesheuvel Create a HII menu option to choose between device tree and ACPI platform descriptions. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 32 ++++++++++++++------ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 1 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni | 8 ++++- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr | 10 +++++- Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h | 8 +++-- 5 files changed, 46 insertions(+), 13 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index 8787aa6288a7..4ae1c5b0ff6f 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -277,15 +277,29 @@ PlatformDxeEntryPoint ( mHiiSettingsVal = PcdGet64 (PcdPlatformSettings); mHiiSettings = (SYNQUACER_PLATFORM_VARSTORE_DATA *)&mHiiSettingsVal; - Dtb = NULL; - Status = DtPlatformLoadDtb (&Dtb, &DtbSize); - if (!EFI_ERROR (Status)) { - Status = gBS->InstallConfigurationTable (&gFdtTableGuid, Dtb); - } - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, - "%a: failed to install FDT configuration table - %r\n", __FUNCTION__, - Status)); + if (mHiiSettings->AcpiPref == ACPIPREF_DT) { + Dtb = NULL; + Status = DtPlatformLoadDtb (&Dtb, &DtbSize); + if (!EFI_ERROR (Status)) { + Status = gBS->InstallConfigurationTable (&gFdtTableGuid, Dtb); + } + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: failed to install FDT configuration table - %r\n", __FUNCTION__, + Status)); + } + } else { + // + // ACPI was selected: install the gEdkiiPlatformHasAcpiGuid GUID as a + // NULL protocol to unlock dispatch of ACPI related drivers. + // + Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle, + &gEdkiiPlatformHasAcpiGuid, NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: failed to install gEdkiiPlatformHasAcpiGuid as a protocol\n", + __FUNCTION__)); + } } Handle = NULL; diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index fca66799ebcb..bef7feccd8b8 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -58,6 +58,7 @@ [LibraryClasses] [Guids] g96BoardsI2c0MasterGuid + gEdkiiPlatformHasAcpiGuid gEfiHiiPlatformSetupFormsetGuid gFdtTableGuid gNetsecNonDiscoverableDeviceGuid diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni index 2eca8bbba8c3..836decc870f0 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* Copyright (c) 2017 - 2018, Linaro, Ltd. All rights reserved. * * This program and the accompanying materials are licensed and made available * under the terms and conditions of the BSD License which accompanies this @@ -33,3 +33,9 @@ #string STR_EMMC_DISABLED #language en-US "Disabled" #string STR_EMMC_ENABLED #language en-US "Enabled" + +#string STR_DT_ACPI_SELECT_PROMPT #language en-US "O/S Hardware Description" +#string STR_DT_ACPI_SELECT_HELP #language en-US "Select the hardware description that will be exposed to the O/S." + +#string STR_DT_ACPI_SELECT_DT #language en-US "Device Tree" +#string STR_DT_ACPI_SELECT_ACPI #language en-US "ACPI" diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr index ea35e902b2d7..8a395eac681b 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* Copyright (c) 2017 - 2018, Linaro, Ltd. All rights reserved. * * This program and the accompanying materials are licensed and made available * under the terms and conditions of the BSD License which accompanies this @@ -70,6 +70,14 @@ formset option text = STRING_TOKEN(STR_EMMC_ENABLED), value = EMMC_ENABLED, flags = 0; endoneof; + oneof varid = SynQuacerPlatformSettings.AcpiPref, + prompt = STRING_TOKEN(STR_DT_ACPI_SELECT_PROMPT), + help = STRING_TOKEN(STR_DT_ACPI_SELECT_HELP), + flags = NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED, + option text = STRING_TOKEN(STR_DT_ACPI_SELECT_DT), value = ACPIPREF_DT, flags = DEFAULT; + option text = STRING_TOKEN(STR_DT_ACPI_SELECT_ACPI), value = ACPIPREF_ACPI, flags = 0; + endoneof; + subtitle text = STRING_TOKEN(STR_NULL_STRING); endform; diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h b/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h index fbbcbd7d3eec..bb0e476fc3f8 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR> + Copyright (c) 2017 - 2018, Linaro, Ltd. All rights reserved.<BR> This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this @@ -22,12 +22,16 @@ #define PCIE_MAX_SPEED_UNLIMITED 0x0 #define PCIE_MAX_SPEED_GEN1 0x1 +#define ACPIPREF_DT 0x0 +#define ACPIPREF_ACPI 0x1 + typedef struct { UINT8 EnableEmmc; UINT8 PcieSlot0MaxSpeed; UINT8 PcieSlot1MaxSpeed; UINT8 PcieSlot2MaxSpeed; - UINT8 Reserved[4]; + UINT8 AcpiPref; + UINT8 Reserved[3]; } SYNQUACER_PLATFORM_VARSTORE_DATA; #endif -- 2.11.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH edk2-platforms 4/5] Silicon/SynQuacer/PlatformDxe: add option to enable ACPI mode 2018-02-27 9:20 ` [PATCH edk2-platforms 4/5] Silicon/SynQuacer/PlatformDxe: add option to enable ACPI mode Ard Biesheuvel @ 2018-02-28 16:32 ` Leif Lindholm 0 siblings, 0 replies; 14+ messages in thread From: Leif Lindholm @ 2018-02-28 16:32 UTC (permalink / raw) To: Ard Biesheuvel; +Cc: edk2-devel, graeme.gregory, masahisa.kojima On Tue, Feb 27, 2018 at 09:20:16AM +0000, Ard Biesheuvel wrote: > Create a HII menu option to choose between device tree and ACPI platform > descriptions. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> > --- > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 32 ++++++++++++++------ > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 1 + > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni | 8 ++++- > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr | 10 +++++- > Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h | 8 +++-- > 5 files changed, 46 insertions(+), 13 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c > index 8787aa6288a7..4ae1c5b0ff6f 100644 > --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c > +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c > @@ -277,15 +277,29 @@ PlatformDxeEntryPoint ( > mHiiSettingsVal = PcdGet64 (PcdPlatformSettings); > mHiiSettings = (SYNQUACER_PLATFORM_VARSTORE_DATA *)&mHiiSettingsVal; > > - Dtb = NULL; > - Status = DtPlatformLoadDtb (&Dtb, &DtbSize); > - if (!EFI_ERROR (Status)) { > - Status = gBS->InstallConfigurationTable (&gFdtTableGuid, Dtb); > - } > - if (EFI_ERROR (Status)) { > - DEBUG ((DEBUG_ERROR, > - "%a: failed to install FDT configuration table - %r\n", __FUNCTION__, > - Status)); > + if (mHiiSettings->AcpiPref == ACPIPREF_DT) { > + Dtb = NULL; > + Status = DtPlatformLoadDtb (&Dtb, &DtbSize); > + if (!EFI_ERROR (Status)) { > + Status = gBS->InstallConfigurationTable (&gFdtTableGuid, Dtb); > + } > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, > + "%a: failed to install FDT configuration table - %r\n", __FUNCTION__, > + Status)); > + } > + } else { > + // > + // ACPI was selected: install the gEdkiiPlatformHasAcpiGuid GUID as a > + // NULL protocol to unlock dispatch of ACPI related drivers. > + // > + Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle, > + &gEdkiiPlatformHasAcpiGuid, NULL, NULL); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, > + "%a: failed to install gEdkiiPlatformHasAcpiGuid as a protocol\n", > + __FUNCTION__)); > + } > } > > Handle = NULL; > diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf > index fca66799ebcb..bef7feccd8b8 100644 > --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf > +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf > @@ -58,6 +58,7 @@ [LibraryClasses] > > [Guids] > g96BoardsI2c0MasterGuid > + gEdkiiPlatformHasAcpiGuid > gEfiHiiPlatformSetupFormsetGuid > gFdtTableGuid > gNetsecNonDiscoverableDeviceGuid > diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni > index 2eca8bbba8c3..836decc870f0 100644 > --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni > +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni > @@ -1,6 +1,6 @@ > /** @file > * > -* Copyright (c) 2017, Linaro, Ltd. All rights reserved. > +* Copyright (c) 2017 - 2018, Linaro, Ltd. All rights reserved. > * > * This program and the accompanying materials are licensed and made available > * under the terms and conditions of the BSD License which accompanies this > @@ -33,3 +33,9 @@ > > #string STR_EMMC_DISABLED #language en-US "Disabled" > #string STR_EMMC_ENABLED #language en-US "Enabled" > + > +#string STR_DT_ACPI_SELECT_PROMPT #language en-US "O/S Hardware Description" > +#string STR_DT_ACPI_SELECT_HELP #language en-US "Select the hardware description that will be exposed to the O/S." > + > +#string STR_DT_ACPI_SELECT_DT #language en-US "Device Tree" > +#string STR_DT_ACPI_SELECT_ACPI #language en-US "ACPI" > diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr > index ea35e902b2d7..8a395eac681b 100644 > --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr > +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr > @@ -1,6 +1,6 @@ > /** @file > * > -* Copyright (c) 2017, Linaro, Ltd. All rights reserved. > +* Copyright (c) 2017 - 2018, Linaro, Ltd. All rights reserved. > * > * This program and the accompanying materials are licensed and made available > * under the terms and conditions of the BSD License which accompanies this > @@ -70,6 +70,14 @@ formset > option text = STRING_TOKEN(STR_EMMC_ENABLED), value = EMMC_ENABLED, flags = 0; > endoneof; > > + oneof varid = SynQuacerPlatformSettings.AcpiPref, > + prompt = STRING_TOKEN(STR_DT_ACPI_SELECT_PROMPT), > + help = STRING_TOKEN(STR_DT_ACPI_SELECT_HELP), > + flags = NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED, > + option text = STRING_TOKEN(STR_DT_ACPI_SELECT_DT), value = ACPIPREF_DT, flags = DEFAULT; > + option text = STRING_TOKEN(STR_DT_ACPI_SELECT_ACPI), value = ACPIPREF_ACPI, flags = 0; > + endoneof; > + > subtitle text = STRING_TOKEN(STR_NULL_STRING); > > endform; > diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h b/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h > index fbbcbd7d3eec..bb0e476fc3f8 100644 > --- a/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h > +++ b/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h > @@ -1,6 +1,6 @@ > /** @file > > - Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR> > + Copyright (c) 2017 - 2018, Linaro, Ltd. All rights reserved.<BR> > > This program and the accompanying materials are licensed and made available > under the terms and conditions of the BSD License which accompanies this > @@ -22,12 +22,16 @@ > #define PCIE_MAX_SPEED_UNLIMITED 0x0 > #define PCIE_MAX_SPEED_GEN1 0x1 > > +#define ACPIPREF_DT 0x0 > +#define ACPIPREF_ACPI 0x1 > + > typedef struct { > UINT8 EnableEmmc; > UINT8 PcieSlot0MaxSpeed; > UINT8 PcieSlot1MaxSpeed; > UINT8 PcieSlot2MaxSpeed; > - UINT8 Reserved[4]; > + UINT8 AcpiPref; > + UINT8 Reserved[3]; > } SYNQUACER_PLATFORM_VARSTORE_DATA; > > #endif > -- > 2.11.0 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH edk2-platforms 5/5] Silicon/SynQuacer/PlatformDxe: add ACPI description of eMMC 2018-02-27 9:20 [PATCH edk2-platforms 0/5] SynQuacer ACPI support Ard Biesheuvel ` (3 preceding siblings ...) 2018-02-27 9:20 ` [PATCH edk2-platforms 4/5] Silicon/SynQuacer/PlatformDxe: add option to enable ACPI mode Ard Biesheuvel @ 2018-02-27 9:20 ` Ard Biesheuvel 4 siblings, 0 replies; 14+ messages in thread From: Ard Biesheuvel @ 2018-02-27 9:20 UTC (permalink / raw) To: edk2-devel; +Cc: leif.lindholm, graeme.gregory, masahisa.kojima, Ard Biesheuvel Expose a separate ACPI description of the SynQuacer eMMC controller when both ACPI and eMMC support have been enabled in the HII menu. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 1 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 1 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl | 41 +++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 55 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 4 ++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 4 ++ 6 files changed, 106 insertions(+) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf index 0d62f3d579cf..2be549027268 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf @@ -447,6 +447,7 @@ [Rule.Common.DXE_DRIVER] PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING="$(MODULE_NAME)" Optional RAW BIN Optional |.dtb + RAW ASL Optional |.aml } [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index 20d19120d1b7..3f47781fe979 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -419,6 +419,7 @@ [Rule.Common.DXE_DRIVER] DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING="$(MODULE_NAME)" Optional + RAW ASL Optional |.aml } [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl new file mode 100644 index 000000000000..4e371befc7b5 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl @@ -0,0 +1,41 @@ +/** @file + SSDT describing the SynQuacer eMMC controller + + Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR> + + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Platform/MemoryMap.h> + +DefinitionBlock ("SsdtEmmc.aml", "SSDT", 1, "SNI", "SynQeMMC", + FixedPcdGet32 (PcdAcpiDefaultOemRevision)) { + Scope (_SB) { + Device (MMC0) { + Name (_HID, "SCX0002") + Name (_UID, Zero) + Name (_CCA, 1) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SYNQUACER_EMMC_BASE, SYNQUACER_EMMC_BASE_SZ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 184 } + }) + + Name (_DSD, Package () // _DSD: Device-Specific Data + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "bus-width", 8 }, + Package (2) { "cap-mmc-highspeed", 0x1 }, + Package (2) { "fujitsu,cmd-dat-delay-select", 0x1 }, + } + }) + } + } // Scope (_SB) +} diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c index 7284ea6a7cee..e0987c954c74 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c @@ -59,6 +59,10 @@ STATIC EFI_HANDLE mSdMmcControllerHandle; +STATIC EFI_ACPI_DESCRIPTION_HEADER *mSsdt; +STATIC UINTN mSsdtSize; +STATIC VOID *mEventRegistration; + /** Override function for SDHCI capability bits @@ -182,6 +186,31 @@ STATIC EDKII_SD_MMC_OVERRIDE mSdMmcOverride = { SynQuacerSdMmcNotifyPhase, }; +STATIC +VOID +EFIAPI +InstallAcpiTable ( + IN EFI_EVENT Event, + IN VOID* Context + ) +{ + UINTN TableKey; + EFI_STATUS Status; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + + Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, + (VOID **)&AcpiTable); + if (EFI_ERROR (Status)) { + return; + } + + Status = AcpiTable->InstallAcpiTable (AcpiTable, mSsdt, mSsdtSize, &TableKey); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to install SSDT table for eMMC - %r\n", + __FUNCTION__, Status)); + } +} + EFI_STATUS EFIAPI RegisterEmmc ( @@ -190,6 +219,32 @@ RegisterEmmc ( { EFI_STATUS Status; EFI_HANDLE Handle; + UINTN Index; + + if (mHiiSettings->AcpiPref == ACPIPREF_ACPI) { + // + // Load the SSDT table from a raw section in this FFS file. + // + for (Index = 0;; Index++) { + Status = GetSectionFromFv (&gEfiCallerIdGuid, EFI_SECTION_RAW, Index, + (VOID **)&mSsdt, &mSsdtSize); + if (EFI_ERROR (Status)) { + break; + } + + if (mSsdt->OemTableId != EMMC_TABLE_ID) { + continue; + } + + // + // Register for the ACPI table protocol + // + EfiCreateProtocolNotifyEvent (&gEfiAcpiTableProtocolGuid, TPL_CALLBACK, + InstallAcpiTable, NULL, &mEventRegistration); + + break; + } + } Status = RegisterNonDiscoverableMmioDevice ( NonDiscoverableDeviceTypeSdhci, diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h index a391d2f67c29..c25b7f168a37 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h @@ -24,6 +24,7 @@ #include <Library/DebugLib.h> #include <Library/DevicePathLib.h> #include <Library/DtPlatformDtbLoaderLib.h> +#include <Library/DxeServicesLib.h> #include <Library/HiiLib.h> #include <Library/IoLib.h> #include <Library/MemoryAllocationLib.h> @@ -35,10 +36,13 @@ #include <Platform/MemoryMap.h> #include <Platform/Pcie.h> #include <Platform/VarStore.h> +#include <Protocol/AcpiTable.h> #include <Protocol/NonDiscoverableDevice.h> #include <Protocol/PciIo.h> #include <Protocol/SdMmcOverride.h> +#define EMMC_TABLE_ID SIGNATURE_64('S','y','n','Q','e','M','M','C') + extern UINT8 PlatformDxeHiiBin[]; extern UINT8 PlatformDxeStrings[]; diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index bef7feccd8b8..8df3073bf24b 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -23,6 +23,7 @@ [Defines] ENTRY_POINT = PlatformDxeEntryPoint [Sources] + Emmc.asl Emmc.c Pci.c PlatformDxe.c @@ -46,6 +47,7 @@ [LibraryClasses] DebugLib DevicePathLib DtPlatformDtbLoaderLib + DxeServicesLib HiiLib IoLib MemoryAllocationLib @@ -69,10 +71,12 @@ [Guids] [Protocols] gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES gEdkiiSdMmcOverrideProtocolGuid ## PRODUCES + gEfiAcpiTableProtocolGuid ## CONSUMES gEfiPciIoProtocolGuid ## CONSUMES gPcf8563RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES [FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress -- 2.11.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
end of thread, other threads:[~2018-02-28 16:40 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-02-27 9:20 [PATCH edk2-platforms 0/5] SynQuacer ACPI support Ard Biesheuvel 2018-02-27 9:20 ` [PATCH edk2-platforms 1/5] Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping Ard Biesheuvel 2018-02-28 16:17 ` Leif Lindholm 2018-02-28 16:18 ` Ard Biesheuvel 2018-02-28 16:39 ` Leif Lindholm 2018-02-27 9:20 ` [PATCH edk2-platforms 2/5] Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support Ard Biesheuvel 2018-02-28 16:26 ` Leif Lindholm 2018-02-28 16:30 ` Ard Biesheuvel 2018-02-28 16:43 ` Leif Lindholm 2018-02-28 16:46 ` Ard Biesheuvel 2018-02-27 9:20 ` [PATCH edk2-platforms 3/5] Silicon/SynQuacer: add ACPI drivers and tables Ard Biesheuvel 2018-02-27 9:20 ` [PATCH edk2-platforms 4/5] Silicon/SynQuacer/PlatformDxe: add option to enable ACPI mode Ard Biesheuvel 2018-02-28 16:32 ` Leif Lindholm 2018-02-27 9:20 ` [PATCH edk2-platforms 5/5] Silicon/SynQuacer/PlatformDxe: add ACPI description of eMMC Ard Biesheuvel
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