From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8751C22402E11 for ; Wed, 28 Feb 2018 08:33:46 -0800 (PST) Received: by mail-wm0-x244.google.com with SMTP id w128so6290073wmw.0 for ; Wed, 28 Feb 2018 08:39:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=ScpJG8dDiFNL7DTeJisvw5gBx9K6FNzreHARu3eogaA=; b=jHYj2UIU5Wp2G6magpsTTR0gENSYDmXlpVcpajWPsx1vUzAyEPA5AaUNKjCoItT28u imla+iFnsvlMCqzR9pSsPgBvxa+hWL5b9eRjpnVSAK1C9fy5Q0IbDRSiJo6NEWcslhVi B1+GFvvXXaz1sCtGpJXNQm9RO2MU55zImVinc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=ScpJG8dDiFNL7DTeJisvw5gBx9K6FNzreHARu3eogaA=; b=fbDgO9Jv16OUrO6+ZCnVTL8RRbb+7LPATN7D6wNNQCbMariILiGO5Hz0rzY9l7vu7P nHn3xGxuq5B70RQkV4NhauSqR5wb2D30EVRmZIGkW4xmHtPMxtS/Y5q+BC0f6wQMzdXF rRk/u4sYpL6JYRaSMPWHaETTmnTztlRQDtwJ8TxYRxq6GyNH2hJvz/am+xO1ZpK8uuoE IXQiuM51F/aagB3uqRkNSkC3PswynIPwxKv4Vl+5FURiPNrgHfOTSNyBBImdM2kK9iuG U8ROA7Bpx2B0jbmy+lHYZ521hlbawYleTJBmzSUXgvdExeFSPDsnrVwdpc/8Ajd+ZAd+ oUCw== X-Gm-Message-State: APf1xPDPY+ydD5PgQcQIw9pD5tbDk2pwM4A7aQ/GttveAuLe1AaE05WT NbJOj9QqvJkB6JzT7WMoN2fz0g== X-Google-Smtp-Source: AH8x226LLv8SM6NkP0HIAZWyOPkkzmlamRP8pFGDRVkWzfHrKG94fP8BblpnrPpW7WjMDarwNkOkMw== X-Received: by 10.28.148.130 with SMTP id w124mr14852135wmd.124.1519835992477; Wed, 28 Feb 2018 08:39:52 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id s21sm1382398wra.45.2018.02.28.08.39.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 08:39:51 -0800 (PST) Date: Wed, 28 Feb 2018 16:39:50 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: "edk2-devel@lists.01.org" , Graeme Gregory , Masahisa Kojima Message-ID: <20180228163950.nw6p5q5gwyxwudtc@bivouac.eciton.net> References: <20180227092017.23617-1-ard.biesheuvel@linaro.org> <20180227092017.23617-2-ard.biesheuvel@linaro.org> <20180228161750.4h5fx4yxfocujfob@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 1/5] Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Feb 2018 16:33:47 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Feb 28, 2018 at 04:18:50PM +0000, Ard Biesheuvel wrote: > On 28 February 2018 at 16:17, Leif Lindholm wrote: > > On Tue, Feb 27, 2018 at 09:20:13AM +0000, Ard Biesheuvel wrote: > >> Fix the static B/D/F specifiers that refer to the pair of x1 PCIe slots > >> on the DeveloperBox PCB. > > > > What is the user-observable problem that is addressed by this patch? > > That limiting the speed of slot 1 affects slot 2 Could you add that to the commit message please? Something like "The current configuration caused user-configurable settings for slots 1/2 to apply to the incorrect one.". > >> Contributed-under: TianoCore Contribution Agreement 1.1 > >> Signed-off-by: Ard Biesheuvel > >> --- > >> Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 4 ++-- > >> 1 file changed, 2 insertions(+), 2 deletions(-) > >> > >> diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > >> index ee2357be9a06..2d3d5cd91be0 100644 > >> --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > >> +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > >> @@ -62,7 +62,7 @@ > >> > >> #define SYNQUACER_PCI_LOCATION(s,b,d) (((s) << 16) | ((b) << 8) | (d)) > >> #define SYNQUACER_PCI_SLOT0_LOCATION SYNQUACER_PCI_LOCATION(1, 0, 0) > >> -#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) > >> -#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) > >> +#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) > >> +#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) > >> > >> #endif > >> -- > >> 2.11.0 > >>