From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7752722352288 for ; Wed, 28 Feb 2018 11:18:30 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id f14so3616645wre.8 for ; Wed, 28 Feb 2018 11:24:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Zy0Ia3ygcecFtPlfGbwDqMjGGjAD1cQ4HvaBG4yB6gQ=; b=Ygz6TttS9u0NYnvvyxbHh1lvOXiaG3GNCFoJ/94x99Wr+fPwKL239WHAK6lQxeKd2V o/RQlB4UpFlIUgFX6dP+TDZJ4OqYAF+c3/8yWr6viDOsvFiLegDuywXPDSvfippLb3XK P6tlewVM3JINdNF6Sb0EOA9RzIz/oYA/Fbc24= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Zy0Ia3ygcecFtPlfGbwDqMjGGjAD1cQ4HvaBG4yB6gQ=; b=QlgWRW8vXgCkykuF7EWILFyzIEA9qtaUedNiVyqmRSVDo6A4yUKPnC3NIxF9xk3BOa Bjs+EYEpmUAplw1eHx0yawVOMXESPG/ElAlJFA7CDbqfKLgJDxzHXAwsvmsTQBQrSNbH ycp01jgZv0iUTm7wpVNG2AYcCh2Ugp72S8P6yCAcsdvKTajRzlvbuEfvKQjLwKYbOP/W sFrN1Vj4h+x+lEFdTa0/knmqFEECUpledF6c0U9JsdeQukvvCFBNnioAeKx4mQANxGaK lESM2Zf8xcPWOQZqrsX8WnrAzzqMbCIhal3kHzTeoQgHjY28lQwFe14CPeO/wFZjCdch oLog== X-Gm-Message-State: APf1xPCD1yTPhnbZ+NqSyZLW+nsGW1XFOoyrrMnvLXtPPRHRloiPrwTR Hd81JeQzDG2/zndt/bo1MsmNxcVJA0A= X-Google-Smtp-Source: AG47ELt5hIRDs47Owbf9l2OQfF10BukCxr/jGFSUL4rCAilmP76saFLoxh0BdFmPV208uz8BeLxEpw== X-Received: by 10.223.182.2 with SMTP id f2mr10792611wre.117.1519845876465; Wed, 28 Feb 2018 11:24:36 -0800 (PST) Received: from localhost.localdomain ([160.163.57.8]) by smtp.gmail.com with ESMTPSA id 47sm2152312wrb.48.2018.02.28.11.24.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 11:24:35 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, graeme.gregory@linaro.org, masahisa.kojima@linaro.org, Ard Biesheuvel Date: Wed, 28 Feb 2018 19:24:15 +0000 Message-Id: <20180228192421.17684-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180228192421.17684-1-ard.biesheuvel@linaro.org> References: <20180228192421.17684-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms v2 1/7] Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Feb 2018 19:18:31 -0000 Fix the static B/D/F specifiers that refer to the pair of x1 PCIe slots on the DeveloperBox PCB. The current configuration caused user-configurable settings for slots 1/2 to apply to the incorrect one. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h index ee2357be9a06..2d3d5cd91be0 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h @@ -62,7 +62,7 @@ #define SYNQUACER_PCI_LOCATION(s,b,d) (((s) << 16) | ((b) << 8) | (d)) #define SYNQUACER_PCI_SLOT0_LOCATION SYNQUACER_PCI_LOCATION(1, 0, 0) -#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) -#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) +#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) +#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) #endif -- 2.11.0