From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::231; helo=mail-wm0-x231.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x231.google.com (mail-wm0-x231.google.com [IPv6:2a00:1450:400c:c09::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 216C222402E1B for ; Wed, 28 Feb 2018 12:15:25 -0800 (PST) Received: by mail-wm0-x231.google.com with SMTP id 188so7458217wme.1 for ; Wed, 28 Feb 2018 12:21:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=8sEf3R7PJ/QNErqQg9dB720CsH+yicAk3dXbRlaUK/c=; b=i+kJ85kP1wYj4+TdGMhoal8dMMukxY1AtTA6ZjOQFDVI9p6CI8FzvNXw+nFNO1l0hW 1LsP73C2T6bo1Av3pyXllVozlrdvPUW4E97q9EcCyVoYGhPkm6LRW6ZjJuFizhGuXhtl a+Puz/c9YDOP1rOwUgZ+zzrv8tFDzhbMzloAo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=8sEf3R7PJ/QNErqQg9dB720CsH+yicAk3dXbRlaUK/c=; b=cBgeab9ddSfoThrI7VWKKoCpb8q9+3P8YIk1rG6N92uxSdnnY4thfUVTgOhqNqMIzh rx1jpGDv4nUn6yH6bDzgDYu9LQoPPg4bad8m6foin9txVgtSLJ1PY5mVK6br0rfdfZuy CLtjwCnYIFRaa/U/zNdjol7mZqgpP3EDUVnRtCa+rqCzsFAKYt6U8U2rw9dH/9SEvqbe wJv0HHtw4Z3gsq3YIVPSBz0ruKxzZMGT8xiQF6cxaQzjLfM88v2VNgP98OWnBa+/JfHs 5JpxRMhGn8LKu/Z4DREXBhK4T7YGeR6MGZNOFbdgtExa73L9MioF5h343udvYrhV03Gb vxEA== X-Gm-Message-State: APf1xPBpauldr4vSpvvvUPlmPp2dAYkoBsa40vTGG6nUtUij2RpAWP62 xkgDy9r51mBHioQcxP0FAT48kA== X-Google-Smtp-Source: AG47ELsjT9UJYqO+741ylvnjYgcv8dpo/Srw1d/FffyWR8TnNFxxJEXRmk0qbBYtQoThd8hpq4eI6A== X-Received: by 10.28.103.9 with SMTP id b9mr14860392wmc.44.1519849291628; Wed, 28 Feb 2018 12:21:31 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id i44sm179542wri.23.2018.02.28.12.21.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 12:21:30 -0800 (PST) Date: Wed, 28 Feb 2018 20:21:28 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, graeme.gregory@linaro.org, masahisa.kojima@linaro.org Message-ID: <20180228202128.5bdiemzinbkiv2i7@bivouac.eciton.net> References: <20180228192421.17684-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180228192421.17684-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v2 0/7] SynQuacer ACPI support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Feb 2018 20:15:26 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline So, on the whole, I'm happy with this series. Some of the .asl looks to me like it could be made more readable with some additional #defines, but I may be oversimplifying. But I'd like someone with more ACPI experience to give an R-b for 3,5-7. With that provision, for the series: Reviewed-by: Leif Lindholm On Wed, Feb 28, 2018 at 07:24:14PM +0000, Ard Biesheuvel wrote: > This implements ACPI support for the SynQuacer platforms. > > Changes since v1: > - improve commit log (#1, #2) > - replace bare numbers with symbolic constants (#2) > - add Leif's R-b (#4) > - add patches #6 and #7 > > Note that supporting ACPI on this SoC is non-trivial, due to the quirky > DesignWare RCs and the pre-ITS that sits between the PCIe RCs and the GICv3. > However, the most important issue has been addressed by modifying the static > SMMU mapping that sits between the CPUs and the PCIe config space, working > around the ghosting issue that occurs on these RCs, due the complete lack of > type 0 config TLP filtering by the [non-existent] root port. (This was tested > using the 20180226-LB1.1-ACPI-ramfw.bin SCP firmware image, which is not [yet] > installed by default on DeveloperBox hardware) > > That leaves the MSI issue, which is worked around by limiting MSI support to a > single RC. In the presented configuration, this is RC #1, which connects to the > x16 slot [and nothing else] on the DeveloperBox PCB. The onboard PCIe devices > (XHCI + SATA) work without problem using wired interrupts only, and so RC #0 > has MSI support disabled. This means cards that require MSI support should > be inserted into the x16 slot, which is likely to be the preferred slot in > such cases anwyay (e.g., when using NVME or high end networking plugin cards) > > Patch #1 fixes a minor issue in the slot-to-BDF mapping. > > Patch #2 modifies the static PCIe window configuration so it can be described > using ACPI as well as DT. > > Patch #3 introduces the static ACPI tables that describe the fixed platform > devices and peripherals to the OS. > > Patch #4 adds a menu option to the platform driver to make ACPI vs DT user > selectable. > > Patch #5 adds support for describing the eMMC controller using a SSDT table > which is only installed if eMMC support is enabled. > > Patch #6 adds a _STA method implementation to the PCIe RC devices so that > they are only exposed to the OS when running on a platform that has one of > the several ECAM workarounds enabled. Otherwise, we can still boot via ACPI > using platform devices, but the PCIe RCs are unavailable. > > Patch #7 extends the _STA method for PCI0 to take the presence detect GPIO > into account. This is necessary because on the SynQuacer evaluation board, > any attempt to access the device registers will lock up the system if no > card is inserted into the slot. > > Note that driver support for the eMMC and network controller only landed in > v4.15, but when using a SATA driver and a plugin network card that does have > driver support, these patches should allow the SynQuacer based platforms to > boot stock Debian Stretch/Fedora/Centos etc installers. > > Ard Biesheuvel (7): > Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping > Silicon/SynQuacer: tweak PCI I/O windows for ACPI/Linux support > Silicon/SynQuacer: add ACPI drivers and tables > Silicon/SynQuacer/PlatformDxe: add option to enable ACPI mode > Silicon/SynQuacer/PlatformDxe: add ACPI description of eMMC > Silicon/SynQuacer/AcpiTables: disable PCI RCs if ECAM ghosts are > detected > Silicon/SynQuacer/AcpiTables: take presence detect of PCI0 into > account > > Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 2 + > Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 14 + > Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 + > Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 14 + > Silicon/Socionext/SynQuacer/Acpi.dsc.inc | 48 +++ > Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl | 317 ++++++++++++++++++++ > Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h | 73 +++++ > Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf | 65 ++++ > Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 187 ++++++++++++ > Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc | 91 ++++++ > Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc | 93 ++++++ > Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 101 +++++++ > Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc | 182 +++++++++++ > Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc | 63 ++++ > Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc | 128 ++++++++ > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 +- > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl | 41 +++ > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 55 ++++ > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 32 +- > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 4 + > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 5 + > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni | 8 +- > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr | 10 +- > Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 22 +- > Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h | 8 +- > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 4 +- > 26 files changed, 1546 insertions(+), 25 deletions(-) > create mode 100644 Silicon/Socionext/SynQuacer/Acpi.dsc.inc > create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl > create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.h > create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf > create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Fadt.aslc > create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Gtdt.aslc > create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc > create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Madt.aslc > create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Mcfg.aslc > create mode 100644 Silicon/Socionext/SynQuacer/AcpiTables/Spcr.aslc > create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.asl > > -- > 2.11.0 >