From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0F60922568639 for ; Thu, 8 Mar 2018 08:57:11 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id m12so6381743wrm.13 for ; Thu, 08 Mar 2018 09:03:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=fqzH+PQeg9GoNUFrFAzF5lIu4NiN8NeySDxG6M4j1B8=; b=QP6Kxrk6LuEV9FG/20gpDr39FmzfQBF30BFH929OqORHEcpbESqbpOo3LRNnYby56c z/EHezXx4RTNDBc9WSYHsV9mOQeP+FDCwsBJq/tRwz3bBBFF3HxD6hF0shYPB2zUN1rb TCN4LqEotZRUW46fVhnbUEVmzAXaRIBDi7/h0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=fqzH+PQeg9GoNUFrFAzF5lIu4NiN8NeySDxG6M4j1B8=; b=QTvFOkAyCjw+TBgATNEy9jydNg6/CnqAdaxwXAO0Zph6CzL7LQ47gHoAjDQ204GbLC PNZ/6P8TDCPKuu8weuEsVftKAfJDCik384CUwIp8+sahh82DpyjPIt+7VpeRKUT4mZY/ E/UfO5pSarE48j7lu36lJWlS1cvnzcNNcABLTl87Sw6t0gDSIjeg9e7K9lvonmEzybMQ DhRKPmhh/8J/8B9OPfMdM8+gr67BBL81QGIdIPISry+2o8UaG2HfbMPwHoJYH0O4VNtm KQh7K9sHgY4Wsu44FMOg5r5pIY/jDWBUWwGkON7GbLQzMICrALWpNG/nhI0yetwvESqb obQg== X-Gm-Message-State: APf1xPBZYlSMhV7Nu4HCyc6YARhuS3bWkh+KlwfwCEE1fy1EwvlpB+nl EESbJavAkM/ETemdNtvpvyyyWgJK58w= X-Google-Smtp-Source: AG47ELv2Epk5JwpaX7wBMdnXQHSM3QEgdXlVqtzhdpGs2bD+bWFIVruQQcKxYdRGBw2kBHpyIjPvkA== X-Received: by 10.223.196.250 with SMTP id o55mr24372203wrf.200.1520528606242; Thu, 08 Mar 2018 09:03:26 -0800 (PST) Received: from localhost.localdomain ([160.89.73.46]) by smtp.gmail.com with ESMTPSA id p21sm12230106wmc.43.2018.03.08.09.03.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Mar 2018 09:03:25 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, alan@softiron.co.uk, Ard Biesheuvel Date: Thu, 8 Mar 2018 17:03:16 +0000 Message-Id: <20180308170316.3200-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.15.1 Subject: [PATCH edk2-platforms] Silicon/AMD/Styx: add PPTT ACPI table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Mar 2018 16:57:12 -0000 Add a ACPI PPTT table describing the cache topology of the Seattle SoC. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/AMD/Styx/AcpiTables/AcpiTables.inf | 1 + Silicon/AMD/Styx/AcpiTables/Pptt.c | 225 ++++++++++++++++++++ Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h | 1 + Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 3 +- 4 files changed, 229 insertions(+), 1 deletion(-) diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf index cfffc73894c0..057c52512e4e 100644 --- a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf +++ b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf @@ -38,6 +38,7 @@ [Sources] Csrt.c Dsdt.c Iort.c + Pptt.c [Packages] ArmPkg/ArmPkg.dec diff --git a/Silicon/AMD/Styx/AcpiTables/Pptt.c b/Silicon/AMD/Styx/AcpiTables/Pptt.c new file mode 100644 index 000000000000..d9d7c494d86f --- /dev/null +++ b/Silicon/AMD/Styx/AcpiTables/Pptt.c @@ -0,0 +1,225 @@ +/** @file + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include + +#include + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; +} STYX_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; + STYX_PPTT_CORE Cores[2]; +} STYX_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; + STYX_PPTT_CLUSTER Clusters[NUM_CORES / 2]; +} STYX_PPTT_PACKAGE; + +typedef struct { + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; + STYX_PPTT_PACKAGE Packages[1]; +} STYX_PPTT_TABLE; +#pragma pack() + +#define PPTT_CORE(pid, cid, id) { \ + { \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ + FIELD_OFFSET (STYX_PPTT_CORE, DCache), \ + {}, \ + { \ + 0, /* PhysicalPackage */ \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \ + }, \ + FIELD_OFFSET (STYX_PPTT_TABLE, \ + Packages[pid].Clusters[cid]), /* Parent */ \ + ((cid) << 8) + (id), /* AcpiProcessorId */ \ + 2, /* NumberOfPrivateResources */\ + }, { \ + FIELD_OFFSET (STYX_PPTT_TABLE, \ + Packages[pid].Clusters[cid].Cores[id].DCache), \ + FIELD_OFFSET (STYX_PPTT_TABLE, \ + Packages[pid].Clusters[cid].Cores[id].ICache), \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 0, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + SIZE_32KB, /* Size */ \ + 256, /* NumberOfSets */ \ + 2, /* Associativity */ \ + { \ + 0, /* AllocationType */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 0, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + 3 * SIZE_16KB,/* Size */ \ + 256, /* NumberOfSets */ \ + 3, /* Associativity */ \ + { \ + 0, /* AllocationType */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + } \ +} + +#define PPTT_CLUSTER(pid, cid) { \ + { \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ + FIELD_OFFSET (STYX_PPTT_CLUSTER, L2Cache), \ + {}, \ + { \ + 0, /* PhysicalPackage */ \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \ + }, \ + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[pid]), /* Parent */ \ + 0, /* AcpiProcessorId */ \ + 1, /* NumberOfPrivateResources */ \ + }, { \ + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[pid].Clusters[cid].L2Cache), \ + }, { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ + {}, \ + { \ + 1, /* SizePropertyValid */ \ + 1, /* NumberOfSetsValid */ \ + 1, /* AssociativityValid */ \ + 0, /* AllocationTypeValid */ \ + 1, /* CacheTypeValid */ \ + 1, /* WritePolicyValid */ \ + 1, /* LineSizeValid */ \ + }, \ + 0, /* NextLevelOfCache */ \ + SIZE_1MB, /* Size */ \ + 1024, /* NumberOfSets */ \ + 16, /* Associativity */ \ + { \ + 0, /* AllocationType */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ + }, \ + 64 /* LineSize */ \ + }, { \ + PPTT_CORE(pid, cid, 0), \ + PPTT_CORE(pid, cid, 1), \ + } \ +} + +STATIC STYX_PPTT_TABLE mSynQuacerPpttTable = { + { + AMD_ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + STYX_PPTT_TABLE, + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION), + }, + { + { + { + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, + FIELD_OFFSET (STYX_PPTT_PACKAGE, L3Cache), + {}, + { + 1, /* PhysicalPackage */ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ + }, + 0, /* Parent */ + 0, /* AcpiProcessorId */ + 1, /* NumberOfPrivateResources */ + }, { + FIELD_OFFSET (STYX_PPTT_TABLE, Packages[0].L3Cache), + }, { + EFI_ACPI_6_2_PPTT_TYPE_CACHE, + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), + {}, + { + 1, /* SizePropertyValid */ + 1, /* NumberOfSetsValid */ + 1, /* AssociativityValid */ + 0, /* AllocationTypeValid */ + 1, /* CacheTypeValid */ + 1, /* WritePolicyValid */ + 1, /* LineSizeValid */ + }, + 0, /* NextLevelOfCache */ + SIZE_8MB, /* Size */ + 8192, /* NumberOfSets */ + 16, /* Associativity */ + { + 0, /* AllocationType */ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, + }, + 64 /* LineSize */ + }, { + PPTT_CLUSTER (0, 0), +#if NUM_CORES > 3 + PPTT_CLUSTER (0, 1), +#if NUM_CORES > 5 + PPTT_CLUSTER (0, 2), +#if NUM_CORES > 7 + PPTT_CLUSTER (0, 3), +#endif +#endif +#endif + } + } + } +}; + +EFI_ACPI_DESCRIPTION_HEADER * +PpttHeader ( + VOID + ) +{ + return (EFI_ACPI_DESCRIPTION_HEADER *)&mSynQuacerPpttTable.Pptt.Header; +} diff --git a/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h b/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h index 9438b8b0c27e..58e160b6d727 100644 --- a/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h +++ b/Silicon/AMD/Styx/Common/AmdStyxAcpiLib.h @@ -28,6 +28,7 @@ EFI_ACPI_DESCRIPTION_HEADER *Dbg2Header (void); EFI_ACPI_DESCRIPTION_HEADER *SpcrHeader (void); EFI_ACPI_DESCRIPTION_HEADER *CsrtHeader (void); EFI_ACPI_DESCRIPTION_HEADER *IortHeader (void); +EFI_ACPI_DESCRIPTION_HEADER *PpttHeader (void); #define EFI_ACPI_AMD_OEM_ID_ARRAY {'A','M','D','I','N','C'} #define EFI_ACPI_AMD_OEM_TABLE_ID SIGNATURE_64('S','E','A','T','T','L','E',' ') diff --git a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c index 15b38bbf89c6..901eac105932 100644 --- a/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c +++ b/Silicon/AMD/Styx/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -27,7 +27,7 @@ #include #include -#define MAX_ACPI_TABLES 12 +#define MAX_ACPI_TABLES 16 EFI_ACPI_DESCRIPTION_HEADER *AcpiTableList[MAX_ACPI_TABLES]; @@ -69,6 +69,7 @@ AcpiPlatformEntryPoint ( if (PcdGetBool (PcdEnableSmmus)) { AcpiTableList[TableIndex++] = IortHeader(); } + AcpiTableList[TableIndex++] = PpttHeader(); AcpiTableList[TableIndex++] = NULL; DEBUG((DEBUG_INFO, "%a(): ACPI Table installer\n", __FUNCTION__)); -- 2.15.1