From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::241; helo=mail-it0-x241.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x241.google.com (mail-it0-x241.google.com [IPv6:2607:f8b0:4001:c0b::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1661B22603B1E for ; Mon, 12 Mar 2018 03:20:28 -0700 (PDT) Received: by mail-it0-x241.google.com with SMTP id d13so10506417itf.0 for ; Mon, 12 Mar 2018 03:26:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:date:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=/AT9qWwXbvV59bRBTQngti6o9o6mOdfKKWvjGnoGrN4=; b=CyW5vWNsv8/9m/8f978IDkLI1z1QYmDz/anOPGSrswoiWH0yBTEgJNm7SenSRFlekJ TT/crQ0o01ETTeEn3UpDZXZXwxwYjVO4iMeXJhzzdTGtqQdMmiSRtpIBisv6ZnaRcMfO BDGzoANK3bSmu0X6tTnm41hayzVeK6z02zmA4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:date:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=/AT9qWwXbvV59bRBTQngti6o9o6mOdfKKWvjGnoGrN4=; b=tjrpjqFZA8yF+vUzMCiXWQ+zQImS2VyAnZ0lVUTAWeorLJC5PdpQA2/87/l1FeByjZ SEwK485hFYN2hSq/8uXDOhtDue6VEHuUtaFZzyqwXS/a9oojMCta9CcKX+SDTqpJaO6D TB786gl43Z1HidAUTMeBhKSxKvE09TKeFi8vtMOqleIKydoJxNwhbaj/HrZzHAD5xE/R TiWto0FsQRMBUc41Y1s36AlU5rY8x3B39h3V88E6d6viLtgq80N3QWshN+7FU8//tO5Z sglNTDtQTm+gWLtiyuBBLpxWJy4TIDbELAnYcg4KSWGgkK7frcwRamV/VRmIj13k17F6 NFfg== X-Gm-Message-State: AElRT7EQiS4dW1o35R4+T0COOCoNJSokBoIVMn7sweUhMiYoj7rbTSpT rnhoo+NzEcv7RT/eoat7YVvLoA== X-Google-Smtp-Source: AG47ELvPS5Y71Yci1f30+0TzwYXuCd4fmVCP3FIIR5CavRIIVT+NEw2ZdVK8I7AKeWMSePDnLxagqQ== X-Received: by 10.36.127.12 with SMTP id r12mr7831883itc.77.1520850408061; Mon, 12 Mar 2018 03:26:48 -0700 (PDT) Received: from SZX1000114654 ([45.56.152.76]) by smtp.gmail.com with ESMTPSA id n132sm2874135itn.28.2018.03.12.03.26.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Mar 2018 03:26:47 -0700 (PDT) From: Guo Heyi X-Google-Original-From: Guo Heyi Date: Mon, 12 Mar 2018 18:26:43 +0800 To: Marc Zyngier Cc: Heyi Guo , edk2-devel@lists.01.org, Yi Li , Leif Lindholm , Ard Biesheuvel Message-ID: <20180312102643.GC60232@SZX1000114654> References: <1520837611-94728-1-git-send-email-heyi.guo@linaro.org> <1520837611-94728-2-git-send-email-heyi.guo@linaro.org> <54c4aab8-cc61-b4cc-6ab0-325dd42cca35@arm.com> MIME-Version: 1.0 In-Reply-To: <54c4aab8-cc61-b4cc-6ab0-325dd42cca35@arm.com> User-Agent: Mutt/1.5.24 (2015-08-30) Subject: Re: [PATCH 1/1] ArmPkg/TimerDxe: Add DSB for timer compare value reload X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 Mar 2018 10:20:29 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Thanks, I can try if ISB works. The issue was observed on Hisilicon D05 platform. Regards, Heyi On Mon, Mar 12, 2018 at 09:46:41AM +0000, Marc Zyngier wrote: > On 12/03/18 06:53, Heyi Guo wrote: > > Resetting timer compare register has a side effect of clearing GIC > > pending status, if timer interrupt is level sensitive, so a "DSB SY" > > is needed to make sure this change effect is synchronized. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Heyi Guo > > Signed-off-by: Yi Li > > Cc: Leif Lindholm > > Cc: Ard Biesheuvel > > Cc: Marc Zyngier > > --- > > ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > index 33d7c922221f..b732a2ac1b64 100644 > > --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > @@ -337,6 +337,7 @@ TimerInterruptHandler ( > > > > // Set next compare value > > ArmGenericTimerSetCompareVal (CompareValue); > > + ArmDataSynchronizationBarrier (); > > ArmGenericTimerEnableTimer (); > > } > > > > > > Which HW platform is that on? > > DSB on its own doesn't have any effect on inputs to the GIC, only on the > synchronization at the GIC system register level (see the GICv3 > architecture specification, 8.1.6). > > I don't believe this is required. You could stick an ISB instead to > ensure that the write to the CNTVCTL_EL0 is executed, but DSB feels > pretty odd, unless this is a workaround for a platform erratum. > > Thanks, > > M. > -- > Jazz is not dead. It just smells funny...