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From: Guo Heyi <heyi.guo@linaro.org>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>,
	edk2-devel@lists.01.org, Yi Li <phoenix.liyi@huawei.com>,
	Leif Lindholm <leif.lindholm@linaro.org>,
	Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: Re: [PATCH 1/1] ArmPkg/TimerDxe: Add DSB for timer compare value reload
Date: Mon, 12 Mar 2018 18:38:08 +0800	[thread overview]
Message-ID: <20180312103808.GD60232@SZX1000114654> (raw)
In-Reply-To: <20180312102643.GC60232@SZX1000114654>

Hi Marc,

I just tested with an ISB and it also worked for our platform.

So is it acceptable to add an ISB after reloading timer compare value?

Regards,
Heyi

On Mon, Mar 12, 2018 at 06:26:43PM +0800, Guo Heyi wrote:
> Thanks, I can try if ISB works. The issue was observed on Hisilicon D05 platform.
> 
> Regards,
> 
> Heyi
> 
> On Mon, Mar 12, 2018 at 09:46:41AM +0000, Marc Zyngier wrote:
> > On 12/03/18 06:53, Heyi Guo wrote:
> > > Resetting timer compare register has a side effect of clearing GIC
> > > pending status, if timer interrupt is level sensitive, so a "DSB SY"
> > > is needed to make sure this change effect is synchronized.
> > > 
> > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> > > Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
> > > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > > Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > > Cc: Marc Zyngier <marc.zyngier@arm.com>
> > > ---
> > >  ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c
> > > index 33d7c922221f..b732a2ac1b64 100644
> > > --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c
> > > +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c
> > > @@ -337,6 +337,7 @@ TimerInterruptHandler (
> > >  
> > >      // Set next compare value
> > >      ArmGenericTimerSetCompareVal (CompareValue);
> > > +    ArmDataSynchronizationBarrier ();
> > >      ArmGenericTimerEnableTimer ();
> > >    }
> > >  
> > > 
> > 
> > Which HW platform is that on?
> > 
> > DSB on its own doesn't have any effect on inputs to the GIC, only on the
> > synchronization at the GIC system register level (see the GICv3
> > architecture specification, 8.1.6).
> > 
> > I don't believe this is required. You could stick an ISB instead to
> > ensure that the write to the CNTVCTL_EL0 is executed, but DSB feels
> > pretty odd, unless this is a workaround for a platform erratum.
> > 
> > Thanks,
> > 
> > 	M.
> > -- 
> > Jazz is not dead. It just smells funny...


  reply	other threads:[~2018-03-12 10:31 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-12  6:53 [PATCH 0/1] ArmPkg/TimerDxe: Add DSB for timer compare value reload Heyi Guo
2018-03-12  6:53 ` [PATCH 1/1] " Heyi Guo
2018-03-12  9:46   ` Marc Zyngier
2018-03-12 10:26     ` Guo Heyi
2018-03-12 10:38       ` Guo Heyi [this message]
2018-03-12 10:38         ` Ard Biesheuvel
2018-03-12 10:48           ` Marc Zyngier
2018-03-13  0:34             ` Guo Heyi

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