From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::244; helo=mail-io0-x244.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x244.google.com (mail-io0-x244.google.com [IPv6:2607:f8b0:4001:c06::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DA5D522135D4A for ; Mon, 12 Mar 2018 03:31:52 -0700 (PDT) Received: by mail-io0-x244.google.com with SMTP id v6so10836654iog.7 for ; Mon, 12 Mar 2018 03:38:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:date:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=3KVa/Ey/5A+MVYABEBhJJP76bPmtuhr8slKPCGjVRrE=; b=ZpnNfx1zfhwAf2jfL5DxzqtnWOTFdwL4KoWIJiM/++NPhqzH7vRmf8DORV+Xvz0vB7 vp0xKEqlDZCn/UX5qulRRjIWM3UFtq9hxmQG86Ib+iP18HG9rzBBvnWx6t+yGJzhkFl8 /Fx42qsbZMY7uH/IB8oqapNaCDK98yHioK+A8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:date:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=3KVa/Ey/5A+MVYABEBhJJP76bPmtuhr8slKPCGjVRrE=; b=CewJbSBCQ701soI/y9tj70An11Myi8ehaKYraXlTScLcxn3lmoxLGgfQdFpCNS4h3t YR/I9DKCzDbGWxoP3AK9FlfVO0Y0FM0cv0XUTtk3L+/k7MRAGTdRQ9ueE9/p91Arm/in 7lsa1Mf9K+6+Vd+GAYv/1+PLlY1sDLjncgDT9+QINCCz6iBsNT/xe82d63Dx9Kz1hTVq DmTz93kHheKv+S0IL3vZlyB2dBd+vml0CHILAvKXuFz/+mKFXS7CNzilJNpiOMMzEBMs KO65/HqMlII1twEU2jfxJBGnb0/C+ouSyq+yiIV7bYttQgGYRkJkGzVCgvhG8eb1ZEby s63Q== X-Gm-Message-State: AElRT7EeBeAJ1uD+F02jP1q8cjn0oia919HAodc/4sEuJQnKQL+GY0Am gdcbM8oSilnX8x/Jw4ssf4pvzg== X-Google-Smtp-Source: AG47ELuENQ4Se2r03hk1/2hEun/1klEtCynrfB/yVLniN+s8xlBGTgDBcZiErtFRaCxuKP62MdM19A== X-Received: by 10.107.20.21 with SMTP id 21mr5291888iou.246.1520851092382; Mon, 12 Mar 2018 03:38:12 -0700 (PDT) Received: from SZX1000114654 ([45.56.152.76]) by smtp.gmail.com with ESMTPSA id p10sm3353053itb.24.2018.03.12.03.38.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Mar 2018 03:38:11 -0700 (PDT) From: Guo Heyi X-Google-Original-From: Guo Heyi Date: Mon, 12 Mar 2018 18:38:08 +0800 To: Marc Zyngier Cc: Marc Zyngier , edk2-devel@lists.01.org, Yi Li , Leif Lindholm , Ard Biesheuvel Message-ID: <20180312103808.GD60232@SZX1000114654> References: <1520837611-94728-1-git-send-email-heyi.guo@linaro.org> <1520837611-94728-2-git-send-email-heyi.guo@linaro.org> <54c4aab8-cc61-b4cc-6ab0-325dd42cca35@arm.com> <20180312102643.GC60232@SZX1000114654> MIME-Version: 1.0 In-Reply-To: <20180312102643.GC60232@SZX1000114654> User-Agent: Mutt/1.5.24 (2015-08-30) Subject: Re: [PATCH 1/1] ArmPkg/TimerDxe: Add DSB for timer compare value reload X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 Mar 2018 10:31:53 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Marc, I just tested with an ISB and it also worked for our platform. So is it acceptable to add an ISB after reloading timer compare value? Regards, Heyi On Mon, Mar 12, 2018 at 06:26:43PM +0800, Guo Heyi wrote: > Thanks, I can try if ISB works. The issue was observed on Hisilicon D05 platform. > > Regards, > > Heyi > > On Mon, Mar 12, 2018 at 09:46:41AM +0000, Marc Zyngier wrote: > > On 12/03/18 06:53, Heyi Guo wrote: > > > Resetting timer compare register has a side effect of clearing GIC > > > pending status, if timer interrupt is level sensitive, so a "DSB SY" > > > is needed to make sure this change effect is synchronized. > > > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > > Signed-off-by: Heyi Guo > > > Signed-off-by: Yi Li > > > Cc: Leif Lindholm > > > Cc: Ard Biesheuvel > > > Cc: Marc Zyngier > > > --- > > > ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > > index 33d7c922221f..b732a2ac1b64 100644 > > > --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > > +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > > > @@ -337,6 +337,7 @@ TimerInterruptHandler ( > > > > > > // Set next compare value > > > ArmGenericTimerSetCompareVal (CompareValue); > > > + ArmDataSynchronizationBarrier (); > > > ArmGenericTimerEnableTimer (); > > > } > > > > > > > > > > Which HW platform is that on? > > > > DSB on its own doesn't have any effect on inputs to the GIC, only on the > > synchronization at the GIC system register level (see the GICv3 > > architecture specification, 8.1.6). > > > > I don't believe this is required. You could stick an ISB instead to > > ensure that the write to the CNTVCTL_EL0 is executed, but DSB feels > > pretty odd, unless this is a workaround for a platform erratum. > > > > Thanks, > > > > M. > > -- > > Jazz is not dead. It just smells funny...