From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3097820956066 for ; Thu, 15 Mar 2018 03:22:09 -0700 (PDT) Received: by mail-wm0-x244.google.com with SMTP id i194so9389983wmg.1 for ; Thu, 15 Mar 2018 03:28:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=s0sCbvNX4aghtPVU3Ni5QVFW5SF6g07RsulreUUCe7Q=; b=dV5gVDxqOIT2cf0yRIHqu0yjNnKmQHyJ0De/cXSg/aEGMi024AjXPwyMtTTvhSkJe1 A/73hQF2b3aDIjzgsQdtS9ch0Xuelx273jFZJdAGuYEB80VCgcKU3DuEaPSynFRkRWpF QHGeiE+YdYRy9qmxxBhw51795qByjn/GNQTiQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=s0sCbvNX4aghtPVU3Ni5QVFW5SF6g07RsulreUUCe7Q=; b=XpZcrigM5DBEJUoPNGsJse//7piQ4e2Gt3SkSD+hfqCv/HMbLRk4s/lm3j7i5YAy1G MoKl8S4wUkm4/T8bP5KmoS+N2yQnsaGr149cdCPrZ2N0KBJQl0PYHlpgYd+utlmKW44d Z4KZDr9MUWv+KrDfA8npY4u8QNtmnQWxqCh3ZAIkOwlLeUYcAv4CIHylFeBI9pGxCAsH hJzAmiQJ9iwkLdMB6D1xXCZOkqzab6eXv96qqWdgg41eAn7qDhv7PWceJH8iW9xBvumH WWfACqmhXq3Y5WstSsyFGEDH9W27NvOKOxCMl7aNtodzkQ2PVI7CqsESdepx6+5CSZ+J dBXA== X-Gm-Message-State: AElRT7FF4gI6/fQv9v3clmSV8sFF1nGEG/JnWBWrgFdMhPba3Z/4h4tv vhX4PSlW+IeJCZ+DFB4tSFyKfNEgcM8= X-Google-Smtp-Source: AG47ELvFdDonGfaXZq+Q5/4glYkUYpUJLupyREMx0ITwybMfTx/oWfpLJdhz9k7ItU69LNLCSFCCkA== X-Received: by 10.28.238.2 with SMTP id m2mr2379473wmh.135.1521109711727; Thu, 15 Mar 2018 03:28:31 -0700 (PDT) Received: from localhost.localdomain ([105.142.191.63]) by smtp.gmail.com with ESMTPSA id s86sm589475wma.23.2018.03.15.03.28.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Mar 2018 03:28:30 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, lersek@redhat.com, marc.zyngier@arm.com, heyi.guo@linaro.org, Ard Biesheuvel Date: Thu, 15 Mar 2018 10:28:26 +0000 Message-Id: <20180315102826.10517-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.15.1 Subject: [PATCH] ArmPkg/TimerDxe: remove workaround for KVM timer handling X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Mar 2018 10:22:10 -0000 When we first ported EDK2 to KVM/arm, we implemented a workaround for the quirky timer handling on the KVM side. This has been fixed in Linux commit f120cd6533d2 ("KVM: arm/arm64: timer: Allow the timer to control the active state") dated 23 June 2014, which was incorporated into Linux release 4.3. So almost 4 years later, it should be safe to drop this workaround on the EDK2 side. This reverts commit b1a633434ddc. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 - ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.c | 10 ---------- 2 files changed, 11 deletions(-) diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c index a3202fa056f3..bd616d2efc73 100644 --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c @@ -337,7 +337,6 @@ TimerInterruptHandler ( // Set next compare value ArmGenericTimerSetCompareVal (CompareValue); - ArmGenericTimerEnableTimer (); ArmInstructionSynchronizationBarrier (); } diff --git a/ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.c b/ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.c index 69a4ceb62db6..c941895a3574 100644 --- a/ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.c +++ b/ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.c @@ -26,16 +26,6 @@ ArmGenericTimerEnableTimer ( TimerCtrlReg = ArmReadCntvCtl (); TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE; - - // - // When running under KVM, we need to unmask the interrupt on the timer side - // as KVM will mask it when servicing the interrupt at the hypervisor level - // and delivering the virtual timer interrupt to the guest. Otherwise, the - // interrupt will fire again, trapping into the hypervisor again, etc. etc. - // This is scheduled to be fixed on the KVM side, but there is no harm in - // leaving this in once KVM gets fixed. - // - TimerCtrlReg &= ~ARM_ARCH_TIMER_IMASK; ArmWriteCntvCtl (TimerCtrlReg); } -- 2.15.1