Re: [PATCH edk2-platforms] Silicon/SynQuacer; add cache topology information to device tree

[Leif Lindholm <leif.lindholm@linaro.org>]

On Thu, Mar 08, 2018 at 03:21:41PM +0000, Ard Biesheuvel wrote:
> Add a DT description of the size and geometry of the various levels
> of caches that are present in the SynQuacer SoC.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi       |  4 +-
>  Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi | 80 ++++++++++++++++++++
>  2 files changed, 83 insertions(+), 1 deletion(-)
> 
> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> index 2db7de3d5b96..2bea91f7f2c0 100644
> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
> @@ -1,5 +1,5 @@
>  /** @file
> - * Copyright (c) 2017, Linaro Limited. All rights reserved.
> + * Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
>   *
>   * This program and the accompanying materials are licensed and made
>   * available under the terms and conditions of the BSD License which
> @@ -575,3 +575,5 @@
>          #size-cells = <0>;
>      };
>  };
> +
> +#include "SynQuacerCaches.dtsi"
> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi
> new file mode 100644
> index 000000000000..1fbcd4aabfb6
> --- /dev/null
> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi
> @@ -0,0 +1,80 @@
> +/** @file
> + * Copyright (c) 2018, Linaro Limited. All rights reserved.
> + *
> + * This program and the accompanying materials are licensed and made
> + * available under the terms and conditions of the BSD License which
> + * accompanies this distribution.  The full text of the license may be
> + * found at http://opensource.org/licenses/bsd-license.php
> + *
> + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> + * IMPLIED.
> + */
> +
> +#define __L1(cpuref, l2ref)                 \
> +cpuref {                                    \
> +    i-cache-size = <0x8000>;                \
> +    i-cache-line-size = <64>;               \
> +    i-cache-sets = <256>;                   \
> +    d-cache-size = <0x8000>;                \
> +    d-cache-line-size = <64>;               \
> +    d-cache-sets = <128>;                   \
> +    l2-cache = <l2ref>;                     \
> +};
> +
> +#define __L2(idx)                           \
> +L2_##idx: l2-cache##idx {                   \
> +    cache-size = <0x40000>;                 \
> +    cache-line-size = <64>;                 \
> +    cache-sets = <256>;                     \
> +    cache-unified;                          \
> +    next-level-cache = <&L3>;               \
> +};
> +
> +/ {
> +    __L2(0)
> +    __L2(1)
> +    __L2(2)
> +    __L2(3)
> +    __L2(4)
> +    __L2(5)
> +    __L2(6)
> +    __L2(7)
> +    __L2(8)
> +    __L2(9)
> +    __L2(10)
> +    __L2(11)
> +
> +    L3: l3-cache {
> +        cache-level = <3>;
> +        cache-size = <0x400000>;
> +        cache-line-size = <64>;
> +        cache-sets = <4096>;
> +        cache-unified;
> +    };
> +};
> +
> +__L1(&CPU0, &L2_0)
> +__L1(&CPU1, &L2_0)
> +__L1(&CPU2, &L2_1)
> +__L1(&CPU3, &L2_1)
> +__L1(&CPU4, &L2_2)
> +__L1(&CPU5, &L2_2)
> +__L1(&CPU6, &L2_3)
> +__L1(&CPU7, &L2_3)
> +__L1(&CPU8, &L2_4)
> +__L1(&CPU9, &L2_4)
> +__L1(&CPU10, &L2_5)
> +__L1(&CPU11, &L2_5)
> +__L1(&CPU12, &L2_6)
> +__L1(&CPU13, &L2_6)
> +__L1(&CPU14, &L2_7)
> +__L1(&CPU15, &L2_7)
> +__L1(&CPU16, &L2_8)
> +__L1(&CPU17, &L2_8)
> +__L1(&CPU18, &L2_9)
> +__L1(&CPU19, &L2_9)
> +__L1(&CPU20, &L2_10)
> +__L1(&CPU21, &L2_10)
> +__L1(&CPU22, &L2_11)
> +__L1(&CPU23, &L2_11)
> -- 
> 2.15.1
>