From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2F8F020956071 for ; Thu, 15 Mar 2018 11:59:02 -0700 (PDT) Received: by mail-wr0-x243.google.com with SMTP id f14so9364594wre.8 for ; Thu, 15 Mar 2018 12:05:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=C3UGP3LzaTg4llRDfBgON/giLLSYMYEwsbyIem6dULs=; b=FEcXP2uTf597vb6G2vKj+qjp4CEcvIHCmCkmSQ+8eIIIWuoEApTWwFOLkMEm3fHZsd DLZgeilwRga5RbJ73ueBWlS37isHSQEVEwL0+Y5Iz+c6TIC3cfVopOXTzvwi+rQTtDsq xG1MVdoozzJZSR+E5m45aG8EX0oHpK58ke9ys= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=C3UGP3LzaTg4llRDfBgON/giLLSYMYEwsbyIem6dULs=; b=qo7XRh3svep3F1g7BdYpgPMfuzUATGK77yUmhzp7CGcUltkuZcmi8ENSCQa37Vtc4C WaspYJqGpJWw75EoiFO5K1qT+7pU93ssA+NXJ0rfNfZccFnpiy2rL+aUe4IEdF0c9bTZ cuFgIRrMKDHlM56tr1lBe13Rk8fz59XzWAJysU/tuzq1LpqqYCNcGoMc5ZwgoO5KiRdB lBAWUBtHVEpqBmxp7E0OxhpR1rASHd1fyICGr//mDyrx7AceYuSKKmLvdpfkSXSrMAkN fFw/I5onyog8CoJ84MWahZnr5+xJk9tIIYJhx0WZaKgzQN362Fc4KTjrP73HgWvvsk6M utOw== X-Gm-Message-State: AElRT7Esk3tdcYS1G33J4YiYDW/dCwM8TL5xjfO6+PqtJM34/eSTdJrc EKAqSGrokdhbyrkOVDzEl38PR0vnvGc= X-Google-Smtp-Source: AG47ELse3pgFu/2d1zxp4tN6QCZ1q+YgdssTCwRz6pZej9mC+dY8jJVmEaK23eZ+ergFN0fOtB0g5g== X-Received: by 10.223.129.33 with SMTP id 30mr8475060wrm.91.1521140724959; Thu, 15 Mar 2018 12:05:24 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id n8sm5889372wrf.12.2018.03.15.12.05.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 15 Mar 2018 12:05:24 -0700 (PDT) Date: Thu, 15 Mar 2018 19:05:22 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org Message-ID: <20180315190522.ivft6htebkmxcxnu@bivouac.eciton.net> References: <20180308152141.1028-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180308152141.1028-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacer; add cache topology information to device tree X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Mar 2018 18:59:02 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Mar 08, 2018 at 03:21:41PM +0000, Ard Biesheuvel wrote: > Add a DT description of the size and geometry of the various levels > of caches that are present in the SynQuacer SoC. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 4 +- > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi | 80 ++++++++++++++++++++ > 2 files changed, 83 insertions(+), 1 deletion(-) > > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > index 2db7de3d5b96..2bea91f7f2c0 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > @@ -1,5 +1,5 @@ > /** @file > - * Copyright (c) 2017, Linaro Limited. All rights reserved. > + * Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved. > * > * This program and the accompanying materials are licensed and made > * available under the terms and conditions of the BSD License which > @@ -575,3 +575,5 @@ > #size-cells = <0>; > }; > }; > + > +#include "SynQuacerCaches.dtsi" > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi > new file mode 100644 > index 000000000000..1fbcd4aabfb6 > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerCaches.dtsi > @@ -0,0 +1,80 @@ > +/** @file > + * Copyright (c) 2018, Linaro Limited. All rights reserved. > + * > + * This program and the accompanying materials are licensed and made > + * available under the terms and conditions of the BSD License which > + * accompanies this distribution. The full text of the license may be > + * found at http://opensource.org/licenses/bsd-license.php > + * > + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > + * IMPLIED. > + */ > + > +#define __L1(cpuref, l2ref) \ > +cpuref { \ > + i-cache-size = <0x8000>; \ > + i-cache-line-size = <64>; \ > + i-cache-sets = <256>; \ > + d-cache-size = <0x8000>; \ > + d-cache-line-size = <64>; \ > + d-cache-sets = <128>; \ > + l2-cache = ; \ > +}; > + > +#define __L2(idx) \ > +L2_##idx: l2-cache##idx { \ > + cache-size = <0x40000>; \ > + cache-line-size = <64>; \ > + cache-sets = <256>; \ > + cache-unified; \ > + next-level-cache = <&L3>; \ > +}; > + > +/ { > + __L2(0) > + __L2(1) > + __L2(2) > + __L2(3) > + __L2(4) > + __L2(5) > + __L2(6) > + __L2(7) > + __L2(8) > + __L2(9) > + __L2(10) > + __L2(11) > + > + L3: l3-cache { > + cache-level = <3>; > + cache-size = <0x400000>; > + cache-line-size = <64>; > + cache-sets = <4096>; > + cache-unified; > + }; > +}; > + > +__L1(&CPU0, &L2_0) > +__L1(&CPU1, &L2_0) > +__L1(&CPU2, &L2_1) > +__L1(&CPU3, &L2_1) > +__L1(&CPU4, &L2_2) > +__L1(&CPU5, &L2_2) > +__L1(&CPU6, &L2_3) > +__L1(&CPU7, &L2_3) > +__L1(&CPU8, &L2_4) > +__L1(&CPU9, &L2_4) > +__L1(&CPU10, &L2_5) > +__L1(&CPU11, &L2_5) > +__L1(&CPU12, &L2_6) > +__L1(&CPU13, &L2_6) > +__L1(&CPU14, &L2_7) > +__L1(&CPU15, &L2_7) > +__L1(&CPU16, &L2_8) > +__L1(&CPU17, &L2_8) > +__L1(&CPU18, &L2_9) > +__L1(&CPU19, &L2_9) > +__L1(&CPU20, &L2_10) > +__L1(&CPU21, &L2_10) > +__L1(&CPU22, &L2_11) > +__L1(&CPU23, &L2_11) > -- > 2.15.1 >