From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F0BFC20954B86 for ; Fri, 16 Mar 2018 09:07:14 -0700 (PDT) Received: by mail-wr0-x241.google.com with SMTP id s18so12206070wrg.9 for ; Fri, 16 Mar 2018 09:13:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UvgEDsDYCRNbKbBTtx/lwSC50yJMhxlnVB6nwljwR+A=; b=jChW1N09J1yVgRMpjaDMrT/6USAn2zTo9OX3if38RPqFNj6yBNi7vS5q9CAW+3IQEC DO9g4U5B3FNAZMy+lQODsUkHLpAjugfWBTUoIJTj9qrklhpeypwCPyRgxQnq4MQOLI5v f2fs71FUKHYVfZ7VhNj2CxeevF4ZBvcZnQMMo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UvgEDsDYCRNbKbBTtx/lwSC50yJMhxlnVB6nwljwR+A=; b=CF8oZvWCzjTKBhFeL5CDH7DEiW92AcR7xkvtVojer6r6SyKRC3lOjNj0GFXGhbP4zq 5BA/uS33J6UnYDNFdc2NCR68ZPZeQZPa7rYMYXOHc57bDNOdmq59HaC9sSLyLrbmlf/U 3cXzAQ0gY/zxWXGbIHFnxS5WpPWNtkIvPNkwS72NzegWOJ8Qrojlbs8uGx2Vuoki1bjM eTWSWQGiWNAGbhDj0VJQb/ft8GjfvTTTFq2Gmh2JtfWjPrs+DetwKDXn5UqmKnhZvoj+ IZC98hv8toFMGJOPC9k34IJs4e0PLPyp+2jNz8j5jtsYdYQbXuFm21wVnwakbUz7nSS2 wA4Q== X-Gm-Message-State: AElRT7E+MQiY+RJrdjELkcOWjhtrtvGNdGpUf2mP4oySbEhfTvjpWA7M 0UwfbjEBLkQTmx5jfiBelSNV2XhlOLs= X-Google-Smtp-Source: AG47ELtnDLx51Pi94drjtlJXBmaATzjfIU6llSfv2CGvAhU0lTZI+dacJOVnXKbgHx+cyp89a3sKCA== X-Received: by 10.223.183.193 with SMTP id t1mr2060192wre.168.1521216818702; Fri, 16 Mar 2018 09:13:38 -0700 (PDT) Received: from localhost.localdomain ([105.142.191.63]) by smtp.gmail.com with ESMTPSA id n8sm7876242wrf.12.2018.03.16.09.13.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 Mar 2018 09:13:37 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, Ard Biesheuvel Date: Fri, 16 Mar 2018 16:13:21 +0000 Message-Id: <20180316161322.6756-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180316161322.6756-1-ard.biesheuvel@linaro.org> References: <20180316161322.6756-1-ard.biesheuvel@linaro.org> Subject: [RFC PATCH edk2-platforms 5/6] TEMPORARY X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Mar 2018 16:07:15 -0000 Needed to make change to capsule footprint installable via capsule update. Will be reverted in next patch, and will be squashed together before going upstream. --- Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c | 4 ++-- Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c index 816d8ba33f8c..cd6ab582fdc5 100644 --- a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c +++ b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c @@ -23,8 +23,8 @@ STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = { { // UEFI code region SYNQUACER_SPI_NOR_BASE, // device base - FixedPcdGet64 (PcdFdBaseAddress), // region base - FixedPcdGet32 (PcdFdSize), // region size + 0x8100000, //FixedPcdGet64 (PcdFdBaseAddress), // region base + 0x300000, //FixedPcdGet32 (PcdFdSize), // region size SIZE_64KB, // block size { 0x19c118b0, 0xc423, 0x42be, { 0xb8, 0x0f, 0x70, 0x6f, 0x1f, 0xcb, 0x59, 0x9a } diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c index 1402ecafce4a..963d568e43df 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c @@ -57,8 +57,8 @@ STATIC CONST EFI_RESOURCE_ATTRIBUTE_TYPE mDramResourceAttributes = STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = { // Memory mapped SPI NOR flash - ARM_CACHED_DEVICE_REGION (FixedPcdGet64 (PcdFdBaseAddress), - FixedPcdGet32 (PcdFdSize)), + ARM_CACHED_DEVICE_REGION (0x8100000,//FixedPcdGet64 (PcdFdBaseAddress), + 0x300000),//FixedPcdGet32 (PcdFdSize)), // SynQuacer OnChip peripherals ARM_DEVICE_REGION (SYNQUACER_PERIPHERALS_BASE, -- 2.15.1