From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1E50A22489C88 for ; Fri, 16 Mar 2018 09:07:17 -0700 (PDT) Received: by mail-wr0-x242.google.com with SMTP id z73so8003742wrb.0 for ; Fri, 16 Mar 2018 09:13:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y62udVq0VwWhemba8Ll8bVP2+GgxceO3HtTpGgI03hk=; b=DuQb1dcP7P3MxbAB81H8HHQWUxQG/t4VAiqyYu94DHIySrjejLDFmqdn5KcNrOe5nY EoT7yHovwRaWbXYGffG9BHBQFkWvUNPm2ZDTNy/fPKviYKjY9CW3n9ze3Xi4+V0FD8RY wAVKVLGSf2a1HqJmc7bC3vH/TRVzXrRlRGBLA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y62udVq0VwWhemba8Ll8bVP2+GgxceO3HtTpGgI03hk=; b=QQe7zkqxWQN9WiiOQkerWrB4I9VZumifnId1l6ZwbH4Sw8E+V3m8euMjN7Cz/tw5cf f+kjhY3Z3GAIpPCvEruScnR6Qa+Ou38u+BwsiHdYOO1MOIWvI/M00A05FmDvS2wymbTA Ex4xda8cvDUUoN2e28cNzEBzyfluEMUojeQXRELv03BBA2CT9L+fDrOrOadv720MRjr1 sZkL35pnyaE2zknFoKKkjzv9iMNyV+23chEJXysAOfOMkrTZE9zgdx8Uy3wdc50HKgUV 3y3hJcX2jv1D1yUIOBX0epsNfmae2AhuOmmnX7fg8IT+vHhygdb+yi0tyAKlKcRxkHBW ymkw== X-Gm-Message-State: AElRT7FcZvYFyhI5X7KJCfQmJ9adqQ85vXrDDF39VYrfhZIKDpeXZ56U R9uF+lDfJWX9cs1mx8FxCoIpGcYDF5k= X-Google-Smtp-Source: AG47ELt4iVfG09DmYBQ2H24txCkZSgz1Xovcn9w/SvntbGDREYR38IMbFR3emUvtujR0eQ3dlBr8tQ== X-Received: by 10.223.153.49 with SMTP id x46mr2281827wrb.224.1521216820631; Fri, 16 Mar 2018 09:13:40 -0700 (PDT) Received: from localhost.localdomain ([105.142.191.63]) by smtp.gmail.com with ESMTPSA id n8sm7876242wrf.12.2018.03.16.09.13.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 Mar 2018 09:13:39 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, Ard Biesheuvel Date: Fri, 16 Mar 2018 16:13:22 +0000 Message-Id: <20180316161322.6756-7-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180316161322.6756-1-ard.biesheuvel@linaro.org> References: <20180316161322.6756-1-ard.biesheuvel@linaro.org> Subject: [RFC PATCH edk2-platforms 6/6] Platform/Socionext/DeveloperBox: add SCP firmware image to capsule X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Mar 2018 16:07:17 -0000 Modify the .FDF definitions describing the Flash Device and the capsule payload so that the SCP firmware can be updated along with the ARM Trusted Firmware and EDK2 code. Note that this does not increase the likelihood some kind of recovery is needed when a capsule update fails: the NOR layout has been updated to allow the serial flasher to execute even if the SCP firmware has been corrupted, and a failed flash of just UEFI already requires such recovery anyway. Since this constitutes a backward incompatible changes as far as capsule update is concerned, add a provision for setting the minimum supported firmware version via the build command line. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 3 +++ Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 15 +++++++++------ Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 4 ++-- Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c | 4 ++-- Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 4 ++-- 5 files changed, 18 insertions(+), 12 deletions(-) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index 538488253d9b..af2930bcbba5 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -29,6 +29,7 @@ [Defines] BUILD_NUMBER = 1 DEFINE DO_X86EMU = FALSE + DEFINE MIN_BUILD_NUMBER = 1 [BuildOptions] RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0 @@ -404,6 +405,8 @@ [PcdsFixedAtBuild.common] !endif gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|$(BUILD_NUMBER) + gSynQuacerTokenSpaceGuid.PcdLowestSupportedFirmwareVersion|$(MIN_BUILD_NUMBER) + # # 96boards mezzanine support # diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf index ddd9757201aa..b2de8a2255c9 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf @@ -26,13 +26,13 @@ ################################################################################ [FD.SPI_NOR_IMAGE] -BaseAddress = 0x08180000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. -Size = 0x00280000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +BaseAddress = 0x08100000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device ErasePolarity = 1 # This one is tricky, it must be: BlockSize * NumBlocks = Size BlockSize = 0x00010000 -NumBlocks = 0x28 +NumBlocks = 0x30 ################################################################################ # @@ -50,13 +50,16 @@ [FD.SPI_NOR_IMAGE] # ################################################################################ -0x00000000|0x00078000 +0x00000000|0x00080000 +FILE = Platform/Socionext/DeveloperBox/scp_firmware.bin + +0x00080000|0x00078000 FILE = Platform/Socionext/DeveloperBox/fip_all_arm_tf.bin -0x00078000|0x00008000 +0x000f8000|0x00008000 FILE = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(ARCH)/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables/OUTPUT/Stage2Tables.bin -0x00080000|0x00200000 +0x00100000|0x00200000 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize FV = FVMAIN_COMPACT diff --git a/Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini b/Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini index 1f77aeab5049..32b342bd0a1b 100644 --- a/Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini +++ b/Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini @@ -19,7 +19,7 @@ Update0 = SynQuacerFvMain [SynQuacerFvMain] FirmwareType = 0 # SystemFirmware AddressType = 1 # 0 - relative address, 1 - absolute address. -BaseAddress = 0x08180000 # Base address offset on flash -Length = 0x00240000 # Length +BaseAddress = 0x08100000 # Base address offset on flash +Length = 0x00300000 # Length ImageOffset = 0x00000000 # Image offset of this SystemFirmware image FileGuid = e99b89f7-c120-4b25-4db1-8394edb0b4f5 # PcdEdkiiSystemFirmwareFileGuid diff --git a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c index cd6ab582fdc5..816d8ba33f8c 100644 --- a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c +++ b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c @@ -23,8 +23,8 @@ STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = { { // UEFI code region SYNQUACER_SPI_NOR_BASE, // device base - 0x8100000, //FixedPcdGet64 (PcdFdBaseAddress), // region base - 0x300000, //FixedPcdGet32 (PcdFdSize), // region size + FixedPcdGet64 (PcdFdBaseAddress), // region base + FixedPcdGet32 (PcdFdSize), // region size SIZE_64KB, // block size { 0x19c118b0, 0xc423, 0x42be, { 0xb8, 0x0f, 0x70, 0x6f, 0x1f, 0xcb, 0x59, 0x9a } diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c index 963d568e43df..1402ecafce4a 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c @@ -57,8 +57,8 @@ STATIC CONST EFI_RESOURCE_ATTRIBUTE_TYPE mDramResourceAttributes = STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = { // Memory mapped SPI NOR flash - ARM_CACHED_DEVICE_REGION (0x8100000,//FixedPcdGet64 (PcdFdBaseAddress), - 0x300000),//FixedPcdGet32 (PcdFdSize)), + ARM_CACHED_DEVICE_REGION (FixedPcdGet64 (PcdFdBaseAddress), + FixedPcdGet32 (PcdFdSize)), // SynQuacer OnChip peripherals ARM_DEVICE_REGION (SYNQUACER_PERIPHERALS_BASE, -- 2.15.1