From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=girish.pathak@arm.com; receiver=edk2-devel@lists.01.org Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CBA96224BBC31 for ; Tue, 20 Mar 2018 09:12:03 -0700 (PDT) Received: from E107875.Emea.Arm.com (e107875.emea.arm.com [10.10.1.104]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id w2KGISRC021595; Tue, 20 Mar 2018 16:18:31 GMT From: Girish Pathak To: edk2-devel@lists.01.org Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Matteo.Carlini@arm.com, Stephanie.Hughes-Fitt@arm.com, nd@arm.com, Arvind.Chauhan@arm.com, Daniil.Egranov@arm.com, thomas.abraham@arm.com Date: Tue, 20 Mar 2018 16:18:15 +0000 Message-Id: <20180320161823.54020-10-girish.pathak@arm.com> X-Mailer: git-send-email 2.13.3.windows.1 In-Reply-To: <20180320161823.54020-1-girish.pathak@arm.com> References: <20180320161823.54020-1-girish.pathak@arm.com> Subject: [PATCH edk2-platforms v3 09/17] ARM/VExpressPkg: HdLcdArmVExpressLib: Remove redundant Bpp X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Mar 2018 16:12:04 -0000 From: EvanLloyd Because of copy/paste effects, HdLcdArmVExpress.c contained a table entry "LCD_BPP Bpp;" specifying the Bits per Pixel for each mode. However, all modes are LCD_BITS_PER_PIXEL_24. This change removes the table entry and related use of the field. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c | 42 ++++++-------------- 1 file changed, 13 insertions(+), 29 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c index cd62cd61883dcd78c72aa614466c6f714cc73fc4..97cbe77ee79f53d3430b0fdb057a3bf262834849 100644 --- a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c @@ -32,7 +32,6 @@ typedef struct { UINT32 Mode; UINT32 HorizontalResolution; UINT32 VerticalResolution; - LCD_BPP Bpp; UINT32 OscFreq; // These are used by HDLCD @@ -48,37 +47,37 @@ typedef struct { **/ LCD_RESOLUTION mResolutions[] = { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, VGA_OSC_FREQUENCY, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, SVGA_OSC_FREQUENCY, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, XGA_OSC_FREQUENCY, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, (SXGA_OSC_FREQUENCY/2), SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, (UXGA_OSC_FREQUENCY/2), UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, (HD_OSC_FREQUENCY/2), HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH @@ -289,27 +288,12 @@ LcdPlatformQueryMode ( Info->VerticalResolution = mResolutions[ModeNumber].VerticalResolution; Info->PixelsPerScanLine = mResolutions[ModeNumber].HorizontalResolution; - switch (mResolutions[ModeNumber].Bpp) { - case LCD_BITS_PER_PIXEL_24: - Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor; - Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK; - break; - - case LCD_BITS_PER_PIXEL_16_555: - case LCD_BITS_PER_PIXEL_16_565: - case LCD_BITS_PER_PIXEL_12_444: - case LCD_BITS_PER_PIXEL_8: - case LCD_BITS_PER_PIXEL_4: - case LCD_BITS_PER_PIXEL_2: - case LCD_BITS_PER_PIXEL_1: - default: - // These are not supported - ASSERT (FALSE); - break; - } + /* Bits per Pixel is always LCD_BITS_PER_PIXEL_24 */ + Info->PixelFormat = PixelRedGreenBlueReserved8BitPerColor; + Info->PixelInformation.RedMask = LCD_24BPP_RED_MASK; + Info->PixelInformation.GreenMask = LCD_24BPP_GREEN_MASK; + Info->PixelInformation.BlueMask = LCD_24BPP_BLUE_MASK; + Info->PixelInformation.ReservedMask = LCD_24BPP_RESERVED_MASK; return EFI_SUCCESS; } @@ -392,7 +376,7 @@ LcdPlatformGetBpp ( return EFI_INVALID_PARAMETER; } - *Bpp = mResolutions[ModeNumber].Bpp; + *Bpp = LCD_BITS_PER_PIXEL_24; return EFI_SUCCESS; } -- 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'