From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5586C22631492 for ; Fri, 23 Mar 2018 14:08:57 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2759D722D5; Fri, 23 Mar 2018 21:15:30 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-180.rdu2.redhat.com [10.10.120.180]) by smtp.corp.redhat.com (Postfix) with ESMTP id 717BC2166BAE; Fri, 23 Mar 2018 21:15:29 +0000 (UTC) From: Laszlo Ersek To: edk2-devel-01 Cc: Eric Dong , Michael D Kinney Date: Fri, 23 Mar 2018 22:15:04 +0100 Message-Id: <20180323211504.22434-16-lersek@redhat.com> In-Reply-To: <20180323211504.22434-1-lersek@redhat.com> References: <20180323211504.22434-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 23 Mar 2018 21:15:30 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 23 Mar 2018 21:15:30 +0000 (UTC) for IP:'10.11.54.6' DOMAIN:'int-mx06.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [PATCH v2 15/15] UefiCpuPkg/PiSmmCpuDxeSmm: use mnemonics for FXSAVE(64)/FXRSTOR(64) X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Mar 2018 21:08:57 -0000 NASM introduced FXSAVE / FXRSTOR support in commit 900fa5b26b8f ("NASM 0.98p3-hpa", 2002-04-30), which commit stands for the nasm-0.98p3-hpa release. NASM introduced FXSAVE64 / FXRSTOR64 support in commit 3a014348ca15 ("insns: add FXSAVE64/FXRSTOR64, drop np prefix", 2010-07-07), which was part of the "nasm-2.09" release. Edk2 requires nasm-2.10 or later for use with the GCC toolchain family, and nasm-2.12.01 or later for use with all other toolchain families. Replace the binary encoding of the FXSAVE(64)/FXRSTOR(64) instructions with mnemonics. I verified that the "Ia32/SmiException.obj", "X64/SmiEntry.obj" and "X64/SmiException.obj" files are rebuilt after this patch, without any change in content. This patch removes the last instructions encoded with DBs from PiSmmCpuDxeSmm. Cc: Eric Dong Cc: Michael D Kinney Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek --- Notes: v2: - new in v2 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm | 8 ++++---- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 6 ++---- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm | 4 ++-- 3 files changed, 8 insertions(+), 10 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm index 7c80a6ae91c2..fa02c1016ce7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm @@ -382,7 +382,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile): ;; FX_SAVE_STATE_IA32 FxSaveState; sub esp, 512 mov edi, esp - db 0xf, 0xae, 0x7 ;fxsave [edi] + fxsave [edi] ; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear cld @@ -410,7 +410,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile): ;; FX_SAVE_STATE_IA32 FxSaveState; mov esi, esp - db 0xf, 0xae, 0xe ; fxrstor [esi] + fxrstor [esi] add esp, 512 ;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; @@ -582,7 +582,7 @@ PFHandlerEntry: clts sub esp, 512 mov edi, esp - db 0xf, 0xae, 0x7 ;fxsave [edi] + fxsave [edi] ; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear cld @@ -612,7 +612,7 @@ PFHandlerEntry: ;; FX_SAVE_STATE_IA32 FxSaveState; mov esi, esp - db 0xf, 0xae, 0xe ; fxrstor [esi] + fxrstor [esi] add esp, 512 ;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm index 5d731e228095..97c7b01d0db7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -182,8 +182,7 @@ _SmiHandler: ; Save FP registers ; sub rsp, 0x200 - DB 0x48 ; FXSAVE64 - fxsave [rsp] + fxsave64 [rsp] add rsp, -0x20 @@ -201,8 +200,7 @@ _SmiHandler: ; ; Restore FP registers ; - DB 0x48 ; FXRSTOR64 - fxrstor [rsp] + fxrstor64 [rsp] add rsp, 0x200 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm index a8a9af300869..98c40949f583 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm @@ -279,7 +279,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile): sub rsp, 512 mov rdi, rsp - db 0xf, 0xae, 00000111y ;fxsave [rdi] + fxsave [rdi] ; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear cld @@ -309,7 +309,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile): ;; FX_SAVE_STATE_X64 FxSaveState; mov rsi, rsp - db 0xf, 0xae, 00001110y ; fxrstor [rsi] + fxrstor [rsi] add rsp, 512 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; -- 2.14.1.3.gb7cf6e02401b