From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B925B225E4008 for ; Fri, 23 Mar 2018 14:08:48 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 90356230EE3; Fri, 23 Mar 2018 21:15:21 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-180.rdu2.redhat.com [10.10.120.180]) by smtp.corp.redhat.com (Postfix) with ESMTP id DA3242166BAE; Fri, 23 Mar 2018 21:15:20 +0000 (UTC) From: Laszlo Ersek To: edk2-devel-01 Cc: Eric Dong , Michael D Kinney Date: Fri, 23 Mar 2018 22:14:55 +0100 Message-Id: <20180323211504.22434-7-lersek@redhat.com> In-Reply-To: <20180323211504.22434-1-lersek@redhat.com> References: <20180323211504.22434-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.6 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 23 Mar 2018 21:15:21 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 23 Mar 2018 21:15:21 +0000 (UTC) for IP:'10.11.54.6' DOMAIN:'int-mx06.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [PATCH v2 06/15] UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiCr3" with PatchInstructionX86() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Mar 2018 21:08:49 -0000 Rename the variable to "gPatchSmiCr3" so that its association with PatchInstructionX86() is clear from the declaration, change its type to X86_ASSEMBLY_PATCH_LABEL, and patch it with PatchInstructionX86(). This lets us remove the binary (DB) encoding of some instructions in "SmiEntry.nasm". Cc: Eric Dong Cc: Michael D Kinney Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek --- Notes: v2: - use the X86_ASSEMBLY_PATCH_LABEL type rather than UINT8 [Mike] UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 6 +++--- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 6 +++--- UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm index 0ea3c1e4498d..0023cb328d6a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -44,7 +44,7 @@ extern ASM_PFX(CpuSmmDebugExit) global ASM_PFX(gcSmiHandlerTemplate) global ASM_PFX(gcSmiHandlerSize) -global ASM_PFX(gSmiCr3) +global ASM_PFX(gPatchSmiCr3) global ASM_PFX(gPatchSmiStack) global ASM_PFX(gPatchSmbase) global ASM_PFX(mXdSupported) @@ -93,8 +93,8 @@ ASM_PFX(gPatchSmiStack): jmp ProtFlatMode ProtFlatMode: - DB 0xb8 ; mov eax, imm32 -ASM_PFX(gSmiCr3): DD 0 + mov eax, strict dword 0 ; source operand will be patched +ASM_PFX(gPatchSmiCr3): mov cr3, eax ; ; Need to test for CR4 specific bit support diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm index 9cfa8e7fc8f4..9971ae6f064a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -56,7 +56,7 @@ extern ASM_PFX(CpuSmmDebugExit) global ASM_PFX(gPatchSmbase) global ASM_PFX(mXdSupported) global ASM_PFX(gPatchSmiStack) -global ASM_PFX(gSmiCr3) +global ASM_PFX(gPatchSmiCr3) global ASM_PFX(gcSmiHandlerTemplate) global ASM_PFX(gcSmiHandlerSize) @@ -102,8 +102,8 @@ ASM_PFX(gPatchSmiStack): BITS 64 ProtFlatMode: - DB 0xb8 ; mov eax, offset gSmiCr3 -ASM_PFX(gSmiCr3): DD 0 + mov eax, strict dword 0 ; source operand will be patched +ASM_PFX(gPatchSmiCr3): mov cr3, rax mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3 mov cr4, rax ; in PreModifyMtrrs() to flush TLB. diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c index f0c289254330..5c2eb9ab6a1e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c @@ -107,7 +107,7 @@ typedef struct { /// X86_ASSEMBLY_PATCH_LABEL gPatchSmbase; X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack; -extern UINT32 gSmiCr3; +X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3; extern volatile UINT8 gcSmiHandlerTemplate[]; extern CONST UINT16 gcSmiHandlerSize; @@ -719,7 +719,7 @@ InstallSmiHandler ( // CpuSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN)); PatchInstructionX86 (gPatchSmiStack, CpuSmiStack, 4); - gSmiCr3 = Cr3; + PatchInstructionX86 (gPatchSmiCr3, Cr3, 4); PatchInstructionX86 (gPatchSmbase, SmBase, 4); gSmiHandlerIdtr.Base = IdtBase; gSmiHandlerIdtr.Limit = (UINT16)(IdtSize - 1); -- 2.14.1.3.gb7cf6e02401b