From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 59E0420957461 for ; Tue, 27 Mar 2018 17:58:57 -0700 (PDT) Received: by mail-pl0-x241.google.com with SMTP id c11-v6so558512plo.0 for ; Tue, 27 Mar 2018 18:05:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:date:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=DvJCE8ODddwK1GY1rtSZpRLM0LcZmNgBHvVPioI3wvM=; b=a/eJFy4F9Jc/cL6q/f0y+IqV+Z3FRDjP2VmacorGNfaF10cqP4t8fwjim0ktT9dG1n ptaUCDE454qqtFN0SQ0kuMgkhcHvWZtbpd7KYlmjIGdD8QatEkS62ZKMiH4L8FG1urdL nwe5sJZ+DkmX+dp4bMQh93pNbo1LgFZHwoIQQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:date:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=DvJCE8ODddwK1GY1rtSZpRLM0LcZmNgBHvVPioI3wvM=; b=hAwY7PNsISGyI0/UDsreuxfqG2w6eWBQyUTdFNraAIKTOQvaJl/RdzkSQT7SX5T9iK eE037mEQ86SKncSHm/K9HyECnpdcnwsOQzzhFbCBfDmjzXVWRWnzRi7jTdxyHKl6usdb uhycw9ttGCw19NvYk9bqTJyeF3AmF8Z8r3ZgBMv7iRxJQTrJ6BqbRLplQz4lc1m4t4Lg TjBV31DLk7qPu+mmKifHKTuJ+UBluLftJDQ3M6nu+CrpSJ5fBBGjPFuyoBzrpJr09edt hEVrO1RHJKcjKaDNZhuJhSYMFI02cb8AtaSq8Fqow8FTLOT+htuc7Bk7QNDWT5y4vP2i Suew== X-Gm-Message-State: AElRT7HfEuh/aB/LQEI1IFcN25HEO/OmMBuo+xnMA2XGAZgxhz7STbRl Q1H372qcrPYaHm37MfwOIKxD7A== X-Google-Smtp-Source: AIpwx48WYTHOWFHMPwPGySoz6YcyEOeRnRHFgdZ5hzzW/VRw6MkO+Gb8ExbJ2Vgi8OQNqCCA8YZ0tg== X-Received: by 2002:a17:902:5a87:: with SMTP id r7-v6mr1503942pli.173.1522199135061; Tue, 27 Mar 2018 18:05:35 -0700 (PDT) Received: from SZX1000114654 ([104.237.91.79]) by smtp.gmail.com with ESMTPSA id z84sm5538045pff.135.2018.03.27.18.05.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Mar 2018 18:05:34 -0700 (PDT) From: Guo Heyi X-Google-Original-From: Guo Heyi Date: Wed, 28 Mar 2018 09:05:31 +0800 To: Leif Lindholm Cc: edk2-devel@lists.01.org, Ard Biesheuvel , Leif Lindholm , Michael D Kinney , Haojian Zhuang Message-ID: <20180328010531.GA69547@SZX1000114654> References: <1521594198-52523-1-git-send-email-heyi.guo@linaro.org> MIME-Version: 1.0 In-Reply-To: <1521594198-52523-1-git-send-email-heyi.guo@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) Subject: Re: [PATCH edk2-platforms 00/12] Hisilicon/D0x: Switch to generic PciHostBridge X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Mar 2018 00:58:57 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Leif, Ard, Any comments for this series of patches? Thanks, Heyi On Wed, Mar 21, 2018 at 09:03:06AM +0800, Heyi Guo wrote: > For BAR address translation support was added to edk2 generic PciHostBridge by > commit 74d0a33, now we can also use it for D03/D05 platforms. > This series of patches include 3 parts of change: > - Preparation for the switch, moving platform specific code out of PciHostBridge > driver. > - Add depending libraries and protocol implementations, like PciHostBridgeLib, > PciSegmentLib and CpuIo2 Protocol. > - Other enhancement and refinement. > > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Cc: Michael D Kinney > Cc: Haojian Zhuang > > Heyi Guo (12): > Hisilicon: Enable WARN and INFO debug message > Hisilicon/D05/PlatformPciLib: fix misuse of macro > Hisilicon/Pci: move ATU configuration to PcieInitDxe > Hisilicon/Pci: Merge PciPlatform into PcieInit Driver > Hisilicon/Pci: Move EnlargeAtuConfig0() to PcieInitDxe > Hisilicon/PlatformPciLib: add segment for each root bridge > Hisilicon: add PciHostBridgeLib > Hisilicon: add PciCpuIo2Dxe > Hisilicon: add PciSegmentLib for Hi161x > Hisilicon/D0x: Switch to generic PciHostBridge driver > Hisilicon: remove platform specific PciHostBridge > Hisilicon/PlatformPciLib: clear redundant felds in RESOURCE_APPETURE > > Silicon/Hisilicon/Hisilicon.dsc.inc | 8 +- > Platform/Hisilicon/D03/D03.dsc | 7 +- > Platform/Hisilicon/D05/D05.dsc | 7 +- > Platform/Hisilicon/D03/D03.fdf | 4 +- > Platform/Hisilicon/D05/D05.fdf | 4 +- > Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf | 53 - > Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 51 + > Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf | 48 + > Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf | 74 - > Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 9 +- > Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf | 36 + > Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 528 ----- > {Platform/Hisilicon/D03/Drivers/PciPlatform => Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610}/PciPlatform.h | 0 > Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 13 + > Silicon/Hisilicon/Include/Library/PlatformPciLib.h | 3 +- > Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c | 24 +- > Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 66 +- > Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c | 304 +++ > Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c | 557 +++++ > Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 1659 -------------- > Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 2404 -------------------- > {Platform/Hisilicon/D03/Drivers/PciPlatform => Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610}/PciPlatform.c | 12 + > Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c | 7 +- > Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c | 309 +++ > Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/PciSegmentLib.c | 1503 ++++++++++++ > 25 files changed, 2897 insertions(+), 4793 deletions(-) > delete mode 100644 Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf > create mode 100644 Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf > create mode 100644 Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf > delete mode 100644 Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf > create mode 100644 Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf > delete mode 100644 Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h > rename {Platform/Hisilicon/D03/Drivers/PciPlatform => Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610}/PciPlatform.h (100%) > create mode 100644 Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c > create mode 100644 Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c > delete mode 100644 Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c > delete mode 100644 Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c > rename {Platform/Hisilicon/D03/Drivers/PciPlatform => Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610}/PciPlatform.c (93%) > create mode 100644 Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c > create mode 100644 Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/PciSegmentLib.c > > -- > 2.7.4 >