From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=pete@akeo.ie; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 37ACF22106DCA for ; Wed, 28 Mar 2018 08:48:57 -0700 (PDT) Received: by mail-wm0-x242.google.com with SMTP id v21so5910559wmc.1 for ; Wed, 28 Mar 2018 08:55:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=agi6x545hRmVBi0IvIub2V6AWoUX9I4Gpjr5UsXlI/M=; b=WvV2rPb3rSdffO2s36goC6opegSnnKXkO3L4EXtM4M6+dDTg4UlXxfFSrQa6shIYa0 fCbdkXgS7ac5DbT50XEaPP57InimluseRHhETsKMgggaC4/O4akSE6Fqk+ABlwhfrufN R2sqy20DFVNRMrUwp+XbZ2f159/N49sz7iyX3l52t/fZsIY9Cx/C3phbJBnQGLYeY8CS FG0VAKOUnMOXotCX0fFRFjbLymAxXuEtE1mPYLYsJZAPlikhHNZ8RmwJuFPabsdN6FSa O/p6HQTcHqjhLxblUjJghv+AA2wOxm6tkAuv4r5hSFmTo/3M1qsz4NAWLBz+MVBp5azn P/XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=agi6x545hRmVBi0IvIub2V6AWoUX9I4Gpjr5UsXlI/M=; b=NmpOB8p5omkQ4OD9l2fUUakqgy/S1YiR142XX96ikjRCI8sJ7rHaJPMQCOpeSgZNvX qOnEUCEpkQx0Dx1xLm4QYg0B3L+urRVP+2h00unW+WrX782Zf00gWBNgXkKikBof4QRk jew4FedKkxVD0otfu5VyGxdUmR9yE33Y/cQfFF6+JnVlz4pZOZ4dgfyfnlNYvMSf1hEV tSXSXw2FGHva08zvdL4dCUmeOOkpcAAGHAXURZRMe3exqFP7IhRZFFTMxIpf1MWVyM/Z 02D6qGHGbTm946WL3jgBLAKyfdP3neiwMjBsyp0rGGncQQKElDY/o2yhsn9XxXrXcvkQ UwXg== X-Gm-Message-State: AElRT7HqoV18IgU4SFk6I7uJvVE2pLLe4/UFUyVk+a03HS10rJtzIfxz WYCjg/Y59ffAjO0Lqpl0Hzjk/lyC08pF9g== X-Google-Smtp-Source: AIpwx48QdnRSf0UShlQNRKmKWN6sBdRfSyNlN/0Zou7hLBymzwLMsUIJDXmMNR2xBPt7PUSBdlloFg== X-Received: by 10.80.131.198 with SMTP id 64mr3927272edi.273.1522252534113; Wed, 28 Mar 2018 08:55:34 -0700 (PDT) Received: from localhost.localdomain ([84.203.68.191]) by smtp.gmail.com with ESMTPSA id h33sm2995268edh.1.2018.03.28.08.55.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Mar 2018 08:55:33 -0700 (PDT) From: Pete Batard To: edk2-devel@lists.01.org Cc: liming.gao@intel.com, ard.biesheuvel@linaro.org Date: Wed, 28 Mar 2018 16:55:21 +0100 Message-Id: <20180328155521.7312-3-pete@akeo.ie> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20180328155521.7312-1-pete@akeo.ie> References: <20180328155521.7312-1-pete@akeo.ie> Subject: [PATCH 2/2] MdePkg/Library/BaseCpuLib: Enable VS2017/ARM64 builds X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Mar 2018 15:48:57 -0000 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Pete Batard --- MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm | 39 +++++++++++++++++++ MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm | 40 ++++++++++++++++++++ MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 8 ++-- 3 files changed, 84 insertions(+), 3 deletions(-) diff --git a/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm b/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm new file mode 100644 index 000000000000..aee9049fba12 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/AArch64/CpuFlushTlb.asm @@ -0,0 +1,39 @@ +;------------------------------------------------------------------------------ +; +; CpuFlushTlb() for ARM +; +; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + + EXPORT CpuFlushTlb + AREA BaseCpuLib_LowLevel, CODE, READONLY + +;/** +; Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU. +; +; Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU. +; +;**/ +;VOID +;EFIAPI +;CpuFlushTlb ( +; VOID +; ); +; +CpuFlushTlb + tlbi vmalle1 // Invalidate Inst TLB and Data TLB + dsb sy + isb + ret + + END diff --git a/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm b/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm new file mode 100644 index 000000000000..7481c225d745 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/AArch64/CpuSleep.asm @@ -0,0 +1,40 @@ +;------------------------------------------------------------------------------ +; +; CpuSleep() for AArch64 +; +; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+; Portions copyright (c) 2011 - 2013, ARM LTD. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +;------------------------------------------------------------------------------ + + EXPORT CpuSleep + AREA BaseCpuLib_LowLevel, CODE, READONLY + +;/** +; Places the CPU in a sleep state until an interrupt is received. +; +; Places the CPU in a sleep state until an interrupt is received. If interrupts +; are disabled prior to calling this function, then the CPU will be placed in a +; sleep state indefinitely. +; +;**/ +;VOID +;EFIAPI +;CpuSleep ( +; VOID +; ); +; + +CpuSleep + wfi + ret + + END diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf index 996446ec1a38..dad08dfe7f54 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -1,7 +1,7 @@ ## @file # Instance of CPU Library for various architecture. # -# CPU Library implemented using ASM functions for IA-32 and X64, +# CPU Library implemented using ASM functions for IA32, X64, ARM, AARCH64, # PAL CALLs for IPF, and empty functions for EBC. # # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
@@ -71,8 +71,10 @@ [Sources.ARM] Arm/CpuSleep.S | GCC [Sources.AARCH64] - AArch64/CpuFlushTlb.S | GCC - AArch64/CpuSleep.S | GCC + AArch64/CpuFlushTlb.S | GCC + AArch64/CpuSleep.S | GCC + AArch64/CpuFlushTlb.asm | MSFT + AArch64/CpuSleep.asm | MSFT [Packages] MdePkg/MdePkg.dec -- 2.9.3.windows.2