From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::244; helo=mail-pg0-x244.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x244.google.com (mail-pg0-x244.google.com [IPv6:2607:f8b0:400e:c05::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2A31221E08175 for ; Fri, 30 Mar 2018 18:37:52 -0700 (PDT) Received: by mail-pg0-x244.google.com with SMTP id y16so5435065pgv.1 for ; Fri, 30 Mar 2018 18:37:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:date:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=MQvPjm/kxe+HE111id+4UvGhJHqC5hBZvxzgE1Z94E0=; b=f17tj+wX3egdHFl+RpYQL3hGUUgqMHe9YYXKzCjxvl+vxmrzeIAT+mxmvSN/qBSHSu 0ZFkKsWZk/X13/XZ6CPXUsDyo3Eek4R3DCGREsBz1noHsA4g5GRPWXGV9nc9pSzojmxc amtX66FejEX4hZJAqlxfpVHppd+wuq1teaMaI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:date:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=MQvPjm/kxe+HE111id+4UvGhJHqC5hBZvxzgE1Z94E0=; b=VWCjlwx4pQbzr68ABGM67uYahuseiM1ert1xo30NJ/HL9MIOzNa0/9Jasj5JW6e9/K 5kkfoaTzssQFjsQ5rQoQS4Yzz0kQqH3AM1DWudpiGgU6Kf9YMsalfK7s61VJ66rjZp5V qhebmiuvHZzmyzRzf5+K6cDymtR7XSnUOAU35eGzjDjJug4Yj/ygdRhozO/QOgFDJElI FeuPxN6LJIhrt7ylavMe86Pmx1T2MXuyEeWrmgpVp3kM99cg15RJZC9lAyvj3qtMJxL+ 0EkAnuqkwiOv4gf0ntx74JqzMEVCOIrXGd0BRmw56V/BtpTnguMnAQRilntY9rnWG1cA 1miQ== X-Gm-Message-State: AElRT7EBMzDHk8Ab7bGFzI7R5g3BngMMHu2/6u+d/cbT89/wxFk+pR14 IpxG5UkcKv+bteQXF/uv8qoYyw== X-Google-Smtp-Source: AIpwx4913GcUy0+dLebrXq0dFHjh4Gk5ENCsSnx0Lfk5dUqU4R4zMoAcA5Aiyra5bwVIHae+ItRfAg== X-Received: by 10.101.98.151 with SMTP id f23mr782149pgv.98.1522460272432; Fri, 30 Mar 2018 18:37:52 -0700 (PDT) Received: from SZX1000114654 ([104.237.91.79]) by smtp.gmail.com with ESMTPSA id 17sm20178908pfo.4.2018.03.30.18.37.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Mar 2018 18:37:51 -0700 (PDT) From: Guo Heyi X-Google-Original-From: Guo Heyi Date: Sat, 31 Mar 2018 09:37:47 +0800 To: Ard Biesheuvel Cc: Guo Heyi , Leif Lindholm , "edk2-devel@lists.01.org" , Michael D Kinney , Haojian Zhuang Message-ID: <20180331013747.GA106704@SZX1000114654> References: <1521594198-52523-1-git-send-email-heyi.guo@linaro.org> <20180328010531.GA69547@SZX1000114654> <20180329002050.GB97590@SZX1000114654> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Subject: Re: [PATCH edk2-platforms 00/12] Hisilicon/D0x: Switch to generic PciHostBridge X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 31 Mar 2018 01:37:53 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ard, Thanks for your time of reviewing the patches. Please see my opinions below. On Fri, Mar 30, 2018 at 05:40:20PM +0200, Ard Biesheuvel wrote: > On 29 March 2018 at 02:20, Guo Heyi wrote: > > On Wed, Mar 28, 2018 at 10:43:41AM +0100, Ard Biesheuvel wrote: > >> On 28 March 2018 at 02:05, Guo Heyi wrote: > >> > Hi Leif, Ard, > >> > > >> > Any comments for this series of patches? > >> > > >> > >> Hello Heyi, > >> > >> Thanks for sending these patches. Leif is at the plugfest, but I will > >> look at these before the end of the week. > > > > Forgot the plugfest as I am not attending :) > > Hello Heyi, > > I think the series looks mostly fine in general, but there are two > things that I'd like you to change (as noted in my replies): > - please split the PCI to CPU I/O translation from the CPU I/O to CPU > MMIO translation I heard that OS did the same as you indicated, but the reasons of why I translated IO address into memory address in PCI host bridge are like below: 1. If we add an intermediate level of "CPU IO address space", it makes things a little more complicated but I don't see any real benefit. If we just make a simple policy that on ARM/AARCH64 CPU IO address is equal to CPU memory address, we can even use a unified CPU IO driver for all ARM/AARCH64 platforms, while the translation is covered by PCI host bridge driver. 2. From hardware perspective, the translation is done by PCIe ATU; for IO bar access, the address from CPU to ATU is a CPU memory address, not an intermediate CPU IO address; the intermediate CPU IO address is a totally logical concept, and it also splits ATU function into separate drivers (CPU IO protocol driver also sees part of ATU function). Please let me know if my understanding is not right. > - please fix the APPETURE spelling (in whichever way is most > convenient for you: separate patch at the beginning, at the end, etc > etc) Nice catch :) will fix that. Thanks, Heyi