From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 119CE226CD785 for ; Wed, 11 Apr 2018 17:55:46 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3EBB7406F972; Thu, 12 Apr 2018 00:55:45 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-97.rdu2.redhat.com [10.10.120.97]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4160A1208F7B; Thu, 12 Apr 2018 00:55:44 +0000 (UTC) From: Laszlo Ersek To: edk2-devel@lists.01.org Cc: Ard Biesheuvel , Leif Lindholm , Steve Capper , Supreeth Venkatesh Date: Thu, 12 Apr 2018 02:55:31 +0200 Message-Id: <20180412005540.26651-2-lersek@redhat.com> In-Reply-To: <20180412005540.26651-1-lersek@redhat.com> References: <20180412005540.26651-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Thu, 12 Apr 2018 00:55:45 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.5]); Thu, 12 Apr 2018 00:55:45 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [PATCH 01/10] Omap35xxPkg/InterruptDxe: replace CPU Arch Protocol depex with notify X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Apr 2018 00:55:46 -0000 In a later patch, we'll modify the depex of "ArmPkg/Drivers/CpuDxe/CpuDxe.inf" (currently "AFTER gArmGicDxeFileGuid") to "gHardwareInterruptProtocolGuid OR gHardwareInterrupt2ProtocolGuid". Considering platforms that include "ArmPkg/Drivers/CpuDxe/CpuDxe.inf", there are two classes: (1) The platform gets its gHardwareInterruptProtocolGuid or gHardwareInterrupt2ProtocolGuid instance from "ArmPkg/Drivers/ArmGic/ArmGicDxe.inf". For such platforms, the upcoming CpuDxe change is not a problem, because commit 61a7b0ec634f made ArmGicDxe wait for the CPU Arch Protocol with a protocol notify. (2) The platform gets its hardware interrupt protocol(s) from a different driver that has a hard depex on the CPU Arch Protocol. The upcoming CpuDxe change would lead to a loop in the DXE dispatch order. In the edk2 tree, only "BeagleBoardPkg/BeagleBoardPkg.dsc" falls in class (2), and the driver in question is "Omap35xxPkg/InterruptDxe". Port (most of) commit 61a7b0ec634f to it. Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Steve Capper Cc: Supreeth Venkatesh Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek --- Notes: build-tested only, as part of BeagleBoardPkg Omap35xxPkg/InterruptDxe/InterruptDxe.inf | 6 +- Omap35xxPkg/InterruptDxe/HardwareInterrupt.c | 81 +++++++++++++++----- 2 files changed, 66 insertions(+), 21 deletions(-) diff --git a/Omap35xxPkg/InterruptDxe/InterruptDxe.inf b/Omap35xxPkg/InterruptDxe/InterruptDxe.inf index 6deb8c3f675c..61ad89af2758 100644 --- a/Omap35xxPkg/InterruptDxe/InterruptDxe.inf +++ b/Omap35xxPkg/InterruptDxe/InterruptDxe.inf @@ -41,14 +41,14 @@ [LibraryClasses] PrintLib UefiDriverEntryPoint IoLib ArmLib [Protocols] - gHardwareInterruptProtocolGuid - gEfiCpuArchProtocolGuid + gHardwareInterruptProtocolGuid ## PRODUCES + gEfiCpuArchProtocolGuid ## CONSUMES ## NOTIFY [FixedPcd.common] gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress [Depex] - gEfiCpuArchProtocolGuid + TRUE diff --git a/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c b/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c index 09e22b5921b0..2ddc7c0566d0 100644 --- a/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c +++ b/Omap35xxPkg/InterruptDxe/HardwareInterrupt.c @@ -293,12 +293,60 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = { EnableInterruptSource, DisableInterruptSource, GetInterruptSourceState, EndOfInterrupt }; +STATIC VOID *mCpuArchProtocolNotifyEventRegistration; + +STATIC +VOID +EFIAPI +CpuArchEventProtocolNotify ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_CPU_ARCH_PROTOCOL *Cpu; + EFI_STATUS Status; + + // + // Get the CPU protocol that this driver requires. + // + Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: gBS->LocateProtocol() - %r\n", __FUNCTION__, + Status)); + ASSERT (FALSE); + return; + } + + // + // Unregister the default exception handler. + // + Status = Cpu->RegisterInterruptHandler (Cpu, EXCEPT_ARM_IRQ, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n", + __FUNCTION__, Status)); + ASSERT (FALSE); + return; + } + + // + // Register to receive interrupts + // + Status = Cpu->RegisterInterruptHandler (Cpu, EXCEPT_ARM_IRQ, + IrqInterruptHandler); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n", + __FUNCTION__, Status)); + ASSERT (FALSE); + return; + } +} + /** Initialize the state information for the CPU Architectural Protocol @param ImageHandle of the loaded driver @param SystemTable Pointer to the System Table @@ -311,13 +359,13 @@ EFI_STATUS InterruptDxeInitialize ( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable ) { EFI_STATUS Status; - EFI_CPU_ARCH_PROTOCOL *Cpu; + EFI_EVENT CpuArchEvent; // Make sure the Interrupt Controller Protocol is not already installed in the system. ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid); // Make sure all interrupts are disabled by default. MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF); @@ -328,30 +376,27 @@ InterruptDxeInitialize ( Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle, &gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol, NULL); ASSERT_EFI_ERROR(Status); // - // Get the CPU protocol that this driver requires. - // - Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu); - ASSERT_EFI_ERROR(Status); - - // - // Unregister the default exception handler. - // - Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL); - ASSERT_EFI_ERROR(Status); - - // - // Register to receive interrupts - // - Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler); - ASSERT_EFI_ERROR(Status); + // Install the interrupt handler as soon as the CPU arch protocol appears. + // + CpuArchEvent = EfiCreateProtocolNotifyEvent ( + &gEfiCpuArchProtocolGuid, + TPL_CALLBACK, + CpuArchEventProtocolNotify, + NULL, + &mCpuArchProtocolNotifyEventRegistration + ); + ASSERT (CpuArchEvent != NULL); // Register for an ExitBootServicesEvent Status = gBS->CreateEvent(EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent); - ASSERT_EFI_ERROR(Status); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + gBS->CloseEvent (CpuArchEvent); + } return Status; } -- 2.14.1.3.gb7cf6e02401b