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From: Guo Heyi <heyi.guo@linaro.org>
To: Guo Heyi <heyi.guo@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>,
	Leif Lindholm <leif.lindholm@linaro.org>,
	"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>,
	Michael D Kinney <michael.d.kinney@intel.com>,
	Haojian Zhuang <haojian.zhuang@linaro.org>
Subject: Re: [PATCH edk2-platforms 00/12] Hisilicon/D0x: Switch to generic PciHostBridge
Date: Fri, 13 Apr 2018 10:05:53 +0800	[thread overview]
Message-ID: <20180413020553.GB119834@SZX1000114654> (raw)
In-Reply-To: <20180331013747.GA106704@SZX1000114654>

Hi Ard,

Any comments?

Anyway we can modify the code if you insist on using an intermediate CPU IO
address space.

Thanks,

Heyi

On Sat, Mar 31, 2018 at 09:37:47AM +0800, Guo Heyi wrote:
> Hi Ard,
> 
> Thanks for your time of reviewing the patches.
> Please see my opinions below.
> 
> On Fri, Mar 30, 2018 at 05:40:20PM +0200, Ard Biesheuvel wrote:
> > On 29 March 2018 at 02:20, Guo Heyi <heyi.guo@linaro.org> wrote:
> > > On Wed, Mar 28, 2018 at 10:43:41AM +0100, Ard Biesheuvel wrote:
> > >> On 28 March 2018 at 02:05, Guo Heyi <heyi.guo@linaro.org> wrote:
> > >> > Hi Leif, Ard,
> > >> >
> > >> > Any comments for this series of patches?
> > >> >
> > >>
> > >> Hello Heyi,
> > >>
> > >> Thanks for sending these patches. Leif is at the plugfest, but I will
> > >> look at these before the end of the week.
> > >
> > > Forgot the plugfest as I am not attending :)
> > 
> > Hello Heyi,
> > 
> > I think the series looks mostly fine in general, but there are two
> > things that I'd like you to change (as noted in my replies):
> > - please split the PCI to CPU I/O translation from the CPU I/O to CPU
> > MMIO translation
> 
> I heard that OS did the same as you indicated, but the reasons of why I
> translated IO address into memory address in PCI host bridge are like below:
> 
> 1. If we add an intermediate level of "CPU IO address space", it makes things a
> little more complicated but I don't see any real benefit. If we just make a
> simple policy that on ARM/AARCH64 CPU IO address is equal to CPU memory address,
> we can even use a unified CPU IO driver for all ARM/AARCH64 platforms, while the
> translation is covered by PCI host bridge driver.
> 
> 2. From hardware perspective, the translation is done by PCIe ATU; for IO bar
> access, the address from CPU to ATU is a CPU memory address, not an intermediate
> CPU IO address; the intermediate CPU IO address is a totally logical concept,
> and it also splits ATU function into separate drivers (CPU IO protocol driver
> also sees part of ATU function).
> 
> Please let me know if my understanding is not right.
> 
> > - please fix the APPETURE spelling (in whichever way is most
> > convenient for you: separate patch at the beginning, at the end, etc
> > etc)
> 
> Nice catch :) will fix that.
> 
> Thanks,
> 
> Heyi


  reply	other threads:[~2018-04-13  2:05 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-21  1:03 [PATCH edk2-platforms 00/12] Hisilicon/D0x: Switch to generic PciHostBridge Heyi Guo
2018-03-21  1:03 ` [PATCH edk2-platforms 01/12] Hisilicon: Enable WARN and INFO debug message Heyi Guo
2018-03-21  1:03 ` [PATCH edk2-platforms 02/12] Hisilicon/D05/PlatformPciLib: fix misuse of macro Heyi Guo
2018-03-21  1:03 ` [PATCH edk2-platforms 03/12] Hisilicon/Pci: move ATU configuration to PcieInitDxe Heyi Guo
2018-03-30 15:19   ` Ard Biesheuvel
2018-03-21  1:03 ` [PATCH edk2-platforms 04/12] Hisilicon/Pci: Merge PciPlatform into PcieInit Driver Heyi Guo
2018-03-21  1:03 ` [PATCH edk2-platforms 05/12] Hisilicon/Pci: Move EnlargeAtuConfig0() to PcieInitDxe Heyi Guo
2018-03-21  1:03 ` [PATCH edk2-platforms 06/12] Hisilicon/PlatformPciLib: add segment for each root bridge Heyi Guo
2018-03-21  1:03 ` [PATCH edk2-platforms 07/12] Hisilicon: add PciHostBridgeLib Heyi Guo
2018-03-30 15:28   ` Ard Biesheuvel
2018-03-21  1:03 ` [PATCH edk2-platforms 08/12] Hisilicon: add PciCpuIo2Dxe Heyi Guo
2018-03-30 15:30   ` Ard Biesheuvel
2018-03-21  1:03 ` [PATCH edk2-platforms 09/12] Hisilicon: add PciSegmentLib for Hi161x Heyi Guo
2018-03-21  1:03 ` [PATCH edk2-platforms 10/12] Hisilicon/D0x: Switch to generic PciHostBridge driver Heyi Guo
2018-03-30 15:34   ` Ard Biesheuvel
2018-03-21  1:03 ` [PATCH edk2-platforms 11/12] Hisilicon: remove platform specific PciHostBridge Heyi Guo
2018-03-30 15:37   ` Ard Biesheuvel
2018-03-21  1:03 ` [PATCH edk2-platforms 12/12] Hisilicon/PlatformPciLib: clear redundant felds in RESOURCE_APPETURE Heyi Guo
2018-03-28  1:05 ` [PATCH edk2-platforms 00/12] Hisilicon/D0x: Switch to generic PciHostBridge Guo Heyi
2018-03-28  9:43   ` Ard Biesheuvel
2018-03-29  0:20     ` Guo Heyi
2018-03-30 15:40       ` Ard Biesheuvel
2018-03-31  1:37         ` Guo Heyi
2018-04-13  2:05           ` Guo Heyi [this message]
2018-04-13  7:19             ` Ard Biesheuvel
2018-04-16 13:57               ` Guo Heyi
2018-04-17  1:20                 ` Guo Heyi
2018-04-17  1:44                   ` Guo Heyi
2018-05-31  1:02                     ` heyi.guo
2018-06-07 11:11                   ` Ard Biesheuvel
2018-06-22 12:58                     ` gary guo
2018-06-22 14:08                       ` Ard Biesheuvel
2018-06-24 11:22                         ` Ard Biesheuvel

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