From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::22d; helo=mail-pg0-x22d.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x22d.google.com (mail-pg0-x22d.google.com [IPv6:2607:f8b0:400e:c05::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 44FB12274F3C7 for ; Thu, 12 Apr 2018 19:05:57 -0700 (PDT) Received: by mail-pg0-x22d.google.com with SMTP id b9so1219882pgf.6 for ; Thu, 12 Apr 2018 19:05:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:date:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=iOuL94Ae/JbY/m6UEh0gUOF/JQ92wTMhEP5eCK4lkgE=; b=Ra3bUUgJYBrox419hc5hnd8r7xQG4rZam5EqzsLg+hRU8BG/+tyIiAB3jZq8oHboA6 02l9CoaIstzKw3o0cmiccLtFWlGjudqTMM83I34DEhhgMKRJdgEVBpHMnOP6pieFi2mV +0P+vz4iWNZHaCwaXqz+qCLu7r1LhbFHLW544= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:date:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=iOuL94Ae/JbY/m6UEh0gUOF/JQ92wTMhEP5eCK4lkgE=; b=CnwckazAtWwSX5Q2Q1lyY1iropkcipiSNWz0+LQ6GNrPty5D6w7IBInviq/oBDsvQN RliIfCgtWeupX0UYMxj2ZqYa0PbqFKRtn+PP8mR1jURJh0fsBhwc8MJDNKXRaMfwFIy5 1A6OwrPm1F54w7rgNFwZN9GRkOsGcKv/fqhuTRNlpTmuCamW9v4VWBVZiWp+vRH9nVm3 udaUmK83/LoD03Ujn75u+hQ45ZCD6KyZ4szbBR56qVe8Aq8IXE/JTpwKDJ/aPN+bwcPu K6y0UOjFXvM/qiSvs6ZS7cgW9d37c8pvLQE9j5G/0TsBSpbDVHG07YZHrqUacqDeN47R bM6A== X-Gm-Message-State: ALQs6tDEYryY6EvjvTgIJXyEpZbalfmCpjIXNsEMHBldWmH4qFi7hTag FTq2i7jogYCFHnstEI6DA44DDQ== X-Google-Smtp-Source: AIpwx491V5oZEGO9v8FlZKGu4FI+hbSOfn6mURnf2wrfa2VZUOAR0JzpphyGHh3AlPHs8IgNeGAVFA== X-Received: by 10.99.142.201 with SMTP id k192mr2528283pge.278.1523585157573; Thu, 12 Apr 2018 19:05:57 -0700 (PDT) Received: from SZX1000114654 ([45.56.152.120]) by smtp.gmail.com with ESMTPSA id k9sm8029203pgo.30.2018.04.12.19.05.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Apr 2018 19:05:56 -0700 (PDT) From: Guo Heyi X-Google-Original-From: Guo Heyi Date: Fri, 13 Apr 2018 10:05:53 +0800 To: Guo Heyi Cc: Ard Biesheuvel , Leif Lindholm , "edk2-devel@lists.01.org" , Michael D Kinney , Haojian Zhuang Message-ID: <20180413020553.GB119834@SZX1000114654> References: <1521594198-52523-1-git-send-email-heyi.guo@linaro.org> <20180328010531.GA69547@SZX1000114654> <20180329002050.GB97590@SZX1000114654> <20180331013747.GA106704@SZX1000114654> MIME-Version: 1.0 In-Reply-To: <20180331013747.GA106704@SZX1000114654> User-Agent: Mutt/1.5.24 (2015-08-30) Subject: Re: [PATCH edk2-platforms 00/12] Hisilicon/D0x: Switch to generic PciHostBridge X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Apr 2018 02:05:58 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ard, Any comments? Anyway we can modify the code if you insist on using an intermediate CPU IO address space. Thanks, Heyi On Sat, Mar 31, 2018 at 09:37:47AM +0800, Guo Heyi wrote: > Hi Ard, > > Thanks for your time of reviewing the patches. > Please see my opinions below. > > On Fri, Mar 30, 2018 at 05:40:20PM +0200, Ard Biesheuvel wrote: > > On 29 March 2018 at 02:20, Guo Heyi wrote: > > > On Wed, Mar 28, 2018 at 10:43:41AM +0100, Ard Biesheuvel wrote: > > >> On 28 March 2018 at 02:05, Guo Heyi wrote: > > >> > Hi Leif, Ard, > > >> > > > >> > Any comments for this series of patches? > > >> > > > >> > > >> Hello Heyi, > > >> > > >> Thanks for sending these patches. Leif is at the plugfest, but I will > > >> look at these before the end of the week. > > > > > > Forgot the plugfest as I am not attending :) > > > > Hello Heyi, > > > > I think the series looks mostly fine in general, but there are two > > things that I'd like you to change (as noted in my replies): > > - please split the PCI to CPU I/O translation from the CPU I/O to CPU > > MMIO translation > > I heard that OS did the same as you indicated, but the reasons of why I > translated IO address into memory address in PCI host bridge are like below: > > 1. If we add an intermediate level of "CPU IO address space", it makes things a > little more complicated but I don't see any real benefit. If we just make a > simple policy that on ARM/AARCH64 CPU IO address is equal to CPU memory address, > we can even use a unified CPU IO driver for all ARM/AARCH64 platforms, while the > translation is covered by PCI host bridge driver. > > 2. From hardware perspective, the translation is done by PCIe ATU; for IO bar > access, the address from CPU to ATU is a CPU memory address, not an intermediate > CPU IO address; the intermediate CPU IO address is a totally logical concept, > and it also splits ATU function into separate drivers (CPU IO protocol driver > also sees part of ATU function). > > Please let me know if my understanding is not right. > > > - please fix the APPETURE spelling (in whichever way is most > > convenient for you: separate patch at the beginning, at the end, etc > > etc) > > Nice catch :) will fix that. > > Thanks, > > Heyi