From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: edk2-devel@lists.01.org
Cc: leif.lindholm@linaro.org, jaswinder.singh@linaro.org,
masahisa.kojima@linaro.org,
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: [PATCH edk2-platforms] Silicon/Socionext/SynQuacer: update PHY reference clock rate
Date: Mon, 16 Apr 2018 13:00:58 +0200 [thread overview]
Message-ID: <20180416110058.16952-1-ard.biesheuvel@linaro.org> (raw)
As reported by Kojima-san, the PHY reference clock value we use in our
ACPI and DT descriptions is out of sync with the hardware. Replace
125 MHz with 250 MHz throughout.
Cc: Masahisa Kojima <masahisa.kojima@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Kojima-san,
Please confirm that the modification to ogma_config.h is correct.
Thanks,
Ard.
Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 2 +-
Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 4 ++--
Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl
index b6f6c4360029..3f73c191d4d6 100644
--- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl
+++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl
@@ -162,7 +162,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR",
Package (2) { "phy-channel", FixedPcdGet32 (PcdNetsecPhyAddress) },
Package (2) { "max-speed", 1000 },
Package (2) { "max-frame-size", 9000 },
- Package (2) { "socionext,phy-clock-frequency", 125000000 },
+ Package (2) { "socionext,phy-clock-frequency", 250000000 },
}
})
}
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
index 6e93c6ae16a8..f6887329f6c7 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
@@ -420,9 +420,9 @@
reg-shift = <2>;
};
- clk_netsec: refclk125mhz {
+ clk_netsec: refclk250mhz {
compatible = "fixed-clock";
- clock-frequency = <125000000>;
+ clock-frequency = <250000000>;
#clock-cells = <0>;
};
diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h
index 1caf64e30623..f6ec9b30ec8e 100644
--- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h
+++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h
@@ -16,8 +16,8 @@
#ifndef OGMA_CONFIG_H
#define OGMA_CONFIG_H
-#define OGMA_CONFIG_CLK_HZ 125000000UL
-#define OGMA_CONFIG_GMAC_CLK_HZ 125000000UL
+#define OGMA_CONFIG_CLK_HZ 250000000UL
+#define OGMA_CONFIG_GMAC_CLK_HZ 250000000UL
#define OGMA_CONFIG_CHECK_CLK_SUPPLY
#define OGMA_CONFIG_USE_READ_GMAC_STAT
--
2.17.0
next reply other threads:[~2018-04-16 11:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-16 11:00 Ard Biesheuvel [this message]
2018-04-16 11:25 ` [PATCH edk2-platforms] Silicon/Socionext/SynQuacer: update PHY reference clock rate Masahisa Kojima
2018-04-19 11:15 ` Ard Biesheuvel
2018-04-19 14:53 ` Masahisa Kojima
2018-04-19 15:38 ` Leif Lindholm
2018-04-26 17:05 ` Ard Biesheuvel
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