>From guoheyi@huawei.com Tue Apr 17 09:40:07 2018 Delivered-To: heyi.guo@linaro.org Received: by 10.103.107.2 with SMTP id g2csp1147351vsc; Mon, 16 Apr 2018 18:40:07 -0700 (PDT) X-Google-Smtp-Source: AIpwx49xa2EjXi3IIuqoYaJ9ZR+KlZePkYWmAvMpJl534IXT0zWt/Jd5UHxMjyCgas2Aluws+S26 X-Received: by 10.101.97.165 with SMTP id i5mr102113pgv.449.1523929207660; Mon, 16 Apr 2018 18:40:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523929207; cv=none; d=google.com; s=arc-20160816; b=JVhwQqc2tHJH/nbb9J4Q5EAe7efNCva8XlNdyeM1AjecnvMtalXxRiIcVSIp2CTTUb RCfB400z6ay0s7SW96MDtN0D8jezfXLZXyuMQTqYAvpXu7rxEmXGJtKblXaJ303GTvgS kavhZQ7QawTzXzWTjokcARGeyR+mFb9aXT8JKm3jdHVM+Ibsjl0HFYSFrMNFoeyC7EqG EPMbjEvcWolADxpywSCM0s0e4EhIVpGrhi1LgdVeATsyrb6GN8sEscVfb+t0b0gMj6XI Nqg7mMHnKZGJ4vmkJBRV5Gx+nnQbOWKsOCp8YZcVLFs8hyqWFokYsup3wsY1YtktovxU GQUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:message-id:date:subject:cc:to:from :arc-authentication-results; bh=MzafS17Rdgthy05RGe4B87hGASmPkGgjBWmjX1ExxLo=; b=fj+XbZcdH1vGFsHllnQeTc3zRavri5L0Use7rHdCRemtfNojWbY1QJKD6tMVi213fj J9IaKL5/Q3Uh0KLfAR848Whbuj4IiFMw1vRsT8BUvu0QjkCsdJo66ypGdQTqkysdtk2X fdNfNTE+Dfa1du8Yx9RiFCetXrtgCjDXljVzd/JufSlKtC41HjgWjnqC2Jka4N0MOT1W oiBtsqOCjRuVRyb5Rlf7RVstwZ7wz6jXbxj7GYkr85bUFe7LNG8HOKxJYIv1bLyOWw6q KvttRU9MKaVex3HApPoMIIgg+sXj3QD1islzlobdLA/OaRKWXCH0fnXH/NuWnKZ7J1jO Hl7A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of guoheyi@huawei.com designates 45.249.212.32 as permitted sender) smtp.mailfrom=guoheyi@huawei.com Return-Path: Received: from huawei.com ([45.249.212.32]) by mx.google.com with ESMTPS id t3si10564595pgt.547.2018.04.16.18.40.07 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Apr 2018 18:40:07 -0700 (PDT) Received-SPF: pass (google.com: domain of guoheyi@huawei.com designates 45.249.212.32 as permitted sender) client-ip=45.249.212.32; Authentication-Results: mx.google.com; spf=pass (google.com: domain of guoheyi@huawei.com designates 45.249.212.32 as permitted sender) smtp.mailfrom=guoheyi@huawei.com Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 2B03711A12683 for ; Tue, 17 Apr 2018 09:40:04 +0800 (CST) Received: from HGH1000039998.huawei.com (10.184.68.188) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.361.1; Tue, 17 Apr 2018 09:39:59 +0800 From: Heyi Guo To: CC: , , Subject: [PATCH] Hisilicon/Hi161x/PcieInit: fix address overlap Date: Tue, 17 Apr 2018 09:35:22 +0800 Message-ID: <1523928922-9573-1-git-send-email-guoheyi@huawei.com> X-Mailer: git-send-email 2.8.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.184.68.188] X-CFilter-Loop: Reflected Content-Length: 2888 Lines: 55 From: Heyi Guo PCIe IO address ranges are overlapped by configuration address spaces when we set CFG0/CFG1 address range starting from ECAM. It causes access to IO space is routed to configuration space and returned with wrong results. So we limit address space for configuration type 0 starting from BusBase and type 1 from (BusBase + 2), to eliminate the address range overlapping. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c index f2365b5..9a92fea 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c @@ -96,11 +96,12 @@ SetAtuConfig0RW ( { UINTN RbPciBase = Private->RbPciBar; UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1; + UINT64 MemBase = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0, 0, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)MemBase); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(MemBase >> 32)); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); @@ -124,12 +125,13 @@ SetAtuConfig1RW ( { UINTN RbPciBase = Private->RbPciBar; UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1; + UINT64 MemBase = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)MemBase); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(MemBase >> 32)); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); -- 2.8.1