From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::244; helo=mail-wr0-x244.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x244.google.com (mail-wr0-x244.google.com [IPv6:2a00:1450:400c:c0c::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2F2C92268479E for ; Wed, 18 Apr 2018 11:43:16 -0700 (PDT) Received: by mail-wr0-x244.google.com with SMTP id q13-v6so7481874wre.3 for ; Wed, 18 Apr 2018 11:43:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=+bTDD6Lg3S+i6oGoCKFl0ZU1MV9YqW1Rb65NcXFxfhc=; b=UoQ/B5QoP515SVMNNDLLnrITDP4TY7eiFQxJctAHru/uGyZJ14d0mDq/RtSkvMGkTe TJ52k1AO0VL7+tgy4ptDo5VW81RRO2451IRYI4lTZyL5GV4yvMWezVSdnyuWqBTuq5Xa p2v9pVZYo5sJOndoB+axdAtNfHlSg0Qp58v6s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=+bTDD6Lg3S+i6oGoCKFl0ZU1MV9YqW1Rb65NcXFxfhc=; b=DPPAVZJaMPNAcXYrqaOpDrrGxeiQ6lIvjSEVyQOaxYQxYeXLyYM1L2PIYC7dvJQkP/ o+JzyZS9wQ7zCe6q/CaZ0Hkzn+t+1MCIcgYMGQgrmMN2dcHZDrgFFsERxFZPvg7r2YxY KCmp0BESF8wFLb6XKrAk+dLb3Q4r5rnLZZJQQPRC0NIQ/aoncF7j6CFZij+cQI6CRf3h 9XSzH36IlkOo6cFA3vncqRW+Xb4IvZNfZjqgVLTF1QJR5FrzfdKxf0J3l5f+HIVzASjt UVtOrl4MaS0h6os/iWgaBm4icO4YATf3p9u2P/VU9avo02fuPRaPGL1dQV2Ls9k8Gfx3 n03Q== X-Gm-Message-State: ALQs6tBeRw5ysk/h9bllAO7WZeg4O9WeHfxBO9FZdvFNIiS+8OFAPxtl Tp2JGLjR1iMoMMRH7txBwjpgMg== X-Google-Smtp-Source: AIpwx4/hHR4o9TroixeSiSZSNQQ5sd+dBtE9o7OfDWAcEw5SV9ZnVObN086oJuXejoTZZWd1ERqycA== X-Received: by 10.28.69.154 with SMTP id l26mr2723188wmi.27.1524076995489; Wed, 18 Apr 2018 11:43:15 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id v111-v6sm2563444wrb.30.2018.04.18.11.43.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Apr 2018 11:43:14 -0700 (PDT) Date: Wed, 18 Apr 2018 19:43:12 +0100 From: Leif Lindholm To: Meenakshi Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, udit.kumar@nxp.com, v.sethi@nxp.com Message-ID: <20180418184312.35uwlykv66d5aqqq@bivouac.eciton.net> References: <1518771035-6733-1-git-send-email-meenakshi.aggarwal@nxp.com> <1518771035-6733-14-git-send-email-meenakshi.aggarwal@nxp.com> MIME-Version: 1.0 In-Reply-To: <1518771035-6733-14-git-send-email-meenakshi.aggarwal@nxp.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 13/39] LS1043/FpgaLib : Add support for FpgaLib. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Apr 2018 18:43:17 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Feb 16, 2018 at 02:20:09PM +0530, Meenakshi wrote: > From: Meenakshi Aggarwal > > FpgaLib export FPGA_READ and FPGA_WRITE function and > provide a function to print Board personality. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Meenakshi Aggarwal If you send a new version, can you fix the indentation in the last few DEBUG statements? If not, I can fix that up before committing. Reviewed-by: Leif Lindholm > --- > .../NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h | 79 ++++++++++++ > .../NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c | 142 +++++++++++++++++++++ > .../NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 +++++ > 3 files changed, 252 insertions(+) > create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h > create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c > create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf > > diff --git a/Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h b/Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h > new file mode 100644 > index 0000000..3f55a02 > --- /dev/null > +++ b/Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h > @@ -0,0 +1,79 @@ > +/** FpgaLib.h > +* Header defining the LS1043a Fpga specific constants (Base addresses, sizes, flags) > +* > +* Copyright 2017 NXP > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#ifndef __LS1043A_FPGA_H__ > +#define __LS1043A_FPGA_H__ > + > +/* > + * FPGA register set of LS1043ARDB board-specific. > + */ > +typedef struct { > + UINT8 FpgaVersionMajor; /* 0x0 - FPGA Major Revision Register */ > + UINT8 FpgaVersionMinor; /* 0x1 - FPGA Minor Revision Register */ > + UINT8 PcbaVersion; /* 0x2 - PCBA Revision Register */ > + UINT8 SystemReset; /* 0x3 - system reset register */ > + UINT8 SoftMuxOn; /* 0x4 - Switch Control Enable Register */ > + UINT8 RcwSource1; /* 0x5 - Reset config word 1 */ > + UINT8 RcwSource2; /* 0x6 - Reset config word 1 */ > + UINT8 Vbank; /* 0x7 - Flash bank selection Control */ > + UINT8 SysclkSelect; /* 0x8 - System clock selection Control */ > + UINT8 UartSel; /* 0x9 - Uart selection Control */ > + UINT8 Sd1RefClkSel; /* 0xA - Serdes1 reference clock selection Control */ > + UINT8 TdmClkMuxSel; /* 0xB - TDM Clock Mux selection Control */ > + UINT8 SdhcSpiCsSel; /* 0xC - SDHC/SPI Chip select selection Control */ > + UINT8 StatusLed; /* 0xD - Status Led */ > + UINT8 GlobalReset; /* 0xE - Global reset */ > +} FPGA_REG_SET; > + > +UINT8 > +FpgaRead ( > + UINTN Reg > + ); > + > +VOID > +FpgaWrite ( > + UINTN Reg, > + UINT8 Value > + ); > + > +VOID > +FpgaRevBit ( > + UINT8 *Value > + ); > + > +VOID > +FpgaInit ( > + VOID > + ); > + > +VOID > +PrintBoardPersonality ( > + VOID > + ); > + > +#define FPGA_BASE_PHYS 0x7fb00000 > + > +#define SRC_VBANK 0x25 > +#define SRC_NAND 0x106 > +#define SRC_QSPI 0x44 > +#define SRC_SD 0x40 > + > +#define SERDES_FREQ1 "100.00 MHz" > +#define SERDES_FREQ2 "156.25 MHz" > + > +#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg)) > +#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), Value) > + > +#endif > diff --git a/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c b/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c > new file mode 100644 > index 0000000..99d514d > --- /dev/null > +++ b/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c > @@ -0,0 +1,142 @@ > +/** @FpgaLib.c > + Fpga Library for LS1043A-RDB board, containing functions to > + program and read the Fpga registers. > + > + FPGA is connected to IFC Controller and so MMIO APIs are used > + to read/write FPGA registers > + > + Copyright 2017 NXP > + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > + > +/** > + Function to read FPGA register. > + > + @param Reg Register offset of FPGA to read. > + > +**/ > +UINT8 > +FpgaRead ( > + IN UINTN Reg > + ) > +{ > + VOID *Base; > + > + Base = (VOID *)FPGA_BASE_PHYS; > + > + return MmioRead8 ((UINTN)(Base + Reg)); > +} > + > +/** > + Function to write FPGA register. > + > + @param Reg Register offset of FPGA to write. > + @param Value Value to be written. > + > +**/ > +VOID > +FpgaWrite ( > + IN UINTN Reg, > + IN UINT8 Value > + ) > +{ > + VOID *Base; > + > + Base = (VOID *)FPGA_BASE_PHYS; > + > + MmioWrite8 ((UINTN)(Base + Reg), Value); > +} > + > +/** > + Function to reverse the number. > + > + @param *Value pointer to number to reverse. > + > + @retval *Value reversed value. > + > +**/ > +VOID > +FpgaRevBit ( > + OUT UINT8 *Value > + ) > +{ > + UINT8 Rev; > + UINT8 Val; > + UINTN Index; > + > + Val = *Value; > + Rev = Val & 1; > + for (Index = 1; Index <= 7; Index++) { > + Val >>= 1; > + Rev <<= 1; > + Rev |= Val & 1; > + } > + > + *Value = Rev; > +} > + > +/** > + Function to print board personality. > + > +**/ > +VOID > +PrintBoardPersonality ( > + VOID > + ) > +{ > + UINT8 RcwSrc1; > + UINT8 RcwSrc2; > + UINT32 RcwSrc; > + UINT32 Sd1RefClkSel; > + > + RcwSrc1 = FPGA_READ(RcwSource1); > + RcwSrc2 = FPGA_READ(RcwSource2); > + FpgaRevBit (&RcwSrc1); > + RcwSrc = RcwSrc1; > + RcwSrc = (RcwSrc << 1) | RcwSrc2; > + > + switch (RcwSrc) { > + case SRC_VBANK: > + DEBUG ((DEBUG_INFO, "vBank: %d\n", FPGA_READ(Vbank))); > + break; > + case SRC_NAND: > + DEBUG ((DEBUG_INFO, "NAND\n")); > + break; > + case SRC_QSPI: > + DEBUG ((DEBUG_INFO, "QSPI vBank %d\n", FPGA_READ(Vbank))); > + break; > + case SRC_SD: > + DEBUG ((DEBUG_INFO, "SD\n")); > + break; > + default: > + DEBUG ((DEBUG_INFO, "Invalid setting of SW5\n")); > + break; > + } > + > + DEBUG ((DEBUG_INFO, "FPGA: V%x.%x\nPCBA: V%x.0\n", > + FPGA_READ(FpgaVersionMajor), > + FPGA_READ(FpgaVersionMinor), > + FPGA_READ(PcbaVersion))); > + > + DEBUG ((DEBUG_INFO, "SERDES Reference Clocks:\n")); > + > + Sd1RefClkSel = FPGA_READ(Sd1RefClkSel); > + DEBUG((DEBUG_INFO, "SD1_CLK1 = %a, SD1_CLK2 = %a\n", > + Sd1RefClkSel ? SERDES_FREQ2 : SERDES_FREQ1, SERDES_FREQ1)); > + > + return; > +} > diff --git a/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf > new file mode 100644 > index 0000000..39e9bde > --- /dev/null > +++ b/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf > @@ -0,0 +1,31 @@ > +# @FpgaLib.inf > +# > +# Copyright 2017 NXP > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > + > +[Defines] > + INF_VERSION = 0x0001000A > + BASE_NAME = FpgaLib > + FILE_GUID = 5962d040-8b8a-11df-9a71-0002a5d5c51b > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = FpgaLib > + > +[Sources.common] > + FpgaLib.c > + > +[Packages] > + MdePkg/MdePkg.dec > + Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec > + Silicon/NXP/NxpQoriqLs.dec > + > +[LibraryClasses] > + BaseLib > + IoLib > -- > 1.9.1 >