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[2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id f10-v6sm3162837wrg.0.2018.04.19.03.00.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 19 Apr 2018 03:00:52 -0700 (PDT) Date: Thu, 19 Apr 2018 11:00:50 +0100 From: Leif Lindholm To: Meenakshi Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, udit.kumar@nxp.com, v.sethi@nxp.com, Vabhav Message-ID: <20180419100050.bl4tdllduqmet6eo@bivouac.eciton.net> References: <1518771035-6733-1-git-send-email-meenakshi.aggarwal@nxp.com> <1518771035-6733-19-git-send-email-meenakshi.aggarwal@nxp.com> MIME-Version: 1.0 In-Reply-To: <1518771035-6733-19-git-send-email-meenakshi.aggarwal@nxp.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 18/39] Silicon/NXP:Add LS1046ARDB SoCLib Support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Apr 2018 10:00:55 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Feb 16, 2018 at 02:20:14PM +0530, Meenakshi wrote: > From: Meenakshi Aggarwal > > On LS1046A NXP SoC,Provide Functions to initialize peripherals > ,print board, soc information. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Vabhav > --- > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 + > Silicon/NXP/Chassis/Chassis.c | 1 + > Silicon/NXP/Chassis/Chassis.h | 1 + > Silicon/NXP/Chassis/Chassis2/Soc.c | 51 ++++++++++++++++++++- > Silicon/NXP/Chassis/LS1043aSocLib.inf | 2 + > Silicon/NXP/Chassis/LS1046aSocLib.inf | 51 +++++++++++++++++++++ > Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 ++++++++++++++++++++++ > Silicon/NXP/LS1046A/LS1046A.dec | 22 +++++++++ > Silicon/NXP/LS1046A/LS1046A.dsc | 68 ++++++++++++++++++++++++++++ > Silicon/NXP/NxpQoriqLs.dec | 2 + > 10 files changed, 253 insertions(+), 1 deletion(-) > create mode 100644 Silicon/NXP/Chassis/LS1046aSocLib.inf > create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h > create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec > create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc > > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc > index 7708e0a..b2b514e 100644 > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc > @@ -59,6 +59,7 @@ > gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500 > gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE > gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1 > + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|TRUE > > # > # I2C controller Pcds > diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c > index 9f2928b..ce07fdc 100644 > --- a/Silicon/NXP/Chassis/Chassis.c > +++ b/Silicon/NXP/Chassis/Chassis.c > @@ -44,6 +44,7 @@ GurRead ( > */ > STATIC CPU_TYPE CpuTypeList[] = { > CPU_TYPE_ENTRY (LS1043A, LS1043A, 4), > + CPU_TYPE_ENTRY (LS1046A, LS1046A, 4), > }; > > /* > diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h > index 4bdb4d0..0beb44c 100644 > --- a/Silicon/NXP/Chassis/Chassis.h > +++ b/Silicon/NXP/Chassis/Chassis.h > @@ -56,6 +56,7 @@ CpuMaskNext ( > > #define SVR_WO_E 0xFFFFFE > #define SVR_LS1043A 0x879200 > +#define SVR_LS1046A 0x870700 > > #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf) > #define SVR_MINOR(svr) (((svr) >> 0) & 0xf) > diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chassis2/Soc.c > index 17de7e4..658df2d 100644 > --- a/Silicon/NXP/Chassis/Chassis2/Soc.c > +++ b/Silicon/NXP/Chassis/Chassis2/Soc.c > @@ -17,6 +17,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -139,6 +140,44 @@ GetSysInfo ( > } > > /** > + Function to select pins depending upon pcd using supplemental > + configuration unit(SCFG) extended RCW controlled pinmux control > + register which contains the bits to provide pin multiplexing control. > + This register is reset on HRESET. > + **/ > +VOID > +ConfigScfgMux (VOID) > +{ > + CCSR_SCFG *Scfg; > + UINT32 UsbPwrFault; > + > + Scfg = (VOID *)PcdGet64 (PcdScfgBaseAddr); > + // Configures functionality of the IIC3_SCL to USB2_DRVVBUS > + // Configures functionality of the IIC3_SDA to USB2_PWRFAULT > + > + // LS1043A > + // Configures functionality of the IIC4_SCL to USB3_DRVVBUS > + // Configures functionality of the IIC4_SDA to USB3_PWRFAULT > + > + // LS1046A > + // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA > + if (PcdGetBool (PcdMuxToUsb3)) { > + BeMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_SELCR_USB); > + } else { > + BeMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB); > + } > + BeMmioWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, CCSR_SCFG_USBDRVVBUS_SELCR_USB1); > + UsbPwrFault = (CCSR_SCFG_USBPWRFAULT_DEDICATED << > + CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) | > + (CCSR_SCFG_USBPWRFAULT_DEDICATED << > + CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) | > + (CCSR_SCFG_USBPWRFAULT_SHARED << > + CCSR_SCFG_USBPWRFAULT_USB1_SHIFT); Can you change indentation like so?: UsbPwrFault = (CCSR_SCFG_USBPWRFAULT_DEDICATED << CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) | (CCSR_SCFG_USBPWRFAULT_DEDICATED << CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) | (CCSR_SCFG_USBPWRFAULT_SHARED << CCSR_SCFG_USBPWRFAULT_USB1_SHIFT); > + BeMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault); > + BeMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault); > +} > + > +/** > Function to initialize SoC specific constructs > CPU Info > SoC Personality > @@ -170,8 +209,18 @@ SocInit ( > // > PrintRCW (); > PrintSoc (); > - IfcInit(); > + IfcInit (); Please fix the whitespace in the originating patch, even if I missed it on review :) > PrintBoardPersonality (); > + // > + // Due to the extensive functionality present on the chip and the limited number of external > + // signals available, several functional blocks share signal resources through multiplexing. > + // In this case when there is alternate functionality between multiple functional blocks, > + // the signal's function is determined at the chip level (rather than at the block level) > + // typically by a reset configuration word (RCW) option. Some of the signals' function are > + // determined externel to RCW at Power-on Reset Sequence. > + // > + ConfigScfgMux (); > + > > return; > } > diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS1043aSocLib.inf > index d01b353..71fa0a8 100644 > --- a/Silicon/NXP/Chassis/LS1043aSocLib.inf > +++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf > @@ -47,3 +47,5 @@ > gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled > gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian > gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3 > diff --git a/Silicon/NXP/Chassis/LS1046aSocLib.inf b/Silicon/NXP/Chassis/LS1046aSocLib.inf > new file mode 100644 > index 0000000..11eeb97 > --- /dev/null > +++ b/Silicon/NXP/Chassis/LS1046aSocLib.inf > @@ -0,0 +1,51 @@ > +# @file > +# > +# Copyright 2017 NXP > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +# > + > +[Defines] > + INF_VERSION = 0x0001001A > + BASE_NAME = SocLib > + FILE_GUID = ddd5f950-8816-4d38-8f98-f42b07333f78 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = SocLib > + > +[Packages] > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Silicon/NXP/NxpQoriqLs.dec > + Silicon/NXP/Chassis/Chassis2/Chassis2.dec > + Silicon/NXP/LS1046A/LS1046A.dec Can you sort these packages alphabetically please? > + > +[LibraryClasses] > + BaseLib > + BeIoLib > + DebugLib > + FpgaLib > + IfcLib > + SerialPortLib > + > +[Sources.common] > + Chassis.c > + Chassis2/Soc.c > + SerDes.c > + > +[FixedPcd] > + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString > + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv > + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled > + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian > + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3 Can you sort these Pcds alphabetically please? > diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h b/Silicon/NXP/LS1046A/Include/SocSerDes.h > new file mode 100644 > index 0000000..a0b5576 > --- /dev/null > +++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h > @@ -0,0 +1,55 @@ > +/** @file > + The Header file of SerDes Module > + > + Copyright 2017 NXP > + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > + > +#ifndef __LS1046A_SERDES_H__ > +#define __LS1046A_SERDES_H__ > + > +#include > + > +SERDES_CONFIG SerDes1ConfigTbl[] = { > + /* SerDes 1 */ Indentation should be two spaces, throughout the file. > + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE } }, > + {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE } }, > + {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6 } }, > + {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6 } }, > + {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, SGMII_FM1_DTSEC6 } }, > + {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, > + {} > +}; > + > +SERDES_CONFIG SerDes2ConfigTbl[] = { > + /* SerDes 2 */ > + {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1 } }, > + {0x5559, {PCIE1, PCIE2, PCIE3, SATA } }, > + {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3 } }, > + {0x5506, {PCIE1, PCIE2, NONE, PCIE3 } }, > + {0x0506, {NONE, PCIE2, NONE, PCIE3 } }, > + {0x0559, {NONE, PCIE2, PCIE3, SATA } }, > + {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA } }, > + {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3 } }, > + {} > +}; > + > +SERDES_CONFIG *SerDesConfigTbl[] = { > + SerDes1ConfigTbl, > + SerDes2ConfigTbl > +}; > + > +#endif /* __LS1046A_SERDES_H */ > diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec > new file mode 100644 > index 0000000..e266aad > --- /dev/null > +++ b/Silicon/NXP/LS1046A/LS1046A.dec > @@ -0,0 +1,22 @@ > +# LS1046A.dec > +# > +# Copyright 2017 NXP > +# > +# This program and the accompanying materials are licensed and made available under > +# the terms and conditions of the BSD License which accompanies this distribution. > +# The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +# > + > +[Defines] > + DEC_SPECIFICATION = 0x00010005 0x0001001a / Leif > + > +[Guids.common] > + gNxpLs1046ATokenSpaceGuid = {0x8d7ffac8, 0xb4d5, 0x43c3, {0xaa, 0x27, 0x84, 0xbc, 0x12, 0x01, 0x28, 0x10}} > + > +[Includes] > + Include > diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc b/Silicon/NXP/LS1046A/LS1046A.dsc > new file mode 100644 > index 0000000..9f87028 > --- /dev/null > +++ b/Silicon/NXP/LS1046A/LS1046A.dsc > @@ -0,0 +1,68 @@ > +# LS1046A.dsc > +# LS1046A Soc package. > +# > +# Copyright 2017 NXP > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +# > + > +################################################################################ > +# > +# Pcd Section - list of all EDK II PCD Entries defined by this Platform > +# > +################################################################################ > +[PcdsDynamicDefault.common] > + > + # > + # ARM General Interrupt Controller > + gArmTokenSpaceGuid.PcdGicDistributorBase|0x01410000 > + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01420000 > + > +[PcdsFixedAtBuild.common] > + > + # > + # CCSR Address Space and other attached Memories > + # > + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000 > + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000 > + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000 > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000 > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000 > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000 > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000 > + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA > + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000 > + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000 > + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000 > + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000 > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000 > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000 > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000 > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000 > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 > + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000 > + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000 > + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000 > + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000 > + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000 > + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000 > + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000 > + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000 > + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000 > + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000 > + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000 > + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000 > + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 > + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000 > + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000 > + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000 > + > +## > diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec > index 43d0a71..39753e7 100644 > --- a/Silicon/NXP/NxpQoriqLs.dec > +++ b/Silicon/NXP/NxpQoriqLs.dec > @@ -30,6 +30,7 @@ > gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0|UINT32|0x00000001 > gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000002 > gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000003 > + gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT32|0x00000004 > > # > # Pcds for base address and size > @@ -101,6 +102,7 @@ > # > gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250 > gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251 > + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE|BOOLEAN|0x00000253 > > # > # Clock PCDs > -- > 1.9.1 >