From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 792CB21E0811F for ; Thu, 19 Apr 2018 08:38:34 -0700 (PDT) Received: by mail-wr0-x241.google.com with SMTP id d1-v6so15253112wrj.13 for ; Thu, 19 Apr 2018 08:38:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=7oFQLB8NR/3OAWCZ98aaHl6cwhcGND7f5x3L35Ke6Kc=; b=htwOrmv+cE9UL/U10y5bYjNvUJbRKvs3+aQ1RLCDDg57cmV5XUAwNinFBs6JzQtHyV pQmJljNETyCzjAO6QrPmlIK9i/3mNUlPONJtKDRrOupaxv0RQMcKlUY/4dfxduE2GbS7 mnF60sxpfwDkBEGt5L4R2Fiup+41PvBeTVK7I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=7oFQLB8NR/3OAWCZ98aaHl6cwhcGND7f5x3L35Ke6Kc=; b=PXLK3WPfH5MuN0wAryOeVzR4zUQEC9Uc9PkN+QyZ+aw3BlUJYiix5+cCqYpQn6wSd/ yNSnFfF4Wd3giVeDbKXwVgYrf/DMTgQ/PYdzm97TkptUKxf7eVyq6Y0cvEWNILtdXCII nh7mzm60xQcTL8veVj+zGPNujuhmccQR8QooBEt5Tw75GIQCAtkKPsl9RzvvJqPJ5Xon RchwdHKeafpAzf30AWfR7YrNH6xGp68s03Jh4YD5sp6aLH9v1y5w58/djeGcRwS9yTIn ibfq1A0uD44g+4Kt6I2NvsvJv+wxh0lWTAjv5wlaJALtHefKJLEagbbwiYZAtpEF49yM 0eLQ== X-Gm-Message-State: ALQs6tAHspiNHf7gg4UvLwSiUiYMoV95ggXZUgmHWu0ElR8EO6X2bmS4 dHJx7ITqHhCFWs2IVo/uD+kDMw== X-Google-Smtp-Source: AIpwx48i6Xi8uoLKZBFxpxexdG2t1E4atUqGwbJFPkAv85XHor6oEw0krh8KyVLKS7ShiPmBidaomA== X-Received: by 10.28.53.194 with SMTP id c185mr5195503wma.27.1524152312900; Thu, 19 Apr 2018 08:38:32 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id g75sm5465172wmc.47.2018.04.19.08.38.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 19 Apr 2018 08:38:31 -0700 (PDT) Date: Thu, 19 Apr 2018 16:38:30 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, jaswinder.singh@linaro.org, masahisa.kojima@linaro.org Message-ID: <20180419153830.jfyl4uk2mbwunwsk@bivouac.eciton.net> References: <20180416110058.16952-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180416110058.16952-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms] Silicon/Socionext/SynQuacer: update PHY reference clock rate X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Apr 2018 15:38:34 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Apr 16, 2018 at 01:00:58PM +0200, Ard Biesheuvel wrote: > As reported by Kojima-san, the PHY reference clock value we use in our > ACPI and DT descriptions is out of sync with the hardware. Replace > 125 MHz with 250 MHz throughout. > > Cc: Masahisa Kojima > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- > Kojima-san, > > Please confirm that the modification to ogma_config.h is correct. > > Thanks, > Ard. > > Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 2 +- > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 4 ++-- > Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h | 4 ++-- > 3 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > index b6f6c4360029..3f73c191d4d6 100644 > --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > @@ -162,7 +162,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", > Package (2) { "phy-channel", FixedPcdGet32 (PcdNetsecPhyAddress) }, > Package (2) { "max-speed", 1000 }, > Package (2) { "max-frame-size", 9000 }, > - Package (2) { "socionext,phy-clock-frequency", 125000000 }, > + Package (2) { "socionext,phy-clock-frequency", 250000000 }, > } > }) > } > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > index 6e93c6ae16a8..f6887329f6c7 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > @@ -420,9 +420,9 @@ > reg-shift = <2>; > }; > > - clk_netsec: refclk125mhz { > + clk_netsec: refclk250mhz { > compatible = "fixed-clock"; > - clock-frequency = <125000000>; > + clock-frequency = <250000000>; > #clock-cells = <0>; > }; > > diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > index 1caf64e30623..f6ec9b30ec8e 100644 > --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > @@ -16,8 +16,8 @@ > #ifndef OGMA_CONFIG_H > #define OGMA_CONFIG_H > > -#define OGMA_CONFIG_CLK_HZ 125000000UL > -#define OGMA_CONFIG_GMAC_CLK_HZ 125000000UL > +#define OGMA_CONFIG_CLK_HZ 250000000UL > +#define OGMA_CONFIG_GMAC_CLK_HZ 250000000UL > #define OGMA_CONFIG_CHECK_CLK_SUPPLY > > #define OGMA_CONFIG_USE_READ_GMAC_STAT > -- > 2.17.0 >