* [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs
@ 2018-02-16 8:49 Meenakshi
2018-02-16 8:49 ` [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs Meenakshi
` (41 more replies)
0 siblings, 42 replies; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:49 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
We have combined all patches which were sent earlier[in multiple patch sets]
in one patch set incorporating review comments recieved till now.
This will help in keeping track of patches.
Following patches will add support of NXP SoCs[LS1043, LS1046 and LS2088] in edk2-platforms.
Our directory structure will be:
|-- Platform
| |-- NXP
| | |-- build.sh
| | |-- Env.cshrc
| | |-- FVRules.fdf.inc
| | |-- LS1043aRdbPkg
| | | |-- Include
| | | | `-- Library
| | | |-- Library
| | | |-- LS1043aRdbPkg.dec
| | | |-- LS1043aRdbPkg.dsc
| | | |-- LS1043aRdbPkg.fdf
| | | `-- VarStore.fdf.inc
| | |-- LS1046aRdbPkg
| | | |-- Include
| | | | `-- Library
| | | |-- Library
| | | |-- LS1046aRdbPkg.dec
| | | |-- LS1046aRdbPkg.dsc
| | | `-- LS1046aRdbPkg.fdf
| | |-- LS2088aRdbPkg
| | | |-- Include
| | | | `-- Library
| | | |-- Library
| | | |-- LS2088aRdbPkg.dec
| | | |-- LS2088aRdbPkg.dsc
| | | |-- LS2088aRdbPkg.fdf
| | | `-- VarStore.fdf.inc
| | |-- NxpQoriqLs.dsc
| | `-- Readme.md
|-- Silicon
| |-- Maxim
| | `-- Library
| | |-- Ds1307RtcLib
| | | |-- Ds1307RtcLib.dec
| | `-- Ds3232RtcLib
| | |-- Ds3232RtcLib.dec
| |-- NXP
| | |-- Chassis
| | | |-- Chassis2
| | | | |-- Chassis2.dec
| | | |-- Chassis3
| | | | |-- Chassis3.dec
| | |-- Drivers
| | |-- Include
| | | |-- Library
| | |-- Library
| | |-- LS1043A
| | | |-- Include
| | | |-- LS1043A.dec
| | | `-- LS1043A.dsc
| | |-- LS1046A
| | | |-- Include
| | | |-- LS1046A.dec
| | | `-- LS1046A.dsc
| | |-- LS2088A
| | | |-- Include
| | | |-- LS2088A.dec
| | | `-- LS2088A.dsc
| | `-- NxpQoriqLs.dec
In Silicon/NXP, we are keeping our SoC specific information and all Drivers and Library
which are used by SoCs.
Platform/NXP/ will host our board packages and build script.
Board specific libraries and header files will reside inside board package.
This patch add support of LS1043, LS1046 and LS2088 RDB boards.
Looking forward for your kind support in upstreaming our boards in edk2-platforms.
Meenakshi Aggarwal (23):
Silicon/NXP: Add support for Big Endian Mmio APIs
Silicon/NXP : Add support for Watchdog driver
SocLib : Add support for initialization of peripherals
Silicon/NXP : Add support for DUART library
Silicon/NXP: Add support for I2c driver
Silicon/Maxim : Add support for DS1307 RTC library
Platform/NXP: Add support for ArmPlatformLib
Compilation : Add the fdf, dsc and dec files.
Build : Add build script and environment script
IFC : Add Header file for IFC controller
LS1043/BoardLib : Add support for LS1043 BoardLib.
Silicon/NXP : Add support of IfcLib
LS1043/FpgaLib : Add support for FpgaLib.
LS1043 : Enable support of FpgaLib.
Silicon/NXP : Add support of NorFlashLib
Silicon/NXP : Add NOR driver.
LS1043 : Enable NOR driver for LS1043aRDB package.
Silicon/NXP:Add LS1046ARDB SoCLib Support
Platform/NXP: LS1046A RDB Board Library
Platform/NXP: LS1046 RDB Board FPGA library
Compilation: Update the fdf, dsc and dec files.
DWC3 : Add DWC3 USB controller initialization driver.
LS2088 : Enable support of USB controller
Vabhav (8):
Silicon/NXP:Add support for PCF2129 Real Time Clock Library
Platform/NXP: Add ArmPlatformLib for LS1046A
Platform/NXP: Compilation for LS1046A RDB Board
Silicon/NXP: Implement PciSegmentLib to support multiple RCs
Silicon/NXP: Implement PciHostBridgeLib support
Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
Platform/NXP:PCIe enablement for LS1046A RDB
Platform/NXP:PCIe enablement for LS2088A RDB
Wasim Khan (8):
Silicon/NXP:SocLib support for initialization of peripherals
Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB
Silicon/Maxim: DS3232 RTC Library Support
Compilation : Add the fdf, dsc and dec files
Platform/NXP: LS2088A RDB Board Library
Platform/NXP: LS2088 RDB Board FPGA library
LS2088 : Enable support of FpgaLib
LS2088ARDB: Enable NOR driver and Runtime Services
Platform/NXP/Env.cshrc | 78 ++
Platform/NXP/FVRules.fdf.inc | 99 +++
.../NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h | 109 +++
.../NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h | 79 ++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 29 +
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 118 +++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 213 ++++++
.../NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c | 69 ++
.../LS1043aRdbPkg/Library/BoardLib/BoardLib.inf | 31 +
.../NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c | 142 ++++
.../NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 +
.../Library/PlatformLib/ArmPlatformLib.c | 105 +++
.../Library/PlatformLib/ArmPlatformLib.inf | 69 ++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 38 +
.../Library/PlatformLib/NxpQoriqLsMem.c | 158 ++++
Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 98 +++
.../NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h | 83 +++
.../NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h | 97 +++
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec | 29 +
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 109 +++
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 206 ++++++
.../NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c | 61 ++
.../LS1046aRdbPkg/Library/BoardLib/BoardLib.inf | 31 +
.../NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c | 144 ++++
.../NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf | 32 +
.../Library/PlatformLib/ArmPlatformLib.c | 105 +++
.../Library/PlatformLib/ArmPlatformLib.inf | 68 ++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 35 +
.../Library/PlatformLib/NxpQoriqLsMem.c | 158 ++++
.../NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h | 114 +++
.../NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h | 166 +++++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec | 29 +
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 134 ++++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 224 ++++++
.../NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c | 69 ++
.../LS2088aRdbPkg/Library/BoardLib/BoardLib.inf | 28 +
.../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c | 115 +++
.../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 +
.../Library/PlatformLib/ArmPlatformLib.c | 106 +++
.../Library/PlatformLib/ArmPlatformLib.inf | 79 ++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 35 +
.../Library/PlatformLib/NxpQoriqLsMem.c | 195 +++++
Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc | 99 +++
Platform/NXP/NxpQoriqLs.dsc | 431 +++++++++++
Platform/NXP/Readme.md | 17 +
Platform/NXP/build.sh | 117 +++
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h | 59 ++
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 329 +++++++++
.../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec | 26 +
.../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf | 45 ++
Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h | 49 ++
Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c | 370 ++++++++++
.../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec | 31 +
.../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf | 49 ++
Silicon/NXP/Chassis/Chassis.c | 424 +++++++++++
Silicon/NXP/Chassis/Chassis.h | 162 +++++
Silicon/NXP/Chassis/Chassis2/Chassis2.dec | 19 +
Silicon/NXP/Chassis/Chassis2/SerDes.h | 68 ++
Silicon/NXP/Chassis/Chassis2/Soc.c | 226 ++++++
Silicon/NXP/Chassis/Chassis2/Soc.h | 367 ++++++++++
Silicon/NXP/Chassis/Chassis3/Chassis3.dec | 19 +
Silicon/NXP/Chassis/Chassis3/SerDes.h | 91 +++
Silicon/NXP/Chassis/Chassis3/Soc.c | 196 +++++
Silicon/NXP/Chassis/Chassis3/Soc.h | 149 ++++
Silicon/NXP/Chassis/LS1043aSocLib.inf | 51 ++
Silicon/NXP/Chassis/LS1046aSocLib.inf | 51 ++
Silicon/NXP/Chassis/LS2088aSocLib.inf | 50 ++
Silicon/NXP/Chassis/SerDes.c | 271 +++++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 726 +++++++++++++++++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 65 ++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 55 ++
.../NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c | 258 +++++++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c | 438 +++++++++++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h | 146 ++++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf | 66 ++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c | 805 +++++++++++++++++++++
Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 529 ++++++++++++++
Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 ++
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c | 219 ++++++
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h | 142 ++++
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf | 48 ++
Silicon/NXP/Drivers/WatchDog/WatchDog.c | 459 ++++++++++++
Silicon/NXP/Drivers/WatchDog/WatchDog.h | 39 +
Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf | 47 ++
Silicon/NXP/Include/Bitops.h | 179 +++++
Silicon/NXP/Include/Ifc.h | 420 +++++++++++
Silicon/NXP/Include/Library/BeIoLib.h | 332 +++++++++
Silicon/NXP/Include/Library/IfcLib.h | 23 +
Silicon/NXP/Include/Library/NorFlashLib.h | 77 ++
Silicon/NXP/Include/NorFlash.h | 48 ++
Silicon/NXP/Include/Pcie.h | 143 ++++
Silicon/NXP/LS1043A/Include/SocSerDes.h | 55 ++
Silicon/NXP/LS1043A/LS1043A.dec | 22 +
Silicon/NXP/LS1043A/LS1043A.dsc | 79 ++
Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 ++
Silicon/NXP/LS1046A/LS1046A.dec | 22 +
Silicon/NXP/LS1046A/LS1046A.dsc | 71 ++
Silicon/NXP/LS2088A/Include/SocSerDes.h | 67 ++
Silicon/NXP/LS2088A/LS2088A.dec | 22 +
Silicon/NXP/LS2088A/LS2088A.dsc | 76 ++
Silicon/NXP/Library/BeIoLib/BeIoLib.c | 400 ++++++++++
Silicon/NXP/Library/BeIoLib/BeIoLib.inf | 31 +
Silicon/NXP/Library/DUartPortLib/DUart.h | 128 ++++
Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 370 ++++++++++
Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 41 ++
Silicon/NXP/Library/IfcLib/IfcLib.c | 155 ++++
Silicon/NXP/Library/IfcLib/IfcLib.h | 184 +++++
Silicon/NXP/Library/IfcLib/IfcLib.inf | 38 +
Silicon/NXP/Library/NorFlashLib/CfiCommand.h | 99 +++
Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c | 233 ++++++
Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h | 68 ++
Silicon/NXP/Library/NorFlashLib/NorFlashLib.c | 660 +++++++++++++++++
Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf | 41 ++
Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h | 43 ++
Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c | 330 +++++++++
.../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf | 47 ++
.../Library/PciHostBridgeLib/PciHostBridgeLib.c | 618 ++++++++++++++++
.../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 50 ++
Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 604 ++++++++++++++++
.../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 41 ++
Silicon/NXP/NxpQoriqLs.dec | 148 ++++
121 files changed, 17825 insertions(+)
create mode 100755 Platform/NXP/Env.cshrc
create mode 100644 Platform/NXP/FVRules.fdf.inc
create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
create mode 100755 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
create mode 100644 Platform/NXP/NxpQoriqLs.dsc
create mode 100644 Platform/NXP/Readme.md
create mode 100755 Platform/NXP/build.sh
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
create mode 100644 Silicon/NXP/Chassis/Chassis.c
create mode 100644 Silicon/NXP/Chassis/Chassis.h
create mode 100644 Silicon/NXP/Chassis/Chassis2/Chassis2.dec
create mode 100644 Silicon/NXP/Chassis/Chassis2/SerDes.h
create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.c
create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.h
create mode 100644 Silicon/NXP/Chassis/Chassis3/Chassis3.dec
create mode 100644 Silicon/NXP/Chassis/Chassis3/SerDes.h
create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.c
create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.h
create mode 100644 Silicon/NXP/Chassis/LS1043aSocLib.inf
create mode 100644 Silicon/NXP/Chassis/LS1046aSocLib.inf
create mode 100644 Silicon/NXP/Chassis/LS2088aSocLib.inf
create mode 100644 Silicon/NXP/Chassis/SerDes.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c
create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c
create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h
create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
create mode 100644 Silicon/NXP/Include/Bitops.h
create mode 100644 Silicon/NXP/Include/Ifc.h
create mode 100644 Silicon/NXP/Include/Library/BeIoLib.h
create mode 100644 Silicon/NXP/Include/Library/IfcLib.h
create mode 100644 Silicon/NXP/Include/Library/NorFlashLib.h
create mode 100644 Silicon/NXP/Include/NorFlash.h
create mode 100644 Silicon/NXP/Include/Pcie.h
create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc
create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc
create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h
create mode 100644 Silicon/NXP/LS2088A/LS2088A.dec
create mode 100644 Silicon/NXP/LS2088A/LS2088A.dsc
create mode 100644 Silicon/NXP/Library/BeIoLib/BeIoLib.c
create mode 100644 Silicon/NXP/Library/BeIoLib/BeIoLib.inf
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.c
create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.h
create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.inf
create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiCommand.h
create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
create mode 100644 Silicon/NXP/NxpQoriqLs.dec
--
1.9.1
^ permalink raw reply [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
@ 2018-02-16 8:49 ` Meenakshi
2018-02-21 15:46 ` Leif Lindholm
2018-02-16 8:49 ` [PATCH edk2-platforms 02/39] Silicon/NXP : Add support for Watchdog driver Meenakshi
` (40 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:49 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
This library add supports for BE read/write and other
MMIO helper function.
In this data swapped after reading from MMIO and before
write using MMIO.
It can be used by any module with BE address space.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Include/Library/BeIoLib.h | 332 ++++++++++++++++++++++++++
Silicon/NXP/Library/BeIoLib/BeIoLib.c | 400 ++++++++++++++++++++++++++++++++
Silicon/NXP/Library/BeIoLib/BeIoLib.inf | 31 +++
3 files changed, 763 insertions(+)
create mode 100644 Silicon/NXP/Include/Library/BeIoLib.h
create mode 100644 Silicon/NXP/Library/BeIoLib/BeIoLib.c
create mode 100644 Silicon/NXP/Library/BeIoLib/BeIoLib.inf
diff --git a/Silicon/NXP/Include/Library/BeIoLib.h b/Silicon/NXP/Include/Library/BeIoLib.h
new file mode 100644
index 0000000..a58883a
--- /dev/null
+++ b/Silicon/NXP/Include/Library/BeIoLib.h
@@ -0,0 +1,332 @@
+/** BeIoLib.h
+ *
+ * Copyright 2017 NXP
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+#ifndef __BE_IOLIB_H__
+#define __BE_IOLIB_H__
+
+#include <Base.h>
+
+/**
+ MmioRead8 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+BeMmioRead8 (
+ IN UINTN Address
+ );
+
+/**
+ MmioRead16 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+BeMmioRead16 (
+ IN UINTN Address
+ );
+
+/**
+ MmioRead32 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+BeMmioRead32 (
+ IN UINTN Address
+ );
+
+/**
+ MmioRead64 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+BeMmioRead64 (
+ IN UINTN Address
+ );
+
+/**
+ MmioWrite8 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ );
+
+/**
+ MmioWrite16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ );
+
+/**
+ MmioWrite32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ MmioWrite64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ );
+
+/**
+ MmioAndThenOr8 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioAndThenOr8 (
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ MmioAndThenOr16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ MmioAndThenOr32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ MmioAndThenOr64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioAndThenOr64 (
+ IN UINTN Address,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ );
+
+/**
+ MmioOr8 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioOr8 (
+ IN UINTN Address,
+ IN UINT8 OrData
+ );
+
+/**
+ MmioOr16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ );
+
+/**
+ MmioOr32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ );
+
+/**
+ MmioOr64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioOr64 (
+ IN UINTN Address,
+ IN UINT64 OrData
+ );
+
+/**
+ MmioAnd8 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioAnd8 (
+ IN UINTN Address,
+ IN UINT8 AndData
+ );
+
+/**
+ MmioAnd16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ );
+
+/**
+ MmioAnd32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ );
+
+/**
+ MmioAnd64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioAnd64 (
+ IN UINTN Address,
+ IN UINT64 AndData
+ );
+
+#endif /* _BE_IOLIB_H */
diff --git a/Silicon/NXP/Library/BeIoLib/BeIoLib.c b/Silicon/NXP/Library/BeIoLib/BeIoLib.c
new file mode 100644
index 0000000..b4b12ac
--- /dev/null
+++ b/Silicon/NXP/Library/BeIoLib/BeIoLib.c
@@ -0,0 +1,400 @@
+/** BeIoLib.c
+
+ Provide MMIO APIs for BE modules.
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+
+/**
+ MmioRead8 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+BeMmioRead8 (
+ IN UINTN Address
+ )
+{
+ return MmioRead8 (Address);
+}
+
+/**
+ MmioRead16 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+BeMmioRead16 (
+ IN UINTN Address
+ )
+{
+ return SwapBytes16 (MmioRead16 (Address));
+}
+
+/**
+ MmioRead32 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+BeMmioRead32 (
+ IN UINTN Address
+ )
+{
+ return SwapBytes32 (MmioRead32 (Address));
+}
+
+/**
+ MmioRead64 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+BeMmioRead64 (
+ IN UINTN Address
+ )
+{
+ return SwapBytes64 (MmioRead64 (Address));
+}
+
+/**
+ MmioWrite8 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ )
+{
+ return MmioWrite8 (Address, Value);
+}
+
+/**
+ MmioWrite16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ )
+{
+ return MmioWrite16 (Address, SwapBytes16 (Value));
+}
+
+/**
+ MmioWrite32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ return MmioWrite32 (Address, SwapBytes32 (Value));
+}
+
+/**
+ MmioWrite64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ )
+{
+ return MmioWrite64 (Address, SwapBytes64 (Value));
+}
+
+/**
+ MmioAndThenOr8 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioAndThenOr8 (
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return MmioAndThenOr8 (Address, AndData, OrData);
+}
+
+/**
+ MmioAndThenOr16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ AndData = SwapBytes16 (AndData);
+ OrData = SwapBytes16 (OrData);
+
+ return MmioAndThenOr16 (Address, AndData, OrData);
+}
+
+/**
+ MmioAndThenOr32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ AndData = SwapBytes32 (AndData);
+ OrData = SwapBytes32 (OrData);
+
+ return MmioAndThenOr32 (Address, AndData, OrData);
+}
+
+/**
+ MmioAndThenOr64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioAndThenOr64 (
+ IN UINTN Address,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ )
+{
+ AndData = SwapBytes64 (AndData);
+ OrData = SwapBytes64 (OrData);
+
+ return MmioAndThenOr64 (Address, AndData, OrData);
+}
+
+/**
+ MmioOr8 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioOr8 (
+ IN UINTN Address,
+ IN UINT8 OrData
+ )
+{
+ return MmioOr8 (Address, OrData);
+}
+
+/**
+ MmioOr16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ )
+{
+ return MmioOr16 (Address, SwapBytes16 (OrData));
+}
+
+/**
+ MmioOr32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ )
+{
+ return MmioOr32 (Address, SwapBytes32 (OrData));
+}
+
+/**
+ MmioOr64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioOr64 (
+ IN UINTN Address,
+ IN UINT64 OrData
+ )
+{
+ return MmioOr64 (Address, SwapBytes64 (OrData));
+}
+
+/**
+ MmioAnd8 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+BeMmioAnd8 (
+ IN UINTN Address,
+ IN UINT8 AndData
+ )
+{
+ return MmioAnd8 (Address, AndData);
+}
+
+/**
+ MmioAnd16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+BeMmioAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ )
+{
+ return MmioAnd16 (Address, SwapBytes16 (AndData));
+}
+
+/**
+ MmioAnd32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+BeMmioAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ )
+{
+ return MmioAnd32 (Address, SwapBytes32 (AndData));
+}
+
+/**
+ MmioAnd64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+BeMmioAnd64 (
+ IN UINTN Address,
+ IN UINT64 AndData
+ )
+{
+ return MmioAnd64 (Address, SwapBytes64 (AndData));
+}
diff --git a/Silicon/NXP/Library/BeIoLib/BeIoLib.inf b/Silicon/NXP/Library/BeIoLib/BeIoLib.inf
new file mode 100644
index 0000000..a1c19d0
--- /dev/null
+++ b/Silicon/NXP/Library/BeIoLib/BeIoLib.inf
@@ -0,0 +1,31 @@
+## @BeIoLib.inf
+
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = BeIoLib
+ FILE_GUID = 28d77333-77eb-4faf-8735-130e5eb3e343
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BeIoLib
+
+[Sources.common]
+ BeIoLib.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ IoLib
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 02/39] Silicon/NXP : Add support for Watchdog driver
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
2018-02-16 8:49 ` [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs Meenakshi
@ 2018-02-16 8:49 ` Meenakshi
2018-02-16 8:49 ` [PATCH edk2-platforms 03/39] SocLib : Add support for initialization of peripherals Meenakshi
` (39 subsequent siblings)
41 siblings, 0 replies; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:49 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Installs watchdog timer arch protocol
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Drivers/WatchDog/WatchDog.c | 459 +++++++++++++++++++++++++++
Silicon/NXP/Drivers/WatchDog/WatchDog.h | 39 +++
Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf | 47 +++
3 files changed, 545 insertions(+)
create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c
create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h
create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.c b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
new file mode 100644
index 0000000..ca1377b
--- /dev/null
+++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
@@ -0,0 +1,459 @@
+/** WatchDog.c
+*
+* Based on Watchdog driver implemenation available in
+* ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/BeIoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/WatchdogTimer.h>
+
+#include "WatchDog.h"
+
+STATIC EFI_EVENT EfiExitBootServicesEvent;
+STATIC EFI_EVENT WdogFeedEvent;
+
+STATIC
+UINT16
+EFIAPI
+WdogRead (
+ IN UINTN Address
+ )
+{
+ if (FixedPcdGetBool (PcdWdogBigEndian)) {
+ return BeMmioRead16 (Address);
+ } else {
+ return MmioRead16(Address);
+ }
+}
+
+STATIC
+UINT16
+EFIAPI
+WdogWrite (
+ IN UINTN Address,
+ IN UINT16 Value
+ )
+{
+ if (FixedPcdGetBool (PcdWdogBigEndian)) {
+ return BeMmioWrite16 (Address, Value);
+ } else {
+ return MmioWrite16 (Address, Value);
+ }
+}
+
+STATIC
+UINT16
+EFIAPI
+WdogAndThenOr (
+ IN UINTN Address,
+ IN UINT16 And,
+ IN UINT16 Or
+ )
+{
+ if (FixedPcdGetBool (PcdWdogBigEndian)) {
+ return BeMmioAndThenOr16 (Address, And, Or);
+ } else {
+ return MmioAndThenOr16 (Address, And, Or);
+ }
+}
+
+STATIC
+UINT16
+EFIAPI
+WdogOr (
+ IN UINTN Address,
+ IN UINT16 Or
+ )
+{
+ if (FixedPcdGetBool (PcdWdogBigEndian)) {
+ return BeMmioOr16 (Address, Or);
+ } else {
+ return MmioOr16 (Address, Or);
+ }
+}
+
+STATIC
+VOID
+WdogPing (
+ VOID
+ )
+{
+ //
+ // To reload a timeout value to the counter the proper service sequence begins by
+ // writing 0x_5555 followed by 0x_AAAA to the Watchdog Service Register (WDOG_WSR).
+ // This service sequence will reload the counter with the timeout value WT[7:0] of
+ // Watchdog Control Register (WDOG_WCR).
+ //
+
+ WdogWrite (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WSR_OFFSET,
+ WDOG_SERVICE_SEQ1);
+ WdogWrite (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WSR_OFFSET,
+ WDOG_SERVICE_SEQ2);
+}
+
+/**
+ Stop the Wdog watchdog timer from counting down.
+**/
+STATIC
+VOID
+WdogStop (
+ VOID
+ )
+{
+ // Watchdog cannot be disabled by software once started.
+ // At best, we can keep reload counter with maximum value
+
+ WdogAndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
+ (UINT16)(~WDOG_WCR_WT),
+ (WD_COUNT (WT_MAX_TIME) & WD_COUNT_MASK));
+ WdogPing ();
+}
+
+/**
+ Starts the Wdog counting down by feeding Service register with
+ desired pattern.
+ The count down will start from the value stored in the Load register,
+ not from the value where it was previously stopped.
+**/
+STATIC
+VOID
+WdogStart (
+ VOID
+ )
+{
+ //Reload the timeout value
+ WdogPing ();
+}
+
+/**
+ On exiting boot services we must make sure the Wdog Watchdog Timer
+ is stopped.
+**/
+STATIC
+VOID
+EFIAPI
+ExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ WdogStop ();
+}
+
+/**
+ This function registers the handler NotifyFunction so it is called every time
+ the watchdog timer expires. It also passes the amount of time since the last
+ handler call to the NotifyFunction.
+ If NotifyFunction is not NULL and a handler is not already registered,
+ then the new handler is registered and EFI_SUCCESS is returned.
+ If NotifyFunction is NULL, and a handler is already registered,
+ then that handler is unregistered.
+ If an attempt is made to register a handler when a handler is already registered,
+ then EFI_ALREADY_STARTED is returned.
+ If an attempt is made to unregister a handler when a handler is not registered,
+ then EFI_INVALID_PARAMETER is returned.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The function to call when a timer interrupt fires. This
+ function executes at TPL_HIGH_LEVEL. The DXE Core will
+ register a handler for the timer interrupt, so it can know
+ how much time has passed. This information is used to
+ signal timer based events. NULL will unregister the handler.
+
+ @retval EFI_SUCCESS The watchdog timer handler was registered.
+ @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
+ registered.
+ @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
+ previously registered.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+WdogRegisterHandler (
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
+ )
+{
+ // ERROR: This function is not supported.
+ // The hardware watchdog will reset the board
+ return EFI_INVALID_PARAMETER;
+}
+
+/**
+
+ This function adjusts the period of timer interrupts to the value specified
+ by TimerPeriod. If the timer period is updated, then the selected timer
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+ If an error occurs while attempting to update the timer period, then the
+ timer hardware will be put back in its state prior to this call, and
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+ is disabled. This is not the same as disabling the CPU's interrupts.
+ Instead, it must either turn off the timer hardware, or it must adjust the
+ interrupt controller so that a CPU interrupt is not generated when the timer
+ interrupt fires.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is
+ returned. If the timer is programmable, then the timer period
+ will be rounded up to the nearest timer period that is supported
+ by the timer hardware. If TimerPeriod is set to 0, then the
+ timer interrupts will be disabled.
+
+
+ @retval EFI_SUCCESS The timer period was changed.
+ @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
+ @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+WdogSetTimerPeriod (
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ IN UINT64 TimerPeriod // In 100ns units
+ )
+{
+ EFI_STATUS Status;
+ UINT64 TimerPeriodInSec;
+ UINT16 Val;
+
+ Status = EFI_SUCCESS;
+
+ if (TimerPeriod == 0) {
+ // This is a watchdog stop request
+ WdogStop ();
+ return Status;
+ } else {
+ // Convert the TimerPeriod (in 100 ns unit) to an equivalent second value
+
+ TimerPeriodInSec = DivU64x32 (TimerPeriod, NANO_SECOND_BASE);
+
+ // The registers in the Wdog are only 32 bits
+ if (TimerPeriodInSec > WT_MAX_TIME) {
+ // We could load the watchdog with the maximum supported value but
+ // if a smaller value was requested, this could have the watchdog
+ // triggering before it was intended.
+ // Better generate an error to let the caller know.
+ Status = EFI_DEVICE_ERROR;
+ return Status;
+ }
+
+ // set the new timeout value in the WCR
+ // Convert the timeout value from Seconds to timer count
+ Val = ((WD_COUNT(TimerPeriodInSec) & WD_COUNT_MASK) << 8);
+
+ WdogAndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
+ (UINT16)(~WDOG_WCR_WT),
+ Val);
+ // Start the watchdog
+ WdogStart ();
+ }
+
+ return Status;
+}
+
+/**
+ This function retrieves the period of timer interrupts in 100 ns units,
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+ returned, then the timer is currently disabled.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
+ 0 is returned, then the timer is currently disabled.
+
+
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+WdogGetTimerPeriod (
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ OUT UINT64 *TimerPeriod
+ )
+{
+ EFI_STATUS Status;
+ UINT64 ReturnValue;
+ UINT16 Val;
+
+ Status = EFI_SUCCESS;
+
+ if (TimerPeriod == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Check if the watchdog is stopped
+ if ((WdogRead (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET)
+ & WDOG_WCR_WDE) == 0 ) {
+ // It is stopped, so return zero.
+ ReturnValue = 0;
+ } else {
+ // Convert the Watchdog ticks into equivalent TimerPeriod second value.
+ Val = (WdogRead (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET)
+ & WDOG_WCR_WT ) >> 8;
+ ReturnValue = WD_SEC(Val);
+ }
+
+ *TimerPeriod = ReturnValue;
+ return Status;
+}
+
+/**
+ Interface structure for the Watchdog Architectural Protocol.
+
+ @par Protocol Description:
+ This protocol provides a service to set the amount of time to wait
+ before firing the watchdog timer, and it also provides a service to
+ register a handler that is invoked when the watchdog timer fires.
+
+ @par When the watchdog timer fires, control will be passed to a handler
+ if one has been registered. If no handler has been registered,
+ or the registered handler returns, then the system will be
+ reset by calling the Runtime Service ResetSystem().
+
+ @param RegisterHandler
+ Registers a handler that will be called each time the
+ watchdogtimer interrupt fires. TimerPeriod defines the minimum
+ time between timer interrupts, so TimerPeriod will also
+ be the minimum time between calls to the registered
+ handler.
+ NOTE: If the watchdog resets the system in hardware, then
+ this function will not have any chance of executing.
+
+ @param SetTimerPeriod
+ Sets the period of the timer interrupt in 100 nS units.
+ This function is optional, and may return EFI_UNSUPPORTED.
+ If this function is supported, then the timer period will
+ be rounded up to the nearest supported timer period.
+
+ @param GetTimerPeriod
+ Retrieves the period of the timer interrupt in 100 nS units.
+
+**/
+STATIC
+EFI_WATCHDOG_TIMER_ARCH_PROTOCOL gWatchdogTimer = {
+ WdogRegisterHandler,
+ WdogSetTimerPeriod,
+ WdogGetTimerPeriod
+};
+
+/**
+ Call back function when the timer event is signaled.
+ This function will feed the watchdog with maximum value
+ so that system wont reset in idle case e.g. stopped on UEFI shell.
+
+ @param[in] Event The Event this notify function registered to.
+ @param[in] Context Pointer to the context data registered to the
+ Event.
+
+**/
+VOID
+EFIAPI
+WdogFeed (
+ IN EFI_EVENT Event,
+ IN VOID* Context
+ )
+{
+ WdogPing();
+}
+/**
+ Initialize state information for the Watchdog Timer Architectural Protocol.
+
+ @param ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Protocol registered
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Hardware problems
+
+**/
+EFI_STATUS
+EFIAPI
+WdogInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ WdogAndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
+ (UINT16)(~WDOG_WCR_WT),
+ (WD_COUNT (WT_MAX_TIME) & WD_COUNT_MASK));
+
+ WdogOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET, WDOG_WCR_WDE);
+
+ //
+ // Make sure the Watchdog Timer Architectural Protocol
+ // has not been installed in the system yet.
+ // This will avoid conflicts with the universal watchdog
+ //
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid);
+
+ // Register for an ExitBootServicesEvent
+ Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,
+ ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
+ if (EFI_ERROR (Status)) {
+ Status = EFI_OUT_OF_RESOURCES;
+ return Status;
+ }
+
+ //
+ // Start the timer to feed Watchdog with maximum timeout value.
+ //
+ Status = gBS->CreateEvent (
+ EVT_TIMER | EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ WdogFeed,
+ NULL,
+ &WdogFeedEvent
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = gBS->SetTimer (WdogFeedEvent, TimerPeriodic, WT_FEED_INTERVAL);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Install the Timer Architectural Protocol onto a new handle
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ gBS->CloseEvent (EfiExitBootServicesEvent);
+ Status = EFI_OUT_OF_RESOURCES;
+ return Status;
+ }
+
+ WdogPing ();
+
+ return Status;
+}
diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.h b/Silicon/NXP/Drivers/WatchDog/WatchDog.h
new file mode 100644
index 0000000..9542608
--- /dev/null
+++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.h
@@ -0,0 +1,39 @@
+/** WatchDog.h
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __WATCHDOG_H__
+#define __WATCHDOG_H__
+
+#define WDOG_SIZE 0x1000
+#define WDOG_WCR_OFFSET 0
+#define WDOG_WSR_OFFSET 2
+#define WDOG_WRSR_OFFSET 4
+#define WDOG_WICR_OFFSET 6
+#define WDOG_WCR_WT (0xFF << 8)
+#define WDOG_WCR_WDE (1 << 2)
+#define WDOG_SERVICE_SEQ1 0x5555
+#define WDOG_SERVICE_SEQ2 0xAAAA
+#define WDOG_WCR_WDZST 0x1
+#define WDOG_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
+
+#define WT_MAX_TIME 128
+#define WD_COUNT(Sec) (((Sec) * 2 - 1) << 8)
+#define WD_COUNT_MASK 0xff00
+#define WD_SEC(Cnt) (((Cnt) + 1) / 2)
+
+#define NANO_SECOND_BASE 10000000
+
+#define WT_FEED_INTERVAL (WT_MAX_TIME * NANO_SECOND_BASE)
+
+#endif //__WATCHDOG_H__
diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf b/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
new file mode 100644
index 0000000..e6c06ef
--- /dev/null
+++ b/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
@@ -0,0 +1,47 @@
+# WatchDog.inf
+#
+# Component description file for WatchDog module
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = WatchDogDxe
+ FILE_GUID = 0358b544-ec65-4339-89cd-cad60a3dd787
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = WdogInitialize
+
+[Sources.common]
+ WatchDog.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ BeIoLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian
+
+[Protocols]
+ gEfiWatchdogTimerArchProtocolGuid
+
+[Depex]
+ TRUE
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 03/39] SocLib : Add support for initialization of peripherals
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
2018-02-16 8:49 ` [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs Meenakshi
2018-02-16 8:49 ` [PATCH edk2-platforms 02/39] Silicon/NXP : Add support for Watchdog driver Meenakshi
@ 2018-02-16 8:49 ` Meenakshi
2018-04-18 15:12 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 04/39] Silicon/NXP : Add support for DUART library Meenakshi
` (38 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:49 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Add SocInit function that initializes peripherals
and print board and soc information.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Chassis/Chassis.c | 388 ++++++++++++++++++++++++++++++
Silicon/NXP/Chassis/Chassis.h | 144 +++++++++++
Silicon/NXP/Chassis/Chassis2/Chassis2.dec | 19 ++
Silicon/NXP/Chassis/Chassis2/SerDes.h | 68 ++++++
Silicon/NXP/Chassis/Chassis2/Soc.c | 172 +++++++++++++
Silicon/NXP/Chassis/Chassis2/Soc.h | 367 ++++++++++++++++++++++++++++
Silicon/NXP/Chassis/LS1043aSocLib.inf | 47 ++++
Silicon/NXP/Chassis/SerDes.c | 271 +++++++++++++++++++++
Silicon/NXP/Include/Bitops.h | 179 ++++++++++++++
Silicon/NXP/LS1043A/Include/SocSerDes.h | 55 +++++
10 files changed, 1710 insertions(+)
create mode 100644 Silicon/NXP/Chassis/Chassis.c
create mode 100644 Silicon/NXP/Chassis/Chassis.h
create mode 100644 Silicon/NXP/Chassis/Chassis2/Chassis2.dec
create mode 100644 Silicon/NXP/Chassis/Chassis2/SerDes.h
create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.c
create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.h
create mode 100644 Silicon/NXP/Chassis/LS1043aSocLib.inf
create mode 100644 Silicon/NXP/Chassis/SerDes.c
create mode 100644 Silicon/NXP/Include/Bitops.h
create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c
new file mode 100644
index 0000000..9f2928b
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis.c
@@ -0,0 +1,388 @@
+/** @file
+ SoC specific Library containg functions to initialize various SoC components
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/BeIoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include <Soc.h>
+
+#include "Chassis.h"
+
+UINT32
+EFIAPI
+GurRead (
+ IN UINTN Address
+ )
+{
+ if (FixedPcdGetBool (PcdGurBigEndian)) {
+ return BeMmioRead32 (Address);
+ } else {
+ return MmioRead32 (Address);
+ }
+}
+
+/*
+ * Structure to list available SOCs.
+ */
+STATIC CPU_TYPE CpuTypeList[] = {
+ CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
+};
+
+/*
+ * Return the number of bits set
+ */
+STATIC
+inline
+UINTN
+CountSetBits (
+ IN UINTN Num
+ )
+{
+ UINTN Count;
+
+ Count = 0;
+
+ while (Num) {
+ Count += Num & 1;
+ Num >>= 1;
+ }
+
+ return Count;
+}
+
+/*
+ * Return the type of initiator (core or hardware accelerator)
+ */
+UINT32
+InitiatorType (
+ IN UINT32 Cluster,
+ IN UINTN InitId
+ )
+{
+ CCSR_GUR *GurBase;
+ UINT32 Idx;
+ UINT32 Type;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
+ Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
+
+ if (Type & TP_ITYP_AV_MASK) {
+ return Type;
+ }
+
+ return 0;
+}
+
+/*
+ * Return the mask for number of cores on this SOC.
+ */
+UINT32
+CpuMask (
+ VOID
+ )
+{
+ CCSR_GUR *GurBase;
+ UINTN ClusterIndex;
+ UINTN Count;
+ UINT32 Cluster;
+ UINT32 Type;
+ UINT32 Mask;
+ UINTN InitiatorIndex;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClusterIndex = 0;
+ Count = 0;
+ Mask = 0;
+
+ do {
+ Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+ for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+ Type = InitiatorType (Cluster, InitiatorIndex);
+ if (Type) {
+ if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM)
+ Mask |= 1 << Count;
+ Count++;
+ }
+ }
+ ClusterIndex++;
+ } while (CHECK_CLUSTER (Cluster));
+
+ return Mask;
+}
+
+/*
+ * Return the number of cores on this SOC.
+ */
+UINTN
+CpuNumCores (
+ VOID
+ )
+{
+ return CountSetBits (CpuMask ());
+}
+
+/*
+ * Return the type of core i.e. A53, A57 etc of inputted
+ * core number.
+ */
+UINT32
+QoriqCoreToType (
+ IN UINTN Core
+ )
+{
+ CCSR_GUR *GurBase;
+ UINTN ClusterIndex;
+ UINTN Count;
+ UINT32 Cluster;
+ UINT32 Type;
+ UINTN InitiatorIndex;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClusterIndex = 0;
+ Count = 0;
+
+ do {
+ Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+ for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+ Type = InitiatorType (Cluster, InitiatorIndex);
+ if (Type) {
+ if (Count == Core)
+ return Type;
+ Count++;
+ }
+ }
+ ClusterIndex++;
+ } while (CHECK_CLUSTER (Cluster));
+
+ return -1; /* cannot identify the cluster */
+}
+
+/*
+ * Print CPU information
+ */
+VOID
+PrintCpuInfo (
+ VOID
+ )
+{
+ SYS_INFO SysInfo;
+ UINTN CoreIndex;
+ UINTN Core;
+ UINT32 Type;
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+
+ GetSysInfo (&SysInfo);
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Clock Configuration:");
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+ ForEachCpu (CoreIndex, Core, CpuNumCores (), CpuMask ()) {
+ if (!(CoreIndex % 3)) {
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n ");
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+ }
+
+ Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "CPU%d(%a):%-4d MHz ", Core,
+ Type == TY_ITYP_VERSION_A7 ? "A7 " :
+ (Type == TY_ITYP_VERSION_A53 ? "A53" :
+ (Type == TY_ITYP_VERSION_A57 ? "A57" :
+ (Type == TY_ITYP_VERSION_A72 ? "A72" : " Unknown Core "))),
+ SysInfo.FreqProcessor[Core] / MEGA_HZ);
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+ }
+
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n Bus: %-4d MHz ",
+ SysInfo.FreqSystemBus / MEGA_HZ);
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "DDR: %-4d MT/s",
+ SysInfo.FreqDdrBus / MEGA_HZ);
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+ if (SysInfo.FreqFman[0] != 0) {
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n FMAN: %-4d MHz ",
+ SysInfo.FreqFman[0] / MEGA_HZ);
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+ }
+
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n");
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+}
+
+/*
+ * Return system bus frequency
+ */
+UINT64
+GetBusFrequency (
+ VOID
+ )
+{
+ SYS_INFO SocSysInfo;
+
+ GetSysInfo (&SocSysInfo);
+
+ return SocSysInfo.FreqSystemBus;
+}
+
+/*
+ * Return SDXC bus frequency
+ */
+UINT64
+GetSdxcFrequency (
+ VOID
+ )
+{
+ SYS_INFO SocSysInfo;
+
+ GetSysInfo (&SocSysInfo);
+
+ return SocSysInfo.FreqSdhc;
+}
+
+/*
+ * Print Soc information
+ */
+VOID
+PrintSoc (
+ VOID
+ )
+{
+ CHAR8 Buf[16];
+ CCSR_GUR *GurBase;
+ UINTN Count;
+ UINTN Svr;
+ UINTN Ver;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+ Buf[0] = L'\0';
+ Svr = GurRead ((UINTN)&GurBase->Svr);
+ Ver = SVR_SOC_VER (Svr);
+
+ for (Count = 0; Count < ARRAY_SIZE (CpuTypeList); Count++)
+ if ((CpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
+ AsciiStrCpy (Buf, (CONST CHAR8 *)CpuTypeList[Count].Name);
+
+ if (IS_E_PROCESSOR (Svr)) {
+ AsciiStrCat (Buf, (CONST CHAR8 *)"E");
+ }
+ break;
+ }
+
+ if (Count == ARRAY_SIZE (CpuTypeList)) {
+ AsciiStrCpy (Buf, (CONST CHAR8 *)"unknown");
+ }
+
+ DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
+ Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
+
+ return;
+}
+
+/*
+ * Dump RCW (Reset Control Word) on console
+ */
+VOID
+PrintRCW (
+ VOID
+ )
+{
+ CCSR_GUR *Base;
+ UINTN Count;
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+
+ Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+ /*
+ * Display the RCW, so that no one gets confused as to what RCW
+ * we're actually using for this boot.
+ */
+
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer),
+ "Reset Configuration Word (RCW):");
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+ for (Count = 0; Count < ARRAY_SIZE(Base->RcwSr); Count++) {
+ UINT32 Rcw = BeMmioRead32((UINTN)&Base->RcwSr[Count]);
+
+ if ((Count % 4) == 0) {
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer),
+ "\n %08x:", Count * 4);
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+ }
+
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), " %08x", Rcw);
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+ }
+
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n");
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+}
+
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+VOID
+SmmuInit (
+ VOID
+ )
+{
+ UINT32 Value;
+
+ /* set pagesize as 64K and ssmu-500 in bypass mode */
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
+ MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
+}
+
+/*
+ * Return current Soc Name form CpuTypeList
+ */
+CHAR8 *
+GetSocName (
+ VOID
+ )
+{
+ UINT8 Count;
+ UINTN Svr;
+ UINTN Ver;
+ CCSR_GUR *GurBase;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+ Svr = GurRead ((UINTN)&GurBase->Svr);
+ Ver = SVR_SOC_VER (Svr);
+
+ for (Count = 0; Count < ARRAY_SIZE (CpuTypeList); Count++) {
+ if ((CpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
+ return (CHAR8 *)CpuTypeList[Count].Name;
+ }
+ }
+
+ return NULL;
+}
diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h
new file mode 100644
index 0000000..4bdb4d0
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis.h
@@ -0,0 +1,144 @@
+/** @file
+* Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __CHASSIS_H__
+#define __CHASSIS_H__
+
+#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
+#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
+#define TP_ITYP_TYPE_ARM 0x0
+#define TP_ITYP_TYPE_PPC 0x1
+#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
+#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
+#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
+#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
+#define TP_INIT_PER_CLUSTER 4
+
+#define TY_ITYP_VERSION_A7 0x1
+#define TY_ITYP_VERSION_A53 0x2
+#define TY_ITYP_VERSION_A57 0x3
+#define TY_ITYP_VERSION_A72 0x4
+
+STATIC
+inline
+UINTN
+CpuMaskNext (
+ IN UINTN Cpu,
+ IN UINTN Mask
+ )
+{
+ for (Cpu++; !((1 << Cpu) & Mask); Cpu++)
+ ;
+
+ return Cpu;
+}
+
+#define ForEachCpu(Iter, Cpu, NumCpus, Mask) \
+ for (Iter = 0, Cpu = CpuMaskNext(-1, Mask); \
+ Iter < NumCpus; \
+ Iter++, Cpu = CpuMaskNext(Cpu, Mask)) \
+
+#define CPU_TYPE_ENTRY(N, V, NC) \
+ { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
+
+#define SVR_WO_E 0xFFFFFE
+#define SVR_LS1043A 0x879200
+
+#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
+#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
+#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
+#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
+
+#define MEGA_HZ 1000000
+
+typedef struct {
+ CHAR8 Name[16];
+ UINT32 SocVer;
+ UINT32 NumCores;
+} CPU_TYPE;
+
+typedef struct {
+ UINTN CpuClk; /* CPU clock in Hz! */
+ UINTN BusClk;
+ UINTN MemClk;
+ UINTN PciClk;
+ UINTN SdhcClk;
+} SOC_CLOCK_INFO;
+
+/*
+ * Print Soc information
+ */
+VOID
+PrintSoc (
+ VOID
+ );
+
+/*
+ * Initialize Clock structure
+ */
+VOID
+ClockInit (
+ VOID
+ );
+
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+VOID
+SmmuInit (
+ VOID
+ );
+
+/*
+ * Print CPU information
+ */
+VOID
+PrintCpuInfo (
+ VOID
+ );
+
+/*
+ * Dump RCW (Reset Control Word) on console
+ */
+VOID
+PrintRCW (
+ VOID
+ );
+
+UINT32
+InitiatorType (
+ IN UINT32 Cluster,
+ IN UINTN InitId
+ );
+
+/*
+ * Return the mask for number of cores on this SOC.
+ */
+UINT32
+CpuMask (
+ VOID
+ );
+
+/*
+ * Return the number of cores on this SOC.
+ */
+UINTN
+CpuNumCores (
+ VOID
+ );
+
+#endif /* __CHASSIS_H__ */
diff --git a/Silicon/NXP/Chassis/Chassis2/Chassis2.dec b/Silicon/NXP/Chassis/Chassis2/Chassis2.dec
new file mode 100644
index 0000000..cf41b3c
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis2/Chassis2.dec
@@ -0,0 +1,19 @@
+# @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+
+[Includes]
+ .
diff --git a/Silicon/NXP/Chassis/Chassis2/SerDes.h b/Silicon/NXP/Chassis/Chassis2/SerDes.h
new file mode 100644
index 0000000..4c874aa
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis2/SerDes.h
@@ -0,0 +1,68 @@
+/** SerDes.h
+ The Header file of SerDes Module for Chassis 2
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SERDES_H__
+#define __SERDES_H__
+
+#include <Uefi/UefiBaseType.h>
+
+#define SRDS_MAX_LANES 4
+
+typedef enum {
+ NONE = 0,
+ PCIE1,
+ PCIE2,
+ PCIE3,
+ SATA,
+ SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC10,
+ QSGMII_FM1_A,
+ XFI_FM1_MAC9,
+ XFI_FM1_MAC10,
+ SGMII_2500_FM1_DTSEC2,
+ SGMII_2500_FM1_DTSEC5,
+ SGMII_2500_FM1_DTSEC9,
+ SGMII_2500_FM1_DTSEC10,
+ SERDES_PRTCL_COUNT
+} SERDES_PROTOCOL;
+
+typedef enum {
+ SRDS_1 = 0,
+ SRDS_2,
+ SRDS_MAX_NUM
+} SERDES_NUMBER;
+
+typedef struct {
+ UINT16 Protocol;
+ UINT8 SrdsLane[SRDS_MAX_LANES];
+} SERDES_CONFIG;
+
+typedef VOID
+(*SERDES_PROBE_LANES_CALLBACK) (
+ IN SERDES_PROTOCOL LaneProtocol,
+ IN VOID *Arg
+ );
+
+VOID
+SerDesProbeLanes(
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ );
+
+#endif /* __SERDES_H */
diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chassis2/Soc.c
new file mode 100644
index 0000000..7f9f963
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis2/Soc.c
@@ -0,0 +1,172 @@
+/** @Soc.c
+ SoC specific Library containg functions to initialize various SoC components
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Chassis.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib/MemLibInternals.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include "Soc.h"
+
+/**
+ Calculate the frequency of various controllers and
+ populate the passed structure with frequuencies.
+
+ @param PtrSysInfo Input structure to populate with
+ frequencies.
+**/
+VOID
+GetSysInfo (
+ OUT SYS_INFO *PtrSysInfo
+ )
+{
+ CCSR_GUR *GurBase;
+ CCSR_CLOCK *ClkBase;
+ UINTN CpuIndex;
+ UINT32 TempRcw;
+ UINT32 CPllSel;
+ UINT32 CplxPll;
+ CONST UINT8 CoreCplxPll[8] = {
+ [0] = 0, /* CC1 PPL / 1 */
+ [1] = 0, /* CC1 PPL / 2 */
+ [4] = 1, /* CC2 PPL / 1 */
+ [5] = 1, /* CC2 PPL / 2 */
+ };
+
+ CONST UINT8 CoreCplxPllDivisor[8] = {
+ [0] = 1, /* CC1 PPL / 1 */
+ [1] = 2, /* CC1 PPL / 2 */
+ [4] = 1, /* CC2 PPL / 1 */
+ [5] = 2, /* CC2 PPL / 2 */
+ };
+
+ UINTN PllCount;
+ UINTN FreqCPll[NUM_CC_PLLS];
+ UINTN PllRatio[NUM_CC_PLLS];
+ UINTN SysClk;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
+ SysClk = CLK_FREQ;
+
+ SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
+
+ PtrSysInfo->FreqSystemBus = SysClk;
+ PtrSysInfo->FreqDdrBus = SysClk;
+
+ //
+ // selects the platform clock:SYSCLK ratio and calculate
+ // system frequency
+ //
+ PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+ CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+ CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+ //
+ // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
+ //
+ PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+ CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
+ CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+
+ for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
+ PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
+ if (PllRatio[PllCount] > 4) {
+ FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
+ } else {
+ FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
+ }
+ }
+
+ //
+ // Calculate Core frequency
+ //
+ for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
+ CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) & 0xf;
+ CplxPll = CoreCplxPll[CPllSel];
+
+ PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
+ }
+
+ //
+ // Calculate FMAN frequency
+ //
+ TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
+ switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
+ case 2:
+ PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
+ break;
+ case 3:
+ PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
+ break;
+ case 4:
+ PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
+ break;
+ case 5:
+ PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
+ break;
+ case 6:
+ PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
+ break;
+ case 7:
+ PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
+ break;
+ default:
+ DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
+ break;
+ }
+ PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
+ PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
+}
+
+/**
+ Function to initialize SoC specific constructs
+ CPU Info
+ SoC Personality
+ Board Personality
+ RCW prints
+ **/
+VOID
+SocInit (
+ VOID
+ )
+{
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+
+ SmmuInit ();
+
+ //
+ // Early init serial Port to get board information.
+ //
+ SerialPortInitialize ();
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\nUEFI firmware (version %s built at %a on %a)\n\r",
+ (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__);
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+ PrintCpuInfo ();
+
+ //
+ // Print Reset control Word
+ //
+ PrintRCW ();
+ PrintSoc ();
+
+ return;
+}
diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.h b/Silicon/NXP/Chassis/Chassis2/Soc.h
new file mode 100644
index 0000000..10e99ab
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis2/Soc.h
@@ -0,0 +1,367 @@
+/** Soc.h
+* Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#define HWA_CGA_M1_CLK_SEL 0xe0000000
+#define HWA_CGA_M1_CLK_SHIFT 29
+
+#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
+#define NUM_CC_PLLS 2
+#define CLK_FREQ 100000000
+#define MAX_CPUS 4
+#define NUM_FMAN 1
+#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
+
+/* RCW SERDES MACRO */
+#define RCWSR_INDEX 4
+#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
+#define RCWSR_SRDS1_PRTCL_SHIFT 16
+#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
+#define RCWSR_SRDS2_PRTCL_SHIFT 0
+
+/* SMMU Defintions */
+#define SMMU_BASE_ADDR 0x09000000
+#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
+#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
+#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
+
+#define SCR0_USFCFG_MASK 0x00000400
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SACR_PAGESIZE_MASK 0x00010000
+#define IDR1_PAGESIZE_MASK 0x80000000
+
+typedef struct {
+ UINTN FreqProcessor[MAX_CPUS];
+ UINTN FreqSystemBus;
+ UINTN FreqDdrBus;
+ UINTN FreqLocalBus;
+ UINTN FreqSdhc;
+ UINTN FreqFman[NUM_FMAN];
+ UINTN FreqQman;
+} SYS_INFO;
+
+/* Device Configuration and Pin Control */
+typedef struct {
+ UINT32 PorSr1; /* POR status 1 */
+#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
+ UINT32 PorSr2; /* POR status 2 */
+ UINT8 Res008[0x20-0x8];
+ UINT32 GppOrCr1; /* General-purpose POR configuration */
+ UINT32 GppOrCr2;
+ UINT32 DcfgFuseSr; /* Fuse status register */
+ UINT8 Res02c[0x70-0x2c];
+ UINT32 DevDisr; /* Device disable control */
+ UINT32 DevDisr2; /* Device disable control 2 */
+ UINT32 DevDisr3; /* Device disable control 3 */
+ UINT32 DevDisr4; /* Device disable control 4 */
+ UINT32 DevDisr5; /* Device disable control 5 */
+ UINT32 DevDisr6; /* Device disable control 6 */
+ UINT32 DevDisr7; /* Device disable control 7 */
+ UINT8 Res08c[0x94-0x8c];
+ UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
+ UINT32 CoreDisrL; /* lower portion for support of 64 cores */
+ UINT8 Res09c[0xa0-0x9c];
+ UINT32 Pvr; /* Processor version */
+ UINT32 Svr; /* System version */
+ UINT32 Mvr; /* Manufacturing version */
+ UINT8 Res0ac[0xb0-0xac];
+ UINT32 RstCr; /* Reset control */
+ UINT32 RstRqPblSr; /* Reset request preboot loader status */
+ UINT8 Res0b8[0xc0-0xb8];
+ UINT32 RstRqMr1; /* Reset request mask */
+ UINT8 Res0c4[0xc8-0xc4];
+ UINT32 RstRqSr1; /* Reset request status */
+ UINT8 Res0cc[0xd4-0xcc];
+ UINT32 RstRqWdTmrL; /* Reset request WDT mask */
+ UINT8 Res0d8[0xdc-0xd8];
+ UINT32 RstRqWdtSrL; /* Reset request WDT status */
+ UINT8 Res0e0[0xe4-0xe0];
+ UINT32 BrrL; /* Boot release */
+ UINT8 Res0e8[0x100-0xe8];
+ UINT32 RcwSr[16]; /* Reset control word status */
+#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
+#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
+#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
+#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
+ UINT8 Res140[0x200-0x140];
+ UINT32 ScratchRw[4]; /* Scratch Read/Write */
+ UINT8 Res210[0x300-0x210];
+ UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
+ UINT8 Res310[0x400-0x310];
+ UINT32 CrstSr[12];
+ UINT8 Res430[0x500-0x430];
+ /* PCI Express n Logical I/O Device Number register */
+ UINT32 DcfgCcsrPex1LiodNr;
+ UINT32 DcfgCcsrPex2LiodNr;
+ UINT32 DcfgCcsrPex3LiodNr;
+ UINT32 DcfgCcsrPex4LiodNr;
+ /* RIO n Logical I/O Device Number register */
+ UINT32 DcfgCcsrRio1LiodNr;
+ UINT32 DcfgCcsrRio2LiodNr;
+ UINT32 DcfgCcsrRio3LiodNr;
+ UINT32 DcfgCcsrRio4LiodNr;
+ /* USB Logical I/O Device Number register */
+ UINT32 DcfgCcsrUsb1LiodNr;
+ UINT32 DcfgCcsrUsb2LiodNr;
+ UINT32 DcfgCcsrUsb3LiodNr;
+ UINT32 DcfgCcsrUsb4LiodNr;
+ /* SD/MMC Logical I/O Device Number register */
+ UINT32 DcfgCcsrSdMmc1LiodNr;
+ UINT32 DcfgCcsrSdMmc2LiodNr;
+ UINT32 DcfgCcsrSdMmc3LiodNr;
+ UINT32 DcfgCcsrSdMmc4LiodNr;
+ /* RIO Message Unit Logical I/O Device Number register */
+ UINT32 DcfgCcsrRiomaintLiodNr;
+ UINT8 Res544[0x550-0x544];
+ UINT32 SataLiodNr[4];
+ UINT8 Res560[0x570-0x560];
+ UINT32 DcfgCcsrMisc1LiodNr;
+ UINT32 DcfgCcsrMisc2LiodNr;
+ UINT32 DcfgCcsrMisc3LiodNr;
+ UINT32 DcfgCcsrMisc4LiodNr;
+ UINT32 DcfgCcsrDma1LiodNr;
+ UINT32 DcfgCcsrDma2LiodNr;
+ UINT32 DcfgCcsrDma3LiodNr;
+ UINT32 DcfgCcsrDma4LiodNr;
+ UINT32 DcfgCcsrSpare1LiodNr;
+ UINT32 DcfgCcsrSpare2LiodNr;
+ UINT32 DcfgCcsrSpare3LiodNr;
+ UINT32 DcfgCcsrSpare4LiodNr;
+ UINT8 Res5a0[0x600-0x5a0];
+ UINT32 DcfgCcsrPblSr;
+ UINT32 PamuBypENr;
+ UINT32 DmaCr1;
+ UINT8 Res60c[0x610-0x60c];
+ UINT32 DcfgCcsrGenSr1;
+ UINT32 DcfgCcsrGenSr2;
+ UINT32 DcfgCcsrGenSr3;
+ UINT32 DcfgCcsrGenSr4;
+ UINT32 DcfgCcsrGenCr1;
+ UINT32 DcfgCcsrGenCr2;
+ UINT32 DcfgCcsrGenCr3;
+ UINT32 DcfgCcsrGenCr4;
+ UINT32 DcfgCcsrGenCr5;
+ UINT32 DcfgCcsrGenCr6;
+ UINT32 DcfgCcsrGenCr7;
+ UINT8 Res63c[0x658-0x63c];
+ UINT32 DcfgCcsrcGenSr1;
+ UINT32 DcfgCcsrcGenSr0;
+ UINT8 Res660[0x678-0x660];
+ UINT32 DcfgCcsrcGenCr1;
+ UINT32 DcfgCcsrcGenCr0;
+ UINT8 Res680[0x700-0x680];
+ UINT32 DcfgCcsrSrIoPstecr;
+ UINT32 DcfgCcsrDcsrCr;
+ UINT8 Res708[0x740-0x708]; /* add more registers when needed */
+ UINT32 TpItyp[64]; /* Topology Initiator Type Register */
+ struct {
+ UINT32 Upper;
+ UINT32 Lower;
+ } TpCluster[16];
+ UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
+ UINT32 DcfgCcsrQmBmWarmRst;
+ UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
+ UINT32 DcfgCcsrReserved0;
+ UINT32 DcfgCcsrReserved1;
+} CCSR_GUR;
+
+/* Supplemental Configuration Unit */
+typedef struct {
+ UINT8 Res000[0x070-0x000];
+ UINT32 Usb1Prm1Cr;
+ UINT32 Usb1Prm2Cr;
+ UINT32 Usb1Prm3Cr;
+ UINT32 Usb2Prm1Cr;
+ UINT32 Usb2Prm2Cr;
+ UINT32 Usb2Prm3Cr;
+ UINT32 Usb3Prm1Cr;
+ UINT32 Usb3Prm2Cr;
+ UINT32 Usb3Prm3Cr;
+ UINT8 Res094[0x100-0x094];
+ UINT32 Usb2Icid;
+ UINT32 Usb3Icid;
+ UINT8 Res108[0x114-0x108];
+ UINT32 DmaIcid;
+ UINT32 SataIcid;
+ UINT32 Usb1Icid;
+ UINT32 QeIcid;
+ UINT32 SdhcIcid;
+ UINT32 EdmaIcid;
+ UINT32 EtrIcid;
+ UINT32 Core0SftRst;
+ UINT32 Core1SftRst;
+ UINT32 Core2SftRst;
+ UINT32 Core3SftRst;
+ UINT8 Res140[0x158-0x140];
+ UINT32 AltCBar;
+ UINT32 QspiCfg;
+ UINT8 Res160[0x180-0x160];
+ UINT32 DmaMcr;
+ UINT8 Res184[0x188-0x184];
+ UINT32 GicAlign;
+ UINT32 DebugIcid;
+ UINT8 Res190[0x1a4-0x190];
+ UINT32 SnpCnfGcr;
+#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
+#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
+#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
+#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
+#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
+#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
+#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
+#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
+#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
+#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
+ UINT8 Res1a8[0x1ac-0x1a8];
+ UINT32 IntpCr;
+ UINT8 Res1b0[0x204-0x1b0];
+ UINT32 CoreSrEnCr;
+ UINT8 Res208[0x220-0x208];
+ UINT32 RvBar00;
+ UINT32 RvBar01;
+ UINT32 RvBar10;
+ UINT32 RvBar11;
+ UINT32 RvBar20;
+ UINT32 RvBar21;
+ UINT32 RvBar30;
+ UINT32 RvBar31;
+ UINT32 LpmCsr;
+ UINT8 Res244[0x400-0x244];
+ UINT32 QspIdQScr;
+ UINT32 EcgTxcMcr;
+ UINT32 SdhcIoVSelCr;
+ UINT32 RcwPMuxCr0;
+ /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+ *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+ *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
+ Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
+#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
+ /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+ *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+ *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
+ Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
+#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
+ UINT32 UsbDrvVBusSelCr;
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
+ UINT32 UsbPwrFaultSelCr;
+#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
+#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
+#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
+#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
+#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
+#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
+ UINT32 UsbRefclkSelcr1;
+ UINT32 UsbRefclkSelcr2;
+ UINT32 UsbRefclkSelcr3;
+ UINT8 Res424[0x600-0x424];
+ UINT32 ScratchRw[4];
+ UINT8 Res610[0x680-0x610];
+ UINT32 CoreBCr;
+ UINT8 Res684[0x1000-0x684];
+ UINT32 Pex1MsiIr;
+ UINT32 Pex1MsiR;
+ UINT8 Res1008[0x2000-0x1008];
+ UINT32 Pex2;
+ UINT32 Pex2MsiR;
+ UINT8 Res2008[0x3000-0x2008];
+ UINT32 Pex3MsiIr;
+ UINT32 Pex3MsiR;
+} CCSR_SCFG;
+
+#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8003
+#define USB_PHY_RX_EQ_VAL_4 0x800b
+
+/*USB_PHY_SS memory map*/
+typedef struct {
+ UINT16 IpIdcodeLo;
+ UINT16 SupIdcodeHi;
+ UINT8 Res4[0x0006-0x0004];
+ UINT16 RtuneDebug;
+ UINT16 RtuneStat;
+ UINT16 SupSsPhase;
+ UINT16 SsFreq;
+ UINT8 ResE[0x0020-0x000e];
+ UINT16 Ateovrd;
+ UINT16 MpllOvrdInLo;
+ UINT8 Res24[0x0026-0x0024];
+ UINT16 SscOvrdIn;
+ UINT8 Res28[0x002A-0x0028];
+ UINT16 LevelOvrdIn;
+ UINT8 Res2C[0x0044-0x002C];
+ UINT16 ScopeCount;
+ UINT8 Res46[0x0060-0x0046];
+ UINT16 MpllLoopCtl;
+ UINT8 Res62[0x006C-0x0062];
+ UINT16 SscClkCntrl;
+ UINT8 Res6E[0x2002-0x006E];
+ UINT16 Lane0TxOvrdInHi;
+ UINT16 Lane0TxOvrdDrvLo;
+ UINT8 Res2006[0x200C-0x2006];
+ UINT16 Lane0RxOvrdInHi;
+ UINT8 Res200E[0x2022-0x200E];
+ UINT16 Lane0TxCmWaitTimeOvrd;
+ UINT8 Res2024[0x202A-0x2024];
+ UINT16 Lane0TxLbertCtl;
+ UINT16 Lane0RxLbertCtl;
+ UINT16 Lane0RxLbertErr;
+ UINT8 Res2030[0x205A-0x2030];
+ UINT16 Lane0TxAltBlock;
+} CCSR_USB_PHY;
+
+/* Clocking */
+typedef struct {
+ struct {
+ UINT32 ClkCnCSr; /* core cluster n clock control status */
+ UINT8 Res004[0x0c];
+ UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
+ UINT8 Res014[0x0c];
+ } ClkcSr[4];
+ UINT8 Res040[0x780]; /* 0x100 */
+ struct {
+ UINT32 PllCnGSr;
+ UINT8 Res804[0x1c];
+ } PllCgSr[NUM_CC_PLLS];
+ UINT8 Res840[0x1c0];
+ UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
+ UINT8 Resa04[0x1fc];
+ UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
+ UINT8 Resc04[0x1c];
+ UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
+ UINT8 Resc24[0x3dc];
+} CCSR_CLOCK;
+
+VOID
+GetSysInfo (
+ OUT SYS_INFO *
+ );
+
+UINT32
+EFIAPI
+GurRead (
+ IN UINTN Address
+ );
+
+#endif /* __SOC_H__ */
diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS1043aSocLib.inf
new file mode 100644
index 0000000..1b2f9c4
--- /dev/null
+++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf
@@ -0,0 +1,47 @@
+# @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SocLib
+ FILE_GUID = e868c5ca-9729-43ae-bff4-438c67de8c68
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis/Chassis2/Chassis2.dec
+ Silicon/NXP/LS1043A/LS1043A.dec
+
+[LibraryClasses]
+ BaseLib
+ BeIoLib
+ DebugLib
+ SerialPortLib
+
+[Sources.common]
+ Chassis.c
+ Chassis2/Soc.c
+ SerDes.c
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
diff --git a/Silicon/NXP/Chassis/SerDes.c b/Silicon/NXP/Chassis/SerDes.c
new file mode 100644
index 0000000..e4578c3
--- /dev/null
+++ b/Silicon/NXP/Chassis/SerDes.c
@@ -0,0 +1,271 @@
+/** SerDes.c
+ Provides the basic interfaces for SerDes Module
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Bitops.h>
+#include <Library/DebugLib.h>
+#include <SerDes.h>
+#include <SocSerDes.h>
+#include <Soc.h>
+#include <Uefi.h>
+
+/**
+ Function to get serdes Lane protocol corresponding to
+ serdes protocol.
+
+ @param SerDes Serdes number.
+ @param Cfg Serdes Protocol.
+ @param Lane Serdes Lane number.
+
+ @return Serdes Lane protocol.
+
+**/
+STATIC
+SERDES_PROTOCOL
+GetSerDesPrtcl (
+ IN INTN SerDes,
+ IN INTN Cfg,
+ IN INTN Lane
+ )
+{
+ SERDES_CONFIG *Config;
+
+ if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
+ return 0;
+ }
+
+ Config = SerDesConfigTbl[SerDes];
+ while (Config->Protocol) {
+ if (Config->Protocol == Cfg) {
+ return Config->SrdsLane[Lane];
+ }
+ Config++;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to check if inputted protocol is a valid serdes protocol.
+
+ @param SerDes Serdes number.
+ @param Prtcl Serdes Protocol to be verified.
+
+ @return EFI_INVALID_PARAMETER Input parameter in invalid.
+ @return EFI_NOT_FOUND Serdes Protocol not a valid protocol.
+ @return EFI_SUCCESS Serdes Protocol is a valid protocol.
+
+**/
+STATIC
+EFI_STATUS
+CheckSerDesPrtclValid (
+ IN INTN SerDes,
+ IN UINT32 Prtcl
+ )
+{
+ SERDES_CONFIG *Config;
+ INTN Cnt;
+
+ if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Config = SerDesConfigTbl[SerDes];
+ while (Config->Protocol) {
+ if (Config->Protocol == Prtcl) {
+ DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl));
+ break;
+ }
+ Config++;
+ }
+
+ if (!Config->Protocol) {
+ return EFI_NOT_FOUND;
+ }
+
+ for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
+ if (Config->SrdsLane[Cnt] != NONE) {
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+ Function to fill serdes map information.
+
+ @param Srds Serdes number.
+ @param SerdesProtocolMask Serdes Protocol Mask.
+ @param SerdesProtocolShift Serdes Protocol shift value.
+ @param SerDesPrtclMap Pointer to Serdes Protocol map.
+
+**/
+STATIC
+VOID
+LSSerDesMap (
+ IN UINT32 Srds,
+ IN UINT32 SerdesProtocolMask,
+ IN UINT32 SerdesProtocolShift,
+ OUT UINT64 *SerDesPrtclMap
+ )
+{
+ CCSR_GUR *Gur;
+ UINT32 SrdsProt;
+ INTN Lane;
+ UINT32 Flag;
+
+ Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ *SerDesPrtclMap = 0x0;
+ Flag = 0;
+
+ SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
+ SrdsProt >>= SerdesProtocolShift;
+
+ DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
+ Srds + 1, SrdsProt, SrdsProt));
+
+ if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
+ DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
+ Srds + 1, SrdsProt));
+ Flag++;
+ }
+
+ for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
+ SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
+ if (LanePrtcl >= SERDES_PRTCL_COUNT) {
+ DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
+ Flag++;
+ } else {
+ *SerDesPrtclMap |= BIT (LanePrtcl);
+ }
+ }
+
+ if (Flag) {
+ DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
+ }
+}
+
+/**
+ Get lane protocol on provided serdes lane and execute callback function.
+
+ @param Srds Serdes number.
+ @param SerdesProtocolMask Mask to get Serdes Protocol for Srds
+ @param SerdesProtocolShift Shift value to get Serdes Protocol for Srds.
+ @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
+ @param Arg Pointer to Arguments to be passed to callback function.
+
+**/
+STATIC
+VOID
+SerDesInstanceProbeLanes (
+ IN UINT32 Srds,
+ IN UINT32 SerdesProtocolMask,
+ IN UINT32 SerdesProtocolShift,
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ )
+{
+
+ CCSR_GUR *Gur;
+ UINT32 SrdsProt;
+ INTN Lane;
+
+ Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
+
+ SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
+ SrdsProt >>= SerdesProtocolShift;
+
+ /*
+ * Invoke callback for all lanes in the SerDes instance:
+ */
+ for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
+ SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
+ if (LanePrtcl >= SERDES_PRTCL_COUNT || LanePrtcl < NONE) {
+ DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
+ }
+ else if (LanePrtcl != NONE) {
+ SerDesLaneProbeCallback (LanePrtcl, Arg);
+ }
+ }
+}
+
+/**
+ Probe all serdes lanes for lane protocol and execute provided callback function.
+
+ @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
+ @param Arg Pointer to Arguments to be passed to callback function.
+
+**/
+VOID
+SerDesProbeLanes (
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ )
+{
+ SerDesInstanceProbeLanes (SRDS_1,
+ RCWSR_SRDS1_PRTCL_MASK,
+ RCWSR_SRDS1_PRTCL_SHIFT,
+ SerDesLaneProbeCallback,
+ Arg);
+
+ if (PcdGetBool (PcdSerdes2Enabled)) {
+ SerDesInstanceProbeLanes (SRDS_2,
+ RCWSR_SRDS2_PRTCL_MASK,
+ RCWSR_SRDS2_PRTCL_SHIFT,
+ SerDesLaneProbeCallback,
+ Arg);
+ }
+}
+
+/**
+ Function to return Serdes protocol map for all serdes available on board.
+
+ @param SerDesPrtclMap Pointer to Serdes protocl map.
+
+**/
+VOID
+GetSerdesProtocolMaps (
+ OUT UINT64 *SerDesPrtclMap
+ )
+{
+ LSSerDesMap (SRDS_1,
+ RCWSR_SRDS1_PRTCL_MASK,
+ RCWSR_SRDS1_PRTCL_SHIFT,
+ SerDesPrtclMap);
+
+ if (PcdGetBool (PcdSerdes2Enabled)) {
+ LSSerDesMap (SRDS_2,
+ RCWSR_SRDS2_PRTCL_MASK,
+ RCWSR_SRDS2_PRTCL_SHIFT,
+ SerDesPrtclMap);
+ }
+
+}
+
+BOOLEAN
+IsSerDesLaneProtocolConfigured (
+ IN UINT64 SerDesPrtclMap,
+ IN SERDES_PROTOCOL Device
+ )
+{
+ if (Device >= SERDES_PRTCL_COUNT || Device < NONE) {
+ ASSERT (Device > NONE && Device < SERDES_PRTCL_COUNT);
+ DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device));
+ }
+
+ return (SerDesPrtclMap & BIT (Device)) != 0 ;
+}
diff --git a/Silicon/NXP/Include/Bitops.h b/Silicon/NXP/Include/Bitops.h
new file mode 100644
index 0000000..beddb4e
--- /dev/null
+++ b/Silicon/NXP/Include/Bitops.h
@@ -0,0 +1,179 @@
+/** Bitops.h
+ Header defining the general bitwise operations
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __BITOPS_H__
+#define __BITOPS_H__
+
+#include <Library/DebugLib.h>
+
+#define MASK_LOWER_16 0xFFFF0000
+#define MASK_UPPER_16 0x0000FFFF
+#define MASK_LOWER_8 0xFF000000
+#define MASK_UPPER_8 0x000000FF
+
+/*
+ * Returns the bit mask for a bit index from 0 to 31
+ */
+#define BIT(_BitIndex) (0x1u << (_BitIndex))
+
+/**
+ * Upper32Bits - return bits 32-63 of a number
+ * @N: the number we're accessing
+ *
+ * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
+ * the "right shift count >= width of type" warning when that quantity is
+ * 32-bits.
+ */
+#define Upper32Bits(N) ((UINT32)(((N) >> 16) >> 16))
+
+/**
+ * Lower32Bits - return bits 0-31 of a number
+ * @N: the number we're accessing
+ */
+#define Lower32Bits(N) ((UINT32)(N))
+
+
+/*
+ * Stores a value for a given bit field in 32-bit '_Container'
+ */
+
+#define SET_BIT_FIELD32(_Container, _BitShift, _BitWidth, _Value) \
+ __SET_BIT_FIELD32(_Container, \
+ __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth), \
+ _BitShift, \
+ _Value)
+
+#define __SET_BIT_FIELD32(_Container, _BitMask, _BitShift, _Value) \
+ do { \
+ (_Container) &= ~(_BitMask); \
+ if ((_Value) != 0) { \
+ ASSERT(((UINT32)(_Value) << (_BitShift)) <= (_BitMask)); \
+ (_Container) |= \
+ ((UINT32)(_Value) << (_BitShift)) & (_BitMask); \
+ } \
+ } while (0)
+
+/*
+ * Extracts the value for a given bit field in 32-bit _Container
+ */
+
+#define GET_BIT_FIELD32(_Container, _BitShift, _BitWidth) \
+ __GET_BIT_FIELD32(_Container, \
+ __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth), \
+ _BitShift)
+
+#define __GET_BIT_FIELD32(_Container, _BitMask, _BitShift) \
+ (((UINT32)(_Container) & (_BitMask)) >> (_BitShift))
+
+#define __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth) \
+ ((_BitWidth) < 32 ? \
+ (((UINT32)1 << (_BitWidth)) - 1) << (_BitShift) : \
+ ~(UINT32)0)
+
+/*
+ *Stores a value for a given bit field in 64-bit '_Container'
+ */
+#define SET_BIT_FIELD64(_Container, _BitShift, _BitWidth, _Value) \
+ __SET_BIT_FIELD64(_Container, \
+ __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth), \
+ _BitShift, \
+ _Value)
+
+#define __SET_BIT_FIELD64(_Container, _BitMask, _BitShift, _Value) \
+ do { \
+ (_Container) &= ~(_BitMask); \
+ if ((_Value) != 0) { \
+ ASSERT(((UINT64)(_Value) << (_BitShift)) <= (_BitMask)); \
+ (_Container) |= \
+ ((UINT64)(_Value) << (_BitShift)) & (_BitMask); \
+ } \
+ } while (0)
+
+/*
+ * Extracts the value for a given bit field in 64-bit _Container
+ */
+#define GET_BIT_FIELD64(_Container, _BitShift, _BitWidth) \
+ __GET_BIT_FIELD64(_Container, \
+ __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth), \
+ _BitShift)
+
+#define __GET_BIT_FIELD64(_Container, _BitMask, _BitShift) \
+ (((UINT64)(_Container) & (_BitMask)) >> (_BitShift))
+
+#define __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth) \
+ ((_BitWidth) < 64 ? \
+ (((UINT64)1 << (_BitWidth)) - 1) << (_BitShift) : \
+ ~(UINT64)0)
+
+/**
+
+ Test If the Destination buffer sets (0->1) or clears (1->0) any bit in Source buffer ?
+
+ @param[in] Source Source Buffer Pointer
+ @param[in] Destination Destination Buffer Pointer
+ @param[in] NumBytes Bytes to Compare
+ @param[in] Set True : Test Weather Destination buffer sets any bit in Source buffer ?
+ False : Test Weather Destination buffer clears any bit in Source buffer ?
+
+ @retval TRUE Destination buffer sets/clear a bit in source buffer.
+ @retval FALSE Destination buffer doesn't sets/clear bit in source buffer.
+
+**/
+STATIC
+inline
+BOOLEAN
+TestBitSetClear (
+ IN VOID *Source,
+ IN VOID *Destination,
+ IN UINTN NumBytes,
+ IN BOOLEAN Set
+ )
+{
+ UINTN Index = 0;
+ VOID* Buffer;
+
+ if (Set) {
+ Buffer = Destination;
+ } else {
+ Buffer = Source;
+ }
+
+ while (Index < NumBytes) {
+ if ((NumBytes - Index) >= 8) {
+ if ((*((UINT64*)(Source+Index)) ^ *((UINT64*)(Destination+Index))) & *((UINT64*)(Buffer+Index))) {
+ return TRUE;
+ }
+ Index += 8;
+ } else if ((NumBytes - Index) >= 4) {
+ if ((*((UINT32*)(Source+Index)) ^ *((UINT32*)(Destination+Index))) & *((UINT32*)(Buffer+Index))) {
+ return TRUE;
+ }
+ Index += 4;
+ } else if ((NumBytes - Index) >= 2) {
+ if ((*((UINT16*)(Source+Index)) ^ *((UINT16*)(Destination+Index))) & *((UINT16*)(Buffer+Index))) {
+ return TRUE;
+ }
+ Index += 2;
+ } else if ((NumBytes - Index) >= 1) {
+ if ((*((UINT8*)(Source+Index)) ^ *((UINT8*)(Destination+Index))) & *((UINT8*)(Buffer+Index))) {
+ return TRUE;
+ }
+ Index += 1;
+ }
+ }
+ return FALSE;
+}
+
+#endif
diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
new file mode 100644
index 0000000..90e165f
--- /dev/null
+++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h
@@ -0,0 +1,55 @@
+/** @file
+ The Header file of SerDes Module for LS1043A
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SOC_SERDES_H__
+#define __SOC_SERDES_H__
+
+#include <SerDes.h>
+
+SERDES_CONFIG SerDes1ConfigTbl[] = {
+ /* SerDes 1 */
+ {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } },
+ {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
+ {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } },
+ {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } },
+ {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } },
+ {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } },
+ {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
+ {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } },
+ {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+ {0x9998, {PCIE1, PCIE2, PCIE3, SATA } },
+ {0x6058, {PCIE1, PCIE1, PCIE2, SATA } },
+ {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+ {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+ {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+ {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+ {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+ {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+ {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } },
+ {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {}
+};
+
+SERDES_CONFIG *SerDesConfigTbl[] = {
+ SerDes1ConfigTbl
+};
+
+#endif /* __SOC_SERDES_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 04/39] Silicon/NXP : Add support for DUART library
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (2 preceding siblings ...)
2018-02-16 8:49 ` [PATCH edk2-platforms 03/39] SocLib : Add support for initialization of peripherals Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-18 15:15 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver Meenakshi
` (37 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Library/DUartPortLib/DUart.h | 128 ++++++++
Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 370 ++++++++++++++++++++++
Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 41 +++
3 files changed, 539 insertions(+)
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h b/Silicon/NXP/Library/DUartPortLib/DUart.h
new file mode 100644
index 0000000..3fa0a68
--- /dev/null
+++ b/Silicon/NXP/Library/DUartPortLib/DUart.h
@@ -0,0 +1,128 @@
+/** DUart.h
+* Header defining the DUART constants (Base addresses, sizes, flags)
+*
+* Based on Serial I/O Port library headers available in PL011Uart.h
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __DUART_H__
+#define __DUART_H__
+
+// FIFO Control Register
+#define DUART_FCR_FIFO_EN 0x01 /* Fifo enable */
+#define DUART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
+#define DUART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
+#define DUART_FCR_DMA_SELECT 0x08 /* For DMA applications */
+#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
+#define DUART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
+#define DUART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
+#define DUART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
+#define DUART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
+#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */
+#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */
+
+// Modem Control Register
+#define DUART_MCR_DTR 0x01 /* Reserved */
+#define DUART_MCR_RTS 0x02 /* RTS */
+#define DUART_MCR_OUT1 0x04 /* Reserved */
+#define DUART_MCR_OUT2 0x08 /* Reserved */
+#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define DUART_MCR_AFE 0x20 /* AFE (Auto Flow Control) */
+#define DUART_MCR_DMA_EN 0x04
+#define DUART_MCR_TX_DFR 0x08
+
+// Line Control Register
+/*
+* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting
+* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+*/
+#define DUART_LCR_WLS_MSK 0x03 /* character length select mask */
+#define DUART_LCR_WLS_5 0x00 /* 5 bit character length */
+#define DUART_LCR_WLS_6 0x01 /* 6 bit character length */
+#define DUART_LCR_WLS_7 0x02 /* 7 bit character length */
+#define DUART_LCR_WLS_8 0x03 /* 8 bit character length */
+#define DUART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
+#define DUART_LCR_PEN 0x08 /* Parity eneble */
+#define DUART_LCR_EPS 0x10 /* Even Parity Select */
+#define DUART_LCR_STKP 0x20 /* Stick Parity */
+#define DUART_LCR_SBRK 0x40 /* Set Break */
+#define DUART_LCR_BKSE 0x80 /* Bank select enable */
+#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */
+
+// Line Status Register
+#define DUART_LSR_DR 0x01 /* Data ready */
+#define DUART_LSR_OE 0x02 /* Overrun */
+#define DUART_LSR_PE 0x04 /* Parity error */
+#define DUART_LSR_FE 0x08 /* Framing error */
+#define DUART_LSR_BI 0x10 /* Break */
+#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */
+#define DUART_LSR_TEMT 0x40 /* Xmitter empty */
+#define DUART_LSR_ERR 0x80 /* Error */
+
+// Modem Status Register
+#define DUART_MSR_DCTS 0x01 /* Delta CTS */
+#define DUART_MSR_DDSR 0x02 /* Reserved */
+#define DUART_MSR_TERI 0x04 /* Reserved */
+#define DUART_MSR_DDCD 0x08 /* Reserved */
+#define DUART_MSR_CTS 0x10 /* Clear to Send */
+#define DUART_MSR_DSR 0x20 /* Reserved */
+#define DUART_MSR_RI 0x40 /* Reserved */
+#define DUART_MSR_DCD 0x80 /* Reserved */
+
+// Interrupt Identification Register
+#define DUART_IIR_NO_INT 0x01 /* No interrupts pending */
+#define DUART_IIR_ID 0x06 /* Mask for the interrupt ID */
+#define DUART_IIR_MSI 0x00 /* Modem status interrupt */
+#define DUART_IIR_THRI 0x02 /* Transmitter holding register empty */
+#define DUART_IIR_RDI 0x04 /* Receiver data interrupt */
+#define DUART_IIR_RLSI 0x06 /* Receiver line status interrupt */
+
+// Interrupt Enable Register
+#define DUART_IER_MSI 0x08 /* Enable Modem status interrupt */
+#define DUART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
+#define DUART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
+#define DUART_IER_RDI 0x01 /* Enable receiver data interrupt */
+
+// LCR defaults
+#define DUART_LCR_8N1 0x03
+#define DUART_LCRVAL DUART_LCR_8N1 /* 8 data, 1 stop, no parity */
+#define DUART_MCRVAL (DUART_MCR_DTR | \
+ DUART_MCR_RTS) /* RTS/DTR */
+#define DUART_FCRVAL (DUART_FCR_FIFO_EN | \
+ DUART_FCR_RXSR | \
+ DUART_FCR_TXSR) /* Clear & enable FIFOs */
+
+#define URBR 0x0
+#define UTHR 0x0
+#define UDLB 0x0
+#define UDMB 0x1
+#define UIER 0x1
+#define UIIR 0x2
+#define UFCR 0x2
+#define UAFR 0x2
+#define ULCR 0x3
+#define UMCR 0x4
+#define ULSR 0x5
+#define UMSR 0x6
+#define USCR 0x7
+#define UDSR 0x10
+
+extern
+UINT64
+GetBusFrequency (
+ VOID
+ );
+
+#endif /* __DUART_H__ */
diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
new file mode 100644
index 0000000..5fcfa9a
--- /dev/null
+++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
@@ -0,0 +1,370 @@
+/** DuartPortLib.c
+ DUART (NS16550) library functions
+
+ Based on Serial I/O Port library functions available in PL011SerialPortLib.c
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+
+#include "DUart.h"
+
+STATIC CONST UINT32 mInvalidControlBits = (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE | \
+ EFI_SERIAL_DATA_TERMINAL_READY);
+
+/**
+ Assert or deassert the control signals on a serial port.
+ The following control signals are set according their bit settings :
+ . Request to Send
+ . Data Terminal Ready
+
+ @param[in] Control The following bits are taken into account :
+ . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
+ "Request To Send" control signal if this bit is
+ equal to one/zero.
+ . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
+ the "Data Terminal Ready" control signal if this
+ bit is equal to one/zero.
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
+ the hardware loopback if this bit is equal to
+ one/zero.
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
+ disable the hardware flow control based on CTS (Clear
+ To Send) and RTS (Ready To Send) control signals.
+
+ @retval EFI_SUCCESS The new control bits were set on the device.
+ @retval EFI_UNSUPPORTED The device does not support this operation.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortSetControl (
+ IN UINT32 Control
+ )
+{
+ UINT32 McrBits;
+ UINTN UartBase;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ if (Control & (mInvalidControlBits)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ McrBits = MmioRead8 (UartBase + UMCR);
+
+ if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
+ McrBits |= DUART_MCR_RTS;
+ } else {
+ McrBits &= ~DUART_MCR_RTS;
+ }
+
+ if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {
+ McrBits |= DUART_MCR_LOOP;
+ } else {
+ McrBits &= ~DUART_MCR_LOOP;
+ }
+
+ if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
+ McrBits |= DUART_MCR_AFE;
+ } else {
+ McrBits &= ~DUART_MCR_AFE;
+ }
+
+ MmioWrite32 (UartBase + UMCR, McrBits);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Retrieve the status of the control bits on a serial device.
+
+ @param[out] Control Status of the control bits on a serial device :
+
+ . EFI_SERIAL_DATA_CLEAR_TO_SEND,
+ EFI_SERIAL_DATA_SET_READY,
+ EFI_SERIAL_RING_INDICATE,
+ EFI_SERIAL_CARRIER_DETECT,
+ EFI_SERIAL_REQUEST_TO_SEND,
+ EFI_SERIAL_DATA_TERMINAL_READY
+ are all related to the DTE (Data Terminal Equipment)
+ and DCE (Data Communication Equipment) modes of
+ operation of the serial device.
+ . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
+ receive buffer is empty, 0 otherwise.
+ . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
+ transmit buffer is empty, 0 otherwise.
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
+ the hardware loopback is enabled (the ouput feeds the
+ receive buffer), 0 otherwise.
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if
+ a loopback is accomplished by software, 0 otherwise.
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
+ one if the hardware flow control based on CTS (Clear
+ To Send) and RTS (Ready To Send) control signals is
+ enabled, 0 otherwise.
+
+ @retval EFI_SUCCESS The control bits were read from the serial device.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortGetControl (
+ OUT UINT32 *Control
+ )
+{
+ UINT32 MsrRegister;
+ UINT32 McrRegister;
+ UINT32 LsrRegister;
+ UINTN UartBase;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ MsrRegister = MmioRead8 (UartBase + UMSR);
+ McrRegister = MmioRead8 (UartBase + UMCR);
+ LsrRegister = MmioRead8 (UartBase + ULSR);
+
+ *Control = 0;
+
+ if ((MsrRegister & DUART_MSR_CTS) == DUART_MSR_CTS) {
+ *Control |= EFI_SERIAL_CLEAR_TO_SEND;
+ }
+
+ if ((McrRegister & DUART_MCR_RTS) == DUART_MCR_RTS) {
+ *Control |= EFI_SERIAL_REQUEST_TO_SEND;
+ }
+
+ if ((LsrRegister & DUART_LSR_TEMT) == DUART_LSR_TEMT) {
+ *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+ }
+
+ if ((McrRegister & DUART_MCR_AFE) == DUART_MCR_AFE) {
+ *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
+ }
+
+ if ((McrRegister & DUART_MCR_LOOP) == DUART_MCR_LOOP) {
+ *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/*
+ * Return Baud divisor on basis of Baudrate
+ */
+UINT32
+CalculateBaudDivisor (
+ IN UINT64 BaudRate
+ )
+{
+ UINTN DUartClk;
+ UINTN FreqSystemBus;
+
+ FreqSystemBus = GetBusFrequency ();
+ DUartClk = FreqSystemBus/PcdGet32(PcdPlatformFreqDiv);
+
+ return ((DUartClk)/(BaudRate * 16));
+}
+
+/*
+ Initialise the serial port to the specified settings.
+ All unspecified settings will be set to the default values.
+
+ @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER.
+
+ **/
+VOID
+EFIAPI
+DuartInitializePort (
+ IN UINT64 BaudRate
+ )
+{
+ UINTN UartBase;
+ UINT32 BaudDivisor;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+ BaudDivisor = CalculateBaudDivisor (BaudRate);
+
+
+ while (!(MmioRead8 (UartBase + ULSR) & DUART_LSR_TEMT));
+
+ //
+ // Enable and assert interrupt when new data is available on
+ // external device,
+ // setup data format, setup baud divisor
+ //
+ MmioWrite8 (UartBase + UIER, 0x1);
+ MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
+ MmioWrite8 (UartBase + UDLB, 0);
+ MmioWrite8 (UartBase + UDMB, 0);
+ MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
+ MmioWrite8 (UartBase + UMCR, DUART_MCRVAL);
+ MmioWrite8 (UartBase + UFCR, DUART_FCRVAL);
+ MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
+ MmioWrite8 (UartBase + UDLB, BaudDivisor & 0xff);
+ MmioWrite8 (UartBase + UDMB, (BaudDivisor >> 8) & 0xff);
+ MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
+
+ return;
+}
+
+/**
+ Programmed hardware of Serial port.
+
+ @return Always return EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ UINT64 BaudRate;
+ BaudRate = (UINTN)PcdGet64 (PcdUartDefaultBaudRate);
+
+
+ DuartInitializePort (BaudRate);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write data to serial device.
+
+ @param Buffer Point of data buffer which need to be written.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Write data failed.
+ @retval !0 Actual number of bytes written to serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
+{
+ UINT8 *Final;
+ UINTN UartBase;
+
+ Final = &Buffer[NumberOfBytes];
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ while (Buffer < Final) {
+ while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_THRE) == 0);
+ MmioWrite8 (UartBase + UTHR, *Buffer++);
+ }
+
+ return NumberOfBytes;
+}
+
+/**
+ Read data from serial device and save the data in buffer.
+
+ @param Buffer Point of data buffer which need to be written.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Read data failed.
+ @retval !0 Actual number of bytes read from serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
+{
+ UINTN Count;
+ UINTN UartBase;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
+ // Loop while waiting for a new char(s) to arrive in the
+ // RxFIFO
+ while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) == 0);
+
+ *Buffer = MmioRead8 (UartBase + URBR);
+ }
+
+ return NumberOfBytes;
+}
+
+/**
+ Check to see if any data is available to be read from the debug device.
+
+ @retval EFI_SUCCESS At least one byte of data is available to be read
+ @retval EFI_NOT_READY No data is available to be read
+ @retval EFI_DEVICE_ERROR The serial device is not functioning properly
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+ UINTN UartBase;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ return ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) != 0);
+}
+
+/**
+ Set new attributes to LS1043a.
+
+ @param BaudRate The baud rate of the serial device. If the baud rate is not supported,
+ the speed will be reduced down to the nearest supported one and the
+ variable's value will be updated accordingly.
+ @param ReceiveFifoDepth The number of characters the device will buffer on input. If the specified
+ value is not supported, the variable's value will be reduced down to the
+ nearest supported one.
+ @param Timeout If applicable, the number of microseconds the device will wait
+ before timing out a Read or a Write operation.
+ @param Parity If applicable, this is the EFI_PARITY_TYPE that is computed or checked
+ as each character is transmitted or received. If the device does not
+ support parity, the value is the default parity value.
+ @param DataBits The number of data bits in each character
+ @param StopBits If applicable, the EFI_STOP_BITS_TYPE number of stop bits per character.
+ If the device does not support stop bits, the value is the default stop
+ bit value.
+
+ @retval EFI_SUCCESS All attributes were set correctly on the serial device.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortSetAttributes (
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+ )
+{
+ DuartInitializePort (*BaudRate);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
new file mode 100644
index 0000000..6940de9
--- /dev/null
+++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
@@ -0,0 +1,41 @@
+# DUartPortLib.inf
+#
+# Component description file for DUartPortLib module
+#
+# Copyright (c) 2013, Freescale Ltd. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = DUartPortLib
+ FILE_GUID = c42dfe79-8de5-429e-a055-2d0a58591498
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialPortLib
+
+[Sources.common]
+ DUartPortLib.c
+
+[LibraryClasses]
+ PcdLib
+ SocLib
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (3 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 04/39] Silicon/NXP : Add support for DUART library Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-17 16:36 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 06/39] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi
` (36 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
I2C driver produces gEfiI2cMasterProtocolGuid which can be
used by other modules.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 726 ++++++++++++++++++++++++++++++++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 65 +++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 55 +++
3 files changed, 846 insertions(+)
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
new file mode 100644
index 0000000..80a8826
--- /dev/null
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
@@ -0,0 +1,726 @@
+/** I2cDxe.c
+ I2c driver APIs for read, write, initialize, set speed and reset
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/I2cMaster.h>
+
+#include "I2cDxe.h"
+
+STATIC CONST UINT16 ClkDiv[60][2] = {
+ { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
+ { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
+ { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
+ { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
+ { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
+ { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
+ { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
+ { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
+ { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
+ { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
+ { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
+ { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 },{ 1280, 0x35 },
+ { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
+ { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
+ { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
+};
+
+/**
+ Calculate and return proper clock divider
+
+ @param Rate clock rate
+
+ @retval ClkDiv Value used to get frequency divider value
+
+**/
+STATIC
+UINT8
+GetClkDiv (
+ IN UINT32 Rate
+ )
+{
+ UINTN ClkRate;
+ UINT32 Div;
+ UINT8 ClkDivx;
+
+ ClkRate = GetBusFrequency ();
+
+ Div = (ClkRate + Rate - 1) / Rate;
+
+ if (Div < ClkDiv[0][0]) {
+ ClkDivx = 0;
+ } else if (Div > ClkDiv[ARRAY_SIZE (ClkDiv) - 1][0]){
+ ClkDivx = ARRAY_SIZE (ClkDiv) - 1;
+ } else {
+ for (ClkDivx = 0; ClkDiv[ClkDivx][0] < Div; ClkDivx++);
+ }
+
+ return ClkDivx;
+}
+
+/**
+ Function used to check if i2c is in mentioned state or not
+
+ @param I2cRegs Pointer to I2C registers
+ @param State i2c state need to be checked
+
+ @retval EFI_NOT_READY Arbitration was lost
+ @retval EFI_TIMEOUT Timeout occured
+ @retval CurrState Value of state register
+
+**/
+STATIC
+EFI_STATUS
+WaitForI2cState (
+ IN I2C_REGS *I2cRegs,
+ IN UINT32 State
+ )
+{
+ UINT8 CurrState;
+ UINT64 Cnt;
+
+ for (Cnt = 0; Cnt < 50000; Cnt++) {
+ MemoryFence ();
+ CurrState = MmioRead8 ((UINTN)&I2cRegs->I2cSr);
+ if (CurrState & I2C_SR_IAL) {
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, CurrState | I2C_SR_IAL);
+ return EFI_NOT_READY;
+ }
+
+ if ((CurrState & (State >> 8)) == (UINT8)State) {
+ return CurrState;
+ }
+ }
+
+ return EFI_TIMEOUT;
+}
+
+/**
+ Function to transfer byte on i2c
+
+ @param I2cRegs Pointer to i2c registers
+ @param Byte Byte to be transferred on i2c bus
+
+ @retval EFI_NOT_READY Arbitration was lost
+ @retval EFI_TIMEOUT Timeout occured
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Data transfer was succesful
+
+**/
+STATIC
+EFI_STATUS
+TransferByte (
+ IN I2C_REGS *I2cRegs,
+ IN UINT8 Byte
+ )
+{
+ EFI_STATUS Ret;
+
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+ MmioWrite8 ((UINTN)&I2cRegs->I2cDr, Byte);
+
+ Ret = WaitForI2cState (I2cRegs, IIF);
+ if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
+ return Ret;
+ }
+
+ if (Ret & I2C_SR_RX_NO_AK) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to stop transaction on i2c bus
+
+ @param I2cRegs Pointer to i2c registers
+
+ @retval EFI_NOT_READY Arbitration was lost
+ @retval EFI_TIMEOUT Timeout occured
+ @retval EFI_SUCCESS Stop operation was successful
+
+**/
+STATIC
+EFI_STATUS
+I2cStop (
+ IN I2C_REGS *I2cRegs
+ )
+{
+ INT32 Ret;
+ UINT32 Temp;
+
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+
+ Temp &= ~(I2C_CR_MSTA | I2C_CR_MTX);
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+ Ret = WaitForI2cState (I2cRegs, BUS_IDLE);
+
+ if (Ret < 0) {
+ return Ret;
+ } else {
+ return EFI_SUCCESS;
+ }
+}
+
+/**
+ Function to send start signal, Chip Address and
+ memory offset
+
+ @param I2cRegs Pointer to i2c base registers
+ @param Chip Chip Address
+ @param Offset Slave memory's offset
+ @param Alen length of chip address
+
+ @retval EFI_NOT_READY Arbitration lost
+ @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Read was successful
+
+**/
+STATIC
+EFI_STATUS
+InitTransfer (
+ IN I2C_REGS *I2cRegs,
+ IN UINT8 Chip,
+ IN UINT32 Offset,
+ IN INT32 Alen
+ )
+{
+ UINT32 Temp;
+ EFI_STATUS Ret;
+
+ // Enable I2C controller
+ if (MmioRead8 ((UINTN)&I2cRegs->I2cCr) & I2C_CR_IDIS) {
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IEN);
+ }
+
+ if (MmioRead8 ((UINTN)&I2cRegs->I2cAdr) == (Chip << 1)) {
+ MmioWrite8 ((UINTN)&I2cRegs->I2cAdr, (Chip << 1) ^ 2);
+ }
+
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+ Ret = WaitForI2cState (I2cRegs, BUS_IDLE);
+ if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
+ return Ret;
+ }
+
+ // Start I2C transaction
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+ // set to master mode
+ Temp |= I2C_CR_MSTA;
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+ Ret = WaitForI2cState (I2cRegs, BUS_BUSY);
+ if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
+ return Ret;
+ }
+
+ Temp |= I2C_CR_MTX | I2C_CR_TX_NO_AK;
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+ // write slave Address
+ Ret = TransferByte (I2cRegs, Chip << 1);
+ if (Ret != EFI_SUCCESS) {
+ return Ret;
+ }
+
+ if (Alen >= 0) {
+ while (Alen--) {
+ Ret = TransferByte (I2cRegs, (Offset >> (Alen * 8)) & 0xff);
+ if (Ret != EFI_SUCCESS)
+ return Ret;
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to check if i2c bus is idle
+
+ @param Base Pointer to base address of I2c controller
+
+ @retval EFI_SUCCESS
+
+**/
+STATIC
+INT32
+I2cBusIdle (
+ IN VOID *Base
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to initiate data transfer on i2c bus
+
+ @param I2cRegs Pointer to i2c base registers
+ @param Chip Chip Address
+ @param Offset Slave memory's offset
+ @param Alen length of chip address
+
+ @retval EFI_NOT_READY Arbitration lost
+ @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Read was successful
+
+**/
+STATIC
+EFI_STATUS
+InitDataTransfer (
+ IN I2C_REGS *I2cRegs,
+ IN UINT8 Chip,
+ IN UINT32 Offset,
+ IN INT32 Alen
+ )
+{
+ EFI_STATUS Status;
+ INT32 Retry;
+
+ for (Retry = 0; Retry < 3; Retry++) {
+ Status = InitTransfer (I2cRegs, Chip, Offset, Alen);
+ if (Status == EFI_SUCCESS) {
+ return EFI_SUCCESS;
+ }
+
+ I2cStop (I2cRegs);
+
+ if (EFI_NOT_FOUND == Status) {
+ return Status;
+ }
+
+ // Disable controller
+ if (Status != EFI_NOT_READY) {
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
+ }
+
+ if (I2cBusIdle (I2cRegs) < 0) {
+ break;
+ }
+ }
+ return Status;
+}
+
+/**
+ Function to read data using i2c bus
+
+ @param I2cBus I2c Controller number
+ @param Chip Address of slave device from where data to be read
+ @param Offset Offset of slave memory
+ @param Alen Address length of slave
+ @param Buffer A pointer to the destination buffer for the data
+ @param Len Length of data to be read
+
+ @retval EFI_NOT_READY Arbitration lost
+ @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Read was successful
+
+**/
+STATIC
+EFI_STATUS
+I2cDataRead (
+ IN UINT32 I2cBus,
+ IN UINT8 Chip,
+ IN UINT32 Offset,
+ IN UINT32 Alen,
+ IN UINT8 *Buffer,
+ IN UINT32 Len
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Temp;
+ INT32 I;
+ I2C_REGS *I2cRegs;
+
+ I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
+ (I2cBus * FixedPcdGet32 (PcdI2cSize))));
+
+ Status = InitDataTransfer (I2cRegs, Chip, Offset, Alen);
+ if (Status != EFI_SUCCESS) {
+ return Status;
+ }
+
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+ Temp |= I2C_CR_RSTA;
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+ Status = TransferByte (I2cRegs, (Chip << 1) | 1);
+ if (Status != EFI_SUCCESS) {
+ I2cStop (I2cRegs);
+ return Status;
+ }
+
+ // setup bus to read data
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+ Temp &= ~(I2C_CR_MTX | I2C_CR_TX_NO_AK);
+ if (Len == 1) {
+ Temp |= I2C_CR_TX_NO_AK;
+ }
+
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+
+ // Dummy Read to initiate recieve operation
+ MmioRead8 ((UINTN)&I2cRegs->I2cDr);
+
+ for (I = 0; I < Len; I++) {
+ Status = WaitForI2cState (I2cRegs, IIF);
+ if ((Status == EFI_TIMEOUT) || (Status == EFI_NOT_READY)) {
+ I2cStop (I2cRegs);
+ return Status;
+ }
+ //
+ // It must generate STOP before read I2DR to prevent
+ // controller from generating another clock cycle
+ //
+ if (I == (Len - 1)) {
+ I2cStop (I2cRegs);
+ } else if (I == (Len - 2)) {
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+ Temp |= I2C_CR_TX_NO_AK;
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+ }
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+ Buffer[I] = MmioRead8 ((UINTN)&I2cRegs->I2cDr);
+ }
+
+ I2cStop (I2cRegs);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to write data using i2c bus
+
+ @param I2cBus I2c Controller number
+ @param Chip Address of slave device where data to be written
+ @param Offset Offset of slave memory
+ @param Alen Address length of slave
+ @param Buffer A pointer to the source buffer for the data
+ @param Len Length of data to be write
+
+ @retval EFI_NOT_READY Arbitration lost
+ @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Read was successful
+
+**/
+STATIC
+EFI_STATUS
+I2cDataWrite (
+ IN UINT32 I2cBus,
+ IN UINT8 Chip,
+ IN UINT32 Offset,
+ IN INT32 Alen,
+ OUT UINT8 *Buffer,
+ IN INT32 Len
+ )
+{
+ EFI_STATUS Status;
+ I2C_REGS *I2cRegs;
+ INT32 I;
+
+ I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
+ (I2cBus * FixedPcdGet32 (PcdI2cSize))));
+
+ Status = InitDataTransfer (I2cRegs, Chip, Offset, Alen);
+ if (Status != EFI_SUCCESS) {
+ return Status;
+ }
+
+ // Write operation
+ for (I = 0; I < Len; I++) {
+ Status = TransferByte (I2cRegs, Buffer[I]);
+ if (Status != EFI_SUCCESS) {
+ break;
+ }
+ }
+
+ I2cStop (I2cRegs);
+ return Status;
+}
+
+/**
+ Function to set i2c bus frequency
+
+ @param This Pointer to I2c master protocol
+ @param BusClockHertz value to be set
+
+ @retval EFI_SUCCESS Operation successfull
+**/
+
+EFI_STATUS
+EFIAPI
+SetBusFrequency (
+ IN CONST EFI_I2C_MASTER_PROTOCOL *This,
+ IN OUT UINTN *BusClockHertz
+ )
+{
+ I2C_REGS *I2cRegs;
+ UINT8 ClkId;
+ UINT8 SpeedId;
+
+ I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
+ (PcdGet32 (PcdI2cBus) * FixedPcdGet32 (PcdI2cSize))));
+
+ ClkId = GetClkDiv (*BusClockHertz);
+ SpeedId = ClkDiv[ClkId][1];
+
+ // Store divider value
+ MmioWrite8 ((UINTN)&I2cRegs->I2cFdr, SpeedId);
+
+ MemoryFence ();
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to reset I2c Controller
+
+ @param This Pointer to I2c master protocol
+
+ @return EFI_SUCCESS Operation successfull
+**/
+EFI_STATUS
+EFIAPI
+Reset (
+ IN CONST EFI_I2C_MASTER_PROTOCOL *This
+ )
+{
+ I2C_REGS *I2cRegs;
+
+ I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
+ (PcdGet32 (PcdI2cBus) * FixedPcdGet32 (PcdI2cSize))));
+
+ // Reset module
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, 0);
+
+ MemoryFence ();
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+StartRequest (
+ IN CONST EFI_I2C_MASTER_PROTOCOL *This,
+ IN UINTN SlaveAddress,
+ IN EFI_I2C_REQUEST_PACKET *RequestPacket,
+ IN EFI_EVENT Event OPTIONAL,
+ OUT EFI_STATUS *I2cStatus OPTIONAL
+ )
+{
+ UINT32 Count;
+ INT32 Ret;
+ UINT32 Length;
+ UINT8 *Buffer;
+ UINT32 Flag;
+ UINT32 RegAddress;
+ UINT32 OffsetLength;
+
+ RegAddress = 0;
+
+ if (RequestPacket->OperationCount <= 0) {
+ DEBUG ((DEBUG_ERROR,"%a: Operation count is not valid %d\n",
+ __FUNCTION__, RequestPacket->OperationCount));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ OffsetLength = RequestPacket->Operation[0].LengthInBytes;
+ RegAddress = *RequestPacket->Operation[0].Buffer;
+
+ for (Count = 1; Count < RequestPacket->OperationCount; Count++) {
+ Flag = RequestPacket->Operation[Count].Flags;
+ Length = RequestPacket->Operation[Count].LengthInBytes;
+ Buffer = RequestPacket->Operation[Count].Buffer;
+
+ if (Length <= 0) {
+ DEBUG ((DEBUG_ERROR,"%a: Invalid length of buffer %d\n",
+ __FUNCTION__, Length));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (Flag == I2C_FLAG_READ) {
+ Ret = I2cDataRead (PcdGet32 (PcdI2cBus), SlaveAddress,
+ RegAddress, OffsetLength, Buffer, Length);
+ if (Ret != EFI_SUCCESS) {
+ DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n",
+ __FUNCTION__, Ret));
+ return Ret;
+ }
+ } else if (Flag == I2C_FLAG_WRITE) {
+ Ret = I2cDataWrite (PcdGet32 (PcdI2cBus), SlaveAddress,
+ RegAddress, OffsetLength, Buffer, Length);
+ if (Ret != EFI_SUCCESS) {
+ DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n",
+ __FUNCTION__, Ret));
+ return Ret;
+ }
+ } else {
+ DEBUG ((DEBUG_ERROR,"%a: Invalid Flag %d\n",
+ __FUNCTION__, Flag));
+ return EFI_INVALID_PARAMETER;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+CONST EFI_I2C_CONTROLLER_CAPABILITIES I2cControllerCapabilities = {
+ 0,
+ 0,
+ 0,
+ 0
+};
+
+STATIC EFI_I2C_MASTER_PROTOCOL gI2c = {
+ ///
+ /// Set the clock frequency for the I2C bus.
+ ///
+ SetBusFrequency,
+ ///
+ /// Reset the I2C host controller.
+ ///
+ Reset,
+ ///
+ /// Start an I2C transaction in master mode on the host controller.
+ ///
+ StartRequest,
+ ///
+ /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure containing
+ /// the capabilities of the I2C host controller.
+ ///
+ &I2cControllerCapabilities
+};
+
+STATIC I2C_DEVICE_PATH gDevicePath = {
+ {
+ {
+ HARDWARE_DEVICE_PATH, HW_VENDOR_DP,
+ {
+ sizeof (VENDOR_DEVICE_PATH), 0
+ }
+ },
+ EFI_CALLER_ID_GUID
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ sizeof (EFI_DEVICE_PATH_PROTOCOL), 0
+ }
+ }
+};
+
+/**
+ The Entry Point for I2C driver.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+I2cDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Install I2c Master protocol on this controller
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gEfiI2cMasterProtocolGuid,
+ (VOID**)&gI2c,
+ &gEfiDevicePathProtocolGuid,
+ &gDevicePath,
+ NULL
+ );
+
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Unload function for the I2c Driver.
+
+ @param ImageHandle[in] The allocated handle for the EFI image
+
+ @retval EFI_SUCCESS The driver was unloaded successfully
+ @retval EFI_INVALID_PARAMETER ImageHandle is not a valid image handle.
+
+**/
+EFI_STATUS
+EFIAPI
+I2cDxeUnload (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ UINTN Index;
+
+ //
+ // Retrieve all I2c handles in the handle database
+ //
+ Status = gBS->LocateHandleBuffer (ByProtocol,
+ &gEfiI2cMasterProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Disconnect the driver from the handles in the handle database
+ //
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->DisconnectController (HandleBuffer[Index],
+ gImageHandle,
+ NULL);
+ }
+
+ //
+ // Free the handle array
+ //
+ gBS->FreePool (HandleBuffer);
+
+ //
+ // Uninstall protocols installed by the driver in its entrypoint
+ //
+ Status = gBS->UninstallMultipleProtocolInterfaces (ImageHandle,
+ &gEfiI2cMasterProtocolGuid, &gI2c,
+ &gEfiDevicePathProtocolGuid, &gDevicePath,
+ NULL);
+
+ return Status;
+}
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
new file mode 100644
index 0000000..4a562d3
--- /dev/null
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
@@ -0,0 +1,65 @@
+/** I2cDxe.h
+ Header defining the constant, base address amd function for I2C controller
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __I2C_DXE_H___
+#define __I2C_DXE_H__
+
+#include <Uefi.h>
+
+#define I2C_CR_IIEN (1 << 6)
+#define I2C_CR_MSTA (1 << 5)
+#define I2C_CR_MTX (1 << 4)
+#define I2C_CR_TX_NO_AK (1 << 3)
+#define I2C_CR_RSTA (1 << 2)
+
+#define I2C_SR_ICF (1 << 7)
+#define I2C_SR_IBB (1 << 5)
+#define I2C_SR_IAL (1 << 4)
+#define I2C_SR_IIF (1 << 1)
+#define I2C_SR_RX_NO_AK (1 << 0)
+
+#define I2C_CR_IEN (0 << 7)
+#define I2C_CR_IDIS (1 << 7)
+#define I2C_SR_IIF_CLEAR (1 << 1)
+
+#define BUS_IDLE (0 | (I2C_SR_IBB << 8))
+#define BUS_BUSY (I2C_SR_IBB | (I2C_SR_IBB << 8))
+#define IIF (I2C_SR_IIF | (I2C_SR_IIF << 8))
+
+#define I2C_FLAG_WRITE 0x0
+
+typedef struct {
+ VENDOR_DEVICE_PATH Guid;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} I2C_DEVICE_PATH;
+
+/**
+ Record defining i2c registers
+**/
+typedef struct {
+ UINT8 I2cAdr;
+ UINT8 I2cFdr;
+ UINT8 I2cCr;
+ UINT8 I2cSr;
+ UINT8 I2cDr;
+} I2C_REGS ;
+
+extern
+UINT64
+GetBusFrequency (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
new file mode 100644
index 0000000..ceb1b11
--- /dev/null
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -0,0 +1,55 @@
+# @file
+#
+# Component description file for I2c driver
+#
+# Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = I2cDxe
+ FILE_GUID = 5f2927ba-1b04-4d5f-8bef-2b50c635d1e7
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = I2cDxeEntryPoint
+ UNLOAD = I2cDxeUnload
+
+[Sources.common]
+ I2cDxe.c
+
+[LibraryClasses]
+ ArmLib
+ IoLib
+ MemoryAllocationLib
+ PcdLib
+ SocLib
+ TimerLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[Protocols]
+ gEfiI2cMasterProtocolGuid
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cBus
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
+
+[Depex]
+ TRUE
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 06/39] Silicon/Maxim : Add support for DS1307 RTC library
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (4 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-18 15:27 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 07/39] Platform/NXP: Add support for ArmPlatformLib Meenakshi
` (35 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Real time clock Apis on top of I2C Apis
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h | 59 ++++
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 329 +++++++++++++++++++++
.../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec | 26 ++
.../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf | 45 +++
4 files changed, 459 insertions(+)
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
new file mode 100644
index 0000000..96271f8
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
@@ -0,0 +1,59 @@
+/** Ds1307Rtc.h
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __DS1307RTC_H__
+#define __DS1307RTC_H__
+
+/*
+ * RTC time register
+ */
+#define DS1307_SEC_REG_ADDR 0x00
+#define DS1307_MIN_REG_ADDR 0x01
+#define DS1307_HR_REG_ADDR 0x02
+#define DS1307_DAY_REG_ADDR 0x03
+#define DS1307_DATE_REG_ADDR 0x04
+#define DS1307_MON_REG_ADDR 0x05
+#define DS1307_YR_REG_ADDR 0x06
+
+#define DS1307_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
+
+/*
+ * RTC control register
+ */
+#define DS1307_CTL_REG_ADDR 0x07
+
+#define START_YEAR 1970
+#define END_YEAR 2070
+
+/*
+ * TIME MASKS
+ */
+#define MASK_SEC 0x7F
+#define MASK_MIN 0x7F
+#define MASK_HOUR 0x3F
+#define MASK_DAY 0x3F
+#define MASK_MONTH 0x1F
+
+/*
+ * I2C FLAGS
+ */
+#define I2C_REG_ADDRESS 0x2
+
+typedef struct {
+ UINTN OperationCount;
+ EFI_I2C_OPERATION SetAddressOp;
+ EFI_I2C_OPERATION GetSetDateTimeOp;
+} RTC_I2C_REQUEST;
+
+#endif // __DS1307RTC_H__
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
new file mode 100644
index 0000000..cf45d49
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
@@ -0,0 +1,329 @@
+/** Ds1307RtcLib.c
+ Implement EFI RealTimeClock via RTC Lib for DS1307 RTC.
+
+ Based on RTC implementation available in
+ EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/I2cMaster.h>
+
+#include "Ds1307Rtc.h"
+
+STATIC VOID *mDriverEventRegistration;
+STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
+
+/**
+ Read RTC register.
+
+ @param RtcRegAddr Register offset of RTC to be read.
+
+ @retval Register Value read
+
+**/
+
+STATIC
+UINT8
+RtcRead (
+ IN UINT8 RtcRegAddr
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+ UINT8 Val;
+
+ Val = 0;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
+ }
+
+ return Val;
+}
+
+/**
+ Write RTC register.
+
+ @param RtcRegAddr Register offset of RTC to write.
+ @param Val Value to be written
+
+**/
+
+STATIC
+VOID
+RtcWrite (
+ IN UINT8 RtcRegAddr,
+ IN UINT8 Val
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = 0;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
+ }
+}
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+
+**/
+
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Second;
+ UINT8 Minute;
+ UINT8 Hour;
+ UINT8 Day;
+ UINT8 Month;
+ UINT8 Year;
+
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ Status = EFI_SUCCESS;
+
+ Second = RtcRead (DS1307_SEC_REG_ADDR);
+ Minute = RtcRead (DS1307_MIN_REG_ADDR);
+ Hour = RtcRead (DS1307_HR_REG_ADDR);
+ Day = RtcRead (DS1307_DATE_REG_ADDR);
+ Month = RtcRead (DS1307_MON_REG_ADDR);
+ Year = RtcRead (DS1307_YR_REG_ADDR);
+
+ if (Second & DS1307_SEC_BIT_CH) {
+ DEBUG ((DEBUG_ERROR, "### Warning: RTC oscillator has stopped\n"));
+ /* clear the CH flag */
+ RtcWrite (DS1307_SEC_REG_ADDR,
+ RtcRead (DS1307_SEC_REG_ADDR) & ~DS1307_SEC_BIT_CH);
+ Status = EFI_DEVICE_ERROR;
+ }
+
+ Time->Second = BcdToDecimal8 (Second & MASK_SEC);
+ Time->Minute = BcdToDecimal8 (Minute & MASK_MIN);
+ Time->Hour = BcdToDecimal8 (Hour & MASK_HOUR);
+ Time->Day = BcdToDecimal8 (Day & MASK_DAY);
+ Time->Month = BcdToDecimal8 (Month & MASK_MONTH);
+
+ //
+ // RTC can save year 1970 to 2069
+ // On writing Year, save year % 100
+ // On Reading reversing the operation e.g. 2012
+ // write = 12 (2012 % 100)
+ // read = 2012 (12 + 2000)
+ //
+ Time->Year = BcdToDecimal8 (Year) +
+ (BcdToDecimal8 (Year) >= 70 ? START_YEAR - 70 : END_YEAR -70);
+
+ return Status;
+}
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ if (Time->Year < START_YEAR || Time->Year >= END_YEAR){
+ DEBUG ((DEBUG_ERROR, "WARNING: Year should be between 1970 and 2069!\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ RtcWrite (DS1307_YR_REG_ADDR, DecimalToBcd8 (Time->Year % 100));
+ RtcWrite (DS1307_MON_REG_ADDR, DecimalToBcd8 (Time->Month));
+ RtcWrite (DS1307_DATE_REG_ADDR, DecimalToBcd8 (Time->Day));
+ RtcWrite (DS1307_HR_REG_ADDR, DecimalToBcd8 (Time->Hour));
+ RtcWrite (DS1307_MIN_REG_ADDR, DecimalToBcd8 (Time->Minute));
+ RtcWrite (DS1307_SEC_REG_ADDR, DecimalToBcd8 (Time->Second));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this
+ platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // The DS1307 does not support setting the alarm
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // The DS1307 does not support setting the alarm
+ return EFI_UNSUPPORTED;
+}
+
+STATIC
+VOID
+I2cDriverRegistrationEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_I2C_MASTER_PROTOCOL *I2cMaster;
+ UINTN BusFrequency;
+
+ Status = gBS->LocateProtocol (&gEfiI2cMasterProtocolGuid, NULL, (VOID **)&I2cMaster);
+
+ gBS->CloseEvent (Event);
+
+ ASSERT_EFI_ERROR (Status);
+
+ Status = I2cMaster->Reset (I2cMaster);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
+ __FUNCTION__, Status));
+ return;
+ }
+
+ BusFrequency = FixedPcdGet16 (PcdI2cBusFrequency);
+ Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
+ __FUNCTION__, Status));
+ return;
+ }
+
+ mI2cMaster = I2cMaster;
+}
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ //
+ // Register a protocol registration notification callback on the driver
+ // binding protocol so we can attempt to connect our I2C master to it
+ // as soon as it appears.
+ //
+ EfiCreateProtocolNotifyEvent (
+ &gEfiI2cMasterProtocolGuid,
+ TPL_CALLBACK,
+ I2cDriverRegistrationEvent,
+ NULL,
+ &mDriverEventRegistration);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
new file mode 100644
index 0000000..1aaf897
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
@@ -0,0 +1,26 @@
+#/** @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+ PACKAGE_NAME = Ds1307RtcLib
+ PACKAGE_GUID = 0c095cf6-834d-4fa2-a5a0-31ac35591ad2
+ PACKAGE_VERSION = 0.1
+
+[Guids]
+ gDs1307RtcLibTokenSpaceGuid = { 0xd939eb84, 0xa95a, 0x46a0, { 0xa8, 0x2b, 0xb9, 0x64, 0x30, 0xcf, 0xf5, 0x99 }}
+
+[PcdsFixedAtBuild]
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
new file mode 100644
index 0000000..268873b
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
@@ -0,0 +1,45 @@
+# @Ds1307RtcLib.inf
+#
+# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Ds1307RtcLib
+ FILE_GUID = 7112fb46-8dda-4a41-ac40-bf212fedfc08
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+[Sources.common]
+ Ds1307RtcLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
+
+[LibraryClasses]
+ DebugLib
+ UefiBootServicesTableLib
+ UefiLib
+
+[Protocols]
+ gEfiDriverBindingProtocolGuid ## CONSUMES
+ gEfiI2cMasterProtocolGuid ## CONSUMES
+
+[FixedPcd]
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency
+
+[Depex]
+ gEfiI2cMasterProtocolGuid
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 07/39] Platform/NXP: Add support for ArmPlatformLib
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (5 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 06/39] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-18 15:32 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 08/39] Compilation : Add the fdf, dsc and dec files Meenakshi
` (34 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../Library/PlatformLib/ArmPlatformLib.c | 105 ++++++++++++++
.../Library/PlatformLib/ArmPlatformLib.inf | 67 +++++++++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 38 ++++++
.../Library/PlatformLib/NxpQoriqLsMem.c | 152 +++++++++++++++++++++
4 files changed, 362 insertions(+)
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 0000000..ab4815d
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,105 @@
+/** ArmPlatformLib.c
+*
+* Contains board initialization functions.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+extern VOID SocInit (VOID);
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Placeholder for Platform Initialization
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = sizeof (LS1043aMpCoreInfoCTA53x4) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = LS1043aMpCoreInfoCTA53x4;
+
+ return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+ IN UINTN MpId
+ )
+{
+ return 1;
+}
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 0000000..7feac56
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,67 @@
+# @file
+#
+# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformLib
+ FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ArmLib
+ SocLib
+
+[Sources.common]
+ NxpQoriqLsHelper.S | GCC
+ NxpQoriqLsMem.c
+ ArmPlatformLib.c
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
new file mode 100644
index 0000000..205c0d8
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
@@ -0,0 +1,38 @@
+# @file
+#
+# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_IMPORT(ArmReadMpidr)
+
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ tst x0, #3
+ cset x0, eq
+ ret
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+EL1_OR_EL2(x0)
+1:
+2:
+ ret
+
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
+ ldrh w0, [x0]
+ ret
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
new file mode 100644
index 0000000..64c5612
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -0,0 +1,152 @@
+/** NxpQoriqLsMem.c
+*
+* Board memory specific Library.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
+ )
+{
+ UINTN Index;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ Index = 0;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
+ EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ // DRAM1 (Must be 1st entry)
+ VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // CCSR Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IFC region 1
+ //
+ // A-009241 : Unaligned write transactions to IFC may result in corruption of data
+ // Affects : IFC
+ // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
+ // writes on external IFC interface that can corrupt data on external flash.
+ // Impact : Data corruption on external flash may happen in case of unaligned writes to
+ // IFC memory space.
+ // Workaround: Following are the workarounds:
+ // For write transactions from core, IFC interface memories (including IFC SRAM)
+ // should be configured as device type memory in MMU.
+ // For write transactions from non-core masters (like system DMA), the address
+ // should be 16 byte aligned and the data size should be multiple of 16 bytes.
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // QMAN SWP
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // BMAN SWP
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // IFC region 2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DRAM2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // PCIe1
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe3
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DRAM3
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram3BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram3BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram3Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // QSPI region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 08/39] Compilation : Add the fdf, dsc and dec files.
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (6 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 07/39] Platform/NXP: Add support for ArmPlatformLib Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-18 15:38 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 09/39] Build : Add build script and environment script Meenakshi
` (33 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
The firmware device, description and declaration files.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/FVRules.fdf.inc | 99 +++++++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 29 ++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 84 ++++++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 197 +++++++++++++
Platform/NXP/NxpQoriqLs.dsc | 412 +++++++++++++++++++++++++++
Silicon/NXP/LS1043A/LS1043A.dec | 22 ++
Silicon/NXP/LS1043A/LS1043A.dsc | 73 +++++
Silicon/NXP/NxpQoriqLs.dec | 117 ++++++++
8 files changed, 1033 insertions(+)
create mode 100644 Platform/NXP/FVRules.fdf.inc
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
create mode 100644 Platform/NXP/NxpQoriqLs.dsc
create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc
create mode 100644 Silicon/NXP/NxpQoriqLs.dec
diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc
new file mode 100644
index 0000000..d0e17cb
--- /dev/null
+++ b/Platform/NXP/FVRules.fdf.inc
@@ -0,0 +1,99 @@
+# FvRules.fdf.inc
+#
+# Rules for creating FD.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
new file mode 100644
index 0000000..1b639e2
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
@@ -0,0 +1,29 @@
+# LS1043aRdbPkg.dec
+# LS1043a board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ PACKAGE_NAME = LS1043aRdbPkg
+ PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
new file mode 100644
index 0000000..6e9e7e0
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -0,0 +1,84 @@
+# LS1043aRdbPkg.dsc
+#
+# LS1043ARDB Board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_NAME = LS1043aRdbPkg
+ PLATFORM_GUID = 60169ec4-d2b4-44f8-825e-f8684fd42e4f
+ OUTPUT_DIRECTORY = Build/LS1043aRdbPkg
+ FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+
+!include ../NxpQoriqLs.dsc
+!include ../../../Silicon/NXP/LS1043A/LS1043A.dsc
+
+[LibraryClasses.common]
+ ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+ BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf
+ SocLib|Silicon/NXP/Chassis/LS1043aSocLib.inf
+ RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
+
+[PcdsFixedAtBuild.common]
+
+ #
+ # LS1043a board Specific PCDs
+ # XX (DRAM - Region 1 2GB)
+ # (NOR - IFC Region 1 512MB)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
+ #
+ # Board Specific Pcds
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
+
+ #
+ # I2C controller Pcds
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0
+
+ #
+ # RTC Pcds
+ #
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # Architectural Protocols
+ #
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+
+ Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
+ Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+
+ ##
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
new file mode 100644
index 0000000..fa6510c
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -0,0 +1,197 @@
+# LS1043aRdbPkg.fdf
+#
+# FLASH layout file for LS1043a board.
+#
+# Copyright (c) 2016, Freescale Ltd. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LS1043ARDB_EFI]
+BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
+Size = 0x000EC890|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xEC890
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x000EC890
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+!include ../FVRules.fdf.inc
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize = 0x1
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+
+ INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ #
+ # Network modules
+ #
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+ INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+ INF NetworkPkg/TcpDxe/TcpDxe.inf
+ INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+ INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+ INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+ INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+!endif
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/FatPei/FatPei.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc
new file mode 100644
index 0000000..5987cd6
--- /dev/null
+++ b/Platform/NXP/NxpQoriqLs.dsc
@@ -0,0 +1,412 @@
+# @file
+#
+# Copyright 2017 NXP.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+
+[LibraryClasses.common]
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+ ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+ BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+ PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+ # Networking Requirements
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+ # ARM GIC400 General Interrupt Driver
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+ SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.common.SEC]
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+ LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+ MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+
+ # 1/123 faster than Stm or Vstm version
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+ # Uncomment to turn on GDB stub in SEC.
+ #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+
+[LibraryClasses.common.PEIM]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.AARCH64]
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[BuildOptions]
+ XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7
+ GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a
+ RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu cortex-a9
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
+ GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+ # It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+ gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+[PcdsDynamicDefault.common]
+ #
+ # Set video resolution for boot options and for text setup.
+ # PlatformDxe can set the former at runtime.
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
+
+[PcdsDynamicHii.common.DEFAULT]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
+
+[PcdsFixedAtBuild.common]
+ gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|1 # Only one core
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|2000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000000
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000044
+!endif
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ #
+ # Optional feature to help prevent EFI memory map fragments
+ # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+ # Values are in EFI Pages (4K). DXE Core will make sure that
+ # at least this much of each type of memory can be allocated
+ # from a single memory range. This way you only end up with
+ # maximum of two fragements for each type in the memory map
+ # (the memory used, and the free memory that was prereserved
+ # but not used).
+ #
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ # Serial Terminal
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+ # Size of the region reserved for fixed address allocations (Reserved 32MB)
+ gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x08000000
+ gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x0
+ gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x94A00000
+ gArmTokenSpaceGuid.PcdCpuResetAddress|0x94A00000
+
+ # Timer
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
+
+ # We want to use the Shell Libraries but don't want it to initialise
+ # automatically. We initialise the libraries when the command is called by the
+ # Shell.
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+
+ # Use the serial console for both ConIn & ConOut
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000
+!ifdef $(NO_SHELL_PROFILES)
+ gEfiShellPkgTokenSpaceGuid.PcdShellProfileMask|0x00
+!endif #$(NO_SHELL_PROFILES)
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # SEC
+ #
+ ArmPlatformPkg/PrePi/PeiUniCore.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+ # FDT installation
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ #
+ # Networking stack
+ #
+ MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+ NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+ NetworkPkg/TcpDxe/TcpDxe.inf
+ NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+ NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+ NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+ NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+!endif
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ FatPkg/FatPei/FatPei.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Example Application
+ #
+ MdeModulePkg/Application/HelloWorld/HelloWorld.inf
+ ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+!ifndef $(NO_SHELL_PROFILES)
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+!endif #$(NO_SHELL_PROFILES)
+ }
+
+ ##
diff --git a/Silicon/NXP/LS1043A/LS1043A.dec b/Silicon/NXP/LS1043A/LS1043A.dec
new file mode 100644
index 0000000..f14edb2
--- /dev/null
+++ b/Silicon/NXP/LS1043A/LS1043A.dec
@@ -0,0 +1,22 @@
+# LS1043A.dec
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+
+[Guids.common]
+ gNxpLs1043ATokenSpaceGuid = {0x6834fe45, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
+
+[Includes]
+ Include
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc b/Silicon/NXP/LS1043A/LS1043A.dsc
new file mode 100644
index 0000000..8395dfd
--- /dev/null
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc
@@ -0,0 +1,73 @@
+# LS1043A.dsc
+# LS1043A Soc package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsDynamicDefault.common]
+
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
+
+[PcdsFixedAtBuild.common]
+
+ #
+ # CCSR Address Space and other attached Memories
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
+ gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000
+ gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
+
+ #
+ # Big Endian IPs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
+
+##
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
new file mode 100644
index 0000000..a73e9d5
--- /dev/null
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -0,0 +1,117 @@
+# @file.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_VERSION = 0.1
+
+[Includes]
+ .
+ Include
+
+[Guids.common]
+ gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
+
+[PcdsFixedAtBuild.common]
+ #
+ # Pcds for I2C Controller
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0|UINT32|0x00000001
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000002
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000003
+
+ #
+ # Pcds for base address and size
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
+ gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
+ gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
+ gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x0|UINT64|0x00000104
+ gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
+ gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
+ gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
+ gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
+ gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
+ gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0|UINT64|0x0000011A
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0|UINT64|0x0000011B
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0|UINT64|0x0000011C
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0|UINT64|0x0000011D
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x0|UINT64|0x0000011E
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x0|UINT64|0x0000011F
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x00000120
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x00000121
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x00000122
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x00000123
+ gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x00000124
+ gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x00000125
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000126
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000127
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000128
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129
+ gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A
+
+ #
+ # IFC PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
+
+ #
+ # NV Pcd
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
+ gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211
+
+ #
+ # Platform PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
+
+ #
+ # Clock PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
+ gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1
+
+ #
+ # Pcds to support Big Endian IPs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
+ gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
+ gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|FALSE|BOOLEAN|0x00000313
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 09/39] Build : Add build script and environment script
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (7 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 08/39] Compilation : Add the fdf, dsc and dec files Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-02-21 16:02 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 10/39] IFC : Add Header file for IFC controller Meenakshi
` (32 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Build script and Environment setup script.
Readme to explain how to run build script
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Platform/NXP/Env.cshrc | 78 +++++++++++++++++++++++++++++++++
Platform/NXP/Readme.md | 17 +++++++
Platform/NXP/build.sh | 117 +++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 212 insertions(+)
create mode 100755 Platform/NXP/Env.cshrc
create mode 100644 Platform/NXP/Readme.md
create mode 100755 Platform/NXP/build.sh
diff --git a/Platform/NXP/Env.cshrc b/Platform/NXP/Env.cshrc
new file mode 100755
index 0000000..eb51018
--- /dev/null
+++ b/Platform/NXP/Env.cshrc
@@ -0,0 +1,78 @@
+# @file.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion
+
+if [ X"$CROSS_COMPILE_64" != X"" ]; then
+ ARM64_PREFIX="$CROSS_COMPILE_64"
+elif [ X"$CROSS_COMPILE" != X"" ]; then
+ ARM64_PREFIX="$CROSS_COMPILE"
+else
+ ARM64_PREFIX="aarch64-linux-gnu-"
+fi
+
+GCC_UTILITY="${ARM64_PREFIX}gcc"
+CheckGcc=`which $GCC_UTILITY >/dev/null 2>&1`
+if [ "$?" -eq 0 ];then
+ GCC_VERSION=`$GCC_UTILITY -v 2>&1 | tail -n 1 | awk '{print $3}'`
+ MajorVersion=`echo $GCC_VERSION | cut -d . -f 1`
+ MinorVersion=`echo $GCC_VERSION | cut -d . -f 2`
+ GCC_ARCH_PREFIX=
+ NOTSUPPORTED=0
+
+ case $MajorVersion in
+ 4)
+ case $MinorVersion in
+ 9)
+ GCC_ARCH_PREFIX="GCC49_AARCH64_PREFIX"
+ ;;
+ *)
+ NOTSUPPORTED=1
+ ;;
+ esac
+ ;;
+ 5)
+ case $MinorVersion in
+ 4)
+ GCC_ARCH_PREFIX="GCC5_AARCH64_PREFIX"
+ ;;
+ *)
+ GCC_ARCH_PREFIX="GCC5_AARCH64_PREFIX"
+ echo "Warning: ${GCC_UTILITY} version ($MajorVersion.$MinorVersion) has not been tested, please use at own risk."
+ ;;
+ esac
+ ;;
+ *)
+ NOTSUPPORTED=1
+ ;;
+ esac
+
+ [ "$NOTSUPPORTED" -eq 1 ] && {
+ echo "Error: ${GCC_UTILITY} version ($MajorVersion.$MinorVersion) not supported ."
+ unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion
+ }
+
+ [ -n "$GCC_ARCH_PREFIX" ] && {
+ export GCC_ARCH_PREFIX="$GCC_ARCH_PREFIX"
+ export "$GCC_ARCH_PREFIX=$ARM64_PREFIX"
+ }
+
+ unset ARCH
+else
+ echo "Error: ${GCC_UTILITY} not found. Please check PATH variable."
+ unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion
+fi
+
+# Export the edk2-platforms path
+export PACKAGES_PATH=`dirname \`dirname "$PWD"\``
diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md
new file mode 100644
index 0000000..94174a7
--- /dev/null
+++ b/Platform/NXP/Readme.md
@@ -0,0 +1,17 @@
+Support for all NXP boards is available in this directory.
+
+# How to build
+
+build script source environment file Env.cshrc
+
+user need to run only build command.
+
+1. source Env.cshrc
+
+2. Build desired board
+ ./build.sh <SoC-name> <board-type> <build-candidate> <clean> (optional)
+
+ Soc-name : LS1043 / LS1046 / LS2088
+ board-type : RDB / QDS
+ build-candidate : DEBUG / RELEASE
+
diff --git a/Platform/NXP/build.sh b/Platform/NXP/build.sh
new file mode 100755
index 0000000..eea83ee
--- /dev/null
+++ b/Platform/NXP/build.sh
@@ -0,0 +1,117 @@
+#!/bin/bash
+
+# UEFI build script for NXP LS SoCs
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+# source environment file
+source Env.cshrc
+
+# Global Defaults
+ARCH=AARCH64
+TARGET_TOOLS=`echo $GCC_ARCH_PREFIX | cut -d _ -f 1`
+BASE_DIR=../../..
+
+[ -z "$TARGET_TOOLS" ] && {
+ echo "TARGET_TOOLS not found. Please run \"source Env.cshrc\" ."
+ exit 1
+}
+
+print_usage_banner()
+{
+ echo ""
+ echo "This shell script expects:"
+ echo " Arg 1 (mandatory): SoC Type (can be LS1043 / LS1046 / LS2088)."
+ echo " Arg 2 (mandatory): Board Type (can be RDB / QDS)."
+ echo " Arg 3 (mandatory): Build candidate (can be RELEASE or DEBUG). By
+ default we build the RELEASE candidate."
+ echo " Arg 4 (optional): clean - To do a 'make clean' operation."
+}
+
+# Check for total num of input arguments
+if [[ "$#" -gt 4 ]]; then
+ echo "Illegal number of parameters"
+ print_usage_banner
+ exit
+fi
+
+# Check for third parameter to be clean only
+if [[ "$4" && $4 != "clean" ]]; then
+ echo "Error ! Either clean or emplty"
+ print_usage_banner
+ exit
+fi
+
+# Check for input arguments
+if [[ $1 == "" || $2 == "" || $3 == "" ]]; then
+ echo "Error !"
+ print_usage_banner
+ exit
+fi
+
+# Check for input arguments
+if [[ $1 != "LS1043" && $1 != "LS1046" && $1 != "LS2088" ]]; then
+ echo "Error ! Incorrect Soc Type specified."
+ print_usage_banner
+ exit
+fi
+
+# Check for input arguments
+if [[ $2 != "RDB" && $2 != "QDS" ]]; then
+ echo "Error ! Incorrect Board Type specified."
+ print_usage_banner
+ exit
+fi
+
+# Check for input arguments
+if [[ $3 != "RELEASE" ]]; then
+ if [[ $3 != "DEBUG" ]]; then
+ echo "Error ! Incorrect build target specified."
+ print_usage_banner
+ exit
+ fi
+fi
+
+# Set Package drirectory
+if [[ $2 == "RDB" ]]; then
+ PKG="aRdbPkg"
+ if [[ $2 == "QDS" ]]; then
+ PKG="aQdsPkg"
+ fi
+fi
+
+echo ".........................................."
+echo "Welcome to $1$PKG UEFI Build environment"
+echo ".........................................."
+
+if [[ $4 == "clean" ]]; then
+ echo "Cleaning up the build directory '$BASE_DIR/Build/$1$PKG/'.."
+ rm -rf $BASE_DIR/Build/$1$PKG/*
+ exit
+fi
+
+# Clean-up
+set -e
+shopt -s nocasematch
+
+#
+# Setup workspace now
+#
+echo Initializing workspace
+cd $BASE_DIR
+
+# Use the BaseTools in edk2
+export EDK_TOOLS_PATH=`pwd`/BaseTools
+source edksetup.sh BaseTools
+
+
+build -p "$PACKAGES_PATH/Platform/NXP/$1$PKG/$1$PKG.dsc" -a $ARCH -t $TARGET_TOOLS -b $3
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 10/39] IFC : Add Header file for IFC controller
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (8 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 09/39] Build : Add build script and environment script Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-18 18:31 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 11/39] LS1043/BoardLib : Add support for LS1043 BoardLib Meenakshi
` (31 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
This header file contain IFC controller timing structure,
chip select enum and other IFC macros.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Include/Ifc.h | 420 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 420 insertions(+)
create mode 100644 Silicon/NXP/Include/Ifc.h
diff --git a/Silicon/NXP/Include/Ifc.h b/Silicon/NXP/Include/Ifc.h
new file mode 100644
index 0000000..0bb7230
--- /dev/null
+++ b/Silicon/NXP/Include/Ifc.h
@@ -0,0 +1,420 @@
+/** @Ifc.h
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __IFC_H__
+#define __IFC_H__
+
+#include <Library/BaseLib.h>
+#include <Uefi.h>
+
+#define IFC_BANK_COUNT 4
+
+#define IFC_CSPR_REG_LEN 148
+#define IFC_AMASK_REG_LEN 144
+#define IFC_CSOR_REG_LEN 144
+#define IFC_FTIM_REG_LEN 576
+
+#define IFC_CSPR_USED_LEN sizeof (IFC_CSPR) * \
+ IFC_BANK_COUNT
+
+#define IFC_AMASK_USED_LEN sizeof (IFC_AMASK) * \
+ IFC_BANK_COUNT
+
+#define IFC_CSOR_USED_LEN sizeof (IFC_CSOR) * \
+ IFC_BANK_COUNT
+
+#define IFC_FTIM_USED_LEN sizeof (IFC_FTIM) * \
+ IFC_BANK_COUNT
+
+/* List of commands */
+#define IFC_NAND_CMD_RESET 0xFF
+#define IFC_NAND_CMD_READID 0x90
+#define IFC_NAND_CMD_STATUS 0x70
+#define IFC_NAND_CMD_READ0 0x00
+#define IFC_NAND_CMD_READSTART 0x30
+#define IFC_NAND_CMD_ERASE1 0x60
+#define IFC_NAND_CMD_ERASE2 0xD0
+#define IFC_NAND_CMD_SEQIN 0x80
+#define IFC_NAND_CMD_PAGEPROG 0x10
+#define MAX_RETRY_COUNT 150000
+
+
+#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
+
+/*
+ * NAND Event and Error Status Register (NAND_EVTER_STAT)
+ */
+
+/* Operation Complete */
+#define IFC_NAND_EVTER_STAT_OPC 0x80000000
+
+/* Flash Timeout Error */
+#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
+
+/* Write Protect Error */
+#define IFC_NAND_EVTER_STAT_WPER 0x04000000
+
+/* ECC Error */
+#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
+
+/*
+ * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
+ */
+
+/* NAND Machine specific opcodes OP0-OP14*/
+#define IFC_NAND_FIR0_OP0 0xFC000000
+#define IFC_NAND_FIR0_OP0_SHIFT 26
+#define IFC_NAND_FIR0_OP1 0x03F00000
+#define IFC_NAND_FIR0_OP1_SHIFT 20
+#define IFC_NAND_FIR0_OP2 0x000FC000
+#define IFC_NAND_FIR0_OP2_SHIFT 14
+#define IFC_NAND_FIR0_OP3 0x00003F00
+#define IFC_NAND_FIR0_OP3_SHIFT 8
+#define IFC_NAND_FIR0_OP4 0x000000FC
+#define IFC_NAND_FIR0_OP4_SHIFT 2
+#define IFC_NAND_FIR1_OP5 0xFC000000
+#define IFC_NAND_FIR1_OP5_SHIFT 26
+#define IFC_NAND_FIR1_OP6 0x03F00000
+#define IFC_NAND_FIR1_OP6_SHIFT 20
+#define IFC_NAND_FIR1_OP7 0x000FC000
+#define IFC_NAND_FIR1_OP7_SHIFT 14
+#define IFC_NAND_FIR1_OP8 0x00003F00
+#define IFC_NAND_FIR1_OP8_SHIFT 8
+#define IFC_NAND_FIR1_OP9 0x000000FC
+#define IFC_NAND_FIR1_OP9_SHIFT 2
+#define IFC_NAND_FIR2_OP10 0xFC000000
+#define IFC_NAND_FIR2_OP10_SHIFT 26
+#define IFC_NAND_FIR2_OP11 0x03F00000
+#define IFC_NAND_FIR2_OP11_SHIFT 20
+#define IFC_NAND_FIR2_OP12 0x000FC000
+#define IFC_NAND_FIR2_OP12_SHIFT 14
+#define IFC_NAND_FIR2_OP13 0x00003F00
+#define IFC_NAND_FIR2_OP13_SHIFT 8
+#define IFC_NAND_FIR2_OP14 0x000000FC
+#define IFC_NAND_FIR2_OP14_SHIFT 2
+
+/*
+ * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
+ */
+
+/* General purpose FCM flash command bytes CMD0-CMD7 */
+#define IFC_NAND_FCR0_CMD0 0xFF000000
+#define IFC_NAND_FCR0_CMD0_SHIFT 24
+#define IFC_NAND_FCR0_CMD1 0x00FF0000
+#define IFC_NAND_FCR0_CMD1_SHIFT 16
+#define IFC_NAND_FCR0_CMD2 0x0000FF00
+#define IFC_NAND_FCR0_CMD2_SHIFT 8
+#define IFC_NAND_FCR0_CMD3 0x000000FF
+#define IFC_NAND_FCR0_CMD3_SHIFT 0
+#define IFC_NAND_FCR1_CMD4 0xFF000000
+#define IFC_NAND_FCR1_CMD4_SHIFT 24
+#define IFC_NAND_FCR1_CMD5 0x00FF0000
+#define IFC_NAND_FCR1_CMD5_SHIFT 16
+#define IFC_NAND_FCR1_CMD6 0x0000FF00
+#define IFC_NAND_FCR1_CMD6_SHIFT 8
+#define IFC_NAND_FCR1_CMD7 0x000000FF
+#define IFC_NAND_FCR1_CMD7_SHIFT 0
+
+/* Timing registers for NAND Flash */
+
+#define IFC_FTIM0_NAND_TCCST_SHIFT 25
+#define IFC_FTIM0_NAND_TCCST(n) ((n) << IFC_FTIM0_NAND_TCCST_SHIFT)
+#define IFC_FTIM0_NAND_TWP_SHIFT 16
+#define IFC_FTIM0_NAND_TWP(n) ((n) << IFC_FTIM0_NAND_TWP_SHIFT)
+#define IFC_FTIM0_NAND_TWCHT_SHIFT 8
+#define IFC_FTIM0_NAND_TWCHT(n) ((n) << IFC_FTIM0_NAND_TWCHT_SHIFT)
+#define IFC_FTIM0_NAND_TWH_SHIFT 0
+#define IFC_FTIM0_NAND_TWH(n) ((n) << IFC_FTIM0_NAND_TWH_SHIFT)
+#define IFC_FTIM1_NAND_TADLE_SHIFT 24
+#define IFC_FTIM1_NAND_TADLE(n) ((n) << IFC_FTIM1_NAND_TADLE_SHIFT)
+#define IFC_FTIM1_NAND_TWBE_SHIFT 16
+#define IFC_FTIM1_NAND_TWBE(n) ((n) << IFC_FTIM1_NAND_TWBE_SHIFT)
+#define IFC_FTIM1_NAND_TRR_SHIFT 8
+#define IFC_FTIM1_NAND_TRR(n) ((n) << IFC_FTIM1_NAND_TRR_SHIFT)
+#define IFC_FTIM1_NAND_TRP_SHIFT 0
+#define IFC_FTIM1_NAND_TRP(n) ((n) << IFC_FTIM1_NAND_TRP_SHIFT)
+#define IFC_FTIM2_NAND_TRAD_SHIFT 21
+#define IFC_FTIM2_NAND_TRAD(n) ((n) << IFC_FTIM2_NAND_TRAD_SHIFT)
+#define IFC_FTIM2_NAND_TREH_SHIFT 11
+#define IFC_FTIM2_NAND_TREH(n) ((n) << IFC_FTIM2_NAND_TREH_SHIFT)
+#define IFC_FTIM2_NAND_TWHRE_SHIFT 0
+#define IFC_FTIM2_NAND_TWHRE(n) ((n) << IFC_FTIM2_NAND_TWHRE_SHIFT)
+#define IFC_FTIM3_NAND_TWW_SHIFT 24
+#define IFC_FTIM3_NAND_TWW(n) ((n) << IFC_FTIM3_NAND_TWW_SHIFT)
+
+/*
+ * Flash ROW and COL Address Register (ROWn, COLn)
+ */
+
+/* Main/spare region locator */
+#define IFC_NAND_COL_MS 0x80000000
+
+/* Column Address */
+#define IFC_NAND_COL_CA_MASK 0x00000FFF
+
+#define NAND_STATUS_WP 0x80
+
+/*
+ * NAND Event and Error Enable Register (NAND_EVTER_EN)
+ */
+
+/* Operation complete event enable */
+#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
+
+/* Page read complete event enable */
+#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
+
+/* Flash Timeout error enable */
+#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
+
+/* Write Protect error enable */
+#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
+
+/* ECC error logging enable */
+#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
+
+/*
+ * CSPR - Chip Select Property Register
+ */
+
+#define IFC_CSPR_BA 0xFFFF0000
+#define IFC_CSPR_BA_SHIFT 16
+#define IFC_CSPR_PORT_SIZE 0x00000180
+#define IFC_CSPR_PORT_SIZE_SHIFT 7
+
+// Port Size 8 bit
+#define IFC_CSPR_PORT_SIZE_8 0x00000080
+
+// Port Size 16 bit
+#define IFC_CSPR_PORT_SIZE_16 0x00000100
+
+// Port Size 32 bit
+#define IFC_CSPR_PORT_SIZE_32 0x00000180
+
+// Write Protect
+#define IFC_CSPR_WP 0x00000040
+#define IFC_CSPR_WP_SHIFT 6
+
+// Machine Select
+#define IFC_CSPR_MSEL 0x00000006
+#define IFC_CSPR_MSEL_SHIFT 1
+
+// NOR
+#define IFC_CSPR_MSEL_NOR 0x00000000
+
+/* NAND */
+#define IFC_CSPR_MSEL_NAND 0x00000002
+
+/* GPCM */
+#define IFC_CSPR_MSEL_GPCM 0x00000004
+
+// Bank Valid
+#define IFC_CSPR_V 0x00000001
+#define IFC_CSPR_V_SHIFT 0
+
+/*
+ * Chip Select Option Register - NOR Flash Mode
+ */
+
+// Enable Address shift Mode
+#define IFC_CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
+
+// Page Read Enable from NOR device
+#define IFC_CSOR_NOR_PGRD_EN 0x10000000
+
+// AVD Toggle Enable during Burst Program
+#define IFC_CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
+
+// Address Data Multiplexing Shift
+#define IFC_CSOR_NOR_ADM_MASK 0x0003E000
+#define IFC_CSOR_NOR_ADM_SHIFT_SHIFT 13
+#define IFC_CSOR_NOR_ADM_SHIFT(n) ((n) << IFC_CSOR_NOR_ADM_SHIFT_SHIFT)
+
+// Type of the NOR device hooked
+#define IFC_CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
+#define IFC_CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
+
+// Time for Read Enable High to Output High Impedance
+#define IFC_CSOR_NOR_TRHZ_MASK 0x0000001C
+#define IFC_CSOR_NOR_TRHZ_SHIFT 2
+#define IFC_CSOR_NOR_TRHZ_20 0x00000000
+#define IFC_CSOR_NOR_TRHZ_40 0x00000004
+#define IFC_CSOR_NOR_TRHZ_60 0x00000008
+#define IFC_CSOR_NOR_TRHZ_80 0x0000000C
+#define IFC_CSOR_NOR_TRHZ_100 0x00000010
+
+// Buffer control disable
+#define IFC_CSOR_NOR_BCTLD 0x00000001
+
+/*
+ * Chip Select Option Register IFC_NAND Machine
+ */
+
+/* Enable ECC Encoder */
+#define IFC_CSOR_NAND_ECC_ENC_EN 0x80000000
+#define IFC_CSOR_NAND_ECC_MODE_MASK 0x30000000
+
+/* 4 bit correction per 520 Byte sector */
+#define IFC_CSOR_NAND_ECC_MODE_4 0x00000000
+
+/* 8 bit correction per 528 Byte sector */
+#define IFC_CSOR_NAND_ECC_MODE_8 0x10000000
+
+/* Enable ECC Decoder */
+#define IFC_CSOR_NAND_ECC_DEC_EN 0x04000000
+
+/* Row Address Length */
+#define IFC_CSOR_NAND_RAL_MASK 0x01800000
+#define IFC_CSOR_NAND_RAL_SHIFT 20
+#define IFC_CSOR_NAND_RAL_1 0x00000000
+#define IFC_CSOR_NAND_RAL_2 0x00800000
+#define IFC_CSOR_NAND_RAL_3 0x01000000
+#define IFC_CSOR_NAND_RAL_4 0x01800000
+
+/* Page Size 512b, 2k, 4k */
+#define IFC_CSOR_NAND_PGS_MASK 0x00180000
+#define IFC_CSOR_NAND_PGS_SHIFT 16
+#define IFC_CSOR_NAND_PGS_512 0x00000000
+#define IFC_CSOR_NAND_PGS_2K 0x00080000
+#define IFC_CSOR_NAND_PGS_4K 0x00100000
+#define IFC_CSOR_NAND_PGS_8K 0x00180000
+
+/* Spare region Size */
+#define IFC_CSOR_NAND_SPRZ_MASK 0x0000E000
+#define IFC_CSOR_NAND_SPRZ_SHIFT 13
+#define IFC_CSOR_NAND_SPRZ_16 0x00000000
+#define IFC_CSOR_NAND_SPRZ_64 0x00002000
+#define IFC_CSOR_NAND_SPRZ_128 0x00004000
+#define IFC_CSOR_NAND_SPRZ_210 0x00006000
+#define IFC_CSOR_NAND_SPRZ_218 0x00008000
+#define IFC_CSOR_NAND_SPRZ_224 0x0000A000
+#define IFC_CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
+
+/* Pages Per Block */
+#define IFC_CSOR_NAND_PB_MASK 0x00000700
+#define IFC_CSOR_NAND_PB_SHIFT 8
+#define IFC_CSOR_NAND_PB(n) (n-5) << IFC_CSOR_NAND_PB_SHIFT
+
+/* Time for Read Enable High to Output High Impedance */
+#define IFC_CSOR_NAND_TRHZ_MASK 0x0000001C
+#define IFC_CSOR_NAND_TRHZ_SHIFT 2
+#define IFC_CSOR_NAND_TRHZ_20 0x00000000
+#define IFC_CSOR_NAND_TRHZ_40 0x00000004
+#define IFC_CSOR_NAND_TRHZ_60 0x00000008
+#define IFC_CSOR_NAND_TRHZ_80 0x0000000C
+#define IFC_CSOR_NAND_TRHZ_100 0x00000010
+
+/*
+ * FTIM0 - NOR Flash Mode
+ */
+#define IFC_FTIM0_NOR 0xF03F3F3F
+#define IFC_FTIM0_NOR_TACSE_SHIFT 28
+#define IFC_FTIM0_NOR_TACSE(n) ((n) << IFC_FTIM0_NOR_TACSE_SHIFT)
+#define IFC_FTIM0_NOR_TEADC_SHIFT 16
+#define IFC_FTIM0_NOR_TEADC(n) ((n) << IFC_FTIM0_NOR_TEADC_SHIFT)
+#define IFC_FTIM0_NOR_TAVDS_SHIFT 8
+#define IFC_FTIM0_NOR_TAVDS(n) ((n) << IFC_FTIM0_NOR_TAVDS_SHIFT)
+#define IFC_FTIM0_NOR_TEAHC_SHIFT 0
+#define IFC_FTIM0_NOR_TEAHC(n) ((n) << IFC_FTIM0_NOR_TEAHC_SHIFT)
+
+/*
+ * FTIM1 - NOR Flash Mode
+ */
+#define IFC_FTIM1_NOR 0xFF003F3F
+#define IFC_FTIM1_NOR_TACO_SHIFT 24
+#define IFC_FTIM1_NOR_TACO(n) ((n) << IFC_FTIM1_NOR_TACO_SHIFT)
+#define IFC_FTIM1_NOR_TRAD_NOR_SHIFT 8
+#define IFC_FTIM1_NOR_TRAD_NOR(n) ((n) << IFC_FTIM1_NOR_TRAD_NOR_SHIFT)
+#define IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
+#define IFC_FTIM1_NOR_TSEQRAD_NOR(n) ((n) << IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT)
+
+/*
+ * FTIM2 - NOR Flash Mode
+ */
+#define IFC_FTIM2_NOR 0x0F3CFCFF
+#define IFC_FTIM2_NOR_TCS_SHIFT 24
+#define IFC_FTIM2_NOR_TCS(n) ((n) << IFC_FTIM2_NOR_TCS_SHIFT)
+#define IFC_FTIM2_NOR_TCH_SHIFT 18
+#define IFC_FTIM2_NOR_TCH(n) ((n) << IFC_FTIM2_NOR_TCH_SHIFT)
+#define IFC_FTIM2_NOR_TWPH_SHIFT 10
+#define IFC_FTIM2_NOR_TWPH(n) ((n) << IFC_FTIM2_NOR_TWPH_SHIFT)
+#define IFC_FTIM2_NOR_TWP_SHIFT 0
+#define IFC_FTIM2_NOR_TWP(n) ((n) << IFC_FTIM2_NOR_TWP_SHIFT)
+
+/*
+ * FTIM0 - Normal GPCM Mode
+ */
+#define IFC_FTIM0_GPCM 0xF03F3F3F
+#define IFC_FTIM0_GPCM_TACSE_SHIFT 28
+#define IFC_FTIM0_GPCM_TACSE(n) ((n) << IFC_FTIM0_GPCM_TACSE_SHIFT)
+#define IFC_FTIM0_GPCM_TEADC_SHIFT 16
+#define IFC_FTIM0_GPCM_TEADC(n) ((n) << IFC_FTIM0_GPCM_TEADC_SHIFT)
+#define IFC_FTIM0_GPCM_TAVDS_SHIFT 8
+#define IFC_FTIM0_GPCM_TAVDS(n) ((n) << IFC_FTIM0_GPCM_TAVDS_SHIFT)
+#define IFC_FTIM0_GPCM_TEAHC_SHIFT 0
+#define IFC_FTIM0_GPCM_TEAHC(n) ((n) << IFC_FTIM0_GPCM_TEAHC_SHIFT)
+
+/*
+ * FTIM1 - Normal GPCM Mode
+ */
+#define IFC_FTIM1_GPCM 0xFF003F00
+#define IFC_FTIM1_GPCM_TACO_SHIFT 24
+#define IFC_FTIM1_GPCM_TACO(n) ((n) << IFC_FTIM1_GPCM_TACO_SHIFT)
+#define IFC_FTIM1_GPCM_TRAD_SHIFT 8
+#define IFC_FTIM1_GPCM_TRAD(n) ((n) << IFC_FTIM1_GPCM_TRAD_SHIFT)
+
+/*
+ * FTIM2 - Normal GPCM Mode
+ */
+#define IFC_FTIM2_GPCM 0x0F3C00FF
+#define IFC_FTIM2_GPCM_TCS_SHIFT 24
+#define IFC_FTIM2_GPCM_TCS(n) ((n) << IFC_FTIM2_GPCM_TCS_SHIFT)
+#define IFC_FTIM2_GPCM_TCH_SHIFT 18
+#define IFC_FTIM2_GPCM_TCH(n) ((n) << IFC_FTIM2_GPCM_TCH_SHIFT)
+#define IFC_FTIM2_GPCM_TWP_SHIFT 0
+#define IFC_FTIM2_GPCM_TWP(n) ((n) << IFC_FTIM2_GPCM_TWP_SHIFT)
+
+/* Convert an address into the right format for the CSPR Registers */
+#define IFC_CSPR_PHYS_ADDR(x) (((UINTN)x) & 0xffff0000)
+
+/*
+ * Address Mask Register
+ */
+#define IFC_AMASK_MASK 0xFFFF0000
+#define IFC_AMASK_SHIFT 16
+#define IFC_AMASK(n) (IFC_AMASK_MASK << \
+ (HighBitSet32(n) - IFC_AMASK_SHIFT))
+
+typedef enum {
+ IFC_CS0 = 0,
+ IFC_CS1,
+ IFC_CS2,
+ IFC_CS3,
+ IFC_CS4,
+ IFC_CS5,
+ IFC_CS6,
+ IFC_CS7,
+ IFC_CS_MAX,
+} IFC_CHIP_SEL;
+
+typedef struct {
+ UINT32 Ftim[IFC_BANK_COUNT];
+ UINT32 CsprExt;
+ UINT32 Cspr;
+ UINT32 Csor;
+ UINT32 Amask;
+ UINT8 CS;
+} IFC_TIMINGS;
+
+#endif //__IFC_H__
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 11/39] LS1043/BoardLib : Add support for LS1043 BoardLib.
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (9 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 10/39] IFC : Add Header file for IFC controller Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-18 18:34 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 12/39] Silicon/NXP : Add support of IfcLib Meenakshi
` (30 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
BoardLib will contain functions specific for LS1043aRdb board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h | 109 +++++++++++++++++++++
.../NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c | 69 +++++++++++++
.../LS1043aRdbPkg/Library/BoardLib/BoardLib.inf | 31 ++++++
3 files changed, 209 insertions(+)
create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h b/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
new file mode 100644
index 0000000..261867a
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
@@ -0,0 +1,109 @@
+/** IfcBoardSpecificLib.h
+
+ IFC Flash Board Specific Macros and structure
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __IFC__BOARD_SPECIFIC_H__
+#define __IFC__BOARD_SPECIFIC_H__
+
+#include <Ifc.h>
+
+// On board flash support
+#define IFC_NAND_BUF_BASE 0x7E800000
+
+// On board Inegrated flash Controller chip select configuration
+#define IFC_NOR_CS IFC_CS0
+#define IFC_NAND_CS IFC_CS1
+#define IFC_FPGA_CS IFC_CS2
+
+// board-specific NAND timing
+#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x7) | \
+ IFC_FTIM0_NAND_TWP(0x18) | \
+ IFC_FTIM0_NAND_TWCHT(0x7) | \
+ IFC_FTIM0_NAND_TWH(0xa))
+
+#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x32) | \
+ IFC_FTIM1_NAND_TWBE(0x39) | \
+ IFC_FTIM1_NAND_TRR(0xe) | \
+ IFC_FTIM1_NAND_TRP(0x18))
+
+#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0xf) | \
+ IFC_FTIM2_NAND_TREH(0xa) | \
+ IFC_FTIM2_NAND_TWHRE(0x1e))
+
+#define NAND_FTIM3 0x0
+
+#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BUF_BASE) \
+ | IFC_CSPR_PORT_SIZE_8 \
+ | IFC_CSPR_MSEL_NAND \
+ | IFC_CSPR_V)
+
+#define NAND_CSPR_EXT 0x0
+#define NAND_AMASK 0xFFFF0000
+
+#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | IFC_CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | IFC_CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | IFC_CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | IFC_CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
+ | IFC_CSOR_NAND_PB(6)) /* 2^6 Pages Per Block */
+
+// board-specific NOR timing
+#define NOR_FTIM0 (IFC_FTIM0_NOR_TACSE(0x1) | \
+ IFC_FTIM0_NOR_TEADC(0x1) | \
+ IFC_FTIM0_NOR_TAVDS(0x0) | \
+ IFC_FTIM0_NOR_TEAHC(0xc))
+#define NOR_FTIM1 (IFC_FTIM1_NOR_TACO(0x1c) | \
+ IFC_FTIM1_NOR_TRAD_NOR(0xb) |\
+ IFC_FTIM1_NOR_TSEQRAD_NOR(0x9))
+#define NOR_FTIM2 (IFC_FTIM2_NOR_TCS(0x1) | \
+ IFC_FTIM2_NOR_TCH(0x4) | \
+ IFC_FTIM2_NOR_TWPH(0x8) | \
+ IFC_FTIM2_NOR_TWP(0x10))
+#define NOR_FTIM3 0x0
+
+#define NOR_CSPR (IFC_CSPR_PHYS_ADDR(FixedPcdGet64 (PcdIfcRegion1BaseAddr)) \
+ | IFC_CSPR_PORT_SIZE_16 \
+ | IFC_CSPR_MSEL_NOR \
+ | IFC_CSPR_V)
+
+#define NOR_CSPR_EXT 0x0
+#define NOR_AMASK IFC_AMASK(128*1024*1024)
+#define NOR_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) | \
+ IFC_CSOR_NOR_TRHZ_80)
+
+// board-specific fpga timing
+#define FPGA_BASE_PHYS 0x7fb00000
+#define FPGA_CSPR_EXT 0x0
+#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
+ IFC_CSPR_PORT_SIZE_8 | \
+ IFC_CSPR_MSEL_GPCM | \
+ IFC_CSPR_V)
+
+#define FPGA_AMASK IFC_AMASK(64 * 1024)
+#define FPGA_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) | \
+ IFC_CSOR_NOR_NOR_MODE_AVD_NOR | \
+ IFC_CSOR_NOR_TRHZ_80)
+
+#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0xf) | \
+ IFC_FTIM0_GPCM_TEADC(0xf) | \
+ IFC_FTIM0_GPCM_TEAHC(0xf))
+#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \
+ IFC_FTIM1_GPCM_TRAD(0x3f))
+#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \
+ IFC_FTIM2_GPCM_TCH(0xf) | \
+ IFC_FTIM2_GPCM_TWP(0xff))
+#define FPGA_FTIM3 0x0
+
+#endif //__IFC__BOARD_SPECIFIC_H__
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
new file mode 100644
index 0000000..a101a8d
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
@@ -0,0 +1,69 @@
+/** @file
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IfcBoardSpecific.h>
+
+VOID
+GetIfcNorFlashTimings (
+ IN IFC_TIMINGS * NorIfcTimings
+ )
+{
+ NorIfcTimings->Ftim[0] = NOR_FTIM0;
+ NorIfcTimings->Ftim[1] = NOR_FTIM1;
+ NorIfcTimings->Ftim[2] = NOR_FTIM2;
+ NorIfcTimings->Ftim[3] = NOR_FTIM3;
+ NorIfcTimings->Cspr = NOR_CSPR;
+ NorIfcTimings->CsprExt = NOR_CSPR_EXT;
+ NorIfcTimings->Amask = NOR_AMASK;
+ NorIfcTimings->Csor = NOR_CSOR;
+ NorIfcTimings->CS = IFC_NOR_CS;
+
+ return ;
+}
+
+VOID
+GetIfcFpgaTimings (
+ IN IFC_TIMINGS *FpgaIfcTimings
+ )
+{
+ FpgaIfcTimings->Ftim[0] = FPGA_FTIM0;
+ FpgaIfcTimings->Ftim[1] = FPGA_FTIM1;
+ FpgaIfcTimings->Ftim[2] = FPGA_FTIM2;
+ FpgaIfcTimings->Ftim[3] = FPGA_FTIM3;
+ FpgaIfcTimings->Cspr = FPGA_CSPR;
+ FpgaIfcTimings->CsprExt = FPGA_CSPR_EXT;
+ FpgaIfcTimings->Amask = FPGA_AMASK;
+ FpgaIfcTimings->Csor = FPGA_CSOR;
+ FpgaIfcTimings->CS = IFC_FPGA_CS;
+
+ return;
+}
+
+VOID
+GetIfcNandFlashTimings (
+ IN IFC_TIMINGS * NandIfcTimings
+ )
+{
+ NandIfcTimings->Ftim[0] = NAND_FTIM0;
+ NandIfcTimings->Ftim[1] = NAND_FTIM1;
+ NandIfcTimings->Ftim[2] = NAND_FTIM2;
+ NandIfcTimings->Ftim[3] = NAND_FTIM3;
+ NandIfcTimings->Cspr = NAND_CSPR;
+ NandIfcTimings->CsprExt = NAND_CSPR_EXT;
+ NandIfcTimings->Amask = NAND_AMASK;
+ NandIfcTimings->Csor = NAND_CSOR;
+ NandIfcTimings->CS = IFC_NAND_CS;
+
+ return;
+}
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
new file mode 100644
index 0000000..7d2702b
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
@@ -0,0 +1,31 @@
+# @file
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = BoardLib
+ FILE_GUID = 8ecefc8f-a2c4-4091-b80f-92da7c4ab37f
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardLib
+
+[Sources.common]
+ BoardLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[FixedPcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 12/39] Silicon/NXP : Add support of IfcLib
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (10 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 11/39] LS1043/BoardLib : Add support for LS1043 BoardLib Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-18 18:39 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 13/39] LS1043/FpgaLib : Add support for FpgaLib Meenakshi
` (29 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Add support of IfcLib, it will be used to perform
any operation on IFC controller.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Include/Library/IfcLib.h | 23 +++++
Silicon/NXP/Library/IfcLib/IfcLib.c | 155 ++++++++++++++++++++++++++++
Silicon/NXP/Library/IfcLib/IfcLib.h | 184 ++++++++++++++++++++++++++++++++++
Silicon/NXP/Library/IfcLib/IfcLib.inf | 38 +++++++
Silicon/NXP/NxpQoriqLs.dec | 1 +
5 files changed, 401 insertions(+)
create mode 100644 Silicon/NXP/Include/Library/IfcLib.h
create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.c
create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.h
create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.inf
diff --git a/Silicon/NXP/Include/Library/IfcLib.h b/Silicon/NXP/Include/Library/IfcLib.h
new file mode 100644
index 0000000..f350d33
--- /dev/null
+++ b/Silicon/NXP/Include/Library/IfcLib.h
@@ -0,0 +1,23 @@
+/** @IfcLib.h
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __IFC_LIB_H__
+#define __IFC_LIB_H__
+
+VOID
+IfcInit (
+ VOID
+ );
+
+#endif //__IFC_LIB_H__
diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.c b/Silicon/NXP/Library/IfcLib/IfcLib.c
new file mode 100644
index 0000000..97a6591
--- /dev/null
+++ b/Silicon/NXP/Library/IfcLib/IfcLib.c
@@ -0,0 +1,155 @@
+/** @IfcLib.c
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BeIoLib.h>
+#include <Library/IoLib.h>
+#include "IfcLib.h"
+
+UINT8 mNandCS;
+UINT8 mNorCS;
+UINT8 mFpgaCS;
+
+UINT32
+EFIAPI
+IfcWrite (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ if (FixedPcdGetBool(PcdIfcBigEndian)) {
+ return BeMmioWrite32 (Address, Value);
+ } else {
+ return MmioWrite32 (Address, Value);
+ }
+}
+
+VOID
+SetTimings (
+ IN UINT8 CS,
+ IN IFC_TIMINGS IfcTimings
+ )
+{
+ IFC_REGS* IfcRegs;
+
+ IfcRegs = (IFC_REGS*) PcdGet64 (PcdIfcBaseAddr);
+
+ // Configure Extended chip select property registers
+ IfcWrite ((UINTN)&IfcRegs->CsprCs[CS].CsprExt, IfcTimings.CsprExt);
+
+ // Configure Fpga timing registers
+ IfcWrite ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM0], IfcTimings.Ftim[0]);
+ IfcWrite ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM1], IfcTimings.Ftim[1]);
+ IfcWrite ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM2], IfcTimings.Ftim[2]);
+ IfcWrite ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM3], IfcTimings.Ftim[3]);
+
+ // Configure chip select option registers
+ IfcWrite ((UINTN)&IfcRegs->CsprCs[CS].Cspr, IfcTimings.Cspr);
+
+ // Configure address mask registers
+ IfcWrite ((UINTN)&IfcRegs->AmaskCs[CS].Amask, IfcTimings.Amask);
+
+ // Configure chip select property registers
+ IfcWrite ((UINTN)&IfcRegs->CsorCs[CS].Csor, IfcTimings.Csor);
+
+ return;
+}
+
+VOID
+NandInit(
+ VOID
+ )
+{
+ IFC_REGS* IfcRegs;
+ IFC_TIMINGS NandIfcTimings;
+
+ IfcRegs = (IFC_REGS*) PcdGet64 (PcdIfcBaseAddr);
+
+ // Get Nand Flash Timings
+ GetIfcNandFlashTimings (&NandIfcTimings);
+
+ // Validate chip select
+ if (NandIfcTimings.CS < IFC_CS_MAX) {
+ mNandCS = NandIfcTimings.CS;
+
+ // clear event registers
+ IfcWrite ((UINTN)&IfcRegs->IfcNand.PgrdcmplEvtStat, ~0U);
+
+ IfcWrite ((UINTN)&IfcRegs->IfcNand.NandEvterStat, ~0U);
+
+ // Enable error and event for any detected errors
+ IfcWrite ((UINTN)&IfcRegs->IfcNand.NandEvterEn,
+ IFC_NAND_EVTER_EN_OPC_EN |
+ IFC_NAND_EVTER_EN_PGRDCMPL_EN |
+ IFC_NAND_EVTER_EN_FTOER_EN |
+ IFC_NAND_EVTER_EN_WPER_EN);
+ IfcWrite ((UINTN)&IfcRegs->IfcNand.Ncfgr, 0x0);
+
+ SetTimings (mNandCS, NandIfcTimings);
+ }
+
+ return;
+}
+
+VOID
+FpgaInit (
+ VOID
+ )
+{
+ IFC_TIMINGS FpgaIfcTimings;
+
+ // Get Fpga Flash Timings
+ GetIfcFpgaTimings (&FpgaIfcTimings);
+
+ // Validate chip select
+ if (FpgaIfcTimings.CS < IFC_CS_MAX) {
+ mFpgaCS = FpgaIfcTimings.CS;
+ SetTimings (mFpgaCS, FpgaIfcTimings);
+ }
+
+ return;
+}
+
+VOID
+NorInit (
+ VOID
+ )
+{
+ IFC_TIMINGS NorIfcTimings;
+
+ // Get NOR Flash Timings
+ GetIfcNorFlashTimings (&NorIfcTimings);
+
+ // Validate chip select
+ if (NorIfcTimings.CS < IFC_CS_MAX) {
+ mNorCS = NorIfcTimings.CS;
+ SetTimings (mNorCS, NorIfcTimings);
+ }
+
+ return;
+}
+
+//
+// IFC has NOR , NAND and FPGA
+//
+VOID
+IfcInit (
+ VOID
+ )
+{
+ NorInit();
+ NandInit();
+ FpgaInit();
+
+ return;
+}
diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.h b/Silicon/NXP/Library/IfcLib/IfcLib.h
new file mode 100644
index 0000000..9f52576
--- /dev/null
+++ b/Silicon/NXP/Library/IfcLib/IfcLib.h
@@ -0,0 +1,184 @@
+/** @IfcLib.h
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __IFC_LIB_H__
+#define __IFC_LIB_H__
+
+#include <Ifc.h>
+#include <Uefi.h>
+
+#define IFC_NAND_RESERVED_SIZE FixedPcdGet32 (PcdIfcNandReservedSize)
+
+typedef enum {
+ IFC_FTIM0 = 0,
+ IFC_FTIM1,
+ IFC_FTIM2,
+ IFC_FTIM3,
+} IFC_FTIMS;
+
+typedef struct {
+ UINT32 CsprExt;
+ UINT32 Cspr;
+ UINT32 Res;
+} IFC_CSPR;
+
+typedef struct {
+ UINT32 Amask;
+ UINT32 Res[0x2];
+} IFC_AMASK;
+
+typedef struct {
+ UINT32 Csor;
+ UINT32 CsorExt;
+ UINT32 Res;
+} IFC_CSOR;
+
+typedef struct {
+ UINT32 Ftim[4];
+ UINT32 Res[0x8];
+}IFC_FTIM ;
+
+typedef struct {
+ UINT32 Ncfgr;
+ UINT32 Res1[0x4];
+ UINT32 NandFcr0;
+ UINT32 NandFcr1;
+ UINT32 Res2[0x8];
+ UINT32 Row0;
+ UINT32 Res3;
+ UINT32 Col0;
+ UINT32 Res4;
+ UINT32 Row1;
+ UINT32 Res5;
+ UINT32 Col1;
+ UINT32 Res6;
+ UINT32 Row2;
+ UINT32 Res7;
+ UINT32 Col2;
+ UINT32 Res8;
+ UINT32 Row3;
+ UINT32 Res9;
+ UINT32 Col3;
+ UINT32 Res10[0x24];
+ UINT32 NandFbcr;
+ UINT32 Res11;
+ UINT32 NandFir0;
+ UINT32 NandFir1;
+ UINT32 nandFir2;
+ UINT32 Res12[0x10];
+ UINT32 NandCsel;
+ UINT32 Res13;
+ UINT32 NandSeqStrt;
+ UINT32 Res14;
+ UINT32 NandEvterStat;
+ UINT32 Res15;
+ UINT32 PgrdcmplEvtStat;
+ UINT32 Res16[0x2];
+ UINT32 NandEvterEn;
+ UINT32 Res17[0x2];
+ UINT32 NandEvterIntrEn;
+ UINT32 Res18[0x2];
+ UINT32 NandErattr0;
+ UINT32 NandErattr1;
+ UINT32 Res19[0x10];
+ UINT32 NandFsr;
+ UINT32 Res20;
+ UINT32 NandEccstat[4];
+ UINT32 Res21[0x20];
+ UINT32 NanNdcr;
+ UINT32 Res22[0x2];
+ UINT32 NandAutobootTrgr;
+ UINT32 Res23;
+ UINT32 NandMdr;
+ UINT32 Res24[0x5C];
+} IFC_NAND;
+
+/*
+ * IFC controller NOR Machine registers
+ */
+typedef struct {
+ UINT32 NorEvterStat;
+ UINT32 Res1[0x2];
+ UINT32 NorEvterEn;
+ UINT32 Res2[0x2];
+ UINT32 NorEvterIntrEn;
+ UINT32 Res3[0x2];
+ UINT32 NorErattr0;
+ UINT32 NorErattr1;
+ UINT32 NorErattr2;
+ UINT32 Res4[0x4];
+ UINT32 NorCr;
+ UINT32 Res5[0xEF];
+} IFC_NOR;
+
+/*
+ * IFC controller GPCM Machine registers
+ */
+typedef struct {
+ UINT32 GpcmEvterStat;
+ UINT32 Res1[0x2];
+ UINT32 GpcmEvterEn;
+ UINT32 Res2[0x2];
+ UINT32 gpcmEvterIntrEn;
+ UINT32 Res3[0x2];
+ UINT32 GpcmErattr0;
+ UINT32 GpcmErattr1;
+ UINT32 GcmErattr2;
+ UINT32 GpcmStat;
+} IFC_GPCM;
+
+/*
+ * IFC Controller Registers
+ */
+typedef struct {
+ UINT32 IfcRev;
+ UINT32 Res1[0x2];
+ IFC_CSPR CsprCs[IFC_BANK_COUNT];
+ UINT8 Res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
+ IFC_AMASK AmaskCs[IFC_BANK_COUNT];
+ UINT8 Res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
+ IFC_CSOR CsorCs[IFC_BANK_COUNT];
+ UINT8 Res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
+ IFC_FTIM FtimCs[IFC_BANK_COUNT];
+ UINT8 Res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
+ UINT32 RbStat;
+ UINT32 RbMap;
+ UINT32 WpMap;
+ UINT32 IfcGcr;
+ UINT32 Res7[0x2];
+ UINT32 CmEvter_stat;
+ UINT32 Res8[0x2];
+ UINT32 CmEvterEn;
+ UINT32 Res9[0x2];
+ UINT32 CmEvterIntrEn;
+ UINT32 Res10[0x2];
+ UINT32 CmErattr0;
+ UINT32 CmErattr1;
+ UINT32 Res11[0x2];
+ UINT32 IfcCcr;
+ UINT32 IfcCsr;
+ UINT32 DdrCcrLow;
+ UINT32 Res12[IFC_NAND_RESERVED_SIZE];
+ IFC_NAND IfcNand;
+ IFC_NOR IfcNor;
+ IFC_GPCM IfcGpcm;
+} IFC_REGS;
+
+extern VOID GetIfcNorFlashTimings (IFC_TIMINGS * NorIfcTimings);
+
+extern VOID GetIfcFpgaTimings (IFC_TIMINGS *FpgaIfcTimings);
+
+extern VOID GetIfcNandFlashTimings (IFC_TIMINGS * NandIfcTimings);
+
+#endif //__IFC_LIB_H__
diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.inf b/Silicon/NXP/Library/IfcLib/IfcLib.inf
new file mode 100644
index 0000000..170ed38
--- /dev/null
+++ b/Silicon/NXP/Library/IfcLib/IfcLib.inf
@@ -0,0 +1,38 @@
+# IfcLib.inf
+#
+# Component description file for IFC Library
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = IfcLib
+ FILE_GUID = a465d76c-0785-4ee7-bd72-767983d575a2
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = IfcLib
+
+[Sources.common]
+ IfcLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BoardLib
+ BeIoLib
+
+[FixedPcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index a73e9d5..43d0a71 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -77,6 +77,7 @@
gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000128
gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129
gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0|UINT64|0x0000012B
#
# IFC PCDs
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 13/39] LS1043/FpgaLib : Add support for FpgaLib.
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (11 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 12/39] Silicon/NXP : Add support of IfcLib Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-18 18:43 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 14/39] LS1043 : Enable support of FpgaLib Meenakshi
` (28 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
FpgaLib export FPGA_READ and FPGA_WRITE function and
provide a function to print Board personality.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h | 79 ++++++++++++
.../NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c | 142 +++++++++++++++++++++
.../NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 +++++
3 files changed, 252 insertions(+)
create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h b/Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h
new file mode 100644
index 0000000..3f55a02
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h
@@ -0,0 +1,79 @@
+/** FpgaLib.h
+* Header defining the LS1043a Fpga specific constants (Base addresses, sizes, flags)
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __LS1043A_FPGA_H__
+#define __LS1043A_FPGA_H__
+
+/*
+ * FPGA register set of LS1043ARDB board-specific.
+ */
+typedef struct {
+ UINT8 FpgaVersionMajor; /* 0x0 - FPGA Major Revision Register */
+ UINT8 FpgaVersionMinor; /* 0x1 - FPGA Minor Revision Register */
+ UINT8 PcbaVersion; /* 0x2 - PCBA Revision Register */
+ UINT8 SystemReset; /* 0x3 - system reset register */
+ UINT8 SoftMuxOn; /* 0x4 - Switch Control Enable Register */
+ UINT8 RcwSource1; /* 0x5 - Reset config word 1 */
+ UINT8 RcwSource2; /* 0x6 - Reset config word 1 */
+ UINT8 Vbank; /* 0x7 - Flash bank selection Control */
+ UINT8 SysclkSelect; /* 0x8 - System clock selection Control */
+ UINT8 UartSel; /* 0x9 - Uart selection Control */
+ UINT8 Sd1RefClkSel; /* 0xA - Serdes1 reference clock selection Control */
+ UINT8 TdmClkMuxSel; /* 0xB - TDM Clock Mux selection Control */
+ UINT8 SdhcSpiCsSel; /* 0xC - SDHC/SPI Chip select selection Control */
+ UINT8 StatusLed; /* 0xD - Status Led */
+ UINT8 GlobalReset; /* 0xE - Global reset */
+} FPGA_REG_SET;
+
+UINT8
+FpgaRead (
+ UINTN Reg
+ );
+
+VOID
+FpgaWrite (
+ UINTN Reg,
+ UINT8 Value
+ );
+
+VOID
+FpgaRevBit (
+ UINT8 *Value
+ );
+
+VOID
+FpgaInit (
+ VOID
+ );
+
+VOID
+PrintBoardPersonality (
+ VOID
+ );
+
+#define FPGA_BASE_PHYS 0x7fb00000
+
+#define SRC_VBANK 0x25
+#define SRC_NAND 0x106
+#define SRC_QSPI 0x44
+#define SRC_SD 0x40
+
+#define SERDES_FREQ1 "100.00 MHz"
+#define SERDES_FREQ2 "156.25 MHz"
+
+#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg))
+#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), Value)
+
+#endif
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c b/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c
new file mode 100644
index 0000000..99d514d
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c
@@ -0,0 +1,142 @@
+/** @FpgaLib.c
+ Fpga Library for LS1043A-RDB board, containing functions to
+ program and read the Fpga registers.
+
+ FPGA is connected to IFC Controller and so MMIO APIs are used
+ to read/write FPGA registers
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/FpgaLib.h>
+#include <Library/IoLib.h>
+
+/**
+ Function to read FPGA register.
+
+ @param Reg Register offset of FPGA to read.
+
+**/
+UINT8
+FpgaRead (
+ IN UINTN Reg
+ )
+{
+ VOID *Base;
+
+ Base = (VOID *)FPGA_BASE_PHYS;
+
+ return MmioRead8 ((UINTN)(Base + Reg));
+}
+
+/**
+ Function to write FPGA register.
+
+ @param Reg Register offset of FPGA to write.
+ @param Value Value to be written.
+
+**/
+VOID
+FpgaWrite (
+ IN UINTN Reg,
+ IN UINT8 Value
+ )
+{
+ VOID *Base;
+
+ Base = (VOID *)FPGA_BASE_PHYS;
+
+ MmioWrite8 ((UINTN)(Base + Reg), Value);
+}
+
+/**
+ Function to reverse the number.
+
+ @param *Value pointer to number to reverse.
+
+ @retval *Value reversed value.
+
+**/
+VOID
+FpgaRevBit (
+ OUT UINT8 *Value
+ )
+{
+ UINT8 Rev;
+ UINT8 Val;
+ UINTN Index;
+
+ Val = *Value;
+ Rev = Val & 1;
+ for (Index = 1; Index <= 7; Index++) {
+ Val >>= 1;
+ Rev <<= 1;
+ Rev |= Val & 1;
+ }
+
+ *Value = Rev;
+}
+
+/**
+ Function to print board personality.
+
+**/
+VOID
+PrintBoardPersonality (
+ VOID
+ )
+{
+ UINT8 RcwSrc1;
+ UINT8 RcwSrc2;
+ UINT32 RcwSrc;
+ UINT32 Sd1RefClkSel;
+
+ RcwSrc1 = FPGA_READ(RcwSource1);
+ RcwSrc2 = FPGA_READ(RcwSource2);
+ FpgaRevBit (&RcwSrc1);
+ RcwSrc = RcwSrc1;
+ RcwSrc = (RcwSrc << 1) | RcwSrc2;
+
+ switch (RcwSrc) {
+ case SRC_VBANK:
+ DEBUG ((DEBUG_INFO, "vBank: %d\n", FPGA_READ(Vbank)));
+ break;
+ case SRC_NAND:
+ DEBUG ((DEBUG_INFO, "NAND\n"));
+ break;
+ case SRC_QSPI:
+ DEBUG ((DEBUG_INFO, "QSPI vBank %d\n", FPGA_READ(Vbank)));
+ break;
+ case SRC_SD:
+ DEBUG ((DEBUG_INFO, "SD\n"));
+ break;
+ default:
+ DEBUG ((DEBUG_INFO, "Invalid setting of SW5\n"));
+ break;
+ }
+
+ DEBUG ((DEBUG_INFO, "FPGA: V%x.%x\nPCBA: V%x.0\n",
+ FPGA_READ(FpgaVersionMajor),
+ FPGA_READ(FpgaVersionMinor),
+ FPGA_READ(PcbaVersion)));
+
+ DEBUG ((DEBUG_INFO, "SERDES Reference Clocks:\n"));
+
+ Sd1RefClkSel = FPGA_READ(Sd1RefClkSel);
+ DEBUG((DEBUG_INFO, "SD1_CLK1 = %a, SD1_CLK2 = %a\n",
+ Sd1RefClkSel ? SERDES_FREQ2 : SERDES_FREQ1, SERDES_FREQ1));
+
+ return;
+}
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
new file mode 100644
index 0000000..39e9bde
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
@@ -0,0 +1,31 @@
+# @FpgaLib.inf
+#
+# Copyright 2017 NXP
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001000A
+ BASE_NAME = FpgaLib
+ FILE_GUID = 5962d040-8b8a-11df-9a71-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = FpgaLib
+
+[Sources.common]
+ FpgaLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ IoLib
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 14/39] LS1043 : Enable support of FpgaLib.
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (12 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 13/39] LS1043/FpgaLib : Add support for FpgaLib Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-18 18:43 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 15/39] Silicon/NXP : Add support of NorFlashLib Meenakshi
` (27 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 3 +++
Silicon/NXP/Chassis/Chassis2/Soc.c | 5 +++++
Silicon/NXP/Chassis/LS1043aSocLib.inf | 2 ++
Silicon/NXP/LS1043A/LS1043A.dsc | 2 ++
4 files changed, 12 insertions(+)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 6e9e7e0..df4d917 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -38,6 +38,9 @@
BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf
SocLib|Silicon/NXP/Chassis/LS1043aSocLib.inf
RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
+ IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
+ BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
+ FpgaLib|Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
[PcdsFixedAtBuild.common]
diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chassis2/Soc.c
index 7f9f963..17de7e4 100644
--- a/Silicon/NXP/Chassis/Chassis2/Soc.c
+++ b/Silicon/NXP/Chassis/Chassis2/Soc.c
@@ -18,6 +18,7 @@
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib/MemLibInternals.h>
#include <Library/DebugLib.h>
+#include <Library/IfcLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
@@ -25,6 +26,8 @@
#include "Soc.h"
+extern VOID PrintBoardPersonality (VOID);
+
/**
Calculate the frequency of various controllers and
populate the passed structure with frequuencies.
@@ -167,6 +170,8 @@ SocInit (
//
PrintRCW ();
PrintSoc ();
+ IfcInit();
+ PrintBoardPersonality ();
return;
}
diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS1043aSocLib.inf
index 1b2f9c4..d01b353 100644
--- a/Silicon/NXP/Chassis/LS1043aSocLib.inf
+++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf
@@ -31,6 +31,8 @@
BaseLib
BeIoLib
DebugLib
+ FpgaLib
+ IfcLib
SerialPortLib
[Sources.common]
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc b/Silicon/NXP/LS1043A/LS1043A.dsc
index 8395dfd..a4eb117 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc
@@ -63,11 +63,13 @@
gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
#
# Big Endian IPs
#
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
##
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 15/39] Silicon/NXP : Add support of NorFlashLib
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (13 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 14/39] LS1043 : Enable support of FpgaLib Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-18 19:26 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 16/39] Silicon/NXP : Add NOR driver Meenakshi
` (26 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
NorFlashLib interacts with the underlying IFC NOR controller.
This will be used by NOR driver for any information
exchange with NOR controller.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Include/Library/NorFlashLib.h | 77 +++
Silicon/NXP/Include/NorFlash.h | 48 ++
Silicon/NXP/Library/NorFlashLib/CfiCommand.h | 99 ++++
Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c | 233 ++++++++
Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h | 68 +++
Silicon/NXP/Library/NorFlashLib/NorFlashLib.c | 660 +++++++++++++++++++++++
Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf | 41 ++
7 files changed, 1226 insertions(+)
create mode 100644 Silicon/NXP/Include/Library/NorFlashLib.h
create mode 100644 Silicon/NXP/Include/NorFlash.h
create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiCommand.h
create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
diff --git a/Silicon/NXP/Include/Library/NorFlashLib.h b/Silicon/NXP/Include/Library/NorFlashLib.h
new file mode 100644
index 0000000..defdc61
--- /dev/null
+++ b/Silicon/NXP/Include/Library/NorFlashLib.h
@@ -0,0 +1,77 @@
+/** @file
+
+ Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+ Copyright 2017 NXP
+
+This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ **/
+
+#ifndef _NOR_FLASH_LIB_H_
+#define _NOR_FLASH_LIB_H_
+
+#include <NorFlash.h>
+
+#define NOR_FLASH_DEVICE_COUNT 1
+
+typedef struct {
+ UINTN DeviceBaseAddress; // Start address of the Device Base Address (DBA)
+ UINTN RegionBaseAddress; // Start address of one single region
+ UINTN Size;
+ UINTN BlockSize;
+ UINTN MultiByteWordCount; // Maximum Word count that can be written to Nor Flash in multi byte write
+ UINTN WordWriteTimeOut; // single byte/word timeout usec
+ UINTN BufferWriteTimeOut; // buffer write timeout usec
+ UINTN BlockEraseTimeOut; // block erase timeout usec
+ UINTN ChipEraseTimeOut; // chip erase timeout usec
+} NorFlashDescription;
+
+EFI_STATUS
+NorFlashPlatformGetDevices (
+ OUT NorFlashDescription **NorFlashDevices,
+ OUT UINT32 *Count
+ );
+
+EFI_STATUS
+NorFlashPlatformFlashGetAttributes (
+ OUT NorFlashDescription *NorFlashDevices,
+ IN UINT32 Count
+ );
+
+EFI_STATUS
+NorFlashPlatformWriteBuffer (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+EFI_STATUS
+NorFlashPlatformEraseSector (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN SectorAddress
+ );
+
+EFI_STATUS
+NorFlashPlatformRead (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN UINTN BufferSizeInBytes,
+ OUT UINT8 *Buffer
+ );
+
+EFI_STATUS
+NorFlashPlatformReset (
+ IN UINTN Instance
+ );
+
+#endif /* _NOR_FLASH_LIB_H_ */
diff --git a/Silicon/NXP/Include/NorFlash.h b/Silicon/NXP/Include/NorFlash.h
new file mode 100644
index 0000000..888f5c1
--- /dev/null
+++ b/Silicon/NXP/Include/NorFlash.h
@@ -0,0 +1,48 @@
+/** @NorFlash.h
+
+ Contains data structure shared by both NOR Library and Driver.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __NOR_FLASH_H__
+#define __NOR_FLASH_H__
+
+#include <Protocol/BlockIo.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+
+typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
+typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Instance);
+
+typedef struct {
+ VENDOR_DEVICE_PATH Vendor;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} NOR_FLASH_DEVICE_PATH;
+
+struct _NOR_FLASH_INSTANCE {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ BOOLEAN Initialized;
+ NOR_FLASH_INITIALIZE Initialize;
+ UINTN DeviceBaseAddress;
+ UINTN RegionBaseAddress;
+ UINTN Size;
+ EFI_LBA StartLba;
+ EFI_BLOCK_IO_PROTOCOL BlockIoProtocol;
+ EFI_BLOCK_IO_MEDIA Media;
+ BOOLEAN SupportFvb;
+ EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
+ VOID* ShadowBuffer;
+ NOR_FLASH_DEVICE_PATH DevicePath;
+};
+
+
+#endif /* __NOR_FLASH_H__ */
diff --git a/Silicon/NXP/Library/NorFlashLib/CfiCommand.h b/Silicon/NXP/Library/NorFlashLib/CfiCommand.h
new file mode 100644
index 0000000..8543227
--- /dev/null
+++ b/Silicon/NXP/Library/NorFlashLib/CfiCommand.h
@@ -0,0 +1,99 @@
+/** @CfiCommand.h
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __CFI_COMMAND_H__
+#define __CFI_COMMAND_H__
+
+// CFI Data "QRY"
+#define CFI_QRY_Q 0x51
+#define CFI_QRY_R 0x52
+#define CFI_QRY_Y 0x59
+#define CFI_QRY 0x515259
+
+#define ENTER_CFI_QUERY_MODE_ADDR 0x0055
+#define ENTER_CFI_QUERY_MODE_CMD 0x0098
+
+#define CFI_QUERY_UNIQUE_QRY_STRING 0x10
+
+// Offsets for CFI queries
+#define CFI_QUERY_TYP_TIMEOUT_WORD_WRITE 0x1F
+#define CFI_QUERY_TYP_TIMEOUT_MAX_BUFFER_WRITE 0x20
+#define CFI_QUERY_TYP_TIMEOUT_BLOCK_ERASE 0x21
+#define CFI_QUERY_TYP_TIMEOUT_CHIP_ERASE 0x22
+#define CFI_QUERY_MAX_TIMEOUT_WORD_WRITE 0x23
+#define CFI_QUERY_MAX_TIMEOUT_MAX_BUFFER_WRITE 0x24
+#define CFI_QUERY_MAX_TIMEOUT_BLOCK_ERASE 0x25
+#define CFI_QUERY_MAX_TIMEOUT_CHIP_ERASE 0x26
+#define CFI_QUERY_DEVICE_SIZE 0x27
+#define CFI_QUERY_MAX_NUM_BYTES_WRITE 0x2A
+#define CFI_QUERY_BLOCK_SIZE 0x2F
+
+// Unlock Address
+#define CMD_UNLOCK_1_ADDR 0x555
+#define CMD_UNLOCK_2_ADDR 0x2AA
+
+// RESET Command
+#define CMD_RESET_FIRST 0xAA
+#define CMD_RESET_SECOND 0x55
+#define CMD_RESET 0xF0
+
+// READ Command
+
+// Manufacturer ID
+#define CMD_READ_M_ID_FIRST 0xAA
+#define CMD_READ_M_ID_SECOND 0x55
+#define CMD_READ_M_ID_THIRD 0x90
+#define CMD_READ_M_ID_FOURTH 0x01
+
+// Device ID
+#define CMD_READ_D_ID_FIRST 0xAA
+#define CMD_READ_D_ID_SECOND 0x55
+#define CMD_READ_D_ID_THIRD 0x90
+#define CMD_READ_D_ID_FOURTH 0x7E
+#define CMD_READ_D_ID_FIFTH 0x13
+#define CMD_READ_D_ID_SIXTH 0x00
+
+// WRITE Command
+
+// PROGRAM Command
+#define CMD_PROGRAM_FIRST 0xAA
+#define CMD_PROGRAM_SECOND 0x55
+#define CMD_PROGRAM_THIRD 0xA0
+
+// Write Buffer Command
+#define CMD_WRITE_TO_BUFFER_FIRST 0xAA
+#define CMD_WRITE_TO_BUFFER_SECOND 0x55
+#define CMD_WRITE_TO_BUFFER_THIRD 0x25
+#define CMD_WRITE_TO_BUFFER_CONFIRM 0x29
+
+// ERASE Command
+
+// UNLOCK COMMANDS FOR ERASE
+#define CMD_ERASE_FIRST 0xAA
+#define CMD_ERASE_SECOND 0x55
+#define CMD_ERASE_THIRD 0x80
+#define CMD_ERASE_FOURTH 0xAA
+#define CMD_ERASE_FIFTH 0x55
+
+// Chip Erase Command
+#define CMD_CHIP_ERASE_SIXTH 0x10
+
+// Sector Erase Command
+#define CMD_SECTOR_ERASE_SIXTH 0x30
+
+// SUSPEND Command
+#define CMD_PROGRAM_OR_ERASE_SUSPEND 0xB0
+#define CMD_PROGRAM_OR_ERASE_RESUME 0x30
+
+#endif // __CFI_COMMAND_H__
diff --git a/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
new file mode 100644
index 0000000..632e943
--- /dev/null
+++ b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
@@ -0,0 +1,233 @@
+/** @CfiNorFlashLib.c
+
+ Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ **/
+
+#include <PiDxe.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+
+#include "CfiCommand.h"
+#include "CfiNorFlashLib.h"
+
+FLASH_DATA
+IfcNorFlashData (
+ IN OUT FLASH_DATA Value
+ )
+{
+ if (FixedPcdGetBool (PcdIfcBigEndian)) {
+ return SwapBytes16 (Value);
+ } else {
+ return Value;
+ }
+}
+
+/**
+ Write Val at given address.
+
+ @param Val Data to be written.
+ @param Addr Address where data is to be written.
+
+**/
+VOID
+FlashWriteData (
+ IN FLASH_DATA Val,
+ IN UINTN Addr
+ )
+{
+ *(volatile FLASH_DATA *)(Addr) = (Val);
+}
+
+/**
+ Check endianness of IFC Controller and depending on swap
+ the data and write on given address.
+
+ @param Val Data to be written.
+ @param Addr Address where data is to be written.
+
+**/
+VOID
+FlashWrite (
+ IN FLASH_DATA Val,
+ IN UINTN Addr
+ )
+{
+ FLASH_DATA ShiftVal;
+
+ ShiftVal = IfcNorFlashData (Val);
+
+ *(volatile FLASH_DATA *)(Addr) = (ShiftVal);
+}
+
+/**
+ Read data from given address.
+
+ @param Addr Address from where data is to be read.
+
+ @return Read Data
+**/
+FLASH_DATA
+FlashReadData (
+ IN UINTN Addr
+ )
+{
+ FLASH_DATA Val;
+
+ Val = *(volatile FLASH_DATA *)(Addr);
+
+ return (Val);
+}
+
+/**
+ Read data from given address and depending on endianness of IFC Controller
+ swap the read data.
+
+ @param Addr Address from where data is to be read.
+
+ @return Read Data
+**/
+FLASH_DATA
+FlashRead (
+ IN UINTN Addr
+ )
+{
+ FLASH_DATA Val;
+ FLASH_DATA ShiftVal;
+
+ Val = *(volatile FLASH_DATA *)(Addr);
+ ShiftVal = IfcNorFlashData (Val);
+
+ return (ShiftVal);
+}
+
+STATIC
+VOID
+NorFlashReadCfiData (
+ IN UINTN DeviceBaseAddress,
+ IN UINTN CfiOffset,
+ IN UINT32 NumberOfShorts,
+ OUT VOID *Data
+ )
+{
+ UINT32 Count;
+ FLASH_DATA *TmpData = (FLASH_DATA *)Data;
+
+ for (Count = 0; Count < NumberOfShorts; Count++, TmpData++) {
+ *TmpData = FLASH_READ ((UINTN)((FLASH_DATA*)DeviceBaseAddress + CfiOffset));
+ CfiOffset++;
+ }
+}
+
+/*
+ Currently we support only CFI flash devices; Bail-out otherwise
+*/
+EFI_STATUS
+CfiNorFlashFlashGetAttributes (
+ OUT NorFlashDescription *NorFlashDevices,
+ IN UINT32 Index
+ )
+{
+ UINT32 Count;
+ FLASH_DATA QryData[3];
+ FLASH_DATA BlockSize[2];
+ UINTN DeviceBaseAddress;
+ FLASH_DATA MaxNumBytes[2];
+ FLASH_DATA Size;
+ FLASH_DATA HighByteMask; // Masks High byte in a UIN16 word
+ FLASH_DATA HighByteShift; // Bitshifts needed to make a byte High Byte in a UIN16 word
+ FLASH_DATA Temp1;
+ FLASH_DATA Temp2;
+
+ HighByteMask = 0xFF;
+ HighByteShift = 8;
+
+ for (Count = 0; Count < Index; Count++) {
+
+ NorFlashDevices[Count].DeviceBaseAddress = DeviceBaseAddress = PcdGet64 (PcdFlashDeviceBase64);
+
+ // Reset flash first
+ NorFlashPlatformReset (DeviceBaseAddress);
+
+ // Enter the CFI Query Mode
+ SEND_NOR_COMMAND (DeviceBaseAddress, ENTER_CFI_QUERY_MODE_ADDR,
+ ENTER_CFI_QUERY_MODE_CMD);
+
+ ArmDataSynchronizationBarrier ();
+
+ // Query the unique QRY
+ NorFlashReadCfiData (DeviceBaseAddress,
+ CFI_QUERY_UNIQUE_QRY_STRING,
+ 3,
+ &QryData);
+ if (QryData[0] != (FLASH_DATA)CFI_QRY_Q || QryData[1] !=
+ (FLASH_DATA)CFI_QRY_R || QryData[2] != (FLASH_DATA)CFI_QRY_Y ) {
+ DEBUG ((DEBUG_ERROR, "Not a CFI flash (QRY not recvd): "
+ "Got = 0x%04x, 0x%04x, 0x%04x\n",
+ QryData[0], QryData[1], QryData[2]));
+ return EFI_DEVICE_ERROR;
+ }
+
+ NorFlashReadCfiData (DeviceBaseAddress, CFI_QUERY_DEVICE_SIZE,
+ 1, &Size);
+ // Refer CFI Specification
+ NorFlashDevices[Count].Size = 1 << Size;
+
+ NorFlashReadCfiData (DeviceBaseAddress, CFI_QUERY_BLOCK_SIZE,
+ 2, &BlockSize);
+ // Refer CFI Specification
+ NorFlashDevices[Count].BlockSize = 256 * ((FLASH_DATA) ((BlockSize[1] <<
+ HighByteShift) | (BlockSize[0] & HighByteMask)));
+
+ NorFlashReadCfiData (DeviceBaseAddress,
+ CFI_QUERY_MAX_NUM_BYTES_WRITE, 2, &MaxNumBytes);
+ // Refer CFI Specification
+ /* from CFI query we get the Max. number of BYTE in multi-byte write = 2^N.
+ But our Flash Library is able to read/write in WORD size (2 bytes) which
+ is why we need to CONVERT MAX BYTES TO MAX WORDS by diving it by
+ width of word size */
+ NorFlashDevices[Count].MultiByteWordCount =\
+ (1 << ((FLASH_DATA)((MaxNumBytes[1] << HighByteShift) |
+ (MaxNumBytes[0] & HighByteMask))))/sizeof(FLASH_DATA);
+
+ NorFlashReadCfiData (DeviceBaseAddress,
+ CFI_QUERY_TYP_TIMEOUT_WORD_WRITE, 1, &Temp1);
+ NorFlashReadCfiData (DeviceBaseAddress,
+ CFI_QUERY_MAX_TIMEOUT_WORD_WRITE, 1, &Temp2);
+ NorFlashDevices[Count].WordWriteTimeOut = (1U << Temp1) * (1U << Temp2);
+
+ NorFlashReadCfiData (DeviceBaseAddress,
+ CFI_QUERY_TYP_TIMEOUT_MAX_BUFFER_WRITE, 1, &Temp1);
+ NorFlashReadCfiData (DeviceBaseAddress,
+ CFI_QUERY_MAX_TIMEOUT_MAX_BUFFER_WRITE, 1, &Temp2);
+ NorFlashDevices[Count].BufferWriteTimeOut = (1U << Temp1) * (1U << Temp2);
+
+ NorFlashReadCfiData (DeviceBaseAddress,
+ CFI_QUERY_TYP_TIMEOUT_BLOCK_ERASE, 1, &Temp1);
+ NorFlashReadCfiData (DeviceBaseAddress,
+ CFI_QUERY_MAX_TIMEOUT_BLOCK_ERASE, 1, &Temp2);
+ NorFlashDevices[Count].BlockEraseTimeOut =
+ (1U << Temp1) * (1U << Temp2) * 1000;
+
+ NorFlashReadCfiData (DeviceBaseAddress,
+ CFI_QUERY_TYP_TIMEOUT_CHIP_ERASE, 1, &Temp1);
+ NorFlashReadCfiData (DeviceBaseAddress,
+ CFI_QUERY_MAX_TIMEOUT_CHIP_ERASE, 1, &Temp2);
+ NorFlashDevices[Count].ChipEraseTimeOut =
+ (1U << Temp1) * (1U << Temp2) * 1000;
+
+ // Put device back into Read Array mode (via Reset)
+ NorFlashPlatformReset (DeviceBaseAddress);
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
new file mode 100644
index 0000000..91d50f0
--- /dev/null
+++ b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
@@ -0,0 +1,68 @@
+/** @CfiNorFlashLib.h
+
+ Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __CFI_NOR_FLASH_LIB_H__
+#define __CFI_NOR_FLASH_LIB_H__
+
+#include <Library/DebugLib.h>
+#include <Library/NorFlashLib.h>
+
+/*
+ * Values for the width of the port
+ */
+#define FLASH_CFI_8BIT 0x01
+#define FLASH_CFI_16BIT 0x02
+#define FLASH_CFI_32BIT 0x04
+#define FLASH_CFI_64BIT 0x08
+
+#define CREATE_BYTE_OFFSET(OffsetAddr) ((sizeof (FLASH_DATA)) * (OffsetAddr))
+#define CREATE_NOR_ADDRESS(BaseAddr, OffsetAddr) ((BaseAddr) + (OffsetAddr))
+#define FLASH_READ(Addr) FlashRead ((Addr))
+#define FLASH_WRITE(Addr, Val) FlashWrite ((Val), (Addr))
+#define FLASH_READ_DATA(Addr) FlashReadData ((Addr))
+#define FLASH_WRITE_DATA(Addr, Val) FlashWriteData ((Val), (Addr))
+#define SEND_NOR_COMMAND(BaseAddr, Offset, Cmd) FLASH_WRITE (CREATE_NOR_ADDRESS (BaseAddr, CREATE_BYTE_OFFSET (Offset)), (Cmd))
+
+typedef UINT16 FLASH_DATA;
+
+VOID
+FlashWrite (
+ IN FLASH_DATA Val,
+ IN UINTN Addr
+ );
+
+FLASH_DATA
+FlashRead (
+ IN UINTN Addr
+ );
+
+VOID
+FlashWriteData (
+ IN FLASH_DATA Val,
+ IN UINTN Addr
+ );
+
+FLASH_DATA
+FlashReadData (
+ IN UINTN Addr
+ );
+
+EFI_STATUS
+CfiNorFlashFlashGetAttributes (
+ OUT NorFlashDescription *NorFlashDevices,
+ IN UINT32 Index
+ );
+
+#endif //__CFI_NOR_FLASH_LIB_H__
diff --git a/Silicon/NXP/Library/NorFlashLib/NorFlashLib.c b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
new file mode 100644
index 0000000..b74e9eb
--- /dev/null
+++ b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
@@ -0,0 +1,660 @@
+/** @NorFlashLib.c
+
+ Based on NorFlash implementation available in NorFlashDxe.c
+
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <Library/BaseMemoryLib/MemLibInternals.h>
+#include <Library/TimerLib.h>
+
+#include "CfiCommand.h"
+#include "CfiNorFlashLib.h"
+
+#define GET_BLOCK_OFFSET(Lba) ((Instance->RegionBaseAddress)-\
+ (Instance->DeviceBaseAddress)+((UINTN)((Lba) * Instance->Media.BlockSize)))
+
+NorFlashDescription mNorFlashDevices[NOR_FLASH_DEVICE_COUNT];
+
+STATIC VOID
+UnlockEraseAddress (
+ IN UINTN DeviceBaseAddress
+ )
+{ // Issue the Unlock cmds
+ SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR,
+ CMD_ERASE_FIRST);
+
+ SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR,
+ CMD_ERASE_SECOND);
+
+ // Issue a setup command
+ SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR,
+ CMD_ERASE_THIRD);
+
+ // Issue the Unlock cmds
+ SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR,
+ CMD_ERASE_FOURTH);
+
+ SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR,
+ CMD_ERASE_FIFTH);
+
+ return;
+}
+
+STATIC
+UINT64
+ConvertMicroSecondsToTicks (
+ IN UINTN MicroSeconds
+ )
+{
+ UINT64 TimerTicks64;
+
+ TimerTicks64 = 0;
+
+ // Calculate counter ticks that represent requested delay:
+ // = MicroSeconds x TICKS_PER_MICRO_SEC
+ // = MicroSeconds x Timer Frequency(in Hz) x 10^-6
+ // GetPerformanceCounterProperties = Get Arm Timer Frequency in Hz
+ TimerTicks64 = DivU64x32 (
+ MultU64x64 (
+ MicroSeconds,
+ GetPerformanceCounterProperties (NULL, NULL)
+ ),
+ 1000000U
+ );
+ return TimerTicks64;
+}
+
+/**
+ * The following function erases a NOR flash sector.
+ **/
+EFI_STATUS
+NorFlashPlatformEraseSector (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN SectorAddress
+ )
+{
+ FLASH_DATA EraseStatus1;
+ FLASH_DATA EraseStatus2;
+ UINT64 Timeout;
+ UINT64 SystemCounterVal;
+
+ EraseStatus1 = 0;
+ EraseStatus2 = 0;
+ Timeout = 0;
+
+ Timeout = ConvertMicroSecondsToTicks (
+ mNorFlashDevices[Instance->Media.MediaId].BlockEraseTimeOut);
+ // Request a sector erase by writing two unlock cycles, followed by a
+ // setup command and two additional unlock cycles
+
+ UnlockEraseAddress (Instance->DeviceBaseAddress);
+
+ // Now send the address of the sector to be erased
+ SEND_NOR_COMMAND (SectorAddress, 0, CMD_SECTOR_ERASE_SIXTH);
+
+ // Wait for erase to complete
+ // Read Sector start address twice to detect bit toggle and to
+ // determine ERASE DONE (all bits are 1)
+ // Get the maximum timer ticks needed to complete the operation
+ // Check if operation is complete or not in continous loop?
+ // if complete, exit from loop
+ // if not check the ticks that have been passed from the begining of loop
+ // if Maximum Ticks allocated for operation has passed exit from loop
+
+ SystemCounterVal = GetPerformanceCounter ();
+ Timeout += SystemCounterVal;
+ while (SystemCounterVal < Timeout) {
+ if ((EraseStatus1 = FLASH_READ (SectorAddress)) ==
+ (EraseStatus2 = FLASH_READ (SectorAddress))) {
+ if (0xFFFF == FLASH_READ (SectorAddress)) {
+ break;
+ }
+ }
+ SystemCounterVal = GetPerformanceCounter ();
+ }
+
+ if (SystemCounterVal >= Timeout) {
+ DEBUG ((DEBUG_ERROR, "%a :Failed to Erase @ SectorAddress 0x%p, Timeout\n",
+ __FUNCTION__, SectorAddress));
+ return EFI_DEVICE_ERROR;
+ } else {
+ return EFI_SUCCESS;
+ }
+}
+
+EFI_STATUS
+NorFlashPlatformWriteWord (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN WordOffset,
+ IN FLASH_DATA Word
+ )
+{
+ UINT64 Timeout;
+ UINTN TargetAddress;
+ UINT64 SystemCounterVal;
+ FLASH_DATA Read1;
+ FLASH_DATA Read2;
+
+ Timeout = 0;
+
+ Timeout = ConvertMicroSecondsToTicks (
+ mNorFlashDevices[Instance->Media.MediaId].WordWriteTimeOut);
+
+ TargetAddress = CREATE_NOR_ADDRESS (Instance->DeviceBaseAddress,
+ CREATE_BYTE_OFFSET (WordOffset));
+
+ // Issue the Unlock cmds
+ SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR,
+ CMD_PROGRAM_FIRST);
+
+ SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_2_ADDR,
+ CMD_PROGRAM_SECOND);
+
+ SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR,
+ CMD_PROGRAM_THIRD);
+
+ FLASH_WRITE_DATA (TargetAddress, Word);
+
+ // Wait for Write to Complete
+ // Read the last written address twice to detect bit toggle and
+ // to determine if date is wriiten successfully or not ?
+ // Get the maximum timer ticks needed to complete the operation
+ // Check if operation is complete or not in continous loop?
+ // if complete, exit from loop
+ // if not check the ticks that have been passed from the begining of loop
+ // if Maximum Ticks allocated for operation has passed, then exit from loop
+
+ SystemCounterVal = GetPerformanceCounter ();
+ Timeout += SystemCounterVal;
+ while (SystemCounterVal < Timeout) {
+ if ((Read1 = FLASH_READ_DATA (TargetAddress)) ==
+ (Read2 = FLASH_READ_DATA (TargetAddress))) {
+ if (Word == FLASH_READ_DATA (TargetAddress)) {
+ break;
+ }
+ }
+ SystemCounterVal = GetPerformanceCounter ();
+ }
+
+ if (SystemCounterVal >= Timeout) {
+ DEBUG ((DEBUG_ERROR, "%a: Failed to Write @ TargetAddress 0x%p, Timeout\n",
+ __FUNCTION__, TargetAddress));
+ return EFI_DEVICE_ERROR;
+ } else {
+ return EFI_SUCCESS;
+ }
+}
+
+EFI_STATUS
+NorFlashPlatformWritePageBuffer (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN PageBufferOffset,
+ IN UINTN NumWords,
+ IN FLASH_DATA *Buffer
+ )
+{
+ UINT64 Timeout;
+ UINTN LastWrittenAddress;
+ FLASH_DATA LastWritenData;
+ UINTN CurrentOffset;
+ UINTN EndOffset;
+ UINTN TargetAddress;
+ UINT64 SystemCounterVal;
+ FLASH_DATA Read1;
+ FLASH_DATA Read2;
+
+ // Initialize variables
+ Timeout = 0;
+ LastWrittenAddress = 0;
+ LastWritenData = 0;
+ CurrentOffset = PageBufferOffset;
+ EndOffset = PageBufferOffset + NumWords - 1;
+ Timeout = ConvertMicroSecondsToTicks (
+ mNorFlashDevices[Instance->Media.MediaId].BufferWriteTimeOut);
+ TargetAddress = CREATE_NOR_ADDRESS (Instance->DeviceBaseAddress,
+ CREATE_BYTE_OFFSET (CurrentOffset));
+
+ // don't try with a count of zero
+ if (!NumWords) {
+ return EFI_SUCCESS;
+ }
+ else if (NumWords == 1) {
+ return NorFlashPlatformWriteWord (Instance, PageBufferOffset, *Buffer);
+ }
+
+ // Issue the Unlock cmds
+ SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR,
+ CMD_WRITE_TO_BUFFER_FIRST);
+
+ SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_2_ADDR,
+ CMD_WRITE_TO_BUFFER_SECOND);
+
+ // Write the buffer load
+ SEND_NOR_COMMAND (TargetAddress, 0, CMD_WRITE_TO_BUFFER_THIRD);
+
+ // Write # of locations to program
+ SEND_NOR_COMMAND (TargetAddress, 0, (NumWords - 1));
+
+ // Load Data into Buffer
+ while (CurrentOffset <= EndOffset) {
+ LastWrittenAddress = CREATE_NOR_ADDRESS (Instance->DeviceBaseAddress,
+ CREATE_BYTE_OFFSET (CurrentOffset++));
+ LastWritenData = *Buffer++;
+
+ // Write Data
+ FLASH_WRITE_DATA (LastWrittenAddress,LastWritenData);
+ }
+
+ // Issue the Buffered Program Confirm command
+ SEND_NOR_COMMAND (TargetAddress, 0, CMD_WRITE_TO_BUFFER_CONFIRM);
+
+ /* Wait for Write to Complete
+ Read the last written address twice to detect bit toggle and
+ to determine if date is wriiten successfully or not ?
+ Get the maximum timer ticks needed to complete the operation
+ Check if operation is complete or not in continous loop?
+ if complete, exit from loop
+ if not check the ticks that have been passed from the begining of loop
+ if Maximum Ticks allocated for operation has passed, then exit from loop **/
+ SystemCounterVal = GetPerformanceCounter();
+ Timeout += SystemCounterVal;
+ while (SystemCounterVal < Timeout) {
+ if ((Read1 = FLASH_READ_DATA (LastWrittenAddress)) ==
+ (Read2 = FLASH_READ_DATA (LastWrittenAddress))) {
+ if (LastWritenData == FLASH_READ_DATA (LastWrittenAddress)) {
+ break;
+ }
+ }
+ SystemCounterVal = GetPerformanceCounter ();
+ }
+
+ if (SystemCounterVal >= Timeout) {
+ DEBUG ((DEBUG_ERROR, "%a: Failed to Write @LastWrittenAddress 0x%p, Timeout\n",
+ __FUNCTION__, LastWrittenAddress));
+ return EFI_DEVICE_ERROR;
+ } else {
+ return EFI_SUCCESS;
+ }
+}
+
+EFI_STATUS
+NorFlashPlatformWriteWordAlignedAddressBuffer (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN Offset,
+ IN UINTN NumWords,
+ IN FLASH_DATA *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINTN MultiByteWordCount;
+ UINTN Mask;
+ UINTN IntWords;
+
+ MultiByteWordCount = mNorFlashDevices[Instance->Media.MediaId].MultiByteWordCount;
+ Mask = MultiByteWordCount - 1;
+ IntWords = NumWords;
+ Status = EFI_SUCCESS;
+
+ if (Offset & Mask) {
+ // program only as much as necessary, so pick the lower of the two numbers
+ if (NumWords < (MultiByteWordCount - (Offset & Mask))) {
+ IntWords = NumWords;
+ } else {
+ IntWords = MultiByteWordCount - (Offset & Mask);
+ }
+
+ // program the first few to get write buffer aligned
+ Status = NorFlashPlatformWritePageBuffer (Instance, Offset, IntWords, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Offset += IntWords; // adjust pointers and counter
+ NumWords -= IntWords;
+ Buffer += IntWords;
+
+ if (NumWords == 0) {
+ return Status;
+ }
+ }
+
+ while (NumWords >= MultiByteWordCount) {// while big chunks to do
+ Status = NorFlashPlatformWritePageBuffer (Instance, Offset,
+ MultiByteWordCount, Buffer);
+ if (EFI_ERROR (Status)) {
+ return (Status);
+ }
+
+ Offset += MultiByteWordCount; // adjust pointers and counter
+ NumWords -= MultiByteWordCount;
+ Buffer += MultiByteWordCount;
+ }
+ if (NumWords == 0) {
+ return (Status);
+ }
+
+ Status = NorFlashPlatformWritePageBuffer (Instance, Offset, NumWords, Buffer);
+ return (Status);
+}
+
+/**
+ Writes data to the NOR Flash using the Buffered Programming method.
+
+ Write Buffer Programming allows the system to write a maximum of 32 bytes
+ in one programming operation. Therefore this function will only handle
+ buffers up to 32 bytes.
+ To deal with larger buffers, call this function again.
+**/
+EFI_STATUS
+NorFlashPlatformWriteBuffer (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ FLASH_DATA *SrcBuffer;
+ UINTN TargetOffsetinBytes;
+ UINTN WordsToWrite;
+ UINTN Mask;
+ UINTN BufferSizeInBytes;
+ UINTN IntBytes;
+ UINT8 *CopyFrom;
+ UINT8 *CopyTo;
+ FLASH_DATA TempWrite;
+
+ SrcBuffer = (FLASH_DATA *)Buffer;
+ TargetOffsetinBytes = 0;
+ WordsToWrite = 0;
+ Mask = sizeof (FLASH_DATA) - 1;
+ BufferSizeInBytes = *NumBytes;
+ IntBytes = BufferSizeInBytes; // Intermediate Bytes needed to copy for alignment
+ TempWrite = 0;
+
+ DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=%ld, Offset=0x%x, "
+ "*NumBytes=0x%x, Buffer @ 0x%08x)\n",
+ __FUNCTION__, Lba, Offset, *NumBytes, Buffer));
+
+ TargetOffsetinBytes = GET_BLOCK_OFFSET (Lba) + (UINTN)(Offset);
+
+ if (TargetOffsetinBytes & Mask) {
+ // Write only as much as necessary, so pick the lower of the two numbers
+ // and call it Intermediate bytes to write to make alignment proper
+ if (BufferSizeInBytes < (sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask))) {
+ IntBytes = BufferSizeInBytes;
+ } else {
+ IntBytes = sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask);
+ }
+
+ // Read the first few to get Read buffer aligned
+ NorFlashPlatformRead (Instance, Lba, (TargetOffsetinBytes & ~Mask) -
+ GET_BLOCK_OFFSET (Lba), sizeof (TempWrite), (UINT8*)&TempWrite);
+
+ CopyTo = (UINT8*)&TempWrite;
+ CopyTo += (TargetOffsetinBytes & Mask);
+ CopyFrom = (UINT8*)Buffer;
+
+ InternalMemCopyMem (CopyTo, CopyFrom, IntBytes);
+
+ Status = NorFlashPlatformWriteWordAlignedAddressBuffer (
+ Instance,
+ (UINTN)((TargetOffsetinBytes & ~Mask) / sizeof (FLASH_DATA)),
+ 1,
+ &TempWrite);
+ if (EFI_ERROR (Status)) {
+ DEBUG((DEBUG_ERROR, "%a : Failed to Write @TargetOffset 0x%x (0x%x)\n",
+ __FUNCTION__, TargetOffsetinBytes, Status));
+ goto EXIT;
+ }
+
+ TargetOffsetinBytes += IntBytes; /* adjust pointers and counter */
+ BufferSizeInBytes -= IntBytes;
+ Buffer += IntBytes;
+
+ if (BufferSizeInBytes == 0) {
+ goto EXIT;
+ }
+ }
+
+ // Write the bytes to CFI width aligned address.
+ // Note we can Write number of bytes=CFI width in one operation
+ WordsToWrite = BufferSizeInBytes/sizeof (FLASH_DATA);
+ SrcBuffer = (FLASH_DATA*)Buffer;
+
+ Status = NorFlashPlatformWriteWordAlignedAddressBuffer (
+ Instance,
+ (UINTN)(TargetOffsetinBytes/sizeof (FLASH_DATA)),
+ WordsToWrite,
+ SrcBuffer);
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "%a : Failed to Write @ TargetOffset 0x%x (0x%x)\n",
+ __FUNCTION__, TargetOffsetinBytes, Status));
+ goto EXIT;
+ }
+
+ BufferSizeInBytes -= (WordsToWrite * sizeof (FLASH_DATA));
+ Buffer += (WordsToWrite*sizeof (FLASH_DATA));
+ TargetOffsetinBytes += (WordsToWrite * sizeof (FLASH_DATA));
+
+ if (BufferSizeInBytes == 0) {
+ goto EXIT;
+ }
+
+ // Now Write bytes that are remaining and are less than CFI width.
+ // Read the first few to get Read buffer aligned
+ NorFlashPlatformRead (
+ Instance,
+ Lba,
+ TargetOffsetinBytes - GET_BLOCK_OFFSET (Lba),
+ sizeof (TempWrite),
+ (UINT8*)&TempWrite);
+
+ CopyFrom = (UINT8*)Buffer;
+ CopyTo = (UINT8*)&TempWrite;
+
+ InternalMemCopyMem (CopyTo, CopyFrom, BufferSizeInBytes);
+
+ Status = NorFlashPlatformWriteWordAlignedAddressBuffer (Instance,
+ (UINTN)(TargetOffsetinBytes/sizeof (FLASH_DATA)),
+ 1,
+ &TempWrite);
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "%a: Failed to Write @TargetOffset 0x%x Status=%d\n",
+ __FUNCTION__, TargetOffsetinBytes, Status));
+ goto EXIT;
+ }
+
+EXIT:
+ // Put device back into Read Array mode (via Reset)
+ NorFlashPlatformReset (Instance->DeviceBaseAddress);
+ return (Status);
+}
+
+EFI_STATUS
+NorFlashPlatformRead (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN UINTN BufferSizeInBytes,
+ OUT UINT8 *Buffer
+ )
+{
+ UINTN IntBytes;
+ UINTN Mask;
+ FLASH_DATA TempRead;
+ UINT8 *CopyFrom;
+ UINT8 *CopyTo;
+ UINTN TargetOffsetinBytes;
+ FLASH_DATA *ReadData;
+ UINTN BlockSize;
+
+ IntBytes = BufferSizeInBytes; //Intermediate Bytes needed to copy for alignment
+ Mask = sizeof (FLASH_DATA) - 1;
+ TempRead = 0;
+ TargetOffsetinBytes = (UINTN)(GET_BLOCK_OFFSET (Lba) + Offset);
+ BlockSize = Instance->Media.BlockSize;
+
+ DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=%ld, Offset=0x%x,"
+ " BufferSizeInBytes=0x%x, Buffer @ 0x%p)\n",
+ __FUNCTION__, Lba, Offset, BufferSizeInBytes, Buffer));
+
+ // The buffer must be valid
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Return if we have not any byte to read
+ if (BufferSizeInBytes == 0) {
+ return EFI_SUCCESS;
+ }
+
+ if (((Lba * BlockSize) + BufferSizeInBytes) > Instance->Size) {
+ DEBUG ((DEBUG_ERROR, "%a : Read will exceed device size.\n", __FUNCTION__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Put device back into Read Array mode (via Reset)
+ NorFlashPlatformReset (Instance->DeviceBaseAddress);
+
+ // First Read bytes to make buffer aligned to CFI width
+ if (TargetOffsetinBytes & Mask) {
+ // Read only as much as necessary, so pick the lower of the two numbers
+ if (BufferSizeInBytes < (sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask))) {
+ IntBytes = BufferSizeInBytes;
+ } else {
+ IntBytes = sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask);
+ }
+
+ // Read the first few to get Read buffer aligned
+ TempRead = FLASH_READ_DATA (CREATE_NOR_ADDRESS (
+ Instance->DeviceBaseAddress,
+ CREATE_BYTE_OFFSET ((TargetOffsetinBytes & ~Mask)/sizeof (FLASH_DATA))));
+
+ CopyFrom = (UINT8*)&TempRead;
+ CopyFrom += (TargetOffsetinBytes & Mask);
+ CopyTo = (UINT8*)Buffer;
+
+ InternalMemCopyMem (CopyTo, CopyFrom, IntBytes);
+
+ TargetOffsetinBytes += IntBytes; // adjust pointers and counter
+ BufferSizeInBytes -= IntBytes;
+ Buffer += IntBytes;
+ if (BufferSizeInBytes == 0) {
+ return EFI_SUCCESS;
+ }
+ }
+
+ ReadData = (FLASH_DATA*)Buffer;
+
+ // Readout the bytes from CFI width aligned address.
+ // Note we can read number of bytes=CFI width in one operation
+ while (BufferSizeInBytes >= sizeof (FLASH_DATA)) {
+ *ReadData = FLASH_READ_DATA (CREATE_NOR_ADDRESS (
+ Instance->DeviceBaseAddress,
+ CREATE_BYTE_OFFSET (TargetOffsetinBytes/sizeof (FLASH_DATA))));
+ ReadData += 1;
+ BufferSizeInBytes -= sizeof (FLASH_DATA);
+ TargetOffsetinBytes += sizeof (FLASH_DATA);
+ }
+
+ if (BufferSizeInBytes == 0) {
+ return EFI_SUCCESS;
+ }
+
+ // Now read bytes that are remaining and are less than CFI width.
+ CopyTo = (UINT8*)ReadData;
+ // Read the first few to get Read buffer aligned
+ TempRead = FLASH_READ_DATA (CREATE_NOR_ADDRESS (
+ Instance->DeviceBaseAddress,
+ CREATE_BYTE_OFFSET (TargetOffsetinBytes/sizeof (FLASH_DATA))));
+ CopyFrom = (UINT8*)&TempRead;
+
+ InternalMemCopyMem (CopyTo, CopyFrom, BufferSizeInBytes);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NorFlashPlatformReset (
+ IN UINTN DeviceBaseAddress
+ )
+{
+ SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR,
+ CMD_RESET_FIRST);
+
+ SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR,
+ CMD_RESET_SECOND);
+
+ SEND_NOR_COMMAND (DeviceBaseAddress, 0, CMD_RESET);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NorFlashPlatformGetDevices (
+ OUT NorFlashDescription **NorFlashDevices,
+ OUT UINT32 *Count
+ )
+{
+ if ((NorFlashDevices == NULL) || (Count == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Get the number of NOR flash devices supported
+ *NorFlashDevices = mNorFlashDevices;
+ *Count = NOR_FLASH_DEVICE_COUNT;
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NorFlashPlatformFlashGetAttributes (
+ OUT NorFlashDescription *NorFlashDevices,
+ IN UINT32 Count
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Index;
+
+ if ((NorFlashDevices == NULL) || (Count == 0)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Check the attributes of the NOR flash slave we are connected to.
+ // Currently we support only CFI flash devices. Bail-out otherwise.
+ Status = CfiNorFlashFlashGetAttributes (NorFlashDevices, Count);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Limit the Size of Nor Flash that can be programmed
+ for (Index = 0; Index < Count; Index++) {
+ NorFlashDevices[Index].RegionBaseAddress = PcdGet64 (PcdFlashReservedRegionBase64);
+ NorFlashDevices[Index].Size -= (NorFlashDevices[Index].RegionBaseAddress -
+ NorFlashDevices[Index].DeviceBaseAddress);
+ if((NorFlashDevices[Index].RegionBaseAddress - NorFlashDevices[Index].DeviceBaseAddress) %
+ NorFlashDevices[Index].BlockSize) {
+ DEBUG ((DEBUG_ERROR, "%a : Reserved Region(0x%p) doesn't start "
+ "from block boundry(0x%08x)\n", __FUNCTION__,
+ (UINTN)NorFlashDevices[Index].RegionBaseAddress,
+ (UINT32)NorFlashDevices[Index].BlockSize));
+ return EFI_DEVICE_ERROR;
+ }
+ }
+ return Status;
+}
diff --git a/Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
new file mode 100644
index 0000000..403766a
--- /dev/null
+++ b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
@@ -0,0 +1,41 @@
+# @NorFlashLib.inf
+#
+# Component description file for NorFlashLib module
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = NorFlashLib
+ FILE_GUID = f3176a49-dde1-450d-a909-8580c03b9ba8
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NorFlashLib
+
+[Sources.common]
+ NorFlashLib.c
+ CfiNorFlashLib.c
+
+[LibraryClasses]
+ ArmLib
+ TimerLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[Pcd.common]
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 16/39] Silicon/NXP : Add NOR driver.
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (14 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 15/39] Silicon/NXP : Add support of NorFlashLib Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-17 16:23 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 17/39] LS1043 : Enable NOR driver for LS1043aRDB package Meenakshi
` (25 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Add NOR DXE phase driver, it installs BlockIO and Fvp
protocol.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 98 +++
.../NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c | 258 +++++++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c | 438 +++++++++++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h | 146 ++++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf | 66 ++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c | 805 +++++++++++++++++++++
6 files changed, 1811 insertions(+)
create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c
diff --git a/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
new file mode 100644
index 0000000..e254337
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,98 @@
+## @file
+# FDF include file with FD definition that defines an empty variable store.
+#
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+##
+
+[FD.LS1043aRdbNv_EFI]
+BaseAddress = 0x60300000 #The base address of the FLASH device
+Size = 0x000C0000 #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xC0000
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
+DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
+DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE = 0x00040000
+DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE = 0x00040000
+
+#############################################################################
+# LS1043ARDB NVRAM Area
+# LS1043ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#############################################################################
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0xC0000
+ 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0xC2, 0xF9, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
+ 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiAuthenticatedVariableGuid =
+ # { 0xaaf32c78, 0x947b, 0x439a,
+ # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+ # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xFF, 0x03, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
new file mode 100644
index 0000000..efa2197
--- /dev/null
+++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
@@ -0,0 +1,258 @@
+/** @NorFlashBlockIoDxe.c
+
+ Based on NorFlash implementation available in
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
+
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/NorFlashLib.h>
+
+#include <NorFlash.h>
+#include "NorFlashDxe.h"
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReset (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_BLKIO_THIS (This);
+
+ DEBUG ((DEBUG_INFO, "NorFlashBlockIoReset (MediaId=0x%x)\n",
+ This->Media->MediaId));
+
+ return NorFlashPlatformReset (Instance->DeviceBaseAddress);
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReadBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+ EFI_STATUS Status;
+ EFI_BLOCK_IO_MEDIA *Media;
+ UINTN NumBlocks;
+ UINT8 *ReadBuffer;
+ UINTN BlockCount;
+ UINTN BlockSizeInBytes;
+ EFI_LBA CurrentBlock;
+
+ Status = EFI_SUCCESS;
+
+ if ((This == NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Instance = INSTANCE_FROM_BLKIO_THIS (This);
+ Media = This->Media;
+
+ if (Media == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a : Media is NULL\n", __FUNCTION__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ NumBlocks = ((UINTN)BufferSizeInBytes) / Instance->Media.BlockSize ;
+
+ DEBUG ((DEBUG_BLKIO, "%a : (MediaId=0x%x, Lba=%ld, "
+ "BufferSize=0x%x bytes (%d kB)"
+ ", BufferPtr @ 0x%p)\n",
+ __FUNCTION__,MediaId, Lba,
+ BufferSizeInBytes, Buffer));
+
+ if (!Media) {
+ Status = EFI_INVALID_PARAMETER;
+ }
+ else if (!Media->MediaPresent) {
+ Status = EFI_NO_MEDIA;
+ }
+ else if (Media->MediaId != MediaId) {
+ Status = EFI_MEDIA_CHANGED;
+ }
+ else if ((Media->IoAlign >= 2) &&
+ (((UINTN)Buffer & (Media->IoAlign - 1)) != 0)) {
+ Status = EFI_INVALID_PARAMETER;
+ }
+ else if (BufferSizeInBytes == 0) {
+ // Return if we have not any byte to read
+ Status = EFI_SUCCESS;
+ }
+ else if ((BufferSizeInBytes % Media->BlockSize) != 0) {
+ // The size of the buffer must be a multiple of the block size
+ DEBUG ((DEBUG_ERROR, "%a : BlockSize in bytes = 0x%x\n",__FUNCTION__,
+ BufferSizeInBytes));
+ Status = EFI_INVALID_PARAMETER;
+ } else if ((Lba + NumBlocks - 1) > Media->LastBlock) {
+ // All blocks must be within the device
+ DEBUG ((DEBUG_ERROR, "%a : Read will exceed last block %d, %d, %d \n",
+ __FUNCTION__, Lba, NumBlocks, Media->LastBlock));
+ Status = EFI_INVALID_PARAMETER;
+ } else {
+ BlockSizeInBytes = Instance->Media.BlockSize;
+
+ /* Because the target *Buffer is a pointer to VOID,
+ * we must put all the data into a pointer
+ * to a proper data type, so use *ReadBuffer */
+ ReadBuffer = (UINT8 *)Buffer;
+
+ CurrentBlock = Lba;
+ // Read data block by Block
+ for (BlockCount = 0; BlockCount < NumBlocks; BlockCount++, CurrentBlock++,
+ ReadBuffer = ReadBuffer + BlockSizeInBytes) {
+ DEBUG ((DEBUG_BLKIO, "%a: Reading block #%d\n",
+ __FUNCTION__,(UINTN)CurrentBlock));
+
+ Status = NorFlashPlatformRead (Instance, CurrentBlock, (UINTN)0 ,
+ BlockSizeInBytes,ReadBuffer);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ }
+ }
+ DEBUG ((DEBUG_BLKIO,"%a: Exit Status = \"%r\".\n",__FUNCTION__,Status));
+
+ return Status;
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoWriteBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID *Buffer
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+ EFI_STATUS Status;
+ EFI_BLOCK_IO_MEDIA *Media;
+ UINTN NumBlocks;
+ EFI_LBA CurrentBlock;
+ UINTN BlockSizeInBytes;
+ UINT32 BlockCount;
+ UINTN SectorAddress;
+ UINT8 *WriteBuffer;
+
+ Status = EFI_SUCCESS;
+
+ if ((This == NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Instance = INSTANCE_FROM_BLKIO_THIS (This);
+ Media = This->Media;
+
+ if (Media == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a : Media is NULL\n", __FUNCTION__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ NumBlocks = ((UINTN)BufferSizeInBytes) / Instance->Media.BlockSize ;
+
+ DEBUG ((DEBUG_BLKIO, "%a : (MediaId=0x%x, Lba=%ld, BufferSize=0x%x "
+ "bytes (%d kB) BufferPtr @ 0x%08x)\n",
+ __FUNCTION__,MediaId, Lba,BufferSizeInBytes, Buffer));
+
+ if (!Media->MediaPresent) {
+ Status = EFI_NO_MEDIA;
+ }
+ else if (Media->MediaId != MediaId) {
+ Status = EFI_MEDIA_CHANGED;
+ }
+ else if (Media->ReadOnly) {
+ Status = EFI_WRITE_PROTECTED;
+ }
+ else if (BufferSizeInBytes == 0) {
+ Status = EFI_BAD_BUFFER_SIZE;
+ }
+ else if ((BufferSizeInBytes % Media->BlockSize) != 0) {
+ // The size of the buffer must be a multiple of the block size
+ DEBUG ((DEBUG_ERROR, "%a : BlockSize in bytes = 0x%x\n",__FUNCTION__,
+ BufferSizeInBytes));
+ Status = EFI_INVALID_PARAMETER;
+ } else if ((Lba + NumBlocks - 1) > Media->LastBlock) {
+ // All blocks must be within the device
+ DEBUG ((DEBUG_ERROR, "%a: Write will exceed last block %d, %d, %d \n",
+ __FUNCTION__,Lba, NumBlocks, Media->LastBlock));
+ Status = EFI_INVALID_PARAMETER;
+ } else {
+ BlockSizeInBytes = Instance->Media.BlockSize;
+
+ WriteBuffer = (UINT8 *)Buffer;
+
+ CurrentBlock = Lba;
+ // Program data block by Block
+ for (BlockCount = 0; BlockCount < NumBlocks;
+ BlockCount++, CurrentBlock++,
+ WriteBuffer = (WriteBuffer + BlockSizeInBytes)) {
+ DEBUG ((DEBUG_BLKIO, "%a: Writing block #%d\n",
+ __FUNCTION__,(UINTN)CurrentBlock));
+ // Erase the Block(Sector) to be written to
+ SectorAddress = GET_NOR_BLOCK_ADDRESS (
+ Instance->RegionBaseAddress,
+ CurrentBlock,
+ Instance->Media.BlockSize
+ );
+ Status = NorFlashPlatformEraseSector (Instance, (UINTN)SectorAddress);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Failed to erase Target 0x%x (0x%x) \n",
+ __FUNCTION__,SectorAddress, Status));
+ break;
+ }
+ // Program Block(Sector) to be written to
+ Status = NorFlashWrite (Instance, CurrentBlock, (UINTN)0,
+ &BlockSizeInBytes, WriteBuffer);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ }
+ }
+ DEBUG ((DEBUG_BLKIO, "%a: Exit Status = \"%r\".\n",__FUNCTION__,Status));
+ return Status;
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoFlushBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This
+ )
+{
+
+ DEBUG ((DEBUG_BLKIO, "%a NOT IMPLEMENTED (not required)\n", __FUNCTION__));
+
+ // Nothing to do so just return without error
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
new file mode 100644
index 0000000..0e7703c
--- /dev/null
+++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
@@ -0,0 +1,438 @@
+/** @file
+
+ Based on NorFlash implementation available in
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c
+
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Bitops.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NorFlashLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+
+#include "NorFlashDxe.h"
+
+STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent;
+
+//
+// Global variable declarations
+//
+NOR_FLASH_INSTANCE **mNorFlashInstances;
+UINT32 mNorFlashDeviceCount;
+
+NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
+ .Signature = NOR_FLASH_SIGNATURE,
+ .Initialized = FALSE,
+ .Initialize = NULL,
+ .StartLba = 0,
+ .BlockIoProtocol = {
+ .Revision = EFI_BLOCK_IO_PROTOCOL_REVISION2,
+ .Reset = NorFlashBlockIoReset,
+ .ReadBlocks = NorFlashBlockIoReadBlocks,
+ .WriteBlocks = NorFlashBlockIoWriteBlocks,
+ .FlushBlocks = NorFlashBlockIoFlushBlocks,
+ },
+
+ .Media = {
+ .RemovableMedia = FALSE,
+ .MediaPresent = TRUE,
+ .LogicalPartition = FALSE,
+ .ReadOnly = FALSE,
+ .WriteCaching = FALSE,
+ .IoAlign = 4,
+ .LowestAlignedLba = 0,
+ .LogicalBlocksPerPhysicalBlock = 1,
+ },
+
+ .FvbProtocol = {
+ .GetAttributes = FvbGetAttributes,
+ .SetAttributes = FvbSetAttributes,
+ .GetPhysicalAddress = FvbGetPhysicalAddress,
+ .GetBlockSize = FvbGetBlockSize,
+ .Read = FvbRead,
+ .Write = FvbWrite,
+ .EraseBlocks = FvbEraseBlocks,
+ .ParentHandle = NULL,
+ },
+ .ShadowBuffer = NULL,
+ .DevicePath = {
+ .Vendor = {
+ .Header = {
+ .Type = HARDWARE_DEVICE_PATH,
+ .SubType = HW_VENDOR_DP,
+ .Length = {(UINT8)sizeof (VENDOR_DEVICE_PATH),
+ (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) }
+ },
+ .Guid = EFI_CALLER_ID_GUID, // GUID ... NEED TO BE FILLED
+ },
+ .End = {
+ .Type = END_DEVICE_PATH_TYPE,
+ .SubType = END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ .Length = { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
+ }
+ }
+};
+
+EFI_STATUS
+NorFlashCreateInstance (
+ IN UINTN NorFlashDeviceBase,
+ IN UINTN NorFlashRegionBase,
+ IN UINTN NorFlashSize,
+ IN UINT32 MediaId,
+ IN UINT32 BlockSize,
+ IN BOOLEAN SupportFvb,
+ OUT NOR_FLASH_INSTANCE** NorFlashInstance
+ )
+{
+ EFI_STATUS Status;
+ NOR_FLASH_INSTANCE* Instance;
+
+ ASSERT (NorFlashInstance != NULL);
+
+ Instance = AllocateRuntimeCopyPool (sizeof (NOR_FLASH_INSTANCE),
+ &mNorFlashInstanceTemplate);
+ if (Instance == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Instance->DeviceBaseAddress = NorFlashDeviceBase;
+ Instance->RegionBaseAddress = NorFlashRegionBase;
+ Instance->Size = NorFlashSize;
+
+ Instance->BlockIoProtocol.Media = &Instance->Media;
+ Instance->Media.MediaId = MediaId;
+ Instance->Media.BlockSize = BlockSize;
+ Instance->Media.LastBlock = (NorFlashSize / BlockSize)-1;
+
+ Instance->ShadowBuffer = AllocateRuntimePool (BlockSize);
+ if (Instance->ShadowBuffer == NULL) {
+ FreePool (Instance);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ if (SupportFvb) {
+ Instance->SupportFvb = TRUE;
+ Instance->Initialize = NorFlashFvbInitialize;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Instance->Handle,
+ &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
+ &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol,
+ &gEfiFirmwareVolumeBlockProtocolGuid, &Instance->FvbProtocol,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ FreePool (Instance->ShadowBuffer);
+ FreePool (Instance);
+ return Status;
+ }
+ } else {
+ Instance->Initialized = TRUE;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Instance->Handle,
+ &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
+ &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ FreePool (Instance->ShadowBuffer);
+ FreePool (Instance);
+ return Status;
+ }
+ }
+
+ *NorFlashInstance = Instance;
+
+ return Status;
+}
+
+/*
+ Write a full or portion of a block.
+ It must not span block boundaries; that is,
+ Offset + NumBytes <= Instance->Media.BlockSize.
+ */
+EFI_STATUS
+NorFlashWrite (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+)
+{
+ EFI_STATUS Status;
+ UINTN BlockSize;
+ BOOLEAN DoErase;
+ VOID *Source;
+ UINTN SectorAddress;
+
+ Status = EFI_SUCCESS;
+ Source = NULL;
+
+ DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=%ld, Offset=0x%x, NumBytes=0x%x, "
+ "Buffer @ 0x%08x)\n", __FUNCTION__,
+ Lba, Offset, *NumBytes, Buffer));
+
+ // The buffer must be valid
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Detect WriteDisabled state
+ if (Instance->Media.ReadOnly == TRUE) {
+ DEBUG ((DEBUG_ERROR, "NorFlashWrite: ERROR - Can not write: "
+ "Device is in WriteDisabled state.\n"));
+ // It is in WriteDisabled state, return an error right away
+ return EFI_ACCESS_DENIED;
+ }
+
+ // Cache the block size to avoid de-referencing pointers all the time
+ BlockSize = Instance->Media.BlockSize;
+
+ // We must have some bytes to write
+ if ((*NumBytes == 0) || (*NumBytes > BlockSize)) {
+ DEBUG ((DEBUG_ERROR, "NorFlashWrite: ERROR - EFI_BAD_BUFFER_SIZE: "
+ "(Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", \
+ Offset, *NumBytes, BlockSize ));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ if (((Lba * BlockSize) + Offset + *NumBytes) > Instance->Size) {
+ DEBUG ((DEBUG_ERROR, "%a: ERROR - Write will exceed device size.\n",
+ __FUNCTION__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Check we did get some memory. Buffer is BlockSize.
+ if (Instance->ShadowBuffer == NULL) {
+ DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - Buffer not ready\n"));
+ return EFI_DEVICE_ERROR;
+ }
+
+ SectorAddress = GET_NOR_BLOCK_ADDRESS (
+ Instance->RegionBaseAddress,
+ Lba,
+ Instance->Media.BlockSize);
+
+ // Pick 128bytes as a good start for word operations as opposed to erasing the
+ // block and writing the data regardless if an erase is really needed.
+ // It looks like most individual NV variable writes are smaller than 128bytes.
+ if (*NumBytes <= 128) {
+ Source = Instance->ShadowBuffer;
+ //First Read the data into shadow buffer from location where data is to be written
+ Status = NorFlashPlatformRead (
+ Instance,
+ Lba,
+ Offset,
+ *NumBytes,
+ Source);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: ERROR - Failed to "
+ "Read @ %p Status=%d\n", __FUNCTION__,
+ Offset + SectorAddress, Status));
+ return Status;
+ }
+ // Check to see if we need to erase before programming the data into NorFlash.
+ // If the destination bits are only changing from 1s to 0s we can
+ // just write. After a block is erased all bits in the block is set to 1.
+ // If any byte requires us to erase we just give up and rewrite all of it.
+ DoErase = TestBitSetClear (Source, Buffer, *NumBytes, TRUE);
+
+ // if we got here then write all the data. Otherwise do the
+ // Erase-Write cycle.
+ if (!DoErase) {
+ Status = NorFlashPlatformWriteBuffer (
+ Instance,
+ Lba,
+ Offset,
+ NumBytes,
+ Buffer);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: ERROR - Failed to "
+ "Write @ %p Status=%d\n", __FUNCTION__,
+ Offset + SectorAddress, Status));
+ return Status;
+ }
+ return EFI_SUCCESS;
+ }
+ }
+
+ // If we are not going to write full block, read block and then update bytes in it
+ if (*NumBytes != BlockSize) {
+ // Read NorFlash Flash data into shadow buffer
+ Status = NorFlashBlockIoReadBlocks (
+ &(Instance->BlockIoProtocol),
+ Instance->Media.MediaId,
+ Lba,
+ BlockSize,
+ Instance->ShadowBuffer);
+ if (EFI_ERROR (Status)) {
+ // Return one of the pre-approved error statuses
+ return EFI_DEVICE_ERROR;
+ }
+ // Put the data at the appropriate location inside the buffer area
+ CopyMem ((VOID *)((UINTN)Instance->ShadowBuffer + Offset), Buffer, *NumBytes);
+ }
+ //Erase Block
+ Status = NorFlashPlatformEraseSector (Instance, SectorAddress);
+ if (EFI_ERROR (Status)) {
+ // Return one of the pre-approved error statuses
+ return EFI_DEVICE_ERROR;
+ }
+ if (*NumBytes != BlockSize) {
+ // Write the modified shadow buffer back to the NorFlash
+ Status = NorFlashPlatformWriteBuffer (
+ Instance,
+ Lba,
+ 0,
+ &BlockSize,
+ Instance->ShadowBuffer);
+ } else {
+ // Write the Buffer to an entire block in NorFlash
+ Status = NorFlashPlatformWriteBuffer (
+ Instance,
+ Lba,
+ 0,
+ &BlockSize,
+ Buffer);
+ }
+ if (EFI_ERROR (Status)) {
+ // Return one of the pre-approved error statuses
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+NorFlashVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINTN Index;
+
+ for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->DeviceBaseAddress);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->RegionBaseAddress);
+
+ // Convert BlockIo protocol
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.FlushBlocks);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.ReadBlocks);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.Reset);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.WriteBlocks);
+
+ // Convert Fvb
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.EraseBlocks);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetAttributes);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetBlockSize);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetPhysicalAddress);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Read);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.SetAttributes);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Write);
+ if (mNorFlashInstances[Index]->ShadowBuffer != NULL) {
+ EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->ShadowBuffer);
+ }
+ }
+
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+NorFlashInitialise (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Index;
+ NorFlashDescription* NorFlashDevices;
+ BOOLEAN ContainVariableStorage;
+
+ ContainVariableStorage = 0;
+
+ Status = NorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashDeviceCount);
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "%a : Failed to get Nor devices (0x%x)\n",
+ __FUNCTION__, Status));
+ return Status;
+ }
+
+ Status = NorFlashPlatformFlashGetAttributes (NorFlashDevices, mNorFlashDeviceCount);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a : Failed to get NOR device attributes (0x%x)\n",
+ __FUNCTION__, Status));
+ ASSERT_EFI_ERROR (Status); // System becomes unusable if NOR flash is not detected
+ return Status;
+ }
+
+ mNorFlashInstances = AllocateRuntimePool (
+ sizeof(NOR_FLASH_INSTANCE*) * mNorFlashDeviceCount);
+ if (mNorFlashInstances == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a : Failed to allocate runtime memory \n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
+ // Check if this NOR Flash device contain the variable storage region
+ ContainVariableStorage =
+ (NorFlashDevices[Index].RegionBaseAddress <= PcdGet64 (PcdFlashNvStorageVariableBase64)) &&
+ (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvStorageVariableSize) <=
+ NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size);
+
+ Status = NorFlashCreateInstance (
+ NorFlashDevices[Index].DeviceBaseAddress,
+ NorFlashDevices[Index].RegionBaseAddress,
+ NorFlashDevices[Index].Size,
+ Index,
+ NorFlashDevices[Index].BlockSize,
+ ContainVariableStorage,
+ &mNorFlashInstances[Index]);
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a : Failed to create instance for "
+ "NorFlash[%d] (0x%x)\n",Index, Status));
+ }
+ }
+
+ //
+ // Register for the virtual address change event
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ NorFlashVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mNorFlashVirtualAddrChangeEvent);
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to create VirtualAddressChange event 0x%x\n", Status));
+ }
+
+ return Status;
+}
diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
new file mode 100644
index 0000000..24504f2
--- /dev/null
+++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
@@ -0,0 +1,146 @@
+/** @NorFlashDxe.h
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __NOR_FLASH_DXE_H__
+#define __NOR_FLASH_DXE_H__
+
+#include <Protocol/BlockIo.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+
+#define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize) ( BaseAddr + (UINTN)((Lba) * LbaSize) )
+
+#define NOR_FLASH_SIGNATURE SIGNATURE_32('n', 'o', 'r', '0')
+
+#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, NOR_FLASH_SIGNATURE)
+
+#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, BlockIoProtocol, NOR_FLASH_SIGNATURE)
+
+EFI_STATUS
+EFIAPI
+NorFlashFvbInitialize (
+ IN NOR_FLASH_INSTANCE* Instance
+ );
+
+EFI_STATUS
+EFIAPI
+FvbGetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+FvbSetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+FvbGetPhysicalAddress(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
+ );
+
+EFI_STATUS
+EFIAPI
+FvbGetBlockSize(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumberOfBlocks
+ );
+
+EFI_STATUS
+EFIAPI
+FvbRead(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN OUT UINT8 *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+FvbWrite(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+FvbEraseBlocks(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ ...
+ );
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReset (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
+ );
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReadBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+);
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoWriteBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID *Buffer
+);
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoFlushBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This
+);
+
+EFI_STATUS
+NorFlashWrite (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+);
+
+#endif /* __NOR_FLASH_DXE_H__ */
diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
new file mode 100644
index 0000000..4081619
--- /dev/null
+++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
@@ -0,0 +1,66 @@
+# @file
+#
+# Component description file for NorFlashDxe module
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = NorFlashDxe
+ FILE_GUID = 616fe8d8-f4aa-42e0-a393-b332bdb2d3c1
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = NorFlashInitialise
+
+[Sources.common]
+ NorFlashDxe.c
+ NorFlashFvbDxe.c
+ NorFlashBlockIoDxe.c
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ DxeServicesTableLib
+ HobLib
+ NorFlashLib
+ UefiDriverEntryPoint
+ UefiRuntimeLib
+
+[Guids]
+ gEfiSystemNvDataFvGuid
+ gEfiVariableGuid
+ gEfiAuthenticatedVariableGuid
+ gEfiEventVirtualAddressChangeGuid
+
+[Protocols]
+ gEfiBlockIoProtocolGuid
+ gEfiFirmwareVolumeBlockProtocolGuid
+
+[Pcd.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize
+
+[Depex]
+ #
+ # NorFlashDxe must be loaded before VariableRuntimeDxe in case empty flash needs populating with default values
+ #
+ BEFORE gVariableRuntimeDxeFileGuid
diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c
new file mode 100644
index 0000000..378546d
--- /dev/null
+++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c
@@ -0,0 +1,805 @@
+/** @NorFlashFvbDxe.c
+
+ Based on NorFlash implementation available in
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvbDxe.c
+
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Guid/VariableFormat.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NorFlashLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeLib.h>
+
+#include <NorFlash.h>
+#include "NorFlashDxe.h"
+
+STATIC EFI_EVENT mFvbVirtualAddrChangeEvent;
+STATIC UINTN mFlashNvStorageVariableBase;
+
+///
+/// The Firmware Volume Block Protocol is the low-level interface
+/// to a firmware volume. File-level access to a firmware volume
+/// should not be done using the Firmware Volume Block Protocol.
+/// Normal access to a firmware volume must use the Firmware
+/// Volume Protocol. Typically, only the file system driver that
+/// produces the Firmware Volume Protocol will bind to the
+/// Firmware Volume Block Protocol.
+///
+
+/**
+ Initialises the FV Header and Variable Store Header
+ to support variable operations.
+
+ @param[in] Ptr - Location to initialise the headers
+
+**/
+EFI_STATUS
+InitializeFvAndVariableStoreHeaders (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ EFI_STATUS Status;
+ VOID* Headers;
+ UINTN HeadersLength;
+ EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader;
+ VARIABLE_STORE_HEADER *VariableStoreHeader;
+
+ if (!Instance->Initialized && Instance->Initialize) {
+ Instance->Initialize (Instance);
+ }
+
+ HeadersLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY) + sizeof (VARIABLE_STORE_HEADER);
+ Headers = AllocateZeroPool (HeadersLength);
+ if (Headers == NULL) {
+ DEBUG ((DEBUG_ERROR, "Memory allocation failed for Headers \n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ // FirmwareVolumeHeader->FvLength is declared to have the Variable area AND the FTW working area AND the FTW Spare contiguous.
+ ASSERT (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvStorageVariableSize) == PcdGet64 (PcdFlashNvStorageFtwWorkingBase64));
+ ASSERT (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) == PcdGet64 (PcdFlashNvStorageFtwSpareBase64));
+
+ // Check if the size of the area is at least one block size
+ ASSERT ((PcdGet32 (PcdFlashNvStorageVariableSize) > 0) && (PcdGet32 (PcdFlashNvStorageVariableSize) / Instance->Media.BlockSize > 0));
+ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingSize) > 0) && (PcdGet32 (PcdFlashNvStorageFtwWorkingSize) / Instance->Media.BlockSize > 0));
+ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareSize) > 0) && (PcdGet32 (PcdFlashNvStorageFtwSpareSize) / Instance->Media.BlockSize > 0));
+
+ // Ensure the Variable area Base Addresses are aligned on a block size boundaries
+ ASSERT (PcdGet64 (PcdFlashNvStorageVariableBase64) % Instance->Media.BlockSize == 0);
+ ASSERT (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) % Instance->Media.BlockSize == 0);
+ ASSERT (PcdGet64 (PcdFlashNvStorageFtwSpareBase64) % Instance->Media.BlockSize == 0);
+
+ //
+ // EFI_FIRMWARE_VOLUME_HEADER
+ //
+ FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers;
+ CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid);
+ FirmwareVolumeHeader->FvLength =
+ PcdGet32 (PcdFlashNvStorageVariableSize) +
+ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ PcdGet32 (PcdFlashNvStorageFtwSpareSize);
+ FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE;
+ FirmwareVolumeHeader->Attributes = (EFI_FVB_ATTRIBUTES_2) (
+ EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
+ EFI_FVB2_READ_STATUS | // Reads are currently enabled
+ EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
+ EFI_FVB2_ERASE_POLARITY | // After erasure all bits take this value (i.e. '1')
+ EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
+ EFI_FVB2_WRITE_ENABLED_CAP // Writes may be enabled
+ );
+ FirmwareVolumeHeader->HeaderLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY);
+ FirmwareVolumeHeader->Revision = EFI_FVH_REVISION;
+ //i.e. if blocks are 0-5 then last block = 5, total blocks = 6
+ FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->Media.LastBlock + 1;
+ FirmwareVolumeHeader->BlockMap[0].Length = Instance->Media.BlockSize;
+ FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0;
+ FirmwareVolumeHeader->BlockMap[1].Length = 0;
+ FirmwareVolumeHeader->Checksum = CalculateCheckSum16 ((UINT16*)FirmwareVolumeHeader,FirmwareVolumeHeader->HeaderLength);
+
+ //
+ // VARIABLE_STORE_HEADER
+ //
+ VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)Headers + FirmwareVolumeHeader->HeaderLength);
+ CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid);
+ VariableStoreHeader->Size = PcdGet32(PcdFlashNvStorageVariableSize) - FirmwareVolumeHeader->HeaderLength;
+ VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED;
+ VariableStoreHeader->State = VARIABLE_STORE_HEALTHY;
+
+ // Install the combined super-header in the NorFlash
+ Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers);
+
+ FreePool (Headers);
+ return Status;
+}
+
+/**
+ Check the integrity of firmware volume header.
+
+ @param[in] FwVolHeader - A pointer to a firmware volume header
+
+ @retval EFI_SUCCESS - The firmware volume is consistent
+ @retval EFI_NOT_FOUND - The firmware volume has been corrupted.
+
+**/
+EFI_STATUS
+ValidateFvHeader (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ UINT16 Checksum;
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
+ VARIABLE_STORE_HEADER *VariableStoreHeader;
+ UINTN VariableStoreLength;
+ UINTN FvLength;
+
+ FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER*)mFlashNvStorageVariableBase;
+
+ FvLength = PcdGet32 (PcdFlashNvStorageVariableSize) + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ PcdGet32 (PcdFlashNvStorageFtwSpareSize);
+
+ //
+ // Verify the header revision, header signature, length
+ // Length of FvBlock cannot be 2**64-1
+ // HeaderLength cannot be an odd number
+ //
+ if ((FwVolHeader->Revision != EFI_FVH_REVISION)
+ || (FwVolHeader->Signature != EFI_FVH_SIGNATURE)
+ || (FwVolHeader->FvLength != FvLength)) {
+ DEBUG ((DEBUG_ERROR, "%a: No Firmware Volume header present\n", __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ // Check the Firmware Volume Guid
+ if (CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid) == FALSE ) {
+ DEBUG ((DEBUG_ERROR, "%a: Firmware Volume Guid non-compatible\n", __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ // Verify the header checksum
+ Checksum = CalculateSum16 ((UINT16*)FwVolHeader, FwVolHeader->HeaderLength);
+ if (Checksum != 0) {
+ DEBUG ((DEBUG_ERROR, "%a: FV checksum is invalid (Checksum:0x%X)\n", __FUNCTION__, Checksum));
+ return EFI_NOT_FOUND;
+ }
+
+ VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)FwVolHeader +
+ FwVolHeader->HeaderLength);
+
+ // Check the Variable Store Guid
+ if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) &&
+ !CompareGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid)) {
+ DEBUG ((DEBUG_ERROR, "%a: Variable Store Guid non-compatible\n",
+ __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) - FwVolHeader->HeaderLength;
+ if (VariableStoreHeader->Size != VariableStoreLength) {
+ DEBUG ((DEBUG_ERROR, "%a: Variable Store Length does not match\n", __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ The GetAttributes() function retrieves the attributes and
+ current settings of the block.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and
+ current settings are returned.
+ Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+**/
+EFI_STATUS
+EFIAPI
+FvbGetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes;
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS (This);
+
+ FlashFvbAttributes = (EFI_FVB_ATTRIBUTES_2) (
+ EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
+ EFI_FVB2_READ_STATUS | // Reads are currently enabled
+ EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
+ EFI_FVB2_ERASE_POLARITY // After erasure all bits take this value (i.e. '1')
+ );
+
+ // Check if it is write protected
+ if (Instance->Media.ReadOnly != TRUE) {
+ FlashFvbAttributes = FlashFvbAttributes |
+ EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
+ EFI_FVB2_WRITE_ENABLED_CAP; // Writes may be enabled
+ }
+
+ *Attributes = FlashFvbAttributes;
+
+ DEBUG ((DEBUG_BLKIO, "FvbGetAttributes(0x%X)\n", *Attributes));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ The SetAttributes() function sets configurable firmware volume attributes
+ and returns the new settings of the firmware volume.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes On input, Attributes is a pointer to EFI_FVB_ATTRIBUTES_2
+ that contains the desired firmware volume settings.
+ On successful return, it contains the new settings of
+ the firmware volume.
+ Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+ @retval EFI_INVALID_PARAMETER The attributes requested are in conflict with the capabilities
+ as declared in the firmware volume header.
+
+**/
+EFI_STATUS
+EFIAPI
+FvbSetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ DEBUG ((DEBUG_BLKIO, "FvbSetAttributes(0x%X) is not supported\n",*Attributes));
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ The GetPhysicalAddress() function retrieves the base address of
+ a memory-mapped firmware volume. This function should be called
+ only for memory-mapped firmware volumes.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Address Pointer to a caller-allocated
+ EFI_PHYSICAL_ADDRESS that, on successful
+ return from GetPhysicalAddress(), contains the
+ base address of the firmware volume.
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped.
+
+**/
+EFI_STATUS
+EFIAPI
+FvbGetPhysicalAddress (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
+ )
+{
+ *Address = mFlashNvStorageVariableBase;
+ return EFI_SUCCESS;
+}
+
+/**
+ The GetBlockSize() function retrieves the size of the requested
+ block. It also returns the number of additional blocks with
+ the identical size. The GetBlockSize() function is used to
+ retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba Indicates the block for which to return the size.
+
+ @param BlockSize Pointer to a caller-allocated UINTN in which
+ the size of the block is returned.
+
+ @param NumberOfBlocks Pointer to a caller-allocated UINTN in
+ which the number of consecutive blocks,
+ starting with Lba, is returned. All
+ blocks in this range have a size of
+ BlockSize.
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range.
+
+**/
+EFI_STATUS
+EFIAPI
+FvbGetBlockSize (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumberOfBlocks
+ )
+{
+ EFI_STATUS Status;
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS (This);
+
+ DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize(Lba=%ld, BlockSize=0x%x, LastBlock=%ld)\n",
+ Lba, Instance->Media.BlockSize, Instance->Media.LastBlock));
+
+ if (Lba > Instance->Media.LastBlock) {
+ DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%ld)\n",
+ __FUNCTION__, Lba, Instance->Media.LastBlock));
+ Status = EFI_INVALID_PARAMETER;
+ } else {
+ // In this platform each NorFlash device has equal sized blocks.
+ *BlockSize = (UINTN) Instance->Media.BlockSize;
+ *NumberOfBlocks = (UINTN) (Instance->Media.LastBlock - Lba + 1);
+
+ DEBUG ((DEBUG_BLKIO, "%a : *BlockSize=0x%x, *NumberOfBlocks=0x%x.\n",
+ __FUNCTION__, *BlockSize, *NumberOfBlocks));
+
+ Status = EFI_SUCCESS;
+ }
+
+ return Status;
+}
+
+/**
+ Reads the specified number of bytes into a buffer from the specified block.
+
+ The Read() function reads the requested number of bytes from the
+ requested block and stores them in the provided buffer.
+ Implementations should be mindful that the firmware volume
+ might be in the ReadDisabled state. If it is in this state,
+ the Read() function must return the status code
+ EFI_ACCESS_DENIED without modifying the contents of the
+ buffer. The Read() function must also prevent spanning block
+ boundaries. If a read is requested that would span a block
+ boundary, the read must read up to the boundary but not
+ beyond. The output parameter NumBytes must be set to correctly
+ indicate the number of bytes actually read. The caller must be
+ aware that a read may be partially completed.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index from which to read.
+
+ @param Offset Offset into the block at which to begin reading.
+
+ @param NumBytes Pointer to a UINTN.
+ At entry, *NumBytes contains the total size of the buffer.
+ At exit, *NumBytes contains the total number of bytes read.
+
+ @param Buffer Pointer to a caller-allocated buffer that will be used
+ to hold the data that is read.
+
+ @retval EFI_SUCCESS The firmware volume was read successfully, and contents are
+ in Buffer.
+
+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary.
+ On output, NumBytes contains the total number of bytes
+ returned in Buffer.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be read.
+
+**/
+EFI_STATUS
+EFIAPI
+FvbRead (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN OUT UINT8 *Buffer
+ )
+{
+ UINTN BlockSize;
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS (This);
+
+ DEBUG ((DEBUG_BLKIO, "FvbRead(Parameters: Lba=%ld, Offset=0x%x, "
+ "*NumBytes=0x%x, Buffer @ 0x%08x)\n",
+ Instance->StartLba + Lba, Offset, *NumBytes, Buffer));
+
+ if (!Instance->Initialized && Instance->Initialize) {
+ Instance->Initialize(Instance);
+ }
+
+ // Cache the block size to avoid de-referencing pointers all the time
+ BlockSize = Instance->Media.BlockSize;
+
+ DEBUG ((DEBUG_BLKIO, "FvbRead: Check if (Offset=0x%x + NumBytes=0x%x) <= "
+ "BlockSize=0x%x\n", Offset, *NumBytes, BlockSize ));
+
+ // The read must not span block boundaries.
+ while (Offset >= BlockSize) {
+ Offset -= BlockSize;
+ Lba++;
+ }
+
+ if ((Instance->StartLba + Lba) > Instance->Media.LastBlock) {
+ DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%ld)\n",
+ __FUNCTION__, Lba, Instance->Media.LastBlock));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((Offset + *NumBytes) > BlockSize) {
+ *NumBytes = BlockSize-Offset;
+ }
+
+ return NorFlashPlatformRead (Instance, Instance->StartLba + Lba,
+ Offset, *NumBytes, Buffer);
+}
+
+/**
+ Writes the specified number of bytes from the input buffer to the block.
+
+ The Write() function writes the specified number of bytes from
+ the provided buffer to the specified block and offset. If the
+ firmware volume is sticky write, the caller must ensure that
+ all the bits of the specified range to write are in the
+ EFI_FVB_ERASE_POLARITY state before calling the Write()
+ function, or else the result will be unpredictable. This
+ unpredictability arises because, for a sticky-write firmware
+ volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
+ state but cannot flip it back again. Before calling the
+ Write() function, it is recommended for the caller to first call
+ the EraseBlocks() function to erase the specified block to
+ write. A block erase cycle will transition bits from the
+ (NOT)EFI_FVB_ERASE_POLARITY state back to the
+ EFI_FVB_ERASE_POLARITY state. Implementations should be
+ mindful that the firmware volume might be in the WriteDisabled
+ state. If it is in this state, the Write() function must
+ return the status code EFI_ACCESS_DENIED without modifying the
+ contents of the firmware volume. The Write() function must
+ also prevent spanning block boundaries. If a write is
+ requested that spans a block boundary, the write must store up
+ to the boundary but not beyond. The output parameter NumBytes
+ must be set to correctly indicate the number of bytes actually
+ written. The caller must be aware that a write may be
+ partially completed. All writes, partial or otherwise, must be
+ fully flushed to the hardware before the Write() service
+ returns.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index to write to.
+
+ @param Offset Offset into the block at which to begin writing.
+
+ @param NumBytes The pointer to a UINTN.
+ At entry, *NumBytes contains the total size of the buffer.
+ At exit, *NumBytes contains the total number of bytes actually written.
+
+ @param Buffer The pointer to a caller-allocated buffer that contains the source for the write.
+
+ @retval EFI_SUCCESS The firmware volume was written successfully.
+
+ @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA boundary.
+ On output, NumBytes contains the total number of bytes
+ actually written.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is malfunctioning and could not be written.
+
+**/
+EFI_STATUS
+EFIAPI
+FvbWrite (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+ UINTN BlockSize;
+
+ Instance = INSTANCE_FROM_FVB_THIS (This);
+ // Cache the block size to avoid de-referencing pointers all the time
+ BlockSize = Instance->Media.BlockSize;
+
+ if (!Instance->Initialized && Instance->Initialize) {
+ Instance->Initialize(Instance);
+ }
+
+ // The write must not span block boundaries.
+ while(Offset >= BlockSize) {
+ Offset -= BlockSize;
+ Lba++;
+ }
+
+ if ((Instance->StartLba + Lba) > Instance->Media.LastBlock) {
+ DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%ld)\n",
+ __FUNCTION__, Lba, Instance->Media.LastBlock));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((Offset + *NumBytes) > BlockSize) {
+ *NumBytes = BlockSize-Offset;
+ }
+
+ return NorFlashWrite (Instance, Instance->StartLba + Lba,
+ Offset, NumBytes, Buffer);
+}
+
+/**
+ Erases and initialises a firmware volume block.
+
+ The EraseBlocks() function erases one or more blocks as denoted
+ by the variable argument list. The entire parameter list of
+ blocks must be verified before erasing any blocks. If a block is
+ requested that does not exist within the associated firmware
+ volume (it has a larger index than the last block of the
+ firmware volume), the EraseBlocks() function must return the
+ status code EFI_INVALID_PARAMETER without modifying the contents
+ of the firmware volume. Implementations should be mindful that
+ the firmware volume might be in the WriteDisabled state. If it
+ is in this state, the EraseBlocks() function must return the
+ status code EFI_ACCESS_DENIED without modifying the contents of
+ the firmware volume. All calls to EraseBlocks() must be fully
+ flushed to the hardware before the EraseBlocks() service
+ returns.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
+ instance.
+
+ @param ... The variable argument list is a list of tuples.
+ Each tuple describes a range of LBAs to erase
+ and consists of the following:
+ - An EFI_LBA that indicates the starting LBA
+ - A UINTN that indicates the number of blocks to erase.
+
+ The list is terminated with an EFI_LBA_LIST_TERMINATOR.
+ For example, the following indicates that two ranges of blocks
+ (5-7 and 10-11) are to be erased:
+ EraseBlocks (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR);
+
+ @retval EFI_SUCCESS The erase request successfully completed.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be written.
+ The firmware device may have been partially erased.
+
+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable argument list do
+ not exist in the firmware volume.
+
+**/
+EFI_STATUS
+EFIAPI
+FvbEraseBlocks (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ ...
+ )
+{
+ EFI_STATUS Status;
+ VA_LIST Args;
+ UINTN BlockAddress; // Physical address of Lba to erase
+ EFI_LBA StartingLba; // Lba from which we start erasing
+ UINTN NumOfLba; // Number of Lba blocks to erase
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS (This);
+
+ DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks()\n"));
+
+ Status = EFI_SUCCESS;
+
+ // Detect WriteDisabled state
+ if (Instance->Media.ReadOnly == TRUE) {
+ // Firmware volume is in WriteDisabled state
+ DEBUG ((DEBUG_ERROR, "%a : Device is in WriteDisabled state\n"));
+ return EFI_ACCESS_DENIED;
+ }
+
+ // Before erasing, check the entire list of parameters to
+ // ensure all specified blocks are valid
+
+ VA_START (Args, This);
+ do {
+ // Get the Lba from which we start erasing
+ StartingLba = VA_ARG (Args, EFI_LBA);
+
+ // Have we reached the end of the list?
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
+ //Exit the while loop
+ break;
+ }
+
+ // How many Lba blocks are we requested to erase?
+ NumOfLba = VA_ARG (Args, UINT32);
+
+ // All blocks must be within range
+ DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Check if: ( StartingLba=%ld + "
+ "NumOfLba=%d - 1 ) > LastBlock=%ld.\n",
+ Instance->StartLba + StartingLba, NumOfLba,
+ Instance->Media.LastBlock));
+ if ((NumOfLba == 0) ||
+ ((Instance->StartLba + StartingLba + NumOfLba - 1) >
+ Instance->Media.LastBlock)) {
+ VA_END (Args);
+ DEBUG ((DEBUG_ERROR, "%a : Lba range goes past the last Lba\n"));
+ Status = EFI_INVALID_PARAMETER;
+ goto EXIT;
+ }
+ } while (TRUE);
+ VA_END (Args);
+
+ //
+ // To get here, all must be ok, so start erasing
+ //
+ VA_START (Args, This);
+ do {
+ // Get the Lba from which we start erasing
+ StartingLba = VA_ARG (Args, EFI_LBA);
+
+ // Have we reached the end of the list?
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
+ // Exit the while loop
+ break;
+ }
+
+ // How many Lba blocks are we requested to erase?
+ NumOfLba = VA_ARG (Args, UINT32);
+
+ // Go through each one and erase it
+ while (NumOfLba > 0) {
+ // Get the physical address of Lba to erase
+ BlockAddress = GET_NOR_BLOCK_ADDRESS (
+ Instance->RegionBaseAddress,
+ Instance->StartLba + StartingLba,
+ Instance->Media.BlockSize
+ );
+
+ // Erase it
+ DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Erasing Lba=%ld @ 0x%08x.\n",
+ Instance->StartLba + StartingLba, BlockAddress));
+ Status = NorFlashPlatformEraseSector(Instance, BlockAddress);
+ if (EFI_ERROR (Status)) {
+ VA_END (Args);
+ Status = EFI_DEVICE_ERROR;
+ goto EXIT;
+ }
+
+ // Move to the next Lba
+ StartingLba++;
+ NumOfLba--;
+ }
+ } while (TRUE);
+ VA_END (Args);
+
+EXIT:
+ return Status;
+}
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+FvbVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase);
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+NorFlashFvbInitialize (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ EFI_STATUS Status;
+ UINT32 FvbNumLba;
+ EFI_BOOT_MODE BootMode;
+ UINTN RuntimeMmioRegionSize;
+
+ DEBUG ((DEBUG_BLKIO, "NorFlashFvbInitialize\n"));
+
+ Instance->Initialized = TRUE;
+ mFlashNvStorageVariableBase = FixedPcdGet64 (PcdFlashNvStorageVariableBase64);
+
+ // Set the index of the first LBA for the FVB
+ Instance->StartLba = (PcdGet64 (PcdFlashNvStorageVariableBase64) - Instance->RegionBaseAddress) / Instance->Media.BlockSize;
+
+ BootMode = GetBootModeHob ();
+ if (BootMode == BOOT_WITH_DEFAULT_SETTINGS) {
+ Status = EFI_INVALID_PARAMETER;
+ } else {
+ // Determine if there is a valid header at the beginning of the NorFlash
+ Status = ValidateFvHeader (Instance);
+ }
+
+ // Install the Default FVB header if required
+ if (EFI_ERROR (Status)) {
+ // There is no valid header, so time to install one.
+ DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Installing a correct one for this volume.\n",
+ __FUNCTION__));
+
+ // Erase all the NorFlash that is reserved for variable storage
+ FvbNumLba = (PcdGet32 (PcdFlashNvStorageVariableSize) +
+ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / Instance->Media.BlockSize;
+
+ Status = FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumLba, EFI_LBA_LIST_TERMINATOR);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Install all appropriate headers
+ Status = InitializeFvAndVariableStoreHeaders (Instance);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ //
+ // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME
+ //
+
+ // Note: all the NOR Flash region needs to be reserved into the UEFI Runtime memory;
+ // even if we only use the small block region at the top of the NOR Flash.
+ // The reason is when the NOR Flash memory is set into program mode, the command
+ // is written as the base of the flash region (ie: Instance->DeviceBaseAddress)
+ RuntimeMmioRegionSize = (Instance->RegionBaseAddress - Instance->DeviceBaseAddress) + Instance->Size;
+
+ Status = gDS->AddMemorySpace (
+ EfiGcdMemoryTypeMemoryMappedIo,
+ Instance->DeviceBaseAddress, RuntimeMmioRegionSize,
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gDS->SetMemorySpaceAttributes (
+ Instance->DeviceBaseAddress, RuntimeMmioRegionSize,
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register for the virtual address change event
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ FvbVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mFvbVirtualAddrChangeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 17/39] LS1043 : Enable NOR driver for LS1043aRDB package.
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (15 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 16/39] Silicon/NXP : Add NOR driver Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 9:54 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 18/39] Silicon/NXP:Add LS1046ARDB SoCLib Support Meenakshi
` (24 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 16 +++++++++++++++-
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 9 ++++++++-
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index df4d917..7708e0a 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -41,6 +41,7 @@
IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
FpgaLib|Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
+ NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
[PcdsFixedAtBuild.common]
@@ -70,6 +71,13 @@
gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
+ #
+ # NV Storage PCDs.
+ #
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
@@ -79,9 +87,15 @@
#
# Architectural Protocols
#
- MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf{
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ }
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+ Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
##
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index fa6510c..6b5b63f 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -55,6 +55,7 @@ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
!include ../FVRules.fdf.inc
+!include VarStore.fdf.inc
################################################################################
#
# FV Section
@@ -103,7 +104,8 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -123,6 +125,11 @@ READ_LOCK_STATUS = TRUE
INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
#
+ # NOR Driver
+ #
+ INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+ #
# Network modules
#
INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 18/39] Silicon/NXP:Add LS1046ARDB SoCLib Support
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (16 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 17/39] LS1043 : Enable NOR driver for LS1043aRDB package Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 10:00 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for PCF2129 Real Time Clock Library Meenakshi
` (23 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
On LS1046A NXP SoC,Provide Functions to initialize peripherals
,print board, soc information.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 +
Silicon/NXP/Chassis/Chassis.c | 1 +
Silicon/NXP/Chassis/Chassis.h | 1 +
Silicon/NXP/Chassis/Chassis2/Soc.c | 51 ++++++++++++++++++++-
Silicon/NXP/Chassis/LS1043aSocLib.inf | 2 +
Silicon/NXP/Chassis/LS1046aSocLib.inf | 51 +++++++++++++++++++++
Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 ++++++++++++++++++++++
Silicon/NXP/LS1046A/LS1046A.dec | 22 +++++++++
Silicon/NXP/LS1046A/LS1046A.dsc | 68 ++++++++++++++++++++++++++++
Silicon/NXP/NxpQoriqLs.dec | 2 +
10 files changed, 253 insertions(+), 1 deletion(-)
create mode 100644 Silicon/NXP/Chassis/LS1046aSocLib.inf
create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 7708e0a..b2b514e 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -59,6 +59,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
+ gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|TRUE
#
# I2C controller Pcds
diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c
index 9f2928b..ce07fdc 100644
--- a/Silicon/NXP/Chassis/Chassis.c
+++ b/Silicon/NXP/Chassis/Chassis.c
@@ -44,6 +44,7 @@ GurRead (
*/
STATIC CPU_TYPE CpuTypeList[] = {
CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
+ CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
};
/*
diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h
index 4bdb4d0..0beb44c 100644
--- a/Silicon/NXP/Chassis/Chassis.h
+++ b/Silicon/NXP/Chassis/Chassis.h
@@ -56,6 +56,7 @@ CpuMaskNext (
#define SVR_WO_E 0xFFFFFE
#define SVR_LS1043A 0x879200
+#define SVR_LS1046A 0x870700
#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chassis2/Soc.c
index 17de7e4..658df2d 100644
--- a/Silicon/NXP/Chassis/Chassis2/Soc.c
+++ b/Silicon/NXP/Chassis/Chassis2/Soc.c
@@ -17,6 +17,7 @@
#include <Chassis.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib/MemLibInternals.h>
+#include <Library/BeIoLib.h>
#include <Library/DebugLib.h>
#include <Library/IfcLib.h>
#include <Library/IoLib.h>
@@ -139,6 +140,44 @@ GetSysInfo (
}
/**
+ Function to select pins depending upon pcd using supplemental
+ configuration unit(SCFG) extended RCW controlled pinmux control
+ register which contains the bits to provide pin multiplexing control.
+ This register is reset on HRESET.
+ **/
+VOID
+ConfigScfgMux (VOID)
+{
+ CCSR_SCFG *Scfg;
+ UINT32 UsbPwrFault;
+
+ Scfg = (VOID *)PcdGet64 (PcdScfgBaseAddr);
+ // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
+ // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
+
+ // LS1043A
+ // Configures functionality of the IIC4_SCL to USB3_DRVVBUS
+ // Configures functionality of the IIC4_SDA to USB3_PWRFAULT
+
+ // LS1046A
+ // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
+ if (PcdGetBool (PcdMuxToUsb3)) {
+ BeMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_SELCR_USB);
+ } else {
+ BeMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB);
+ }
+ BeMmioWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, CCSR_SCFG_USBDRVVBUS_SELCR_USB1);
+ UsbPwrFault = (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
+ CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
+ CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (CCSR_SCFG_USBPWRFAULT_SHARED <<
+ CCSR_SCFG_USBPWRFAULT_USB1_SHIFT);
+ BeMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+ BeMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+}
+
+/**
Function to initialize SoC specific constructs
CPU Info
SoC Personality
@@ -170,8 +209,18 @@ SocInit (
//
PrintRCW ();
PrintSoc ();
- IfcInit();
+ IfcInit ();
PrintBoardPersonality ();
+ //
+ // Due to the extensive functionality present on the chip and the limited number of external
+ // signals available, several functional blocks share signal resources through multiplexing.
+ // In this case when there is alternate functionality between multiple functional blocks,
+ // the signal's function is determined at the chip level (rather than at the block level)
+ // typically by a reset configuration word (RCW) option. Some of the signals' function are
+ // determined externel to RCW at Power-on Reset Sequence.
+ //
+ ConfigScfgMux ();
+
return;
}
diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS1043aSocLib.inf
index d01b353..71fa0a8 100644
--- a/Silicon/NXP/Chassis/LS1043aSocLib.inf
+++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf
@@ -47,3 +47,5 @@
gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3
diff --git a/Silicon/NXP/Chassis/LS1046aSocLib.inf b/Silicon/NXP/Chassis/LS1046aSocLib.inf
new file mode 100644
index 0000000..11eeb97
--- /dev/null
+++ b/Silicon/NXP/Chassis/LS1046aSocLib.inf
@@ -0,0 +1,51 @@
+# @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SocLib
+ FILE_GUID = ddd5f950-8816-4d38-8f98-f42b07333f78
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis/Chassis2/Chassis2.dec
+ Silicon/NXP/LS1046A/LS1046A.dec
+
+[LibraryClasses]
+ BaseLib
+ BeIoLib
+ DebugLib
+ FpgaLib
+ IfcLib
+ SerialPortLib
+
+[Sources.common]
+ Chassis.c
+ Chassis2/Soc.c
+ SerDes.c
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3
diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h b/Silicon/NXP/LS1046A/Include/SocSerDes.h
new file mode 100644
index 0000000..a0b5576
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h
@@ -0,0 +1,55 @@
+/** @file
+ The Header file of SerDes Module
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __LS1046A_SERDES_H__
+#define __LS1046A_SERDES_H__
+
+#include <SerDes.h>
+
+SERDES_CONFIG SerDes1ConfigTbl[] = {
+ /* SerDes 1 */
+ {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE } },
+ {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE } },
+ {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6 } },
+ {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6 } },
+ {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, SGMII_FM1_DTSEC6 } },
+ {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {}
+};
+
+SERDES_CONFIG SerDes2ConfigTbl[] = {
+ /* SerDes 2 */
+ {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+ {0x5559, {PCIE1, PCIE2, PCIE3, SATA } },
+ {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3 } },
+ {0x5506, {PCIE1, PCIE2, NONE, PCIE3 } },
+ {0x0506, {NONE, PCIE2, NONE, PCIE3 } },
+ {0x0559, {NONE, PCIE2, PCIE3, SATA } },
+ {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA } },
+ {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3 } },
+ {}
+};
+
+SERDES_CONFIG *SerDesConfigTbl[] = {
+ SerDes1ConfigTbl,
+ SerDes2ConfigTbl
+};
+
+#endif /* __LS1046A_SERDES_H */
diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec
new file mode 100644
index 0000000..e266aad
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dec
@@ -0,0 +1,22 @@
+# LS1046A.dec
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+
+[Guids.common]
+ gNxpLs1046ATokenSpaceGuid = {0x8d7ffac8, 0xb4d5, 0x43c3, {0xaa, 0x27, 0x84, 0xbc, 0x12, 0x01, 0x28, 0x10}}
+
+[Includes]
+ Include
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc b/Silicon/NXP/LS1046A/LS1046A.dsc
new file mode 100644
index 0000000..9f87028
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc
@@ -0,0 +1,68 @@
+# LS1046A.dsc
+# LS1046A Soc package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsDynamicDefault.common]
+
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x01410000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01420000
+
+[PcdsFixedAtBuild.common]
+
+ #
+ # CCSR Address Space and other attached Memories
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
+ gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000
+ gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
+
+##
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 43d0a71..39753e7 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -30,6 +30,7 @@
gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0|UINT32|0x00000001
gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000002
gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000003
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT32|0x00000004
#
# Pcds for base address and size
@@ -101,6 +102,7 @@
#
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
+ gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE|BOOLEAN|0x00000253
#
# Clock PCDs
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for PCF2129 Real Time Clock Library
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (17 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 18/39] Silicon/NXP:Add LS1046ARDB SoCLib Support Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 10:11 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 20/39] Platform/NXP: LS1046A RDB Board Library Meenakshi
` (22 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
Library to provide functions for NXP pcf2129 real time clock library
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
---
Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h | 43 +++
Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c | 330 +++++++++++++++++++++
.../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf | 47 +++
3 files changed, 420 insertions(+)
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
new file mode 100644
index 0000000..735f697
--- /dev/null
+++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
@@ -0,0 +1,43 @@
+/** Pcf2129Rtc.h
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCF2129RTC_H__
+#define __PCF2129RTC_H__
+
+/*
+ * RTC register addresses
+ */
+#define PCF2129_CTRL1_REG_ADDR 0x00 // Control Register 1
+#define PCF2129_CTRL2_REG_ADDR 0x01 // Control Register 2
+#define PCF2129_CTRL3_REG_ADDR 0x02 // Control Register 3
+#define PCF2129_SEC_REG_ADDR 0x03
+#define PCF2129_MIN_REG_ADDR 0x04
+#define PCF2129_HR_REG_ADDR 0x05
+#define PCF2129_DAY_REG_ADDR 0x06
+#define PCF2129_WEEKDAY_REG_ADDR 0x07
+#define PCF2129_MON_REG_ADDR 0x08
+#define PCF2129_YR_REG_ADDR 0x09
+
+#define PCF2129_CTRL3_BIT_BLF BIT2 /* Battery Low Flag*/
+
+// Define EPOCH (1998-JANUARY-01) in the Julian Date representation
+#define EPOCH_JULIAN_DATE 2450815
+
+typedef struct {
+ UINTN OperationCount;
+ EFI_I2C_OPERATION SetAddressOp;
+ EFI_I2C_OPERATION GetSetDateTimeOp;
+} RTC_I2C_REQUEST;
+
+#endif // __PCF2129RTC_H__
diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
new file mode 100644
index 0000000..2e21014
--- /dev/null
+++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
@@ -0,0 +1,330 @@
+/** @PCF2129RtcLib.c
+ Implement EFI RealTimeClock with runtime services via RTC Lib for PCF2129 RTC.
+
+ Based on RTC implementation available in
+ EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/I2cMaster.h>
+
+#include "Pcf2129Rtc.h"
+
+STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
+
+/**
+ returns Day of the week [0-6] 0=Sunday
+ Don't try to provide a Year that's before 1998, please !
+ **/
+UINTN
+EfiTimeToWday (
+ IN EFI_TIME *Time
+ )
+{
+ UINTN MonthDiff;
+ UINTN Year;
+ UINTN Month;
+ UINTN JulianDate; // Absolute Julian Date representation of the supplied Time
+ UINTN EpochDays; // Number of days elapsed since EPOCH_JULIAN_DAY
+
+ MonthDiff = (14 - Time->Month) / 12 ;
+ Year = Time->Year + 4800 - MonthDiff;
+ Month = Time->Month + (12*MonthDiff) - 3;
+
+ JulianDate = Time->Day + ((153*Month + 2)/5) + (365*Year) + (Year/4) - (Year/100) + (Year/400) - 32045;
+
+ ASSERT (JulianDate >= EPOCH_JULIAN_DATE);
+ EpochDays = JulianDate - EPOCH_JULIAN_DATE;
+
+ // 4=1/1/1998 was a Thursday
+
+ return (EpochDays + 4) % 7;
+}
+
+/**
+ Write RTC register.
+
+ @param RtcRegAddr Register offset of RTC to write.
+ @param Val Value to be written
+
+**/
+
+STATIC
+VOID
+RtcWrite (
+ IN UINT8 RtcRegAddr,
+ IN UINT8 Val
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = 0;
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = 0;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
+ }
+
+}
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+
+**/
+
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Buffer[10];
+ RTC_I2C_REQUEST Req;
+ UINT8 RtcRegAddr;
+
+ Status = EFI_SUCCESS;
+ RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
+ Buffer[0] = 0;
+
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ RtcWrite (PCF2129_CTRL1_REG_ADDR, Buffer[0]);
+
+ if (Time == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = 0;
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Buffer);
+ Req.GetSetDateTimeOp.Buffer = Buffer;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
+ }
+
+ if (Buffer[PCF2129_CTRL3_REG_ADDR] & PCF2129_CTRL3_BIT_BLF) {
+ DEBUG((DEBUG_INFO, "### Warning: RTC battery status low, check/replace RTC battery.\n"));
+ }
+
+ Time->Nanosecond = 0;
+ Time->Second = BcdToDecimal8 (Buffer[PCF2129_SEC_REG_ADDR] & 0x7F);
+ Time->Minute = BcdToDecimal8 (Buffer[PCF2129_MIN_REG_ADDR] & 0x7F);
+ Time->Hour = BcdToDecimal8 (Buffer[PCF2129_HR_REG_ADDR] & 0x3F);
+ Time->Day = BcdToDecimal8 (Buffer[PCF2129_DAY_REG_ADDR] & 0x3F);
+ Time->Month = BcdToDecimal8 (Buffer[PCF2129_MON_REG_ADDR] & 0x1F);
+ Time->Year = BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]) + ( BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]) >= 98 ? 1900 : 2000);
+
+ return Status;
+}
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
+
+**/
+
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ UINT8 Buffer[8];
+ UINT8 Index;
+ EFI_STATUS Status;
+ RTC_I2C_REQUEST Req;
+ UINT8 RtcRegAddr;
+
+ Index = 0;
+ Status = EFI_SUCCESS;
+ RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
+
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ // start register address
+ Buffer[Index++] = PCF2129_SEC_REG_ADDR;
+
+ // hours, minutes and seconds
+ Buffer[Index++] = DecimalToBcd8 (Time->Second);
+ Buffer[Index++] = DecimalToBcd8 (Time->Minute);
+ Buffer[Index++] = DecimalToBcd8 (Time->Hour);
+ Buffer[Index++] = DecimalToBcd8 (Time->Day);
+ Buffer[Index++] = EfiTimeToWday (Time) & 0x07;
+ Buffer[Index++] = DecimalToBcd8 (Time->Month);
+ Buffer[Index++] = DecimalToBcd8 (Time->Year % 100);
+
+ Req.OperationCount = 2;
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = 0;
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = 0;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Buffer);
+ Req.GetSetDateTimeOp.Buffer = Buffer;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
+ return Status;
+ }
+
+ return Status;
+}
+
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_DEVICE_ERROR The operation could not be started.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+
+ EFI_STATUS Status;
+ EFI_I2C_MASTER_PROTOCOL *I2cMaster;
+ UINTN BusFrequency;
+
+ Status = gBS->LocateProtocol (&gEfiI2cMasterProtocolGuid, NULL, (VOID **)&I2cMaster);
+
+ ASSERT_EFI_ERROR (Status);
+
+ Status = I2cMaster->Reset (I2cMaster);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
+ __FUNCTION__, Status));
+ return Status;
+ }
+
+ BusFrequency = FixedPcdGet32 (PcdI2cSpeed);
+ Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
+ __FUNCTION__, Status));
+ return Status;
+ }
+
+ mI2cMaster = I2cMaster;
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
new file mode 100644
index 0000000..873bcea
--- /dev/null
+++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
@@ -0,0 +1,47 @@
+#/** @Pcf2129RtcLib.inf
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Pcf2129RtcLib
+ FILE_GUID = B661E02D-A90B-42AB-A5F9-CF841AAA43D9
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+
+[Sources.common]
+ Pcf2129RtcLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ DebugLib
+ UefiBootServicesTableLib
+ UefiLib
+
+[Protocols]
+ gEfiDriverBindingProtocolGuid ## CONSUMES
+ gEfiI2cMasterProtocolGuid ## CONSUMES
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cBus
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress
+
+[Depex]
+ gEfiI2cMasterProtocolGuid
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 20/39] Platform/NXP: LS1046A RDB Board Library
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (18 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for PCF2129 Real Time Clock Library Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 13:49 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 21/39] Platform/NXP: Add ArmPlatformLib for LS1046A Meenakshi
` (21 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Library to provide board specific timings for LS1046ARDB
board with interfacing to IFC controller for accessing
FPGA and NAND.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h | 83 ++++++++++++++++++++++
.../NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c | 61 ++++++++++++++++
.../LS1046aRdbPkg/Library/BoardLib/BoardLib.inf | 31 ++++++++
3 files changed, 175 insertions(+)
create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
diff --git a/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h b/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
new file mode 100644
index 0000000..e15100d
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
@@ -0,0 +1,83 @@
+/** IfcBoardSpecificLib.h
+
+ IFC Flash Board Specific Macros and structure
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __IFC__BOARD_SPECIFIC_H__
+#define __IFC__BOARD_SPECIFIC_H__
+
+#include <Ifc.h>
+
+// On board flash support
+#define IFC_NAND_BUF_BASE 0x7E800000
+
+// On board Inegrated flash Controller chip select configuration
+#define IFC_NOR_CS IFC_CS_MAX
+#define IFC_NAND_CS IFC_CS0
+#define IFC_FPGA_CS IFC_CS2
+
+// board-specific NAND timing
+#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x7) | \
+ IFC_FTIM0_NAND_TWP(0x18) | \
+ IFC_FTIM0_NAND_TWCHT(0x7) | \
+ IFC_FTIM0_NAND_TWH(0xa))
+
+#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x32) | \
+ IFC_FTIM1_NAND_TWBE(0x39) | \
+ IFC_FTIM1_NAND_TRR(0xe) | \
+ IFC_FTIM1_NAND_TRP(0x18))
+
+#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0xf) | \
+ IFC_FTIM2_NAND_TREH(0xa) | \
+ IFC_FTIM2_NAND_TWHRE(0x1e))
+
+#define NAND_FTIM3 0x0
+
+#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BUF_BASE) \
+ | IFC_CSPR_PORT_SIZE_8 \
+ | IFC_CSPR_MSEL_NAND \
+ | IFC_CSPR_V)
+
+#define NAND_CSPR_EXT 0x0
+#define NAND_AMASK 0xFFFF0000
+
+#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | IFC_CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
+ | IFC_CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | IFC_CSOR_NAND_PGS_4K /* Page Size = 4K */ \
+ | IFC_CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
+ | IFC_CSOR_NAND_PB(6)) /* 2^6 Pages Per Block */
+
+// board-specific fpga timing
+#define FPGA_BASE_PHYS 0x7fb00000
+#define FPGA_CSPR_EXT 0x0
+#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
+ IFC_CSPR_PORT_SIZE_8 | \
+ IFC_CSPR_MSEL_GPCM | \
+ IFC_CSPR_V)
+
+#define FPGA_AMASK IFC_AMASK(64 * 1024)
+#define FPGA_CSOR IFC_CSOR_NOR_ADM_SHIFT(16)
+
+#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0x0e) | \
+ IFC_FTIM0_GPCM_TEADC(0x0e) | \
+ IFC_FTIM0_GPCM_TEAHC(0x0e))
+#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \
+ IFC_FTIM1_GPCM_TRAD(0x3f))
+#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \
+ IFC_FTIM2_GPCM_TCH(0xf) | \
+ IFC_FTIM2_GPCM_TWP(0x3E))
+#define FPGA_FTIM3 0x0
+
+#endif //__IFC__BOARD_SPECIFIC_H__
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
new file mode 100644
index 0000000..0971935
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
@@ -0,0 +1,61 @@
+/** @file
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IfcBoardSpecific.h>
+
+VOID
+GetIfcNorFlashTimings (
+ IN IFC_TIMINGS * NorIfcTimings
+ )
+{
+ NorIfcTimings->CS = IFC_NOR_CS;
+
+ return ;
+}
+
+VOID
+GetIfcFpgaTimings (
+ IN IFC_TIMINGS *FpgaIfcTimings
+ )
+{
+ FpgaIfcTimings->Ftim[0] = FPGA_FTIM0;
+ FpgaIfcTimings->Ftim[1] = FPGA_FTIM1;
+ FpgaIfcTimings->Ftim[2] = FPGA_FTIM2;
+ FpgaIfcTimings->Ftim[3] = FPGA_FTIM3;
+ FpgaIfcTimings->Cspr = FPGA_CSPR;
+ FpgaIfcTimings->CsprExt = FPGA_CSPR_EXT;
+ FpgaIfcTimings->Amask = FPGA_AMASK;
+ FpgaIfcTimings->Csor = FPGA_CSOR;
+ FpgaIfcTimings->CS = IFC_FPGA_CS;
+
+ return;
+}
+
+VOID
+GetIfcNandFlashTimings (
+ IN IFC_TIMINGS * NandIfcTimings
+ )
+{
+ NandIfcTimings->Ftim[0] = NAND_FTIM0;
+ NandIfcTimings->Ftim[1] = NAND_FTIM1;
+ NandIfcTimings->Ftim[2] = NAND_FTIM2;
+ NandIfcTimings->Ftim[3] = NAND_FTIM3;
+ NandIfcTimings->Cspr = NAND_CSPR;
+ NandIfcTimings->CsprExt = NAND_CSPR_EXT;
+ NandIfcTimings->Amask = NAND_AMASK;
+ NandIfcTimings->Csor = NAND_CSOR;
+ NandIfcTimings->CS = IFC_NAND_CS;
+
+ return;
+}
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
new file mode 100644
index 0000000..151c383
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
@@ -0,0 +1,31 @@
+# @file
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = BoardLib
+ FILE_GUID = 66041dab-97b4-4b45-b9b4-1209a2d55d7a
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardLib
+
+[Sources.common]
+ BoardLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[FixedPcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 21/39] Platform/NXP: Add ArmPlatformLib for LS1046A
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (19 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 20/39] Platform/NXP: LS1046A RDB Board Library Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 13:53 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 22/39] Platform/NXP: LS1046 RDB Board FPGA library Meenakshi
` (20 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
Adding support of ArmPlatformLib for NXP LS1046ARDB board
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../Library/PlatformLib/ArmPlatformLib.c | 105 ++++++++++++++
.../Library/PlatformLib/ArmPlatformLib.inf | 66 +++++++++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 35 +++++
.../Library/PlatformLib/NxpQoriqLsMem.c | 152 +++++++++++++++++++++
4 files changed, 358 insertions(+)
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 0000000..a0bb01d
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,105 @@
+/** ArmPlatformLib.c
+*
+* Contains board initialization functions.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+extern VOID SocInit (VOID);
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Placeholder for Platform Initialization
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+ARM_CORE_INFO LS1046aMpCoreInfoCTA72x4[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = sizeof (LS1046aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = LS1046aMpCoreInfoCTA72x4;
+
+ return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+ IN UINTN MpId
+ )
+{
+ return 1;
+}
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 0000000..49b57fc
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,66 @@
+# @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformLib
+ FILE_GUID = 05a9029b-266f-421d-bb46-0e8385c64aa0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ArmLib
+ SocLib
+
+[Sources.common]
+ NxpQoriqLsHelper.S | GCC
+ NxpQoriqLsMem.c
+ ArmPlatformLib.c
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
new file mode 100644
index 0000000..6d54091
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
@@ -0,0 +1,35 @@
+# @file
+#
+# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_IMPORT(ArmReadMpidr)
+
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ tst x0, #3
+ cset x0, eq
+ ret
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ ret
+
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
+ ldrh w0, [x0]
+ ret
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
new file mode 100644
index 0000000..64c5612
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -0,0 +1,152 @@
+/** NxpQoriqLsMem.c
+*
+* Board memory specific Library.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
+ )
+{
+ UINTN Index;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ Index = 0;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
+ EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ // DRAM1 (Must be 1st entry)
+ VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // CCSR Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IFC region 1
+ //
+ // A-009241 : Unaligned write transactions to IFC may result in corruption of data
+ // Affects : IFC
+ // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
+ // writes on external IFC interface that can corrupt data on external flash.
+ // Impact : Data corruption on external flash may happen in case of unaligned writes to
+ // IFC memory space.
+ // Workaround: Following are the workarounds:
+ // For write transactions from core, IFC interface memories (including IFC SRAM)
+ // should be configured as device type memory in MMU.
+ // For write transactions from non-core masters (like system DMA), the address
+ // should be 16 byte aligned and the data size should be multiple of 16 bytes.
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // QMAN SWP
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // BMAN SWP
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // IFC region 2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DRAM2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // PCIe1
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe3
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DRAM3
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram3BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram3BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram3Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // QSPI region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 22/39] Platform/NXP: LS1046 RDB Board FPGA library
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (20 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 21/39] Platform/NXP: Add ArmPlatformLib for LS1046A Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 14:44 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 23/39] Platform/NXP: Compilation for LS1046A RDB Board Meenakshi
` (19 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Library to provide functions for accessing FPGA
on LS1046ARDB board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h | 97 ++++++++++++++
.../NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c | 144 +++++++++++++++++++++
.../NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf | 32 +++++
3 files changed, 273 insertions(+)
create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
diff --git a/Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h b/Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
new file mode 100644
index 0000000..c8f7411
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
@@ -0,0 +1,97 @@
+/** FpgaLib.h
+* Header defining the LS1046a Fpga specific constants (Base addresses, sizes, flags)
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __LS1046A_FPGA_H__
+#define __LS1046A_FPGA_H__
+
+/**
+ FPGA register set of LS1046ARDB board-specific.
+ **/
+typedef struct {
+ UINT8 FpgaVersionMajor; // 0x0 - FPGA Major Revision Register
+ UINT8 FpgaVersionMinor; // 0x1 - FPGA Minor Revision Register
+ UINT8 PcbaVersion; // 0x2 - PCBA Revision Register
+ UINT8 SystemReset; // 0x3 - system reset register
+ UINT8 SoftMuxOn; // 0x4 - Switch Control Enable Register
+ UINT8 RcwSource1; // 0x5 - Reset config word 1
+ UINT8 RcwSource2; // 0x6 - Reset config word 1
+ UINT8 Vbank; // 0x7 - Flash bank selection Control
+ UINT8 SysclkSelect; // 0x8 - System clock selection Control
+ UINT8 UartSel; // 0x9 - Uart selection Control
+ UINT8 Sd1RefClkSel; // 0xA - Serdes1 reference clock selection Control
+ UINT8 TdmClkMuxSel; // 0xB - TDM Clock Mux selection Control
+ UINT8 SdhcSpiCsSel; // 0xC - SDHC/SPI Chip select selection Control
+ UINT8 StatusLed; // 0xD - Status Led
+ UINT8 GlobalReset; // 0xE - Global reset
+ UINT8 SdEmmc; // 0xF - SD or EMMC Interface Control Regsiter
+ UINT8 VddEn; // 0x10 - VDD Voltage Control Enable Register
+ UINT8 VddSel; // 0x11 - VDD Voltage Control Register
+} FPGA_REG_SET;
+
+/**
+ Function to read FPGA register.
+**/
+UINT8
+FpgaRead (
+ UINTN Reg
+ );
+
+/**
+ Function to write FPGA register.
+**/
+VOID
+FpgaWrite (
+ UINTN Reg,
+ UINT8 Value
+ );
+
+/**
+ Function to read FPGA revision.
+**/
+VOID
+FpgaRevBit (
+ UINT8 *Value
+ );
+
+/**
+ Function to initialize FPGA timings.
+**/
+VOID
+FpgaInit (
+ VOID
+ );
+
+/**
+ Function to print board personality.
+**/
+VOID
+PrintBoardPersonality (
+ VOID
+ );
+
+#define FPGA_BASE_PHYS 0x7fb00000
+
+#define SRC_VBANK 0x25
+#define SRC_NAND 0x106
+#define SRC_QSPI 0x44
+#define SRC_SD 0x40
+
+#define SERDES_FREQ1 "100.00 MHz"
+#define SERDES_FREQ2 "156.25 MHz"
+
+#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg))
+#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), Value)
+
+#endif
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c b/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c
new file mode 100644
index 0000000..90cc1ea
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c
@@ -0,0 +1,144 @@
+/** @FpgaLib.c
+ Fpga Library for LS1046A-RDB board, containing functions to
+ program and read the Fpga registers.
+
+ FPGA is connected to IFC Controller and so MMIO APIs are used
+ to read/write FPGA registers
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/FpgaLib.h>
+#include <Library/IoLib.h>
+
+/**
+ Function to read FPGA register.
+
+ @param Reg Register offset of FPGA to read.
+
+**/
+UINT8
+FpgaRead (
+ IN UINTN Reg
+ )
+{
+ VOID *Base;
+
+ Base = (VOID *)FPGA_BASE_PHYS;
+
+ return MmioRead8 ((UINTN)(Base + Reg));
+}
+
+/**
+ Function to write FPGA register.
+
+ @param Reg Register offset of FPGA to write.
+ @param Value Value to be written.
+
+**/
+VOID
+FpgaWrite (
+ IN UINTN Reg,
+ IN UINT8 Value
+ )
+{
+ VOID *Base;
+
+ Base = (VOID *)FPGA_BASE_PHYS;
+
+ MmioWrite8 ((UINTN)(Base + Reg), Value);
+}
+
+/**
+ Function to reverse the number.
+
+ @param *Value pointer to number to reverse.
+
+ @retval *Value reversed value.
+
+**/
+VOID
+FpgaRevBit (
+ OUT UINT8 *Value
+ )
+{
+ UINT8 Rev;
+ UINT8 Val;
+ UINTN Index;
+
+ Val = *Value;
+ Rev = Val & 1;
+ for (Index = 1; Index <= 7; Index++) {
+ Val >>= 1;
+ Rev <<= 1;
+ Rev |= Val & 1;
+ }
+
+ *Value = Rev;
+}
+
+/**
+ Function to print board personality.
+
+**/
+VOID
+PrintBoardPersonality (
+ VOID
+ )
+{
+ UINT8 RcwSrc1;
+ UINT8 RcwSrc2;
+ UINT32 RcwSrc;
+ UINT32 Sd1RefClkSel;
+
+ RcwSrc1 = FPGA_READ(RcwSource1);
+ RcwSrc2 = FPGA_READ(RcwSource2);
+ FpgaRevBit (&RcwSrc1);
+ RcwSrc = RcwSrc1;
+ RcwSrc = (RcwSrc << 1) | RcwSrc2;
+
+ switch (RcwSrc) {
+ case SRC_VBANK:
+ DEBUG ((DEBUG_INFO, "vBank: %d\n", FPGA_READ(Vbank)));
+ break;
+ case SRC_NAND:
+ DEBUG ((DEBUG_INFO, "NAND\n"));
+ break;
+ case SRC_QSPI:
+ DEBUG ((DEBUG_INFO, "QSPI vBank %d\n", FPGA_READ(Vbank)));
+ break;
+ case SRC_SD:
+ DEBUG ((DEBUG_INFO, "SD\n"));
+ break;
+ default:
+ DEBUG ((DEBUG_INFO, "Invalid setting of SW5\n"));
+ break;
+ }
+
+ DEBUG ((DEBUG_INFO, "FPGA: V%x.%x\nPCBA: V%x.0\n",
+ FPGA_READ(FpgaVersionMajor),
+ FPGA_READ(FpgaVersionMinor),
+ FPGA_READ(PcbaVersion)));
+
+ DEBUG ((DEBUG_INFO, "SERDES Reference Clocks:\n"));
+
+ Sd1RefClkSel = FPGA_READ(Sd1RefClkSel);
+ DEBUG((DEBUG_INFO, "SD1_CLK1 = %a, SD1_CLK2 = %a\n",
+ Sd1RefClkSel ? SERDES_FREQ2 : SERDES_FREQ1, SERDES_FREQ1));
+ DEBUG((DEBUG_INFO, "SD2_CLK1 = %a, SD2_CLK2 = %a\n",
+ SERDES_FREQ1, SERDES_FREQ1));
+
+ return;
+}
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
new file mode 100644
index 0000000..afc41e3
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
@@ -0,0 +1,32 @@
+# @FpgaLib.inf
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001000A
+ BASE_NAME = FpgaLib
+ FILE_GUID = 6e06ebbf-3a1d-47be-b4f6-1d82f2a9ac73
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = FpgaLib
+
+[Sources.common]
+ FpgaLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ IoLib
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 23/39] Platform/NXP: Compilation for LS1046A RDB Board
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (21 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 22/39] Platform/NXP: LS1046 RDB Board FPGA library Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 14:54 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 24/39] Silicon/NXP:SocLib support for initialization of peripherals Meenakshi
` (18 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
Adding firmware device,description and declaration files to enable
compilation for NXP LS1046ARDB board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
---
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec | 29 ++++
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 94 +++++++++++++
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 197 +++++++++++++++++++++++++++
3 files changed, 320 insertions(+)
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
new file mode 100644
index 0000000..a872ade
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
@@ -0,0 +1,29 @@
+# LS1046aRdbPkg.dec
+# LS1046a board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ PACKAGE_NAME = LS1046aRdbPkg
+ PACKAGE_GUID = c0c8d5e4-f63b-4470-89bc-73c13c13b247
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
new file mode 100644
index 0000000..36002d5
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
@@ -0,0 +1,94 @@
+# LS1046aRdbPkg.dsc
+#
+# LS1046ARDB Board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_NAME = LS1046aRdbPkg
+ PLATFORM_GUID = 43920156-3f3b-4199-9b29-c6db1fb792b0
+ OUTPUT_DIRECTORY = Build/LS1046aRdbPkg
+ FLASH_DEFINITION = Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
+
+!include ../NxpQoriqLs.dsc
+!include ../../../Silicon/NXP/LS1046A/LS1046A.dsc
+
+[LibraryClasses.common]
+ ArmPlatformLib|Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+ BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf
+ SocLib|Silicon/NXP/Chassis/LS1046aSocLib.inf
+ RealTimeClockLib|Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
+ IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
+ BoardLib|Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
+ FpgaLib|Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
+
+[PcdsFixedAtBuild.common]
+
+ #
+ # LS1046a board Specific PCDs
+ # XX (DRAM - Region 1 2GB)
+ # (NOR - IFC Region 1 512MB)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
+ #
+ # Board Specific Pcds
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x2
+
+ #
+ # Big Endian IPs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
+
+ #
+ # I2C controller Pcds
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|3
+
+ #
+ # RTC Pcds
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|100000
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # Architectural Protocols
+ #
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+
+ Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
+ Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+
+ ##
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
new file mode 100644
index 0000000..834e3a4
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
@@ -0,0 +1,197 @@
+# LS1046aRdbPkg.fdf
+#
+# FLASH layout file for LS1046a board.
+#
+# Copyright (c) 2016, Freescale Ltd. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LS1046ARDB_EFI]
+BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
+Size = 0x000EC890|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xEC890
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x000EC890
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+!include ../FVRules.fdf.inc
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize = 0x1
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+
+ INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ #
+ # Network modules
+ #
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+ INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+ INF NetworkPkg/TcpDxe/TcpDxe.inf
+ INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+ INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+ INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+ INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+!endif
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/FatPei/FatPei.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+ FILE FV_IMAGE = c1c1e1a2-3879-4b5e-9dd1-3df2ce60d8ec {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 24/39] Silicon/NXP:SocLib support for initialization of peripherals
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (22 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 23/39] Platform/NXP: Compilation for LS1046A RDB Board Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 15:20 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 25/39] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB Meenakshi
` (17 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Wasim Khan <wasim.khan@nxp.com>
Added SocInit function that initializes peripherals
and print board and soc information for LS2088ARDB Board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Silicon/NXP/Chassis/Chassis.c | 35 ++++++
Silicon/NXP/Chassis/Chassis.h | 17 +++
Silicon/NXP/Chassis/Chassis3/Chassis3.dec | 19 ++++
Silicon/NXP/Chassis/Chassis3/SerDes.h | 91 +++++++++++++++
Silicon/NXP/Chassis/Chassis3/Soc.c | 180 ++++++++++++++++++++++++++++++
Silicon/NXP/Chassis/Chassis3/Soc.h | 150 +++++++++++++++++++++++++
Silicon/NXP/Chassis/LS2088aSocLib.inf | 48 ++++++++
Silicon/NXP/LS2088A/Include/SocSerDes.h | 67 +++++++++++
8 files changed, 607 insertions(+)
create mode 100644 Silicon/NXP/Chassis/Chassis3/Chassis3.dec
create mode 100644 Silicon/NXP/Chassis/Chassis3/SerDes.h
create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.c
create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.h
create mode 100644 Silicon/NXP/Chassis/LS2088aSocLib.inf
create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h
diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c
index ce07fdc..b63efdc 100644
--- a/Silicon/NXP/Chassis/Chassis.c
+++ b/Silicon/NXP/Chassis/Chassis.c
@@ -45,6 +45,7 @@ GurRead (
STATIC CPU_TYPE CpuTypeList[] = {
CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
+ CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
};
/*
@@ -142,6 +143,40 @@ CpuNumCores (
}
/*
+ * Return core's cluster
+ */
+UINT32
+QoriqCoreToCluster (
+ IN UINTN Core
+ )
+{
+ CCSR_GUR *GurBase;
+ UINTN ClusterIndex;
+ UINTN Count;
+ UINT32 Cluster;
+ UINT32 Type;
+ UINTN InitiatorIndex;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClusterIndex = 0;
+ Count = 0;
+ do {
+ Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+ for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+ Type = InitiatorType (Cluster, InitiatorIndex);
+ if (Type) {
+ if (Count == Core)
+ return ClusterIndex;
+ Count++;
+ }
+ }
+ ClusterIndex++;
+ } while (CHECK_CLUSTER (Cluster));
+
+ return -1; // cannot identify the cluster
+}
+
+/*
* Return the type of core i.e. A53, A57 etc of inputted
* core number.
*/
diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h
index 0beb44c..974fefb 100644
--- a/Silicon/NXP/Chassis/Chassis.h
+++ b/Silicon/NXP/Chassis/Chassis.h
@@ -57,6 +57,7 @@ CpuMaskNext (
#define SVR_WO_E 0xFFFFFE
#define SVR_LS1043A 0x879200
#define SVR_LS1046A 0x870700
+#define SVR_LS2088A 0x870901
#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
@@ -142,4 +143,20 @@ CpuNumCores (
VOID
);
+/*
+ * Return the type of initiator for core/hardware accelerator for given core index.
+ */
+UINT32
+QoriqCoreToType (
+ IN UINTN Core
+ );
+
+/*
+ * Return the cluster of initiator for core/hardware accelerator for given core index.
+ */
+UINT32
+QoriqCoreToCluster (
+ IN UINTN Core
+ );
+
#endif /* __CHASSIS_H__ */
diff --git a/Silicon/NXP/Chassis/Chassis3/Chassis3.dec b/Silicon/NXP/Chassis/Chassis3/Chassis3.dec
new file mode 100644
index 0000000..cf41b3c
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis3/Chassis3.dec
@@ -0,0 +1,19 @@
+# @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+
+[Includes]
+ .
diff --git a/Silicon/NXP/Chassis/Chassis3/SerDes.h b/Silicon/NXP/Chassis/Chassis3/SerDes.h
new file mode 100644
index 0000000..a77ddd5
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis3/SerDes.h
@@ -0,0 +1,91 @@
+/** SerDes.h
+ The Header file of SerDes Module for Chassis 3
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SERDES_H__
+#define __SERDES_H__
+
+#include <Uefi/UefiBaseType.h>
+
+#define SRDS_MAX_LANES 8
+
+//
+// SerDes lane protocols/devices
+//
+typedef enum {
+ NONE = 0,
+ PCIE1,
+ PCIE2,
+ PCIE3,
+ PCIE4,
+ SATA1,
+ SATA2,
+ XAUI1,
+ XAUI2,
+ XFI1,
+ XFI2,
+ XFI3,
+ XFI4,
+ XFI5,
+ XFI6,
+ XFI7,
+ XFI8,
+ SGMII1,
+ SGMII2,
+ SGMII3,
+ SGMII4,
+ SGMII5,
+ SGMII6,
+ SGMII7,
+ SGMII8,
+ SGMII9,
+ SGMII10,
+ SGMII11,
+ SGMII12,
+ SGMII13,
+ SGMII14,
+ SGMII15,
+ SGMII16,
+ QSGMII_A,
+ QSGMII_B,
+ QSGMII_C,
+ QSGMII_D,
+ // Number of entries in this enum
+ SERDES_PRTCL_COUNT
+} SERDES_PROTOCOL;
+
+typedef enum {
+ SRDS_1 = 0,
+ SRDS_2,
+ SRDS_MAX_NUM
+} SERDES_NUMBER;
+
+typedef struct {
+ UINT16 Protocol;
+ UINT8 SrdsLane[SRDS_MAX_LANES];
+} SERDES_CONFIG;
+
+typedef VOID
+(*SERDES_PROBE_LANES_CALLBACK) (
+ IN SERDES_PROTOCOL LaneProtocol,
+ IN VOID *Arg
+ );
+
+VOID
+SerDesProbeLanes(
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ );
+
+#endif /* __SERDES_H */
diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.c b/Silicon/NXP/Chassis/Chassis3/Soc.c
new file mode 100644
index 0000000..ed6c3cc
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis3/Soc.c
@@ -0,0 +1,180 @@
+/** @Soc.c
+ SoC specific Library containg functions to initialize various SoC components
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Chassis.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib/MemLibInternals.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include "Soc.h"
+
+VOID
+GetSysInfo (
+ OUT SYS_INFO *PtrSysInfo
+ )
+{
+ UINT32 Index;
+ CCSR_GUR *GurBase;
+ CCSR_CLT_CTRL *ClkBase;
+ CCSR_CLK_CLUSTER *ClkGrp[2] = {
+ (VOID *) (FSL_CLK_GRPA_ADDR),
+ (VOID *) (FSL_CLK_GRPB_ADDR)
+ };
+
+ const UINT8 CoreCplxPll[16] = {
+ [0] = 0, // CC1 PPL / 1
+ [1] = 0, // CC1 PPL / 2
+ [2] = 0, // CC1 PPL / 4
+ [4] = 1, // CC2 PPL / 1
+ [5] = 1, // CC2 PPL / 2
+ [6] = 1, // CC2 PPL / 4
+ [8] = 2, // CC3 PPL / 1
+ [9] = 2, // CC3 PPL / 2
+ [10] = 2, // CC3 PPL / 4
+ [12] = 3, // CC4 PPL / 1
+ [13] = 3, // CC4 PPL / 2
+ [14] = 3, // CC4 PPL / 4
+ };
+
+ const UINT8 CoreCplxPllDivisor[16] = {
+ [0] = 1, // CC1 PPL / 1
+ [1] = 2, // CC1 PPL / 2
+ [2] = 4, // CC1 PPL / 4
+ [4] = 1, // CC2 PPL / 1
+ [5] = 2, // CC2 PPL / 2
+ [6] = 4, // CC2 PPL / 4
+ [8] = 1, // CC3 PPL / 1
+ [9] = 2, // CC3 PPL / 2
+ [10] = 4, // CC3 PPL / 4
+ [12] = 1, // CC4 PPL / 1
+ [13] = 2, // CC4 PPL / 2
+ [14] = 4, // CC4 PPL / 4
+ };
+
+ INT32 CcGroup[12] = FSL_CLUSTER_CLOCKS;
+ UINTN PllCount;
+ UINTN Cluster;
+ UINTN FreqCPll[NUM_CC_PLLS];
+ UINTN PllRatio[NUM_CC_PLLS];
+ UINTN SysClk;
+ UINT32 Cpu;
+ UINT32 CPllSel;
+ UINT32 CplxPll;
+ VOID *Offset;
+
+ SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
+ SysClk = CLK_FREQ;
+
+ PtrSysInfo->FreqSystemBus = SysClk;
+ PtrSysInfo->FreqDdrBus = PcdGet64 (PcdDdrClk);
+ PtrSysInfo->FreqDdrBus2 = PcdGet64 (PcdDdrClk);
+
+ //
+ // selects the platform clock:SYSCLK ratio and calculate
+ // system frequency
+ //
+ PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+ CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT) &
+ CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK;
+
+ //
+ // Platform clock is half of platform PLL
+ //
+ PtrSysInfo->FreqSystemBus /= PcdGet32 (PcdPlatformFreqDiv);
+
+ //
+ // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
+ //
+ PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+ CHASSIS3_RCWSR_0_MEM_PLL_RAT_SHIFT) &
+ CHASSIS3_RCWSR_0_MEM_PLL_RAT_MASK;
+ PtrSysInfo->FreqDdrBus2 *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+ CHASSIS3_RCWSR_0_MEM2_PLL_RAT_SHIFT) &
+ CHASSIS3_RCWSR_0_MEM2_PLL_RAT_MASK;
+
+ for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
+ Offset = (VOID *)((UINTN)ClkGrp[PllCount/3] +
+ __builtin_offsetof (CCSR_CLK_CLUSTER, PllnGsr[PllCount%3].Gsr));
+ PllRatio[PllCount] = (GurRead ((UINTN)Offset) >> 1) & 0x3f;
+ FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
+ }
+
+ //
+ // Calculate Core frequency
+ //
+ ForEachCpu (Index, Cpu, CpuNumCores (), CpuMask ()) {
+ Cluster = QoriqCoreToCluster (Cpu);
+ ASSERT_EFI_ERROR (Cluster);
+ CPllSel = (GurRead ((UINTN)&ClkBase->ClkCnCsr[Cluster].Csr) >> 27) & 0xf;
+ CplxPll = CoreCplxPll[CPllSel];
+ CplxPll += CcGroup[Cluster] - 1;
+ PtrSysInfo->FreqProcessor[Cpu] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
+ }
+ PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
+}
+
+/**
+ Perform the early initialization.
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+
+**/
+VOID
+SocInit (
+ VOID
+ )
+{
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+
+ //
+ // Initialize SMMU
+ //
+ SmmuInit ();
+
+ //
+ // Initialize the Serial Port.
+ // Early serial port initialization is required to print RCW, Soc and CPU infomation at
+ // the begining of UEFI boot.
+ //
+ SerialPortInitialize ();
+
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\nUEFI firmware (version %s built at %a on %a)\n\r",
+ (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__);
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+ //
+ // Print CPU information
+ //
+ PrintCpuInfo ();
+
+ //
+ // Print Reset Controll Word
+ //
+ PrintRCW ();
+
+ //
+ // Print Soc Personality information
+ //
+ PrintSoc ();
+}
+
diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.h b/Silicon/NXP/Chassis/Chassis3/Soc.h
new file mode 100644
index 0000000..0e892fb
--- /dev/null
+++ b/Silicon/NXP/Chassis/Chassis3/Soc.h
@@ -0,0 +1,150 @@
+/** Soc.h
+* Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+* Copyright (c) 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#define MAX_CPUS 16
+#define FSL_CLK_GRPA_ADDR 0x01300000
+#define FSL_CLK_GRPB_ADDR 0x01310000
+#define NUM_CC_PLLS 6
+#define CLK_FREQ 100000000
+
+#define FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } /* LS208x */
+#define TP_CLUSTER_EOC_MASK 0x80000000 /* Mask for End of clusters */
+#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) != TP_CLUSTER_EOC_MASK)
+
+// RCW SERDES MACRO
+#define RCWSR_INDEX 28
+#define RCWSR_SRDS1_PRTCL_MASK 0x00ff0000
+#define RCWSR_SRDS1_PRTCL_SHIFT 16
+#define RCWSR_SRDS2_PRTCL_MASK 0xff000000
+#define RCWSR_SRDS2_PRTCL_SHIFT 24
+
+// SMMU Defintions
+#define SMMU_BASE_ADDR 0x05000000
+#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
+#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
+#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
+
+#define SACR_PAGESIZE_MASK 0x00010000
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SCR0_USFCFG_MASK 0x00000400
+
+typedef struct {
+ UINTN FreqProcessor[MAX_CPUS];
+ UINTN FreqSystemBus;
+ UINTN FreqDdrBus;
+ UINTN FreqDdrBus2;
+ UINTN FreqLocalBus;
+ UINTN FreqSdhc;
+ UINTN FreqFman[1];
+ UINTN FreqQman;
+ UINTN FreqPme;
+}SYS_INFO;
+
+///
+/// Device Configuration and Pin Control
+///
+typedef struct {
+ UINT32 PorSr1; // POR status register 1
+ UINT32 PorSr2; // POR status register 2
+ UINT8 Res008[0x20-0x8];
+ UINT32 GppOrCr1; // General-purpose POR configuration register
+ UINT32 GppOrCr2; // General-purpose POR configuration register 2
+ UINT32 DcfgFuseSr; // Fuse status register */
+ UINT32 GppOrCr3;
+ UINT32 GppOrCr4;
+ UINT8 Res034[0x70-0x34];
+ UINT32 DevDisr; // Device disable control register
+ UINT32 DevDisr2; // Device disable control register 2
+ UINT32 DevDisr3; // Device disable control register 3
+ UINT32 DevDisr4; // Device disable control register 4
+ UINT32 DevDisr5; // Device disable control register 5
+ UINT32 DevDisr6; // Device disable control register 6
+ UINT32 DevDisr7; // Device disable control register 7
+ UINT8 Res08c[0x90-0x8c];
+ UINT32 CoreDisrUpper; // CORE DISR Uppper for support of 64 cores
+ UINT32 CoreDisrLower; // CORE DISR Lower for support of 64 cores
+ UINT8 Res098[0xa0-0x98];
+ UINT32 Pvr; // Processor version
+ UINT32 Svr; // System version
+ UINT32 Mvr; // Manufacturing version
+ UINT8 Res0ac[0x100-0xac];
+ UINT32 RcwSr[32]; // Reset control word status
+#define CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT 2
+#define CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK 0x1f
+#define CHASSIS3_RCWSR_0_MEM_PLL_RAT_SHIFT 10
+#define CHASSIS3_RCWSR_0_MEM_PLL_RAT_MASK 0x3f
+#define CHASSIS3_RCWSR_0_MEM2_PLL_RAT_SHIFT 18
+#define CHASSIS3_RCWSR_0_MEM2_PLL_RAT_MASK 0x3f
+ UINT8 Res180[0x200-0x180];
+ UINT32 ScratchRw[32]; // Scratch Read/Write
+ UINT8 Res280[0x300-0x280];
+ UINT32 ScratchW1R[4]; // Scratch Read (Write once)
+ UINT8 Res310[0x400-0x310];
+ UINT32 BootLocPtrL; // Low addr : Boot location pointer
+ UINT32 BootLocPtrH; // High addr : Boot location pointer
+ UINT8 Res408[0x500-0x408];
+ UINT8 Res500[0x740-0x500];
+ UINT32 TpItyp[64];
+ struct {
+ UINT32 Upper;
+ UINT32 Lower;
+ } TpCluster[3];
+ UINT8 Res858[0x1000-0x858];
+} CCSR_GUR;
+
+///
+/// Clocking
+///
+typedef struct {
+ struct {
+ UINT32 Csr; // core cluster n clock control status
+ UINT8 Res04[0x20-0x04];
+ } ClkCnCsr[8];
+} CCSR_CLT_CTRL;
+
+///
+/// Clock Cluster
+///
+typedef struct {
+ struct {
+ UINT8 Res00[0x10];
+ UINT32 Csr; // core cluster n clock control status
+ UINT8 Res14[0x20-0x14];
+ } HwnCsr[3];
+ UINT8 Res60[0x80-0x60];
+ struct {
+ UINT32 Gsr; // core cluster n clock general status
+ UINT8 Res84[0xa0-0x84];
+ } PllnGsr[3];
+ UINT8 Rese0[0x100-0xe0];
+} CCSR_CLK_CLUSTER;
+
+VOID
+GetSysInfo (
+ OUT SYS_INFO *
+ );
+
+UINT32
+EFIAPI
+GurRead (
+ IN UINTN Address
+ );
+
+#endif /* __SOC_H__ */
diff --git a/Silicon/NXP/Chassis/LS2088aSocLib.inf b/Silicon/NXP/Chassis/LS2088aSocLib.inf
new file mode 100644
index 0000000..8a4da50
--- /dev/null
+++ b/Silicon/NXP/Chassis/LS2088aSocLib.inf
@@ -0,0 +1,48 @@
+# @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SocLib
+ FILE_GUID = 3b233a6a-0ee1-42a3-a7f7-c285b5ba80dc
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis/Chassis3/Chassis3.dec
+ Silicon/NXP/LS2088A/LS2088A.dec
+
+[LibraryClasses]
+ BaseLib
+ BeIoLib
+ DebugLib
+ SerialPortLib
+
+[Sources.common]
+ Chassis.c
+ Chassis3/Soc.c
+ SerDes.c
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDdrClk
diff --git a/Silicon/NXP/LS2088A/Include/SocSerDes.h b/Silicon/NXP/LS2088A/Include/SocSerDes.h
new file mode 100644
index 0000000..f631ccb
--- /dev/null
+++ b/Silicon/NXP/LS2088A/Include/SocSerDes.h
@@ -0,0 +1,67 @@
+/** @file
+ The Header file of SerDes Module for LS2088A
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SOC_SERDES_H__
+#define __SOC_SERDES_H__
+
+#include <SerDes.h>
+
+SERDES_CONFIG SerDes1ConfigTbl[] = {
+ // SerDes 1
+ { 0x03, { PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
+ { 0x05, { PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x07, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x09, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x0A, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x0C, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x0E, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x26, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
+ { 0x28, { SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
+ { 0x2A, { XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
+ { 0x2B, { SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
+ { 0x32, { XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
+ { 0x33, { PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B, QSGMII_A } },
+ { 0x35, { QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+ {}
+};
+
+SERDES_CONFIG SerDes2ConfigTbl[] = {
+ // SerDes 2
+ { 0x07, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x09, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x0A, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x0C, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x0E, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x3D, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
+ { 0x3E, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
+ { 0x3F, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
+ { 0x40, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
+ { 0x41, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
+ { 0x42, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
+ { 0x43, { PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
+ { 0x44, { PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
+ { 0x45, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, PCIE4 } },
+ { 0x47, { PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, SGMII16 } },
+ { 0x49, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } },
+ { 0x4A, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } },
+ {}
+};
+
+SERDES_CONFIG *SerDesConfigTbl[] = {
+ SerDes1ConfigTbl,
+ SerDes2ConfigTbl
+};
+
+#endif /* __SOC_SERDES_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 25/39] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (23 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 24/39] Silicon/NXP:SocLib support for initialization of peripherals Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 15:59 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 26/39] Silicon/Maxim: DS3232 RTC Library Support Meenakshi
` (16 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Wasim Khan <wasim.khan@nxp.com>
Add support of ArmPlatformLib for NXP LS2088ARDB board
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../Library/PlatformLib/ArmPlatformLib.c | 106 ++++++++++++
.../Library/PlatformLib/ArmPlatformLib.inf | 77 +++++++++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 35 ++++
.../Library/PlatformLib/NxpQoriqLsMem.c | 189 +++++++++++++++++++++
4 files changed, 407 insertions(+)
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 0000000..90f14ba
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,106 @@
+/** ArmPlatformLib.c
+*
+* Contains board initialization functions.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+extern VOID SocInit (VOID);
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Placeholder for Platform Initialization
+
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+ARM_CORE_INFO LS2088aMpCoreInfoCTA72x4[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = sizeof (LS2088aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = LS2088aMpCoreInfoCTA72x4;
+
+ return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+ IN UINTN MpId
+ )
+{
+ return 1;
+}
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 0000000..f5e5abd
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,77 @@
+#/** @file
+#
+# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformLib
+ FILE_GUID = d1361285-8a47-421c-9efd-6b262c9093fc
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ArmLib
+ SocLib
+
+[Sources.common]
+ ArmPlatformLib.c
+ NxpQoriqLsHelper.S | GCC
+ NxpQoriqLsMem.c
+
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsCacheSize
+
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
new file mode 100644
index 0000000..1917b02
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
@@ -0,0 +1,35 @@
+#/** @file
+#
+# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#include <AsmMacroIoLibV8.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_IMPORT(ArmReadMpidr)
+
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ tst x0, #3
+ cset x0, eq
+ ret
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ ret
+
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
+ ldrh w0, [x0]
+ ret
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
new file mode 100644
index 0000000..ccb49f6
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -0,0 +1,189 @@
+/** NxpQoriqLsMem.c
+*
+* Board memory specific Library.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
+
+//
+// Calculate the MC (Management Complex) base address and DDR size based on
+// if the MC is loaded in DDR low memory region or in DDR high memory region.
+//
+#if FixedPcdGetBool (PcdMcHighMemSupport)
+#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemSize) - FixedPcdGet64 (PcdDpaa2McRamSize)
+#define MC_BASE_ADDR FixedPcdGet64 (PcdDram2BaseAddr) + DDR_MEM_SIZE
+#else
+#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemSize)
+#define MC_BASE_ADDR FixedPcdGet64 (PcdDram1BaseAddr) - FixedPcdGet64 (PcdDpaa2McRamSize)
+#endif
+
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR ** VirtualMemoryMap
+ )
+{
+ UINTN Index;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ Index = 0;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
+ EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ // DRAM1 (Must be 1st entry)
+ VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
+
+ // CCSR Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IFC region 1
+ //
+ // A-009241 : Unaligned write transactions to IFC may result in corruption of data
+ // Affects : IFC
+ // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
+ // writes on external IFC interface that can corrupt data on external flash.
+ // Impact : Data corruption on external flash may happen in case of unaligned writes to
+ // IFC memory space.
+ // Workaround: Following are the workarounds:
+ // For write transactions from core, IFC interface memories (including IFC SRAM)
+ // should be configured as device type memory in MMU.
+ // For write transactions from non-core masters (like system DMA), the address
+ // should be 16 byte aligned and the data size should be multiple of 16 bytes.
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IFC region 2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // QSPI region 1
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // QSPI region 2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegion2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegion2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegion2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // DRAM2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].Length = DDR_MEM_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
+
+ // MC private DRAM
+ VirtualMemoryTable[++Index].PhysicalBase = MC_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = MC_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2McRamSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe1
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe3
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe4
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp4BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp4BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp4BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DPAA2 MC Portals region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2McPortalBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2McPortalBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2McPortalSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DPAA2 NI Portals region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2NiPortalsBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2NiPortalsBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2NiPortalsSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DPAA2 QBMAN Portals - cache enabled region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
+
+ // DPAA2 QBMAN Portals - cache inhibited region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2QBmanPortalSize) - FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 26/39] Silicon/Maxim: DS3232 RTC Library Support
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (24 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 25/39] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 16:02 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 27/39] Compilation : Add the fdf, dsc and dec files Meenakshi
` (15 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Wasim Khan <wasim.khan@nxp.com>
Add Maxim DS3232 RTC Library support
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h | 49 +++
Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c | 370 +++++++++++++++++++++
.../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec | 31 ++
.../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf | 49 +++
4 files changed, 499 insertions(+)
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
new file mode 100644
index 0000000..cd1a321
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
@@ -0,0 +1,49 @@
+/** Ds3232Rtc.h
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __DS3232RTC_H__
+#define __DS3232RTC_H__
+
+//RTC time register
+#define DS3232_SEC_REG_ADDR 0x00
+#define DS3232_MIN_REG_ADDR 0x01
+#define DS3232_HR_REG_ADDR 0x02
+#define DS3232_DAY_REG_ADDR 0x03
+#define DS3232_DATE_REG_ADDR 0x04
+#define DS3232_MON_REG_ADDR 0x05
+#define DS3232_YR_REG_ADDR 0x06
+
+#define DS3232_SEC_BIT_CH 0x80 // Clock Halt (in Register 0)
+
+//RTC control register
+#define DS3232_CTL_REG_ADDR 0x0e
+#define DS3232_STAT_REG_ADDR 0x0f
+
+#define START_YEAR 1970
+#define END_YEAR 2070
+
+//TIME MASKS
+#define MASK_SEC 0x7F
+#define MASK_MIN 0x7F
+#define MASK_HOUR 0x3F
+#define MASK_DAY 0x3F
+#define MASK_MONTH 0x1F
+
+typedef struct {
+ UINTN OperationCount;
+ EFI_I2C_OPERATION SetAddressOp;
+ EFI_I2C_OPERATION GetSetDateTimeOp;
+} RTC_I2C_REQUEST;
+
+#endif // __DS3232RTC_H__
diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
new file mode 100644
index 0000000..1a852e9
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
@@ -0,0 +1,370 @@
+/** Ds3232RtcLib.c
+* Implement EFI RealTimeClock via RTC Lib for DS3232 RTC.
+*
+* Based on RTC implementation available in
+* EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
+*
+* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/I2cMaster.h>
+
+#include "Ds3232Rtc.h"
+
+STATIC VOID *mDriverEventRegistration;
+STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
+
+/**
+ Read RTC register.
+
+ @param SlaveDeviceAddress Slave device address offset of RTC to be read.
+ @param RtcRegAddr Register offset of RTC to be read.
+
+ @retval Register Value read
+
+**/
+STATIC
+UINT8
+RtcRead (
+ IN UINT8 SlaveDeviceAddress,
+ IN UINT8 RtcRegAddr
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+ UINT8 Val;
+
+ Val = 0;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress,
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
+ }
+
+ return Val;
+}
+
+/**
+ Write RTC register.
+
+ @param SlaveDeviceAddress Slave device address offset of RTC to be read.
+ @param RtcRegAddr Register offset of RTC to write.
+ @param Val Value to be written
+
+**/
+STATIC
+VOID
+RtcWrite (
+ IN UINT8 SlaveDeviceAddress,
+ IN UINT8 RtcRegAddr,
+ IN UINT8 Val
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = 0;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress,
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
+ }
+}
+
+/**
+ Configure the MUX device connected to I2C.
+
+ @param RegValue Value to write on mux device register address
+
+**/
+VOID
+ConfigureMuxDevice (
+ IN UINT8 RegValue
+ )
+{
+ RtcWrite (FixedPcdGet8 (PcdMuxDeviceAddress), FixedPcdGet8 (PcdMuxControlRegOffset), RegValue);
+}
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Second;
+ UINT8 Minute;
+ UINT8 Hour;
+ UINT8 Day;
+ UINT8 Month;
+ UINT8 Year;
+
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ Status = EFI_SUCCESS;
+
+ //
+ // Check if the I2C device is connected though a MUX device.
+ //
+ if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
+ // Switch to the channel connected to Ds3232 RTC
+ ConfigureMuxDevice (FixedPcdGet8 (PcdMuxRtcChannelValue));
+ }
+
+ Second = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR);
+ Minute = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MIN_REG_ADDR);
+ Hour = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_HR_REG_ADDR);
+ Day = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_DATE_REG_ADDR);
+ Month = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MON_REG_ADDR);
+ Year = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_YR_REG_ADDR);
+
+ if (Second & DS3232_SEC_BIT_CH) {
+ DEBUG ((DEBUG_ERROR, "### Warning: RTC oscillator has stopped\n"));
+ /* clear the CH flag */
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR,
+ RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR) & ~DS3232_SEC_BIT_CH);
+ Status = EFI_DEVICE_ERROR;
+ goto EXIT;
+ }
+
+ Time->Second = BcdToDecimal8 (Second & MASK_SEC);
+ Time->Minute = BcdToDecimal8 (Minute & MASK_MIN);
+ Time->Hour = BcdToDecimal8 (Hour & MASK_HOUR);
+ Time->Day = BcdToDecimal8 (Day & MASK_DAY);
+ Time->Month = BcdToDecimal8 (Month & MASK_MONTH);
+
+ //
+ // RTC can save year 1970 to 2069
+ // On writing Year, save year % 100
+ // On Reading reversing the operation e.g. 2012
+ // write = 12 (2012 % 100)
+ // read = 2012 (12 + 2000)
+ //
+ Time->Year = BcdToDecimal8 (Year) +
+ (BcdToDecimal8 (Year) >= 70 ? START_YEAR - 70 : END_YEAR -70);
+
+EXIT:
+ if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
+ // Switch to the default channel
+ ConfigureMuxDevice (FixedPcdGet8 (PcdMuxDefaultChannelValue));
+ }
+
+ return Status;
+}
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ if (Time->Year < START_YEAR || Time->Year >= END_YEAR){
+ DEBUG ((DEBUG_ERROR, "WARNING: Year should be between 1970 and 2069!\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check if the I2C device is connected though a MUX device.
+ //
+ if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
+ // Switch to the channel connected to Ds3232 RTC
+ ConfigureMuxDevice (FixedPcdGet8 (PcdMuxRtcChannelValue));
+ }
+
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_YR_REG_ADDR, DecimalToBcd8 (Time->Year % 100));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MON_REG_ADDR, DecimalToBcd8 (Time->Month));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_DATE_REG_ADDR, DecimalToBcd8 (Time->Day));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_HR_REG_ADDR, DecimalToBcd8 (Time->Hour));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MIN_REG_ADDR, DecimalToBcd8 (Time->Minute));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR, DecimalToBcd8 (Time->Second));
+
+ if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
+ // Switch to the default channel
+ ConfigureMuxDevice (FixedPcdGet8 (PcdMuxDefaultChannelValue));
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // Currently not supporting this feature.
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // Currently not supporting this feature.
+ return EFI_UNSUPPORTED;
+}
+
+STATIC
+VOID
+I2cDriverRegistrationEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_I2C_MASTER_PROTOCOL *I2cMaster;
+ UINTN BusFrequency;
+
+ Status = gBS->LocateProtocol (&gEfiI2cMasterProtocolGuid, NULL, (VOID **)&I2cMaster);
+
+ gBS->CloseEvent (Event);
+
+ ASSERT_EFI_ERROR (Status);
+
+ Status = I2cMaster->Reset (I2cMaster);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
+ __FUNCTION__, Status));
+ return;
+ }
+
+ BusFrequency = FixedPcdGet16 (PcdI2cBusFrequency);
+ Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
+ __FUNCTION__, Status));
+ return;
+ }
+
+ mI2cMaster = I2cMaster;
+}
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ //
+ // Register a protocol registration notification callback on the driver
+ // binding protocol so we can attempt to connect our I2C master to it
+ // as soon as it appears.
+ //
+ EfiCreateProtocolNotifyEvent (
+ &gEfiI2cMasterProtocolGuid,
+ TPL_CALLBACK,
+ I2cDriverRegistrationEvent,
+ NULL,
+ &mDriverEventRegistration);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
new file mode 100644
index 0000000..4471d57
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
@@ -0,0 +1,31 @@
+#/** @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+ PACKAGE_NAME = Ds3232RtcLib
+ PACKAGE_GUID = 0b4192f7-e404-4019-b2e5-1e6004da3313
+ PACKAGE_VERSION = 0.1
+
+[Guids]
+ gDs3232RtcLibTokenSpaceGuid = { 0x7960fc51, 0x0832, 0x4f0b, { 0xb4, 0x22, 0x53, 0x87, 0x03, 0xaa, 0x85, 0xda }}
+
+[PcdsFixedAtBuild]
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002
+ gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed|FALSE|BOOLEAN|0x00000003
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress|0|UINT8|0x00000004
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset|0|UINT8|0x00000005
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0|UINT8|0x00000006
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0|UINT8|0x00000007
diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
new file mode 100644
index 0000000..9cac100
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
@@ -0,0 +1,49 @@
+# @Ds3232RtcLib.inf
+#
+# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Ds3232RtcLib
+ FILE_GUID = 97f1f2c2-51e1-47ad-9660-70b33da1fe71
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+[Sources.common]
+ Ds3232RtcLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
+
+[LibraryClasses]
+ DebugLib
+ UefiBootServicesTableLib
+ UefiLib
+
+[Protocols]
+ gEfiI2cMasterProtocolGuid ## CONSUMES
+
+[FixedPcd]
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency
+ gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue
+
+[Depex]
+ gEfiI2cMasterProtocolGuid
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 27/39] Compilation : Add the fdf, dsc and dec files
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (25 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 26/39] Silicon/Maxim: DS3232 RTC Library Support Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 16:28 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 28/39] Platform/NXP: LS2088A RDB Board Library Meenakshi
` (14 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Wasim Khan <wasim.khan@nxp.com>
The firmware device, description and declaration files for LS2088 board
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec | 29 ++++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 100 ++++++++++++++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 198 +++++++++++++++++++++++++++
Silicon/NXP/LS2088A/LS2088A.dec | 22 +++
Silicon/NXP/LS2088A/LS2088A.dsc | 71 ++++++++++
Silicon/NXP/NxpQoriqLs.dec | 13 ++
6 files changed, 433 insertions(+)
create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
create mode 100755 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
create mode 100644 Silicon/NXP/LS2088A/LS2088A.dec
create mode 100644 Silicon/NXP/LS2088A/LS2088A.dsc
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
new file mode 100644
index 0000000..93d2e5a
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
@@ -0,0 +1,29 @@
+# LS2088aRdbPkg.dec
+# LS2088a board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ PACKAGE_NAME = LS2088aRdbPkg
+ PACKAGE_GUID = 474e0c59-5f77-4060-82dd-9025ee4f4939
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
new file mode 100755
index 0000000..c0a802d
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -0,0 +1,100 @@
+# LS2088aRdbPkg.dsc
+#
+# LS2088ARDB Board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_NAME = LS2088aRdbPkg
+ PLATFORM_GUID = be06d8bc-05eb-44d6-b39f-191e93617ebd
+ OUTPUT_DIRECTORY = Build/LS2088aRdbPkg
+ FLASH_DEFINITION = Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+ DEFINE MC_HIGH_MEM = TRUE
+
+!include ../NxpQoriqLs.dsc
+!include ../../../Silicon/NXP/LS2088A/LS2088A.dsc
+
+[LibraryClasses.common]
+ ArmPlatformLib|Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+ BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf
+ SocLib|Silicon/NXP/Chassis/LS2088aSocLib.inf
+ RealTimeClockLib|Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
+
+[PcdsFixedAtBuild.common]
+
+!if $(MC_HIGH_MEM) == TRUE # Management Complex loaded at the end of DDR2
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000 # Actual base address (0x0080000000)
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000 # 2 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x80000000 # 2GB (PcdDpaa2McRamSize must be 512MB aligned)
+ gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|1
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0080000000 # Actual base
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x0080000000 # 2G
+!else
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x00A0000000 # Actual base address (0x0080000000) + 512MB
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0060000000 # 2GB - 512MB
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x20000000 # 512MB (Fixed)
+ gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|0
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00A0000000 # Actual base + 512MB
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x0060000000 # 2G - 512MB
+!endif
+ gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x380000000 # 14 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x8080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x8800000000 # 512 GB
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
+ #
+ # Board Specific Pcds
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0600
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x2
+ gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|133333333
+
+ #
+ # I2C controller Pcds
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0
+
+ #
+ # RTC Pcds
+ #
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
+ gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed|TRUE
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress|0x75
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset|0x09
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0x09
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0x08
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # Architectural Protocols
+ #
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+ Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
new file mode 100644
index 0000000..14072a6
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
@@ -0,0 +1,198 @@
+# LS2088aRdbPkg.fdf
+#
+# FLASH layout file for LS2088a board.
+#
+# Copyright (c) 2016, Freescale Ltd. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LS2088aRdb_EFI]
+BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
+Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0x00100000
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x00100000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+!include ../FVRules.fdf.inc
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize = 0x1
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+
+ INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ #
+ # Network modules
+ #
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+ INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+ INF NetworkPkg/TcpDxe/TcpDxe.inf
+ INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+ INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+ INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+ INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+!endif
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/FatPei/FatPei.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
diff --git a/Silicon/NXP/LS2088A/LS2088A.dec b/Silicon/NXP/LS2088A/LS2088A.dec
new file mode 100644
index 0000000..8539c63
--- /dev/null
+++ b/Silicon/NXP/LS2088A/LS2088A.dec
@@ -0,0 +1,22 @@
+# LS2088A.dec
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+
+[Guids.common]
+ gNxpLs2088ATokenSpaceGuid = {0xaf770da7, 0x264c, 0x4857, {0x9d, 0xed, 0x56, 0x5e, 0x2c, 0x08, 0x7e, 0x26}}
+
+[Includes]
+ Include
diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc b/Silicon/NXP/LS2088A/LS2088A.dsc
new file mode 100644
index 0000000..8f7dbb5
--- /dev/null
+++ b/Silicon/NXP/LS2088A/LS2088A.dsc
@@ -0,0 +1,71 @@
+# LS2088A.dsc
+# LS2088A Soc package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsDynamicDefault.common]
+
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x6000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x6100000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x00
+
+[PcdsFixedAtBuild.common]
+
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0C000000
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|266666666 #266MHz
+
+ #
+ # ARM L2x0 PCDs
+ gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x10900000
+
+ #
+ # CCSR Address Space and other attached Memories
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x1370000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x30000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x10000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x510000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0xF0000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x3EEA
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x10000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x400000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x10000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x2000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000 # 32 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x2800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 # 32 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x3000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 # 32 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x3800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x800000000 # 32 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x8080000000 # Extended System Memory Base
+ gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0380000000 # 14GB Extended System Memory Size
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x3100000
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x10000
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x1E00000
+ gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x02140000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02000000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
+
+##
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 39753e7..3cb476d 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -92,6 +92,18 @@
gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
#
+ # DPAA2 PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x0|UINT64|0x000001E0
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalBaseAddr|0x0|UINT64|0x000001E1
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalSize|0x0|UINT64|0x000001E2
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsBaseAddr|0x0|UINT64|0x000001E3
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsSize|0x0|UINT64|0x000001E4
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsBaseAddr|0x0|UINT64|0x000001E5
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalSize|0x0|UINT64|0x000001E6
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsCacheSize|0x0|UINT64|0x000001E7
+
+ #
# NV Pcd
#
gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
@@ -102,6 +114,7 @@
#
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
+ gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|FALSE|BOOLEAN|0x00000252
gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE|BOOLEAN|0x00000253
#
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 28/39] Platform/NXP: LS2088A RDB Board Library
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (26 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 27/39] Compilation : Add the fdf, dsc and dec files Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 16:28 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 29/39] Platform/NXP: LS2088 RDB Board FPGA library Meenakshi
` (13 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Wasim Khan <wasim.khan@nxp.com>
Library to provide board specific timings for LS2088ARDB
board with interfacing to IFC controller for accessing
NOR, NAND and FPGA.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
.../NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h | 114 +++++++++++++++++++++
.../NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c | 69 +++++++++++++
.../LS2088aRdbPkg/Library/BoardLib/BoardLib.inf | 28 +++++
3 files changed, 211 insertions(+)
create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h b/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
new file mode 100644
index 0000000..174a242
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
@@ -0,0 +1,114 @@
+/** IfcBoardSpecificLib.h
+
+ IFC Flash Board Specific Macros and structure
+
+ Copyright 2017-2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __IFC__BOARD_SPECIFIC_H__
+#define __IFC__BOARD_SPECIFIC_H__
+
+#include <Ifc.h>
+
+// On board flash support
+#define IFC_NAND_BUF_BASE 0x530000000ULL
+
+// On board Inegrated flash Controller chip select configuration
+#define IFC_NOR_CS IFC_CS0
+#define IFC_NAND_CS IFC_CS2
+#define IFC_FPGA_CS IFC_CS3
+
+
+/* board-specific NAND timing */
+#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x0e) | \
+ IFC_FTIM0_NAND_TWP(0x30) | \
+ IFC_FTIM0_NAND_TWCHT(0x0e) | \
+ IFC_FTIM0_NAND_TWH(0x14))
+
+#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x64) | \
+ IFC_FTIM1_NAND_TWBE(0xab) | \
+ IFC_FTIM1_NAND_TRR(0x1c) | \
+ IFC_FTIM1_NAND_TRP(0x30))
+
+#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0x1e) | \
+ IFC_FTIM2_NAND_TREH(0x14) | \
+ IFC_FTIM2_NAND_TWHRE(0x3c))
+
+#define NAND_FTIM3 0x0
+
+#define IFC_NAND_BASE_PHYS 0x30000000
+#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BASE_PHYS) \
+ | IFC_CSPR_PORT_SIZE_8 \
+ | IFC_CSPR_MSEL_NAND \
+ | IFC_CSPR_V)
+
+#define NAND_CSPR_EXT 0x0
+#define NAND_AMASK 0xFFFF0000
+
+#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | IFC_CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | IFC_CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | IFC_CSOR_NAND_PGS_4K /* Page Size = 4K */ \
+ | IFC_CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
+ | IFC_CSOR_NAND_PB(7)) /* 2^7 Pages Per Block */
+
+// board-specific NOR timing
+#define NOR_FTIM0 (IFC_FTIM0_NOR_TACSE(0x4) | \
+ IFC_FTIM0_NOR_TEADC(0x5) | \
+ IFC_FTIM0_NOR_TEAHC(0x5))
+
+#define NOR_FTIM1 (IFC_FTIM1_NOR_TACO(0x35) | \
+ IFC_FTIM1_NOR_TRAD_NOR(0x1a) | \
+ IFC_FTIM1_NOR_TSEQRAD_NOR(0x13))
+
+#define NOR_FTIM2 (IFC_FTIM2_NOR_TCS(0x4) | \
+ IFC_FTIM2_NOR_TCH(0x4) | \
+ IFC_FTIM2_NOR_TWPH(0xe) | \
+ IFC_FTIM2_NOR_TWP(0x1c))
+
+#define NOR_FTIM3 0x04000000
+
+#define IFC_FLASH_BASE_PHYS 0x80000000
+#define NOR_CSPR (IFC_CSPR_PHYS_ADDR(IFC_FLASH_BASE_PHYS) \
+ | IFC_CSPR_PORT_SIZE_16 \
+ | IFC_CSPR_MSEL_NOR \
+ | IFC_CSPR_V)
+
+#define NOR_CSPR_EXT 0x0
+#define NOR_AMASK IFC_AMASK(128*1024*1024)
+#define NOR_CSOR IFC_CSOR_NOR_ADM_SHIFT(12)
+
+// board-specific fpga timing
+#define FPGA_BASE_PHYS 0x20000000
+#define FPGA_CSPR_EXT 0x0
+#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
+ IFC_CSPR_PORT_SIZE_8 | \
+ IFC_CSPR_MSEL_GPCM | \
+ IFC_CSPR_V)
+
+#define FPGA_AMASK IFC_AMASK(64 * 1024)
+#define FPGA_CSOR IFC_CSOR_NOR_ADM_SHIFT(12)
+
+#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0xe) | \
+ IFC_FTIM0_GPCM_TEADC(0xe) | \
+ IFC_FTIM0_GPCM_TEAHC(0xe))
+
+#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \
+ IFC_FTIM1_GPCM_TRAD(0x3f))
+
+#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \
+ IFC_FTIM2_GPCM_TCH(0xf) | \
+ IFC_FTIM2_GPCM_TWP(0x3e))
+
+#define FPGA_FTIM3 0x0
+
+#endif //__IFC__BOARD_SPECIFIC_H__
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
new file mode 100644
index 0000000..936b789
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
@@ -0,0 +1,69 @@
+/** @file
+
+ Copyright 2017-2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IfcBoardSpecific.h>
+
+VOID
+GetIfcNorFlashTimings (
+ IN IFC_TIMINGS * NorIfcTimings
+ )
+{
+ NorIfcTimings->Ftim[0] = NOR_FTIM0;
+ NorIfcTimings->Ftim[1] = NOR_FTIM1;
+ NorIfcTimings->Ftim[2] = NOR_FTIM2;
+ NorIfcTimings->Ftim[3] = NOR_FTIM3;
+ NorIfcTimings->Cspr = NOR_CSPR;
+ NorIfcTimings->CsprExt = NOR_CSPR_EXT;
+ NorIfcTimings->Amask = NOR_AMASK;
+ NorIfcTimings->Csor = NOR_CSOR;
+ NorIfcTimings->CS = IFC_NOR_CS;
+
+ return ;
+}
+
+VOID
+GetIfcFpgaTimings (
+ IN IFC_TIMINGS *FpgaIfcTimings
+ )
+{
+ FpgaIfcTimings->Ftim[0] = FPGA_FTIM0;
+ FpgaIfcTimings->Ftim[1] = FPGA_FTIM1;
+ FpgaIfcTimings->Ftim[2] = FPGA_FTIM2;
+ FpgaIfcTimings->Ftim[3] = FPGA_FTIM3;
+ FpgaIfcTimings->Cspr = FPGA_CSPR;
+ FpgaIfcTimings->CsprExt = FPGA_CSPR_EXT;
+ FpgaIfcTimings->Amask = FPGA_AMASK;
+ FpgaIfcTimings->Csor = FPGA_CSOR;
+ FpgaIfcTimings->CS = IFC_FPGA_CS;
+
+ return;
+}
+
+VOID
+GetIfcNandFlashTimings (
+ IN IFC_TIMINGS * NandIfcTimings
+ )
+{
+ NandIfcTimings->Ftim[0] = NAND_FTIM0;
+ NandIfcTimings->Ftim[1] = NAND_FTIM1;
+ NandIfcTimings->Ftim[2] = NAND_FTIM2;
+ NandIfcTimings->Ftim[3] = NAND_FTIM3;
+ NandIfcTimings->Cspr = NAND_CSPR;
+ NandIfcTimings->CsprExt = NAND_CSPR_EXT;
+ NandIfcTimings->Amask = NAND_AMASK;
+ NandIfcTimings->Csor = NAND_CSOR;
+ NandIfcTimings->CS = IFC_NAND_CS;
+
+ return;
+}
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
new file mode 100644
index 0000000..5df84b1
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
@@ -0,0 +1,28 @@
+# @file
+#
+# Copyright 2017-2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = BoardLib
+ FILE_GUID = 13eacf2a-4338-48f4-88de-6ce4618e1a53
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardLib
+
+[Sources.common]
+ BoardLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 29/39] Platform/NXP: LS2088 RDB Board FPGA library
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (27 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 28/39] Platform/NXP: LS2088A RDB Board Library Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 16:30 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 30/39] LS2088 : Enable support of FpgaLib Meenakshi
` (12 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Wasim Khan <wasim.khan@nxp.com>
Library to provide functions for accessing FPGA
on LS2088ARDB board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
.../NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h | 166 +++++++++++++++++++++
.../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c | 115 ++++++++++++++
.../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 ++++
3 files changed, 312 insertions(+)
create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h b/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
new file mode 100644
index 0000000..84d1f02
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
@@ -0,0 +1,166 @@
+/** FpgaLib.h
+* Header defining the LS2088a Fpga specific constants (Base addresses, sizes, flags)
+*
+* Copyright 2017-2018 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __LS2088A_FPGA_H__
+#define __LS2088A_FPGA_H__
+
+typedef enum {
+ CLK_66,
+ CLK_83,
+ CLK_100,
+ CLK_125,
+ CLK_133
+} SYSTEM_CLOCK;
+
+/*
+ * FPGA register set of LS2088ARDB board-specific.
+ */
+typedef struct {
+ UINT8 Id; // ID value uniquely identifying each QorIQ board type
+ UINT8 Arch; // Board Version
+ UINT8 Ver; // FPGA Version
+ UINT8 Model; // Programming Model
+ UINT8 Minor; // Minor Revision Number
+ UINT8 CtlSys;
+ UINT8 Aux;
+ UINT8 ClkSpd;
+ UINT8 StatDut;
+ UINT8 StatSys;
+ UINT8 StatAlrm;
+ UINT8 Present;
+ UINT8 Present2;
+ UINT8 RcwCtl;
+ UINT8 CtlLed;
+ UINT8 I2cBlk;
+ UINT8 RcfgCtl;
+ UINT8 RcfgSt;
+ UINT8 DcmAd;
+ UINT8 DcmDa;
+ UINT8 Dcmd;
+ UINT8 Dmsg;
+ UINT8 Gdc;
+ UINT8 Gdd;
+ UINT8 Dmack;
+ UINT8 Res1[6];
+ UINT8 Watch;
+ UINT8 PwrCtl[2];
+ UINT8 Res2[2];
+ UINT8 PwrStat[4];
+ UINT8 Res3[8];
+ UINT8 ClkSpd2[2];
+ UINT8 Res4[2];
+ UINT8 Sclk[3];
+ UINT8 Res5;
+ UINT8 Dclk[3];
+ UINT8 Res6;
+ UINT8 ClkDspd[3];
+ UINT8 Res7;
+ UINT8 RstCtl;
+ UINT8 RstStat;
+ UINT8 RstRsn;
+ UINT8 RstFrc[2];
+ UINT8 Res8[11];
+ UINT8 BrdCfg[16];
+ UINT8 DutCfg[16];
+ UINT8 RcwAd[2];
+ UINT8 RcwData;
+ UINT8 Res9[5];
+ UINT8 PostCtl;
+ UINT8 PostStat;
+ UINT8 PostDat[2];
+ UINT8 Pid[4];
+ UINT8 GpioIo[4];
+ UINT8 GpioDir[4];
+ UINT8 Res10[20];
+ UINT8 RjtagCtl;
+ UINT8 RjtagDat;
+ UINT8 Res11[2];
+ UINT8 TrigSrc[4];
+ UINT8 TrigDst[4];
+ UINT8 TrigStat;
+ UINT8 Res12[3];
+ UINT8 TrigCtr[4];
+ UINT8 Res13[16];
+ UINT8 ClkFreq[6];
+ UINT8 ResC6[8];
+ UINT8 ClkBase[2];
+ UINT8 ResD0[8];
+ UINT8 Cms[2];
+ UINT8 ResC0[6];
+ UINT8 Aux2[4];
+ UINT8 Res14[10];
+ UINT8 AuxAd;
+ UINT8 AuxDa;
+ UINT8 Res15[16];
+} FPGA_REG_SET;
+
+/**
+ Function to read FPGA register.
+**/
+UINT8
+FpgaRead (
+ UINTN Reg
+ );
+
+/**
+ Function to write FPGA register.
+**/
+VOID
+FpgaWrite (
+ UINTN Reg,
+ UINT8 Value
+ );
+
+/**
+ Function to initialize FPGA timings.
+**/
+VOID
+FpgaInit (
+ VOID
+ );
+
+/**
+ Function to get system clock frequency.
+**/
+UINTN
+GetBoardSysClk (
+ VOID
+ );
+
+/**
+ Function to print board personality.
+**/
+VOID
+PrintBoardPersonality (
+ VOID
+ );
+
+#define FPGA_BASE_PHYS 0x520000000
+
+//SYSCLK
+#define FPGA_CLK_MASK 0x0F // FPGA Clock Mask
+#define SYSCLK_66_MHZ 66000000
+#define SYSCLK_83_MHZ 83000000
+#define SYSCLK_100_MHZ 100000000
+#define SYSCLK_125_MHZ 125000000
+#define SYSCLK_133_MHZ 133000000
+
+#define FPGA_VBANK_MASK 0x07
+#define FPGA_CS_MASK 0x08
+
+#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg))
+#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), Value)
+
+#endif // __LS2088A_FPGA_H__
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
new file mode 100644
index 0000000..8948c21
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
@@ -0,0 +1,115 @@
+/** @FpgaLib.c
+ Fpga Library for LS2088A-RDB board, containing functions to
+ program and read the Fpga registers.
+
+ FPGA is connected to IFC Controller and so MMIO APIs are used
+ to read/write FPGA registers
+
+ Copyright 2017-2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/FpgaLib.h>
+#include <Library/IoLib.h>
+
+/**
+ Function to read FPGA register.
+
+ @param Reg Register offset of FPGA to read.
+
+**/
+UINT8
+FpgaRead (
+ IN UINTN Reg
+ )
+{
+ VOID *Base;
+
+ Base = (VOID *)FPGA_BASE_PHYS;
+
+ return MmioRead8 ((UINTN)(Base + Reg));
+}
+
+/**
+ Function to write FPGA register.
+
+ @param Reg Register offset of FPGA to write.
+ @param Value Value to be written.
+
+**/
+VOID
+FpgaWrite (
+ IN UINTN Reg,
+ IN UINT8 Value
+ )
+{
+ VOID *Base;
+
+ Base = (VOID *)FPGA_BASE_PHYS;
+
+ MmioWrite8 ((UINTN)(Base + Reg), Value);
+}
+
+/**
+ Function to get board system clock frequency.
+
+**/
+UINTN
+GetBoardSysClk (
+ VOID
+ )
+{
+ UINT8 SysclkConf;
+ SysclkConf = FPGA_READ (BrdCfg[1]);
+ switch (SysclkConf & FPGA_CLK_MASK) {
+ case CLK_66:
+ return SYSCLK_66_MHZ;
+ case CLK_83:
+ return SYSCLK_83_MHZ;
+ case CLK_100:
+ return SYSCLK_100_MHZ;
+ case CLK_125:
+ return SYSCLK_125_MHZ;
+ case CLK_133:
+ return SYSCLK_133_MHZ;
+ }
+ return SYSCLK_100_MHZ;
+}
+
+/**
+ Function to print board personality.
+
+**/
+VOID
+PrintBoardPersonality (
+ VOID
+ )
+{
+ UINT8 SwitchConf;
+ SwitchConf = FPGA_READ (Arch);
+
+ DEBUG ((DEBUG_INFO, "Board Arch: V%d, ", SwitchConf >> 4));
+ DEBUG ((DEBUG_INFO, "Board version: %c, boot from ",
+ (SwitchConf & 0xf) + 'A'));
+
+ SwitchConf = FPGA_READ (BrdCfg[0]);
+
+ if (SwitchConf & FPGA_CS_MASK)
+ DEBUG ((DEBUG_INFO, "NAND\n"));
+ else
+ DEBUG ((DEBUG_INFO, "vBank: %d\n", (SwitchConf & FPGA_VBANK_MASK)));
+
+ DEBUG ((DEBUG_INFO, "FPGA: v%d.%d\n", FPGA_READ (Ver),
+ FPGA_READ (Minor)));
+}
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
new file mode 100644
index 0000000..e70723a
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
@@ -0,0 +1,31 @@
+# @FpgaLib.inf
+#
+# Copyright 2017-2018 NXP
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001000A
+ BASE_NAME = FpgaLib
+ FILE_GUID = dd2ce2f3-f219-4b57-82fd-f1ff8ae8bf5a
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = FpgaLib
+
+[Sources.common]
+ FpgaLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ IoLib
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 30/39] LS2088 : Enable support of FpgaLib
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (28 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 29/39] Platform/NXP: LS2088 RDB Board FPGA library Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 16:31 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 31/39] LS2088ARDB: Enable NOR driver and Runtime Services Meenakshi
` (11 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Wasim Khan <wasim.khan@nxp.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 3 +++
Silicon/NXP/Chassis/Chassis3/Soc.c | 18 +++++++++++++++++-
Silicon/NXP/Chassis/Chassis3/Soc.h | 1 -
Silicon/NXP/Chassis/LS2088aSocLib.inf | 2 ++
Silicon/NXP/LS2088A/LS2088A.dsc | 1 +
5 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
index c0a802d..7894925 100755
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -39,6 +39,9 @@
BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf
SocLib|Silicon/NXP/Chassis/LS2088aSocLib.inf
RealTimeClockLib|Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
+ IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
+ BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
+ FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
[PcdsFixedAtBuild.common]
diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.c b/Silicon/NXP/Chassis/Chassis3/Soc.c
index ed6c3cc..dbb1884 100644
--- a/Silicon/NXP/Chassis/Chassis3/Soc.c
+++ b/Silicon/NXP/Chassis/Chassis3/Soc.c
@@ -18,6 +18,7 @@
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib/MemLibInternals.h>
#include <Library/DebugLib.h>
+#include <Library/IfcLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
@@ -25,6 +26,9 @@
#include "Soc.h"
+extern VOID PrintBoardPersonality (VOID);
+extern UINTN GetBoardSysClk (VOID);
+
VOID
GetSysInfo (
OUT SYS_INFO *PtrSysInfo
@@ -83,7 +87,7 @@ GetSysInfo (
GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
- SysClk = CLK_FREQ;
+ SysClk = GetBoardSysClk ();
PtrSysInfo->FreqSystemBus = SysClk;
PtrSysInfo->FreqDdrBus = PcdGet64 (PcdDdrClk);
@@ -152,6 +156,13 @@ SocInit (
SmmuInit ();
//
+ // Perform IFC Initialization.
+ // Early IFC initialization is required to set timings required for fpga initilzation to
+ // get system clock frequency, board info etc.
+ //
+ IfcInit ();
+
+ //
// Initialize the Serial Port.
// Early serial port initialization is required to print RCW, Soc and CPU infomation at
// the begining of UEFI boot.
@@ -176,5 +187,10 @@ SocInit (
// Print Soc Personality information
//
PrintSoc ();
+
+ //
+ // Print Board Personality information
+ //
+ PrintBoardPersonality ();
}
diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.h b/Silicon/NXP/Chassis/Chassis3/Soc.h
index 0e892fb..c3ac1d5 100644
--- a/Silicon/NXP/Chassis/Chassis3/Soc.h
+++ b/Silicon/NXP/Chassis/Chassis3/Soc.h
@@ -20,7 +20,6 @@
#define FSL_CLK_GRPA_ADDR 0x01300000
#define FSL_CLK_GRPB_ADDR 0x01310000
#define NUM_CC_PLLS 6
-#define CLK_FREQ 100000000
#define FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } /* LS208x */
#define TP_CLUSTER_EOC_MASK 0x80000000 /* Mask for End of clusters */
diff --git a/Silicon/NXP/Chassis/LS2088aSocLib.inf b/Silicon/NXP/Chassis/LS2088aSocLib.inf
index 8a4da50..3111d49 100644
--- a/Silicon/NXP/Chassis/LS2088aSocLib.inf
+++ b/Silicon/NXP/Chassis/LS2088aSocLib.inf
@@ -31,6 +31,8 @@
BaseLib
BeIoLib
DebugLib
+ FpgaLib
+ IfcLib
SerialPortLib
[Sources.common]
diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc b/Silicon/NXP/LS2088A/LS2088A.dsc
index 8f7dbb5..2cff40f 100644
--- a/Silicon/NXP/LS2088A/LS2088A.dsc
+++ b/Silicon/NXP/LS2088A/LS2088A.dsc
@@ -67,5 +67,6 @@
gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02000000
gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000
##
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 31/39] LS2088ARDB: Enable NOR driver and Runtime Services
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (29 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 30/39] LS2088 : Enable support of FpgaLib Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 16:32 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 32/39] Silicon/NXP: Implement PciSegmentLib to support multiple RCs Meenakshi
` (10 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Wasim Khan <wasim.khan@nxp.com>
Enable NOR driver and Runtime Services for LS2088ARDB Platform
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 15 ++++-
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 6 +-
Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc | 99 ++++++++++++++++++++++++++++
3 files changed, 118 insertions(+), 2 deletions(-)
create mode 100644 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
index 7894925..60449b5 100755
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -42,6 +42,7 @@
IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
+ NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
[PcdsFixedAtBuild.common]
@@ -89,6 +90,13 @@
gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0x09
gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0x08
+ #
+ # NV Storage PCDs.
+ #
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x580000000
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x580300000
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
@@ -98,6 +106,11 @@
#
# Architectural Protocols
#
- MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf{
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ }
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+ Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
index 14072a6..785f88b 100644
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
@@ -55,6 +55,7 @@ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
!include ../FVRules.fdf.inc
+!include VarStore.fdf.inc
################################################################################
#
# FV Section
@@ -103,7 +104,8 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -122,6 +124,8 @@ READ_LOCK_STATUS = TRUE
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+ INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
+
#
# Network modules
#
diff --git a/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
new file mode 100644
index 0000000..7d35042
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,99 @@
+## @file
+# FDF include file with FD definition that defines an empty variable store.
+#
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+# Copyright 2017-2018 NXP.
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+##
+
+[FD.LS2088aRdbNv_EFI]
+
+BaseAddress = 0x580300000|gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase #The base address of the FLASH device
+Size = 0x000C0000|gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xC0000
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
+DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
+DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE = 0x00040000
+DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE = 0x00040000
+
+#############################################################################
+# LS2088ARDB NVRAM Area
+# LS2088ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#############################################################################
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0xC0000
+ 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0xFA, 0xF5, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
+ 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiAuthenticatedVariableGuid =
+ # { 0xaaf32c78, 0x947b, 0x439a,
+ # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+ # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xFF, 0x03, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 32/39] Silicon/NXP: Implement PciSegmentLib to support multiple RCs
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (30 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 31/39] LS2088ARDB: Enable NOR driver and Runtime Services Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-19 19:27 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 33/39] Silicon/NXP: Implement PciHostBridgeLib support Meenakshi
` (9 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
Multiple root complex support is not provided by standard library
PciLib/PciExpressLib/PciSegmentLib, Reimplementing it and provide
function for reading/writing into PCIe configuration Space.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Include/Pcie.h | 143 +++++
Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 604 +++++++++++++++++++++
.../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 41 ++
3 files changed, 788 insertions(+)
create mode 100644 Silicon/NXP/Include/Pcie.h
create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
diff --git a/Silicon/NXP/Include/Pcie.h b/Silicon/NXP/Include/Pcie.h
new file mode 100644
index 0000000..a7e6f9b
--- /dev/null
+++ b/Silicon/NXP/Include/Pcie.h
@@ -0,0 +1,143 @@
+/** @file
+ PCI memory configuration for NXP
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __PCI_H__
+#define __PCI_H__
+
+// Segment 0
+#define PCI_SEG0_NUM 0
+
+#define PCI_SEG0_BUSNUM_MIN 0x0
+#define PCI_SEG0_BUSNUM_MAX 0xff
+
+#define PCI_SEG0_PORTIO_MIN 0x0
+#define PCI_SEG0_PORTIO_MAX 0xffff
+
+#define PCI_SEG0_MMIO32_MIN 0x40000000
+#define PCI_SEG0_MMIO32_MAX 0x4fffffff
+#define PCI_SEG0_MMIO64_MIN PCI_SEG0_MMIO_MEMBASE + SEG_MEM_SIZE
+#define PCI_SEG0_MMIO64_MAX PCI_SEG0_MMIO_MEMBASE + SEG_MEM_LIMIT
+#define PCI_SEG0_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp1BaseAddr)
+
+#define PCI_SEG0_DBI_BASE 0x03400000
+
+// Segment 1
+#define PCI_SEG1_NUM 1
+
+#define PCI_SEG1_BUSNUM_MIN 0x0
+#define PCI_SEG1_BUSNUM_MAX 0xff
+
+#define PCI_SEG1_PORTIO_MIN 0x10000
+#define PCI_SEG1_PORTIO_MAX 0x1ffff
+
+#define PCI_SEG1_MMIO32_MIN 0x50000000
+#define PCI_SEG1_MMIO32_MAX 0x5fffffff
+#define PCI_SEG1_MMIO64_MIN PCI_SEG1_MMIO_MEMBASE + SEG_MEM_SIZE
+#define PCI_SEG1_MMIO64_MAX PCI_SEG1_MMIO_MEMBASE + SEG_MEM_LIMIT
+#define PCI_SEG1_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp2BaseAddr)
+
+#define PCI_SEG1_DBI_BASE 0x03500000
+
+// Segment 2
+#define PCI_SEG2_NUM 2
+
+#define PCI_SEG2_BUSNUM_MIN 0x0
+#define PCI_SEG2_BUSNUM_MAX 0xff
+
+#define PCI_SEG2_PORTIO_MIN 0x20000
+#define PCI_SEG2_PORTIO_MAX 0x2ffff
+
+#define PCI_SEG2_MMIO32_MIN 0x60000000
+#define PCI_SEG2_MMIO32_MAX 0x6fffffff
+#define PCI_SEG2_MMIO64_MIN PCI_SEG2_MMIO_MEMBASE + SEG_MEM_SIZE
+#define PCI_SEG2_MMIO64_MAX PCI_SEG2_MMIO_MEMBASE + SEG_MEM_LIMIT
+#define PCI_SEG2_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp3BaseAddr)
+
+#define PCI_SEG2_DBI_BASE 0x03600000
+
+// Segment 3
+#define PCI_SEG3_NUM 3
+
+#define PCI_SEG3_BUSNUM_MIN 0x0
+#define PCI_SEG3_BUSNUM_MAX 0xff
+
+#define PCI_SEG3_PORTIO_MIN 0x30000
+#define PCI_SEG3_PORTIO_MAX 0x3ffff
+
+#define PCI_SEG3_MMIO32_MIN 0x70000000
+#define PCI_SEG3_MMIO32_MAX 0x7fffffff
+#define PCI_SEG3_MMIO64_MIN PCI_SEG3_MMIO_MEMBASE + SEG_MEM_SIZE
+#define PCI_SEG3_MMIO64_MAX PCI_SEG3_MMIO_MEMBASE + SEG_MEM_LIMIT
+#define PCI_SEG3_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp4BaseAddr)
+
+#define PCI_SEG3_DBI_BASE 0x03700000
+
+// Segment configuration
+#define SEG_CFG_SIZE 0x00001000
+#define SEG_CFG_BUS 0x00000000
+#define SEG_MEM_SIZE 0x40000000
+#define SEG_MEM_LIMIT 0x7fffffff
+#define SEG_MEM_BUS 0x40000000
+#define SEG_IO_SIZE 0x00010000
+#define SEG_IO_BUS 0x00000000
+#define PCI_BASE_DIFF 0x800000000
+#define PCI_DBI_SIZE_DIFF 0x100000
+#define PCI_SEG0_PHY_CFG0_BASE PCI_SEG0_MMIO_MEMBASE
+#define PCI_SEG0_PHY_CFG1_BASE PCI_SEG0_PHY_CFG0_BASE + SEG_CFG_SIZE
+#define PCI_SEG0_PHY_MEM_BASE PCI_SEG0_MMIO64_MIN
+#define PCI_SEG0_PHY_IO_BASE PCI_SEG0_MMIO_MEMBASE + SEG_IO_SIZE
+
+// iATU configuration
+#define IATU_VIEWPORT_OFF 0x900
+#define IATU_VIEWPORT_OUTBOUND 0
+
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
+
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31
+
+#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
+#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
+#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914
+#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918
+#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C
+
+#define IATU_REGION_INDEX0 0x0
+#define IATU_REGION_INDEX1 0x1
+#define IATU_REGION_INDEX2 0x2
+#define IATU_REGION_INDEX3 0x3
+
+// PCIe Controller configuration
+#define NUM_PCIE_CONTROLLER FixedPcdGet32 (PcdNumPciController)
+#define PCI_LUT_DBG FixedPcdGet32 (PcdPcieLutDbg)
+#define PCI_LUT_BASE FixedPcdGet32 (PcdPcieLutBase)
+#define LTSSM_STATE_MASK 0x3f
+#define LTSSM_PCIE_L0 0x11
+#define PCI_LINK_CAP 0x7c
+#define PCI_LINK_SPEED_MASK 0xf
+#define PCI_CLASS_BRIDGE_PCI 0x6040010
+#define PCI_CLASS_DEVICE 0x8
+#define PCI_DBI_RO_WR_EN 0x8bc
+#define PCI_BASE_ADDRESS_0 0x10
+
+VOID GetSerdesProtocolMaps (UINT64 *);
+
+BOOLEAN IsSerDesLaneProtocolConfigured (UINT64, UINT16);
+
+#endif
diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
new file mode 100644
index 0000000..acb614d
--- /dev/null
+++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
@@ -0,0 +1,604 @@
+/** @file
+ PCI Segment Library for NXP SoCs with multiple RCs
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials are
+ licensed and made available under the terms and conditions of
+ the BSD License which accompanies this distribution. The full
+ text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Pcie.h>
+
+typedef enum {
+ PciCfgWidthUint8 = 0,
+ PciCfgWidthUint16,
+ PciCfgWidthUint32,
+ PciCfgWidthMax
+} PCI_CFG_WIDTH;
+
+/**
+ Assert the validity of a PCI Segment address.
+ A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
+
+ @param A The address to validate.
+ @param M Additional bits to assert to be zero.
+
+**/
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
+ ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
+
+/**
+ Function to return PCIe Physical Address(PCIe view) or Controller
+ Address(CPU view) for different RCs
+
+ @param Address Address passed from bus layer.
+ @param Segment Segment number for Root Complex.
+
+ @return Return PCIe CPU or Controller address.
+
+**/
+STATIC
+UINT64
+PciSegmentLibGetConfigBase (
+ IN UINT64 Address,
+ IN UINT16 Segment
+ )
+{
+
+ switch (Segment) {
+ // Root Complex 1
+ case PCI_SEG0_NUM:
+ // Reading bus number(bits 20-27)
+ if ((Address >> 20) & 1) {
+ return PCI_SEG0_MMIO_MEMBASE;
+ } else {
+ // On Bus 0 RCs are connected
+ return PCI_SEG0_DBI_BASE;
+ }
+ // Root Complex 2
+ case PCI_SEG1_NUM:
+ // Reading bus number(bits 20-27)
+ if ((Address >> 20) & 1) {
+ return PCI_SEG1_MMIO_MEMBASE;
+ } else {
+ // On Bus 0 RCs are connected
+ return PCI_SEG1_DBI_BASE;
+ }
+ // Root Complex 3
+ case PCI_SEG2_NUM:
+ // Reading bus number(bits 20-27)
+ if ((Address >> 20) & 1) {
+ return PCI_SEG2_MMIO_MEMBASE;
+ } else {
+ // On Bus 0 RCs are connected
+ return PCI_SEG2_DBI_BASE;
+ }
+ // Root Complex 4
+ case PCI_SEG3_NUM:
+ // Reading bus number(bits 20-27)
+ if ((Address >> 20) & 1) {
+ return PCI_SEG3_MMIO_MEMBASE;
+ } else {
+ // On Bus 0 RCs are connected
+ return PCI_SEG3_DBI_BASE;
+ }
+ default:
+ return 0;
+ }
+
+}
+
+/**
+ Internal worker function to read a PCI configuration register.
+
+ @param Address The address that encodes the Segment, PCI Bus, Device,
+ Function and Register.
+ @param Width The width of data to read
+
+ @return The value read from the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibReadWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width
+ )
+{
+ UINT64 Base;
+ UINT16 Offset;
+ UINT16 Segment;
+
+ //
+ // Reading Segment number(47-32) bits in Address
+ //
+ Segment = (Address >> 32);
+ //
+ // Reading Function(12-0) bits in Address
+ //
+ Offset = (Address & 0xfff );
+
+ Base = PciSegmentLibGetConfigBase (Address, Segment);
+
+ //
+ // ignore devices > 0 on bus 0
+ //
+ if ((Address & 0xff00000) == 0 && (Address & 0xf8000) != 0) {
+ return MAX_UINT32;
+ }
+
+ //
+ // ignore device > 0 on bus 1
+ //
+ if ((Address & 0xfe00000) == 0 && (Address & 0xf8000) != 0) {
+ return MAX_UINT32;
+ }
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ return MmioRead8 (Base + (UINT8)Offset);
+ case PciCfgWidthUint16:
+ return MmioRead16 (Base + (UINT16)Offset);
+ case PciCfgWidthUint32:
+ return MmioRead32 (Base + (UINT32)Offset);
+ default:
+ ASSERT (FALSE);
+ }
+
+ return CHAR_NULL;
+}
+
+/**
+ Internal worker function to writes a PCI configuration register.
+
+ @param Address The address that encodes the Segment, PCI Bus, Device,
+ Function and Register.
+ @param Width The width of data to write
+ @param Data The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibWriteWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width,
+ IN UINT32 Data
+ )
+{
+ UINT64 Base;
+ UINT32 Offset;
+ UINT16 Segment;
+
+ //
+ // Reading Segment number(47-32 bits) in Address
+ Segment = (Address >> 32);
+ //
+ // Reading Function(12-0 bits) in Address
+ //
+ Offset = (Address & 0xfff );
+
+ Base = PciSegmentLibGetConfigBase (Address, Segment);
+
+ //
+ // ignore devices > 0 on bus 0
+ //
+ if ((Address & 0xff00000) == 0 && (Address & 0xf8000) != 0) {
+ return Data;
+ }
+
+ //
+ // ignore device > 0 on bus 1
+ //
+ if ((Address & 0xfe00000) == 0 && (Address & 0xf8000) != 0) {
+ return MAX_UINT32;
+ }
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ MmioWrite8 (Base + (UINT8)Offset, Data);
+ break;
+ case PciCfgWidthUint16:
+ MmioWrite16 (Base + (UINT16)Offset, Data);
+ break;
+ case PciCfgWidthUint32:
+ MmioWrite32 (Base + (UINT16)Offset, Data);
+ break;
+ default:
+ ASSERT (FALSE);
+ }
+
+ return Data;
+}
+
+/**
+ Register a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Bus, Device,
+ Function and Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciSegmentRegisterForRuntimeAccess (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+ return RETURN_UNSUPPORTED;
+}
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+
+ @return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+PciSegmentRead8 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
+}
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
+}
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+PciSegmentRead16 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
+}
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the
+ value specified by Value.
+
+ Value is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+PciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
+}
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+PciSegmentRead32 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
+}
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the
+ value specified by Value.
+
+ Value is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+PciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
+}
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param Size The size in bytes of the transfer.
+ @param Buffer The pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+PciSegmentReadBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ // 0xFFF is used as limit for 4KB config space
+ ASSERT (((StartAddress & 0xFFF) + Size) <= SIZE_4KB);
+
+ if (Size == 0) {
+ return Size;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ //
+ // Read a byte if StartAddress is byte aligned
+ //
+ *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8*)Buffer + BIT0;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ //
+ // Read a word if StartAddress is word aligned
+ //
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + BIT0;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Read as many double words as possible
+ //
+ WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32*)Buffer + BIT0;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Read the last remaining word if exist
+ //
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + BIT0;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Read the last remaining byte if exist
+ //
+ *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ }
+
+ return ReturnValue;
+}
+
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param Size The size in bytes of the transfer.
+ @param Buffer The pointer to a buffer containing the data to write.
+
+ @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+PciSegmentWriteBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ // 0xFFF is used as limit for 4KB config space
+ ASSERT (((StartAddress & 0xFFF) + Size) <= SIZE_4KB);
+
+ if (Size == 0) {
+ return Size;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ //
+ // Write a byte if StartAddress is byte aligned
+ //
+ PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8*)Buffer + BIT0;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ //
+ // Write a word if StartAddress is word aligned
+ //
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + BIT0;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Write as many double words as possible
+ //
+ PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32*)Buffer + BIT0;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Write the last remaining word if exist
+ //
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + BIT0;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Write the last remaining byte if exist
+ //
+ PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
+ }
+
+ return ReturnValue;
+}
diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
new file mode 100644
index 0000000..1ac83d4
--- /dev/null
+++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
@@ -0,0 +1,41 @@
+## @file
+# PCI Segment Library for NXP SoCs with multiple RCs
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PciSegmentLib
+ FILE_GUID = c9f59261-5a60-4a4c-82f6-1f520442e100
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciSegmentLib
+
+[Sources]
+ PciSegmentLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 33/39] Silicon/NXP: Implement PciHostBridgeLib support
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (31 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 32/39] Silicon/NXP: Implement PciSegmentLib to support multiple RCs Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-20 8:34 ` Ard Biesheuvel
2018-04-20 14:54 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 34/39] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL Meenakshi
` (8 subsequent siblings)
41 siblings, 2 replies; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
Implement the library that exposes the PCIe root complexes to the
generic PCI host bridge driver,Putting SoC Specific low level init
code for the RCs.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../Library/PciHostBridgeLib/PciHostBridgeLib.c | 618 +++++++++++++++++++++
.../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 50 ++
2 files changed, 668 insertions(+)
create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
new file mode 100644
index 0000000..e6f9b7c
--- /dev/null
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -0,0 +1,618 @@
+/** @file
+ PCI Host Bridge Library instance for NXP SoCs
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/BeIoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Pcie.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+#pragma pack(1)
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }
+ },
+ EISA_PNP_ID (0x0A08), // PCI Express
+ PCI_SEG0_NUM
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }
+ },
+ EISA_PNP_ID (0x0A08), // PCI Express
+ PCI_SEG1_NUM
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }
+ },
+ EISA_PNP_ID (0x0A08), // PCI Express
+ PCI_SEG2_NUM
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }
+ },
+ EISA_PNP_ID (0x0A08), // PCI Express
+ PCI_SEG3_NUM
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ }
+};
+
+STATIC
+GLOBAL_REMOVE_IF_UNREFERENCED
+CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+ L"Mem", L"I/O", L"Bus"
+};
+
+#define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | \
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE
+
+#define PCI_SUPPORT_ATTRIBUTES EFI_PCI_ATTRIBUTE_ISA_IO_16 | \
+ EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
+ EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
+ EFI_PCI_ATTRIBUTE_VGA_IO_16 | \
+ EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
+
+PCI_ROOT_BRIDGE mPciRootBridges[] = {
+ {
+ PCI_SEG0_NUM, // Segment
+ PCI_SUPPORT_ATTRIBUTES, // Supports
+ PCI_SUPPORT_ATTRIBUTES, // Attributes
+ FALSE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
+ { PCI_SEG0_BUSNUM_MIN,
+ PCI_SEG0_BUSNUM_MAX }, // Bus
+ { PCI_SEG0_PORTIO_MIN,
+ PCI_SEG0_PORTIO_MAX }, // Io
+ { PCI_SEG0_MMIO32_MIN,
+ PCI_SEG0_MMIO32_MAX }, // Mem
+ { PCI_SEG0_MMIO64_MIN,
+ PCI_SEG0_MMIO64_MAX }, // MemAbove4G
+ { MAX_UINT64, 0x0 }, // PMem
+ { MAX_UINT64, 0x0 }, // PMemAbove4G
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG0_NUM]
+ }, {
+ PCI_SEG1_NUM, // Segment
+ PCI_SUPPORT_ATTRIBUTES, // Supports
+ PCI_SUPPORT_ATTRIBUTES, // Attributes
+ FALSE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
+ { PCI_SEG1_BUSNUM_MIN,
+ PCI_SEG1_BUSNUM_MAX }, // Bus
+ { PCI_SEG1_PORTIO_MIN,
+ PCI_SEG1_PORTIO_MAX }, // Io
+ { PCI_SEG1_MMIO32_MIN,
+ PCI_SEG1_MMIO32_MAX }, // Mem
+ { PCI_SEG1_MMIO64_MIN,
+ PCI_SEG1_MMIO64_MAX }, // MemAbove4G
+ { MAX_UINT64, 0x0 }, // PMem
+ { MAX_UINT64, 0x0 }, // PMemAbove4G
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG1_NUM]
+ }, {
+ PCI_SEG2_NUM, // Segment
+ PCI_SUPPORT_ATTRIBUTES, // Supports
+ PCI_SUPPORT_ATTRIBUTES, // Attributes
+ FALSE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
+ { PCI_SEG2_BUSNUM_MIN,
+ PCI_SEG2_BUSNUM_MAX }, // Bus
+ { PCI_SEG2_PORTIO_MIN,
+ PCI_SEG2_PORTIO_MAX }, // Io
+ { PCI_SEG2_MMIO32_MIN,
+ PCI_SEG2_MMIO32_MAX }, // Mem
+ { PCI_SEG2_MMIO64_MIN,
+ PCI_SEG2_MMIO64_MAX }, // MemAbove4G
+ { MAX_UINT64, 0x0 }, // PMem
+ { MAX_UINT64, 0x0 }, // PMemAbove4G
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG2_NUM]
+ }, {
+ PCI_SEG3_NUM, // Segment
+ PCI_SUPPORT_ATTRIBUTES, // Supports
+ PCI_SUPPORT_ATTRIBUTES, // Attributes
+ FALSE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
+ { PCI_SEG3_BUSNUM_MIN,
+ PCI_SEG3_BUSNUM_MAX }, // Bus
+ { PCI_SEG3_PORTIO_MIN,
+ PCI_SEG3_PORTIO_MAX }, // Io
+ { PCI_SEG3_MMIO32_MIN,
+ PCI_SEG3_MMIO32_MAX }, // Mem
+ { PCI_SEG3_MMIO64_MIN,
+ PCI_SEG3_MMIO64_MAX }, // MemAbove4G
+ { MAX_UINT64, 0x0 }, // PMem
+ { MAX_UINT64, 0x0 }, // PMemAbove4G
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG3_NUM]
+ }
+};
+
+/**
+ Function to set-up iATU outbound window for PCIe controller
+
+ @param Dbi Address of PCIe host controller.
+ @param Idx Index of iATU outbound window.
+ @param Type Type(Cfg0/Cfg1/Mem/IO) of iATU outbound window.
+ @param Phys PCIe controller phy address for outbound window.
+ @param BusAdr PCIe controller bus address for outbound window.
+ @param Pcie Size of PCIe controller space(Cfg0/Cfg1/Mem/IO).
+
+**/
+STATIC
+VOID
+PcieIatuOutboundSet (
+ IN EFI_PHYSICAL_ADDRESS Dbi,
+ IN UINT32 Idx,
+ IN UINT32 Type,
+ IN UINT64 Phys,
+ IN UINT64 BusAddr,
+ IN UINT64 Size
+ )
+{
+ MmioWrite32 (Dbi + IATU_VIEWPORT_OFF,
+ (UINT32)(IATU_VIEWPORT_OUTBOUND | Idx));
+ MmioWrite32 (Dbi + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
+ (UINT32)Phys);
+ MmioWrite32 (Dbi + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
+ (UINT32)(Phys >> 32));
+ MmioWrite32 (Dbi + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
+ (UINT32)(Phys + Size - BIT0));
+ MmioWrite32 (Dbi + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
+ (UINT32)BusAddr);
+ MmioWrite32 (Dbi + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
+ (UINT32)(BusAddr >> 32));
+ MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
+ (UINT32)Type);
+ MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
+ IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN);
+}
+
+/**
+ Function to check PCIe controller LTSSM state
+
+ @param Pcie Address of PCIe host controller.
+
+**/
+STATIC
+INTN
+PcieLinkState (
+ IN EFI_PHYSICAL_ADDRESS Pcie
+ )
+{
+ UINT32 State;
+
+ //
+ // Reading PCIe controller LTSSM state
+ //
+ if (FeaturePcdGet (PcdPciLutBigEndian)) {
+ State = BeMmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
+ LTSSM_STATE_MASK;
+ } else {
+ State = MmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
+ LTSSM_STATE_MASK;
+ }
+
+ if (State < LTSSM_PCIE_L0) {
+ DEBUG ((DEBUG_INFO," Pcie Link error. LTSSM=0x%2x\n", State));
+ return EFI_SUCCESS;
+ }
+
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Helper function to check PCIe link state
+
+ @param Pcie Address of PCIe host controller.
+
+**/
+STATIC
+INTN
+PcieLinkUp (
+ IN EFI_PHYSICAL_ADDRESS Pcie
+ )
+{
+ INTN State;
+ UINT32 Cap;
+
+ State = PcieLinkState (Pcie);
+ if (State) {
+ return State;
+ }
+
+ //
+ // Try to download speed to gen1
+ //
+ Cap = MmioRead32 ((UINTN)Pcie + PCI_LINK_CAP);
+ MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, (UINT32)(Cap & (~PCI_LINK_SPEED_MASK)) | BIT0);
+ State = PcieLinkState (Pcie);
+ if (State) {
+ return State;
+ }
+
+ MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, Cap);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function checks whether PCIe is enabled or not
+ depending upon SoC serdes protocol map
+
+ @param PcieNum PCIe number.
+
+ @return The PCIe number enabled in map.
+ @return FALSE PCIe number is disabled in map.
+
+**/
+STATIC
+BOOLEAN
+IsPcieNumEnabled(
+ IN UINTN PcieNum
+ )
+{
+ UINT64 SerDes1ProtocolMap;
+
+ SerDes1ProtocolMap = 0x0;
+
+ //
+ // Reading serdes map
+ //
+ GetSerdesProtocolMaps (&SerDes1ProtocolMap);
+
+ //
+ // Verify serdes line is configured in the map
+ //
+ if (PcieNum < NUM_PCIE_CONTROLLER) {
+ return IsSerDesLaneProtocolConfigured (SerDes1ProtocolMap, (PcieNum + BIT0));
+ } else {
+ DEBUG ((DEBUG_ERROR, "Device not supported\n"));
+ }
+
+ return FALSE;
+}
+
+/**
+ Function to set-up iATU outbound window for PCIe controller
+
+ @param Pcie Address of PCIe host controller
+ @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
+ @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
+ @param MemBase PCIe controller phy address Memory Space.
+ @param IoBase PCIe controller phy address IO Space.
+**/
+STATIC
+VOID
+PcieSetupAtu (
+ IN EFI_PHYSICAL_ADDRESS Pcie,
+ IN EFI_PHYSICAL_ADDRESS Cfg0Base,
+ IN EFI_PHYSICAL_ADDRESS Cfg1Base,
+ IN EFI_PHYSICAL_ADDRESS MemBase,
+ IN EFI_PHYSICAL_ADDRESS IoBase
+ )
+{
+
+ //
+ // iATU : OUTBOUND WINDOW 0 : CFG0
+ //
+ PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX0,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
+ Cfg0Base,
+ SEG_CFG_BUS,
+ SEG_CFG_SIZE);
+
+ //
+ // iATU : OUTBOUND WINDOW 1 : CFG1
+ PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX1,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
+ Cfg1Base,
+ SEG_CFG_BUS,
+ SEG_CFG_SIZE);
+ //
+ // iATU 2 : OUTBOUND WINDOW 2 : MEM
+ //
+ PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX2,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
+ MemBase,
+ SEG_MEM_BUS,
+ SEG_MEM_SIZE);
+
+ //
+ // iATU 3 : OUTBOUND WINDOW 3: IO
+ //
+ PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX3,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
+ IoBase,
+ SEG_IO_BUS,
+ SEG_IO_SIZE);
+
+}
+
+/**
+ Helper function to set-up PCIe controller
+
+ @param Pcie Address of PCIe host controller
+ @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
+ @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
+ @param MemBase PCIe controller phy address Memory Space.
+ @param IoBase PCIe controller phy address IO Space.
+
+**/
+STATIC
+VOID
+PcieSetupCntrl (
+ IN EFI_PHYSICAL_ADDRESS Pcie,
+ IN EFI_PHYSICAL_ADDRESS Cfg0Base,
+ IN EFI_PHYSICAL_ADDRESS Cfg1Base,
+ IN EFI_PHYSICAL_ADDRESS MemBase,
+ IN EFI_PHYSICAL_ADDRESS IoBase
+ )
+{
+ //
+ // iATU outbound set-up
+ //
+ PcieSetupAtu (Pcie, Cfg0Base, Cfg1Base, MemBase, IoBase);
+
+ //
+ // program correct class for RC
+ //
+ MmioWrite32 ((UINTN)Pcie + PCI_BASE_ADDRESS_0, (BIT0 - BIT0));
+ MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)BIT0);
+ MmioWrite32 ((UINTN)Pcie + PCI_CLASS_DEVICE, (UINT32)PCI_CLASS_BRIDGE_PCI);
+ MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)(BIT0 - BIT0));
+}
+
+/**
+ Return all the root bridge instances in an array.
+
+ @param Count Return the count of root bridge instances.
+
+ @return All the root bridge instances in an array.
+
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+ OUT UINTN *Count
+ )
+{
+ UINTN Idx;
+ INTN LinkUp;
+ UINT64 PciPhyMemAddr[NUM_PCIE_CONTROLLER];
+ UINT64 PciPhyCfg0Addr[NUM_PCIE_CONTROLLER];
+ UINT64 PciPhyCfg1Addr[NUM_PCIE_CONTROLLER];
+ UINT64 PciPhyIoAddr[NUM_PCIE_CONTROLLER];
+ UINT64 Regs[NUM_PCIE_CONTROLLER];
+
+ *Count = 0;
+
+ //
+ // Filling local array for
+ // PCIe controller Physical address space for Cfg0,Cfg1,Mem,IO
+ // Host Contoller address
+ //
+ for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
+ PciPhyMemAddr[Idx] = PCI_SEG0_PHY_MEM_BASE + (PCI_BASE_DIFF * Idx);
+ PciPhyCfg0Addr[Idx] = PCI_SEG0_PHY_CFG0_BASE + (PCI_BASE_DIFF * Idx);
+ PciPhyCfg1Addr[Idx] = PCI_SEG0_PHY_CFG1_BASE + (PCI_BASE_DIFF * Idx);
+ PciPhyIoAddr [Idx] = PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx);
+ Regs[Idx] = PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx);
+ }
+
+ for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
+ //
+ // Verify PCIe controller is enabled in Soc Serdes Map
+ //
+ if (!IsPcieNumEnabled (Idx)) {
+ DEBUG ((DEBUG_ERROR, "PCIE%d is disabled\n", (Idx + BIT0)));
+ //
+ // Continue with other PCIe controller
+ //
+ continue;
+ }
+ DEBUG ((DEBUG_INFO, "PCIE%d is Enabled\n", Idx + BIT0));
+
+ //
+ // Verify PCIe controller LTSSM state
+ //
+ LinkUp = PcieLinkUp(Regs[Idx]);
+ if (!LinkUp) {
+ //
+ // Let the user know there's no PCIe link
+ //
+ DEBUG ((DEBUG_INFO,"no link, regs @ 0x%lx\n", Regs[Idx]));
+ //
+ // Continue with other PCIe controller
+ //
+ continue;
+ }
+ DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + BIT0));
+
+ //
+ // Function to set up address translation unit outbound window for
+ // PCIe Controller
+ //
+ PcieSetupCntrl (Regs[Idx],
+ PciPhyCfg0Addr[Idx],
+ PciPhyCfg1Addr[Idx],
+ PciPhyMemAddr[Idx],
+ PciPhyIoAddr[Idx]);
+ *Count += BIT0;
+ break;
+ }
+
+ if (*Count == 0) {
+ return NULL;
+ } else {
+ return &mPciRootBridges[Idx];
+ }
+}
+
+/**
+ Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
+
+ @param Bridges The root bridge instances array.
+ @param Count The count of the array.
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+ PCI_ROOT_BRIDGE *Bridges,
+ UINTN Count
+ )
+{
+}
+
+/**
+ Inform the platform that the resource conflict happens.
+
+ @param HostBridgeHandle Handle of the Host Bridge.
+ @param Configuration Pointer to PCI I/O and PCI memory resource
+ descriptors. The Configuration contains the resources
+ for all the root bridges. The resource for each root
+ bridge is terminated with END descriptor and an
+ additional END is appended indicating the end of the
+ entire resources. The resource descriptor field
+ values follow the description in
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ .SubmitResources().
+
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+ EFI_HANDLE HostBridgeHandle,
+ VOID *Configuration
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ UINTN RootBridgeIndex;
+ DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
+
+ RootBridgeIndex = 0;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+ while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+ DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
+ for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ ASSERT (Descriptor->ResType <
+ ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));
+ DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrLen, Descriptor->AddrRangeMax
+ ));
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+ DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
+ Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
+ ((Descriptor->SpecificFlag &
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+ ) != 0) ? L" (Prefetchable)" : L""
+ ));
+ }
+ }
+ //
+ // Skip the END descriptor for root bridge
+ //
+ ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+ );
+ }
+
+ return;
+}
diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
new file mode 100644
index 0000000..f08ac60
--- /dev/null
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -0,0 +1,50 @@
+## @file
+# PCI Host Bridge Library instance for NXP ARM SOC
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PciHostBridgeLib
+ FILE_GUID = f4c99bcc-5c95-49ad-b0f3-fc5b611dc9c1
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciHostBridgeLib
+
+[Sources]
+ PciHostBridgeLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/Chassis/Chassis2/Chassis2.dec
+
+[LibraryClasses]
+ DebugLib
+ DevicePathLib
+ MemoryAllocationLib
+ PcdLib
+ SocLib
+ UefiBootServicesTableLib
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdNumPciController
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 34/39] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (32 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 33/39] Silicon/NXP: Implement PciHostBridgeLib support Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-20 8:40 ` Ard Biesheuvel
2018-04-20 15:15 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 35/39] Compilation: Update the fdf, dsc and dec files Meenakshi
` (7 subsequent siblings)
41 siblings, 2 replies; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
NXP SOC has mutiple PCIe RCs,Adding respective implementation of
EFI_CPU_IO2_PROTOCOL to provide Memory Space Read/Write functions
used by generic Host Bridge Driver including correct value for
the translation offset during MMIO accesses
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 529 ++++++++++++++++++++++
Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 ++
2 files changed, 577 insertions(+)
create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
new file mode 100644
index 0000000..b5fb72c
--- /dev/null
+++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
@@ -0,0 +1,529 @@
+/** @file
+ Produces the CPU I/O 2 Protocol.
+
+ Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+ Copyright 2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Pcie.h>
+#include <Protocol/CpuIo2.h>
+
+#define MAX_IO_PORT_ADDRESS PCI_SEG2_PORTIO_MAX
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE mHandle;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mInStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 0, // EfiCpuIoWidthFifoUint8
+ 0, // EfiCpuIoWidthFifoUint16
+ 0, // EfiCpuIoWidthFifoUint32
+ 0, // EfiCpuIoWidthFifoUint64
+ 1, // EfiCpuIoWidthFillUint8
+ 2, // EfiCpuIoWidthFillUint16
+ 4, // EfiCpuIoWidthFillUint32
+ 8 // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mOutStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 1, // EfiCpuIoWidthFifoUint8
+ 2, // EfiCpuIoWidthFifoUint16
+ 4, // EfiCpuIoWidthFifoUint32
+ 8, // EfiCpuIoWidthFifoUint64
+ 0, // EfiCpuIoWidthFillUint8
+ 0, // EfiCpuIoWidthFillUint16
+ 0, // EfiCpuIoWidthFillUint32
+ 0 // EfiCpuIoWidthFillUint64
+};
+
+/**
+ Check parameters to a CPU I/O 2 Protocol service request.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work.
+
+ @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The parameters for this request pass the checks.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+CpuIoCheckParameter (
+ IN BOOLEAN MmioOperation,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ UINT64 MaxCount;
+ UINT64 Limit;
+
+ //
+ // Check to see if Buffer is NULL
+ //
+ if (Buffer == NULL) {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Width is in the valid range
+ //
+ if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // For FIFO type, the target address won't increase during the access,
+ // so treat Count as 1
+ //
+ if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
+ Count = 1;
+ }
+
+ //
+ // Check to see if Width is in the valid range for I/O Port operations
+ //
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
+ if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Address is aligned
+ //
+ if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Check to see if any address associated with this transfer exceeds the maximum
+ // allowed address. The maximum address implied by the parameters passed in is
+ // Address + Size * Count. If the following condition is met, then the transfer
+ // is not supported.
+ //
+ // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
+ //
+ // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
+ // can also be the maximum integer value supported by the CPU, this range
+ // check must be adjusted to avoid all oveflow conditions.
+ //
+ Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
+ if (Count == 0) {
+ if (Address > Limit) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ } else {
+ MaxCount = RShiftU64 (Limit, Width);
+ if (MaxCount < (Count - 1)) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ }
+
+ //
+ // Check to see if Buffer is aligned
+ //
+ if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads memory-mapped registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceRead (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((Address >= PCI_SEG0_MMIO32_MIN) &&
+ (Address <= PCI_SEG0_MMIO32_MAX)) {
+ Address += PCI_SEG0_MMIO_MEMBASE;
+ } else if ((Address >= PCI_SEG1_MMIO32_MIN) &&
+ (Address <= PCI_SEG1_MMIO32_MAX)) {
+ Address += PCI_SEG1_MMIO_MEMBASE;
+ } else if ((Address >= PCI_SEG2_MMIO32_MIN) &&
+ (Address <= PCI_SEG2_MMIO32_MAX)) {
+ Address += PCI_SEG2_MMIO_MEMBASE;
+ } else if ((Address >= PCI_SEG3_MMIO32_MIN) &&
+ (Address <= PCI_SEG3_MMIO32_MAX)) {
+ Address += PCI_SEG3_MMIO_MEMBASE;
+ } else {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Writes memory-mapped registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceWrite (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((Address >= PCI_SEG0_MMIO32_MIN) &&
+ (Address <= PCI_SEG0_MMIO32_MAX)) {
+ Address += PCI_SEG0_MMIO_MEMBASE;
+ } else if ((Address >= PCI_SEG1_MMIO32_MIN) &&
+ (Address <= PCI_SEG1_MMIO32_MAX)) {
+ Address += PCI_SEG1_MMIO_MEMBASE;
+ } else if ((Address >= PCI_SEG2_MMIO32_MIN) &&
+ (Address <= PCI_SEG2_MMIO32_MAX)) {
+ Address += PCI_SEG2_MMIO_MEMBASE;
+ } else if ((Address >= PCI_SEG3_MMIO32_MIN) &&
+ (Address <= PCI_SEG3_MMIO32_MAX)) {
+ Address += PCI_SEG3_MMIO_MEMBASE;
+ } else {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads I/O registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceRead (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Write I/O registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceWrite (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ return EFI_SUCCESS;
+}
+
+//
+// CPU I/O 2 Protocol instance
+//
+STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
+ {
+ CpuMemoryServiceRead,
+ CpuMemoryServiceWrite
+ },
+ {
+ CpuIoServiceRead,
+ CpuIoServiceWrite
+ }
+};
+
+
+/**
+ The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+PciCpuIo2Initialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mHandle,
+ &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
new file mode 100644
index 0000000..25a1db1
--- /dev/null
+++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
@@ -0,0 +1,48 @@
+## @file
+# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PciCpuIo2Dxe
+ FILE_GUID = 7bff18d7-9aae-434b-9c06-f10a7e157eac
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PciCpuIo2Initialize
+
+[Sources]
+ PciCpuIo2Dxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
+
+[Protocols]
+ gEfiCpuIo2ProtocolGuid ## PRODUCES
+
+[Depex]
+ TRUE
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 35/39] Compilation: Update the fdf, dsc and dec files.
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (33 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 34/39] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-20 15:22 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 36/39] DWC3 : Add DWC3 USB controller initialization driver Meenakshi
` (6 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
LS1043A PCIe compilation and update firmware device,
description and declaration files.Defining Embedded Package
PCD which should be at least 20 for 64K PCIe IO size required
for CPU hob during PEI phase to Add IO space post PEI phase.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 16 ++++++++++++++++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 9 +++++++++
.../LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++
.../LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
Platform/NXP/NxpQoriqLs.dsc | 7 +++++++
Silicon/NXP/LS1043A/LS1043A.dsc | 4 ++++
Silicon/NXP/NxpQoriqLs.dec | 10 ++++++++++
7 files changed, 54 insertions(+)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index b2b514e..8cbaf88 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -42,6 +42,8 @@
BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
FpgaLib|Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
+ PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
+ PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
[PcdsFixedAtBuild.common]
@@ -79,6 +81,13 @@
gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000
gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000
+ #
+ # PCI PCDs.
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x10000
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x7FC
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
@@ -99,4 +108,11 @@
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
+ Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+ }
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
##
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 6b5b63f..7993bf1 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -130,6 +130,13 @@ READ_LOCK_STATUS = TRUE
INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
#
+ # PCI
+ #
+ INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
# Network modules
#
INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
@@ -154,6 +161,8 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
!endif
+ INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+
#
# FAT filesystem + GPT/MBR partitioning
#
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
index 7feac56..f2c8b66 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -65,3 +65,5 @@
gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
+ gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdRomSize
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
index 64c5612..1ef3292 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ // ROM Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdRomBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
// IFC region 1
//
// A-009241 : Unaligned write transactions to IFC may result in corruption of data
diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc
index 5987cd6..f5bb2e9 100644
--- a/Platform/NXP/NxpQoriqLs.dsc
+++ b/Platform/NXP/NxpQoriqLs.dsc
@@ -244,6 +244,8 @@
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|20
+
#
# Optional feature to help prevent EFI memory map fragments
# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
@@ -409,4 +411,9 @@
!endif #$(NO_SHELL_PROFILES)
}
+ #
+ # TFTP Shell Command
+ #
+ ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+
##
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc b/Silicon/NXP/LS1043A/LS1043A.dsc
index a4eb117..f3220fa 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc
@@ -64,6 +64,9 @@
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3
+ gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
+ gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
#
# Big Endian IPs
@@ -71,5 +74,6 @@
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE
##
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 3cb476d..a3508b5 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -79,6 +79,16 @@
gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129
gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A
gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0|UINT64|0x0000012B
+ gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x0|UINT64|0x0000012C
+ gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x0|UINT64|0x0000012D
+
+ #
+ # PCI PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x000001D0
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x000001D1
+ gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE|BOOLEAN|0x000001D2
+ gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|0|UINT32|0x000001D3
#
# IFC PCDs
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 36/39] DWC3 : Add DWC3 USB controller initialization driver.
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (34 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 35/39] Compilation: Update the fdf, dsc and dec files Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-20 15:30 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 37/39] LS2088 : Enable support of USB controller Meenakshi
` (5 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Add support of DWC3 controller driver which
Performs DWC3 controller initialization and
Register itself as NonDiscoverableMmioDevice
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c | 219 +++++++++++++++++++++++++++
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h | 142 +++++++++++++++++
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf | 48 ++++++
Silicon/NXP/NxpQoriqLs.dec | 5 +
4 files changed, 414 insertions(+)
create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
new file mode 100644
index 0000000..b08e19c
--- /dev/null
+++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
@@ -0,0 +1,219 @@
+/** @file
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Bitops.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/NonDiscoverableDeviceRegistrationLib.h>
+
+#include "UsbHcd.h"
+
+STATIC
+VOID
+XhciSetBeatBurstLength (
+ IN UINTN UsbReg
+ )
+{
+ Dwc3 *Dwc3Reg;
+
+ Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET);
+
+ MmioAndThenOr32 ((UINTN)&Dwc3Reg->GSBusCfg0, ~USB3_ENABLE_BEAT_BURST_MASK,
+ USB3_ENABLE_BEAT_BURST);
+ MmioOr32 ((UINTN)&Dwc3Reg->GSBusCfg1, USB3_SET_BEAT_BURST_LIMIT);
+
+ return;
+}
+
+STATIC
+VOID
+Dwc3SetFladj (
+ IN Dwc3 *Dwc3Reg,
+ IN UINT32 Val
+ )
+{
+ MmioOr32 ((UINTN)&Dwc3Reg->GFLAdj, GFLADJ_30MHZ_REG_SEL |
+ GFLADJ_30MHZ(Val));
+}
+
+VOID
+Dwc3SetMode (
+ IN Dwc3 *Dwc3Reg,
+ IN UINT32 Mode
+ )
+{
+ MmioAndThenOr32 ((UINTN)&Dwc3Reg->GCtl,
+ ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
+ DWC3_GCTL_PRTCAPDIR(Mode));
+}
+
+STATIC
+VOID
+Dwc3CoreSoftReset (
+ IN Dwc3 *Dwc3Reg
+ )
+{
+ MmioOr32 ((UINTN)&Dwc3Reg->GCtl, DWC3_GCTL_CORESOFTRESET);
+ MmioOr32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+ MmioOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+ MmioAnd32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], ~DWC3_GUSB3PIPECTL_PHYSOFTRST);
+ MmioAnd32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg, ~DWC3_GUSB2PHYCFG_PHYSOFTRST);
+ MmioAnd32 ((UINTN)&Dwc3Reg->GCtl, ~DWC3_GCTL_CORESOFTRESET);
+
+ return;
+}
+
+STATIC
+EFI_STATUS
+Dwc3CoreInit (
+ IN Dwc3 *Dwc3Reg
+ )
+{
+ UINT32 Revision;
+ UINT32 Reg;
+ UINTN Dwc3Hwparams1;
+
+ Revision = MmioRead32 ((UINTN)&Dwc3Reg->GSnpsId);
+ //
+ // This should read as 0x5533, ascii of U3(DWC_usb3) followed by revision number
+ //
+ if ((Revision & DWC3_GSNPSID_MASK) != DWC3_SYNOPSIS_ID) {
+ DEBUG ((DEBUG_ERROR,"This is not a DesignWare USB3 DRD Core.\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ Dwc3CoreSoftReset (Dwc3Reg);
+
+ Reg = MmioRead32 ((UINTN)&Dwc3Reg->GCtl);
+ Reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
+ Reg &= ~DWC3_GCTL_DISSCRAMBLE;
+
+ Dwc3Hwparams1 = MmioRead32 ((UINTN)&Dwc3Reg->GHwParams1);
+
+ if (DWC3_GHWPARAMS1_EN_PWROPT(Dwc3Hwparams1) == DWC3_GHWPARAMS1_EN_PWROPT_CLK) {
+ Reg &= ~DWC3_GCTL_DSBLCLKGTNG;
+ } else {
+ DEBUG ((DEBUG_ERROR,"No power optimization available.\n"));
+ }
+
+ if ((Revision & DWC3_RELEASE_MASK) < DWC3_RELEASE_190a) {
+ Reg |= DWC3_GCTL_U2RSTECN;
+ }
+
+ MmioWrite32 ((UINTN)&Dwc3Reg->GCtl, Reg);
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+XhciCoreInit (
+ IN UINTN UsbReg
+ )
+{
+ EFI_STATUS Status;
+ Dwc3 *Dwc3Reg;
+
+ Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET);
+
+ Status = Dwc3CoreInit (Dwc3Reg);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Dwc3CoreInit Failed for controller 0x%x (0x%x) \n",
+ UsbReg, Status));
+ return Status;
+ }
+
+ Dwc3SetMode (Dwc3Reg, DWC3_GCTL_PRTCAP_HOST);
+
+ Dwc3SetFladj (Dwc3Reg, GFLADJ_30MHZ_DEFAULT);
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+InitializeUsbController (
+ IN UINTN UsbReg
+ )
+{
+ EFI_STATUS Status;
+
+ Status = XhciCoreInit (UsbReg);
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Change beat burst and outstanding pipelined transfers requests
+ //
+ XhciSetBeatBurstLength (UsbReg);
+
+ return Status;
+}
+
+/**
+ The Entry Point of module. It follows the standard UEFI driver model.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeUsbHcd (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINT32 NumUsbController;
+ UINT32 ControllerAddr;
+
+ Status = EFI_SUCCESS;
+ NumUsbController = PcdGet32 (PcdNumUsbController);
+
+ while (NumUsbController) {
+ NumUsbController--;
+ ControllerAddr = PcdGet32 (PcdUsbBaseAddr) +
+ (NumUsbController * PcdGet32 (PcdUsbSize));
+
+ Status = InitializeUsbController (ControllerAddr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "USB Controller initialization Failed for %d (0x%x)\n",
+ ControllerAddr, Status));
+ continue;
+ }
+
+ Status = RegisterNonDiscoverableMmioDevice (
+ NonDiscoverableDeviceTypeXhci,
+ NonDiscoverableDeviceDmaTypeNonCoherent,
+ NULL,
+ NULL,
+ 1,
+ ControllerAddr, PcdGet32 (PcdUsbSize)
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to register USB device (0x%x) with error 0x%x \n",
+ ControllerAddr, Status));
+ }
+ }
+
+ return Status;
+}
diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
new file mode 100644
index 0000000..3237f5d
--- /dev/null
+++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
@@ -0,0 +1,142 @@
+/** @file
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __USB_HCD__
+#define __USB_HCD__
+
+/* Global constants */
+#define DWC3_GSNPSID_MASK 0xffff0000
+#define DWC3_SYNOPSIS_ID 0x55330000
+#define DWC3_RELEASE_MASK 0xffff
+#define DWC3_REG_OFFSET 0xC100
+#define DWC3_RELEASE_190a 0x190a
+
+/* Global Configuration Register */
+#define DWC3_GCTL_U2RSTECN BIT(16)
+#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
+#define DWC3_GCTL_PRTCAP_HOST 1
+#define DWC3_GCTL_PRTCAP_OTG 3
+#define DWC3_GCTL_CORESOFTRESET BIT(11)
+#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
+#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
+#define DWC3_GCTL_DISSCRAMBLE BIT(3)
+#define DWC3_GCTL_DSBLCLKGTNG BIT(0)
+
+/* Global HWPARAMS1 Register */
+#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
+#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
+
+/* Global USB2 PHY Configuration Register */
+#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
+
+/* Global USB3 PIPE Control Register */
+#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
+
+/* Global Frame Length Adjustment Register */
+#define GFLADJ_30MHZ_REG_SEL BIT(7)
+#define GFLADJ_30MHZ(n) ((n) & 0x3f)
+#define GFLADJ_30MHZ_DEFAULT 0x20
+
+/* Default to the FSL XHCI defines */
+#define USB3_ENABLE_BEAT_BURST 0xF
+#define USB3_ENABLE_BEAT_BURST_MASK 0xFF
+#define USB3_SET_BEAT_BURST_LIMIT 0xF00
+
+typedef struct {
+ UINT32 GEvntAdrLo;
+ UINT32 GEvntAdrHi;
+ UINT32 GEvntSiz;
+ UINT32 GEvntCount;
+} GEventBuffer;
+
+typedef struct {
+ UINT32 DDepCmdPar2;
+ UINT32 DDepCmdPar1;
+ UINT32 DDepCmdPar0;
+ UINT32 DDepCmd;
+} DPhysicalEndpoint;
+
+typedef struct {
+ UINT32 GSBusCfg0;
+ UINT32 GSBusCfg1;
+ UINT32 GTxThrCfg;
+ UINT32 GRxThrCfg;
+ UINT32 GCtl;
+ UINT32 Res1;
+ UINT32 GSts;
+ UINT32 Res2;
+ UINT32 GSnpsId;
+ UINT32 GGpio;
+ UINT32 GUid;
+ UINT32 GUctl;
+ UINT64 GBusErrAddr;
+ UINT64 GPrtbImap;
+ UINT32 GHwParams0;
+ UINT32 GHwParams1;
+ UINT32 GHwParams2;
+ UINT32 GHwParams3;
+ UINT32 GHwParams4;
+ UINT32 GHwParams5;
+ UINT32 GHwParams6;
+ UINT32 GHwParams7;
+ UINT32 GDbgFifoSpace;
+ UINT32 GDbgLtssm;
+ UINT32 GDbgLnmcc;
+ UINT32 GDbgBmu;
+ UINT32 GDbgLspMux;
+ UINT32 GDbgLsp;
+ UINT32 GDbgEpInfo0;
+ UINT32 GDbgEpInfo1;
+ UINT64 GPrtbImapHs;
+ UINT64 GPrtbImapFs;
+ UINT32 Res3[28];
+ UINT32 GUsb2PhyCfg[16];
+ UINT32 GUsb2I2cCtl[16];
+ UINT32 GUsb2PhyAcc[16];
+ UINT32 GUsb3PipeCtl[16];
+ UINT32 GTxFifoSiz[32];
+ UINT32 GRxFifoSiz[32];
+ GEventBuffer GEvntBuf[32];
+ UINT32 GHwParams8;
+ UINT32 Res4[11];
+ UINT32 GFLAdj;
+ UINT32 Res5[51];
+ UINT32 DCfg;
+ UINT32 DCtl;
+ UINT32 DEvten;
+ UINT32 DSts;
+ UINT32 DGCmdPar;
+ UINT32 DGCmd;
+ UINT32 Res6[2];
+ UINT32 DAlepena;
+ UINT32 Res7[55];
+ DPhysicalEndpoint DPhyEpCmd[32];
+ UINT32 Res8[128];
+ UINT32 OCfg;
+ UINT32 OCtl;
+ UINT32 OEvt;
+ UINT32 OEvtEn;
+ UINT32 OSts;
+ UINT32 Res9[3];
+ UINT32 AdpCfg;
+ UINT32 AdpCtl;
+ UINT32 AdpEvt;
+ UINT32 AdpEvten;
+ UINT32 BcCfg;
+ UINT32 Res10;
+ UINT32 BcEvt;
+ UINT32 BcEvten;
+} Dwc3;
+
+#endif
diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
new file mode 100644
index 0000000..cefb8bd
--- /dev/null
+++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
@@ -0,0 +1,48 @@
+# UsbHcd.inf
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001000A
+ BASE_NAME = UsbHcdDxe
+ FILE_GUID = 196e7c2a-37b2-4b85-8683-718588952449
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InitializeUsbHcd
+
+[Sources.common]
+ UsbHcd.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ IoLib
+ MemoryAllocationLib
+ NonDiscoverableDeviceRegistrationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[FixedPcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbSize
+
+[Depex]
+ TRUE
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index a3508b5..90e9957 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -83,6 +83,11 @@
gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x0|UINT64|0x0000012D
#
+ # USB PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|0|UINT32|0x00000170
+
+ #
# PCI PCDs
#
gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x000001D0
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 37/39] LS2088 : Enable support of USB controller
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (35 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 36/39] DWC3 : Add DWC3 USB controller initialization driver Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-20 15:30 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 38/39] Platform/NXP:PCIe enablement for LS1046A RDB Meenakshi
` (4 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Enable support of USB drives on ls2088 board.
LS2088 has DWC3 controller
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 1 +
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 13 +++++++++++++
Platform/NXP/NxpQoriqLs.dsc | 12 ++++++++++++
Silicon/NXP/LS2088A/LS2088A.dsc | 1 +
4 files changed, 27 insertions(+)
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
index 60449b5..4d32ea5 100755
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -114,3 +114,4 @@
ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
+ Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
index 785f88b..8688d85 100644
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
@@ -151,6 +151,19 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
!endif
+ INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+ #
+ # USB Support
+ #
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ INF Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
#
# FAT filesystem + GPT/MBR partitioning
#
diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc
index f5bb2e9..18e8cde 100644
--- a/Platform/NXP/NxpQoriqLs.dsc
+++ b/Platform/NXP/NxpQoriqLs.dsc
@@ -99,6 +99,7 @@
VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
@@ -367,6 +368,17 @@
!endif
#
+ # USB Support
+ #
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+ #
# FAT filesystem + GPT/MBR partitioning
#
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc b/Silicon/NXP/LS2088A/LS2088A.dsc
index 2cff40f..0d8fd82 100644
--- a/Silicon/NXP/LS2088A/LS2088A.dsc
+++ b/Silicon/NXP/LS2088A/LS2088A.dsc
@@ -68,5 +68,6 @@
gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|2
##
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 38/39] Platform/NXP:PCIe enablement for LS1046A RDB
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (36 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 37/39] LS2088 : Enable support of USB controller Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-20 15:33 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 39/39] Platform/NXP:PCIe enablement for LS2088A RDB Meenakshi
` (3 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
Compilation: Update the fdf, dsc and dec files.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
---
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 15 +++++++++++++++
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 9 +++++++++
.../LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++
.../NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
Silicon/NXP/LS1046A/LS1046A.dsc | 3 +++
5 files changed, 35 insertions(+)
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
index 36002d5..231207d 100644
--- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
@@ -41,6 +41,8 @@
IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
BoardLib|Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
FpgaLib|Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
+ PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
+ PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
[PcdsFixedAtBuild.common]
@@ -65,6 +67,7 @@
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE
#
# I2C controller Pcds
@@ -77,6 +80,12 @@
gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51
gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|100000
+ #
+ # PCI PCDs.
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x80000
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
@@ -90,5 +99,11 @@
Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+ Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+ }
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
##
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
index 834e3a4..3351a06 100644
--- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
@@ -123,6 +123,13 @@ READ_LOCK_STATUS = TRUE
INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
#
+ # PCI
+ #
+ INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
# Network modules
#
INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
@@ -147,6 +154,8 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
!endif
+ INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+
#
# FAT filesystem + GPT/MBR partitioning
#
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
index 49b57fc..5e09757 100644
--- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -42,6 +42,8 @@
gArmTokenSpaceGuid.PcdArmPrimaryCore
gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+ gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdRomSize
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
index 64c5612..1ef3292 100644
--- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ // ROM Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdRomBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
// IFC region 1
//
// A-009241 : Unaligned write transactions to IFC may result in corruption of data
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc b/Silicon/NXP/LS1046A/LS1046A.dsc
index 9f87028..59a6150 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc
@@ -64,5 +64,8 @@
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3
+ gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
+ gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
##
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 39/39] Platform/NXP:PCIe enablement for LS2088A RDB
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (37 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 38/39] Platform/NXP:PCIe enablement for LS1046A RDB Meenakshi
@ 2018-02-16 8:50 ` Meenakshi
2018-04-20 15:36 ` Leif Lindholm
2018-04-17 16:44 ` [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Leif Lindholm
` (2 subsequent siblings)
41 siblings, 1 reply; 254+ messages in thread
From: Meenakshi @ 2018-02-16 8:50 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
Compilation: Update the fdf, dsc and dec files.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
---
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 17 +++++++++++++++++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 9 +++++++++
.../Library/PlatformLib/ArmPlatformLib.inf | 2 ++
.../LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
Silicon/NXP/LS2088A/LS2088A.dsc | 3 +++
5 files changed, 37 insertions(+)
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
index 4d32ea5..1ae55d4 100755
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -43,6 +43,8 @@
BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
+ PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
+ PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
[PcdsFixedAtBuild.common]
@@ -97,6 +99,13 @@
gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x580000000
gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x580300000
+ #
+ # PCI PCDs.
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x80000
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
@@ -115,3 +124,11 @@
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+ Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+ }
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ ##
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
index 8688d85..35a79bd 100644
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
@@ -127,6 +127,13 @@ READ_LOCK_STATUS = TRUE
INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
#
+ # PCI
+ #
+ INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
# Network modules
#
INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
@@ -153,6 +160,8 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+ INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+
#
# USB Support
#
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
index f5e5abd..0b836a8 100644
--- a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -44,6 +44,8 @@
gArmTokenSpaceGuid.PcdArmPrimaryCore
gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+ gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdRomSize
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
index ccb49f6..8b2145b 100644
--- a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -80,6 +80,12 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ // ROM Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdRomBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
// IFC region 1
//
// A-009241 : Unaligned write transactions to IFC may result in corruption of data
diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc b/Silicon/NXP/LS2088A/LS2088A.dsc
index 0d8fd82..831edea 100644
--- a/Silicon/NXP/LS2088A/LS2088A.dsc
+++ b/Silicon/NXP/LS2088A/LS2088A.dsc
@@ -69,5 +69,8 @@
gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000
gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|2
+ gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|4
+ gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
+ gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
##
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-16 8:49 ` [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs Meenakshi
@ 2018-02-21 15:46 ` Leif Lindholm
2018-02-21 16:06 ` Laszlo Ersek
2018-02-22 4:49 ` Udit Kumar
0 siblings, 2 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-02-21 15:46 UTC (permalink / raw)
To: Meenakshi
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
Apologies for dropping the ball on this series during my sabbatical.
For this particular patch, I would still like to see a core library
provide the needed functionality. I just sent out an RFC of a possible
implementation.
Regardless, a key point is that this isn't about "big-endian", it is
about endianness opposite to the executing processor.
/
Leif
On Fri, Feb 16, 2018 at 02:19:57PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> This library add supports for BE read/write and other
> MMIO helper function.
> In this data swapped after reading from MMIO and before
> write using MMIO.
> It can be used by any module with BE address space.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/Library/BeIoLib.h | 332 ++++++++++++++++++++++++++
> Silicon/NXP/Library/BeIoLib/BeIoLib.c | 400 ++++++++++++++++++++++++++++++++
> Silicon/NXP/Library/BeIoLib/BeIoLib.inf | 31 +++
> 3 files changed, 763 insertions(+)
> create mode 100644 Silicon/NXP/Include/Library/BeIoLib.h
> create mode 100644 Silicon/NXP/Library/BeIoLib/BeIoLib.c
> create mode 100644 Silicon/NXP/Library/BeIoLib/BeIoLib.inf
>
> diff --git a/Silicon/NXP/Include/Library/BeIoLib.h b/Silicon/NXP/Include/Library/BeIoLib.h
> new file mode 100644
> index 0000000..a58883a
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/BeIoLib.h
> @@ -0,0 +1,332 @@
> +/** BeIoLib.h
> + *
> + * Copyright 2017 NXP
> + *
> + * This program and the accompanying materials
> + * are licensed and made available under the terms and conditions of the BSD License
> + * which accompanies this distribution. The full text of the license may be found at
> + * http://opensource.org/licenses/bsd-license.php
> + *
> + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> + *
> + **/
> +
> +#ifndef __BE_IOLIB_H__
> +#define __BE_IOLIB_H__
> +
> +#include <Base.h>
> +
> +/**
> + MmioRead8 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT8
> +EFIAPI
> +BeMmioRead8 (
> + IN UINTN Address
> + );
> +
> +/**
> + MmioRead16 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +BeMmioRead16 (
> + IN UINTN Address
> + );
> +
> +/**
> + MmioRead32 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +BeMmioRead32 (
> + IN UINTN Address
> + );
> +
> +/**
> + MmioRead64 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT64
> +EFIAPI
> +BeMmioRead64 (
> + IN UINTN Address
> + );
> +
> +/**
> + MmioWrite8 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT8
> +EFIAPI
> +BeMmioWrite8 (
> + IN UINTN Address,
> + IN UINT8 Value
> + );
> +
> +/**
> + MmioWrite16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +BeMmioWrite16 (
> + IN UINTN Address,
> + IN UINT16 Value
> + );
> +
> +/**
> + MmioWrite32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +BeMmioWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + );
> +
> +/**
> + MmioWrite64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +BeMmioWrite64 (
> + IN UINTN Address,
> + IN UINT64 Value
> + );
> +
> +/**
> + MmioAndThenOr8 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT8
> +EFIAPI
> +BeMmioAndThenOr8 (
> + IN UINTN Address,
> + IN UINT8 AndData,
> + IN UINT8 OrData
> + );
> +
> +/**
> + MmioAndThenOr16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +BeMmioAndThenOr16 (
> + IN UINTN Address,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + );
> +
> +/**
> + MmioAndThenOr32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +BeMmioAndThenOr32 (
> + IN UINTN Address,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + );
> +
> +/**
> + MmioAndThenOr64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +BeMmioAndThenOr64 (
> + IN UINTN Address,
> + IN UINT64 AndData,
> + IN UINT64 OrData
> + );
> +
> +/**
> + MmioOr8 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT8
> +EFIAPI
> +BeMmioOr8 (
> + IN UINTN Address,
> + IN UINT8 OrData
> + );
> +
> +/**
> + MmioOr16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +BeMmioOr16 (
> + IN UINTN Address,
> + IN UINT16 OrData
> + );
> +
> +/**
> + MmioOr32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +BeMmioOr32 (
> + IN UINTN Address,
> + IN UINT32 OrData
> + );
> +
> +/**
> + MmioOr64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +BeMmioOr64 (
> + IN UINTN Address,
> + IN UINT64 OrData
> + );
> +
> +/**
> + MmioAnd8 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT8
> +EFIAPI
> +BeMmioAnd8 (
> + IN UINTN Address,
> + IN UINT8 AndData
> + );
> +
> +/**
> + MmioAnd16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +BeMmioAnd16 (
> + IN UINTN Address,
> + IN UINT16 AndData
> + );
> +
> +/**
> + MmioAnd32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +BeMmioAnd32 (
> + IN UINTN Address,
> + IN UINT32 AndData
> + );
> +
> +/**
> + MmioAnd64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +BeMmioAnd64 (
> + IN UINTN Address,
> + IN UINT64 AndData
> + );
> +
> +#endif /* _BE_IOLIB_H */
> diff --git a/Silicon/NXP/Library/BeIoLib/BeIoLib.c b/Silicon/NXP/Library/BeIoLib/BeIoLib.c
> new file mode 100644
> index 0000000..b4b12ac
> --- /dev/null
> +++ b/Silicon/NXP/Library/BeIoLib/BeIoLib.c
> @@ -0,0 +1,400 @@
> +/** BeIoLib.c
> +
> + Provide MMIO APIs for BE modules.
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +
> +/**
> + MmioRead8 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT8
> +EFIAPI
> +BeMmioRead8 (
> + IN UINTN Address
> + )
> +{
> + return MmioRead8 (Address);
> +}
> +
> +/**
> + MmioRead16 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +BeMmioRead16 (
> + IN UINTN Address
> + )
> +{
> + return SwapBytes16 (MmioRead16 (Address));
> +}
> +
> +/**
> + MmioRead32 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +BeMmioRead32 (
> + IN UINTN Address
> + )
> +{
> + return SwapBytes32 (MmioRead32 (Address));
> +}
> +
> +/**
> + MmioRead64 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT64
> +EFIAPI
> +BeMmioRead64 (
> + IN UINTN Address
> + )
> +{
> + return SwapBytes64 (MmioRead64 (Address));
> +}
> +
> +/**
> + MmioWrite8 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT8
> +EFIAPI
> +BeMmioWrite8 (
> + IN UINTN Address,
> + IN UINT8 Value
> + )
> +{
> + return MmioWrite8 (Address, Value);
> +}
> +
> +/**
> + MmioWrite16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +BeMmioWrite16 (
> + IN UINTN Address,
> + IN UINT16 Value
> + )
> +{
> + return MmioWrite16 (Address, SwapBytes16 (Value));
> +}
> +
> +/**
> + MmioWrite32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +BeMmioWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + return MmioWrite32 (Address, SwapBytes32 (Value));
> +}
> +
> +/**
> + MmioWrite64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +BeMmioWrite64 (
> + IN UINTN Address,
> + IN UINT64 Value
> + )
> +{
> + return MmioWrite64 (Address, SwapBytes64 (Value));
> +}
> +
> +/**
> + MmioAndThenOr8 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT8
> +EFIAPI
> +BeMmioAndThenOr8 (
> + IN UINTN Address,
> + IN UINT8 AndData,
> + IN UINT8 OrData
> + )
> +{
> + return MmioAndThenOr8 (Address, AndData, OrData);
> +}
> +
> +/**
> + MmioAndThenOr16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +BeMmioAndThenOr16 (
> + IN UINTN Address,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + )
> +{
> + AndData = SwapBytes16 (AndData);
> + OrData = SwapBytes16 (OrData);
> +
> + return MmioAndThenOr16 (Address, AndData, OrData);
> +}
> +
> +/**
> + MmioAndThenOr32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +BeMmioAndThenOr32 (
> + IN UINTN Address,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + )
> +{
> + AndData = SwapBytes32 (AndData);
> + OrData = SwapBytes32 (OrData);
> +
> + return MmioAndThenOr32 (Address, AndData, OrData);
> +}
> +
> +/**
> + MmioAndThenOr64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +BeMmioAndThenOr64 (
> + IN UINTN Address,
> + IN UINT64 AndData,
> + IN UINT64 OrData
> + )
> +{
> + AndData = SwapBytes64 (AndData);
> + OrData = SwapBytes64 (OrData);
> +
> + return MmioAndThenOr64 (Address, AndData, OrData);
> +}
> +
> +/**
> + MmioOr8 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT8
> +EFIAPI
> +BeMmioOr8 (
> + IN UINTN Address,
> + IN UINT8 OrData
> + )
> +{
> + return MmioOr8 (Address, OrData);
> +}
> +
> +/**
> + MmioOr16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +BeMmioOr16 (
> + IN UINTN Address,
> + IN UINT16 OrData
> + )
> +{
> + return MmioOr16 (Address, SwapBytes16 (OrData));
> +}
> +
> +/**
> + MmioOr32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +BeMmioOr32 (
> + IN UINTN Address,
> + IN UINT32 OrData
> + )
> +{
> + return MmioOr32 (Address, SwapBytes32 (OrData));
> +}
> +
> +/**
> + MmioOr64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +BeMmioOr64 (
> + IN UINTN Address,
> + IN UINT64 OrData
> + )
> +{
> + return MmioOr64 (Address, SwapBytes64 (OrData));
> +}
> +
> +/**
> + MmioAnd8 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT8
> +EFIAPI
> +BeMmioAnd8 (
> + IN UINTN Address,
> + IN UINT8 AndData
> + )
> +{
> + return MmioAnd8 (Address, AndData);
> +}
> +
> +/**
> + MmioAnd16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +BeMmioAnd16 (
> + IN UINTN Address,
> + IN UINT16 AndData
> + )
> +{
> + return MmioAnd16 (Address, SwapBytes16 (AndData));
> +}
> +
> +/**
> + MmioAnd32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +BeMmioAnd32 (
> + IN UINTN Address,
> + IN UINT32 AndData
> + )
> +{
> + return MmioAnd32 (Address, SwapBytes32 (AndData));
> +}
> +
> +/**
> + MmioAnd64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +BeMmioAnd64 (
> + IN UINTN Address,
> + IN UINT64 AndData
> + )
> +{
> + return MmioAnd64 (Address, SwapBytes64 (AndData));
> +}
> diff --git a/Silicon/NXP/Library/BeIoLib/BeIoLib.inf b/Silicon/NXP/Library/BeIoLib/BeIoLib.inf
> new file mode 100644
> index 0000000..a1c19d0
> --- /dev/null
> +++ b/Silicon/NXP/Library/BeIoLib/BeIoLib.inf
> @@ -0,0 +1,31 @@
> +## @BeIoLib.inf
> +
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = BeIoLib
> + FILE_GUID = 28d77333-77eb-4faf-8735-130e5eb3e343
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = BeIoLib
> +
> +[Sources.common]
> + BeIoLib.c
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> + IoLib
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 09/39] Build : Add build script and environment script
2018-02-16 8:50 ` [PATCH edk2-platforms 09/39] Build : Add build script and environment script Meenakshi
@ 2018-02-21 16:02 ` Leif Lindholm
2018-02-22 4:58 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-02-21 16:02 UTC (permalink / raw)
To: Meenakshi
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Wasim Khan
We need to have a tree where we can build all of the platforms in a
predictable manner, so I am not inclined to take any platform-specific
build helper scripts.
(If a platform that needs some special scripts to post-process the
built image before writing it to a target, that is a different thing.)
What would be really useful here would be a Readme.md listing the
platforms supported, with a brief description, and the location of
their .dsc files (and any option that can be specified on the command
line at build time).
I would be more than happy to add some entries for these platforms to
(the entirely unofficial) uefi-tools set of helper scripts available
from https://git.linaro.org/uefi/uefi-tools.git.
(edk2-build.sh in there supports the same sort of 'figure out which
toolchain profile to use' as these scripts implement)
Also, feel free to add a link to your Readme.md from
https://github.com/tianocore/edk2-platforms#supported-platforms
/
Leif
On Fri, Feb 16, 2018 at 02:20:05PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> Build script and Environment setup script.
> Readme to explain how to run build script
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> ---
> Platform/NXP/Env.cshrc | 78 +++++++++++++++++++++++++++++++++
> Platform/NXP/Readme.md | 17 +++++++
> Platform/NXP/build.sh | 117 +++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 212 insertions(+)
> create mode 100755 Platform/NXP/Env.cshrc
> create mode 100644 Platform/NXP/Readme.md
> create mode 100755 Platform/NXP/build.sh
>
> diff --git a/Platform/NXP/Env.cshrc b/Platform/NXP/Env.cshrc
> new file mode 100755
> index 0000000..eb51018
> --- /dev/null
> +++ b/Platform/NXP/Env.cshrc
> @@ -0,0 +1,78 @@
> +# @file.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion
> +
> +if [ X"$CROSS_COMPILE_64" != X"" ]; then
> + ARM64_PREFIX="$CROSS_COMPILE_64"
> +elif [ X"$CROSS_COMPILE" != X"" ]; then
> + ARM64_PREFIX="$CROSS_COMPILE"
> +else
> + ARM64_PREFIX="aarch64-linux-gnu-"
> +fi
> +
> +GCC_UTILITY="${ARM64_PREFIX}gcc"
> +CheckGcc=`which $GCC_UTILITY >/dev/null 2>&1`
> +if [ "$?" -eq 0 ];then
> + GCC_VERSION=`$GCC_UTILITY -v 2>&1 | tail -n 1 | awk '{print $3}'`
> + MajorVersion=`echo $GCC_VERSION | cut -d . -f 1`
> + MinorVersion=`echo $GCC_VERSION | cut -d . -f 2`
> + GCC_ARCH_PREFIX=
> + NOTSUPPORTED=0
> +
> + case $MajorVersion in
> + 4)
> + case $MinorVersion in
> + 9)
> + GCC_ARCH_PREFIX="GCC49_AARCH64_PREFIX"
> + ;;
> + *)
> + NOTSUPPORTED=1
> + ;;
> + esac
> + ;;
> + 5)
> + case $MinorVersion in
> + 4)
> + GCC_ARCH_PREFIX="GCC5_AARCH64_PREFIX"
> + ;;
> + *)
> + GCC_ARCH_PREFIX="GCC5_AARCH64_PREFIX"
> + echo "Warning: ${GCC_UTILITY} version ($MajorVersion.$MinorVersion) has not been tested, please use at own risk."
> + ;;
> + esac
> + ;;
> + *)
> + NOTSUPPORTED=1
> + ;;
> + esac
> +
> + [ "$NOTSUPPORTED" -eq 1 ] && {
> + echo "Error: ${GCC_UTILITY} version ($MajorVersion.$MinorVersion) not supported ."
> + unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion
> + }
> +
> + [ -n "$GCC_ARCH_PREFIX" ] && {
> + export GCC_ARCH_PREFIX="$GCC_ARCH_PREFIX"
> + export "$GCC_ARCH_PREFIX=$ARM64_PREFIX"
> + }
> +
> + unset ARCH
> +else
> + echo "Error: ${GCC_UTILITY} not found. Please check PATH variable."
> + unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion
> +fi
> +
> +# Export the edk2-platforms path
> +export PACKAGES_PATH=`dirname \`dirname "$PWD"\``
> diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md
> new file mode 100644
> index 0000000..94174a7
> --- /dev/null
> +++ b/Platform/NXP/Readme.md
> @@ -0,0 +1,17 @@
> +Support for all NXP boards is available in this directory.
> +
> +# How to build
> +
> +build script source environment file Env.cshrc
> +
> +user need to run only build command.
> +
> +1. source Env.cshrc
> +
> +2. Build desired board
> + ./build.sh <SoC-name> <board-type> <build-candidate> <clean> (optional)
> +
> + Soc-name : LS1043 / LS1046 / LS2088
> + board-type : RDB / QDS
> + build-candidate : DEBUG / RELEASE
> +
> diff --git a/Platform/NXP/build.sh b/Platform/NXP/build.sh
> new file mode 100755
> index 0000000..eea83ee
> --- /dev/null
> +++ b/Platform/NXP/build.sh
> @@ -0,0 +1,117 @@
> +#!/bin/bash
> +
> +# UEFI build script for NXP LS SoCs
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +# source environment file
> +source Env.cshrc
> +
> +# Global Defaults
> +ARCH=AARCH64
> +TARGET_TOOLS=`echo $GCC_ARCH_PREFIX | cut -d _ -f 1`
> +BASE_DIR=../../..
> +
> +[ -z "$TARGET_TOOLS" ] && {
> + echo "TARGET_TOOLS not found. Please run \"source Env.cshrc\" ."
> + exit 1
> +}
> +
> +print_usage_banner()
> +{
> + echo ""
> + echo "This shell script expects:"
> + echo " Arg 1 (mandatory): SoC Type (can be LS1043 / LS1046 / LS2088)."
> + echo " Arg 2 (mandatory): Board Type (can be RDB / QDS)."
> + echo " Arg 3 (mandatory): Build candidate (can be RELEASE or DEBUG). By
> + default we build the RELEASE candidate."
> + echo " Arg 4 (optional): clean - To do a 'make clean' operation."
> +}
> +
> +# Check for total num of input arguments
> +if [[ "$#" -gt 4 ]]; then
> + echo "Illegal number of parameters"
> + print_usage_banner
> + exit
> +fi
> +
> +# Check for third parameter to be clean only
> +if [[ "$4" && $4 != "clean" ]]; then
> + echo "Error ! Either clean or emplty"
> + print_usage_banner
> + exit
> +fi
> +
> +# Check for input arguments
> +if [[ $1 == "" || $2 == "" || $3 == "" ]]; then
> + echo "Error !"
> + print_usage_banner
> + exit
> +fi
> +
> +# Check for input arguments
> +if [[ $1 != "LS1043" && $1 != "LS1046" && $1 != "LS2088" ]]; then
> + echo "Error ! Incorrect Soc Type specified."
> + print_usage_banner
> + exit
> +fi
> +
> +# Check for input arguments
> +if [[ $2 != "RDB" && $2 != "QDS" ]]; then
> + echo "Error ! Incorrect Board Type specified."
> + print_usage_banner
> + exit
> +fi
> +
> +# Check for input arguments
> +if [[ $3 != "RELEASE" ]]; then
> + if [[ $3 != "DEBUG" ]]; then
> + echo "Error ! Incorrect build target specified."
> + print_usage_banner
> + exit
> + fi
> +fi
> +
> +# Set Package drirectory
> +if [[ $2 == "RDB" ]]; then
> + PKG="aRdbPkg"
> + if [[ $2 == "QDS" ]]; then
> + PKG="aQdsPkg"
> + fi
> +fi
> +
> +echo ".........................................."
> +echo "Welcome to $1$PKG UEFI Build environment"
> +echo ".........................................."
> +
> +if [[ $4 == "clean" ]]; then
> + echo "Cleaning up the build directory '$BASE_DIR/Build/$1$PKG/'.."
> + rm -rf $BASE_DIR/Build/$1$PKG/*
> + exit
> +fi
> +
> +# Clean-up
> +set -e
> +shopt -s nocasematch
> +
> +#
> +# Setup workspace now
> +#
> +echo Initializing workspace
> +cd $BASE_DIR
> +
> +# Use the BaseTools in edk2
> +export EDK_TOOLS_PATH=`pwd`/BaseTools
> +source edksetup.sh BaseTools
> +
> +
> +build -p "$PACKAGES_PATH/Platform/NXP/$1$PKG/$1$PKG.dsc" -a $ARCH -t $TARGET_TOOLS -b $3
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-21 15:46 ` Leif Lindholm
@ 2018-02-21 16:06 ` Laszlo Ersek
2018-02-21 18:58 ` Leif Lindholm
2018-02-22 4:49 ` Udit Kumar
1 sibling, 1 reply; 254+ messages in thread
From: Laszlo Ersek @ 2018-02-21 16:06 UTC (permalink / raw)
To: Leif Lindholm; +Cc: Meenakshi, michael.d.kinney, edk2-devel, ard.biesheuvel
On 02/21/18 16:46, Leif Lindholm wrote:
> Apologies for dropping the ball on this series during my sabbatical.
>
> For this particular patch, I would still like to see a core library
> provide the needed functionality. I just sent out an RFC of a possible
> implementation.
>
> Regardless, a key point is that this isn't about "big-endian", it is
> about endianness opposite to the executing processor.
I commented on just this aspect under your RFC. I think I disagree, for
two reasons:
- As long as the specs are LE-only, "endianness opposite to the
executing processor" is needless complication / speculative generality
in my eyes.
- Even if we supported multiple endiannesses on the CPU front, the API
names should reflect the *device* byte order, not the CPU byte order.
Think of the case when the same platform device is integrated on board
B1 whose CPU is LE, and on board B2 whose CPU is BE. If we name the APIs
after the CPU byte order, then the same driver source code will be
misleading on one of the boards. Whereas, if we name the APIs after
device byte order, then the driver source code will be correct
regardless of board / CPU, and only the internal workings of the APIs
should change. For example, on a BE CPU / platform, the "normal" (LE)
IoLib class should be resolved to an instance that byte-swaps
internally, and the BE IoLib class should be resolved to an instance
that is transparent internally.
Thanks
Laszlo
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-21 16:06 ` Laszlo Ersek
@ 2018-02-21 18:58 ` Leif Lindholm
2018-02-22 4:45 ` Meenakshi Aggarwal
2018-02-22 8:34 ` Laszlo Ersek
0 siblings, 2 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-02-21 18:58 UTC (permalink / raw)
To: Laszlo Ersek; +Cc: Meenakshi, michael.d.kinney, edk2-devel, ard.biesheuvel
On Wed, Feb 21, 2018 at 05:06:02PM +0100, Laszlo Ersek wrote:
> On 02/21/18 16:46, Leif Lindholm wrote:
> > Apologies for dropping the ball on this series during my sabbatical.
> >
> > For this particular patch, I would still like to see a core library
> > provide the needed functionality. I just sent out an RFC of a possible
> > implementation.
> >
> > Regardless, a key point is that this isn't about "big-endian", it is
> > about endianness opposite to the executing processor.
>
> I commented on just this aspect under your RFC. I think I disagree, for
> two reasons:
>
> - As long as the specs are LE-only, "endianness opposite to the
> executing processor" is needless complication / speculative generality
> in my eyes.
HTON/NTOH?
The specs are not LE-only.
PI _is_ (at this point in time) LE-only.
UEFI leaves this entirely to architectural bindings.
For PI, this is mentioned in a single paragraph, repeated 4 times in
the PI 1.6 specification (due to it merging what was previously
separate documents).
> - Even if we supported multiple endiannesses on the CPU front, the API
> names should reflect the *device* byte order, not the CPU byte order.
> Think of the case when the same platform device is integrated on board
> B1 whose CPU is LE, and on board B2 whose CPU is BE.
The actual watchdog code in this series, and comments made on the
list, suggests that there exists variants of this _device_ with BE
or LE byte order.
If this is not the case, then yes, I agree that BE-naming makes sense.
So, Meenakshi - can you confirm that the Watchdog driver is expected
to be used against devices in both BE and LE mode?
If it is the case, maybe this library would make more sense as the
non-standard protocol you suggested in
https://www.mail-archive.com/edk2-devel@lists.01.org/msg17869.html
?
> If we name the APIs
> after the CPU byte order, then the same driver source code will be
> misleading on one of the boards. Whereas, if we name the APIs after
> device byte order, then the driver source code will be correct
> regardless of board / CPU, and only the internal workings of the APIs
> should change. For example, on a BE CPU / platform, the "normal" (LE)
> IoLib class should be resolved to an instance that byte-swaps
> internally, and the BE IoLib class should be resolved to an instance
> that is transparent internally.
Right.
But that brings back the complication as to how we have a driver that
needs an LE IO library to write output, and a BE IO library to
manipulate the hardware.
/
Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-21 18:58 ` Leif Lindholm
@ 2018-02-22 4:45 ` Meenakshi Aggarwal
2018-02-22 8:34 ` Laszlo Ersek
1 sibling, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-02-22 4:45 UTC (permalink / raw)
To: Leif Lindholm, Laszlo Ersek
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Thursday, February 22, 2018 12:28 AM
> To: Laszlo Ersek <lersek@redhat.com>
> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
> michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> ard.biesheuvel@linaro.org
> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
> for Big Endian Mmio APIs
>
> On Wed, Feb 21, 2018 at 05:06:02PM +0100, Laszlo Ersek wrote:
> > On 02/21/18 16:46, Leif Lindholm wrote:
> > > Apologies for dropping the ball on this series during my sabbatical.
> > >
> > > For this particular patch, I would still like to see a core library
> > > provide the needed functionality. I just sent out an RFC of a possible
> > > implementation.
> > >
> > > Regardless, a key point is that this isn't about "big-endian", it is
> > > about endianness opposite to the executing processor.
> >
> > I commented on just this aspect under your RFC. I think I disagree, for
> > two reasons:
> >
> > - As long as the specs are LE-only, "endianness opposite to the
> > executing processor" is needless complication / speculative generality
> > in my eyes.
>
> HTON/NTOH?
>
> The specs are not LE-only.
> PI _is_ (at this point in time) LE-only.
> UEFI leaves this entirely to architectural bindings.
>
> For PI, this is mentioned in a single paragraph, repeated 4 times in
> the PI 1.6 specification (due to it merging what was previously
> separate documents).
>
> > - Even if we supported multiple endiannesses on the CPU front, the API
> > names should reflect the *device* byte order, not the CPU byte order.
> > Think of the case when the same platform device is integrated on board
> > B1 whose CPU is LE, and on board B2 whose CPU is BE.
>
> The actual watchdog code in this series, and comments made on the
> list, suggests that there exists variants of this _device_ with BE
> or LE byte order.
>
> If this is not the case, then yes, I agree that BE-naming makes sense.
>
> So, Meenakshi - can you confirm that the Watchdog driver is expected
> to be used against devices in both BE and LE mode?
>
Yes Leif,
Watchdog is BE in this series of patches and will be LE for coming SoCs.
In this series, IFC is the example which is in BE mode for LS1043 and LS1046
and LE for LS2088.
> If it is the case, maybe this library would make more sense as the
> non-standard protocol you suggested in
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fw
> ww.mail-archive.com%2Fedk2-
> devel%40lists.01.org%2Fmsg17869.html&data=02%7C01%7Cmeenakshi.aggar
> wal%40nxp.com%7C3ba61129eca0405466d508d5795d1454%7C686ea1d3bc2b
> 4c6fa92cd99c5c301635%7C0%7C0%7C636548363050169302&sdata=pIcASmlSK
> CD0jsCvEMkKk2ikjSuD19lTa8xErcxaH4Y%3D&reserved=0
> ?
>
> > If we name the APIs
> > after the CPU byte order, then the same driver source code will be
> > misleading on one of the boards. Whereas, if we name the APIs after
> > device byte order, then the driver source code will be correct
> > regardless of board / CPU, and only the internal workings of the APIs
> > should change. For example, on a BE CPU / platform, the "normal" (LE)
> > IoLib class should be resolved to an instance that byte-swaps
> > internally, and the BE IoLib class should be resolved to an instance
> > that is transparent internally.
>
> Right.
>
> But that brings back the complication as to how we have a driver that
> needs an LE IO library to write output, and a BE IO library to
> manipulate the hardware.
>
Yes it is complicated, but we have similar situation.
> /
> Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-21 15:46 ` Leif Lindholm
2018-02-21 16:06 ` Laszlo Ersek
@ 2018-02-22 4:49 ` Udit Kumar
1 sibling, 0 replies; 254+ messages in thread
From: Udit Kumar @ 2018-02-22 4:49 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
edk2-devel@lists.01.org, Varun Sethi
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Wednesday, February 21, 2018 9:16 PM
> Subject: Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big
> Endian Mmio APIs
>
> Apologies for dropping the ball on this series during my sabbatical.
>
> For this particular patch, I would still like to see a core library provide the
> needed functionality. I just sent out an RFC of a possible implementation.
>
> Regardless, a key point is that this isn't about "big-endian", it is about
> endianness opposite to the executing processor.
Ok.
But We should know endianness of CPU and associated IP at the start.
Most of time We are in little endian mode, therefore we had BeMmioxx.
Anyway for me this is ok to rename as SwapMmioxx, if you are making
CPU endianness variant as well.
> /
> Leif
>
> On Fri, Feb 16, 2018 at 02:19:57PM +0530, Meenakshi wrote:
> > From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> >
> > This library add supports for BE read/write and other MMIO helper
> > function.
> > In this data swapped after reading from MMIO and before write using
> > MMIO.
> > It can be used by any module with BE address space.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> > ---
> > Silicon/NXP/Include/Library/BeIoLib.h | 332
> ++++++++++++++++++++++++++
> > Silicon/NXP/Library/BeIoLib/BeIoLib.c | 400
> ++++++++++++++++++++++++++++++++
> > Silicon/NXP/Library/BeIoLib/BeIoLib.inf | 31 +++
> > 3 files changed, 763 insertions(+)
> > create mode 100644 Silicon/NXP/Include/Library/BeIoLib.h
> > create mode 100644 Silicon/NXP/Library/BeIoLib/BeIoLib.c
> > create mode 100644 Silicon/NXP/Library/BeIoLib/BeIoLib.inf
> >
> > diff --git a/Silicon/NXP/Include/Library/BeIoLib.h
> > b/Silicon/NXP/Include/Library/BeIoLib.h
> > new file mode 100644
> > index 0000000..a58883a
> > --- /dev/null
> > +++ b/Silicon/NXP/Include/Library/BeIoLib.h
> > @@ -0,0 +1,332 @@
> > +/** BeIoLib.h
> > + *
> > + * Copyright 2017 NXP
> > + *
> > + * This program and the accompanying materials
> > + * are licensed and made available under the terms and conditions of
> > +the BSD License
> > + * which accompanies this distribution. The full text of the
> > +license may be found at
> > + *
> >
> +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> > +nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cudit.kumar%40
> >
> +nxp.com%7Cf911978f84484376f56e08d5794237e8%7C686ea1d3bc2b4c6fa92
> cd99c
> >
> +5c301635%7C0%7C0%7C636548247671415204&sdata=GTzQcn%2FbZmfV41%
> 2BwBELVN
> > +n1OUYJ3zz2ARFG6kF2rvcg%3D&reserved=0
> > + *
> > + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > +BASIS,
> > + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > + *
> > + **/
> > +
> > +#ifndef __BE_IOLIB_H__
> > +#define __BE_IOLIB_H__
> > +
> > +#include <Base.h>
> > +
> > +/**
> > + MmioRead8 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +
> > +**/
> > +UINT8
> > +EFIAPI
> > +BeMmioRead8 (
> > + IN UINTN Address
> > + );
> > +
> > +/**
> > + MmioRead16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +BeMmioRead16 (
> > + IN UINTN Address
> > + );
> > +
> > +/**
> > + MmioRead32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +BeMmioRead32 (
> > + IN UINTN Address
> > + );
> > +
> > +/**
> > + MmioRead64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +BeMmioRead64 (
> > + IN UINTN Address
> > + );
> > +
> > +/**
> > + MmioWrite8 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > +**/
> > +UINT8
> > +EFIAPI
> > +BeMmioWrite8 (
> > + IN UINTN Address,
> > + IN UINT8 Value
> > + );
> > +
> > +/**
> > + MmioWrite16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +BeMmioWrite16 (
> > + IN UINTN Address,
> > + IN UINT16 Value
> > + );
> > +
> > +/**
> > + MmioWrite32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +BeMmioWrite32 (
> > + IN UINTN Address,
> > + IN UINT32 Value
> > + );
> > +
> > +/**
> > + MmioWrite64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +BeMmioWrite64 (
> > + IN UINTN Address,
> > + IN UINT64 Value
> > + );
> > +
> > +/**
> > + MmioAndThenOr8 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > + @param OrData The value to OR with the result of the AND operation.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT8
> > +EFIAPI
> > +BeMmioAndThenOr8 (
> > + IN UINTN Address,
> > + IN UINT8 AndData,
> > + IN UINT8 OrData
> > + );
> > +
> > +/**
> > + MmioAndThenOr16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > + @param OrData The value to OR with the result of the AND operation.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +BeMmioAndThenOr16 (
> > + IN UINTN Address,
> > + IN UINT16 AndData,
> > + IN UINT16 OrData
> > + );
> > +
> > +/**
> > + MmioAndThenOr32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > + @param OrData The value to OR with the result of the AND operation.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +BeMmioAndThenOr32 (
> > + IN UINTN Address,
> > + IN UINT32 AndData,
> > + IN UINT32 OrData
> > + );
> > +
> > +/**
> > + MmioAndThenOr64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > + @param OrData The value to OR with the result of the AND operation.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +BeMmioAndThenOr64 (
> > + IN UINTN Address,
> > + IN UINT64 AndData,
> > + IN UINT64 OrData
> > + );
> > +
> > +/**
> > + MmioOr8 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param OrData The value to OR with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT8
> > +EFIAPI
> > +BeMmioOr8 (
> > + IN UINTN Address,
> > + IN UINT8 OrData
> > + );
> > +
> > +/**
> > + MmioOr16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param OrData The value to OR with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +BeMmioOr16 (
> > + IN UINTN Address,
> > + IN UINT16 OrData
> > + );
> > +
> > +/**
> > + MmioOr32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param OrData The value to OR with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +BeMmioOr32 (
> > + IN UINTN Address,
> > + IN UINT32 OrData
> > + );
> > +
> > +/**
> > + MmioOr64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param OrData The value to OR with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +BeMmioOr64 (
> > + IN UINTN Address,
> > + IN UINT64 OrData
> > + );
> > +
> > +/**
> > + MmioAnd8 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT8
> > +EFIAPI
> > +BeMmioAnd8 (
> > + IN UINTN Address,
> > + IN UINT8 AndData
> > + );
> > +
> > +/**
> > + MmioAnd16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +BeMmioAnd16 (
> > + IN UINTN Address,
> > + IN UINT16 AndData
> > + );
> > +
> > +/**
> > + MmioAnd32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +BeMmioAnd32 (
> > + IN UINTN Address,
> > + IN UINT32 AndData
> > + );
> > +
> > +/**
> > + MmioAnd64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +BeMmioAnd64 (
> > + IN UINTN Address,
> > + IN UINT64 AndData
> > + );
> > +
> > +#endif /* _BE_IOLIB_H */
> > diff --git a/Silicon/NXP/Library/BeIoLib/BeIoLib.c
> > b/Silicon/NXP/Library/BeIoLib/BeIoLib.c
> > new file mode 100644
> > index 0000000..b4b12ac
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/BeIoLib/BeIoLib.c
> > @@ -0,0 +1,400 @@
> > +/** BeIoLib.c
> > +
> > + Provide MMIO APIs for BE modules.
> > +
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials are licensed and made
> > + available under the terms and conditions of the BSD License which
> > + accompanies this distribution. The full text of the license may be
> > + found at
> > +
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop
> > + ensource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cudit.kumar%
> > +
> 40nxp.com%7Cf911978f84484376f56e08d5794237e8%7C686ea1d3bc2b4c6fa9
> 2cd
> > +
> 99c5c301635%7C0%7C0%7C636548247671415204&sdata=GTzQcn%2FbZmfV4
> 1%2BwB
> > + ELVNn1OUYJ3zz2ARFG6kF2rvcg%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#include <Base.h>
> > +#include <Library/BaseLib.h>
> > +#include <Library/IoLib.h>
> > +
> > +/**
> > + MmioRead8 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +
> > +**/
> > +UINT8
> > +EFIAPI
> > +BeMmioRead8 (
> > + IN UINTN Address
> > + )
> > +{
> > + return MmioRead8 (Address);
> > +}
> > +
> > +/**
> > + MmioRead16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +BeMmioRead16 (
> > + IN UINTN Address
> > + )
> > +{
> > + return SwapBytes16 (MmioRead16 (Address)); }
> > +
> > +/**
> > + MmioRead32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +BeMmioRead32 (
> > + IN UINTN Address
> > + )
> > +{
> > + return SwapBytes32 (MmioRead32 (Address)); }
> > +
> > +/**
> > + MmioRead64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +BeMmioRead64 (
> > + IN UINTN Address
> > + )
> > +{
> > + return SwapBytes64 (MmioRead64 (Address)); }
> > +
> > +/**
> > + MmioWrite8 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > +**/
> > +UINT8
> > +EFIAPI
> > +BeMmioWrite8 (
> > + IN UINTN Address,
> > + IN UINT8 Value
> > + )
> > +{
> > + return MmioWrite8 (Address, Value); }
> > +
> > +/**
> > + MmioWrite16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +BeMmioWrite16 (
> > + IN UINTN Address,
> > + IN UINT16 Value
> > + )
> > +{
> > + return MmioWrite16 (Address, SwapBytes16 (Value)); }
> > +
> > +/**
> > + MmioWrite32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +BeMmioWrite32 (
> > + IN UINTN Address,
> > + IN UINT32 Value
> > + )
> > +{
> > + return MmioWrite32 (Address, SwapBytes32 (Value)); }
> > +
> > +/**
> > + MmioWrite64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +BeMmioWrite64 (
> > + IN UINTN Address,
> > + IN UINT64 Value
> > + )
> > +{
> > + return MmioWrite64 (Address, SwapBytes64 (Value)); }
> > +
> > +/**
> > + MmioAndThenOr8 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > + @param OrData The value to OR with the result of the AND operation.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT8
> > +EFIAPI
> > +BeMmioAndThenOr8 (
> > + IN UINTN Address,
> > + IN UINT8 AndData,
> > + IN UINT8 OrData
> > + )
> > +{
> > + return MmioAndThenOr8 (Address, AndData, OrData); }
> > +
> > +/**
> > + MmioAndThenOr16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > + @param OrData The value to OR with the result of the AND operation.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +BeMmioAndThenOr16 (
> > + IN UINTN Address,
> > + IN UINT16 AndData,
> > + IN UINT16 OrData
> > + )
> > +{
> > + AndData = SwapBytes16 (AndData);
> > + OrData = SwapBytes16 (OrData);
> > +
> > + return MmioAndThenOr16 (Address, AndData, OrData); }
> > +
> > +/**
> > + MmioAndThenOr32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > + @param OrData The value to OR with the result of the AND operation.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +BeMmioAndThenOr32 (
> > + IN UINTN Address,
> > + IN UINT32 AndData,
> > + IN UINT32 OrData
> > + )
> > +{
> > + AndData = SwapBytes32 (AndData);
> > + OrData = SwapBytes32 (OrData);
> > +
> > + return MmioAndThenOr32 (Address, AndData, OrData); }
> > +
> > +/**
> > + MmioAndThenOr64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > + @param OrData The value to OR with the result of the AND operation.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +BeMmioAndThenOr64 (
> > + IN UINTN Address,
> > + IN UINT64 AndData,
> > + IN UINT64 OrData
> > + )
> > +{
> > + AndData = SwapBytes64 (AndData);
> > + OrData = SwapBytes64 (OrData);
> > +
> > + return MmioAndThenOr64 (Address, AndData, OrData); }
> > +
> > +/**
> > + MmioOr8 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param OrData The value to OR with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT8
> > +EFIAPI
> > +BeMmioOr8 (
> > + IN UINTN Address,
> > + IN UINT8 OrData
> > + )
> > +{
> > + return MmioOr8 (Address, OrData);
> > +}
> > +
> > +/**
> > + MmioOr16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param OrData The value to OR with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +BeMmioOr16 (
> > + IN UINTN Address,
> > + IN UINT16 OrData
> > + )
> > +{
> > + return MmioOr16 (Address, SwapBytes16 (OrData)); }
> > +
> > +/**
> > + MmioOr32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param OrData The value to OR with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +BeMmioOr32 (
> > + IN UINTN Address,
> > + IN UINT32 OrData
> > + )
> > +{
> > + return MmioOr32 (Address, SwapBytes32 (OrData)); }
> > +
> > +/**
> > + MmioOr64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param OrData The value to OR with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +BeMmioOr64 (
> > + IN UINTN Address,
> > + IN UINT64 OrData
> > + )
> > +{
> > + return MmioOr64 (Address, SwapBytes64 (OrData)); }
> > +
> > +/**
> > + MmioAnd8 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT8
> > +EFIAPI
> > +BeMmioAnd8 (
> > + IN UINTN Address,
> > + IN UINT8 AndData
> > + )
> > +{
> > + return MmioAnd8 (Address, AndData); }
> > +
> > +/**
> > + MmioAnd16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +BeMmioAnd16 (
> > + IN UINTN Address,
> > + IN UINT16 AndData
> > + )
> > +{
> > + return MmioAnd16 (Address, SwapBytes16 (AndData)); }
> > +
> > +/**
> > + MmioAnd32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +BeMmioAnd32 (
> > + IN UINTN Address,
> > + IN UINT32 AndData
> > + )
> > +{
> > + return MmioAnd32 (Address, SwapBytes32 (AndData)); }
> > +
> > +/**
> > + MmioAnd64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +BeMmioAnd64 (
> > + IN UINTN Address,
> > + IN UINT64 AndData
> > + )
> > +{
> > + return MmioAnd64 (Address, SwapBytes64 (AndData)); }
> > diff --git a/Silicon/NXP/Library/BeIoLib/BeIoLib.inf
> > b/Silicon/NXP/Library/BeIoLib/BeIoLib.inf
> > new file mode 100644
> > index 0000000..a1c19d0
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/BeIoLib/BeIoLib.inf
> > @@ -0,0 +1,31 @@
> > +## @BeIoLib.inf
> > +
> > +# Copyright 2017 NXP
> > +#
> > +# This program and the accompanying materials # are licensed and
> > +made available under the terms and conditions of the BSD License #
> > +which accompanies this distribution. The full text of the license
> > +may be found at #
> >
> +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> > +nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cudit.kumar%40
> >
> +nxp.com%7Cf911978f84484376f56e08d5794237e8%7C686ea1d3bc2b4c6fa92
> cd99c
> >
> +5c301635%7C0%7C0%7C636548247671415204&sdata=GTzQcn%2FbZmfV41%
> 2BwBELVN
> > +n1OUYJ3zz2ARFG6kF2rvcg%3D&reserved=0
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> > +#
> > +##
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001A
> > + BASE_NAME = BeIoLib
> > + FILE_GUID = 28d77333-77eb-4faf-8735-130e5eb3e343
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = BeIoLib
> > +
> > +[Sources.common]
> > + BeIoLib.c
> > +
> > +[Packages]
> > + MdeModulePkg/MdeModulePkg.dec
> > + MdePkg/MdePkg.dec
> > +
> > +[LibraryClasses]
> > + IoLib
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 09/39] Build : Add build script and environment script
2018-02-21 16:02 ` Leif Lindholm
@ 2018-02-22 4:58 ` Meenakshi Aggarwal
0 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-02-22 4:58 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
edk2-devel@lists.01.org, Udit Kumar, Varun Sethi, Wasim Khan
Thanks,
Meenakshi
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Wednesday, February 21, 2018 9:32 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; michael.d.kinney@intel.com; edk2-
> devel@lists.01.org; Udit Kumar <udit.kumar@nxp.com>; Varun Sethi
> <V.Sethi@nxp.com>; Wasim Khan <wasim.khan@nxp.com>
> Subject: Re: [PATCH edk2-platforms 09/39] Build : Add build script and
> environment script
>
> We need to have a tree where we can build all of the platforms in a
> predictable manner, so I am not inclined to take any platform-specific
> build helper scripts.
>
> (If a platform that needs some special scripts to post-process the
> built image before writing it to a target, that is a different thing.)
>
> What would be really useful here would be a Readme.md listing the
> platforms supported, with a brief description, and the location of
> their .dsc files (and any option that can be specified on the command
> line at build time).
>
Yes,
Sounds Valid.
Let me give a try to same.
> I would be more than happy to add some entries for these platforms to
> (the entirely unofficial) uefi-tools set of helper scripts available
> from
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.
> linaro.org%2Fuefi%2Fuefi-
> tools.git&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cdab85d129
> a9f4bfd36c608d579447d69%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
> 0%7C636548257431632170&sdata=VHMKWjdfr2FSy8uClW4%2BLeosuVPYpD
> wOYhrIIUop5w0%3D&reserved=0.
>
> (edk2-build.sh in there supports the same sort of 'figure out which
> toolchain profile to use' as these scripts implement)
>
> Also, feel free to add a link to your Readme.md from
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit
> hub.com%2Ftianocore%2Fedk2-platforms%23supported-
> platforms&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cdab85d1
> 29a9f4bfd36c608d579447d69%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%
> 7C0%7C636548257431788421&sdata=zrQfMandU%2BpMoSiZhc3R9%2F3vrRK
> 9tF5gMJX%2FgBrt5Lc%3D&reserved=0
>
> /
> Leif
>
> On Fri, Feb 16, 2018 at 02:20:05PM +0530, Meenakshi wrote:
> > From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> >
> > Build script and Environment setup script.
> > Readme to explain how to run build script
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> > Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> > ---
> > Platform/NXP/Env.cshrc | 78 +++++++++++++++++++++++++++++++++
> > Platform/NXP/Readme.md | 17 +++++++
> > Platform/NXP/build.sh | 117
> +++++++++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 212 insertions(+)
> > create mode 100755 Platform/NXP/Env.cshrc
> > create mode 100644 Platform/NXP/Readme.md
> > create mode 100755 Platform/NXP/build.sh
> >
> > diff --git a/Platform/NXP/Env.cshrc b/Platform/NXP/Env.cshrc
> > new file mode 100755
> > index 0000000..eb51018
> > --- /dev/null
> > +++ b/Platform/NXP/Env.cshrc
> > @@ -0,0 +1,78 @@
> > +# @file.
> > +#
> > +# Copyright 2017 NXP
> > +#
> > +# This program and the accompanying materials are licensed and made
> available under
> > +# the terms and conditions of the BSD License which accompanies this
> distribution.
> > +# The full text of the license may be found at
> > +#
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cdab85d
> 129a9f4bfd36c608d579447d69%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636548257431788421&sdata=Ut5kElH5tECkkHPBx53AJD0LeoqScX9w
> 6%2FoMz7eRclU%3D&reserved=0
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +#
> > +#
> > +
> > +unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion
> > +
> > +if [ X"$CROSS_COMPILE_64" != X"" ]; then
> > + ARM64_PREFIX="$CROSS_COMPILE_64"
> > +elif [ X"$CROSS_COMPILE" != X"" ]; then
> > + ARM64_PREFIX="$CROSS_COMPILE"
> > +else
> > + ARM64_PREFIX="aarch64-linux-gnu-"
> > +fi
> > +
> > +GCC_UTILITY="${ARM64_PREFIX}gcc"
> > +CheckGcc=`which $GCC_UTILITY >/dev/null 2>&1`
> > +if [ "$?" -eq 0 ];then
> > + GCC_VERSION=`$GCC_UTILITY -v 2>&1 | tail -n 1 | awk '{print $3}'`
> > + MajorVersion=`echo $GCC_VERSION | cut -d . -f 1`
> > + MinorVersion=`echo $GCC_VERSION | cut -d . -f 2`
> > + GCC_ARCH_PREFIX=
> > + NOTSUPPORTED=0
> > +
> > + case $MajorVersion in
> > + 4)
> > + case $MinorVersion in
> > + 9)
> > + GCC_ARCH_PREFIX="GCC49_AARCH64_PREFIX"
> > + ;;
> > + *)
> > + NOTSUPPORTED=1
> > + ;;
> > + esac
> > + ;;
> > + 5)
> > + case $MinorVersion in
> > + 4)
> > + GCC_ARCH_PREFIX="GCC5_AARCH64_PREFIX"
> > + ;;
> > + *)
> > + GCC_ARCH_PREFIX="GCC5_AARCH64_PREFIX"
> > + echo "Warning: ${GCC_UTILITY} version
> ($MajorVersion.$MinorVersion) has not been tested, please use at own
> risk."
> > + ;;
> > + esac
> > + ;;
> > + *)
> > + NOTSUPPORTED=1
> > + ;;
> > + esac
> > +
> > + [ "$NOTSUPPORTED" -eq 1 ] && {
> > + echo "Error: ${GCC_UTILITY} version ($MajorVersion.$MinorVersion)
> not supported ."
> > + unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion
> > + }
> > +
> > + [ -n "$GCC_ARCH_PREFIX" ] && {
> > + export GCC_ARCH_PREFIX="$GCC_ARCH_PREFIX"
> > + export "$GCC_ARCH_PREFIX=$ARM64_PREFIX"
> > + }
> > +
> > + unset ARCH
> > +else
> > + echo "Error: ${GCC_UTILITY} not found. Please check PATH variable."
> > + unset GCC_UTILITY GCC_VERSION MajorVersion MinorVersion
> > +fi
> > +
> > +# Export the edk2-platforms path
> > +export PACKAGES_PATH=`dirname \`dirname "$PWD"\``
> > diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md
> > new file mode 100644
> > index 0000000..94174a7
> > --- /dev/null
> > +++ b/Platform/NXP/Readme.md
> > @@ -0,0 +1,17 @@
> > +Support for all NXP boards is available in this directory.
> > +
> > +# How to build
> > +
> > +build script source environment file Env.cshrc
> > +
> > +user need to run only build command.
> > +
> > +1. source Env.cshrc
> > +
> > +2. Build desired board
> > + ./build.sh <SoC-name> <board-type> <build-candidate> <clean>
> (optional)
> > +
> > + Soc-name : LS1043 / LS1046 / LS2088
> > + board-type : RDB / QDS
> > + build-candidate : DEBUG / RELEASE
> > +
> > diff --git a/Platform/NXP/build.sh b/Platform/NXP/build.sh
> > new file mode 100755
> > index 0000000..eea83ee
> > --- /dev/null
> > +++ b/Platform/NXP/build.sh
> > @@ -0,0 +1,117 @@
> > +#!/bin/bash
> > +
> > +# UEFI build script for NXP LS SoCs
> > +#
> > +# Copyright 2017 NXP
> > +#
> > +# This program and the accompanying materials
> > +# are licensed and made available under the terms and conditions of the
> BSD License
> > +# which accompanies this distribution. The full text of the license may be
> found at
> > +#
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cdab85d
> 129a9f4bfd36c608d579447d69%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636548257431788421&sdata=Ut5kElH5tECkkHPBx53AJD0LeoqScX9w
> 6%2FoMz7eRclU%3D&reserved=0
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +#
> > +
> > +# source environment file
> > +source Env.cshrc
> > +
> > +# Global Defaults
> > +ARCH=AARCH64
> > +TARGET_TOOLS=`echo $GCC_ARCH_PREFIX | cut -d _ -f 1`
> > +BASE_DIR=../../..
> > +
> > +[ -z "$TARGET_TOOLS" ] && {
> > + echo "TARGET_TOOLS not found. Please run \"source Env.cshrc\" ."
> > + exit 1
> > +}
> > +
> > +print_usage_banner()
> > +{
> > + echo ""
> > + echo "This shell script expects:"
> > + echo " Arg 1 (mandatory): SoC Type (can be LS1043 / LS1046 / LS2088)."
> > + echo " Arg 2 (mandatory): Board Type (can be RDB / QDS)."
> > + echo " Arg 3 (mandatory): Build candidate (can be RELEASE or DEBUG).
> By
> > + default we build the RELEASE candidate."
> > + echo " Arg 4 (optional): clean - To do a 'make clean' operation."
> > +}
> > +
> > +# Check for total num of input arguments
> > +if [[ "$#" -gt 4 ]]; then
> > + echo "Illegal number of parameters"
> > + print_usage_banner
> > + exit
> > +fi
> > +
> > +# Check for third parameter to be clean only
> > +if [[ "$4" && $4 != "clean" ]]; then
> > + echo "Error ! Either clean or emplty"
> > + print_usage_banner
> > + exit
> > +fi
> > +
> > +# Check for input arguments
> > +if [[ $1 == "" || $2 == "" || $3 == "" ]]; then
> > + echo "Error !"
> > + print_usage_banner
> > + exit
> > +fi
> > +
> > +# Check for input arguments
> > +if [[ $1 != "LS1043" && $1 != "LS1046" && $1 != "LS2088" ]]; then
> > + echo "Error ! Incorrect Soc Type specified."
> > + print_usage_banner
> > + exit
> > +fi
> > +
> > +# Check for input arguments
> > +if [[ $2 != "RDB" && $2 != "QDS" ]]; then
> > + echo "Error ! Incorrect Board Type specified."
> > + print_usage_banner
> > + exit
> > +fi
> > +
> > +# Check for input arguments
> > +if [[ $3 != "RELEASE" ]]; then
> > + if [[ $3 != "DEBUG" ]]; then
> > + echo "Error ! Incorrect build target specified."
> > + print_usage_banner
> > + exit
> > + fi
> > +fi
> > +
> > +# Set Package drirectory
> > +if [[ $2 == "RDB" ]]; then
> > + PKG="aRdbPkg"
> > + if [[ $2 == "QDS" ]]; then
> > + PKG="aQdsPkg"
> > + fi
> > +fi
> > +
> > +echo ".........................................."
> > +echo "Welcome to $1$PKG UEFI Build environment"
> > +echo ".........................................."
> > +
> > +if [[ $4 == "clean" ]]; then
> > + echo "Cleaning up the build directory '$BASE_DIR/Build/$1$PKG/'.."
> > + rm -rf $BASE_DIR/Build/$1$PKG/*
> > + exit
> > +fi
> > +
> > +# Clean-up
> > +set -e
> > +shopt -s nocasematch
> > +
> > +#
> > +# Setup workspace now
> > +#
> > +echo Initializing workspace
> > +cd $BASE_DIR
> > +
> > +# Use the BaseTools in edk2
> > +export EDK_TOOLS_PATH=`pwd`/BaseTools
> > +source edksetup.sh BaseTools
> > +
> > +
> > +build -p "$PACKAGES_PATH/Platform/NXP/$1$PKG/$1$PKG.dsc" -a
> $ARCH -t $TARGET_TOOLS -b $3
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-21 18:58 ` Leif Lindholm
2018-02-22 4:45 ` Meenakshi Aggarwal
@ 2018-02-22 8:34 ` Laszlo Ersek
2018-02-22 11:52 ` Leif Lindholm
1 sibling, 1 reply; 254+ messages in thread
From: Laszlo Ersek @ 2018-02-22 8:34 UTC (permalink / raw)
To: Leif Lindholm; +Cc: Meenakshi, michael.d.kinney, edk2-devel, ard.biesheuvel
On 02/21/18 19:58, Leif Lindholm wrote:
> On Wed, Feb 21, 2018 at 05:06:02PM +0100, Laszlo Ersek wrote:
>> On 02/21/18 16:46, Leif Lindholm wrote:
>>> Apologies for dropping the ball on this series during my sabbatical.
>>>
>>> For this particular patch, I would still like to see a core library
>>> provide the needed functionality. I just sent out an RFC of a possible
>>> implementation.
>>>
>>> Regardless, a key point is that this isn't about "big-endian", it is
>>> about endianness opposite to the executing processor.
>>
>> I commented on just this aspect under your RFC. I think I disagree, for
>> two reasons:
>>
>> - As long as the specs are LE-only, "endianness opposite to the
>> executing processor" is needless complication / speculative generality
>> in my eyes.
>
> HTON/NTOH?
I don't understand this reference; host-to-net and net-to-host seem to
support my suggestion. "net" is always BE, and "host" is whatever it is.
So the API names are the same, but they work differently, dependent on
CPU byte order. (Apologies if you mean something else by HTON/NTOH.)
> The specs are not LE-only.
> PI _is_ (at this point in time) LE-only.
> UEFI leaves this entirely to architectural bindings.
I disagree; from UEFI 2.7:
1 Introduction
1.9 Conventions Used in this Document
1.9.1 Data Structure Descriptions
Supported processors are “little endian” machines. This distinction
means that the low-order byte of a multibyte data item in memory is
at the lowest address, while the high-order byte is at the highest
address. Some supported 64-bit processors may be configured for both
“little endian” and “big endian” operation. All implementations
designed to conform to this specification use “little endian”
operation.
> For PI, this is mentioned in a single paragraph, repeated 4 times in
> the PI 1.6 specification (due to it merging what was previously
> separate documents).
The same paragraph is present in UEFI 2.7.
>> - Even if we supported multiple endiannesses on the CPU front, the API
>> names should reflect the *device* byte order, not the CPU byte order.
>> Think of the case when the same platform device is integrated on board
>> B1 whose CPU is LE, and on board B2 whose CPU is BE.
>
> The actual watchdog code in this series, and comments made on the
> list, suggests that there exists variants of this _device_ with BE
> or LE byte order.
>
> If this is not the case, then yes, I agree that BE-naming makes sense.
In my opinion, even if the same device is seen in the wild with both
byte orders, the library class (the function names) should be designed
independently of CPU byte order. The device driver should pick one set
of functions dependent on device byte order (if indeed both byte orders
are seen on variants of the device). How those APIs map to CPU byte
order is a library instance detail.
> So, Meenakshi - can you confirm that the Watchdog driver is expected
> to be used against devices in both BE and LE mode?
>
> If it is the case, maybe this library would make more sense as the
> non-standard protocol you suggested in
> https://www.mail-archive.com/edk2-devel@lists.01.org/msg17869.html
> ?
Hmmm. Looking back at that email of mine, I think my "incomplete"
argument no longer stands. Jordan and Mike have explained to me since
that BaseLib (the class) has several APIs that are simply
un-implementable on various CPUs, for example it has a number of
Itanium-specific functions. Drivers that are not tied to IPF should
simply not call them. This is supposed to be by design.
Having skimmed your RFC, I also think I may have been wrong about
"overkill" originally. If there are many BE registers, swapping bytes
all the time explicitly is annoying, and people can mess up the word
size. So right now I feel that having these APIs in a new lib class
should be OK, as long as the function names are clear.
(Clearly I've been wrong already on this topic, see above, so do take my
points with a grain of salt :) )
>> If we name the APIs
>> after the CPU byte order, then the same driver source code will be
>> misleading on one of the boards. Whereas, if we name the APIs after
>> device byte order, then the driver source code will be correct
>> regardless of board / CPU, and only the internal workings of the APIs
>> should change. For example, on a BE CPU / platform, the "normal" (LE)
>> IoLib class should be resolved to an instance that byte-swaps
>> internally, and the BE IoLib class should be resolved to an instance
>> that is transparent internally.
>
> Right.
>
> But that brings back the complication as to how we have a driver that
> needs an LE IO library to write output, and a BE IO library to
> manipulate the hardware.
Can you please explain the "write output" use case more precisely?
My thinking would be this:
- Use the IoLib class directly for "writing output" in little endian
byte order (which is still unclear to me sorry).
- Have some function pointers (global variables, or members of a global
structure) that point to either IoLib or BeIoLib functions, dependent on
the detected device byte order. A module can be linked against both
IoLib and BeIoLib.
- Use those function pointers to talk to the device.
Thanks!
Laszlo
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-22 8:34 ` Laszlo Ersek
@ 2018-02-22 11:52 ` Leif Lindholm
2018-02-22 13:56 ` Laszlo Ersek
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-02-22 11:52 UTC (permalink / raw)
To: Laszlo Ersek; +Cc: Meenakshi, michael.d.kinney, edk2-devel, ard.biesheuvel
On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
> >> - As long as the specs are LE-only, "endianness opposite to the
> >> executing processor" is needless complication / speculative generality
> >> in my eyes.
> >
> > HTON/NTOH?
>
> I don't understand this reference; host-to-net and net-to-host seem to
> support my suggestion. "net" is always BE, and "host" is whatever it is.
> So the API names are the same, but they work differently, dependent on
> CPU byte order. (Apologies if you mean something else by HTON/NTOH.)
Well, they work differently depending on whether host and net byte
order differ or not :)
> > The specs are not LE-only.
> > PI _is_ (at this point in time) LE-only.
> > UEFI leaves this entirely to architectural bindings.
>
> I disagree; from UEFI 2.7:
>
> 1 Introduction
> 1.9 Conventions Used in this Document
> 1.9.1 Data Structure Descriptions
>
> Supported processors are “little endian” machines. This distinction
> means that the low-order byte of a multibyte data item in memory is
> at the lowest address, while the high-order byte is at the highest
> address. Some supported 64-bit processors may be configured for both
> “little endian” and “big endian” operation. All implementations
> designed to conform to this specification use “little endian”
> operation.
Interestingly, that paragraph never appeared when I searched through
the spec... (but I see it now you point it out).
Nevertheless, the spec is reflecting the current state of things. This
is UEFI, not ULEEFI, and is a BE-only architecture was ever added, the
spec would need to change.
> >> - Even if we supported multiple endiannesses on the CPU front, the API
> >> names should reflect the *device* byte order, not the CPU byte order.
> >> Think of the case when the same platform device is integrated on board
> >> B1 whose CPU is LE, and on board B2 whose CPU is BE.
> >
> > The actual watchdog code in this series, and comments made on the
> > list, suggests that there exists variants of this _device_ with BE
> > or LE byte order.
> >
> > If this is not the case, then yes, I agree that BE-naming makes sense.
>
> In my opinion, even if the same device is seen in the wild with both
> byte orders, the library class (the function names) should be designed
> independently of CPU byte order. The device driver should pick one set
> of functions dependent on device byte order (if indeed both byte orders
> are seen on variants of the device). How those APIs map to CPU byte
> order is a library instance detail.
>
> > So, Meenakshi - can you confirm that the Watchdog driver is expected
> > to be used against devices in both BE and LE mode?
> >
> > If it is the case, maybe this library would make more sense as the
> > non-standard protocol you suggested in
> > https://www.mail-archive.com/edk2-devel@lists.01.org/msg17869.html
> > ?
>
> Hmmm. Looking back at that email of mine, I think my "incomplete"
> argument no longer stands. Jordan and Mike have explained to me since
> that BaseLib (the class) has several APIs that are simply
> un-implementable on various CPUs, for example it has a number of
> Itanium-specific functions. Drivers that are not tied to IPF should
> simply not call them. This is supposed to be by design.
>
> Having skimmed your RFC, I also think I may have been wrong about
> "overkill" originally. If there are many BE registers, swapping bytes
> all the time explicitly is annoying, and people can mess up the word
> size. So right now I feel that having these APIs in a new lib class
> should be OK, as long as the function names are clear.
OK.
> (Clearly I've been wrong already on this topic, see above, so do take my
> points with a grain of salt :) )
>
> >> If we name the APIs
> >> after the CPU byte order, then the same driver source code will be
> >> misleading on one of the boards. Whereas, if we name the APIs after
> >> device byte order, then the driver source code will be correct
> >> regardless of board / CPU, and only the internal workings of the APIs
> >> should change. For example, on a BE CPU / platform, the "normal" (LE)
> >> IoLib class should be resolved to an instance that byte-swaps
> >> internally, and the BE IoLib class should be resolved to an instance
> >> that is transparent internally.
> >
> > Right.
> >
> > But that brings back the complication as to how we have a driver that
> > needs an LE IO library to write output, and a BE IO library to
> > manipulate the hardware.
>
> Can you please explain the "write output" use case more precisely?
>
> My thinking would be this:
>
> - Use the IoLib class directly for "writing output" in little endian
> byte order (which is still unclear to me sorry).
If the IoLib class is mapped to a an instance that byte-swaps (hereto
referred to as BeIoLib if IoLibSwap is unsuitable), would we not then
end up mapping the non-swapping, currently implemented in
BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
needing to duplicated all IoLib implementation .infs to provide an
IoLib and a BeIoLib for each?
It's at that point I burst an aneurysm.
Am I overthinking/underthinking this?
> - Have some function pointers (global variables, or members of a global
> structure) that point to either IoLib or BeIoLib functions, dependent on
> the detected device byte order. A module can be linked against both
> IoLib and BeIoLib.
>
> - Use those function pointers to talk to the device.
Yes, that does sound like the best solution for the code in the driver
regardless.
/
Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-22 11:52 ` Leif Lindholm
@ 2018-02-22 13:56 ` Laszlo Ersek
2018-02-23 8:40 ` Pankaj Bansal
2018-02-23 10:25 ` Udit Kumar
0 siblings, 2 replies; 254+ messages in thread
From: Laszlo Ersek @ 2018-02-22 13:56 UTC (permalink / raw)
To: Leif Lindholm; +Cc: Meenakshi, michael.d.kinney, edk2-devel, ard.biesheuvel
On 02/22/18 12:52, Leif Lindholm wrote:
> On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
>>> But that brings back the complication as to how we have a driver that
>>> needs an LE IO library to write output, and a BE IO library to
>>> manipulate the hardware.
>>
>> Can you please explain the "write output" use case more precisely?
>>
>> My thinking would be this:
>>
>> - Use the IoLib class directly for "writing output" in little endian
>> byte order (which is still unclear to me sorry).
>
> If the IoLib class is mapped to a an instance that byte-swaps (hereto
> referred to as BeIoLib if IoLibSwap is unsuitable), would we not then
> end up mapping the non-swapping, currently implemented in
> BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
> needing to duplicated all IoLib implementation .infs to provide an
> IoLib and a BeIoLib for each?
>
> It's at that point I burst an aneurysm.
> Am I overthinking/underthinking this?
We need two library classes, one for talking to LE devices and another
to BE devices. These should be usable in a given module at the same
time, as Ard says.
Both library classes need to work on both LE and BE CPUs (working from
your suggestion that UEFI might grow BE CPU support at some point).
Whether that is implemented by dumb, separate library instances
(yielding in total 2*2=4 library instances), or by smart,
CPU-endianness-agnostic library instances (in total, 2), is a different
question.
Note that such "smarts" could be less than trivial to implement:
- check CPU endianness in each library API?
- or check in the lib constructor only, and flip some function pointers?
- use a dynamic PCD for caching CPU endianness?
- use a HOB for the same?
- use a lib global variable (for caching only on the module level)?
I think the solution that saves the most on the *source* code size is:
- introduce the BeIoLib class
- duplicate the MMIO functions from BaseIoLibIntrinsic to the one
BeIoLib instance that we introduce
- modify the MMIO functions in *both* lib instances (original LE, and
new BE), like this:
- If the CPU architecture is known to be bound to a single endianness,
then hardcode the appropriate operation. This can be done with
preprocessor macros, or with the architecture support of INF files /
separate source files. For example, on IA32 and X64, the IoLib
instance should work transparently, unconditionally, and the BeIoLib
instance should byte-swap, unconditionally.
- On other CPU arches, all the wider-than-byte MMIO functions, in
*both* lib instances should do something like this:
//
// at file scope
//
STATIC CONST UINT16 mOne = 1;
//
// at function scope
//
if (*(CONST UINT8 *)&mOne == 1) {
//
// CPU in LE mode:
// - work transparently in the IoLib instance
// - byte-swap in the BeIoLib instance
//
} else {
//
// CPU in BE mode:
// - byte-swap in the IoLib instance
// - work transparently in the BeIoLib instance
//
}
Thanks,
Laszlo
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-22 13:56 ` Laszlo Ersek
@ 2018-02-23 8:40 ` Pankaj Bansal
2018-02-23 9:21 ` Laszlo Ersek
2018-02-23 10:25 ` Udit Kumar
1 sibling, 1 reply; 254+ messages in thread
From: Pankaj Bansal @ 2018-02-23 8:40 UTC (permalink / raw)
To: Laszlo Ersek, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org
Hi All
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Laszlo Ersek
> Sent: Thursday, February 22, 2018 7:26 PM
> To: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> ard.biesheuvel@linaro.org
> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
> for Big Endian Mmio APIs
>
> On 02/22/18 12:52, Leif Lindholm wrote:
> > On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
>
> >>> But that brings back the complication as to how we have a driver
> >>> that needs an LE IO library to write output, and a BE IO library to
> >>> manipulate the hardware.
> >>
> >> Can you please explain the "write output" use case more precisely?
> >>
> >> My thinking would be this:
> >>
> >> - Use the IoLib class directly for "writing output" in little endian
> >> byte order (which is still unclear to me sorry).
> >
> > If the IoLib class is mapped to a an instance that byte-swaps (hereto
> > referred to as BeIoLib if IoLibSwap is unsuitable), would we not then
> > end up mapping the non-swapping, currently implemented in
> > BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
> > needing to duplicated all IoLib implementation .infs to provide an
> > IoLib and a BeIoLib for each?
> >
> > It's at that point I burst an aneurysm.
> > Am I overthinking/underthinking this?
>
> We need two library classes, one for talking to LE devices and another to BE
> devices. These should be usable in a given module at the same time, as Ard
> says.
>
> Both library classes need to work on both LE and BE CPUs (working from your
> suggestion that UEFI might grow BE CPU support at some point).
> Whether that is implemented by dumb, separate library instances (yielding in
> total 2*2=4 library instances), or by smart, CPU-endianness-agnostic library
> instances (in total, 2), is a different question.
>
> Note that such "smarts" could be less than trivial to implement:
> - check CPU endianness in each library API?
> - or check in the lib constructor only, and flip some function pointers?
> - use a dynamic PCD for caching CPU endianness?
> - use a HOB for the same?
> - use a lib global variable (for caching only on the module level)?
>
> I think the solution that saves the most on the *source* code size is:
> - introduce the BeIoLib class
> - duplicate the MMIO functions from BaseIoLibIntrinsic to the one
> BeIoLib instance that we introduce
> - modify the MMIO functions in *both* lib instances (original LE, and
> new BE), like this:
>
> - If the CPU architecture is known to be bound to a single endianness,
> then hardcode the appropriate operation. This can be done with
> preprocessor macros, or with the architecture support of INF files /
> separate source files. For example, on IA32 and X64, the IoLib
> instance should work transparently, unconditionally, and the BeIoLib
> instance should byte-swap, unconditionally.
>
> - On other CPU arches, all the wider-than-byte MMIO functions, in
> *both* lib instances should do something like this:
>
> //
> // at file scope
> //
> STATIC CONST UINT16 mOne = 1;
>
> //
> // at function scope
> //
> if (*(CONST UINT8 *)&mOne == 1) {
> //
> // CPU in LE mode:
> // - work transparently in the IoLib instance
> // - byte-swap in the BeIoLib instance
> //
> } else {
> //
> // CPU in BE mode:
> // - byte-swap in the IoLib instance
> // - work transparently in the BeIoLib instance
> //
> }
I suggest this approach :
1. Add BeMmio* functions in existing IoLib. BeMmio* functions will swap the input before write and swap output after read and so on.
Mmio* functions will not perform any byte swapping
2. create second instance (a copy) of this IoLib for CPUs that are Big Endian. We can call it BigEndianIoLib.
In this library Mmio* functions will swap the input before write and swap output after read and so on.
BeMmio* functions will not perform any byte swapping.
3. Include the instance of IoLib in dsc file based on cpu endianness that the platform wants to use. i.e.
If BIG_ENDIAN == FALSE
IoLib | ..\..\..\IoLib
Else
IoLib | ..\..\..\BigEndianIoLib
4. The devices that are Big endian in platform will always call BeMmio* functions. They need not check CPU endianness.
5. The devices that are Little endian in platform will always call Mmio* functions. They need not check CPU endianness.
>
> Thanks,
> Laszlo
> _______________________________________________
> edk2-devel mailing list
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> devel&data=02%7C01%7Cpankaj.bansal%40nxp.com%7C930d96bb226d4491
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^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-23 8:40 ` Pankaj Bansal
@ 2018-02-23 9:21 ` Laszlo Ersek
2018-02-23 9:47 ` Meenakshi Aggarwal
2018-02-23 10:39 ` Udit Kumar
0 siblings, 2 replies; 254+ messages in thread
From: Laszlo Ersek @ 2018-02-23 9:21 UTC (permalink / raw)
To: Pankaj Bansal, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org
On 02/23/18 09:40, Pankaj Bansal wrote:
> Hi All
>
>> -----Original Message-----
>> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
>> Laszlo Ersek
>> Sent: Thursday, February 22, 2018 7:26 PM
>> To: Leif Lindholm <leif.lindholm@linaro.org>
>> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
>> ard.biesheuvel@linaro.org
>> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
>> for Big Endian Mmio APIs
>>
>> On 02/22/18 12:52, Leif Lindholm wrote:
>>> On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
>>
>>>>> But that brings back the complication as to how we have a driver
>>>>> that needs an LE IO library to write output, and a BE IO library to
>>>>> manipulate the hardware.
>>>>
>>>> Can you please explain the "write output" use case more precisely?
>>>>
>>>> My thinking would be this:
>>>>
>>>> - Use the IoLib class directly for "writing output" in little endian
>>>> byte order (which is still unclear to me sorry).
>>>
>>> If the IoLib class is mapped to a an instance that byte-swaps (hereto
>>> referred to as BeIoLib if IoLibSwap is unsuitable), would we not then
>>> end up mapping the non-swapping, currently implemented in
>>> BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
>>> needing to duplicated all IoLib implementation .infs to provide an
>>> IoLib and a BeIoLib for each?
>>>
>>> It's at that point I burst an aneurysm.
>>> Am I overthinking/underthinking this?
>>
>> We need two library classes, one for talking to LE devices and another to BE
>> devices. These should be usable in a given module at the same time, as Ard
>> says.
>>
>> Both library classes need to work on both LE and BE CPUs (working from your
>> suggestion that UEFI might grow BE CPU support at some point).
>> Whether that is implemented by dumb, separate library instances (yielding in
>> total 2*2=4 library instances), or by smart, CPU-endianness-agnostic library
>> instances (in total, 2), is a different question.
>>
>> Note that such "smarts" could be less than trivial to implement:
>> - check CPU endianness in each library API?
>> - or check in the lib constructor only, and flip some function pointers?
>> - use a dynamic PCD for caching CPU endianness?
>> - use a HOB for the same?
>> - use a lib global variable (for caching only on the module level)?
>>
>> I think the solution that saves the most on the *source* code size is:
>> - introduce the BeIoLib class
>> - duplicate the MMIO functions from BaseIoLibIntrinsic to the one
>> BeIoLib instance that we introduce
>> - modify the MMIO functions in *both* lib instances (original LE, and
>> new BE), like this:
>>
>> - If the CPU architecture is known to be bound to a single endianness,
>> then hardcode the appropriate operation. This can be done with
>> preprocessor macros, or with the architecture support of INF files /
>> separate source files. For example, on IA32 and X64, the IoLib
>> instance should work transparently, unconditionally, and the BeIoLib
>> instance should byte-swap, unconditionally.
>>
>> - On other CPU arches, all the wider-than-byte MMIO functions, in
>> *both* lib instances should do something like this:
>>
>> //
>> // at file scope
>> //
>> STATIC CONST UINT16 mOne = 1;
>>
>> //
>> // at function scope
>> //
>> if (*(CONST UINT8 *)&mOne == 1) {
>> //
>> // CPU in LE mode:
>> // - work transparently in the IoLib instance
>> // - byte-swap in the BeIoLib instance
>> //
>> } else {
>> //
>> // CPU in BE mode:
>> // - byte-swap in the IoLib instance
>> // - work transparently in the BeIoLib instance
>> //
>> }
>
> I suggest this approach :
>
> 1. Add BeMmio* functions in existing IoLib. BeMmio* functions will swap the input before write and swap output after read and so on.
> Mmio* functions will not perform any byte swapping
> 2. create second instance (a copy) of this IoLib for CPUs that are Big Endian. We can call it BigEndianIoLib.
> In this library Mmio* functions will swap the input before write and swap output after read and so on.
> BeMmio* functions will not perform any byte swapping.
> 3. Include the instance of IoLib in dsc file based on cpu endianness that the platform wants to use. i.e.
> If BIG_ENDIAN == FALSE
> IoLib | ..\..\..\IoLib
> Else
> IoLib | ..\..\..\BigEndianIoLib
> 4. The devices that are Big endian in platform will always call BeMmio* functions. They need not check CPU endianness.
> 5. The devices that are Little endian in platform will always call Mmio* functions. They need not check CPU endianness.
This can work too, but there is a downside: a large number of IoLib
instances exist in the tree already. If you add the BeMmio* functions to
the existent IoLib class, you'll have to duplicate the implementation to
all instances (identically, I think).
We've had this debate in the past. Back then it was about IoFifo
routines. I argued for an IoFifo lib class. Ultimately the IoFifo
routines were added to IoLib, and they had to be implemented for many
more library instances than client code would have actually required.
(See the series at 13a50a6fe1dc..2b631390f9f5.) In turn this runs the
risk of adding untested code.
Regarding the instances for BE CPUs: the name should likely be
BaseIoLibBigEndian or something similar. In lib instance names, the lib
class name is usually prefixed with the firmware phases where the
instance is usable, and hints about the implementation or constraints
are added as a suffix.
Also, if you want to support BE CPUs with separate IoLib instances, I'm
afraid that's going to lead to the combinatorial explosion that Leif
characterized as "burst[ing] an aneurysm". I think using the (seemingly
dynamic) "mOne" approach I suggested above, a smart compiler can
eliminate all the branches at build time.
Anyway, I don't insist; I just commented on an RFC.
Laszlo
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-23 9:21 ` Laszlo Ersek
@ 2018-02-23 9:47 ` Meenakshi Aggarwal
2018-02-23 10:17 ` Laszlo Ersek
2018-02-23 10:39 ` Udit Kumar
1 sibling, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-02-23 9:47 UTC (permalink / raw)
To: Laszlo Ersek, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org, Udit Kumar, Pankaj Bansal
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Laszlo Ersek
> Sent: Friday, February 23, 2018 2:51 PM
> To: Pankaj Bansal <pankaj.bansal@nxp.com>; Leif Lindholm
> <leif.lindholm@linaro.org>
> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> ard.biesheuvel@linaro.org
> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
> for Big Endian Mmio APIs
>
> On 02/23/18 09:40, Pankaj Bansal wrote:
> > Hi All
> >
> >> -----Original Message-----
> >> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> >> Laszlo Ersek
> >> Sent: Thursday, February 22, 2018 7:26 PM
> >> To: Leif Lindholm <leif.lindholm@linaro.org>
> >> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> >> ard.biesheuvel@linaro.org
> >> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add
> support
> >> for Big Endian Mmio APIs
> >>
> >> On 02/22/18 12:52, Leif Lindholm wrote:
> >>> On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
> >>
> >>>>> But that brings back the complication as to how we have a driver
> >>>>> that needs an LE IO library to write output, and a BE IO library to
> >>>>> manipulate the hardware.
> >>>>
> >>>> Can you please explain the "write output" use case more precisely?
> >>>>
> >>>> My thinking would be this:
> >>>>
> >>>> - Use the IoLib class directly for "writing output" in little endian
> >>>> byte order (which is still unclear to me sorry).
> >>>
> >>> If the IoLib class is mapped to a an instance that byte-swaps (hereto
> >>> referred to as BeIoLib if IoLibSwap is unsuitable), would we not then
> >>> end up mapping the non-swapping, currently implemented in
> >>> BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
> >>> needing to duplicated all IoLib implementation .infs to provide an
> >>> IoLib and a BeIoLib for each?
> >>>
> >>> It's at that point I burst an aneurysm.
> >>> Am I overthinking/underthinking this?
> >>
> >> We need two library classes, one for talking to LE devices and another to
> BE
> >> devices. These should be usable in a given module at the same time, as
> Ard
> >> says.
> >>
> >> Both library classes need to work on both LE and BE CPUs (working from
> your
> >> suggestion that UEFI might grow BE CPU support at some point).
> >> Whether that is implemented by dumb, separate library instances
> (yielding in
> >> total 2*2=4 library instances), or by smart, CPU-endianness-agnostic
> library
> >> instances (in total, 2), is a different question.
> >>
> >> Note that such "smarts" could be less than trivial to implement:
> >> - check CPU endianness in each library API?
> >> - or check in the lib constructor only, and flip some function pointers?
> >> - use a dynamic PCD for caching CPU endianness?
> >> - use a HOB for the same?
> >> - use a lib global variable (for caching only on the module level)?
> >>
> >> I think the solution that saves the most on the *source* code size is:
> >> - introduce the BeIoLib class
> >> - duplicate the MMIO functions from BaseIoLibIntrinsic to the one
> >> BeIoLib instance that we introduce
> >> - modify the MMIO functions in *both* lib instances (original LE, and
> >> new BE), like this:
> >>
> >> - If the CPU architecture is known to be bound to a single endianness,
> >> then hardcode the appropriate operation. This can be done with
> >> preprocessor macros, or with the architecture support of INF files /
> >> separate source files. For example, on IA32 and X64, the IoLib
> >> instance should work transparently, unconditionally, and the BeIoLib
> >> instance should byte-swap, unconditionally.
> >>
> >> - On other CPU arches, all the wider-than-byte MMIO functions, in
> >> *both* lib instances should do something like this:
> >>
> >> //
> >> // at file scope
> >> //
> >> STATIC CONST UINT16 mOne = 1;
> >>
> >> //
> >> // at function scope
> >> //
> >> if (*(CONST UINT8 *)&mOne == 1) {
> >> //
> >> // CPU in LE mode:
> >> // - work transparently in the IoLib instance
> >> // - byte-swap in the BeIoLib instance
> >> //
> >> } else {
> >> //
> >> // CPU in BE mode:
> >> // - byte-swap in the IoLib instance
> >> // - work transparently in the BeIoLib instance
> >> //
> >> }
> >
> > I suggest this approach :
> >
> > 1. Add BeMmio* functions in existing IoLib. BeMmio* functions will swap
> the input before write and swap output after read and so on.
> > Mmio* functions will not perform any byte swapping
> > 2. create second instance (a copy) of this IoLib for CPUs that are Big Endian.
> We can call it BigEndianIoLib.
> > In this library Mmio* functions will swap the input before write and swap
> output after read and so on.
> > BeMmio* functions will not perform any byte swapping.
> > 3. Include the instance of IoLib in dsc file based on cpu endianness that the
> platform wants to use. i.e.
> > If BIG_ENDIAN == FALSE
> > IoLib | ..\..\..\IoLib
> > Else
> > IoLib | ..\..\..\BigEndianIoLib
> > 4. The devices that are Big endian in platform will always call BeMmio*
> functions. They need not check CPU endianness.
> > 5. The devices that are Little endian in platform will always call Mmio*
> functions. They need not check CPU endianness.
>
> This can work too, but there is a downside: a large number of IoLib
> instances exist in the tree already. If you add the BeMmio* functions to
> the existent IoLib class, you'll have to duplicate the implementation to
> all instances (identically, I think).
>
> We've had this debate in the past. Back then it was about IoFifo
> routines. I argued for an IoFifo lib class. Ultimately the IoFifo
> routines were added to IoLib, and they had to be implemented for many
> more library instances than client code would have actually required.
> (See the series at 13a50a6fe1dc..2b631390f9f5.) In turn this runs the
> risk of adding untested code.
>
> Regarding the instances for BE CPUs: the name should likely be
> BaseIoLibBigEndian or something similar. In lib instance names, the lib
> class name is usually prefixed with the firmware phases where the
> instance is usable, and hints about the implementation or constraints
> are added as a suffix.
>
> Also, if you want to support BE CPUs with separate IoLib instances, I'm
> afraid that's going to lead to the combinatorial explosion that Leif
> characterized as "burst[ing] an aneurysm". I think using the (seemingly
> dynamic) "mOne" approach I suggested above, a smart compiler can
> eliminate all the branches at build time.
>
> Anyway, I don't insist; I just commented on an RFC.
>
The implementation suggested by you is pretty clean.
Just one concern on the naming convention,
STATIC CONST UINT16 mOne = 1;
//
// at function scope
//
if (*(CONST UINT8 *)&mOne == 1) {
//
// CPU in LE mode:
// - work transparently in the IoLib instance
// - byte-swap in the BeIoLib instance
//
} else {
//
// CPU in BE mode:
// - byte-swap in the IoLib instance
// - work transparently in the BeIoLib instance
//
}
If we keep it BeIoLib, then it is not justifying the case for BE CPUs.
I mean, for a BE CPU architecture, it look weird to call BeIoLib APIs when swap is needed.
So, i think, we should name it IoLibSwap.
> Laszlo
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.01.org%2Fmailman%2Flistinfo%2Fedk2-
> devel&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C932b04d97a2
> 648845d9208d57a9ece38%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> %7C636549744880515349&sdata=SBrgvgbrsk3ViYygJdNIzy%2FuB19pWeSvHln
> IMX6ae90%3D&reserved=0
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-23 9:47 ` Meenakshi Aggarwal
@ 2018-02-23 10:17 ` Laszlo Ersek
0 siblings, 0 replies; 254+ messages in thread
From: Laszlo Ersek @ 2018-02-23 10:17 UTC (permalink / raw)
To: Meenakshi Aggarwal, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org, Udit Kumar, Pankaj Bansal
On 02/23/18 10:47, Meenakshi Aggarwal wrote:
>
>
>> -----Original Message-----
>> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
>> Laszlo Ersek
>> Sent: Friday, February 23, 2018 2:51 PM
>> To: Pankaj Bansal <pankaj.bansal@nxp.com>; Leif Lindholm
>> <leif.lindholm@linaro.org>
>> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
>> ard.biesheuvel@linaro.org
>> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
>> for Big Endian Mmio APIs
>>
>> On 02/23/18 09:40, Pankaj Bansal wrote:
>>> Hi All
>>>
>>>> -----Original Message-----
>>>> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
>>>> Laszlo Ersek
>>>> Sent: Thursday, February 22, 2018 7:26 PM
>>>> To: Leif Lindholm <leif.lindholm@linaro.org>
>>>> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
>>>> ard.biesheuvel@linaro.org
>>>> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add
>> support
>>>> for Big Endian Mmio APIs
>>>>
>>>> On 02/22/18 12:52, Leif Lindholm wrote:
>>>>> On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
>>>>
>>>>>>> But that brings back the complication as to how we have a driver
>>>>>>> that needs an LE IO library to write output, and a BE IO library to
>>>>>>> manipulate the hardware.
>>>>>>
>>>>>> Can you please explain the "write output" use case more precisely?
>>>>>>
>>>>>> My thinking would be this:
>>>>>>
>>>>>> - Use the IoLib class directly for "writing output" in little endian
>>>>>> byte order (which is still unclear to me sorry).
>>>>>
>>>>> If the IoLib class is mapped to a an instance that byte-swaps (hereto
>>>>> referred to as BeIoLib if IoLibSwap is unsuitable), would we not then
>>>>> end up mapping the non-swapping, currently implemented in
>>>>> BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
>>>>> needing to duplicated all IoLib implementation .infs to provide an
>>>>> IoLib and a BeIoLib for each?
>>>>>
>>>>> It's at that point I burst an aneurysm.
>>>>> Am I overthinking/underthinking this?
>>>>
>>>> We need two library classes, one for talking to LE devices and another to
>> BE
>>>> devices. These should be usable in a given module at the same time, as
>> Ard
>>>> says.
>>>>
>>>> Both library classes need to work on both LE and BE CPUs (working from
>> your
>>>> suggestion that UEFI might grow BE CPU support at some point).
>>>> Whether that is implemented by dumb, separate library instances
>> (yielding in
>>>> total 2*2=4 library instances), or by smart, CPU-endianness-agnostic
>> library
>>>> instances (in total, 2), is a different question.
>>>>
>>>> Note that such "smarts" could be less than trivial to implement:
>>>> - check CPU endianness in each library API?
>>>> - or check in the lib constructor only, and flip some function pointers?
>>>> - use a dynamic PCD for caching CPU endianness?
>>>> - use a HOB for the same?
>>>> - use a lib global variable (for caching only on the module level)?
>>>>
>>>> I think the solution that saves the most on the *source* code size is:
>>>> - introduce the BeIoLib class
>>>> - duplicate the MMIO functions from BaseIoLibIntrinsic to the one
>>>> BeIoLib instance that we introduce
>>>> - modify the MMIO functions in *both* lib instances (original LE, and
>>>> new BE), like this:
>>>>
>>>> - If the CPU architecture is known to be bound to a single endianness,
>>>> then hardcode the appropriate operation. This can be done with
>>>> preprocessor macros, or with the architecture support of INF files /
>>>> separate source files. For example, on IA32 and X64, the IoLib
>>>> instance should work transparently, unconditionally, and the BeIoLib
>>>> instance should byte-swap, unconditionally.
>>>>
>>>> - On other CPU arches, all the wider-than-byte MMIO functions, in
>>>> *both* lib instances should do something like this:
>>>>
>>>> //
>>>> // at file scope
>>>> //
>>>> STATIC CONST UINT16 mOne = 1;
>>>>
>>>> //
>>>> // at function scope
>>>> //
>>>> if (*(CONST UINT8 *)&mOne == 1) {
>>>> //
>>>> // CPU in LE mode:
>>>> // - work transparently in the IoLib instance
>>>> // - byte-swap in the BeIoLib instance
>>>> //
>>>> } else {
>>>> //
>>>> // CPU in BE mode:
>>>> // - byte-swap in the IoLib instance
>>>> // - work transparently in the BeIoLib instance
>>>> //
>>>> }
>>>
>>> I suggest this approach :
>>>
>>> 1. Add BeMmio* functions in existing IoLib. BeMmio* functions will swap
>> the input before write and swap output after read and so on.
>>> Mmio* functions will not perform any byte swapping
>>> 2. create second instance (a copy) of this IoLib for CPUs that are Big Endian.
>> We can call it BigEndianIoLib.
>>> In this library Mmio* functions will swap the input before write and swap
>> output after read and so on.
>>> BeMmio* functions will not perform any byte swapping.
>>> 3. Include the instance of IoLib in dsc file based on cpu endianness that the
>> platform wants to use. i.e.
>>> If BIG_ENDIAN == FALSE
>>> IoLib | ..\..\..\IoLib
>>> Else
>>> IoLib | ..\..\..\BigEndianIoLib
>>> 4. The devices that are Big endian in platform will always call BeMmio*
>> functions. They need not check CPU endianness.
>>> 5. The devices that are Little endian in platform will always call Mmio*
>> functions. They need not check CPU endianness.
>>
>> This can work too, but there is a downside: a large number of IoLib
>> instances exist in the tree already. If you add the BeMmio* functions to
>> the existent IoLib class, you'll have to duplicate the implementation to
>> all instances (identically, I think).
>>
>> We've had this debate in the past. Back then it was about IoFifo
>> routines. I argued for an IoFifo lib class. Ultimately the IoFifo
>> routines were added to IoLib, and they had to be implemented for many
>> more library instances than client code would have actually required.
>> (See the series at 13a50a6fe1dc..2b631390f9f5.) In turn this runs the
>> risk of adding untested code.
>>
>> Regarding the instances for BE CPUs: the name should likely be
>> BaseIoLibBigEndian or something similar. In lib instance names, the lib
>> class name is usually prefixed with the firmware phases where the
>> instance is usable, and hints about the implementation or constraints
>> are added as a suffix.
>>
>> Also, if you want to support BE CPUs with separate IoLib instances, I'm
>> afraid that's going to lead to the combinatorial explosion that Leif
>> characterized as "burst[ing] an aneurysm". I think using the (seemingly
>> dynamic) "mOne" approach I suggested above, a smart compiler can
>> eliminate all the branches at build time.
>>
>> Anyway, I don't insist; I just commented on an RFC.
>>
> The implementation suggested by you is pretty clean.
>
> Just one concern on the naming convention,
>
> STATIC CONST UINT16 mOne = 1;
>
> //
> // at function scope
> //
> if (*(CONST UINT8 *)&mOne == 1) {
> //
> // CPU in LE mode:
> // - work transparently in the IoLib instance
> // - byte-swap in the BeIoLib instance
> //
> } else {
> //
> // CPU in BE mode:
> // - byte-swap in the IoLib instance
> // - work transparently in the BeIoLib instance
> //
> }
>
> If we keep it BeIoLib, then it is not justifying the case for BE CPUs.
> I mean, for a BE CPU architecture, it look weird to call BeIoLib APIs when swap is needed.
Sorry, I don't undertand. The "Be" in BeIoLib refers to device byte
order, it has nothing to do with the CPU byte order.
Calling "BeIoLib APIs" is dictated by the device in question. The caller
(= the driver code) should be left entirely unaware of the CPU byte
order. "When swap is needed" is a question to be handled within the
library instance; "byte swapping" is a concept that should be totally
absent from driver code.
Laszlo
> So, i think, we should name it IoLibSwap.
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-22 13:56 ` Laszlo Ersek
2018-02-23 8:40 ` Pankaj Bansal
@ 2018-02-23 10:25 ` Udit Kumar
2018-02-23 10:47 ` Laszlo Ersek
1 sibling, 1 reply; 254+ messages in thread
From: Udit Kumar @ 2018-02-23 10:25 UTC (permalink / raw)
To: Laszlo Ersek, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Laszlo Ersek
> Sent: Thursday, February 22, 2018 7:26 PM
> To: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> ard.biesheuvel@linaro.org
> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
> for Big Endian Mmio APIs
>
> On 02/22/18 12:52, Leif Lindholm wrote:
> > On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
>
> >>> But that brings back the complication as to how we have a driver
> >>> that needs an LE IO library to write output, and a BE IO library to
> >>> manipulate the hardware.
> >>
> >> Can you please explain the "write output" use case more precisely?
> >>
> >> My thinking would be this:
> >>
> >> - Use the IoLib class directly for "writing output" in little endian
> >> byte order (which is still unclear to me sorry).
> >
> > If the IoLib class is mapped to a an instance that byte-swaps (hereto
> > referred to as BeIoLib if IoLibSwap is unsuitable), would we not then
> > end up mapping the non-swapping, currently implemented in
> > BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
> > needing to duplicated all IoLib implementation .infs to provide an
> > IoLib and a BeIoLib for each?
> >
> > It's at that point I burst an aneurysm.
> > Am I overthinking/underthinking this?
>
> We need two library classes, one for talking to LE devices and another to BE
> devices. These should be usable in a given module at the same time, as Ard
> says.
>
> Both library classes need to work on both LE and BE CPUs (working from
> your suggestion that UEFI might grow BE CPU support at some point).
> Whether that is implemented by dumb, separate library instances (yielding
> in total 2*2=4 library instances), or by smart, CPU-endianness-agnostic
> library instances (in total, 2), is a different question.
>
> Note that such "smarts" could be less than trivial to implement:
> - check CPU endianness in each library API?
> - or check in the lib constructor only, and flip some function pointers?
> - use a dynamic PCD for caching CPU endianness?
> - use a HOB for the same?
> - use a lib global variable (for caching only on the module level)?
>
> I think the solution that saves the most on the *source* code size is:
> - introduce the BeIoLib class
> - duplicate the MMIO functions from BaseIoLibIntrinsic to the one
> BeIoLib instance that we introduce
> - modify the MMIO functions in *both* lib instances (original LE, and
> new BE), like this:
>
> - If the CPU architecture is known to be bound to a single endianness,
> then hardcode the appropriate operation. This can be done with
> preprocessor macros, or with the architecture support of INF files /
> separate source files. For example, on IA32 and X64, the IoLib
> instance should work transparently, unconditionally, and the BeIoLib
> instance should byte-swap, unconditionally.
>
> - On other CPU arches, all the wider-than-byte MMIO functions, in
> *both* lib instances should do something like this:
>
> //
> // at file scope
> //
> STATIC CONST UINT16 mOne = 1;
>
> //
> // at function scope
> //
> if (*(CONST UINT8 *)&mOne == 1) {
> //
> // CPU in LE mode:
> // - work transparently in the IoLib instance
> // - byte-swap in the BeIoLib instance
> //
> } else {
> //
> // CPU in BE mode:
> // - byte-swap in the IoLib instance
> // - work transparently in the BeIoLib instance
> //
> }
You meant, sort of cpu_to_le and cpu_to_be sort of APIs
Thanks
Udit
> Thanks,
> Laszlo
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
> 01.org%2Fmailman%2Flistinfo%2Fedk2-
> devel&data=02%7C01%7Cudit.kumar%40nxp.com%7C930d96bb226d4491df2
> d08d579fc1717%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63654
> 9046016636482&sdata=0uPLjiDP60oNVSdbh44gostMx2id%2BzdLYjk8t%2BLwJ
> tU%3D&reserved=0
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-23 9:21 ` Laszlo Ersek
2018-02-23 9:47 ` Meenakshi Aggarwal
@ 2018-02-23 10:39 ` Udit Kumar
2018-02-23 10:59 ` Laszlo Ersek
1 sibling, 1 reply; 254+ messages in thread
From: Udit Kumar @ 2018-02-23 10:39 UTC (permalink / raw)
To: Laszlo Ersek, Pankaj Bansal, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org, Meenakshi Aggarwal
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Laszlo Ersek
> Sent: Friday, February 23, 2018 2:51 PM
> To: Pankaj Bansal <pankaj.bansal@nxp.com>; Leif Lindholm
> <leif.lindholm@linaro.org>
> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> ard.biesheuvel@linaro.org
> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
> for Big Endian Mmio APIs
>
> On 02/23/18 09:40, Pankaj Bansal wrote:
> > Hi All
> >
> >> -----Original Message-----
> >> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> >> Laszlo Ersek
> >> Sent: Thursday, February 22, 2018 7:26 PM
> >> To: Leif Lindholm <leif.lindholm@linaro.org>
> >> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> >> ard.biesheuvel@linaro.org
> >> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add
> support
> >> for Big Endian Mmio APIs
> >>
> >> On 02/22/18 12:52, Leif Lindholm wrote:
> >>> On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
> >>
> >>>>> But that brings back the complication as to how we have a driver
> >>>>> that needs an LE IO library to write output, and a BE IO library to
> >>>>> manipulate the hardware.
> >>>>
> >>>> Can you please explain the "write output" use case more precisely?
> >>>>
> >>>> My thinking would be this:
> >>>>
> >>>> - Use the IoLib class directly for "writing output" in little endian
> >>>> byte order (which is still unclear to me sorry).
> >>>
> >>> If the IoLib class is mapped to a an instance that byte-swaps (hereto
> >>> referred to as BeIoLib if IoLibSwap is unsuitable), would we not then
> >>> end up mapping the non-swapping, currently implemented in
> >>> BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
> >>> needing to duplicated all IoLib implementation .infs to provide an
> >>> IoLib and a BeIoLib for each?
> >>>
> >>> It's at that point I burst an aneurysm.
> >>> Am I overthinking/underthinking this?
> >>
> >> We need two library classes, one for talking to LE devices and another to
> BE
> >> devices. These should be usable in a given module at the same time, as
> Ard
> >> says.
> >>
> >> Both library classes need to work on both LE and BE CPUs (working from
> your
> >> suggestion that UEFI might grow BE CPU support at some point).
> >> Whether that is implemented by dumb, separate library instances
> (yielding in
> >> total 2*2=4 library instances), or by smart, CPU-endianness-agnostic
> library
> >> instances (in total, 2), is a different question.
> >>
> >> Note that such "smarts" could be less than trivial to implement:
> >> - check CPU endianness in each library API?
> >> - or check in the lib constructor only, and flip some function pointers?
> >> - use a dynamic PCD for caching CPU endianness?
> >> - use a HOB for the same?
> >> - use a lib global variable (for caching only on the module level)?
> >>
> >> I think the solution that saves the most on the *source* code size is:
> >> - introduce the BeIoLib class
> >> - duplicate the MMIO functions from BaseIoLibIntrinsic to the one
> >> BeIoLib instance that we introduce
> >> - modify the MMIO functions in *both* lib instances (original LE, and
> >> new BE), like this:
> >>
> >> - If the CPU architecture is known to be bound to a single endianness,
> >> then hardcode the appropriate operation. This can be done with
> >> preprocessor macros, or with the architecture support of INF files /
> >> separate source files. For example, on IA32 and X64, the IoLib
> >> instance should work transparently, unconditionally, and the BeIoLib
> >> instance should byte-swap, unconditionally.
> >>
> >> - On other CPU arches, all the wider-than-byte MMIO functions, in
> >> *both* lib instances should do something like this:
> >>
> >> //
> >> // at file scope
> >> //
> >> STATIC CONST UINT16 mOne = 1;
> >>
> >> //
> >> // at function scope
> >> //
> >> if (*(CONST UINT8 *)&mOne == 1) {
> >> //
> >> // CPU in LE mode:
> >> // - work transparently in the IoLib instance
> >> // - byte-swap in the BeIoLib instance
> >> //
> >> } else {
> >> //
> >> // CPU in BE mode:
> >> // - byte-swap in the IoLib instance
> >> // - work transparently in the BeIoLib instance
> >> //
> >> }
> >
> > I suggest this approach :
> >
> > 1. Add BeMmio* functions in existing IoLib. BeMmio* functions will swap
> the input before write and swap output after read and so on.
> > Mmio* functions will not perform any byte swapping
> > 2. create second instance (a copy) of this IoLib for CPUs that are Big Endian.
> We can call it BigEndianIoLib.
> > In this library Mmio* functions will swap the input before write and
> swap output after read and so on.
> > BeMmio* functions will not perform any byte swapping.
> > 3. Include the instance of IoLib in dsc file based on cpu endianness that the
> platform wants to use. i.e.
> > If BIG_ENDIAN == FALSE
> > IoLib | ..\..\..\IoLib
> > Else
> > IoLib | ..\..\..\BigEndianIoLib
> > 4. The devices that are Big endian in platform will always call BeMmio*
> functions. They need not check CPU endianness.
> > 5. The devices that are Little endian in platform will always call Mmio*
> functions. They need not check CPU endianness.
>
> This can work too, but there is a downside: a large number of IoLib
> instances exist in the tree already. If you add the BeMmio* functions to
> the existent IoLib class, you'll have to duplicate the implementation to
> all instances (identically, I think).
>
> We've had this debate in the past. Back then it was about IoFifo
> routines. I argued for an IoFifo lib class. Ultimately the IoFifo
> routines were added to IoLib, and they had to be implemented for many
> more library instances than client code would have actually required.
> (See the series at 13a50a6fe1dc..2b631390f9f5.) In turn this runs the
> risk of adding untested code.
>
> Regarding the instances for BE CPUs: the name should likely be
> BaseIoLibBigEndian or something similar. In lib instance names, the lib
> class name is usually prefixed with the firmware phases where the
> instance is usable, and hints about the implementation or constraints
> are added as a suffix.
I see like below
CPU IP Call Lib
LE LE MMIO BaseIoLib
LE BE SwappedMMIO BaseIoLibEx
BE BE MMIO BaseIoLib
BE LE SwappedMMIO BaseIoLibEx
I am calling BaseIoLibEx for extend the feature of CPU endianness
In this case SwappedMMIO could be MmioToBe or MmioToLe
Let this this new lib BaseIoLibEx decide endianness of CPU based
upon Pcd, hob list etc and do conversion if needed.
Thanks
Udit
> Also, if you want to support BE CPUs with separate IoLib instances, I'm
> afraid that's going to lead to the combinatorial explosion that Leif
> characterized as "burst[ing] an aneurysm". I think using the (seemingly
> dynamic) "mOne" approach I suggested above, a smart compiler can
> eliminate all the branches at build time.
>
> Anyway, I don't insist; I just commented on an RFC.
>
> Laszlo
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
> 01.org%2Fmailman%2Flistinfo%2Fedk2-
> devel&data=02%7C01%7Cudit.kumar%40nxp.com%7C932b04d97a2648845d9
> 208d57a9ece38%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6365
> 49744881765464&sdata=wHi1Jd5Ar3AlM9sIWI9osdHR%2FF3%2Bx%2BrDEK7U
> AqECXDY%3D&reserved=0
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-23 10:25 ` Udit Kumar
@ 2018-02-23 10:47 ` Laszlo Ersek
2018-02-23 11:48 ` Udit Kumar
2018-02-28 13:19 ` Leif Lindholm
0 siblings, 2 replies; 254+ messages in thread
From: Laszlo Ersek @ 2018-02-23 10:47 UTC (permalink / raw)
To: Udit Kumar, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org
On 02/23/18 11:25, Udit Kumar wrote:
>
>
>> -----Original Message-----
>> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf
>> Of Laszlo Ersek
>> Sent: Thursday, February 22, 2018 7:26 PM
>> To: Leif Lindholm <leif.lindholm@linaro.org>
>> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
>> ard.biesheuvel@linaro.org
>> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add
>> support for Big Endian Mmio APIs
>>
>> On 02/22/18 12:52, Leif Lindholm wrote:
>>> On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
>>
>>>>> But that brings back the complication as to how we have a driver
>>>>> that needs an LE IO library to write output, and a BE IO library
>>>>> to manipulate the hardware.
>>>>
>>>> Can you please explain the "write output" use case more precisely?
>>>>
>>>> My thinking would be this:
>>>>
>>>> - Use the IoLib class directly for "writing output" in little
>>>> endian byte order (which is still unclear to me sorry).
>>>
>>> If the IoLib class is mapped to a an instance that byte-swaps
>>> (hereto referred to as BeIoLib if IoLibSwap is unsuitable), would we
>>> not then end up mapping the non-swapping, currently implemented in
>>> BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
>>> needing to duplicated all IoLib implementation .infs to provide an
>>> IoLib and a BeIoLib for each?
>>>
>>> It's at that point I burst an aneurysm.
>>> Am I overthinking/underthinking this?
>>
>> We need two library classes, one for talking to LE devices and
>> another to BE devices. These should be usable in a given module at
>> the same time, as Ard says.
>>
>> Both library classes need to work on both LE and BE CPUs (working
>> from your suggestion that UEFI might grow BE CPU support at some
>> point). Whether that is implemented by dumb, separate library
>> instances (yielding in total 2*2=4 library instances), or by smart,
>> CPU-endianness-agnostic library instances (in total, 2), is a
>> different question.
>>
>> Note that such "smarts" could be less than trivial to implement:
>> - check CPU endianness in each library API?
>> - or check in the lib constructor only, and flip some function
>> pointers?
>> - use a dynamic PCD for caching CPU endianness?
>> - use a HOB for the same?
>> - use a lib global variable (for caching only on the module level)?
>>
>> I think the solution that saves the most on the *source* code size
>> is:
>> - introduce the BeIoLib class
>> - duplicate the MMIO functions from BaseIoLibIntrinsic to the one
>> BeIoLib instance that we introduce
>> - modify the MMIO functions in *both* lib instances (original LE, and
>> new BE), like this:
>>
>> - If the CPU architecture is known to be bound to a single
>> endianness, then hardcode the appropriate operation. This can be
>> done with preprocessor macros, or with the architecture support
>> of INF files / separate source files. For example, on IA32 and
>> X64, the IoLib instance should work transparently,
>> unconditionally, and the BeIoLib instance should byte-swap,
>> unconditionally.
>>
>> - On other CPU arches, all the wider-than-byte MMIO functions, in
>> *both* lib instances should do something like this:
>>
>> //
>> // at file scope
>> //
>> STATIC CONST UINT16 mOne = 1;
>>
>> //
>> // at function scope
>> //
>> if (*(CONST UINT8 *)&mOne == 1) {
>> //
>> // CPU in LE mode:
>> // - work transparently in the IoLib instance
>> // - byte-swap in the BeIoLib instance
>> //
>> } else {
>> //
>> // CPU in BE mode:
>> // - byte-swap in the IoLib instance
>> // - work transparently in the BeIoLib instance
>> //
>> }
>
> You meant, sort of cpu_to_le and cpu_to_be sort of APIs
I'm lost. I don't know how to put it any clearer. Let me try with actual
code.
(a) Suggested for "MdePkg/Library/BaseIoLibIntrinsic/IoLib.c", which is
used on IA32 and X64, therefore CPU byte order is little endian only:
> UINT32
> EFIAPI
> MmioWrite32 (
> IN UINTN Address,
> IN UINT32 Value
> )
> {
> ASSERT ((Address & 3) == 0);
>
> MemoryFence ();
> *(volatile UINT32*)Address = Value;
> MemoryFence ();
>
> return Value;
> }
In other words, no change to the current implementation.
(b) Suggested for "MdePkg/Library/BaseBeIoLibIntrinsic/IoLib.c", also to
be used on IA32 and X64. Because the CPU byte order is LE only, this
variant will byte-swap unconditionally.
> UINT32
> EFIAPI
> BeMmioWrite32 (
> IN UINTN Address,
> IN UINT32 Value
> )
> {
> ASSERT ((Address & 3) == 0);
>
> MemoryFence ();
> *(volatile UINT32*)Address = SwapBytes32 (Value);
> MemoryFence ();
>
> return Value;
> }
(c) Suggested for "MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c", which
is used on ARM and AARCH64. And here I'll assume that the CPU byte order
on those can be either LE or BE.
> UINT32
> EFIAPI
> MmioWrite32 (
> IN UINTN Address,
> IN UINT32 Value
> )
> {
> ASSERT ((Address & 3) == 0);
> *(volatile UINT32*)Address = (*(CONST UINT8 *)&mOne == 1) ?
> Value :
> SwapBytes32 (Value);
> return Value;
> }
(d) Suggested for "MdePkg/Library/BaseBeIoLibIntrinsic/BeIoLibArm.c",
which is to be used on ARM and AARCH64. And here I'll assume that the
CPU byte order on those can be either LE or BE.
> UINT32
> EFIAPI
> BeMmioWrite32 (
> IN UINTN Address,
> IN UINT32 Value
> )
> {
> ASSERT ((Address & 3) == 0);
> *(volatile UINT32*)Address = (*(CONST UINT8 *)&mOne == 1) ?
> SwapBytes32 (Value) :
> Value;
> return Value;
> }
Laszlo
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-23 10:39 ` Udit Kumar
@ 2018-02-23 10:59 ` Laszlo Ersek
2018-02-23 11:04 ` Pankaj Bansal
2018-02-23 11:21 ` Udit Kumar
0 siblings, 2 replies; 254+ messages in thread
From: Laszlo Ersek @ 2018-02-23 10:59 UTC (permalink / raw)
To: Udit Kumar, Pankaj Bansal, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org, Meenakshi Aggarwal
On 02/23/18 11:39, Udit Kumar wrote:
>
>
>> -----Original Message-----
>> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
>> Laszlo Ersek
>> Sent: Friday, February 23, 2018 2:51 PM
>> To: Pankaj Bansal <pankaj.bansal@nxp.com>; Leif Lindholm
>> <leif.lindholm@linaro.org>
>> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
>> ard.biesheuvel@linaro.org
>> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
>> for Big Endian Mmio APIs
>>
>> On 02/23/18 09:40, Pankaj Bansal wrote:
>>> Hi All
>>>
>>>> -----Original Message-----
>>>> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
>>>> Laszlo Ersek
>>>> Sent: Thursday, February 22, 2018 7:26 PM
>>>> To: Leif Lindholm <leif.lindholm@linaro.org>
>>>> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
>>>> ard.biesheuvel@linaro.org
>>>> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add
>> support
>>>> for Big Endian Mmio APIs
>>>>
>>>> On 02/22/18 12:52, Leif Lindholm wrote:
>>>>> On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
>>>>
>>>>>>> But that brings back the complication as to how we have a driver
>>>>>>> that needs an LE IO library to write output, and a BE IO library to
>>>>>>> manipulate the hardware.
>>>>>>
>>>>>> Can you please explain the "write output" use case more precisely?
>>>>>>
>>>>>> My thinking would be this:
>>>>>>
>>>>>> - Use the IoLib class directly for "writing output" in little endian
>>>>>> byte order (which is still unclear to me sorry).
>>>>>
>>>>> If the IoLib class is mapped to a an instance that byte-swaps (hereto
>>>>> referred to as BeIoLib if IoLibSwap is unsuitable), would we not then
>>>>> end up mapping the non-swapping, currently implemented in
>>>>> BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
>>>>> needing to duplicated all IoLib implementation .infs to provide an
>>>>> IoLib and a BeIoLib for each?
>>>>>
>>>>> It's at that point I burst an aneurysm.
>>>>> Am I overthinking/underthinking this?
>>>>
>>>> We need two library classes, one for talking to LE devices and another to
>> BE
>>>> devices. These should be usable in a given module at the same time, as
>> Ard
>>>> says.
>>>>
>>>> Both library classes need to work on both LE and BE CPUs (working from
>> your
>>>> suggestion that UEFI might grow BE CPU support at some point).
>>>> Whether that is implemented by dumb, separate library instances
>> (yielding in
>>>> total 2*2=4 library instances), or by smart, CPU-endianness-agnostic
>> library
>>>> instances (in total, 2), is a different question.
>>>>
>>>> Note that such "smarts" could be less than trivial to implement:
>>>> - check CPU endianness in each library API?
>>>> - or check in the lib constructor only, and flip some function pointers?
>>>> - use a dynamic PCD for caching CPU endianness?
>>>> - use a HOB for the same?
>>>> - use a lib global variable (for caching only on the module level)?
>>>>
>>>> I think the solution that saves the most on the *source* code size is:
>>>> - introduce the BeIoLib class
>>>> - duplicate the MMIO functions from BaseIoLibIntrinsic to the one
>>>> BeIoLib instance that we introduce
>>>> - modify the MMIO functions in *both* lib instances (original LE, and
>>>> new BE), like this:
>>>>
>>>> - If the CPU architecture is known to be bound to a single endianness,
>>>> then hardcode the appropriate operation. This can be done with
>>>> preprocessor macros, or with the architecture support of INF files /
>>>> separate source files. For example, on IA32 and X64, the IoLib
>>>> instance should work transparently, unconditionally, and the BeIoLib
>>>> instance should byte-swap, unconditionally.
>>>>
>>>> - On other CPU arches, all the wider-than-byte MMIO functions, in
>>>> *both* lib instances should do something like this:
>>>>
>>>> //
>>>> // at file scope
>>>> //
>>>> STATIC CONST UINT16 mOne = 1;
>>>>
>>>> //
>>>> // at function scope
>>>> //
>>>> if (*(CONST UINT8 *)&mOne == 1) {
>>>> //
>>>> // CPU in LE mode:
>>>> // - work transparently in the IoLib instance
>>>> // - byte-swap in the BeIoLib instance
>>>> //
>>>> } else {
>>>> //
>>>> // CPU in BE mode:
>>>> // - byte-swap in the IoLib instance
>>>> // - work transparently in the BeIoLib instance
>>>> //
>>>> }
>>>
>>> I suggest this approach :
>>>
>>> 1. Add BeMmio* functions in existing IoLib. BeMmio* functions will swap
>> the input before write and swap output after read and so on.
>>> Mmio* functions will not perform any byte swapping
>>> 2. create second instance (a copy) of this IoLib for CPUs that are Big Endian.
>> We can call it BigEndianIoLib.
>>> In this library Mmio* functions will swap the input before write and
>> swap output after read and so on.
>>> BeMmio* functions will not perform any byte swapping.
>>> 3. Include the instance of IoLib in dsc file based on cpu endianness that the
>> platform wants to use. i.e.
>>> If BIG_ENDIAN == FALSE
>>> IoLib | ..\..\..\IoLib
>>> Else
>>> IoLib | ..\..\..\BigEndianIoLib
>>> 4. The devices that are Big endian in platform will always call BeMmio*
>> functions. They need not check CPU endianness.
>>> 5. The devices that are Little endian in platform will always call Mmio*
>> functions. They need not check CPU endianness.
>>
>> This can work too, but there is a downside: a large number of IoLib
>> instances exist in the tree already. If you add the BeMmio* functions to
>> the existent IoLib class, you'll have to duplicate the implementation to
>> all instances (identically, I think).
>>
>> We've had this debate in the past. Back then it was about IoFifo
>> routines. I argued for an IoFifo lib class. Ultimately the IoFifo
>> routines were added to IoLib, and they had to be implemented for many
>> more library instances than client code would have actually required.
>> (See the series at 13a50a6fe1dc..2b631390f9f5.) In turn this runs the
>> risk of adding untested code.
>>
>> Regarding the instances for BE CPUs: the name should likely be
>> BaseIoLibBigEndian or something similar. In lib instance names, the lib
>> class name is usually prefixed with the firmware phases where the
>> instance is usable, and hints about the implementation or constraints
>> are added as a suffix.
>
> I see like below
> CPU IP Call Lib
> LE LE MMIO BaseIoLib
> LE BE SwappedMMIO BaseIoLibEx
> BE BE MMIO BaseIoLib
> BE LE SwappedMMIO BaseIoLibEx
In my opinion, this is wrong. The "Call" column should not vary with CPU
endianness, it should only vary with "IP" (device) endianness.
Basically you are putting the entire work on the driver code, to figure
out whether swapping will be necessary or not. For that, the driver has
to consult the byte order of *both* the CPU *and* the device, and then
call "transparent" or "swapped" MMIO functions.
What I am suggesting is that the driver care about device byte order
only. This will determine whether the driver calls MmioWrite32() or
BeMmioWrite32().
In turn, whether or not those functions byte-swap, according to CPU byte
order, is an internal matter of the libraries.
IP Call Lib CPU Byte-swap within Lib
-- ------------- ------- --- --------------------
LE MmioWrite32 IoLib LE no
LE MmioWrite32 IoLib BE yes
BE BeMmioWrite32 BeIoLib LE yes
BE BeMmioWrite32 BeIoLib BE no
Obviously, the end result is the same; the question is what *concepts*
the device driver has to care about.
Under your scheme, every device driver has to care about concepts such
as "device byte order", "cpu byte order", and "swapping".
Under my scheme, every device driver has to care about "device byte order".
Laszlo
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-23 10:59 ` Laszlo Ersek
@ 2018-02-23 11:04 ` Pankaj Bansal
2018-02-23 11:22 ` Laszlo Ersek
2018-02-23 11:21 ` Udit Kumar
1 sibling, 1 reply; 254+ messages in thread
From: Pankaj Bansal @ 2018-02-23 11:04 UTC (permalink / raw)
To: Laszlo Ersek, Udit Kumar, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org, Meenakshi Aggarwal
Hi All
> -----Original Message-----
> From: Laszlo Ersek [mailto:lersek@redhat.com]
> Sent: Friday, February 23, 2018 4:29 PM
> To: Udit Kumar <udit.kumar@nxp.com>; Pankaj Bansal
> <pankaj.bansal@nxp.com>; Leif Lindholm <leif.lindholm@linaro.org>
> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> ard.biesheuvel@linaro.org; Meenakshi Aggarwal
> <meenakshi.aggarwal@nxp.com>
> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
> for Big Endian Mmio APIs
>
> On 02/23/18 11:39, Udit Kumar wrote:
> >
> >
> >> -----Original Message-----
> >> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf
> >> Of Laszlo Ersek
> >> Sent: Friday, February 23, 2018 2:51 PM
> >> To: Pankaj Bansal <pankaj.bansal@nxp.com>; Leif Lindholm
> >> <leif.lindholm@linaro.org>
> >> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> >> ard.biesheuvel@linaro.org
> >> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add
> >> support for Big Endian Mmio APIs
> >>
> >> On 02/23/18 09:40, Pankaj Bansal wrote:
> >>> Hi All
> >>>
> >>>> -----Original Message-----
> >>>> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf
> >>>> Of Laszlo Ersek
> >>>> Sent: Thursday, February 22, 2018 7:26 PM
> >>>> To: Leif Lindholm <leif.lindholm@linaro.org>
> >>>> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> >>>> ard.biesheuvel@linaro.org
> >>>> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add
> >> support
> >>>> for Big Endian Mmio APIs
> >>>>
> >>>> On 02/22/18 12:52, Leif Lindholm wrote:
> >>>>> On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
> >>>>
> >>>>>>> But that brings back the complication as to how we have a driver
> >>>>>>> that needs an LE IO library to write output, and a BE IO library
> >>>>>>> to manipulate the hardware.
> >>>>>>
> >>>>>> Can you please explain the "write output" use case more precisely?
> >>>>>>
> >>>>>> My thinking would be this:
> >>>>>>
> >>>>>> - Use the IoLib class directly for "writing output" in little
> >>>>>> endian byte order (which is still unclear to me sorry).
> >>>>>
> >>>>> If the IoLib class is mapped to a an instance that byte-swaps
> >>>>> (hereto referred to as BeIoLib if IoLibSwap is unsuitable), would
> >>>>> we not then end up mapping the non-swapping, currently
> implemented
> >>>>> in BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
> >>>>> needing to duplicated all IoLib implementation .infs to provide an
> >>>>> IoLib and a BeIoLib for each?
> >>>>>
> >>>>> It's at that point I burst an aneurysm.
> >>>>> Am I overthinking/underthinking this?
> >>>>
> >>>> We need two library classes, one for talking to LE devices and
> >>>> another to
> >> BE
> >>>> devices. These should be usable in a given module at the same time,
> >>>> as
> >> Ard
> >>>> says.
> >>>>
> >>>> Both library classes need to work on both LE and BE CPUs (working
> >>>> from
> >> your
> >>>> suggestion that UEFI might grow BE CPU support at some point).
> >>>> Whether that is implemented by dumb, separate library instances
> >> (yielding in
> >>>> total 2*2=4 library instances), or by smart,
> >>>> CPU-endianness-agnostic
> >> library
> >>>> instances (in total, 2), is a different question.
> >>>>
> >>>> Note that such "smarts" could be less than trivial to implement:
> >>>> - check CPU endianness in each library API?
> >>>> - or check in the lib constructor only, and flip some function pointers?
> >>>> - use a dynamic PCD for caching CPU endianness?
> >>>> - use a HOB for the same?
> >>>> - use a lib global variable (for caching only on the module level)?
> >>>>
> >>>> I think the solution that saves the most on the *source* code size is:
> >>>> - introduce the BeIoLib class
> >>>> - duplicate the MMIO functions from BaseIoLibIntrinsic to the one
> >>>> BeIoLib instance that we introduce
> >>>> - modify the MMIO functions in *both* lib instances (original LE, and
> >>>> new BE), like this:
> >>>>
> >>>> - If the CPU architecture is known to be bound to a single endianness,
> >>>> then hardcode the appropriate operation. This can be done with
> >>>> preprocessor macros, or with the architecture support of INF files /
> >>>> separate source files. For example, on IA32 and X64, the IoLib
> >>>> instance should work transparently, unconditionally, and the BeIoLib
> >>>> instance should byte-swap, unconditionally.
> >>>>
> >>>> - On other CPU arches, all the wider-than-byte MMIO functions, in
> >>>> *both* lib instances should do something like this:
> >>>>
> >>>> //
> >>>> // at file scope
> >>>> //
> >>>> STATIC CONST UINT16 mOne = 1;
> >>>>
> >>>> //
> >>>> // at function scope
> >>>> //
> >>>> if (*(CONST UINT8 *)&mOne == 1) {
> >>>> //
> >>>> // CPU in LE mode:
> >>>> // - work transparently in the IoLib instance
> >>>> // - byte-swap in the BeIoLib instance
> >>>> //
> >>>> } else {
> >>>> //
> >>>> // CPU in BE mode:
> >>>> // - byte-swap in the IoLib instance
> >>>> // - work transparently in the BeIoLib instance
> >>>> //
> >>>> }
> >>>
> >>> I suggest this approach :
> >>>
> >>> 1. Add BeMmio* functions in existing IoLib. BeMmio* functions will
> >>> swap
> >> the input before write and swap output after read and so on.
> >>> Mmio* functions will not perform any byte swapping 2. create
> >>> second instance (a copy) of this IoLib for CPUs that are Big Endian.
> >> We can call it BigEndianIoLib.
> >>> In this library Mmio* functions will swap the input before
> >>> write and
> >> swap output after read and so on.
> >>> BeMmio* functions will not perform any byte swapping.
> >>> 3. Include the instance of IoLib in dsc file based on cpu endianness
> >>> that the
> >> platform wants to use. i.e.
> >>> If BIG_ENDIAN == FALSE
> >>> IoLib | ..\..\..\IoLib
> >>> Else
> >>> IoLib | ..\..\..\BigEndianIoLib 4. The devices that are Big
> >>> endian in platform will always call BeMmio*
> >> functions. They need not check CPU endianness.
> >>> 5. The devices that are Little endian in platform will always call
> >>> Mmio*
> >> functions. They need not check CPU endianness.
> >>
> >> This can work too, but there is a downside: a large number of IoLib
> >> instances exist in the tree already. If you add the BeMmio* functions
> >> to the existent IoLib class, you'll have to duplicate the
> >> implementation to all instances (identically, I think).
> >>
> >> We've had this debate in the past. Back then it was about IoFifo
> >> routines. I argued for an IoFifo lib class. Ultimately the IoFifo
> >> routines were added to IoLib, and they had to be implemented for many
> >> more library instances than client code would have actually required.
> >> (See the series at 13a50a6fe1dc..2b631390f9f5.) In turn this runs the
> >> risk of adding untested code.
> >>
> >> Regarding the instances for BE CPUs: the name should likely be
> >> BaseIoLibBigEndian or something similar. In lib instance names, the
> >> lib class name is usually prefixed with the firmware phases where the
> >> instance is usable, and hints about the implementation or constraints
> >> are added as a suffix.
> >
> > I see like below
> > CPU IP Call Lib
> > LE LE MMIO BaseIoLib
> > LE BE SwappedMMIO
> BaseIoLibEx
> > BE BE MMIO BaseIoLib
> > BE LE SwappedMMIO
> BaseIoLibEx
>
> In my opinion, this is wrong. The "Call" column should not vary with CPU
> endianness, it should only vary with "IP" (device) endianness.
>
> Basically you are putting the entire work on the driver code, to figure out
> whether swapping will be necessary or not. For that, the driver has to consult
> the byte order of *both* the CPU *and* the device, and then call
> "transparent" or "swapped" MMIO functions.
>
> What I am suggesting is that the driver care about device byte order only.
> This will determine whether the driver calls MmioWrite32() or
> BeMmioWrite32().
>
> In turn, whether or not those functions byte-swap, according to CPU byte
> order, is an internal matter of the libraries.
>
> IP Call Lib CPU Byte-swap within Lib
> -- ------------- ------- --- --------------------
> LE MmioWrite32 IoLib LE no
> LE MmioWrite32 IoLib BE yes
> BE BeMmioWrite32 BeIoLib LE yes
> BE BeMmioWrite32 BeIoLib BE no
>
> Obviously, the end result is the same; the question is what *concepts* the
> device driver has to care about.
>
> Under your scheme, every device driver has to care about concepts such as
> "device byte order", "cpu byte order", and "swapping".
>
> Under my scheme, every device driver has to care about "device byte order".
I agree with Laszlo. Device driver's concern should be device's endianness NOT cpu endianness.
However Laszlo, with the method you suggest (using STATIC CONST UINT16 mOne), would it not add delay in each Mmio Operation ?
I am concerned about boot delay using this approach.
>
> Laszlo
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-23 10:59 ` Laszlo Ersek
2018-02-23 11:04 ` Pankaj Bansal
@ 2018-02-23 11:21 ` Udit Kumar
1 sibling, 0 replies; 254+ messages in thread
From: Udit Kumar @ 2018-02-23 11:21 UTC (permalink / raw)
To: Laszlo Ersek, Pankaj Bansal, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org, Meenakshi Aggarwal
Hi Laszlo
> -----Original Message-----
> From: Laszlo Ersek [mailto:lersek@redhat.com]
> Sent: Friday, February 23, 2018 4:29 PM
> To: Udit Kumar <udit.kumar@nxp.com>; Pankaj Bansal
> <pankaj.bansal@nxp.com>; Leif Lindholm <leif.lindholm@linaro.org>
> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> ard.biesheuvel@linaro.org; Meenakshi Aggarwal
> <meenakshi.aggarwal@nxp.com>
> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
> for Big Endian Mmio APIs
>
> On 02/23/18 11:39, Udit Kumar wrote:
> >
> >
> >> -----Original Message-----
> >> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> >> Laszlo Ersek
> >> Sent: Friday, February 23, 2018 2:51 PM
> >> To: Pankaj Bansal <pankaj.bansal@nxp.com>; Leif Lindholm
> >> <leif.lindholm@linaro.org>
> >> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> >> ard.biesheuvel@linaro.org
> >> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add
> support
> >> for Big Endian Mmio APIs
> >>
> >> On 02/23/18 09:40, Pankaj Bansal wrote:
> >>> Hi All
> >>>
> >>>> -----Original Message-----
> >>>> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf
> Of
> >>>> Laszlo Ersek
> >>>> Sent: Thursday, February 22, 2018 7:26 PM
> >>>> To: Leif Lindholm <leif.lindholm@linaro.org>
> >>>> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> >>>> ard.biesheuvel@linaro.org
> >>>> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add
> >> support
> >>>> for Big Endian Mmio APIs
> >>>>
> >>>> On 02/22/18 12:52, Leif Lindholm wrote:
> >>>>> On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
> >>>>
> >>>>>>> But that brings back the complication as to how we have a driver
> >>>>>>> that needs an LE IO library to write output, and a BE IO library to
> >>>>>>> manipulate the hardware.
> >>>>>>
> >>>>>> Can you please explain the "write output" use case more precisely?
> >>>>>>
> >>>>>> My thinking would be this:
> >>>>>>
> >>>>>> - Use the IoLib class directly for "writing output" in little endian
> >>>>>> byte order (which is still unclear to me sorry).
> >>>>>
> >>>>> If the IoLib class is mapped to a an instance that byte-swaps (hereto
> >>>>> referred to as BeIoLib if IoLibSwap is unsuitable), would we not then
> >>>>> end up mapping the non-swapping, currently implemented in
> >>>>> BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
> >>>>> needing to duplicated all IoLib implementation .infs to provide an
> >>>>> IoLib and a BeIoLib for each?
> >>>>>
> >>>>> It's at that point I burst an aneurysm.
> >>>>> Am I overthinking/underthinking this?
> >>>>
> >>>> We need two library classes, one for talking to LE devices and another
> to
> >> BE
> >>>> devices. These should be usable in a given module at the same time, as
> >> Ard
> >>>> says.
> >>>>
> >>>> Both library classes need to work on both LE and BE CPUs (working
> from
> >> your
> >>>> suggestion that UEFI might grow BE CPU support at some point).
> >>>> Whether that is implemented by dumb, separate library instances
> >> (yielding in
> >>>> total 2*2=4 library instances), or by smart, CPU-endianness-agnostic
> >> library
> >>>> instances (in total, 2), is a different question.
> >>>>
> >>>> Note that such "smarts" could be less than trivial to implement:
> >>>> - check CPU endianness in each library API?
> >>>> - or check in the lib constructor only, and flip some function pointers?
> >>>> - use a dynamic PCD for caching CPU endianness?
> >>>> - use a HOB for the same?
> >>>> - use a lib global variable (for caching only on the module level)?
> >>>>
> >>>> I think the solution that saves the most on the *source* code size is:
> >>>> - introduce the BeIoLib class
> >>>> - duplicate the MMIO functions from BaseIoLibIntrinsic to the one
> >>>> BeIoLib instance that we introduce
> >>>> - modify the MMIO functions in *both* lib instances (original LE, and
> >>>> new BE), like this:
> >>>>
> >>>> - If the CPU architecture is known to be bound to a single endianness,
> >>>> then hardcode the appropriate operation. This can be done with
> >>>> preprocessor macros, or with the architecture support of INF files /
> >>>> separate source files. For example, on IA32 and X64, the IoLib
> >>>> instance should work transparently, unconditionally, and the BeIoLib
> >>>> instance should byte-swap, unconditionally.
> >>>>
> >>>> - On other CPU arches, all the wider-than-byte MMIO functions, in
> >>>> *both* lib instances should do something like this:
> >>>>
> >>>> //
> >>>> // at file scope
> >>>> //
> >>>> STATIC CONST UINT16 mOne = 1;
> >>>>
> >>>> //
> >>>> // at function scope
> >>>> //
> >>>> if (*(CONST UINT8 *)&mOne == 1) {
> >>>> //
> >>>> // CPU in LE mode:
> >>>> // - work transparently in the IoLib instance
> >>>> // - byte-swap in the BeIoLib instance
> >>>> //
> >>>> } else {
> >>>> //
> >>>> // CPU in BE mode:
> >>>> // - byte-swap in the IoLib instance
> >>>> // - work transparently in the BeIoLib instance
> >>>> //
> >>>> }
> >>>
> >>> I suggest this approach :
> >>>
> >>> 1. Add BeMmio* functions in existing IoLib. BeMmio* functions will
> swap
> >> the input before write and swap output after read and so on.
> >>> Mmio* functions will not perform any byte swapping
> >>> 2. create second instance (a copy) of this IoLib for CPUs that are Big
> Endian.
> >> We can call it BigEndianIoLib.
> >>> In this library Mmio* functions will swap the input before write and
> >> swap output after read and so on.
> >>> BeMmio* functions will not perform any byte swapping.
> >>> 3. Include the instance of IoLib in dsc file based on cpu endianness that
> the
> >> platform wants to use. i.e.
> >>> If BIG_ENDIAN == FALSE
> >>> IoLib | ..\..\..\IoLib
> >>> Else
> >>> IoLib | ..\..\..\BigEndianIoLib
> >>> 4. The devices that are Big endian in platform will always call BeMmio*
> >> functions. They need not check CPU endianness.
> >>> 5. The devices that are Little endian in platform will always call Mmio*
> >> functions. They need not check CPU endianness.
> >>
> >> This can work too, but there is a downside: a large number of IoLib
> >> instances exist in the tree already. If you add the BeMmio* functions to
> >> the existent IoLib class, you'll have to duplicate the implementation to
> >> all instances (identically, I think).
> >>
> >> We've had this debate in the past. Back then it was about IoFifo
> >> routines. I argued for an IoFifo lib class. Ultimately the IoFifo
> >> routines were added to IoLib, and they had to be implemented for many
> >> more library instances than client code would have actually required.
> >> (See the series at 13a50a6fe1dc..2b631390f9f5.) In turn this runs the
> >> risk of adding untested code.
> >>
> >> Regarding the instances for BE CPUs: the name should likely be
> >> BaseIoLibBigEndian or something similar. In lib instance names, the lib
> >> class name is usually prefixed with the firmware phases where the
> >> instance is usable, and hints about the implementation or constraints
> >> are added as a suffix.
> >
> > I see like below
> > CPU IP Call Lib
> > LE LE MMIO BaseIoLib
> > LE BE SwappedMMIO BaseIoLibEx
> > BE BE MMIO BaseIoLib
> > BE LE SwappedMMIO
> BaseIoLibEx
>
> In my opinion, this is wrong. The "Call" column should not vary with CPU
> endianness, it should only vary with "IP" (device) endianness.
>
> Basically you are putting the entire work on the driver code, to figure
> out whether swapping will be necessary or not. For that, the driver has
> to consult the byte order of *both* the CPU *and* the device, and then
> call "transparent" or "swapped" MMIO functions.
>
> What I am suggesting is that the driver care about device byte order
> only. This will determine whether the driver calls MmioWrite32() or
> BeMmioWrite32().
> In turn, whether or not those functions byte-swap, according to CPU byte
> order, is an internal matter of the libraries.
>
> IP Call Lib CPU Byte-swap within Lib
> -- ------------- ------- --- --------------------
> LE MmioWrite32 IoLib LE no
> LE MmioWrite32 IoLib BE yes
> BE BeMmioWrite32 BeIoLib LE yes
> BE BeMmioWrite32 BeIoLib BE no
>
> Obviously, the end result is the same; the question is what *concepts*
> the device driver has to care about.
> Under your scheme, every device driver has to care about concepts such
> as "device byte order", "cpu byte order", and "swapping".
>
> Under my scheme, every device driver has to care about "device byte order".
Thanks for detailing .
May be I was not clear in previous email by saying
>> I am calling BaseIoLibEx for extend the feature of CPU endianness In this case SwappedMMIO could be MmioToBe or MmioToLe Let this this new
>> lib BaseIoLibEx decide endianness of CPU based upon Pcd, hob list etc and do conversion if needed.
I think, more or less we are saying same thing.
I am saying for new development will use MmioToBe or MmioToLe based upon IP mode,
Whereas you are referring as MmioWrite32 and BeMmioWrite32 to be used.
The difference what I see, between your proposal and mine
You are saying , to do swapping in MmioWrite32 based upon CPU mode.
Whereas I am referring to new APIs.
Anyway , I am ok with your proposal , which looks more inline w.r.t current edk-2 code
Thanks
Udit
> Laszlo
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-23 11:04 ` Pankaj Bansal
@ 2018-02-23 11:22 ` Laszlo Ersek
2018-02-23 11:48 ` Pankaj Bansal
0 siblings, 1 reply; 254+ messages in thread
From: Laszlo Ersek @ 2018-02-23 11:22 UTC (permalink / raw)
To: Pankaj Bansal, Udit Kumar, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org, Meenakshi Aggarwal
On 02/23/18 12:04, Pankaj Bansal wrote:
> However Laszlo, with the method you suggest (using STATIC CONST
> UINT16 mOne), would it not add delay in each Mmio Operation ?
>
> I am concerned about boot delay using this approach.
The condition can be evaluated at compile time, so I expect optimizing
compilers to eliminate the dead branch.
Assuming the condition cannot be eliminated at build time, what is your
concern: the single byte access, or the branch instruction?
I don't think the single byte access matters. (If you tried to replace
that with a HOB or PCD lookup, it could only be worse.)
I also doubt the branch should be a concern. You could replace the "if"
(or the ternary operator "?:") with function pointers that you set e.g.
in a constructor function. But I think an "if" with an invariable
(constant) controlling expression is at least as friendly towards branch
predictors as a function pointer variable (through which you might be
*forced* to make a real function call).
Personally I wouldn't worry.
Anyway: please do not mistake my willingness / preference to go into
such detail for having high stakes at this. If you go an entirely
different route, I'm OK with that too. I felt I was asked for my opinion
and I tried to express it in detail, that's all.
Thanks
Laszlo
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-23 10:47 ` Laszlo Ersek
@ 2018-02-23 11:48 ` Udit Kumar
2018-02-23 15:15 ` Laszlo Ersek
2018-02-28 13:19 ` Leif Lindholm
1 sibling, 1 reply; 254+ messages in thread
From: Udit Kumar @ 2018-02-23 11:48 UTC (permalink / raw)
To: Laszlo Ersek, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org, Meenakshi Aggarwal
Hi Laszlo/Leif,
For short term, is this ok to keep this lib under Silicon/NXP, here we are assuming
CPU will always on be LE mode whereas IP can vary between LE/BE mode ?
For long term, we can discuss on APIs/name of Lib/Function name etc
We will update our code, as per agreement.
For me, Suggested approach is ok as well to keep CPU endianness in ARM package.
but need views from Ard/Leif here.
Thanks
Udit
> -----Original Message-----
> From: Laszlo Ersek [mailto:lersek@redhat.com]
> Sent: Friday, February 23, 2018 4:17 PM
> To: Udit Kumar <udit.kumar@nxp.com>; Leif Lindholm
> <leif.lindholm@linaro.org>
> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> ard.biesheuvel@linaro.org
> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
> for Big Endian Mmio APIs
>
> On 02/23/18 11:25, Udit Kumar wrote:
> >
> >
> >> -----Original Message-----
> >> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf
> >> Of Laszlo Ersek
> >> Sent: Thursday, February 22, 2018 7:26 PM
> >> To: Leif Lindholm <leif.lindholm@linaro.org>
> >> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> >> ard.biesheuvel@linaro.org
> >> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add
> >> support for Big Endian Mmio APIs
> >>
> >> On 02/22/18 12:52, Leif Lindholm wrote:
> >>> On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
> >>
> >>>>> But that brings back the complication as to how we have a driver
> >>>>> that needs an LE IO library to write output, and a BE IO library
> >>>>> to manipulate the hardware.
> >>>>
> >>>> Can you please explain the "write output" use case more precisely?
> >>>>
> >>>> My thinking would be this:
> >>>>
> >>>> - Use the IoLib class directly for "writing output" in little
> >>>> endian byte order (which is still unclear to me sorry).
> >>>
> >>> If the IoLib class is mapped to a an instance that byte-swaps
> >>> (hereto referred to as BeIoLib if IoLibSwap is unsuitable), would we
> >>> not then end up mapping the non-swapping, currently implemented in
> >>> BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
> >>> needing to duplicated all IoLib implementation .infs to provide an
> >>> IoLib and a BeIoLib for each?
> >>>
> >>> It's at that point I burst an aneurysm.
> >>> Am I overthinking/underthinking this?
> >>
> >> We need two library classes, one for talking to LE devices and
> >> another to BE devices. These should be usable in a given module at
> >> the same time, as Ard says.
> >>
> >> Both library classes need to work on both LE and BE CPUs (working
> >> from your suggestion that UEFI might grow BE CPU support at some
> >> point). Whether that is implemented by dumb, separate library
> >> instances (yielding in total 2*2=4 library instances), or by smart,
> >> CPU-endianness-agnostic library instances (in total, 2), is a
> >> different question.
> >>
> >> Note that such "smarts" could be less than trivial to implement:
> >> - check CPU endianness in each library API?
> >> - or check in the lib constructor only, and flip some function
> >> pointers?
> >> - use a dynamic PCD for caching CPU endianness?
> >> - use a HOB for the same?
> >> - use a lib global variable (for caching only on the module level)?
> >>
> >> I think the solution that saves the most on the *source* code size
> >> is:
> >> - introduce the BeIoLib class
> >> - duplicate the MMIO functions from BaseIoLibIntrinsic to the one
> >> BeIoLib instance that we introduce
> >> - modify the MMIO functions in *both* lib instances (original LE, and
> >> new BE), like this:
> >>
> >> - If the CPU architecture is known to be bound to a single
> >> endianness, then hardcode the appropriate operation. This can be
> >> done with preprocessor macros, or with the architecture support
> >> of INF files / separate source files. For example, on IA32 and
> >> X64, the IoLib instance should work transparently,
> >> unconditionally, and the BeIoLib instance should byte-swap,
> >> unconditionally.
> >>
> >> - On other CPU arches, all the wider-than-byte MMIO functions, in
> >> *both* lib instances should do something like this:
> >>
> >> //
> >> // at file scope
> >> //
> >> STATIC CONST UINT16 mOne = 1;
> >>
> >> //
> >> // at function scope
> >> //
> >> if (*(CONST UINT8 *)&mOne == 1) {
> >> //
> >> // CPU in LE mode:
> >> // - work transparently in the IoLib instance
> >> // - byte-swap in the BeIoLib instance
> >> //
> >> } else {
> >> //
> >> // CPU in BE mode:
> >> // - byte-swap in the IoLib instance
> >> // - work transparently in the BeIoLib instance
> >> //
> >> }
> >
> > You meant, sort of cpu_to_le and cpu_to_be sort of APIs
>
> I'm lost. I don't know how to put it any clearer. Let me try with actual
> code.
>
> (a) Suggested for "MdePkg/Library/BaseIoLibIntrinsic/IoLib.c", which is
> used on IA32 and X64, therefore CPU byte order is little endian only:
>
> > UINT32
> > EFIAPI
> > MmioWrite32 (
> > IN UINTN Address,
> > IN UINT32 Value
> > )
> > {
> > ASSERT ((Address & 3) == 0);
> >
> > MemoryFence ();
> > *(volatile UINT32*)Address = Value;
> > MemoryFence ();
> >
> > return Value;
> > }
>
> In other words, no change to the current implementation.
>
>
> (b) Suggested for "MdePkg/Library/BaseBeIoLibIntrinsic/IoLib.c", also to
> be used on IA32 and X64. Because the CPU byte order is LE only, this
> variant will byte-swap unconditionally.
>
> > UINT32
> > EFIAPI
> > BeMmioWrite32 (
> > IN UINTN Address,
> > IN UINT32 Value
> > )
> > {
> > ASSERT ((Address & 3) == 0);
> >
> > MemoryFence ();
> > *(volatile UINT32*)Address = SwapBytes32 (Value);
> > MemoryFence ();
> >
> > return Value;
> > }
>
> (c) Suggested for "MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c", which
> is used on ARM and AARCH64. And here I'll assume that the CPU byte order
> on those can be either LE or BE.
>
> > UINT32
> > EFIAPI
> > MmioWrite32 (
> > IN UINTN Address,
> > IN UINT32 Value
> > )
> > {
> > ASSERT ((Address & 3) == 0);
> > *(volatile UINT32*)Address = (*(CONST UINT8 *)&mOne == 1) ?
> > Value :
> > SwapBytes32 (Value);
> > return Value;
> > }
>
>
> (d) Suggested for "MdePkg/Library/BaseBeIoLibIntrinsic/BeIoLibArm.c",
> which is to be used on ARM and AARCH64. And here I'll assume that the
> CPU byte order on those can be either LE or BE.
>
> > UINT32
> > EFIAPI
> > BeMmioWrite32 (
> > IN UINTN Address,
> > IN UINT32 Value
> > )
> > {
> > ASSERT ((Address & 3) == 0);
> > *(volatile UINT32*)Address = (*(CONST UINT8 *)&mOne == 1) ?
> > SwapBytes32 (Value) :
> > Value;
> > return Value;
> > }
> Laszlo
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-23 11:22 ` Laszlo Ersek
@ 2018-02-23 11:48 ` Pankaj Bansal
2018-02-23 15:17 ` Laszlo Ersek
0 siblings, 1 reply; 254+ messages in thread
From: Pankaj Bansal @ 2018-02-23 11:48 UTC (permalink / raw)
To: Laszlo Ersek, Udit Kumar, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org, Meenakshi Aggarwal
> -----Original Message-----
> From: Laszlo Ersek [mailto:lersek@redhat.com]
> Sent: Friday, February 23, 2018 4:52 PM
> To: Pankaj Bansal <pankaj.bansal@nxp.com>; Udit Kumar
> <udit.kumar@nxp.com>; Leif Lindholm <leif.lindholm@linaro.org>
> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
> ard.biesheuvel@linaro.org; Meenakshi Aggarwal
> <meenakshi.aggarwal@nxp.com>
> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
> for Big Endian Mmio APIs
>
> On 02/23/18 12:04, Pankaj Bansal wrote:
>
> > However Laszlo, with the method you suggest (using STATIC CONST
> > UINT16 mOne), would it not add delay in each Mmio Operation ?
> >
> > I am concerned about boot delay using this approach.
> The condition can be evaluated at compile time, so I expect optimizing
> compilers to eliminate the dead branch.
>
> Assuming the condition cannot be eliminated at build time, what is your
> concern: the single byte access, or the branch instruction?
>
> I don't think the single byte access matters. (If you tried to replace that with a
> HOB or PCD lookup, it could only be worse.)
>
> I also doubt the branch should be a concern. You could replace the "if"
> (or the ternary operator "?:") with function pointers that you set e.g.
> in a constructor function. But I think an "if" with an invariable
> (constant) controlling expression is at least as friendly towards branch
> predictors as a function pointer variable (through which you might be
> *forced* to make a real function call).
>
> Personally I wouldn't worry.
>
I think you are right about smart compiler eliminating the branches at build time.
I just pointed this out because we call Mmio/BeMmio APIs when accessing Nor flash for variable read/write.
As these are called so many time during boot, I did not want any delay to be added to these APIs than necessary.
Now that you have pointed it out, I don't think any significant delay will be added to these APIs.
>
> Anyway: please do not mistake my willingness / preference to go into such
> detail for having high stakes at this. If you go an entirely different route, I'm
> OK with that too. I felt I was asked for my opinion and I tried to express it in
> detail, that's all.
Any comments/suggestions/opinions are always appreciated from you or from any edk2 mailing list member.
>
> Thanks
> Laszlo
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-23 11:48 ` Udit Kumar
@ 2018-02-23 15:15 ` Laszlo Ersek
0 siblings, 0 replies; 254+ messages in thread
From: Laszlo Ersek @ 2018-02-23 15:15 UTC (permalink / raw)
To: Udit Kumar, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org, Meenakshi Aggarwal
On 02/23/18 12:48, Udit Kumar wrote:
> Hi Laszlo/Leif,
>
> For short term, is this ok to keep this lib under Silicon/NXP, here we are assuming
> CPU will always on be LE mode whereas IP can vary between LE/BE mode ?
>
> For long term, we can discuss on APIs/name of Lib/Function name etc
> We will update our code, as per agreement.
I think this is not my call; please talk to Leif and Ard.
Thanks
Laszlo
> For me, Suggested approach is ok as well to keep CPU endianness in ARM package.
> but need views from Ard/Leif here.
>
> Thanks
> Udit
>
>> -----Original Message-----
>> From: Laszlo Ersek [mailto:lersek@redhat.com]
>> Sent: Friday, February 23, 2018 4:17 PM
>> To: Udit Kumar <udit.kumar@nxp.com>; Leif Lindholm
>> <leif.lindholm@linaro.org>
>> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
>> ard.biesheuvel@linaro.org
>> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
>> for Big Endian Mmio APIs
>>
>> On 02/23/18 11:25, Udit Kumar wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf
>>>> Of Laszlo Ersek
>>>> Sent: Thursday, February 22, 2018 7:26 PM
>>>> To: Leif Lindholm <leif.lindholm@linaro.org>
>>>> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
>>>> ard.biesheuvel@linaro.org
>>>> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add
>>>> support for Big Endian Mmio APIs
>>>>
>>>> On 02/22/18 12:52, Leif Lindholm wrote:
>>>>> On Thu, Feb 22, 2018 at 09:34:05AM +0100, Laszlo Ersek wrote:
>>>>
>>>>>>> But that brings back the complication as to how we have a driver
>>>>>>> that needs an LE IO library to write output, and a BE IO library
>>>>>>> to manipulate the hardware.
>>>>>>
>>>>>> Can you please explain the "write output" use case more precisely?
>>>>>>
>>>>>> My thinking would be this:
>>>>>>
>>>>>> - Use the IoLib class directly for "writing output" in little
>>>>>> endian byte order (which is still unclear to me sorry).
>>>>>
>>>>> If the IoLib class is mapped to a an instance that byte-swaps
>>>>> (hereto referred to as BeIoLib if IoLibSwap is unsuitable), would we
>>>>> not then end up mapping the non-swapping, currently implemented in
>>>>> BaseLibIoIntrinsic, variant as BeIoLib? Or if not, do we end up
>>>>> needing to duplicated all IoLib implementation .infs to provide an
>>>>> IoLib and a BeIoLib for each?
>>>>>
>>>>> It's at that point I burst an aneurysm.
>>>>> Am I overthinking/underthinking this?
>>>>
>>>> We need two library classes, one for talking to LE devices and
>>>> another to BE devices. These should be usable in a given module at
>>>> the same time, as Ard says.
>>>>
>>>> Both library classes need to work on both LE and BE CPUs (working
>>>> from your suggestion that UEFI might grow BE CPU support at some
>>>> point). Whether that is implemented by dumb, separate library
>>>> instances (yielding in total 2*2=4 library instances), or by smart,
>>>> CPU-endianness-agnostic library instances (in total, 2), is a
>>>> different question.
>>>>
>>>> Note that such "smarts" could be less than trivial to implement:
>>>> - check CPU endianness in each library API?
>>>> - or check in the lib constructor only, and flip some function
>>>> pointers?
>>>> - use a dynamic PCD for caching CPU endianness?
>>>> - use a HOB for the same?
>>>> - use a lib global variable (for caching only on the module level)?
>>>>
>>>> I think the solution that saves the most on the *source* code size
>>>> is:
>>>> - introduce the BeIoLib class
>>>> - duplicate the MMIO functions from BaseIoLibIntrinsic to the one
>>>> BeIoLib instance that we introduce
>>>> - modify the MMIO functions in *both* lib instances (original LE, and
>>>> new BE), like this:
>>>>
>>>> - If the CPU architecture is known to be bound to a single
>>>> endianness, then hardcode the appropriate operation. This can be
>>>> done with preprocessor macros, or with the architecture support
>>>> of INF files / separate source files. For example, on IA32 and
>>>> X64, the IoLib instance should work transparently,
>>>> unconditionally, and the BeIoLib instance should byte-swap,
>>>> unconditionally.
>>>>
>>>> - On other CPU arches, all the wider-than-byte MMIO functions, in
>>>> *both* lib instances should do something like this:
>>>>
>>>> //
>>>> // at file scope
>>>> //
>>>> STATIC CONST UINT16 mOne = 1;
>>>>
>>>> //
>>>> // at function scope
>>>> //
>>>> if (*(CONST UINT8 *)&mOne == 1) {
>>>> //
>>>> // CPU in LE mode:
>>>> // - work transparently in the IoLib instance
>>>> // - byte-swap in the BeIoLib instance
>>>> //
>>>> } else {
>>>> //
>>>> // CPU in BE mode:
>>>> // - byte-swap in the IoLib instance
>>>> // - work transparently in the BeIoLib instance
>>>> //
>>>> }
>>>
>>> You meant, sort of cpu_to_le and cpu_to_be sort of APIs
>>
>> I'm lost. I don't know how to put it any clearer. Let me try with actual
>> code.
>>
>> (a) Suggested for "MdePkg/Library/BaseIoLibIntrinsic/IoLib.c", which is
>> used on IA32 and X64, therefore CPU byte order is little endian only:
>>
>>> UINT32
>>> EFIAPI
>>> MmioWrite32 (
>>> IN UINTN Address,
>>> IN UINT32 Value
>>> )
>>> {
>>> ASSERT ((Address & 3) == 0);
>>>
>>> MemoryFence ();
>>> *(volatile UINT32*)Address = Value;
>>> MemoryFence ();
>>>
>>> return Value;
>>> }
>>
>> In other words, no change to the current implementation.
>>
>>
>> (b) Suggested for "MdePkg/Library/BaseBeIoLibIntrinsic/IoLib.c", also to
>> be used on IA32 and X64. Because the CPU byte order is LE only, this
>> variant will byte-swap unconditionally.
>>
>>> UINT32
>>> EFIAPI
>>> BeMmioWrite32 (
>>> IN UINTN Address,
>>> IN UINT32 Value
>>> )
>>> {
>>> ASSERT ((Address & 3) == 0);
>>>
>>> MemoryFence ();
>>> *(volatile UINT32*)Address = SwapBytes32 (Value);
>>> MemoryFence ();
>>>
>>> return Value;
>>> }
>>
>> (c) Suggested for "MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c", which
>> is used on ARM and AARCH64. And here I'll assume that the CPU byte order
>> on those can be either LE or BE.
>>
>>> UINT32
>>> EFIAPI
>>> MmioWrite32 (
>>> IN UINTN Address,
>>> IN UINT32 Value
>>> )
>>> {
>>> ASSERT ((Address & 3) == 0);
>>> *(volatile UINT32*)Address = (*(CONST UINT8 *)&mOne == 1) ?
>>> Value :
>>> SwapBytes32 (Value);
>>> return Value;
>>> }
>>
>>
>> (d) Suggested for "MdePkg/Library/BaseBeIoLibIntrinsic/BeIoLibArm.c",
>> which is to be used on ARM and AARCH64. And here I'll assume that the
>> CPU byte order on those can be either LE or BE.
>>
>>> UINT32
>>> EFIAPI
>>> BeMmioWrite32 (
>>> IN UINTN Address,
>>> IN UINT32 Value
>>> )
>>> {
>>> ASSERT ((Address & 3) == 0);
>>> *(volatile UINT32*)Address = (*(CONST UINT8 *)&mOne == 1) ?
>>> SwapBytes32 (Value) :
>>> Value;
>>> return Value;
>>> }
>
>
>> Laszlo
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-23 11:48 ` Pankaj Bansal
@ 2018-02-23 15:17 ` Laszlo Ersek
0 siblings, 0 replies; 254+ messages in thread
From: Laszlo Ersek @ 2018-02-23 15:17 UTC (permalink / raw)
To: Pankaj Bansal, Udit Kumar, Leif Lindholm
Cc: michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org, Meenakshi Aggarwal
On 02/23/18 12:48, Pankaj Bansal wrote:
>> -----Original Message-----
>> From: Laszlo Ersek [mailto:lersek@redhat.com]
>> Sent: Friday, February 23, 2018 4:52 PM
>> To: Pankaj Bansal <pankaj.bansal@nxp.com>; Udit Kumar
>> <udit.kumar@nxp.com>; Leif Lindholm <leif.lindholm@linaro.org>
>> Cc: michael.d.kinney@intel.com; edk2-devel@lists.01.org;
>> ard.biesheuvel@linaro.org; Meenakshi Aggarwal
>> <meenakshi.aggarwal@nxp.com>
>> Subject: Re: [edk2] [PATCH edk2-platforms 01/39] Silicon/NXP: Add support
>> for Big Endian Mmio APIs
>>
>> On 02/23/18 12:04, Pankaj Bansal wrote:
>>
>>> However Laszlo, with the method you suggest (using STATIC CONST
>>> UINT16 mOne), would it not add delay in each Mmio Operation ?
>>>
>>> I am concerned about boot delay using this approach.
>> The condition can be evaluated at compile time, so I expect optimizing
>> compilers to eliminate the dead branch.
>>
>> Assuming the condition cannot be eliminated at build time, what is your
>> concern: the single byte access, or the branch instruction?
>>
>> I don't think the single byte access matters. (If you tried to replace that with a
>> HOB or PCD lookup, it could only be worse.)
>>
>> I also doubt the branch should be a concern. You could replace the "if"
>> (or the ternary operator "?:") with function pointers that you set e.g.
>> in a constructor function. But I think an "if" with an invariable
>> (constant) controlling expression is at least as friendly towards branch
>> predictors as a function pointer variable (through which you might be
>> *forced* to make a real function call).
>>
>> Personally I wouldn't worry.
>>
>
> I think you are right about smart compiler eliminating the branches at build time.
> I just pointed this out because we call Mmio/BeMmio APIs when accessing Nor flash for variable read/write.
> As these are called so many time during boot, I did not want any delay to be added to these APIs than necessary.
> Now that you have pointed it out, I don't think any significant delay will be added to these APIs.
In addition to that, physical flash access is likely so slow anyway that
a few additional instructions should be lost in the noise, generally
speaking.
Thanks
Laszlo
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs
2018-02-23 10:47 ` Laszlo Ersek
2018-02-23 11:48 ` Udit Kumar
@ 2018-02-28 13:19 ` Leif Lindholm
1 sibling, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-02-28 13:19 UTC (permalink / raw)
To: Laszlo Ersek
Cc: Udit Kumar, michael.d.kinney@intel.com, edk2-devel@lists.01.org,
ard.biesheuvel@linaro.org
On Fri, Feb 23, 2018 at 11:47:28AM +0100, Laszlo Ersek wrote:
> >> I think the solution that saves the most on the *source* code size
> >> is:
> >> - introduce the BeIoLib class
> >> - duplicate the MMIO functions from BaseIoLibIntrinsic to the one
> >> BeIoLib instance that we introduce
> >> - modify the MMIO functions in *both* lib instances (original LE, and
> >> new BE), like this:
> >>
> >> - If the CPU architecture is known to be bound to a single
> >> endianness, then hardcode the appropriate operation. This can be
> >> done with preprocessor macros, or with the architecture support
> >> of INF files / separate source files. For example, on IA32 and
> >> X64, the IoLib instance should work transparently,
> >> unconditionally, and the BeIoLib instance should byte-swap,
> >> unconditionally.
> >>
> >> - On other CPU arches, all the wider-than-byte MMIO functions, in
> >> *both* lib instances should do something like this:
> >>
> >> //
> >> // at file scope
> >> //
> >> STATIC CONST UINT16 mOne = 1;
> >>
> >> //
> >> // at function scope
> >> //
> >> if (*(CONST UINT8 *)&mOne == 1) {
> >> //
> >> // CPU in LE mode:
> >> // - work transparently in the IoLib instance
> >> // - byte-swap in the BeIoLib instance
> >> //
> >> } else {
> >> //
> >> // CPU in BE mode:
> >> // - byte-swap in the IoLib instance
> >> // - work transparently in the BeIoLib instance
> >> //
> >> }
> >
> > You meant, sort of cpu_to_le and cpu_to_be sort of APIs
>
> I'm lost. I don't know how to put it any clearer. Let me try with actual
> code.
>
> (a) Suggested for "MdePkg/Library/BaseIoLibIntrinsic/IoLib.c", which is
> used on IA32 and X64, therefore CPU byte order is little endian only:
>
> > UINT32
> > EFIAPI
> > MmioWrite32 (
> > IN UINTN Address,
> > IN UINT32 Value
> > )
> > {
> > ASSERT ((Address & 3) == 0);
> >
> > MemoryFence ();
> > *(volatile UINT32*)Address = Value;
> > MemoryFence ();
> >
> > return Value;
> > }
>
> In other words, no change to the current implementation.
>
>
> (b) Suggested for "MdePkg/Library/BaseBeIoLibIntrinsic/IoLib.c", also to
> be used on IA32 and X64. Because the CPU byte order is LE only, this
> variant will byte-swap unconditionally.
>
> > UINT32
> > EFIAPI
> > BeMmioWrite32 (
> > IN UINTN Address,
> > IN UINT32 Value
> > )
> > {
> > ASSERT ((Address & 3) == 0);
> >
> > MemoryFence ();
> > *(volatile UINT32*)Address = SwapBytes32 (Value);
> > MemoryFence ();
> >
> > return Value;
> > }
>
> (c) Suggested for "MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c", which
> is used on ARM and AARCH64. And here I'll assume that the CPU byte order
> on those can be either LE or BE.
We badly need to reduce the number of architecture-specific libraries
for doing mmio accesses from C code, rather than increasing them.
So, I realise I've confused the situation somewhat here by talking
about big-endian CPUs. We are not looking to support big-endian CPUs
today. All I wanted was to make sure we don't unneccesarily build in
assumptions in the codebase about things that could change in the
future with fairly minor changes to the specifications.
What I do see as an absolute is that a single _UEFI_ architecture
could never be more than one possible endianness. I.e., if someone
wanted to (and this _really_ isn't me being *nudge* *nudge*, *wink*
*wink*) bring in a BE-port of AArch64, that wouldn't be AARCH64, that
would be AARCH64BE.
Which also means I don't think there is any need for any sort of
runtime detection of this.
Your proposal of a set of function-pointers in the driver being mapped
to appropriate device endianness on initialization seems sufficient to
resolve the situation posed. And the situation feels sufficiently
esoteric to motivate that level of clunkiness.
Regards,
Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 16/39] Silicon/NXP : Add NOR driver.
2018-02-16 8:50 ` [PATCH edk2-platforms 16/39] Silicon/NXP : Add NOR driver Meenakshi
@ 2018-04-17 16:23 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-17 16:23 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
(Responding somewhat out of sequence, as I'm going through to build
this port and encountering issues.)
This patch will require something similar to
edk2-platforms 79c9dd55a32752b7ae11d5f1a50fa3ae27d6d126 in order to
work with recent upstream edk2. (gVariableRuntimeDxeFileGuid has gone
away with edk2 6281a2ed3bb3ffe57ed54cabd9a31dcf13b415f8.)
(Further comments inline below.)
On Fri, Feb 16, 2018 at 02:20:12PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> Add NOR DXE phase driver, it installs BlockIO and Fvp
> protocol.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 98 +++
> .../NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c | 258 +++++++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c | 438 +++++++++++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h | 146 ++++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf | 66 ++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c | 805 +++++++++++++++++++++
> 6 files changed, 1811 insertions(+)
> create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
> new file mode 100644
> index 0000000..e254337
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
> @@ -0,0 +1,98 @@
> +## @file
> +# FDF include file with FD definition that defines an empty variable store.
> +#
> +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
> +# Copyright (C) 2014, Red Hat, Inc.
> +# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
> +# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available
> +# under the terms and conditions of the BSD License which accompanies this
> +# distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> +# IMPLIED.
> +#
> +##
> +
> +[FD.LS1043aRdbNv_EFI]
> +BaseAddress = 0x60300000 #The base address of the FLASH device
> +Size = 0x000C0000 #The size in bytes of the FLASH device
> +ErasePolarity = 1
> +BlockSize = 0x1
> +NumBlocks = 0xC0000
> +
> +#
> +# Place NV Storage just above Platform Data Base
> +#
> +DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
> +DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
> +DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
> +DEFINE FTW_WORKING_SIZE = 0x00040000
> +DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
> +DEFINE FTW_SPARE_SIZE = 0x00040000
> +
> +#############################################################################
> +# LS1043ARDB NVRAM Area
> +# LS1043ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
> +#############################################################################
> +
> +
> +$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +#NV_VARIABLE_STORE
> +DATA = {
> + ## This is the EFI_FIRMWARE_VOLUME_HEADER
> + # ZeroVector []
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + # FileSystemGuid: gEfiSystemNvDataFvGuid =
> + # { 0xFFF12B8D, 0x7696, 0x4C8B,
> + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
> + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
> + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
> + # FvLength: 0xC0000
> + 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
> + # Signature "_FVH" # Attributes
> + 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
> + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
> + 0x48, 0x00, 0xC2, 0xF9, 0x00, 0x00, 0x00, 0x02,
> + # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
> + 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
> + # Blockmap[1]: End
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + ## This is the VARIABLE_STORE_HEADER
> + # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
> + # Signature: gEfiAuthenticatedVariableGuid =
> + # { 0xaaf32c78, 0x947b, 0x439a,
> + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
> + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
> + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
> + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
> + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
> + # This can speed up the Variable Dispatch a bit.
> + 0xB8, 0xFF, 0x03, 0x00,
> + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
> + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +#NV_FTW_WORKING
> +DATA = {
> + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
> + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
> + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
> + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
> + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
> + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
> + # WriteQueueSize: UINT64
> + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +#NV_FTW_SPARE
> diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
> new file mode 100644
> index 0000000..efa2197
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
> @@ -0,0 +1,258 @@
> +/** @NorFlashBlockIoDxe.c
> +
> + Based on NorFlash implementation available in
> + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
> +
> + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/DebugLib.h>
> +#include <Library/NorFlashLib.h>
> +
> +#include <NorFlash.h>
> +#include "NorFlashDxe.h"
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoReset (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN BOOLEAN ExtendedVerification
> + )
> +{
> + NOR_FLASH_INSTANCE *Instance;
> +
> + Instance = INSTANCE_FROM_BLKIO_THIS (This);
> +
> + DEBUG ((DEBUG_INFO, "NorFlashBlockIoReset (MediaId=0x%x)\n",
> + This->Media->MediaId));
> +
> + return NorFlashPlatformReset (Instance->DeviceBaseAddress);
> +}
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoReadBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN UINT32 MediaId,
> + IN EFI_LBA Lba,
> + IN UINTN BufferSizeInBytes,
> + OUT VOID *Buffer
> + )
> +{
> + NOR_FLASH_INSTANCE *Instance;
> + EFI_STATUS Status;
> + EFI_BLOCK_IO_MEDIA *Media;
> + UINTN NumBlocks;
> + UINT8 *ReadBuffer;
> + UINTN BlockCount;
> + UINTN BlockSizeInBytes;
> + EFI_LBA CurrentBlock;
> +
> + Status = EFI_SUCCESS;
> +
> + if ((This == NULL) || (Buffer == NULL)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Instance = INSTANCE_FROM_BLKIO_THIS (This);
> + Media = This->Media;
> +
> + if (Media == NULL) {
> + DEBUG ((DEBUG_ERROR, "%a : Media is NULL\n", __FUNCTION__));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + NumBlocks = ((UINTN)BufferSizeInBytes) / Instance->Media.BlockSize ;
BufferSizeInBytes is already UINTN, why the cast?
> +
> + DEBUG ((DEBUG_BLKIO, "%a : (MediaId=0x%x, Lba=%ld, "
> + "BufferSize=0x%x bytes (%d kB)"
> + ", BufferPtr @ 0x%p)\n",
> + __FUNCTION__,MediaId, Lba,
> + BufferSizeInBytes, Buffer));
Please don't break output string:
I'm happy to take either
DEBUG ((DEBUG_BLKIO,
"%a : (MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%p)\n",
__FUNCTION__,MediaId, Lba, BufferSizeInBytes, Buffer));
or two calls to DEBUG on separate lines.
> +
> + if (!Media) {
> + Status = EFI_INVALID_PARAMETER;
> + }
> + else if (!Media->MediaPresent) {
> + Status = EFI_NO_MEDIA;
> + }
> + else if (Media->MediaId != MediaId) {
> + Status = EFI_MEDIA_CHANGED;
> + }
This is a lot of tests where most of them just set a return value.
The compiler will take care of any optimisation required - just return
directly and skip all these elses.
But, when using elses elsewhere, please put them on same line as }.
> + else if ((Media->IoAlign >= 2) &&
> + (((UINTN)Buffer & (Media->IoAlign - 1)) != 0)) {
Please indent continuation to reflect it's inside the if test.
else if ((Media->IoAlign >= 2) &&
(((UINTN)Buffer & (Media->IoAlign - 1)) != 0)) {
(Well, if you drop the else as per above, this fits in 80 columns.)
> + Status = EFI_INVALID_PARAMETER;
> + }
> + else if (BufferSizeInBytes == 0) {
> + // Return if we have not any byte to read
> + Status = EFI_SUCCESS;
> + }
> + else if ((BufferSizeInBytes % Media->BlockSize) != 0) {
> + // The size of the buffer must be a multiple of the block size
> + DEBUG ((DEBUG_ERROR, "%a : BlockSize in bytes = 0x%x\n",__FUNCTION__,
> + BufferSizeInBytes));
Indentation. (Please adjust throughout.)
> + Status = EFI_INVALID_PARAMETER;
> + } else if ((Lba + NumBlocks - 1) > Media->LastBlock) {
> + // All blocks must be within the device
> + DEBUG ((DEBUG_ERROR, "%a : Read will exceed last block %d, %d, %d \n",
> + __FUNCTION__, Lba, NumBlocks, Media->LastBlock));
> + Status = EFI_INVALID_PARAMETER;
> + } else {
And just make this the remainder of the function.
> + BlockSizeInBytes = Instance->Media.BlockSize;
> +
> + /* Because the target *Buffer is a pointer to VOID,
> + * we must put all the data into a pointer
> + * to a proper data type, so use *ReadBuffer */
> + ReadBuffer = (UINT8 *)Buffer;
> +
> + CurrentBlock = Lba;
> + // Read data block by Block
> + for (BlockCount = 0; BlockCount < NumBlocks; BlockCount++, CurrentBlock++,
> + ReadBuffer = ReadBuffer + BlockSizeInBytes) {
Could you reformat this as
for (BlockCount = 0; BlockCount < NumBlocks; BlockCount++) {
...
CurrentBlock++;
ReadBuffer = ReadBuffer + BlockSizeInBytes;
}
?
> + DEBUG ((DEBUG_BLKIO, "%a: Reading block #%d\n",
> + __FUNCTION__,(UINTN)CurrentBlock));
Missing space after ','.
> +
> + Status = NorFlashPlatformRead (Instance, CurrentBlock, (UINTN)0 ,
Does that 0 need a (UINTN)? Trailing space after 0.
> + BlockSizeInBytes,ReadBuffer);
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> + }
> + }
> + DEBUG ((DEBUG_BLKIO,"%a: Exit Status = \"%r\".\n",__FUNCTION__,Status));
And move this DEBUG to call sites if needed.
> +
> + return Status;
> +}
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoWriteBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN UINT32 MediaId,
> + IN EFI_LBA Lba,
> + IN UINTN BufferSizeInBytes,
> + IN VOID *Buffer
> + )
> +{
> + NOR_FLASH_INSTANCE *Instance;
> + EFI_STATUS Status;
> + EFI_BLOCK_IO_MEDIA *Media;
> + UINTN NumBlocks;
> + EFI_LBA CurrentBlock;
> + UINTN BlockSizeInBytes;
> + UINT32 BlockCount;
> + UINTN SectorAddress;
> + UINT8 *WriteBuffer;
> +
> + Status = EFI_SUCCESS;
> +
> + if ((This == NULL) || (Buffer == NULL)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Instance = INSTANCE_FROM_BLKIO_THIS (This);
> + Media = This->Media;
> +
> + if (Media == NULL) {
> + DEBUG ((DEBUG_ERROR, "%a : Media is NULL\n", __FUNCTION__));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + NumBlocks = ((UINTN)BufferSizeInBytes) / Instance->Media.BlockSize ;
BufferSizeInBytes is already UINTN.
> +
> + DEBUG ((DEBUG_BLKIO, "%a : (MediaId=0x%x, Lba=%ld, BufferSize=0x%x "
> + "bytes (%d kB) BufferPtr @ 0x%08x)\n",
> + __FUNCTION__,MediaId, Lba,BufferSizeInBytes, Buffer));
> +
> + if (!Media->MediaPresent) {
> + Status = EFI_NO_MEDIA;
Return directly.
> + }
> + else if (Media->MediaId != MediaId) {
No else (throughout).
> + Status = EFI_MEDIA_CHANGED;
> + }
> + else if (Media->ReadOnly) {
> + Status = EFI_WRITE_PROTECTED;
> + }
> + else if (BufferSizeInBytes == 0) {
> + Status = EFI_BAD_BUFFER_SIZE;
> + }
> + else if ((BufferSizeInBytes % Media->BlockSize) != 0) {
> + // The size of the buffer must be a multiple of the block size
> + DEBUG ((DEBUG_ERROR, "%a : BlockSize in bytes = 0x%x\n",__FUNCTION__,
> + BufferSizeInBytes));
> + Status = EFI_INVALID_PARAMETER;
> + } else if ((Lba + NumBlocks - 1) > Media->LastBlock) {
> + // All blocks must be within the device
> + DEBUG ((DEBUG_ERROR, "%a: Write will exceed last block %d, %d, %d \n",
> + __FUNCTION__,Lba, NumBlocks, Media->LastBlock));
> + Status = EFI_INVALID_PARAMETER;
> + } else {
Remainder of function.
> + BlockSizeInBytes = Instance->Media.BlockSize;
> +
> + WriteBuffer = (UINT8 *)Buffer;
> +
> + CurrentBlock = Lba;
> + // Program data block by Block
> + for (BlockCount = 0; BlockCount < NumBlocks;
> + BlockCount++, CurrentBlock++,
> + WriteBuffer = (WriteBuffer + BlockSizeInBytes)) {
Same comment for for-loop layout: can you keep only the BlockCount
update in the for statement and move the other updates to end of loop
body?
> + DEBUG ((DEBUG_BLKIO, "%a: Writing block #%d\n",
> + __FUNCTION__,(UINTN)CurrentBlock));
> + // Erase the Block(Sector) to be written to
> + SectorAddress = GET_NOR_BLOCK_ADDRESS (
> + Instance->RegionBaseAddress,
> + CurrentBlock,
> + Instance->Media.BlockSize
> + );
> + Status = NorFlashPlatformEraseSector (Instance, (UINTN)SectorAddress);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a: Failed to erase Target 0x%x (0x%x) \n",
> + __FUNCTION__,SectorAddress, Status));
> + break;
> + }
> + // Program Block(Sector) to be written to
> + Status = NorFlashWrite (Instance, CurrentBlock, (UINTN)0,
> + &BlockSizeInBytes, WriteBuffer);
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> + }
> + }
> + DEBUG ((DEBUG_BLKIO, "%a: Exit Status = \"%r\".\n",__FUNCTION__,Status));
DEBUG at call site if needed.
> + return Status;
> +}
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoFlushBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This
> + )
> +{
> +
> + DEBUG ((DEBUG_BLKIO, "%a NOT IMPLEMENTED (not required)\n", __FUNCTION__));
> +
> + // Nothing to do so just return without error
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
> new file mode 100644
> index 0000000..0e7703c
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
> @@ -0,0 +1,438 @@
> +/** @file
> +
> + Based on NorFlash implementation available in
> + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c
> +
> + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Bitops.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/NorFlashLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiRuntimeLib.h>
> +
> +#include "NorFlashDxe.h"
> +
> +STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent;
> +
> +//
> +// Global variable declarations
> +//
> +NOR_FLASH_INSTANCE **mNorFlashInstances;
> +UINT32 mNorFlashDeviceCount;
> +
> +NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
> + .Signature = NOR_FLASH_SIGNATURE,
> + .Initialized = FALSE,
> + .Initialize = NULL,
> + .StartLba = 0,
> + .BlockIoProtocol = {
> + .Revision = EFI_BLOCK_IO_PROTOCOL_REVISION2,
> + .Reset = NorFlashBlockIoReset,
> + .ReadBlocks = NorFlashBlockIoReadBlocks,
> + .WriteBlocks = NorFlashBlockIoWriteBlocks,
> + .FlushBlocks = NorFlashBlockIoFlushBlocks,
> + },
> +
> + .Media = {
> + .RemovableMedia = FALSE,
> + .MediaPresent = TRUE,
> + .LogicalPartition = FALSE,
> + .ReadOnly = FALSE,
> + .WriteCaching = FALSE,
> + .IoAlign = 4,
> + .LowestAlignedLba = 0,
> + .LogicalBlocksPerPhysicalBlock = 1,
> + },
> +
> + .FvbProtocol = {
> + .GetAttributes = FvbGetAttributes,
> + .SetAttributes = FvbSetAttributes,
> + .GetPhysicalAddress = FvbGetPhysicalAddress,
> + .GetBlockSize = FvbGetBlockSize,
> + .Read = FvbRead,
> + .Write = FvbWrite,
> + .EraseBlocks = FvbEraseBlocks,
> + .ParentHandle = NULL,
> + },
> + .ShadowBuffer = NULL,
> + .DevicePath = {
> + .Vendor = {
> + .Header = {
> + .Type = HARDWARE_DEVICE_PATH,
> + .SubType = HW_VENDOR_DP,
> + .Length = {(UINT8)sizeof (VENDOR_DEVICE_PATH),
> + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) }
> + },
> + .Guid = EFI_CALLER_ID_GUID, // GUID ... NEED TO BE FILLED
> + },
> + .End = {
> + .Type = END_DEVICE_PATH_TYPE,
> + .SubType = END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + .Length = { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
> + }
> + }
> +};
> +
> +EFI_STATUS
> +NorFlashCreateInstance (
> + IN UINTN NorFlashDeviceBase,
> + IN UINTN NorFlashRegionBase,
> + IN UINTN NorFlashSize,
> + IN UINT32 MediaId,
> + IN UINT32 BlockSize,
> + IN BOOLEAN SupportFvb,
> + OUT NOR_FLASH_INSTANCE** NorFlashInstance
> + )
> +{
> + EFI_STATUS Status;
> + NOR_FLASH_INSTANCE* Instance;
> +
> + ASSERT (NorFlashInstance != NULL);
> +
> + Instance = AllocateRuntimeCopyPool (sizeof (NOR_FLASH_INSTANCE),
> + &mNorFlashInstanceTemplate);
> + if (Instance == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + Instance->DeviceBaseAddress = NorFlashDeviceBase;
> + Instance->RegionBaseAddress = NorFlashRegionBase;
> + Instance->Size = NorFlashSize;
> +
> + Instance->BlockIoProtocol.Media = &Instance->Media;
> + Instance->Media.MediaId = MediaId;
> + Instance->Media.BlockSize = BlockSize;
> + Instance->Media.LastBlock = (NorFlashSize / BlockSize)-1;
Spaces around '-'.
> +
> + Instance->ShadowBuffer = AllocateRuntimePool (BlockSize);
> + if (Instance->ShadowBuffer == NULL) {
> + FreePool (Instance);
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + if (SupportFvb) {
> + Instance->SupportFvb = TRUE;
> + Instance->Initialize = NorFlashFvbInitialize;
> +
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &Instance->Handle,
Indent to two spaces from start of function name:
Status = gBS->InstallMultipleProtocolInterfaces (
&Instance->Handle,
> + &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
> + &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol,
> + &gEfiFirmwareVolumeBlockProtocolGuid, &Instance->FvbProtocol,
> + NULL
> + );
> + if (EFI_ERROR (Status)) {
> + FreePool (Instance->ShadowBuffer);
> + FreePool (Instance);
> + return Status;
> + }
> + } else {
> + Instance->Initialized = TRUE;
> +
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &Instance->Handle,
> + &gEfiDevicePathProtocolGuid, &Instance->DevicePath,
> + &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol,
> + NULL
> + );
> + if (EFI_ERROR (Status)) {
> + FreePool (Instance->ShadowBuffer);
> + FreePool (Instance);
> + return Status;
> + }
> + }
> +
> + *NorFlashInstance = Instance;
> +
> + return Status;
> +}
> +
> +/*
> + Write a full or portion of a block.
> + It must not span block boundaries; that is,
> + Offset + NumBytes <= Instance->Media.BlockSize.
> + */
> +EFI_STATUS
> +NorFlashWrite (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> +)
> +{
> + EFI_STATUS Status;
> + UINTN BlockSize;
> + BOOLEAN DoErase;
> + VOID *Source;
> + UINTN SectorAddress;
> +
> + Status = EFI_SUCCESS;
> + Source = NULL;
> +
> + DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=%ld, Offset=0x%x, NumBytes=0x%x, "
> + "Buffer @ 0x%08x)\n", __FUNCTION__,
> + Lba, Offset, *NumBytes, Buffer));
> +
> + // The buffer must be valid
> + if (Buffer == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Detect WriteDisabled state
> + if (Instance->Media.ReadOnly == TRUE) {
> + DEBUG ((DEBUG_ERROR, "NorFlashWrite: ERROR - Can not write: "
> + "Device is in WriteDisabled state.\n"));
> + // It is in WriteDisabled state, return an error right away
> + return EFI_ACCESS_DENIED;
> + }
> +
> + // Cache the block size to avoid de-referencing pointers all the time
> + BlockSize = Instance->Media.BlockSize;
> +
> + // We must have some bytes to write
> + if ((*NumBytes == 0) || (*NumBytes > BlockSize)) {
> + DEBUG ((DEBUG_ERROR, "NorFlashWrite: ERROR - EFI_BAD_BUFFER_SIZE: "
> + "(Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", \
> + Offset, *NumBytes, BlockSize ));
> + return EFI_BAD_BUFFER_SIZE;
> + }
> +
> + if (((Lba * BlockSize) + Offset + *NumBytes) > Instance->Size) {
> + DEBUG ((DEBUG_ERROR, "%a: ERROR - Write will exceed device size.\n",
> + __FUNCTION__));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Check we did get some memory. Buffer is BlockSize.
> + if (Instance->ShadowBuffer == NULL) {
> + DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - Buffer not ready\n"));
> + return EFI_DEVICE_ERROR;
> + }
> +
> + SectorAddress = GET_NOR_BLOCK_ADDRESS (
> + Instance->RegionBaseAddress,
> + Lba,
> + Instance->Media.BlockSize);
> +
> + // Pick 128bytes as a good start for word operations as opposed to erasing the
> + // block and writing the data regardless if an erase is really needed.
> + // It looks like most individual NV variable writes are smaller than 128bytes.
> + if (*NumBytes <= 128) {
> + Source = Instance->ShadowBuffer;
> + //First Read the data into shadow buffer from location where data is to be written
> + Status = NorFlashPlatformRead (
> + Instance,
> + Lba,
> + Offset,
> + *NumBytes,
> + Source);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a: ERROR - Failed to "
> + "Read @ %p Status=%d\n", __FUNCTION__,
> + Offset + SectorAddress, Status));
> + return Status;
> + }
> + // Check to see if we need to erase before programming the data into NorFlash.
> + // If the destination bits are only changing from 1s to 0s we can
> + // just write. After a block is erased all bits in the block is set to 1.
> + // If any byte requires us to erase we just give up and rewrite all of it.
> + DoErase = TestBitSetClear (Source, Buffer, *NumBytes, TRUE);
> +
> + // if we got here then write all the data. Otherwise do the
> + // Erase-Write cycle.
> + if (!DoErase) {
> + Status = NorFlashPlatformWriteBuffer (
> + Instance,
> + Lba,
> + Offset,
> + NumBytes,
> + Buffer);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a: ERROR - Failed to "
> + "Write @ %p Status=%d\n", __FUNCTION__,
> + Offset + SectorAddress, Status));
> + return Status;
> + }
> + return EFI_SUCCESS;
> + }
> + }
> +
> + // If we are not going to write full block, read block and then update bytes in it
> + if (*NumBytes != BlockSize) {
> + // Read NorFlash Flash data into shadow buffer
> + Status = NorFlashBlockIoReadBlocks (
> + &(Instance->BlockIoProtocol),
> + Instance->Media.MediaId,
> + Lba,
> + BlockSize,
> + Instance->ShadowBuffer);
> + if (EFI_ERROR (Status)) {
> + // Return one of the pre-approved error statuses
> + return EFI_DEVICE_ERROR;
> + }
> + // Put the data at the appropriate location inside the buffer area
> + CopyMem ((VOID *)((UINTN)Instance->ShadowBuffer + Offset), Buffer, *NumBytes);
> + }
> + //Erase Block
> + Status = NorFlashPlatformEraseSector (Instance, SectorAddress);
> + if (EFI_ERROR (Status)) {
> + // Return one of the pre-approved error statuses
> + return EFI_DEVICE_ERROR;
> + }
> + if (*NumBytes != BlockSize) {
> + // Write the modified shadow buffer back to the NorFlash
> + Status = NorFlashPlatformWriteBuffer (
> + Instance,
> + Lba,
> + 0,
> + &BlockSize,
> + Instance->ShadowBuffer);
> + } else {
> + // Write the Buffer to an entire block in NorFlash
> + Status = NorFlashPlatformWriteBuffer (
> + Instance,
> + Lba,
> + 0,
> + &BlockSize,
> + Buffer);
> + }
> + if (EFI_ERROR (Status)) {
> + // Return one of the pre-approved error statuses
> + return EFI_DEVICE_ERROR;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Fixup internal data so that EFI can be call in virtual mode.
> + Call the passed in Child Notify event and convert any pointers in
> + lib to virtual mode.
> +
> + @param[in] Event The Event that is being processed
> + @param[in] Context Event Context
> +**/
> +VOID
> +EFIAPI
> +NorFlashVirtualNotifyEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + UINTN Index;
> +
> + for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->DeviceBaseAddress);
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->RegionBaseAddress);
> +
> + // Convert BlockIo protocol
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.FlushBlocks);
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.ReadBlocks);
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.Reset);
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.WriteBlocks);
> +
> + // Convert Fvb
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.EraseBlocks);
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetAttributes);
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetBlockSize);
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetPhysicalAddress);
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Read);
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.SetAttributes);
> + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Write);
> + if (mNorFlashInstances[Index]->ShadowBuffer != NULL) {
> + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->ShadowBuffer);
> + }
> + }
> +
> + return;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +NorFlashInitialise (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 Index;
> + NorFlashDescription* NorFlashDevices;
> + BOOLEAN ContainVariableStorage;
> +
> + ContainVariableStorage = 0;
> +
> + Status = NorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashDeviceCount);
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a : Failed to get Nor devices (0x%x)\n",
> + __FUNCTION__, Status));
> + return Status;
> + }
> +
> + Status = NorFlashPlatformFlashGetAttributes (NorFlashDevices, mNorFlashDeviceCount);
> + if (EFI_ERROR(Status)) {
> + DEBUG ((DEBUG_ERROR, "%a : Failed to get NOR device attributes (0x%x)\n",
> + __FUNCTION__, Status));
> + ASSERT_EFI_ERROR (Status); // System becomes unusable if NOR flash is not detected
> + return Status;
> + }
> +
> + mNorFlashInstances = AllocateRuntimePool (
> + sizeof(NOR_FLASH_INSTANCE*) * mNorFlashDeviceCount);
> + if (mNorFlashInstances == NULL) {
> + DEBUG ((DEBUG_ERROR, "%a : Failed to allocate runtime memory \n"));
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
> + // Check if this NOR Flash device contain the variable storage region
> + ContainVariableStorage =
> + (NorFlashDevices[Index].RegionBaseAddress <= PcdGet64 (PcdFlashNvStorageVariableBase64)) &&
> + (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvStorageVariableSize) <=
> + NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size);
> +
> + Status = NorFlashCreateInstance (
> + NorFlashDevices[Index].DeviceBaseAddress,
> + NorFlashDevices[Index].RegionBaseAddress,
> + NorFlashDevices[Index].Size,
> + Index,
> + NorFlashDevices[Index].BlockSize,
> + ContainVariableStorage,
> + &mNorFlashInstances[Index]);
> +
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a : Failed to create instance for "
> + "NorFlash[%d] (0x%x)\n",Index, Status));
> + }
> + }
> +
> + //
> + // Register for the virtual address change event
> + //
> + Status = gBS->CreateEventEx (
> + EVT_NOTIFY_SIGNAL,
> + TPL_NOTIFY,
> + NorFlashVirtualNotifyEvent,
> + NULL,
> + &gEfiEventVirtualAddressChangeGuid,
> + &mNorFlashVirtualAddrChangeEvent);
> +
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "Failed to create VirtualAddressChange event 0x%x\n", Status));
> + }
> +
> + return Status;
> +}
> diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
> new file mode 100644
> index 0000000..24504f2
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
> @@ -0,0 +1,146 @@
> +/** @NorFlashDxe.h
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __NOR_FLASH_DXE_H__
> +#define __NOR_FLASH_DXE_H__
> +
> +#include <Protocol/BlockIo.h>
> +#include <Protocol/FirmwareVolumeBlock.h>
> +
> +#define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize) ( BaseAddr + (UINTN)((Lba) * LbaSize) )
> +
> +#define NOR_FLASH_SIGNATURE SIGNATURE_32('n', 'o', 'r', '0')
> +
> +#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, NOR_FLASH_SIGNATURE)
> +
> +#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, BlockIoProtocol, NOR_FLASH_SIGNATURE)
> +
> +EFI_STATUS
> +EFIAPI
> +NorFlashFvbInitialize (
> + IN NOR_FLASH_INSTANCE* Instance
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbGetAttributes(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbSetAttributes(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbGetPhysicalAddress(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + OUT EFI_PHYSICAL_ADDRESS *Address
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbGetBlockSize(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + OUT UINTN *BlockSize,
> + OUT UINTN *NumberOfBlocks
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbRead(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN OUT UINT8 *Buffer
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbWrite(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +FvbEraseBlocks(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + ...
> + );
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoReset (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN BOOLEAN ExtendedVerification
> + );
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoReadBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN UINT32 MediaId,
> + IN EFI_LBA Lba,
> + IN UINTN BufferSizeInBytes,
> + OUT VOID *Buffer
> +);
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoWriteBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN UINT32 MediaId,
> + IN EFI_LBA Lba,
> + IN UINTN BufferSizeInBytes,
> + IN VOID *Buffer
> +);
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoFlushBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This
> +);
> +
> +EFI_STATUS
> +NorFlashWrite (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> +);
> +
> +#endif /* __NOR_FLASH_DXE_H__ */
> diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> new file mode 100644
> index 0000000..4081619
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> @@ -0,0 +1,66 @@
> +# @file
> +#
> +# Component description file for NorFlashDxe module
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = NorFlashDxe
> + FILE_GUID = 616fe8d8-f4aa-42e0-a393-b332bdb2d3c1
> + MODULE_TYPE = DXE_RUNTIME_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = NorFlashInitialise
> +
> +[Sources.common]
> + NorFlashDxe.c
> + NorFlashFvbDxe.c
> + NorFlashBlockIoDxe.c
> +
> +[Packages]
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + DxeServicesTableLib
> + HobLib
> + NorFlashLib
> + UefiDriverEntryPoint
> + UefiRuntimeLib
> +
> +[Guids]
> + gEfiSystemNvDataFvGuid
> + gEfiVariableGuid
> + gEfiAuthenticatedVariableGuid
> + gEfiEventVirtualAddressChangeGuid
> +
> +[Protocols]
> + gEfiBlockIoProtocolGuid
> + gEfiFirmwareVolumeBlockProtocolGuid
> +
> +[Pcd.common]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize
> +
> +[Depex]
> + #
> + # NorFlashDxe must be loaded before VariableRuntimeDxe in case empty flash needs populating with default values
> + #
> + BEFORE gVariableRuntimeDxeFileGuid
(This one disappeared.)
/
Leif
> diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c
> new file mode 100644
> index 0000000..378546d
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c
> @@ -0,0 +1,805 @@
> +/** @NorFlashFvbDxe.c
> +
> + Based on NorFlash implementation available in
> + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvbDxe.c
> +
> + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Guid/VariableFormat.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/DxeServicesTableLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/NorFlashLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +#include <Library/UefiRuntimeLib.h>
> +
> +#include <NorFlash.h>
> +#include "NorFlashDxe.h"
> +
> +STATIC EFI_EVENT mFvbVirtualAddrChangeEvent;
> +STATIC UINTN mFlashNvStorageVariableBase;
> +
> +///
> +/// The Firmware Volume Block Protocol is the low-level interface
> +/// to a firmware volume. File-level access to a firmware volume
> +/// should not be done using the Firmware Volume Block Protocol.
> +/// Normal access to a firmware volume must use the Firmware
> +/// Volume Protocol. Typically, only the file system driver that
> +/// produces the Firmware Volume Protocol will bind to the
> +/// Firmware Volume Block Protocol.
> +///
> +
> +/**
> + Initialises the FV Header and Variable Store Header
> + to support variable operations.
> +
> + @param[in] Ptr - Location to initialise the headers
> +
> +**/
> +EFI_STATUS
> +InitializeFvAndVariableStoreHeaders (
> + IN NOR_FLASH_INSTANCE *Instance
> + )
> +{
> + EFI_STATUS Status;
> + VOID* Headers;
> + UINTN HeadersLength;
> + EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader;
> + VARIABLE_STORE_HEADER *VariableStoreHeader;
> +
> + if (!Instance->Initialized && Instance->Initialize) {
> + Instance->Initialize (Instance);
> + }
> +
> + HeadersLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY) + sizeof (VARIABLE_STORE_HEADER);
> + Headers = AllocateZeroPool (HeadersLength);
> + if (Headers == NULL) {
> + DEBUG ((DEBUG_ERROR, "Memory allocation failed for Headers \n"));
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + // FirmwareVolumeHeader->FvLength is declared to have the Variable area AND the FTW working area AND the FTW Spare contiguous.
> + ASSERT (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvStorageVariableSize) == PcdGet64 (PcdFlashNvStorageFtwWorkingBase64));
> + ASSERT (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) == PcdGet64 (PcdFlashNvStorageFtwSpareBase64));
> +
> + // Check if the size of the area is at least one block size
> + ASSERT ((PcdGet32 (PcdFlashNvStorageVariableSize) > 0) && (PcdGet32 (PcdFlashNvStorageVariableSize) / Instance->Media.BlockSize > 0));
> + ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingSize) > 0) && (PcdGet32 (PcdFlashNvStorageFtwWorkingSize) / Instance->Media.BlockSize > 0));
> + ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareSize) > 0) && (PcdGet32 (PcdFlashNvStorageFtwSpareSize) / Instance->Media.BlockSize > 0));
> +
> + // Ensure the Variable area Base Addresses are aligned on a block size boundaries
> + ASSERT (PcdGet64 (PcdFlashNvStorageVariableBase64) % Instance->Media.BlockSize == 0);
> + ASSERT (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) % Instance->Media.BlockSize == 0);
> + ASSERT (PcdGet64 (PcdFlashNvStorageFtwSpareBase64) % Instance->Media.BlockSize == 0);
> +
> + //
> + // EFI_FIRMWARE_VOLUME_HEADER
> + //
> + FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers;
> + CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid);
> + FirmwareVolumeHeader->FvLength =
> + PcdGet32 (PcdFlashNvStorageVariableSize) +
> + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
> + PcdGet32 (PcdFlashNvStorageFtwSpareSize);
> + FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE;
> + FirmwareVolumeHeader->Attributes = (EFI_FVB_ATTRIBUTES_2) (
> + EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
> + EFI_FVB2_READ_STATUS | // Reads are currently enabled
> + EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
> + EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
> + EFI_FVB2_ERASE_POLARITY | // After erasure all bits take this value (i.e. '1')
> + EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
> + EFI_FVB2_WRITE_ENABLED_CAP // Writes may be enabled
> + );
> + FirmwareVolumeHeader->HeaderLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY);
> + FirmwareVolumeHeader->Revision = EFI_FVH_REVISION;
> + //i.e. if blocks are 0-5 then last block = 5, total blocks = 6
> + FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->Media.LastBlock + 1;
> + FirmwareVolumeHeader->BlockMap[0].Length = Instance->Media.BlockSize;
> + FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0;
> + FirmwareVolumeHeader->BlockMap[1].Length = 0;
> + FirmwareVolumeHeader->Checksum = CalculateCheckSum16 ((UINT16*)FirmwareVolumeHeader,FirmwareVolumeHeader->HeaderLength);
> +
> + //
> + // VARIABLE_STORE_HEADER
> + //
> + VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)Headers + FirmwareVolumeHeader->HeaderLength);
> + CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid);
> + VariableStoreHeader->Size = PcdGet32(PcdFlashNvStorageVariableSize) - FirmwareVolumeHeader->HeaderLength;
> + VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED;
> + VariableStoreHeader->State = VARIABLE_STORE_HEALTHY;
> +
> + // Install the combined super-header in the NorFlash
> + Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers);
> +
> + FreePool (Headers);
> + return Status;
> +}
> +
> +/**
> + Check the integrity of firmware volume header.
> +
> + @param[in] FwVolHeader - A pointer to a firmware volume header
> +
> + @retval EFI_SUCCESS - The firmware volume is consistent
> + @retval EFI_NOT_FOUND - The firmware volume has been corrupted.
> +
> +**/
> +EFI_STATUS
> +ValidateFvHeader (
> + IN NOR_FLASH_INSTANCE *Instance
> + )
> +{
> + UINT16 Checksum;
> + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
> + VARIABLE_STORE_HEADER *VariableStoreHeader;
> + UINTN VariableStoreLength;
> + UINTN FvLength;
> +
> + FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER*)mFlashNvStorageVariableBase;
> +
> + FvLength = PcdGet32 (PcdFlashNvStorageVariableSize) + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
> + PcdGet32 (PcdFlashNvStorageFtwSpareSize);
> +
> + //
> + // Verify the header revision, header signature, length
> + // Length of FvBlock cannot be 2**64-1
> + // HeaderLength cannot be an odd number
> + //
> + if ((FwVolHeader->Revision != EFI_FVH_REVISION)
> + || (FwVolHeader->Signature != EFI_FVH_SIGNATURE)
> + || (FwVolHeader->FvLength != FvLength)) {
> + DEBUG ((DEBUG_ERROR, "%a: No Firmware Volume header present\n", __FUNCTION__));
> + return EFI_NOT_FOUND;
> + }
> +
> + // Check the Firmware Volume Guid
> + if (CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid) == FALSE ) {
> + DEBUG ((DEBUG_ERROR, "%a: Firmware Volume Guid non-compatible\n", __FUNCTION__));
> + return EFI_NOT_FOUND;
> + }
> +
> + // Verify the header checksum
> + Checksum = CalculateSum16 ((UINT16*)FwVolHeader, FwVolHeader->HeaderLength);
> + if (Checksum != 0) {
> + DEBUG ((DEBUG_ERROR, "%a: FV checksum is invalid (Checksum:0x%X)\n", __FUNCTION__, Checksum));
> + return EFI_NOT_FOUND;
> + }
> +
> + VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)FwVolHeader +
> + FwVolHeader->HeaderLength);
> +
> + // Check the Variable Store Guid
> + if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) &&
> + !CompareGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid)) {
> + DEBUG ((DEBUG_ERROR, "%a: Variable Store Guid non-compatible\n",
> + __FUNCTION__));
> + return EFI_NOT_FOUND;
> + }
> +
> + VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) - FwVolHeader->HeaderLength;
> + if (VariableStoreHeader->Size != VariableStoreLength) {
> + DEBUG ((DEBUG_ERROR, "%a: Variable Store Length does not match\n", __FUNCTION__));
> + return EFI_NOT_FOUND;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + The GetAttributes() function retrieves the attributes and
> + current settings of the block.
> +
> + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
> +
> + @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and
> + current settings are returned.
> + Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER.
> +
> + @retval EFI_SUCCESS The firmware volume attributes were returned.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbGetAttributes(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + )
> +{
> + EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes;
> + NOR_FLASH_INSTANCE *Instance;
> +
> + Instance = INSTANCE_FROM_FVB_THIS (This);
> +
> + FlashFvbAttributes = (EFI_FVB_ATTRIBUTES_2) (
> + EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
> + EFI_FVB2_READ_STATUS | // Reads are currently enabled
> + EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
> + EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
> + EFI_FVB2_ERASE_POLARITY // After erasure all bits take this value (i.e. '1')
> + );
> +
> + // Check if it is write protected
> + if (Instance->Media.ReadOnly != TRUE) {
> + FlashFvbAttributes = FlashFvbAttributes |
> + EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
> + EFI_FVB2_WRITE_ENABLED_CAP; // Writes may be enabled
> + }
> +
> + *Attributes = FlashFvbAttributes;
> +
> + DEBUG ((DEBUG_BLKIO, "FvbGetAttributes(0x%X)\n", *Attributes));
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + The SetAttributes() function sets configurable firmware volume attributes
> + and returns the new settings of the firmware volume.
> +
> + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
> +
> + @param Attributes On input, Attributes is a pointer to EFI_FVB_ATTRIBUTES_2
> + that contains the desired firmware volume settings.
> + On successful return, it contains the new settings of
> + the firmware volume.
> + Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER.
> +
> + @retval EFI_SUCCESS The firmware volume attributes were returned.
> +
> + @retval EFI_INVALID_PARAMETER The attributes requested are in conflict with the capabilities
> + as declared in the firmware volume header.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbSetAttributes(
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
> + )
> +{
> + DEBUG ((DEBUG_BLKIO, "FvbSetAttributes(0x%X) is not supported\n",*Attributes));
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + The GetPhysicalAddress() function retrieves the base address of
> + a memory-mapped firmware volume. This function should be called
> + only for memory-mapped firmware volumes.
> +
> + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
> +
> + @param Address Pointer to a caller-allocated
> + EFI_PHYSICAL_ADDRESS that, on successful
> + return from GetPhysicalAddress(), contains the
> + base address of the firmware volume.
> +
> + @retval EFI_SUCCESS The firmware volume base address was returned.
> +
> + @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbGetPhysicalAddress (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + OUT EFI_PHYSICAL_ADDRESS *Address
> + )
> +{
> + *Address = mFlashNvStorageVariableBase;
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + The GetBlockSize() function retrieves the size of the requested
> + block. It also returns the number of additional blocks with
> + the identical size. The GetBlockSize() function is used to
> + retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).
> +
> + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
> +
> + @param Lba Indicates the block for which to return the size.
> +
> + @param BlockSize Pointer to a caller-allocated UINTN in which
> + the size of the block is returned.
> +
> + @param NumberOfBlocks Pointer to a caller-allocated UINTN in
> + which the number of consecutive blocks,
> + starting with Lba, is returned. All
> + blocks in this range have a size of
> + BlockSize.
> +
> + @retval EFI_SUCCESS The firmware volume base address was returned.
> +
> + @retval EFI_INVALID_PARAMETER The requested LBA is out of range.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbGetBlockSize (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + OUT UINTN *BlockSize,
> + OUT UINTN *NumberOfBlocks
> + )
> +{
> + EFI_STATUS Status;
> + NOR_FLASH_INSTANCE *Instance;
> +
> + Instance = INSTANCE_FROM_FVB_THIS (This);
> +
> + DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize(Lba=%ld, BlockSize=0x%x, LastBlock=%ld)\n",
> + Lba, Instance->Media.BlockSize, Instance->Media.LastBlock));
> +
> + if (Lba > Instance->Media.LastBlock) {
> + DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%ld)\n",
> + __FUNCTION__, Lba, Instance->Media.LastBlock));
> + Status = EFI_INVALID_PARAMETER;
> + } else {
> + // In this platform each NorFlash device has equal sized blocks.
> + *BlockSize = (UINTN) Instance->Media.BlockSize;
> + *NumberOfBlocks = (UINTN) (Instance->Media.LastBlock - Lba + 1);
> +
> + DEBUG ((DEBUG_BLKIO, "%a : *BlockSize=0x%x, *NumberOfBlocks=0x%x.\n",
> + __FUNCTION__, *BlockSize, *NumberOfBlocks));
> +
> + Status = EFI_SUCCESS;
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Reads the specified number of bytes into a buffer from the specified block.
> +
> + The Read() function reads the requested number of bytes from the
> + requested block and stores them in the provided buffer.
> + Implementations should be mindful that the firmware volume
> + might be in the ReadDisabled state. If it is in this state,
> + the Read() function must return the status code
> + EFI_ACCESS_DENIED without modifying the contents of the
> + buffer. The Read() function must also prevent spanning block
> + boundaries. If a read is requested that would span a block
> + boundary, the read must read up to the boundary but not
> + beyond. The output parameter NumBytes must be set to correctly
> + indicate the number of bytes actually read. The caller must be
> + aware that a read may be partially completed.
> +
> + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
> +
> + @param Lba The starting logical block index from which to read.
> +
> + @param Offset Offset into the block at which to begin reading.
> +
> + @param NumBytes Pointer to a UINTN.
> + At entry, *NumBytes contains the total size of the buffer.
> + At exit, *NumBytes contains the total number of bytes read.
> +
> + @param Buffer Pointer to a caller-allocated buffer that will be used
> + to hold the data that is read.
> +
> + @retval EFI_SUCCESS The firmware volume was read successfully, and contents are
> + in Buffer.
> +
> + @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary.
> + On output, NumBytes contains the total number of bytes
> + returned in Buffer.
> +
> + @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled state.
> +
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be read.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbRead (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN OUT UINT8 *Buffer
> + )
> +{
> + UINTN BlockSize;
> + NOR_FLASH_INSTANCE *Instance;
> +
> + Instance = INSTANCE_FROM_FVB_THIS (This);
> +
> + DEBUG ((DEBUG_BLKIO, "FvbRead(Parameters: Lba=%ld, Offset=0x%x, "
> + "*NumBytes=0x%x, Buffer @ 0x%08x)\n",
> + Instance->StartLba + Lba, Offset, *NumBytes, Buffer));
> +
> + if (!Instance->Initialized && Instance->Initialize) {
> + Instance->Initialize(Instance);
> + }
> +
> + // Cache the block size to avoid de-referencing pointers all the time
> + BlockSize = Instance->Media.BlockSize;
> +
> + DEBUG ((DEBUG_BLKIO, "FvbRead: Check if (Offset=0x%x + NumBytes=0x%x) <= "
> + "BlockSize=0x%x\n", Offset, *NumBytes, BlockSize ));
> +
> + // The read must not span block boundaries.
> + while (Offset >= BlockSize) {
> + Offset -= BlockSize;
> + Lba++;
> + }
> +
> + if ((Instance->StartLba + Lba) > Instance->Media.LastBlock) {
> + DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%ld)\n",
> + __FUNCTION__, Lba, Instance->Media.LastBlock));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if ((Offset + *NumBytes) > BlockSize) {
> + *NumBytes = BlockSize-Offset;
> + }
> +
> + return NorFlashPlatformRead (Instance, Instance->StartLba + Lba,
> + Offset, *NumBytes, Buffer);
> +}
> +
> +/**
> + Writes the specified number of bytes from the input buffer to the block.
> +
> + The Write() function writes the specified number of bytes from
> + the provided buffer to the specified block and offset. If the
> + firmware volume is sticky write, the caller must ensure that
> + all the bits of the specified range to write are in the
> + EFI_FVB_ERASE_POLARITY state before calling the Write()
> + function, or else the result will be unpredictable. This
> + unpredictability arises because, for a sticky-write firmware
> + volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
> + state but cannot flip it back again. Before calling the
> + Write() function, it is recommended for the caller to first call
> + the EraseBlocks() function to erase the specified block to
> + write. A block erase cycle will transition bits from the
> + (NOT)EFI_FVB_ERASE_POLARITY state back to the
> + EFI_FVB_ERASE_POLARITY state. Implementations should be
> + mindful that the firmware volume might be in the WriteDisabled
> + state. If it is in this state, the Write() function must
> + return the status code EFI_ACCESS_DENIED without modifying the
> + contents of the firmware volume. The Write() function must
> + also prevent spanning block boundaries. If a write is
> + requested that spans a block boundary, the write must store up
> + to the boundary but not beyond. The output parameter NumBytes
> + must be set to correctly indicate the number of bytes actually
> + written. The caller must be aware that a write may be
> + partially completed. All writes, partial or otherwise, must be
> + fully flushed to the hardware before the Write() service
> + returns.
> +
> + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
> +
> + @param Lba The starting logical block index to write to.
> +
> + @param Offset Offset into the block at which to begin writing.
> +
> + @param NumBytes The pointer to a UINTN.
> + At entry, *NumBytes contains the total size of the buffer.
> + At exit, *NumBytes contains the total number of bytes actually written.
> +
> + @param Buffer The pointer to a caller-allocated buffer that contains the source for the write.
> +
> + @retval EFI_SUCCESS The firmware volume was written successfully.
> +
> + @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA boundary.
> + On output, NumBytes contains the total number of bytes
> + actually written.
> +
> + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state.
> +
> + @retval EFI_DEVICE_ERROR The block device is malfunctioning and could not be written.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbWrite (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + )
> +{
> + NOR_FLASH_INSTANCE *Instance;
> + UINTN BlockSize;
> +
> + Instance = INSTANCE_FROM_FVB_THIS (This);
> + // Cache the block size to avoid de-referencing pointers all the time
> + BlockSize = Instance->Media.BlockSize;
> +
> + if (!Instance->Initialized && Instance->Initialize) {
> + Instance->Initialize(Instance);
> + }
> +
> + // The write must not span block boundaries.
> + while(Offset >= BlockSize) {
> + Offset -= BlockSize;
> + Lba++;
> + }
> +
> + if ((Instance->StartLba + Lba) > Instance->Media.LastBlock) {
> + DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%ld)\n",
> + __FUNCTION__, Lba, Instance->Media.LastBlock));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if ((Offset + *NumBytes) > BlockSize) {
> + *NumBytes = BlockSize-Offset;
> + }
> +
> + return NorFlashWrite (Instance, Instance->StartLba + Lba,
> + Offset, NumBytes, Buffer);
> +}
> +
> +/**
> + Erases and initialises a firmware volume block.
> +
> + The EraseBlocks() function erases one or more blocks as denoted
> + by the variable argument list. The entire parameter list of
> + blocks must be verified before erasing any blocks. If a block is
> + requested that does not exist within the associated firmware
> + volume (it has a larger index than the last block of the
> + firmware volume), the EraseBlocks() function must return the
> + status code EFI_INVALID_PARAMETER without modifying the contents
> + of the firmware volume. Implementations should be mindful that
> + the firmware volume might be in the WriteDisabled state. If it
> + is in this state, the EraseBlocks() function must return the
> + status code EFI_ACCESS_DENIED without modifying the contents of
> + the firmware volume. All calls to EraseBlocks() must be fully
> + flushed to the hardware before the EraseBlocks() service
> + returns.
> +
> + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
> + instance.
> +
> + @param ... The variable argument list is a list of tuples.
> + Each tuple describes a range of LBAs to erase
> + and consists of the following:
> + - An EFI_LBA that indicates the starting LBA
> + - A UINTN that indicates the number of blocks to erase.
> +
> + The list is terminated with an EFI_LBA_LIST_TERMINATOR.
> + For example, the following indicates that two ranges of blocks
> + (5-7 and 10-11) are to be erased:
> + EraseBlocks (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR);
> +
> + @retval EFI_SUCCESS The erase request successfully completed.
> +
> + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state.
> +
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be written.
> + The firmware device may have been partially erased.
> +
> + @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable argument list do
> + not exist in the firmware volume.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +FvbEraseBlocks (
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
> + ...
> + )
> +{
> + EFI_STATUS Status;
> + VA_LIST Args;
> + UINTN BlockAddress; // Physical address of Lba to erase
> + EFI_LBA StartingLba; // Lba from which we start erasing
> + UINTN NumOfLba; // Number of Lba blocks to erase
> + NOR_FLASH_INSTANCE *Instance;
> +
> + Instance = INSTANCE_FROM_FVB_THIS (This);
> +
> + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks()\n"));
> +
> + Status = EFI_SUCCESS;
> +
> + // Detect WriteDisabled state
> + if (Instance->Media.ReadOnly == TRUE) {
> + // Firmware volume is in WriteDisabled state
> + DEBUG ((DEBUG_ERROR, "%a : Device is in WriteDisabled state\n"));
> + return EFI_ACCESS_DENIED;
> + }
> +
> + // Before erasing, check the entire list of parameters to
> + // ensure all specified blocks are valid
> +
> + VA_START (Args, This);
> + do {
> + // Get the Lba from which we start erasing
> + StartingLba = VA_ARG (Args, EFI_LBA);
> +
> + // Have we reached the end of the list?
> + if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
> + //Exit the while loop
> + break;
> + }
> +
> + // How many Lba blocks are we requested to erase?
> + NumOfLba = VA_ARG (Args, UINT32);
> +
> + // All blocks must be within range
> + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Check if: ( StartingLba=%ld + "
> + "NumOfLba=%d - 1 ) > LastBlock=%ld.\n",
> + Instance->StartLba + StartingLba, NumOfLba,
> + Instance->Media.LastBlock));
> + if ((NumOfLba == 0) ||
> + ((Instance->StartLba + StartingLba + NumOfLba - 1) >
> + Instance->Media.LastBlock)) {
> + VA_END (Args);
> + DEBUG ((DEBUG_ERROR, "%a : Lba range goes past the last Lba\n"));
> + Status = EFI_INVALID_PARAMETER;
> + goto EXIT;
> + }
> + } while (TRUE);
> + VA_END (Args);
> +
> + //
> + // To get here, all must be ok, so start erasing
> + //
> + VA_START (Args, This);
> + do {
> + // Get the Lba from which we start erasing
> + StartingLba = VA_ARG (Args, EFI_LBA);
> +
> + // Have we reached the end of the list?
> + if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
> + // Exit the while loop
> + break;
> + }
> +
> + // How many Lba blocks are we requested to erase?
> + NumOfLba = VA_ARG (Args, UINT32);
> +
> + // Go through each one and erase it
> + while (NumOfLba > 0) {
> + // Get the physical address of Lba to erase
> + BlockAddress = GET_NOR_BLOCK_ADDRESS (
> + Instance->RegionBaseAddress,
> + Instance->StartLba + StartingLba,
> + Instance->Media.BlockSize
> + );
> +
> + // Erase it
> + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Erasing Lba=%ld @ 0x%08x.\n",
> + Instance->StartLba + StartingLba, BlockAddress));
> + Status = NorFlashPlatformEraseSector(Instance, BlockAddress);
> + if (EFI_ERROR (Status)) {
> + VA_END (Args);
> + Status = EFI_DEVICE_ERROR;
> + goto EXIT;
> + }
> +
> + // Move to the next Lba
> + StartingLba++;
> + NumOfLba--;
> + }
> + } while (TRUE);
> + VA_END (Args);
> +
> +EXIT:
> + return Status;
> +}
> +
> +/**
> + Fixup internal data so that EFI can be call in virtual mode.
> + Call the passed in Child Notify event and convert any pointers in
> + lib to virtual mode.
> +
> + @param[in] Event The Event that is being processed
> + @param[in] Context Event Context
> +**/
> +VOID
> +EFIAPI
> +FvbVirtualNotifyEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase);
> + return;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +NorFlashFvbInitialize (
> + IN NOR_FLASH_INSTANCE *Instance
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 FvbNumLba;
> + EFI_BOOT_MODE BootMode;
> + UINTN RuntimeMmioRegionSize;
> +
> + DEBUG ((DEBUG_BLKIO, "NorFlashFvbInitialize\n"));
> +
> + Instance->Initialized = TRUE;
> + mFlashNvStorageVariableBase = FixedPcdGet64 (PcdFlashNvStorageVariableBase64);
> +
> + // Set the index of the first LBA for the FVB
> + Instance->StartLba = (PcdGet64 (PcdFlashNvStorageVariableBase64) - Instance->RegionBaseAddress) / Instance->Media.BlockSize;
> +
> + BootMode = GetBootModeHob ();
> + if (BootMode == BOOT_WITH_DEFAULT_SETTINGS) {
> + Status = EFI_INVALID_PARAMETER;
> + } else {
> + // Determine if there is a valid header at the beginning of the NorFlash
> + Status = ValidateFvHeader (Instance);
> + }
> +
> + // Install the Default FVB header if required
> + if (EFI_ERROR (Status)) {
> + // There is no valid header, so time to install one.
> + DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __FUNCTION__));
> + DEBUG ((DEBUG_INFO, "%a: Installing a correct one for this volume.\n",
> + __FUNCTION__));
> +
> + // Erase all the NorFlash that is reserved for variable storage
> + FvbNumLba = (PcdGet32 (PcdFlashNvStorageVariableSize) +
> + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
> + PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / Instance->Media.BlockSize;
> +
> + Status = FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumLba, EFI_LBA_LIST_TERMINATOR);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + // Install all appropriate headers
> + Status = InitializeFvAndVariableStoreHeaders (Instance);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> + }
> +
> + //
> + // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME
> + //
> +
> + // Note: all the NOR Flash region needs to be reserved into the UEFI Runtime memory;
> + // even if we only use the small block region at the top of the NOR Flash.
> + // The reason is when the NOR Flash memory is set into program mode, the command
> + // is written as the base of the flash region (ie: Instance->DeviceBaseAddress)
> + RuntimeMmioRegionSize = (Instance->RegionBaseAddress - Instance->DeviceBaseAddress) + Instance->Size;
> +
> + Status = gDS->AddMemorySpace (
> + EfiGcdMemoryTypeMemoryMappedIo,
> + Instance->DeviceBaseAddress, RuntimeMmioRegionSize,
> + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = gDS->SetMemorySpaceAttributes (
> + Instance->DeviceBaseAddress, RuntimeMmioRegionSize,
> + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Register for the virtual address change event
> + //
> + Status = gBS->CreateEventEx (
> + EVT_NOTIFY_SIGNAL,
> + TPL_NOTIFY,
> + FvbVirtualNotifyEvent,
> + NULL,
> + &gEfiEventVirtualAddressChangeGuid,
> + &mFvbVirtualAddrChangeEvent
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver
2018-02-16 8:50 ` [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver Meenakshi
@ 2018-04-17 16:36 ` Leif Lindholm
2018-04-23 8:21 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-17 16:36 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
On Fri, Feb 16, 2018 at 02:20:01PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> I2C driver produces gEfiI2cMasterProtocolGuid which can be
> used by other modules.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 726 ++++++++++++++++++++++++++++++++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 65 +++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 55 +++
> 3 files changed, 846 insertions(+)
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
>
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> new file mode 100644
> index 0000000..80a8826
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> @@ -0,0 +1,726 @@
> +/** I2cDxe.c
> + I2c driver APIs for read, write, initialize, set speed and reset
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +
> +#include <Protocol/I2cMaster.h>
> +
> +#include "I2cDxe.h"
> +
> +STATIC CONST UINT16 ClkDiv[60][2] = {
> + { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
> + { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
> + { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
> + { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
> + { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
> + { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
> + { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
> + { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
> + { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
> + { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
> + { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
> + { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 },{ 1280, 0x35 },
> + { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
> + { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
> + { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
> +};
> +
> +/**
> + Calculate and return proper clock divider
> +
> + @param Rate clock rate
> +
> + @retval ClkDiv Value used to get frequency divider value
> +
> +**/
> +STATIC
> +UINT8
> +GetClkDiv (
> + IN UINT32 Rate
> + )
> +{
> + UINTN ClkRate;
> + UINT32 Div;
> + UINT8 ClkDivx;
> +
> + ClkRate = GetBusFrequency ();
> +
> + Div = (ClkRate + Rate - 1) / Rate;
> +
> + if (Div < ClkDiv[0][0]) {
> + ClkDivx = 0;
> + } else if (Div > ClkDiv[ARRAY_SIZE (ClkDiv) - 1][0]){
> + ClkDivx = ARRAY_SIZE (ClkDiv) - 1;
> + } else {
> + for (ClkDivx = 0; ClkDiv[ClkDivx][0] < Div; ClkDivx++);
> + }
> +
> + return ClkDivx;
> +}
> +
> +/**
> + Function used to check if i2c is in mentioned state or not
> +
> + @param I2cRegs Pointer to I2C registers
> + @param State i2c state need to be checked
> +
> + @retval EFI_NOT_READY Arbitration was lost
> + @retval EFI_TIMEOUT Timeout occured
> + @retval CurrState Value of state register
> +
> +**/
> +STATIC
> +EFI_STATUS
> +WaitForI2cState (
> + IN I2C_REGS *I2cRegs,
> + IN UINT32 State
> + )
> +{
> + UINT8 CurrState;
> + UINT64 Cnt;
> +
> + for (Cnt = 0; Cnt < 50000; Cnt++) {
> + MemoryFence ();
> + CurrState = MmioRead8 ((UINTN)&I2cRegs->I2cSr);
> + if (CurrState & I2C_SR_IAL) {
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, CurrState | I2C_SR_IAL);
> + return EFI_NOT_READY;
> + }
> +
> + if ((CurrState & (State >> 8)) == (UINT8)State) {
> + return CurrState;
> + }
> + }
> +
> + return EFI_TIMEOUT;
> +}
> +
> +/**
> + Function to transfer byte on i2c
> +
> + @param I2cRegs Pointer to i2c registers
> + @param Byte Byte to be transferred on i2c bus
> +
> + @retval EFI_NOT_READY Arbitration was lost
> + @retval EFI_TIMEOUT Timeout occured
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Data transfer was succesful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +TransferByte (
> + IN I2C_REGS *I2cRegs,
> + IN UINT8 Byte
> + )
> +{
> + EFI_STATUS Ret;
> +
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> + MmioWrite8 ((UINTN)&I2cRegs->I2cDr, Byte);
> +
> + Ret = WaitForI2cState (I2cRegs, IIF);
> + if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
> + return Ret;
> + }
> +
> + if (Ret & I2C_SR_RX_NO_AK) {
> + return EFI_NOT_FOUND;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to stop transaction on i2c bus
> +
> + @param I2cRegs Pointer to i2c registers
> +
> + @retval EFI_NOT_READY Arbitration was lost
> + @retval EFI_TIMEOUT Timeout occured
> + @retval EFI_SUCCESS Stop operation was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +I2cStop (
> + IN I2C_REGS *I2cRegs
> + )
> +{
> + INT32 Ret;
> + UINT32 Temp;
> +
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> +
> + Temp &= ~(I2C_CR_MSTA | I2C_CR_MTX);
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> +
> + Ret = WaitForI2cState (I2cRegs, BUS_IDLE);
> +
> + if (Ret < 0) {
> + return Ret;
> + } else {
> + return EFI_SUCCESS;
> + }
> +}
> +
> +/**
> + Function to send start signal, Chip Address and
> + memory offset
> +
> + @param I2cRegs Pointer to i2c base registers
> + @param Chip Chip Address
> + @param Offset Slave memory's offset
> + @param Alen length of chip address
> +
> + @retval EFI_NOT_READY Arbitration lost
> + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Read was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +InitTransfer (
> + IN I2C_REGS *I2cRegs,
> + IN UINT8 Chip,
> + IN UINT32 Offset,
> + IN INT32 Alen
> + )
> +{
> + UINT32 Temp;
> + EFI_STATUS Ret;
> +
> + // Enable I2C controller
> + if (MmioRead8 ((UINTN)&I2cRegs->I2cCr) & I2C_CR_IDIS) {
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IEN);
> + }
> +
> + if (MmioRead8 ((UINTN)&I2cRegs->I2cAdr) == (Chip << 1)) {
> + MmioWrite8 ((UINTN)&I2cRegs->I2cAdr, (Chip << 1) ^ 2);
> + }
> +
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> + Ret = WaitForI2cState (I2cRegs, BUS_IDLE);
> + if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
> + return Ret;
> + }
> +
> + // Start I2C transaction
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> + // set to master mode
> + Temp |= I2C_CR_MSTA;
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> +
> + Ret = WaitForI2cState (I2cRegs, BUS_BUSY);
> + if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
> + return Ret;
> + }
> +
> + Temp |= I2C_CR_MTX | I2C_CR_TX_NO_AK;
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> +
> + // write slave Address
> + Ret = TransferByte (I2cRegs, Chip << 1);
> + if (Ret != EFI_SUCCESS) {
> + return Ret;
> + }
> +
> + if (Alen >= 0) {
> + while (Alen--) {
> + Ret = TransferByte (I2cRegs, (Offset >> (Alen * 8)) & 0xff);
> + if (Ret != EFI_SUCCESS)
> + return Ret;
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to check if i2c bus is idle
> +
> + @param Base Pointer to base address of I2c controller
> +
> + @retval EFI_SUCCESS
> +
> +**/
> +STATIC
> +INT32
> +I2cBusIdle (
> + IN VOID *Base
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to initiate data transfer on i2c bus
> +
> + @param I2cRegs Pointer to i2c base registers
> + @param Chip Chip Address
> + @param Offset Slave memory's offset
> + @param Alen length of chip address
> +
> + @retval EFI_NOT_READY Arbitration lost
> + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Read was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +InitDataTransfer (
> + IN I2C_REGS *I2cRegs,
> + IN UINT8 Chip,
> + IN UINT32 Offset,
> + IN INT32 Alen
> + )
> +{
> + EFI_STATUS Status;
> + INT32 Retry;
> +
> + for (Retry = 0; Retry < 3; Retry++) {
> + Status = InitTransfer (I2cRegs, Chip, Offset, Alen);
> + if (Status == EFI_SUCCESS) {
> + return EFI_SUCCESS;
> + }
> +
> + I2cStop (I2cRegs);
> +
> + if (EFI_NOT_FOUND == Status) {
> + return Status;
> + }
> +
> + // Disable controller
> + if (Status != EFI_NOT_READY) {
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
> + }
> +
> + if (I2cBusIdle (I2cRegs) < 0) {
> + break;
> + }
> + }
> + return Status;
> +}
> +
> +/**
> + Function to read data using i2c bus
> +
> + @param I2cBus I2c Controller number
> + @param Chip Address of slave device from where data to be read
> + @param Offset Offset of slave memory
> + @param Alen Address length of slave
> + @param Buffer A pointer to the destination buffer for the data
> + @param Len Length of data to be read
> +
> + @retval EFI_NOT_READY Arbitration lost
> + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Read was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +I2cDataRead (
> + IN UINT32 I2cBus,
> + IN UINT8 Chip,
> + IN UINT32 Offset,
> + IN UINT32 Alen,
> + IN UINT8 *Buffer,
> + IN UINT32 Len
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 Temp;
> + INT32 I;
> + I2C_REGS *I2cRegs;
> +
> + I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
> + (I2cBus * FixedPcdGet32 (PcdI2cSize))));
Please get rid of this hardcoded base address and use NonDiscoverable
Have a look at Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/ and
Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/
for example.
> +
> + Status = InitDataTransfer (I2cRegs, Chip, Offset, Alen);
> + if (Status != EFI_SUCCESS) {
> + return Status;
> + }
> +
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> + Temp |= I2C_CR_RSTA;
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> +
> + Status = TransferByte (I2cRegs, (Chip << 1) | 1);
> + if (Status != EFI_SUCCESS) {
> + I2cStop (I2cRegs);
> + return Status;
> + }
> +
> + // setup bus to read data
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> + Temp &= ~(I2C_CR_MTX | I2C_CR_TX_NO_AK);
> + if (Len == 1) {
> + Temp |= I2C_CR_TX_NO_AK;
> + }
> +
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> +
> + // Dummy Read to initiate recieve operation
> + MmioRead8 ((UINTN)&I2cRegs->I2cDr);
> +
> + for (I = 0; I < Len; I++) {
> + Status = WaitForI2cState (I2cRegs, IIF);
> + if ((Status == EFI_TIMEOUT) || (Status == EFI_NOT_READY)) {
> + I2cStop (I2cRegs);
> + return Status;
> + }
> + //
> + // It must generate STOP before read I2DR to prevent
> + // controller from generating another clock cycle
> + //
> + if (I == (Len - 1)) {
> + I2cStop (I2cRegs);
> + } else if (I == (Len - 2)) {
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> + Temp |= I2C_CR_TX_NO_AK;
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> + }
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> + Buffer[I] = MmioRead8 ((UINTN)&I2cRegs->I2cDr);
> + }
> +
> + I2cStop (I2cRegs);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to write data using i2c bus
> +
> + @param I2cBus I2c Controller number
> + @param Chip Address of slave device where data to be written
> + @param Offset Offset of slave memory
> + @param Alen Address length of slave
> + @param Buffer A pointer to the source buffer for the data
> + @param Len Length of data to be write
> +
> + @retval EFI_NOT_READY Arbitration lost
> + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Read was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +I2cDataWrite (
> + IN UINT32 I2cBus,
> + IN UINT8 Chip,
> + IN UINT32 Offset,
> + IN INT32 Alen,
> + OUT UINT8 *Buffer,
> + IN INT32 Len
> + )
> +{
> + EFI_STATUS Status;
> + I2C_REGS *I2cRegs;
> + INT32 I;
> +
> + I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
> + (I2cBus * FixedPcdGet32 (PcdI2cSize))));
> +
> + Status = InitDataTransfer (I2cRegs, Chip, Offset, Alen);
> + if (Status != EFI_SUCCESS) {
> + return Status;
> + }
> +
> + // Write operation
> + for (I = 0; I < Len; I++) {
> + Status = TransferByte (I2cRegs, Buffer[I]);
> + if (Status != EFI_SUCCESS) {
> + break;
> + }
> + }
> +
> + I2cStop (I2cRegs);
> + return Status;
> +}
> +
> +/**
> + Function to set i2c bus frequency
> +
> + @param This Pointer to I2c master protocol
> + @param BusClockHertz value to be set
> +
> + @retval EFI_SUCCESS Operation successfull
> +**/
> +
> +EFI_STATUS
> +EFIAPI
> +SetBusFrequency (
> + IN CONST EFI_I2C_MASTER_PROTOCOL *This,
> + IN OUT UINTN *BusClockHertz
> + )
> +{
> + I2C_REGS *I2cRegs;
> + UINT8 ClkId;
> + UINT8 SpeedId;
> +
> + I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
> + (PcdGet32 (PcdI2cBus) * FixedPcdGet32 (PcdI2cSize))));
> +
> + ClkId = GetClkDiv (*BusClockHertz);
> + SpeedId = ClkDiv[ClkId][1];
> +
> + // Store divider value
> + MmioWrite8 ((UINTN)&I2cRegs->I2cFdr, SpeedId);
> +
> + MemoryFence ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to reset I2c Controller
> +
> + @param This Pointer to I2c master protocol
> +
> + @return EFI_SUCCESS Operation successfull
> +**/
> +EFI_STATUS
> +EFIAPI
> +Reset (
> + IN CONST EFI_I2C_MASTER_PROTOCOL *This
> + )
> +{
> + I2C_REGS *I2cRegs;
> +
> + I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
> + (PcdGet32 (PcdI2cBus) * FixedPcdGet32 (PcdI2cSize))));
> +
> + // Reset module
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, 0);
> +
> + MemoryFence ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +StartRequest (
> + IN CONST EFI_I2C_MASTER_PROTOCOL *This,
> + IN UINTN SlaveAddress,
> + IN EFI_I2C_REQUEST_PACKET *RequestPacket,
> + IN EFI_EVENT Event OPTIONAL,
> + OUT EFI_STATUS *I2cStatus OPTIONAL
> + )
> +{
> + UINT32 Count;
> + INT32 Ret;
> + UINT32 Length;
> + UINT8 *Buffer;
> + UINT32 Flag;
> + UINT32 RegAddress;
> + UINT32 OffsetLength;
> +
> + RegAddress = 0;
> +
> + if (RequestPacket->OperationCount <= 0) {
> + DEBUG ((DEBUG_ERROR,"%a: Operation count is not valid %d\n",
> + __FUNCTION__, RequestPacket->OperationCount));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + OffsetLength = RequestPacket->Operation[0].LengthInBytes;
> + RegAddress = *RequestPacket->Operation[0].Buffer;
> +
> + for (Count = 1; Count < RequestPacket->OperationCount; Count++) {
> + Flag = RequestPacket->Operation[Count].Flags;
> + Length = RequestPacket->Operation[Count].LengthInBytes;
> + Buffer = RequestPacket->Operation[Count].Buffer;
> +
> + if (Length <= 0) {
> + DEBUG ((DEBUG_ERROR,"%a: Invalid length of buffer %d\n",
> + __FUNCTION__, Length));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if (Flag == I2C_FLAG_READ) {
> + Ret = I2cDataRead (PcdGet32 (PcdI2cBus), SlaveAddress,
> + RegAddress, OffsetLength, Buffer, Length);
> + if (Ret != EFI_SUCCESS) {
> + DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n",
> + __FUNCTION__, Ret));
> + return Ret;
> + }
> + } else if (Flag == I2C_FLAG_WRITE) {
> + Ret = I2cDataWrite (PcdGet32 (PcdI2cBus), SlaveAddress,
> + RegAddress, OffsetLength, Buffer, Length);
> + if (Ret != EFI_SUCCESS) {
> + DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n",
> + __FUNCTION__, Ret));
> + return Ret;
> + }
> + } else {
> + DEBUG ((DEBUG_ERROR,"%a: Invalid Flag %d\n",
> + __FUNCTION__, Flag));
> + return EFI_INVALID_PARAMETER;
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +CONST EFI_I2C_CONTROLLER_CAPABILITIES I2cControllerCapabilities = {
> + 0,
> + 0,
> + 0,
> + 0
> +};
> +
> +STATIC EFI_I2C_MASTER_PROTOCOL gI2c = {
> + ///
> + /// Set the clock frequency for the I2C bus.
> + ///
> + SetBusFrequency,
> + ///
> + /// Reset the I2C host controller.
> + ///
> + Reset,
> + ///
> + /// Start an I2C transaction in master mode on the host controller.
> + ///
> + StartRequest,
> + ///
> + /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure containing
> + /// the capabilities of the I2C host controller.
> + ///
> + &I2cControllerCapabilities
> +};
> +
> +STATIC I2C_DEVICE_PATH gDevicePath = {
> + {
> + {
> + HARDWARE_DEVICE_PATH, HW_VENDOR_DP,
> + {
> + sizeof (VENDOR_DEVICE_PATH), 0
> + }
> + },
> + EFI_CALLER_ID_GUID
> + },
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + sizeof (EFI_DEVICE_PATH_PROTOCOL), 0
> + }
> + }
> +};
> +
> +/**
> + The Entry Point for I2C driver.
> +
> + @param[in] ImageHandle The firmware allocated handle for the EFI image.
> + @param[in] SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The entry point is executed successfully.
> + @retval other Some error occurs when executing this entry point.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +I2cDxeEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> +
> + //
> + // Install I2c Master protocol on this controller
> + //
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &ImageHandle,
Indentation - + 2 spaces.
> + &gEfiI2cMasterProtocolGuid,
> + (VOID**)&gI2c,
> + &gEfiDevicePathProtocolGuid,
> + &gDevicePath,
> + NULL
> + );
> +
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +
> +/**
> + Unload function for the I2c Driver.
> +
> + @param ImageHandle[in] The allocated handle for the EFI image
> +
> + @retval EFI_SUCCESS The driver was unloaded successfully
> + @retval EFI_INVALID_PARAMETER ImageHandle is not a valid image handle.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +I2cDxeUnload (
> + IN EFI_HANDLE ImageHandle
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE *HandleBuffer;
> + UINTN HandleCount;
> + UINTN Index;
> +
> + //
> + // Retrieve all I2c handles in the handle database
> + //
> + Status = gBS->LocateHandleBuffer (ByProtocol,
> + &gEfiI2cMasterProtocolGuid,
> + NULL,
> + &HandleCount,
> + &HandleBuffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Disconnect the driver from the handles in the handle database
> + //
> + for (Index = 0; Index < HandleCount; Index++) {
> + Status = gBS->DisconnectController (HandleBuffer[Index],
> + gImageHandle,
> + NULL);
> + }
> +
> + //
> + // Free the handle array
> + //
> + gBS->FreePool (HandleBuffer);
> +
> + //
> + // Uninstall protocols installed by the driver in its entrypoint
> + //
> + Status = gBS->UninstallMultipleProtocolInterfaces (ImageHandle,
> + &gEfiI2cMasterProtocolGuid, &gI2c,
> + &gEfiDevicePathProtocolGuid, &gDevicePath,
> + NULL);
> +
> + return Status;
> +}
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> new file mode 100644
> index 0000000..4a562d3
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> @@ -0,0 +1,65 @@
> +/** I2cDxe.h
> + Header defining the constant, base address amd function for I2C controller
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __I2C_DXE_H___
Typo in include guard, making it not a guard. (Extra '_'.)
> +#define __I2C_DXE_H__
> +
> +#include <Uefi.h>
> +
> +#define I2C_CR_IIEN (1 << 6)
> +#define I2C_CR_MSTA (1 << 5)
> +#define I2C_CR_MTX (1 << 4)
> +#define I2C_CR_TX_NO_AK (1 << 3)
> +#define I2C_CR_RSTA (1 << 2)
> +
> +#define I2C_SR_ICF (1 << 7)
> +#define I2C_SR_IBB (1 << 5)
> +#define I2C_SR_IAL (1 << 4)
> +#define I2C_SR_IIF (1 << 1)
> +#define I2C_SR_RX_NO_AK (1 << 0)
> +
> +#define I2C_CR_IEN (0 << 7)
> +#define I2C_CR_IDIS (1 << 7)
> +#define I2C_SR_IIF_CLEAR (1 << 1)
> +
> +#define BUS_IDLE (0 | (I2C_SR_IBB << 8))
> +#define BUS_BUSY (I2C_SR_IBB | (I2C_SR_IBB << 8))
> +#define IIF (I2C_SR_IIF | (I2C_SR_IIF << 8))
> +
> +#define I2C_FLAG_WRITE 0x0
> +
> +typedef struct {
> + VENDOR_DEVICE_PATH Guid;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} I2C_DEVICE_PATH;
> +
> +/**
> + Record defining i2c registers
> +**/
> +typedef struct {
> + UINT8 I2cAdr;
> + UINT8 I2cFdr;
> + UINT8 I2cCr;
> + UINT8 I2cSr;
> + UINT8 I2cDr;
> +} I2C_REGS ;
> +
> +extern
> +UINT64
> +GetBusFrequency (
> + VOID
> + );
> +
> +#endif
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> new file mode 100644
> index 0000000..ceb1b11
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> @@ -0,0 +1,55 @@
> +# @file
> +#
> +# Component description file for I2c driver
> +#
> +# Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = I2cDxe
> + FILE_GUID = 5f2927ba-1b04-4d5f-8bef-2b50c635d1e7
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = I2cDxeEntryPoint
> + UNLOAD = I2cDxeUnload
> +
> +[Sources.common]
> + I2cDxe.c
> +
> +[LibraryClasses]
> + ArmLib
> + IoLib
> + MemoryAllocationLib
> + PcdLib
> + SocLib
> + TimerLib
> + UefiDriverEntryPoint
> + UefiLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[Protocols]
> + gEfiI2cMasterProtocolGuid
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
> +
> +[Depex]
> + TRUE
Migrating to NonDiscoverableDeviceRegistrationLib should also let you
get rid of this hardcoded depex.
/
Leif
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (38 preceding siblings ...)
2018-02-16 8:50 ` [PATCH edk2-platforms 39/39] Platform/NXP:PCIe enablement for LS2088A RDB Meenakshi
@ 2018-04-17 16:44 ` Leif Lindholm
2018-04-20 16:15 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
41 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-17 16:44 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
Could you please integrate the below changes in whichever commits they
belong individually?
- Clarifications (via file name changes) of which .dsc files are meant
as include files rather than standalone platform descriptions.
- Getting rid of relative paths to locate said include files.
(No, I don't need copyright or attribution, it's just a more
structured way to provide this particular bit of feedback.)
/
Leif
>From 7da6ca87177153532811f8ecd9ad6847b480161e Mon Sep 17 00:00:00 2001
From: Leif Lindholm <leif.lindholm@linaro.org>
Date: Tue, 17 Apr 2018 16:22:00 +0100
Subject: [PATCH edk2-platforms] {Platform|Silicon}/NXP: Build config includes
cleanup
---
Platform/NXP/{NxpQoriqLs.dsc => NxpQoriqLs.dsc.inc} | 0
Silicon/NXP/LS1043A/{LS1043A.dsc => LS1043A.dsc.inc} | 0
Silicon/NXP/LS1046A/{LS1046A.dsc => LS1046A.dsc.inc} | 0
Silicon/NXP/LS2088A/{LS2088A.dsc => LS2088A.dsc.inc} | 0
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 4 ++--
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 4 ++--
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 4 ++--
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 2 +-
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 2 +-
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 2 +-
10 files changed, 9 insertions(+), 9 deletions(-)
rename Platform/NXP/{NxpQoriqLs.dsc => NxpQoriqLs.dsc.inc} (100%)
rename Silicon/NXP/LS1043A/{LS1043A.dsc => LS1043A.dsc.inc} (100%)
rename Silicon/NXP/LS1046A/{LS1046A.dsc => LS1046A.dsc.inc} (100%)
rename Silicon/NXP/LS2088A/{LS2088A.dsc => LS2088A.dsc.inc} (100%)
diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc.inc
similarity index 100%
rename from Platform/NXP/NxpQoriqLs.dsc
rename to Platform/NXP/NxpQoriqLs.dsc.inc
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
similarity index 100%
rename from Silicon/NXP/LS1043A/LS1043A.dsc
rename to Silicon/NXP/LS1043A/LS1043A.dsc.inc
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
similarity index 100%
rename from Silicon/NXP/LS1046A/LS1046A.dsc
rename to Silicon/NXP/LS1046A/LS1046A.dsc.inc
diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
similarity index 100%
rename from Silicon/NXP/LS2088A/LS2088A.dsc
rename to Silicon/NXP/LS2088A/LS2088A.dsc.inc
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 8cbaf8829c..e75672cd0c 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -28,8 +28,8 @@ [Defines]
OUTPUT_DIRECTORY = Build/LS1043aRdbPkg
FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
-!include ../NxpQoriqLs.dsc
-!include ../../../Silicon/NXP/LS1043A/LS1043A.dsc
+!include Platform/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
[LibraryClasses.common]
ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
index 231207d7ca..93a01a770f 100644
--- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
@@ -28,8 +28,8 @@ [Defines]
OUTPUT_DIRECTORY = Build/LS1046aRdbPkg
FLASH_DEFINITION = Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
-!include ../NxpQoriqLs.dsc
-!include ../../../Silicon/NXP/LS1046A/LS1046A.dsc
+!include Platform/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS1046A/LS1046A.dsc.inc
[LibraryClasses.common]
ArmPlatformLib|Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
index 1ae55d4584..7605ea50f8 100755
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -29,8 +29,8 @@ [Defines]
FLASH_DEFINITION = Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
DEFINE MC_HIGH_MEM = TRUE
-!include ../NxpQoriqLs.dsc
-!include ../../../Silicon/NXP/LS2088A/LS2088A.dsc
+!include Platform/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS2088A/LS2088A.dsc.inc
[LibraryClasses.common]
ArmPlatformLib|Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 7993bf170a..c88bbe1475 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -54,7 +54,7 @@ [FD.LS1043ARDB_EFI]
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
-!include ../FVRules.fdf.inc
+!include Platform/NXP/FVRules.fdf.inc
!include VarStore.fdf.inc
################################################################################
#
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
index 3351a062e9..8ae0ada5b2 100644
--- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
@@ -54,7 +54,7 @@ [FD.LS1046ARDB_EFI]
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
-!include ../FVRules.fdf.inc
+!include Platform/NXP/FVRules.fdf.inc
################################################################################
#
# FV Section
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
index 35a79bda6f..93760df409 100644
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
@@ -54,7 +54,7 @@ [FD.LS2088aRdb_EFI]
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
-!include ../FVRules.fdf.inc
+!include Platform/NXP/FVRules.fdf.inc
!include VarStore.fdf.inc
################################################################################
#
--
2.11.0
^ permalink raw reply related [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 03/39] SocLib : Add support for initialization of peripherals
2018-02-16 8:49 ` [PATCH edk2-platforms 03/39] SocLib : Add support for initialization of peripherals Meenakshi
@ 2018-04-18 15:12 ` Leif Lindholm
2018-04-18 16:38 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-18 15:12 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
On Fri, Feb 16, 2018 at 02:19:59PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> Add SocInit function that initializes peripherals
> and print board and soc information.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Chassis/Chassis.c | 388 ++++++++++++++++++++++++++++++
> Silicon/NXP/Chassis/Chassis.h | 144 +++++++++++
> Silicon/NXP/Chassis/Chassis2/Chassis2.dec | 19 ++
> Silicon/NXP/Chassis/Chassis2/SerDes.h | 68 ++++++
> Silicon/NXP/Chassis/Chassis2/Soc.c | 172 +++++++++++++
> Silicon/NXP/Chassis/Chassis2/Soc.h | 367 ++++++++++++++++++++++++++++
> Silicon/NXP/Chassis/LS1043aSocLib.inf | 47 ++++
> Silicon/NXP/Chassis/SerDes.c | 271 +++++++++++++++++++++
> Silicon/NXP/Include/Bitops.h | 179 ++++++++++++++
> Silicon/NXP/LS1043A/Include/SocSerDes.h | 55 +++++
> 10 files changed, 1710 insertions(+)
> create mode 100644 Silicon/NXP/Chassis/Chassis.c
> create mode 100644 Silicon/NXP/Chassis/Chassis.h
> create mode 100644 Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> create mode 100644 Silicon/NXP/Chassis/Chassis2/SerDes.h
> create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.c
> create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.h
> create mode 100644 Silicon/NXP/Chassis/LS1043aSocLib.inf
> create mode 100644 Silicon/NXP/Chassis/SerDes.c
> create mode 100644 Silicon/NXP/Include/Bitops.h
> create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
>
> diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c
> new file mode 100644
> index 0000000..9f2928b
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/Chassis.c
> @@ -0,0 +1,388 @@
> +/** @file
> + SoC specific Library containg functions to initialize various SoC components
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BeIoLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +#include <Soc.h>
> +
> +#include "Chassis.h"
> +
> +UINT32
> +EFIAPI
> +GurRead (
> + IN UINTN Address
> + )
> +{
> + if (FixedPcdGetBool (PcdGurBigEndian)) {
> + return BeMmioRead32 (Address);
> + } else {
> + return MmioRead32 (Address);
> + }
> +}
So, since this pattern is being repeated in multiple modules, I think
it would make sense to have (for now) an NXP-specific helper library
to return a struct of function pointers accessing either
I.e. something like (in a header)
typedef struct _MMIO_OPERATIONS {
MMIO_WRITE_8 Write8;
...
} MMIO_OPERATIONS;
and then in the .c file:
STATIC MMIO_OPERATIONS SwappingFunctions = {
SwapMmioWrite8,
...
};
STATIC MMIO_OPERATIONS NonSwappingFunctions = {
MmioWrite8,
...
};
MMIO_OPERATIONS *GetMmioOperationsStructure (BOOL BigEndian)
{
if (BigEndian) {
return &SwappingFunctions;
else {
return &NonSwappingFunctions;
}
}
To be used in _this_ file as
STATIC MMIO_OPERATIONS mGurOps;
Initialized in some sort of Initialize() function as
mGurOps = GetMmioOperationsStructure (FixedPcdGetBool (PcdGurBigEndian));
This will then let us fix up whatever the final core function names
end up being in a single place.
This feedback applies also to the resubmitted watchdog driver (but
should be a very minor change there).
> +
> +/*
> + * Structure to list available SOCs.
> + */
> +STATIC CPU_TYPE CpuTypeList[] = {
> + CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
> +};
> +
> +/*
> + * Return the number of bits set
> + */
> +STATIC
> +inline
> +UINTN
> +CountSetBits (
This helper function is only used in one location.
If there is enough in this set to break out into a generically useful
helper library (for later consideration for inclusion in edk2 for
example), please do so. Otherwise, please move this inline in the
(otherwise near-empty) calling function.
> + IN UINTN Num
> + )
> +{
> + UINTN Count;
> +
> + Count = 0;
> +
> + while (Num) {
> + Count += Num & 1;
> + Num >>= 1;
> + }
> +
> + return Count;
> +}
> +
> +/*
> + * Return the type of initiator (core or hardware accelerator)
> + */
> +UINT32
> +InitiatorType (
> + IN UINT32 Cluster,
> + IN UINTN InitId
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINT32 Idx;
> + UINT32 Type;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
> + Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
> +
> + if (Type & TP_ITYP_AV_MASK) {
> + return Type;
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * Return the mask for number of cores on this SOC.
> + */
> +UINT32
> +CpuMask (
> + VOID
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINTN ClusterIndex;
> + UINTN Count;
> + UINT32 Cluster;
> + UINT32 Type;
> + UINT32 Mask;
> + UINTN InitiatorIndex;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClusterIndex = 0;
> + Count = 0;
> + Mask = 0;
> +
> + do {
> + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> + Type = InitiatorType (Cluster, InitiatorIndex);
> + if (Type) {
> + if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM)
> + Mask |= 1 << Count;
Always use braces {} with if.
> + Count++;
> + }
> + }
> + ClusterIndex++;
> + } while (CHECK_CLUSTER (Cluster));
> +
> + return Mask;
> +}
> +
> +/*
> + * Return the number of cores on this SOC.
> + */
> +UINTN
> +CpuNumCores (
> + VOID
> + )
> +{
> + return CountSetBits (CpuMask ());
Spurious indentation. (Should be 2 spaces.)
> +}
> +
> +/*
> + * Return the type of core i.e. A53, A57 etc of inputted
> + * core number.
> + */
> +UINT32
> +QoriqCoreToType (
> + IN UINTN Core
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINTN ClusterIndex;
> + UINTN Count;
> + UINT32 Cluster;
> + UINT32 Type;
> + UINTN InitiatorIndex;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClusterIndex = 0;
> + Count = 0;
> +
> + do {
> + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> + Type = InitiatorType (Cluster, InitiatorIndex);
> + if (Type) {
> + if (Count == Core)
> + return Type;
Always braces with if.
> + Count++;
> + }
> + }
> + ClusterIndex++;
> + } while (CHECK_CLUSTER (Cluster));
> +
> + return -1; /* cannot identify the cluster */
Please use a #define for return value.
> +}
> +
> +/*
> + * Print CPU information
> + */
> +VOID
> +PrintCpuInfo (
> + VOID
> + )
> +{
> + SYS_INFO SysInfo;
> + UINTN CoreIndex;
> + UINTN Core;
> + UINT32 Type;
> + CHAR8 Buffer[100];
> + UINTN CharCount;
> +
> + GetSysInfo (&SysInfo);
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Clock Configuration:");
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
Why SerialPortWrite instead of Print? (Question for throughout patch.)
> +
> + ForEachCpu (CoreIndex, Core, CpuNumCores (), CpuMask ()) {
> + if (!(CoreIndex % 3)) {
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n ");
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> + }
> +
> + Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "CPU%d(%a):%-4d MHz ", Core,
> + Type == TY_ITYP_VERSION_A7 ? "A7 " :
> + (Type == TY_ITYP_VERSION_A53 ? "A53" :
> + (Type == TY_ITYP_VERSION_A57 ? "A57" :
> + (Type == TY_ITYP_VERSION_A72 ? "A72" : " Unknown Core "))),
That's a lot more nested than I like my ternaries.
Can you rewrite as a switch statement that sets a pointer.
> + SysInfo.FreqProcessor[Core] / MEGA_HZ);
Please use either MEGAHERTZ or MHZ.
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> + }
> +
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n Bus: %-4d MHz ",
> + SysInfo.FreqSystemBus / MEGA_HZ);
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "DDR: %-4d MT/s",
> + SysInfo.FreqDdrBus / MEGA_HZ);
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> +
> + if (SysInfo.FreqFman[0] != 0) {
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n FMAN: %-4d MHz ",
> + SysInfo.FreqFman[0] / MEGA_HZ);
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> + }
> +
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n");
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> +}
> +
> +/*
> + * Return system bus frequency
> + */
> +UINT64
> +GetBusFrequency (
> + VOID
> + )
> +{
> + SYS_INFO SocSysInfo;
> +
> + GetSysInfo (&SocSysInfo);
> +
> + return SocSysInfo.FreqSystemBus;
> +}
> +
> +/*
> + * Return SDXC bus frequency
> + */
> +UINT64
> +GetSdxcFrequency (
> + VOID
> + )
> +{
> + SYS_INFO SocSysInfo;
> +
> + GetSysInfo (&SocSysInfo);
> +
> + return SocSysInfo.FreqSdhc;
> +}
> +
> +/*
> + * Print Soc information
> + */
> +VOID
> +PrintSoc (
> + VOID
> + )
> +{
> + CHAR8 Buf[16];
> + CCSR_GUR *GurBase;
> + UINTN Count;
> + UINTN Svr;
> + UINTN Ver;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> +
> + Buf[0] = L'\0';
> + Svr = GurRead ((UINTN)&GurBase->Svr);
> + Ver = SVR_SOC_VER (Svr);
> +
> + for (Count = 0; Count < ARRAY_SIZE (CpuTypeList); Count++)
> + if ((CpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
> + AsciiStrCpy (Buf, (CONST CHAR8 *)CpuTypeList[Count].Name);
> +
> + if (IS_E_PROCESSOR (Svr)) {
> + AsciiStrCat (Buf, (CONST CHAR8 *)"E");
> + }
> + break;
> + }
> +
> + if (Count == ARRAY_SIZE (CpuTypeList)) {
> + AsciiStrCpy (Buf, (CONST CHAR8 *)"unknown");
> + }
> +
> + DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
> + Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
> +
> + return;
> +}
> +
> +/*
> + * Dump RCW (Reset Control Word) on console
> + */
> +VOID
> +PrintRCW (
> + VOID
> + )
> +{
> + CCSR_GUR *Base;
> + UINTN Count;
> + CHAR8 Buffer[100];
> + UINTN CharCount;
> +
> + Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> +
> + /*
> + * Display the RCW, so that no one gets confused as to what RCW
> + * we're actually using for this boot.
> + */
> +
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer),
> + "Reset Configuration Word (RCW):");
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> + for (Count = 0; Count < ARRAY_SIZE(Base->RcwSr); Count++) {
> + UINT32 Rcw = BeMmioRead32((UINTN)&Base->RcwSr[Count]);
> +
> + if ((Count % 4) == 0) {
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer),
> + "\n %08x:", Count * 4);
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> + }
> +
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), " %08x", Rcw);
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> + }
> +
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n");
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> +}
> +
> +/*
> + * Setup SMMU in bypass mode
> + * and also set its pagesize
> + */
> +VOID
> +SmmuInit (
> + VOID
> + )
> +{
> + UINT32 Value;
> +
> + /* set pagesize as 64K and ssmu-500 in bypass mode */
> + Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> +
> + Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> +
> + Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> +}
> +
> +/*
> + * Return current Soc Name form CpuTypeList
> + */
> +CHAR8 *
> +GetSocName (
> + VOID
> + )
> +{
> + UINT8 Count;
> + UINTN Svr;
> + UINTN Ver;
> + CCSR_GUR *GurBase;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> +
> + Svr = GurRead ((UINTN)&GurBase->Svr);
> + Ver = SVR_SOC_VER (Svr);
> +
> + for (Count = 0; Count < ARRAY_SIZE (CpuTypeList); Count++) {
> + if ((CpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
> + return (CHAR8 *)CpuTypeList[Count].Name;
> + }
> + }
> +
> + return NULL;
> +}
> diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h
> new file mode 100644
> index 0000000..4bdb4d0
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/Chassis.h
> @@ -0,0 +1,144 @@
> +/** @file
> +* Header defining the Base addresses, sizes, flags etc for chassis 1
> +*
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __CHASSIS_H__
> +#define __CHASSIS_H__
> +
> +#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
> +#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
> +#define TP_ITYP_TYPE_ARM 0x0
> +#define TP_ITYP_TYPE_PPC 0x1
> +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
> +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
> +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
> +#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
> +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
> +#define TP_INIT_PER_CLUSTER 4
> +
> +#define TY_ITYP_VERSION_A7 0x1
> +#define TY_ITYP_VERSION_A53 0x2
> +#define TY_ITYP_VERSION_A57 0x3
> +#define TY_ITYP_VERSION_A72 0x4
> +
> +STATIC
> +inline
> +UINTN
> +CpuMaskNext (
> + IN UINTN Cpu,
> + IN UINTN Mask
> + )
> +{
> + for (Cpu++; !((1 << Cpu) & Mask); Cpu++)
> + ;
> +
> + return Cpu;
> +}
> +
> +#define ForEachCpu(Iter, Cpu, NumCpus, Mask) \
> + for (Iter = 0, Cpu = CpuMaskNext(-1, Mask); \
> + Iter < NumCpus; \
> + Iter++, Cpu = CpuMaskNext(Cpu, Mask)) \
> +
> +#define CPU_TYPE_ENTRY(N, V, NC) \
> + { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
> +
> +#define SVR_WO_E 0xFFFFFE
> +#define SVR_LS1043A 0x879200
> +
> +#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> +#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
> +#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
> +
> +#define MEGA_HZ 1000000
> +
> +typedef struct {
> + CHAR8 Name[16];
> + UINT32 SocVer;
> + UINT32 NumCores;
> +} CPU_TYPE;
> +
> +typedef struct {
> + UINTN CpuClk; /* CPU clock in Hz! */
> + UINTN BusClk;
> + UINTN MemClk;
> + UINTN PciClk;
> + UINTN SdhcClk;
> +} SOC_CLOCK_INFO;
> +
> +/*
> + * Print Soc information
> + */
> +VOID
> +PrintSoc (
> + VOID
> + );
> +
> +/*
> + * Initialize Clock structure
> + */
> +VOID
> +ClockInit (
> + VOID
> + );
> +
> +/*
> + * Setup SMMU in bypass mode
> + * and also set its pagesize
> + */
> +VOID
> +SmmuInit (
> + VOID
> + );
> +
> +/*
> + * Print CPU information
> + */
> +VOID
> +PrintCpuInfo (
> + VOID
> + );
> +
> +/*
> + * Dump RCW (Reset Control Word) on console
> + */
> +VOID
> +PrintRCW (
> + VOID
> + );
> +
> +UINT32
> +InitiatorType (
> + IN UINT32 Cluster,
> + IN UINTN InitId
> + );
> +
> +/*
> + * Return the mask for number of cores on this SOC.
> + */
> +UINT32
> +CpuMask (
> + VOID
> + );
> +
> +/*
> + * Return the number of cores on this SOC.
> + */
> +UINTN
> +CpuNumCores (
> + VOID
> + );
> +
> +#endif /* __CHASSIS_H__ */
> diff --git a/Silicon/NXP/Chassis/Chassis2/Chassis2.dec b/Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> new file mode 100644
> index 0000000..cf41b3c
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> @@ -0,0 +1,19 @@
> +# @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x00010005
0x0001001a
> +
> +[Includes]
> + .
Hmm. In general, this appears to be using the .dec file simply to
tweak which "Soc.h" and "SerDes.h" file gets included in
Silicon/NXP/Chassis/Chassis.c and Silicon/NXP/Chassis/SerDes.c
First of all, a .dec is a package declaration file, and that is not
what is being created here. So this doesn't follow expected TianoCore
layout.
Secondly, there appears to be some quite spurious differences between
Chassis2/Soc.h and Chassis3/Soc.h: difference in indentation,
differences in comment style, use of macros for array sizes in struct
definitions in one and hardcoded in the other.
Can this be cleaned up so that a
diff -u Silicon/NXP/Chassis/Chassis2/Soc.h Silicon/NXP/Chassis/Chassis3/Soc.h
describes the differences between the platforms rather than the
differences in coding style?
Finally, can Silicon/NXP/Chassis be moved across to
Silicon/NXP/Library/SocLib, with include files under
Silicon/NXP/Include/{Chassis2|Chassis3}?
The different .inf files can then set a -D CHASSIS_MODEL=Chassis2 or
-D CHASSIS_MODEL=Chassis3 in GCC:*_*_*_CC_FLAGS [BuildOptions]
with affected source files referring to them as
#include <Library/CHASSIS_MODEL/Soc.h>
and
#include <Library/CHASSIS_MODEL/SerDes.h>
?
> diff --git a/Silicon/NXP/Chassis/Chassis2/SerDes.h b/Silicon/NXP/Chassis/Chassis2/SerDes.h
> new file mode 100644
> index 0000000..4c874aa
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/Chassis2/SerDes.h
> @@ -0,0 +1,68 @@
> +/** SerDes.h
> + The Header file of SerDes Module for Chassis 2
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __SERDES_H__
> +#define __SERDES_H__
> +
> +#include <Uefi/UefiBaseType.h>
> +
> +#define SRDS_MAX_LANES 4
> +
> +typedef enum {
> + NONE = 0,
> + PCIE1,
> + PCIE2,
> + PCIE3,
> + SATA,
> + SGMII_FM1_DTSEC1,
> + SGMII_FM1_DTSEC2,
> + SGMII_FM1_DTSEC5,
> + SGMII_FM1_DTSEC6,
> + SGMII_FM1_DTSEC9,
> + SGMII_FM1_DTSEC10,
> + QSGMII_FM1_A,
> + XFI_FM1_MAC9,
> + XFI_FM1_MAC10,
> + SGMII_2500_FM1_DTSEC2,
> + SGMII_2500_FM1_DTSEC5,
> + SGMII_2500_FM1_DTSEC9,
> + SGMII_2500_FM1_DTSEC10,
> + SERDES_PRTCL_COUNT
> +} SERDES_PROTOCOL;
> +
> +typedef enum {
> + SRDS_1 = 0,
> + SRDS_2,
> + SRDS_MAX_NUM
> +} SERDES_NUMBER;
> +
> +typedef struct {
> + UINT16 Protocol;
> + UINT8 SrdsLane[SRDS_MAX_LANES];
> +} SERDES_CONFIG;
> +
> +typedef VOID
> +(*SERDES_PROBE_LANES_CALLBACK) (
> + IN SERDES_PROTOCOL LaneProtocol,
> + IN VOID *Arg
> + );
> +
> +VOID
> +SerDesProbeLanes(
> + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> + IN VOID *Arg
> + );
> +
> +#endif /* __SERDES_H */
> diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chassis2/Soc.c
> new file mode 100644
> index 0000000..7f9f963
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/Chassis2/Soc.c
> @@ -0,0 +1,172 @@
> +/** @Soc.c
> + SoC specific Library containg functions to initialize various SoC components
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Chassis.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib/MemLibInternals.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +#include "Soc.h"
> +
> +/**
> + Calculate the frequency of various controllers and
> + populate the passed structure with frequuencies.
> +
> + @param PtrSysInfo Input structure to populate with
> + frequencies.
> +**/
> +VOID
> +GetSysInfo (
> + OUT SYS_INFO *PtrSysInfo
> + )
> +{
> + CCSR_GUR *GurBase;
> + CCSR_CLOCK *ClkBase;
> + UINTN CpuIndex;
> + UINT32 TempRcw;
> + UINT32 CPllSel;
> + UINT32 CplxPll;
> + CONST UINT8 CoreCplxPll[8] = {
> + [0] = 0, /* CC1 PPL / 1 */
> + [1] = 0, /* CC1 PPL / 2 */
> + [4] = 1, /* CC2 PPL / 1 */
> + [5] = 1, /* CC2 PPL / 2 */
> + };
> +
> + CONST UINT8 CoreCplxPllDivisor[8] = {
> + [0] = 1, /* CC1 PPL / 1 */
> + [1] = 2, /* CC1 PPL / 2 */
> + [4] = 1, /* CC2 PPL / 1 */
> + [5] = 2, /* CC2 PPL / 2 */
> + };
> +
> + UINTN PllCount;
> + UINTN FreqCPll[NUM_CC_PLLS];
> + UINTN PllRatio[NUM_CC_PLLS];
> + UINTN SysClk;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
> + SysClk = CLK_FREQ;
> +
> + SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> +
> + PtrSysInfo->FreqSystemBus = SysClk;
> + PtrSysInfo->FreqDdrBus = SysClk;
> +
> + //
> + // selects the platform clock:SYSCLK ratio and calculate
> + // system frequency
> + //
> + PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> + CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> + CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> + //
> + // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
> + //
> + PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> + CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
> + CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
> +
> + for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
> + PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
> + if (PllRatio[PllCount] > 4) {
> + FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
> + } else {
> + FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
> + }
> + }
> +
> + //
> + // Calculate Core frequency
> + //
> + for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
> + CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) & 0xf;
> + CplxPll = CoreCplxPll[CPllSel];
> +
> + PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
> + }
> +
> + //
> + // Calculate FMAN frequency
> + //
> + TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
> + switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
> + case 2:
> + PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
> + break;
> + case 3:
> + PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
> + break;
> + case 4:
> + PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
> + break;
> + case 5:
> + PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
> + break;
> + case 6:
> + PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
> + break;
> + case 7:
> + PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
> + break;
> + default:
> + DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
> + break;
> + }
> + PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
> + PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
> +}
> +
> +/**
> + Function to initialize SoC specific constructs
> + CPU Info
> + SoC Personality
> + Board Personality
> + RCW prints
> + **/
> +VOID
> +SocInit (
> + VOID
> + )
> +{
> + CHAR8 Buffer[100];
> + UINTN CharCount;
> +
> + SmmuInit ();
> +
> + //
> + // Early init serial Port to get board information.
> + //
> + SerialPortInitialize ();
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\nUEFI firmware (version %s built at %a on %a)\n\r",
> + (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__);
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> +
> + PrintCpuInfo ();
> +
> + //
> + // Print Reset control Word
> + //
> + PrintRCW ();
> + PrintSoc ();
> +
> + return;
> +}
> diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.h b/Silicon/NXP/Chassis/Chassis2/Soc.h
> new file mode 100644
> index 0000000..10e99ab
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/Chassis2/Soc.h
> @@ -0,0 +1,367 @@
> +/** Soc.h
> +* Header defining the Base addresses, sizes, flags etc for chassis 1
> +*
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __SOC_H__
> +#define __SOC_H__
> +
> +#define HWA_CGA_M1_CLK_SEL 0xe0000000
> +#define HWA_CGA_M1_CLK_SHIFT 29
> +
> +#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
> +#define NUM_CC_PLLS 2
> +#define CLK_FREQ 100000000
> +#define MAX_CPUS 4
> +#define NUM_FMAN 1
> +#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
> +
> +/* RCW SERDES MACRO */
> +#define RCWSR_INDEX 4
> +#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
> +#define RCWSR_SRDS1_PRTCL_SHIFT 16
> +#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
> +#define RCWSR_SRDS2_PRTCL_SHIFT 0
> +
> +/* SMMU Defintions */
> +#define SMMU_BASE_ADDR 0x09000000
> +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> +
> +#define SCR0_USFCFG_MASK 0x00000400
> +#define SCR0_CLIENTPD_MASK 0x00000001
> +#define SACR_PAGESIZE_MASK 0x00010000
> +#define IDR1_PAGESIZE_MASK 0x80000000
> +
> +typedef struct {
> + UINTN FreqProcessor[MAX_CPUS];
> + UINTN FreqSystemBus;
> + UINTN FreqDdrBus;
> + UINTN FreqLocalBus;
> + UINTN FreqSdhc;
> + UINTN FreqFman[NUM_FMAN];
> + UINTN FreqQman;
> +} SYS_INFO;
> +
> +/* Device Configuration and Pin Control */
> +typedef struct {
> + UINT32 PorSr1; /* POR status 1 */
> +#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
> + UINT32 PorSr2; /* POR status 2 */
> + UINT8 Res008[0x20-0x8];
> + UINT32 GppOrCr1; /* General-purpose POR configuration */
> + UINT32 GppOrCr2;
> + UINT32 DcfgFuseSr; /* Fuse status register */
> + UINT8 Res02c[0x70-0x2c];
> + UINT32 DevDisr; /* Device disable control */
> + UINT32 DevDisr2; /* Device disable control 2 */
> + UINT32 DevDisr3; /* Device disable control 3 */
> + UINT32 DevDisr4; /* Device disable control 4 */
> + UINT32 DevDisr5; /* Device disable control 5 */
> + UINT32 DevDisr6; /* Device disable control 6 */
> + UINT32 DevDisr7; /* Device disable control 7 */
> + UINT8 Res08c[0x94-0x8c];
> + UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
> + UINT32 CoreDisrL; /* lower portion for support of 64 cores */
> + UINT8 Res09c[0xa0-0x9c];
> + UINT32 Pvr; /* Processor version */
> + UINT32 Svr; /* System version */
> + UINT32 Mvr; /* Manufacturing version */
> + UINT8 Res0ac[0xb0-0xac];
> + UINT32 RstCr; /* Reset control */
> + UINT32 RstRqPblSr; /* Reset request preboot loader status */
> + UINT8 Res0b8[0xc0-0xb8];
> + UINT32 RstRqMr1; /* Reset request mask */
> + UINT8 Res0c4[0xc8-0xc4];
> + UINT32 RstRqSr1; /* Reset request status */
> + UINT8 Res0cc[0xd4-0xcc];
> + UINT32 RstRqWdTmrL; /* Reset request WDT mask */
> + UINT8 Res0d8[0xdc-0xd8];
> + UINT32 RstRqWdtSrL; /* Reset request WDT status */
> + UINT8 Res0e0[0xe4-0xe0];
> + UINT32 BrrL; /* Boot release */
> + UINT8 Res0e8[0x100-0xe8];
> + UINT32 RcwSr[16]; /* Reset control word status */
> +#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
> +#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
> +#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
> +#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
> + UINT8 Res140[0x200-0x140];
> + UINT32 ScratchRw[4]; /* Scratch Read/Write */
> + UINT8 Res210[0x300-0x210];
> + UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
> + UINT8 Res310[0x400-0x310];
> + UINT32 CrstSr[12];
> + UINT8 Res430[0x500-0x430];
> + /* PCI Express n Logical I/O Device Number register */
> + UINT32 DcfgCcsrPex1LiodNr;
> + UINT32 DcfgCcsrPex2LiodNr;
> + UINT32 DcfgCcsrPex3LiodNr;
> + UINT32 DcfgCcsrPex4LiodNr;
> + /* RIO n Logical I/O Device Number register */
> + UINT32 DcfgCcsrRio1LiodNr;
> + UINT32 DcfgCcsrRio2LiodNr;
> + UINT32 DcfgCcsrRio3LiodNr;
> + UINT32 DcfgCcsrRio4LiodNr;
> + /* USB Logical I/O Device Number register */
> + UINT32 DcfgCcsrUsb1LiodNr;
> + UINT32 DcfgCcsrUsb2LiodNr;
> + UINT32 DcfgCcsrUsb3LiodNr;
> + UINT32 DcfgCcsrUsb4LiodNr;
> + /* SD/MMC Logical I/O Device Number register */
> + UINT32 DcfgCcsrSdMmc1LiodNr;
> + UINT32 DcfgCcsrSdMmc2LiodNr;
> + UINT32 DcfgCcsrSdMmc3LiodNr;
> + UINT32 DcfgCcsrSdMmc4LiodNr;
> + /* RIO Message Unit Logical I/O Device Number register */
> + UINT32 DcfgCcsrRiomaintLiodNr;
> + UINT8 Res544[0x550-0x544];
> + UINT32 SataLiodNr[4];
> + UINT8 Res560[0x570-0x560];
> + UINT32 DcfgCcsrMisc1LiodNr;
> + UINT32 DcfgCcsrMisc2LiodNr;
> + UINT32 DcfgCcsrMisc3LiodNr;
> + UINT32 DcfgCcsrMisc4LiodNr;
> + UINT32 DcfgCcsrDma1LiodNr;
> + UINT32 DcfgCcsrDma2LiodNr;
> + UINT32 DcfgCcsrDma3LiodNr;
> + UINT32 DcfgCcsrDma4LiodNr;
> + UINT32 DcfgCcsrSpare1LiodNr;
> + UINT32 DcfgCcsrSpare2LiodNr;
> + UINT32 DcfgCcsrSpare3LiodNr;
> + UINT32 DcfgCcsrSpare4LiodNr;
> + UINT8 Res5a0[0x600-0x5a0];
> + UINT32 DcfgCcsrPblSr;
> + UINT32 PamuBypENr;
> + UINT32 DmaCr1;
> + UINT8 Res60c[0x610-0x60c];
> + UINT32 DcfgCcsrGenSr1;
> + UINT32 DcfgCcsrGenSr2;
> + UINT32 DcfgCcsrGenSr3;
> + UINT32 DcfgCcsrGenSr4;
> + UINT32 DcfgCcsrGenCr1;
> + UINT32 DcfgCcsrGenCr2;
> + UINT32 DcfgCcsrGenCr3;
> + UINT32 DcfgCcsrGenCr4;
> + UINT32 DcfgCcsrGenCr5;
> + UINT32 DcfgCcsrGenCr6;
> + UINT32 DcfgCcsrGenCr7;
> + UINT8 Res63c[0x658-0x63c];
> + UINT32 DcfgCcsrcGenSr1;
> + UINT32 DcfgCcsrcGenSr0;
> + UINT8 Res660[0x678-0x660];
> + UINT32 DcfgCcsrcGenCr1;
> + UINT32 DcfgCcsrcGenCr0;
> + UINT8 Res680[0x700-0x680];
> + UINT32 DcfgCcsrSrIoPstecr;
> + UINT32 DcfgCcsrDcsrCr;
> + UINT8 Res708[0x740-0x708]; /* add more registers when needed */
> + UINT32 TpItyp[64]; /* Topology Initiator Type Register */
> + struct {
> + UINT32 Upper;
> + UINT32 Lower;
> + } TpCluster[16];
> + UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
> + UINT32 DcfgCcsrQmBmWarmRst;
> + UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
> + UINT32 DcfgCcsrReserved0;
> + UINT32 DcfgCcsrReserved1;
> +} CCSR_GUR;
> +
> +/* Supplemental Configuration Unit */
> +typedef struct {
> + UINT8 Res000[0x070-0x000];
> + UINT32 Usb1Prm1Cr;
> + UINT32 Usb1Prm2Cr;
> + UINT32 Usb1Prm3Cr;
> + UINT32 Usb2Prm1Cr;
> + UINT32 Usb2Prm2Cr;
> + UINT32 Usb2Prm3Cr;
> + UINT32 Usb3Prm1Cr;
> + UINT32 Usb3Prm2Cr;
> + UINT32 Usb3Prm3Cr;
> + UINT8 Res094[0x100-0x094];
> + UINT32 Usb2Icid;
> + UINT32 Usb3Icid;
> + UINT8 Res108[0x114-0x108];
> + UINT32 DmaIcid;
> + UINT32 SataIcid;
> + UINT32 Usb1Icid;
> + UINT32 QeIcid;
> + UINT32 SdhcIcid;
> + UINT32 EdmaIcid;
> + UINT32 EtrIcid;
> + UINT32 Core0SftRst;
> + UINT32 Core1SftRst;
> + UINT32 Core2SftRst;
> + UINT32 Core3SftRst;
> + UINT8 Res140[0x158-0x140];
> + UINT32 AltCBar;
> + UINT32 QspiCfg;
> + UINT8 Res160[0x180-0x160];
> + UINT32 DmaMcr;
> + UINT8 Res184[0x188-0x184];
> + UINT32 GicAlign;
> + UINT32 DebugIcid;
> + UINT8 Res190[0x1a4-0x190];
> + UINT32 SnpCnfGcr;
> +#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
> +#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
> +#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
> +#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
> +#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
> +#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
> +#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
> +#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
> +#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
> +#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
> + UINT8 Res1a8[0x1ac-0x1a8];
> + UINT32 IntpCr;
> + UINT8 Res1b0[0x204-0x1b0];
> + UINT32 CoreSrEnCr;
> + UINT8 Res208[0x220-0x208];
> + UINT32 RvBar00;
> + UINT32 RvBar01;
> + UINT32 RvBar10;
> + UINT32 RvBar11;
> + UINT32 RvBar20;
> + UINT32 RvBar21;
> + UINT32 RvBar30;
> + UINT32 RvBar31;
> + UINT32 LpmCsr;
> + UINT8 Res244[0x400-0x244];
> + UINT32 QspIdQScr;
> + UINT32 EcgTxcMcr;
> + UINT32 SdhcIoVSelCr;
> + UINT32 RcwPMuxCr0;
> + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> + *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> + *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
> + Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
> +#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
> + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> + *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> + *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
> + Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
> +#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
> + UINT32 UsbDrvVBusSelCr;
> +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
> +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
> +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
> + UINT32 UsbPwrFaultSelCr;
> +#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
> +#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
> +#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
> +#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
> +#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
> +#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
> + UINT32 UsbRefclkSelcr1;
> + UINT32 UsbRefclkSelcr2;
> + UINT32 UsbRefclkSelcr3;
> + UINT8 Res424[0x600-0x424];
> + UINT32 ScratchRw[4];
> + UINT8 Res610[0x680-0x610];
> + UINT32 CoreBCr;
> + UINT8 Res684[0x1000-0x684];
> + UINT32 Pex1MsiIr;
> + UINT32 Pex1MsiR;
> + UINT8 Res1008[0x2000-0x1008];
> + UINT32 Pex2;
> + UINT32 Pex2MsiR;
> + UINT8 Res2008[0x3000-0x2008];
> + UINT32 Pex3MsiIr;
> + UINT32 Pex3MsiR;
> +} CCSR_SCFG;
> +
> +#define USB_TXVREFTUNE 0x9
> +#define USB_SQRXTUNE 0xFC7FFFFF
> +#define USB_PCSTXSWINGFULL 0x47
> +#define USB_PHY_RX_EQ_VAL_1 0x0000
> +#define USB_PHY_RX_EQ_VAL_2 0x8000
> +#define USB_PHY_RX_EQ_VAL_3 0x8003
> +#define USB_PHY_RX_EQ_VAL_4 0x800b
> +
> +/*USB_PHY_SS memory map*/
> +typedef struct {
> + UINT16 IpIdcodeLo;
> + UINT16 SupIdcodeHi;
> + UINT8 Res4[0x0006-0x0004];
> + UINT16 RtuneDebug;
> + UINT16 RtuneStat;
> + UINT16 SupSsPhase;
> + UINT16 SsFreq;
> + UINT8 ResE[0x0020-0x000e];
> + UINT16 Ateovrd;
> + UINT16 MpllOvrdInLo;
> + UINT8 Res24[0x0026-0x0024];
> + UINT16 SscOvrdIn;
> + UINT8 Res28[0x002A-0x0028];
> + UINT16 LevelOvrdIn;
> + UINT8 Res2C[0x0044-0x002C];
> + UINT16 ScopeCount;
> + UINT8 Res46[0x0060-0x0046];
> + UINT16 MpllLoopCtl;
> + UINT8 Res62[0x006C-0x0062];
> + UINT16 SscClkCntrl;
> + UINT8 Res6E[0x2002-0x006E];
> + UINT16 Lane0TxOvrdInHi;
> + UINT16 Lane0TxOvrdDrvLo;
> + UINT8 Res2006[0x200C-0x2006];
> + UINT16 Lane0RxOvrdInHi;
> + UINT8 Res200E[0x2022-0x200E];
> + UINT16 Lane0TxCmWaitTimeOvrd;
> + UINT8 Res2024[0x202A-0x2024];
> + UINT16 Lane0TxLbertCtl;
> + UINT16 Lane0RxLbertCtl;
> + UINT16 Lane0RxLbertErr;
> + UINT8 Res2030[0x205A-0x2030];
> + UINT16 Lane0TxAltBlock;
> +} CCSR_USB_PHY;
> +
> +/* Clocking */
> +typedef struct {
> + struct {
> + UINT32 ClkCnCSr; /* core cluster n clock control status */
> + UINT8 Res004[0x0c];
> + UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
> + UINT8 Res014[0x0c];
> + } ClkcSr[4];
> + UINT8 Res040[0x780]; /* 0x100 */
> + struct {
> + UINT32 PllCnGSr;
> + UINT8 Res804[0x1c];
> + } PllCgSr[NUM_CC_PLLS];
> + UINT8 Res840[0x1c0];
> + UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
> + UINT8 Resa04[0x1fc];
> + UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
> + UINT8 Resc04[0x1c];
> + UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
> + UINT8 Resc24[0x3dc];
> +} CCSR_CLOCK;
> +
> +VOID
> +GetSysInfo (
> + OUT SYS_INFO *
> + );
> +
> +UINT32
> +EFIAPI
> +GurRead (
> + IN UINTN Address
> + );
> +
> +#endif /* __SOC_H__ */
> diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS1043aSocLib.inf
> new file mode 100644
> index 0000000..1b2f9c4
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf
> @@ -0,0 +1,47 @@
> +# @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = SocLib
> + FILE_GUID = e868c5ca-9729-43ae-bff4-438c67de8c68
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SocLib
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> + Silicon/NXP/LS1043A/LS1043A.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BeIoLib
> + DebugLib
> + SerialPortLib
> +
> +[Sources.common]
> + Chassis.c
> + Chassis2/Soc.c
> + SerDes.c
> +
> +[FixedPcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> diff --git a/Silicon/NXP/Chassis/SerDes.c b/Silicon/NXP/Chassis/SerDes.c
> new file mode 100644
> index 0000000..e4578c3
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/SerDes.c
> @@ -0,0 +1,271 @@
> +/** SerDes.c
> + Provides the basic interfaces for SerDes Module
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Bitops.h>
> +#include <Library/DebugLib.h>
> +#include <SerDes.h>
> +#include <SocSerDes.h>
> +#include <Soc.h>
> +#include <Uefi.h>
> +
> +/**
> + Function to get serdes Lane protocol corresponding to
> + serdes protocol.
> +
> + @param SerDes Serdes number.
> + @param Cfg Serdes Protocol.
> + @param Lane Serdes Lane number.
> +
> + @return Serdes Lane protocol.
> +
> +**/
> +STATIC
> +SERDES_PROTOCOL
> +GetSerDesPrtcl (
> + IN INTN SerDes,
> + IN INTN Cfg,
> + IN INTN Lane
> + )
> +{
> + SERDES_CONFIG *Config;
> +
> + if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
> + return 0;
> + }
> +
> + Config = SerDesConfigTbl[SerDes];
> + while (Config->Protocol) {
> + if (Config->Protocol == Cfg) {
> + return Config->SrdsLane[Lane];
> + }
> + Config++;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to check if inputted protocol is a valid serdes protocol.
> +
> + @param SerDes Serdes number.
> + @param Prtcl Serdes Protocol to be verified.
> +
> + @return EFI_INVALID_PARAMETER Input parameter in invalid.
> + @return EFI_NOT_FOUND Serdes Protocol not a valid protocol.
> + @return EFI_SUCCESS Serdes Protocol is a valid protocol.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +CheckSerDesPrtclValid (
> + IN INTN SerDes,
> + IN UINT32 Prtcl
> + )
> +{
> + SERDES_CONFIG *Config;
> + INTN Cnt;
> +
> + if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Config = SerDesConfigTbl[SerDes];
> + while (Config->Protocol) {
> + if (Config->Protocol == Prtcl) {
> + DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl));
> + break;
> + }
> + Config++;
> + }
> +
> + if (!Config->Protocol) {
> + return EFI_NOT_FOUND;
> + }
> +
> + for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
> + if (Config->SrdsLane[Cnt] != NONE) {
> + return EFI_SUCCESS;
> + }
> + }
> +
> + return EFI_NOT_FOUND;
> +}
> +
> +/**
> + Function to fill serdes map information.
> +
> + @param Srds Serdes number.
> + @param SerdesProtocolMask Serdes Protocol Mask.
> + @param SerdesProtocolShift Serdes Protocol shift value.
> + @param SerDesPrtclMap Pointer to Serdes Protocol map.
> +
> +**/
> +STATIC
> +VOID
> +LSSerDesMap (
> + IN UINT32 Srds,
> + IN UINT32 SerdesProtocolMask,
> + IN UINT32 SerdesProtocolShift,
> + OUT UINT64 *SerDesPrtclMap
> + )
> +{
> + CCSR_GUR *Gur;
> + UINT32 SrdsProt;
> + INTN Lane;
> + UINT32 Flag;
> +
> + Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + *SerDesPrtclMap = 0x0;
> + Flag = 0;
> +
> + SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
> + SrdsProt >>= SerdesProtocolShift;
> +
> + DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
> + Srds + 1, SrdsProt, SrdsProt));
Spurious indentation.
> +
> + if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
> + DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
> + Srds + 1, SrdsProt));
Spurious indentation.
> + Flag++;
> + }
> +
> + for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
> + SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
> + if (LanePrtcl >= SERDES_PRTCL_COUNT) {
> + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
> + Flag++;
> + } else {
> + *SerDesPrtclMap |= BIT (LanePrtcl);
> + }
> + }
> +
> + if (Flag) {
> + DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
> + } else {
> + DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
> + }
> +}
> +
> +/**
> + Get lane protocol on provided serdes lane and execute callback function.
> +
> + @param Srds Serdes number.
> + @param SerdesProtocolMask Mask to get Serdes Protocol for Srds
> + @param SerdesProtocolShift Shift value to get Serdes Protocol for Srds.
> + @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
> + @param Arg Pointer to Arguments to be passed to callback function.
> +
> +**/
> +STATIC
> +VOID
> +SerDesInstanceProbeLanes (
> + IN UINT32 Srds,
> + IN UINT32 SerdesProtocolMask,
> + IN UINT32 SerdesProtocolShift,
> + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> + IN VOID *Arg
> + )
> +{
> +
> + CCSR_GUR *Gur;
> + UINT32 SrdsProt;
> + INTN Lane;
> +
> + Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
> +
> + SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
> + SrdsProt >>= SerdesProtocolShift;
> +
> + /*
> + * Invoke callback for all lanes in the SerDes instance:
> + */
> + for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
> + SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
> + if (LanePrtcl >= SERDES_PRTCL_COUNT || LanePrtcl < NONE) {
Please use parentheses rather than relying on operator precedence.
> + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
> + }
> + else if (LanePrtcl != NONE) {
else on same line as }
> + SerDesLaneProbeCallback (LanePrtcl, Arg);
> + }
> + }
> +}
> +
> +/**
> + Probe all serdes lanes for lane protocol and execute provided callback function.
> +
> + @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
> + @param Arg Pointer to Arguments to be passed to callback function.
> +
> +**/
> +VOID
> +SerDesProbeLanes (
> + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> + IN VOID *Arg
> + )
> +{
> + SerDesInstanceProbeLanes (SRDS_1,
> + RCWSR_SRDS1_PRTCL_MASK,
> + RCWSR_SRDS1_PRTCL_SHIFT,
> + SerDesLaneProbeCallback,
> + Arg);
> +
> + if (PcdGetBool (PcdSerdes2Enabled)) {
> + SerDesInstanceProbeLanes (SRDS_2,
> + RCWSR_SRDS2_PRTCL_MASK,
> + RCWSR_SRDS2_PRTCL_SHIFT,
> + SerDesLaneProbeCallback,
> + Arg);
> + }
> +}
> +
> +/**
> + Function to return Serdes protocol map for all serdes available on board.
> +
> + @param SerDesPrtclMap Pointer to Serdes protocl map.
> +
> +**/
> +VOID
> +GetSerdesProtocolMaps (
> + OUT UINT64 *SerDesPrtclMap
> + )
> +{
> + LSSerDesMap (SRDS_1,
> + RCWSR_SRDS1_PRTCL_MASK,
> + RCWSR_SRDS1_PRTCL_SHIFT,
> + SerDesPrtclMap);
> +
> + if (PcdGetBool (PcdSerdes2Enabled)) {
> + LSSerDesMap (SRDS_2,
> + RCWSR_SRDS2_PRTCL_MASK,
> + RCWSR_SRDS2_PRTCL_SHIFT,
> + SerDesPrtclMap);
> + }
> +
> +}
> +
> +BOOLEAN
> +IsSerDesLaneProtocolConfigured (
> + IN UINT64 SerDesPrtclMap,
> + IN SERDES_PROTOCOL Device
> + )
> +{
> + if (Device >= SERDES_PRTCL_COUNT || Device < NONE) {
Please use parentheses rather than relying on operator precedence.
> + ASSERT (Device > NONE && Device < SERDES_PRTCL_COUNT);
(Here as well.)
> + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device));
> + }
> +
> + return (SerDesPrtclMap & BIT (Device)) != 0 ;
> +}
> diff --git a/Silicon/NXP/Include/Bitops.h b/Silicon/NXP/Include/Bitops.h
> new file mode 100644
> index 0000000..beddb4e
> --- /dev/null
> +++ b/Silicon/NXP/Include/Bitops.h
> @@ -0,0 +1,179 @@
> +/** Bitops.h
> + Header defining the general bitwise operations
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __BITOPS_H__
> +#define __BITOPS_H__
> +
> +#include <Library/DebugLib.h>
> +
> +#define MASK_LOWER_16 0xFFFF0000
> +#define MASK_UPPER_16 0x0000FFFF
> +#define MASK_LOWER_8 0xFF000000
> +#define MASK_UPPER_8 0x000000FF
These appear unused by the set.
> +
> +/*
> + * Returns the bit mask for a bit index from 0 to 31
> + */
> +#define BIT(_BitIndex) (0x1u << (_BitIndex))
I don't see these being used for anything other than setting up BIT1
BIT2 BIT3 and so on. We already have those in Base.h.
> +
> +/**
> + * Upper32Bits - return bits 32-63 of a number
> + * @N: the number we're accessing
> + *
> + * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
> + * the "right shift count >= width of type" warning when that quantity is
> + * 32-bits.
> + */
> +#define Upper32Bits(N) ((UINT32)(((N) >> 16) >> 16))
1) Compiler warnings are there for a reason.
2) This does not appear to be actually used.
Can we just drop it?
> +
> +/**
> + * Lower32Bits - return bits 0-31 of a number
> + * @N: the number we're accessing
> + */
> +#define Lower32Bits(N) ((UINT32)(N))
Same here.
> +
> +
> +/*
> + * Stores a value for a given bit field in 32-bit '_Container'
> + */
> +
> +#define SET_BIT_FIELD32(_Container, _BitShift, _BitWidth, _Value) \
> + __SET_BIT_FIELD32(_Container, \
> + __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth), \
> + _BitShift, \
> + _Value)
> +
> +#define __SET_BIT_FIELD32(_Container, _BitMask, _BitShift, _Value) \
> + do { \
> + (_Container) &= ~(_BitMask); \
> + if ((_Value) != 0) { \
> + ASSERT(((UINT32)(_Value) << (_BitShift)) <= (_BitMask)); \
> + (_Container) |= \
> + ((UINT32)(_Value) << (_BitShift)) & (_BitMask); \
> + } \
> + } while (0)
> +
> +/*
> + * Extracts the value for a given bit field in 32-bit _Container
> + */
> +
> +#define GET_BIT_FIELD32(_Container, _BitShift, _BitWidth) \
> + __GET_BIT_FIELD32(_Container, \
> + __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth), \
> + _BitShift)
> +
> +#define __GET_BIT_FIELD32(_Container, _BitMask, _BitShift) \
> + (((UINT32)(_Container) & (_BitMask)) >> (_BitShift))
> +
> +#define __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth) \
> + ((_BitWidth) < 32 ? \
> + (((UINT32)1 << (_BitWidth)) - 1) << (_BitShift) : \
> + ~(UINT32)0)
> +
> +/*
> + *Stores a value for a given bit field in 64-bit '_Container'
> + */
> +#define SET_BIT_FIELD64(_Container, _BitShift, _BitWidth, _Value) \
> + __SET_BIT_FIELD64(_Container, \
> + __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth), \
> + _BitShift, \
> + _Value)
> +
> +#define __SET_BIT_FIELD64(_Container, _BitMask, _BitShift, _Value) \
> + do { \
> + (_Container) &= ~(_BitMask); \
> + if ((_Value) != 0) { \
> + ASSERT(((UINT64)(_Value) << (_BitShift)) <= (_BitMask)); \
> + (_Container) |= \
> + ((UINT64)(_Value) << (_BitShift)) & (_BitMask); \
> + } \
> + } while (0)
> +
> +/*
> + * Extracts the value for a given bit field in 64-bit _Container
> + */
> +#define GET_BIT_FIELD64(_Container, _BitShift, _BitWidth) \
> + __GET_BIT_FIELD64(_Container, \
> + __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth), \
> + _BitShift)
> +
> +#define __GET_BIT_FIELD64(_Container, _BitMask, _BitShift) \
> + (((UINT64)(_Container) & (_BitMask)) >> (_BitShift))
> +
> +#define __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth) \
> + ((_BitWidth) < 64 ? \
> + (((UINT64)1 << (_BitWidth)) - 1) << (_BitShift) : \
> + ~(UINT64)0)
> +
These all appear unused.
Also, there are BitField operations in edk2 BaseLib.
> +/**
> +
> + Test If the Destination buffer sets (0->1) or clears (1->0) any bit in Source buffer ?
> +
> + @param[in] Source Source Buffer Pointer
> + @param[in] Destination Destination Buffer Pointer
> + @param[in] NumBytes Bytes to Compare
> + @param[in] Set True : Test Weather Destination buffer sets any bit in Source buffer ?
> + False : Test Weather Destination buffer clears any bit in Source buffer ?
> +
> + @retval TRUE Destination buffer sets/clear a bit in source buffer.
> + @retval FALSE Destination buffer doesn't sets/clear bit in source buffer.
> +
> +**/
> +STATIC
> +inline
> +BOOLEAN
> +TestBitSetClear (
This one is used, but only once, in NorFlashDxe.
Coding Style also bans function definitions in header files.
Can this move directly to NorFlashDxe.c?
> + IN VOID *Source,
> + IN VOID *Destination,
> + IN UINTN NumBytes,
> + IN BOOLEAN Set
> + )
> +{
> + UINTN Index = 0;
> + VOID* Buffer;
> +
> + if (Set) {
> + Buffer = Destination;
> + } else {
> + Buffer = Source;
> + }
> +
> + while (Index < NumBytes) {
> + if ((NumBytes - Index) >= 8) {
> + if ((*((UINT64*)(Source+Index)) ^ *((UINT64*)(Destination+Index))) & *((UINT64*)(Buffer+Index))) {
> + return TRUE;
> + }
> + Index += 8;
> + } else if ((NumBytes - Index) >= 4) {
> + if ((*((UINT32*)(Source+Index)) ^ *((UINT32*)(Destination+Index))) & *((UINT32*)(Buffer+Index))) {
> + return TRUE;
> + }
> + Index += 4;
> + } else if ((NumBytes - Index) >= 2) {
> + if ((*((UINT16*)(Source+Index)) ^ *((UINT16*)(Destination+Index))) & *((UINT16*)(Buffer+Index))) {
> + return TRUE;
> + }
> + Index += 2;
> + } else if ((NumBytes - Index) >= 1) {
> + if ((*((UINT8*)(Source+Index)) ^ *((UINT8*)(Destination+Index))) & *((UINT8*)(Buffer+Index))) {
> + return TRUE;
> + }
> + Index += 1;
> + }
> + }
> + return FALSE;
> +}
> +
> +#endif
On the whole, it looks like this header file can go.
/
Leif
> diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
> new file mode 100644
> index 0000000..90e165f
> --- /dev/null
> +++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h
> @@ -0,0 +1,55 @@
> +/** @file
> + The Header file of SerDes Module for LS1043A
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __SOC_SERDES_H__
> +#define __SOC_SERDES_H__
> +
> +#include <SerDes.h>
> +
> +SERDES_CONFIG SerDes1ConfigTbl[] = {
> + /* SerDes 1 */
> + {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } },
> + {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
> + {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } },
> + {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } },
> + {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
> + {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
> + {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } },
> + {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
> + {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } },
> + {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
> + {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } },
> + {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } },
> + {0x9998, {PCIE1, PCIE2, PCIE3, SATA } },
> + {0x6058, {PCIE1, PCIE1, PCIE2, SATA } },
> + {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
> + {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
> + {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } },
> + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
> + {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
> + {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
> + {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
> + {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } },
> + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {}
> +};
> +
> +SERDES_CONFIG *SerDesConfigTbl[] = {
> + SerDes1ConfigTbl
> +};
> +
> +#endif /* __SOC_SERDES_H */
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 04/39] Silicon/NXP : Add support for DUART library
2018-02-16 8:50 ` [PATCH edk2-platforms 04/39] Silicon/NXP : Add support for DUART library Meenakshi
@ 2018-04-18 15:15 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-18 15:15 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
On Fri, Feb 16, 2018 at 02:20:00PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Silicon/NXP/Library/DUartPortLib/DUart.h | 128 ++++++++
> Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 370 ++++++++++++++++++++++
> Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 41 +++
> 3 files changed, 539 insertions(+)
> create mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
> create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
>
> diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h b/Silicon/NXP/Library/DUartPortLib/DUart.h
> new file mode 100644
> index 0000000..3fa0a68
> --- /dev/null
> +++ b/Silicon/NXP/Library/DUartPortLib/DUart.h
> @@ -0,0 +1,128 @@
> +/** DUart.h
> +* Header defining the DUART constants (Base addresses, sizes, flags)
> +*
> +* Based on Serial I/O Port library headers available in PL011Uart.h
> +*
> +* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __DUART_H__
> +#define __DUART_H__
> +
> +// FIFO Control Register
> +#define DUART_FCR_FIFO_EN 0x01 /* Fifo enable */
> +#define DUART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
> +#define DUART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
> +#define DUART_FCR_DMA_SELECT 0x08 /* For DMA applications */
> +#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
> +#define DUART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
> +#define DUART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
> +#define DUART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
> +#define DUART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
> +#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */
> +#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */
> +
> +// Modem Control Register
> +#define DUART_MCR_DTR 0x01 /* Reserved */
> +#define DUART_MCR_RTS 0x02 /* RTS */
> +#define DUART_MCR_OUT1 0x04 /* Reserved */
> +#define DUART_MCR_OUT2 0x08 /* Reserved */
> +#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */
> +#define DUART_MCR_AFE 0x20 /* AFE (Auto Flow Control) */
> +#define DUART_MCR_DMA_EN 0x04
> +#define DUART_MCR_TX_DFR 0x08
> +
> +// Line Control Register
> +/*
> +* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting
> +* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
> +*/
> +#define DUART_LCR_WLS_MSK 0x03 /* character length select mask */
> +#define DUART_LCR_WLS_5 0x00 /* 5 bit character length */
> +#define DUART_LCR_WLS_6 0x01 /* 6 bit character length */
> +#define DUART_LCR_WLS_7 0x02 /* 7 bit character length */
> +#define DUART_LCR_WLS_8 0x03 /* 8 bit character length */
> +#define DUART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
> +#define DUART_LCR_PEN 0x08 /* Parity eneble */
> +#define DUART_LCR_EPS 0x10 /* Even Parity Select */
> +#define DUART_LCR_STKP 0x20 /* Stick Parity */
> +#define DUART_LCR_SBRK 0x40 /* Set Break */
> +#define DUART_LCR_BKSE 0x80 /* Bank select enable */
> +#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */
> +
> +// Line Status Register
> +#define DUART_LSR_DR 0x01 /* Data ready */
> +#define DUART_LSR_OE 0x02 /* Overrun */
> +#define DUART_LSR_PE 0x04 /* Parity error */
> +#define DUART_LSR_FE 0x08 /* Framing error */
> +#define DUART_LSR_BI 0x10 /* Break */
> +#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */
> +#define DUART_LSR_TEMT 0x40 /* Xmitter empty */
> +#define DUART_LSR_ERR 0x80 /* Error */
> +
> +// Modem Status Register
> +#define DUART_MSR_DCTS 0x01 /* Delta CTS */
> +#define DUART_MSR_DDSR 0x02 /* Reserved */
> +#define DUART_MSR_TERI 0x04 /* Reserved */
> +#define DUART_MSR_DDCD 0x08 /* Reserved */
> +#define DUART_MSR_CTS 0x10 /* Clear to Send */
> +#define DUART_MSR_DSR 0x20 /* Reserved */
> +#define DUART_MSR_RI 0x40 /* Reserved */
> +#define DUART_MSR_DCD 0x80 /* Reserved */
> +
> +// Interrupt Identification Register
> +#define DUART_IIR_NO_INT 0x01 /* No interrupts pending */
> +#define DUART_IIR_ID 0x06 /* Mask for the interrupt ID */
> +#define DUART_IIR_MSI 0x00 /* Modem status interrupt */
> +#define DUART_IIR_THRI 0x02 /* Transmitter holding register empty */
> +#define DUART_IIR_RDI 0x04 /* Receiver data interrupt */
> +#define DUART_IIR_RLSI 0x06 /* Receiver line status interrupt */
> +
> +// Interrupt Enable Register
> +#define DUART_IER_MSI 0x08 /* Enable Modem status interrupt */
> +#define DUART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
> +#define DUART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
> +#define DUART_IER_RDI 0x01 /* Enable receiver data interrupt */
> +
> +// LCR defaults
> +#define DUART_LCR_8N1 0x03
> +#define DUART_LCRVAL DUART_LCR_8N1 /* 8 data, 1 stop, no parity */
> +#define DUART_MCRVAL (DUART_MCR_DTR | \
> + DUART_MCR_RTS) /* RTS/DTR */
> +#define DUART_FCRVAL (DUART_FCR_FIFO_EN | \
> + DUART_FCR_RXSR | \
> + DUART_FCR_TXSR) /* Clear & enable FIFOs */
> +
> +#define URBR 0x0
> +#define UTHR 0x0
> +#define UDLB 0x0
> +#define UDMB 0x1
> +#define UIER 0x1
> +#define UIIR 0x2
> +#define UFCR 0x2
> +#define UAFR 0x2
> +#define ULCR 0x3
> +#define UMCR 0x4
> +#define ULSR 0x5
> +#define UMSR 0x6
> +#define USCR 0x7
> +#define UDSR 0x10
> +
> +extern
> +UINT64
> +GetBusFrequency (
> + VOID
> + );
> +
> +#endif /* __DUART_H__ */
> diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> new file mode 100644
> index 0000000..5fcfa9a
> --- /dev/null
> +++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> @@ -0,0 +1,370 @@
> +/** DuartPortLib.c
> + DUART (NS16550) library functions
> +
> + Based on Serial I/O Port library functions available in PL011SerialPortLib.c
> +
> + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
> + Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
> + Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +#include "DUart.h"
> +
> +STATIC CONST UINT32 mInvalidControlBits = (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE | \
> + EFI_SERIAL_DATA_TERMINAL_READY);
> +
> +/**
> + Assert or deassert the control signals on a serial port.
> + The following control signals are set according their bit settings :
> + . Request to Send
> + . Data Terminal Ready
> +
> + @param[in] Control The following bits are taken into account :
> + . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
> + "Request To Send" control signal if this bit is
> + equal to one/zero.
> + . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
> + the "Data Terminal Ready" control signal if this
> + bit is equal to one/zero.
> + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
> + the hardware loopback if this bit is equal to
> + one/zero.
> + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
> + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
> + disable the hardware flow control based on CTS (Clear
> + To Send) and RTS (Ready To Send) control signals.
> +
> + @retval EFI_SUCCESS The new control bits were set on the device.
> + @retval EFI_UNSUPPORTED The device does not support this operation.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SerialPortSetControl (
> + IN UINT32 Control
> + )
> +{
> + UINT32 McrBits;
> + UINTN UartBase;
> +
> + UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> +
> + if (Control & (mInvalidControlBits)) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + McrBits = MmioRead8 (UartBase + UMCR);
> +
> + if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
> + McrBits |= DUART_MCR_RTS;
> + } else {
> + McrBits &= ~DUART_MCR_RTS;
> + }
> +
> + if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {
> + McrBits |= DUART_MCR_LOOP;
> + } else {
> + McrBits &= ~DUART_MCR_LOOP;
> + }
> +
> + if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
> + McrBits |= DUART_MCR_AFE;
> + } else {
> + McrBits &= ~DUART_MCR_AFE;
> + }
> +
> + MmioWrite32 (UartBase + UMCR, McrBits);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Retrieve the status of the control bits on a serial device.
> +
> + @param[out] Control Status of the control bits on a serial device :
> +
> + . EFI_SERIAL_DATA_CLEAR_TO_SEND,
> + EFI_SERIAL_DATA_SET_READY,
> + EFI_SERIAL_RING_INDICATE,
> + EFI_SERIAL_CARRIER_DETECT,
> + EFI_SERIAL_REQUEST_TO_SEND,
> + EFI_SERIAL_DATA_TERMINAL_READY
> + are all related to the DTE (Data Terminal Equipment)
> + and DCE (Data Communication Equipment) modes of
> + operation of the serial device.
> + . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
> + receive buffer is empty, 0 otherwise.
> + . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
> + transmit buffer is empty, 0 otherwise.
> + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
> + the hardware loopback is enabled (the ouput feeds the
> + receive buffer), 0 otherwise.
> + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if
> + a loopback is accomplished by software, 0 otherwise.
> + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
> + one if the hardware flow control based on CTS (Clear
> + To Send) and RTS (Ready To Send) control signals is
> + enabled, 0 otherwise.
> +
> + @retval EFI_SUCCESS The control bits were read from the serial device.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SerialPortGetControl (
> + OUT UINT32 *Control
> + )
> +{
> + UINT32 MsrRegister;
> + UINT32 McrRegister;
> + UINT32 LsrRegister;
> + UINTN UartBase;
> +
> + UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> +
> + MsrRegister = MmioRead8 (UartBase + UMSR);
> + McrRegister = MmioRead8 (UartBase + UMCR);
> + LsrRegister = MmioRead8 (UartBase + ULSR);
> +
> + *Control = 0;
> +
> + if ((MsrRegister & DUART_MSR_CTS) == DUART_MSR_CTS) {
> + *Control |= EFI_SERIAL_CLEAR_TO_SEND;
> + }
> +
> + if ((McrRegister & DUART_MCR_RTS) == DUART_MCR_RTS) {
> + *Control |= EFI_SERIAL_REQUEST_TO_SEND;
> + }
> +
> + if ((LsrRegister & DUART_LSR_TEMT) == DUART_LSR_TEMT) {
> + *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
> + }
> +
> + if ((McrRegister & DUART_MCR_AFE) == DUART_MCR_AFE) {
> + *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
> + }
> +
> + if ((McrRegister & DUART_MCR_LOOP) == DUART_MCR_LOOP) {
> + *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/*
> + * Return Baud divisor on basis of Baudrate
> + */
> +UINT32
> +CalculateBaudDivisor (
> + IN UINT64 BaudRate
> + )
> +{
> + UINTN DUartClk;
> + UINTN FreqSystemBus;
> +
> + FreqSystemBus = GetBusFrequency ();
> + DUartClk = FreqSystemBus/PcdGet32(PcdPlatformFreqDiv);
> +
> + return ((DUartClk)/(BaudRate * 16));
> +}
> +
> +/*
> + Initialise the serial port to the specified settings.
> + All unspecified settings will be set to the default values.
> +
> + @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER.
> +
> + **/
> +VOID
> +EFIAPI
> +DuartInitializePort (
> + IN UINT64 BaudRate
> + )
> +{
> + UINTN UartBase;
> + UINT32 BaudDivisor;
> +
> + UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> + BaudDivisor = CalculateBaudDivisor (BaudRate);
> +
> +
> + while (!(MmioRead8 (UartBase + ULSR) & DUART_LSR_TEMT));
> +
> + //
> + // Enable and assert interrupt when new data is available on
> + // external device,
> + // setup data format, setup baud divisor
> + //
> + MmioWrite8 (UartBase + UIER, 0x1);
> + MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
> + MmioWrite8 (UartBase + UDLB, 0);
> + MmioWrite8 (UartBase + UDMB, 0);
> + MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
> + MmioWrite8 (UartBase + UMCR, DUART_MCRVAL);
> + MmioWrite8 (UartBase + UFCR, DUART_FCRVAL);
> + MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
> + MmioWrite8 (UartBase + UDLB, BaudDivisor & 0xff);
> + MmioWrite8 (UartBase + UDMB, (BaudDivisor >> 8) & 0xff);
> + MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
> +
> + return;
> +}
> +
> +/**
> + Programmed hardware of Serial port.
> +
> + @return Always return EFI_SUCCESS.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SerialPortInitialize (
> + VOID
> + )
> +{
> + UINT64 BaudRate;
> + BaudRate = (UINTN)PcdGet64 (PcdUartDefaultBaudRate);
> +
> +
> + DuartInitializePort (BaudRate);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Write data to serial device.
> +
> + @param Buffer Point of data buffer which need to be written.
> + @param NumberOfBytes Number of output bytes which are cached in Buffer.
> +
> + @retval 0 Write data failed.
> + @retval !0 Actual number of bytes written to serial device.
> +
> +**/
> +UINTN
> +EFIAPI
> +SerialPortWrite (
> + IN UINT8 *Buffer,
> + IN UINTN NumberOfBytes
> + )
> +{
> + UINT8 *Final;
> + UINTN UartBase;
> +
> + Final = &Buffer[NumberOfBytes];
> + UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> +
> + while (Buffer < Final) {
> + while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_THRE) == 0);
> + MmioWrite8 (UartBase + UTHR, *Buffer++);
> + }
> +
> + return NumberOfBytes;
> +}
> +
> +/**
> + Read data from serial device and save the data in buffer.
> +
> + @param Buffer Point of data buffer which need to be written.
> + @param NumberOfBytes Number of output bytes which are cached in Buffer.
> +
> + @retval 0 Read data failed.
> + @retval !0 Actual number of bytes read from serial device.
> +
> +**/
> +UINTN
> +EFIAPI
> +SerialPortRead (
> + OUT UINT8 *Buffer,
> + IN UINTN NumberOfBytes
> + )
> +{
> + UINTN Count;
> + UINTN UartBase;
> +
> + UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> +
> + for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
> + // Loop while waiting for a new char(s) to arrive in the
> + // RxFIFO
> + while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) == 0);
> +
> + *Buffer = MmioRead8 (UartBase + URBR);
> + }
> +
> + return NumberOfBytes;
> +}
> +
> +/**
> + Check to see if any data is available to be read from the debug device.
> +
> + @retval EFI_SUCCESS At least one byte of data is available to be read
> + @retval EFI_NOT_READY No data is available to be read
> + @retval EFI_DEVICE_ERROR The serial device is not functioning properly
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +SerialPortPoll (
> + VOID
> + )
> +{
> + UINTN UartBase;
> +
> + UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
> +
> + return ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) != 0);
> +}
> +
> +/**
> + Set new attributes to LS1043a.
> +
> + @param BaudRate The baud rate of the serial device. If the baud rate is not supported,
> + the speed will be reduced down to the nearest supported one and the
> + variable's value will be updated accordingly.
> + @param ReceiveFifoDepth The number of characters the device will buffer on input. If the specified
> + value is not supported, the variable's value will be reduced down to the
> + nearest supported one.
> + @param Timeout If applicable, the number of microseconds the device will wait
> + before timing out a Read or a Write operation.
> + @param Parity If applicable, this is the EFI_PARITY_TYPE that is computed or checked
> + as each character is transmitted or received. If the device does not
> + support parity, the value is the default parity value.
> + @param DataBits The number of data bits in each character
> + @param StopBits If applicable, the EFI_STOP_BITS_TYPE number of stop bits per character.
> + If the device does not support stop bits, the value is the default stop
> + bit value.
> +
> + @retval EFI_SUCCESS All attributes were set correctly on the serial device.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SerialPortSetAttributes (
> + IN OUT UINT64 *BaudRate,
> + IN OUT UINT32 *ReceiveFifoDepth,
> + IN OUT UINT32 *Timeout,
> + IN OUT EFI_PARITY_TYPE *Parity,
> + IN OUT UINT8 *DataBits,
> + IN OUT EFI_STOP_BITS_TYPE *StopBits
> + )
> +{
> + DuartInitializePort (*BaudRate);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> new file mode 100644
> index 0000000..6940de9
> --- /dev/null
> +++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> @@ -0,0 +1,41 @@
> +# DUartPortLib.inf
> +#
> +# Component description file for DUartPortLib module
> +#
> +# Copyright (c) 2013, Freescale Ltd. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = DUartPortLib
> + FILE_GUID = c42dfe79-8de5-429e-a055-2d0a58591498
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SerialPortLib
> +
> +[Sources.common]
> + DUartPortLib.c
> +
> +[LibraryClasses]
> + PcdLib
> + SocLib
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[Pcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 06/39] Silicon/Maxim : Add support for DS1307 RTC library
2018-02-16 8:50 ` [PATCH edk2-platforms 06/39] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi
@ 2018-04-18 15:27 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-18 15:27 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
On Fri, Feb 16, 2018 at 02:20:02PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> Real time clock Apis on top of I2C Apis
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h | 59 ++++
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 329 +++++++++++++++++++++
> .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec | 26 ++
> .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf | 45 +++
This isn't part of the review, but in future can you try to follow
Laszlo's guide when generating patches:
https://github.com/tianocore/tianocore.github.io/wiki/Laszlo's-unkempt-git-guide-for-edk2-contributors-and-maintainers#contrib-23
?
For this patch:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> 4 files changed, 459 insertions(+)
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
>
> diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
> new file mode 100644
> index 0000000..96271f8
> --- /dev/null
> +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
> @@ -0,0 +1,59 @@
> +/** Ds1307Rtc.h
> +*
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __DS1307RTC_H__
> +#define __DS1307RTC_H__
> +
> +/*
> + * RTC time register
> + */
> +#define DS1307_SEC_REG_ADDR 0x00
> +#define DS1307_MIN_REG_ADDR 0x01
> +#define DS1307_HR_REG_ADDR 0x02
> +#define DS1307_DAY_REG_ADDR 0x03
> +#define DS1307_DATE_REG_ADDR 0x04
> +#define DS1307_MON_REG_ADDR 0x05
> +#define DS1307_YR_REG_ADDR 0x06
> +
> +#define DS1307_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
> +
> +/*
> + * RTC control register
> + */
> +#define DS1307_CTL_REG_ADDR 0x07
> +
> +#define START_YEAR 1970
> +#define END_YEAR 2070
> +
> +/*
> + * TIME MASKS
> + */
> +#define MASK_SEC 0x7F
> +#define MASK_MIN 0x7F
> +#define MASK_HOUR 0x3F
> +#define MASK_DAY 0x3F
> +#define MASK_MONTH 0x1F
> +
> +/*
> + * I2C FLAGS
> + */
> +#define I2C_REG_ADDRESS 0x2
> +
> +typedef struct {
> + UINTN OperationCount;
> + EFI_I2C_OPERATION SetAddressOp;
> + EFI_I2C_OPERATION GetSetDateTimeOp;
> +} RTC_I2C_REQUEST;
> +
> +#endif // __DS1307RTC_H__
> diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> new file mode 100644
> index 0000000..cf45d49
> --- /dev/null
> +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> @@ -0,0 +1,329 @@
> +/** Ds1307RtcLib.c
> + Implement EFI RealTimeClock via RTC Lib for DS1307 RTC.
> +
> + Based on RTC implementation available in
> + EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
> +
> + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/RealTimeClockLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +#include <Protocol/I2cMaster.h>
> +
> +#include "Ds1307Rtc.h"
> +
> +STATIC VOID *mDriverEventRegistration;
> +STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
> +
> +/**
> + Read RTC register.
> +
> + @param RtcRegAddr Register offset of RTC to be read.
> +
> + @retval Register Value read
> +
> +**/
> +
> +STATIC
> +UINT8
> +RtcRead (
> + IN UINT8 RtcRegAddr
> + )
> +{
> + RTC_I2C_REQUEST Req;
> + EFI_STATUS Status;
> + UINT8 Val;
> +
> + Val = 0;
> +
> + Req.OperationCount = 2;
> +
> + Req.SetAddressOp.Flags = 0;
> + Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
> + Req.SetAddressOp.Buffer = &RtcRegAddr;
> +
> + Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
> + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
> + Req.GetSetDateTimeOp.Buffer = &Val;
> +
> + Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
> + (VOID *)&Req,
> + NULL, NULL);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
> + }
> +
> + return Val;
> +}
> +
> +/**
> + Write RTC register.
> +
> + @param RtcRegAddr Register offset of RTC to write.
> + @param Val Value to be written
> +
> +**/
> +
> +STATIC
> +VOID
> +RtcWrite (
> + IN UINT8 RtcRegAddr,
> + IN UINT8 Val
> + )
> +{
> + RTC_I2C_REQUEST Req;
> + EFI_STATUS Status;
> +
> + Req.OperationCount = 2;
> +
> + Req.SetAddressOp.Flags = 0;
> + Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
> + Req.SetAddressOp.Buffer = &RtcRegAddr;
> +
> + Req.GetSetDateTimeOp.Flags = 0;
> + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
> + Req.GetSetDateTimeOp.Buffer = &Val;
> +
> + Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
> + (VOID *)&Req,
> + NULL, NULL);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
> + }
> +}
> +
> +/**
> + Returns the current time and date information, and the time-keeping capabilities
> + of the hardware platform.
> +
> + @param Time A pointer to storage to receive a snapshot of the current time.
> + @param Capabilities An optional pointer to a buffer to receive the real time clock
> + device's capabilities.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_INVALID_PARAMETER Time is NULL.
> + @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
> +
> +**/
> +
> +EFI_STATUS
> +EFIAPI
> +LibGetTime (
> + OUT EFI_TIME *Time,
> + OUT EFI_TIME_CAPABILITIES *Capabilities
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 Second;
> + UINT8 Minute;
> + UINT8 Hour;
> + UINT8 Day;
> + UINT8 Month;
> + UINT8 Year;
> +
> + if (mI2cMaster == NULL) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + Status = EFI_SUCCESS;
> +
> + Second = RtcRead (DS1307_SEC_REG_ADDR);
> + Minute = RtcRead (DS1307_MIN_REG_ADDR);
> + Hour = RtcRead (DS1307_HR_REG_ADDR);
> + Day = RtcRead (DS1307_DATE_REG_ADDR);
> + Month = RtcRead (DS1307_MON_REG_ADDR);
> + Year = RtcRead (DS1307_YR_REG_ADDR);
> +
> + if (Second & DS1307_SEC_BIT_CH) {
> + DEBUG ((DEBUG_ERROR, "### Warning: RTC oscillator has stopped\n"));
> + /* clear the CH flag */
> + RtcWrite (DS1307_SEC_REG_ADDR,
> + RtcRead (DS1307_SEC_REG_ADDR) & ~DS1307_SEC_BIT_CH);
> + Status = EFI_DEVICE_ERROR;
> + }
> +
> + Time->Second = BcdToDecimal8 (Second & MASK_SEC);
> + Time->Minute = BcdToDecimal8 (Minute & MASK_MIN);
> + Time->Hour = BcdToDecimal8 (Hour & MASK_HOUR);
> + Time->Day = BcdToDecimal8 (Day & MASK_DAY);
> + Time->Month = BcdToDecimal8 (Month & MASK_MONTH);
> +
> + //
> + // RTC can save year 1970 to 2069
> + // On writing Year, save year % 100
> + // On Reading reversing the operation e.g. 2012
> + // write = 12 (2012 % 100)
> + // read = 2012 (12 + 2000)
> + //
> + Time->Year = BcdToDecimal8 (Year) +
> + (BcdToDecimal8 (Year) >= 70 ? START_YEAR - 70 : END_YEAR -70);
> +
> + return Status;
> +}
> +
> +/**
> + Sets the current local time and date information.
> +
> + @param Time A pointer to the current time.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_INVALID_PARAMETER A time field is out of range.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibSetTime (
> + IN EFI_TIME *Time
> + )
> +{
> + if (mI2cMaster == NULL) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + if (Time->Year < START_YEAR || Time->Year >= END_YEAR){
> + DEBUG ((DEBUG_ERROR, "WARNING: Year should be between 1970 and 2069!\n"));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + RtcWrite (DS1307_YR_REG_ADDR, DecimalToBcd8 (Time->Year % 100));
> + RtcWrite (DS1307_MON_REG_ADDR, DecimalToBcd8 (Time->Month));
> + RtcWrite (DS1307_DATE_REG_ADDR, DecimalToBcd8 (Time->Day));
> + RtcWrite (DS1307_HR_REG_ADDR, DecimalToBcd8 (Time->Hour));
> + RtcWrite (DS1307_MIN_REG_ADDR, DecimalToBcd8 (Time->Minute));
> + RtcWrite (DS1307_SEC_REG_ADDR, DecimalToBcd8 (Time->Second));
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Returns the current wakeup alarm clock setting.
> +
> + @param Enabled Indicates if the alarm is currently enabled or disabled.
> + @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
> + @param Time The current alarm setting.
> +
> + @retval EFI_SUCCESS The alarm settings were returned.
> + @retval EFI_INVALID_PARAMETER Any parameter is NULL.
> + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
> + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this
> + platform.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibGetWakeupTime (
> + OUT BOOLEAN *Enabled,
> + OUT BOOLEAN *Pending,
> + OUT EFI_TIME *Time
> + )
> +{
> + // The DS1307 does not support setting the alarm
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + Sets the system wakeup alarm clock time.
> +
> + @param Enabled Enable or disable the wakeup alarm.
> + @param Time If Enable is TRUE, the time to set the wakeup alarm for.
> +
> + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
> + Enable is FALSE, then the wakeup alarm was disabled.
> + @retval EFI_INVALID_PARAMETER A time field is out of range.
> + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
> + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibSetWakeupTime (
> + IN BOOLEAN Enabled,
> + OUT EFI_TIME *Time
> + )
> +{
> + // The DS1307 does not support setting the alarm
> + return EFI_UNSUPPORTED;
> +}
> +
> +STATIC
> +VOID
> +I2cDriverRegistrationEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EFI_STATUS Status;
> + EFI_I2C_MASTER_PROTOCOL *I2cMaster;
> + UINTN BusFrequency;
> +
> + Status = gBS->LocateProtocol (&gEfiI2cMasterProtocolGuid, NULL, (VOID **)&I2cMaster);
> +
> + gBS->CloseEvent (Event);
> +
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = I2cMaster->Reset (I2cMaster);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
> + __FUNCTION__, Status));
> + return;
> + }
> +
> + BusFrequency = FixedPcdGet16 (PcdI2cBusFrequency);
> + Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
> + __FUNCTION__, Status));
> + return;
> + }
> +
> + mI2cMaster = I2cMaster;
> +}
> +
> +/**
> + This is the declaration of an EFI image entry point. This can be the entry point to an application
> + written to this specification, an EFI boot service driver.
> +
> + @param ImageHandle Handle that identifies the loaded image.
> + @param SystemTable System Table for this image.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibRtcInitialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + //
> + // Register a protocol registration notification callback on the driver
> + // binding protocol so we can attempt to connect our I2C master to it
> + // as soon as it appears.
> + //
> + EfiCreateProtocolNotifyEvent (
> + &gEfiI2cMasterProtocolGuid,
> + TPL_CALLBACK,
> + I2cDriverRegistrationEvent,
> + NULL,
> + &mDriverEventRegistration);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> new file mode 100644
> index 0000000..1aaf897
> --- /dev/null
> +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> @@ -0,0 +1,26 @@
> +#/** @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#**/
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x0001001A
> + PACKAGE_NAME = Ds1307RtcLib
> + PACKAGE_GUID = 0c095cf6-834d-4fa2-a5a0-31ac35591ad2
> + PACKAGE_VERSION = 0.1
> +
> +[Guids]
> + gDs1307RtcLibTokenSpaceGuid = { 0xd939eb84, 0xa95a, 0x46a0, { 0xa8, 0x2b, 0xb9, 0x64, 0x30, 0xcf, 0xf5, 0x99 }}
> +
> +[PcdsFixedAtBuild]
> + gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001
> + gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002
> diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
> new file mode 100644
> index 0000000..268873b
> --- /dev/null
> +++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
> @@ -0,0 +1,45 @@
> +# @Ds1307RtcLib.inf
> +#
> +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = Ds1307RtcLib
> + FILE_GUID = 7112fb46-8dda-4a41-ac40-bf212fedfc08
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = RealTimeClockLib
> +
> +[Sources.common]
> + Ds1307RtcLib.c
> +
> +[Packages]
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> +
> +[LibraryClasses]
> + DebugLib
> + UefiBootServicesTableLib
> + UefiLib
> +
> +[Protocols]
> + gEfiDriverBindingProtocolGuid ## CONSUMES
> + gEfiI2cMasterProtocolGuid ## CONSUMES
> +
> +[FixedPcd]
> + gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress
> + gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency
> +
> +[Depex]
> + gEfiI2cMasterProtocolGuid
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 07/39] Platform/NXP: Add support for ArmPlatformLib
2018-02-16 8:50 ` [PATCH edk2-platforms 07/39] Platform/NXP: Add support for ArmPlatformLib Meenakshi
@ 2018-04-18 15:32 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-18 15:32 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
On Fri, Feb 16, 2018 at 02:20:03PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> .../Library/PlatformLib/ArmPlatformLib.c | 105 ++++++++++++++
> .../Library/PlatformLib/ArmPlatformLib.inf | 67 +++++++++
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 38 ++++++
> .../Library/PlatformLib/NxpQoriqLsMem.c | 152 +++++++++++++++++++++
> 4 files changed, 362 insertions(+)
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> new file mode 100644
> index 0000000..ab4815d
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> @@ -0,0 +1,105 @@
> +/** ArmPlatformLib.c
> +*
> +* Contains board initialization functions.
> +*
> +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
> +*
> +* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +extern VOID SocInit (VOID);
> +
> +/**
> + Return the current Boot Mode
> +
> + This function returns the boot reason on the platform
> +
> +**/
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> + VOID
> + )
> +{
> + return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +/**
> + Placeholder for Platform Initialization
> +**/
> +EFI_STATUS
> +ArmPlatformInitialize (
> + IN UINTN MpId
> + )
> +{
> + SocInit ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {
> + {
> + // Cluster 0, Core 0
> + 0x0, 0x0,
> +
> + // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (UINT64)0xFFFFFFFF
> + },
> +};
> +
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> + OUT UINTN *CoreCount,
> + OUT ARM_CORE_INFO **ArmCoreTable
> + )
> +{
> + *CoreCount = sizeof (LS1043aMpCoreInfoCTA53x4) / sizeof (ARM_CORE_INFO);
> + *ArmCoreTable = LS1043aMpCoreInfoCTA53x4;
> +
> + return EFI_SUCCESS;
> +}
> +
> +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> +
> +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gArmMpCoreInfoPpiGuid,
> + &mMpCoreInfoPpi
> + }
> +};
> +
> +VOID
> +ArmPlatformGetPlatformPpiList (
> + OUT UINTN *PpiListSize,
> + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
> + )
> +{
> + *PpiListSize = sizeof (gPlatformPpiTable);
> + *PpiList = gPlatformPpiTable;
> +}
> +
> +
> +UINTN
> +ArmPlatformGetCorePosition (
> + IN UINTN MpId
> + )
> +{
> + return 1;
> +}
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> new file mode 100644
> index 0000000..7feac56
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> @@ -0,0 +1,67 @@
> +# @file
> +#
> +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PlatformLib
> + FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ArmPlatformLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + ArmLib
> + SocLib
> +
> +[Sources.common]
> + NxpQoriqLsHelper.S | GCC
> + NxpQoriqLsMem.c
> + ArmPlatformLib.c
> +
> +[Ppis]
> + gArmMpCoreInfoPpiGuid
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdArmPrimaryCore
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> new file mode 100644
> index 0000000..205c0d8
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> @@ -0,0 +1,38 @@
> +# @file
> +#
> +# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <AutoGen.h>
> +
> +.text
> +.align 2
> +
> +GCC_ASM_IMPORT(ArmReadMpidr)
> +
> +ASM_FUNC(ArmPlatformIsPrimaryCore)
> + tst x0, #3
> + cset x0, eq
> + ret
> +
> +ASM_FUNC(ArmPlatformPeiBootAction)
> +EL1_OR_EL2(x0)
> +1:
> +2:
> + ret
> +
> +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
> + MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
> + ldrh w0, [x0]
> + ret
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> new file mode 100644
> index 0000000..64c5612
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> @@ -0,0 +1,152 @@
> +/** NxpQoriqLsMem.c
> +*
> +* Board memory specific Library.
> +*
> +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
> +*
> +* Copyright (c) 2011, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
> +
> +/**
> + Return the Virtual Memory Map of your platform
> +
> + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
> +
> + @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
> + Virtual Memory mapping. This array must be ended by a zero-filled
> + entry
> +
> +**/
> +
> +VOID
> +ArmPlatformGetVirtualMemoryMap (
> + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
> + )
> +{
> + UINTN Index;
> + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> +
> + Index = 0;
> +
> + ASSERT (VirtualMemoryMap != NULL);
> +
> + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
> + EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
> +
> + if (VirtualMemoryTable == NULL) {
> + return;
> + }
> +
> + // DRAM1 (Must be 1st entry)
> + VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // CCSR Space
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // IFC region 1
> + //
> + // A-009241 : Unaligned write transactions to IFC may result in corruption of data
> + // Affects : IFC
> + // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
> + // writes on external IFC interface that can corrupt data on external flash.
> + // Impact : Data corruption on external flash may happen in case of unaligned writes to
> + // IFC memory space.
> + // Workaround: Following are the workarounds:
> + // For write transactions from core, IFC interface memories (including IFC SRAM)
> + // should be configured as device type memory in MMU.
> + // For write transactions from non-core masters (like system DMA), the address
> + // should be 16 byte aligned and the data size should be multiple of 16 bytes.
> + //
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // QMAN SWP
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // BMAN SWP
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // IFC region 2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DRAM2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram2Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // PCIe1
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe3
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DRAM3
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram3BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram3BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram3Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // QSPI region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // End of Table
> + VirtualMemoryTable[++Index].PhysicalBase = 0;
> + VirtualMemoryTable[Index].VirtualBase = 0;
> + VirtualMemoryTable[Index].Length = 0;
> + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
> +
> + ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> + *VirtualMemoryMap = VirtualMemoryTable;
> +}
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 08/39] Compilation : Add the fdf, dsc and dec files.
2018-02-16 8:50 ` [PATCH edk2-platforms 08/39] Compilation : Add the fdf, dsc and dec files Meenakshi
@ 2018-04-18 15:38 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-18 15:38 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
On Fri, Feb 16, 2018 at 02:20:04PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> The firmware device, description and declaration files.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
I am generally happy with this patch, but am expecting an updated
version based on the patch I sent before, so won't give a R-b yet.
When you're looking into these, could you also update the VERSION
fields?
/
Leif
> ---
> Platform/NXP/FVRules.fdf.inc | 99 +++++++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 29 ++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 84 ++++++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 197 +++++++++++++
> Platform/NXP/NxpQoriqLs.dsc | 412 +++++++++++++++++++++++++++
> Silicon/NXP/LS1043A/LS1043A.dec | 22 ++
> Silicon/NXP/LS1043A/LS1043A.dsc | 73 +++++
> Silicon/NXP/NxpQoriqLs.dec | 117 ++++++++
> 8 files changed, 1033 insertions(+)
> create mode 100644 Platform/NXP/FVRules.fdf.inc
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> create mode 100644 Platform/NXP/NxpQoriqLs.dsc
> create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
> create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc
> create mode 100644 Silicon/NXP/NxpQoriqLs.dec
>
> diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc
> new file mode 100644
> index 0000000..d0e17cb
> --- /dev/null
> +++ b/Platform/NXP/FVRules.fdf.inc
> @@ -0,0 +1,99 @@
> +# FvRules.fdf.inc
> +#
> +# Rules for creating FD.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# Rules are use with the [FV] section's module INF type to define
> +# how an FFS file is created for a given INF file. The following Rule are the default
> +# rules for the different module type. User can add the customized rules to define the
> +# content of the FFS file.
> +#
> +################################################################################
> +
> +[Rule.Common.SEC]
> + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> + TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + }
> +
> +[Rule.Common.PEI_CORE]
> + FILE PEI_CORE = $(NAMED_GUID) {
> + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING ="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.PEIM]
> + FILE PEIM = $(NAMED_GUID) {
> + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.PEIM.TIANOCOMPRESSED]
> + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
> + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> + }
> +
> +[Rule.Common.DXE_CORE]
> + FILE DXE_CORE = $(NAMED_GUID) {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +
> +[Rule.Common.UEFI_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.DXE_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.DXE_RUNTIME_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.UEFI_APPLICATION]
> + FILE APPLICATION = $(NAMED_GUID) {
> + UI STRING ="$(MODULE_NAME)" Optional
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + }
> +
> +[Rule.Common.UEFI_DRIVER.BINARY]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional |.depex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_APPLICATION.BINARY]
> + FILE APPLICATION = $(NAMED_GUID) {
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> + }
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> new file mode 100644
> index 0000000..1b639e2
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> @@ -0,0 +1,29 @@
> +# LS1043aRdbPkg.dec
> +# LS1043a board package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + PACKAGE_NAME = LS1043aRdbPkg
> + PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +# Supported Module Types:
> +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> new file mode 100644
> index 0000000..6e9e7e0
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -0,0 +1,84 @@
> +# LS1043aRdbPkg.dsc
> +#
> +# LS1043ARDB Board package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + #
> + # Defines for default states. These can be changed on the command line.
> + # -D FLAG=VALUE
> + #
> + PLATFORM_NAME = LS1043aRdbPkg
> + PLATFORM_GUID = 60169ec4-d2b4-44f8-825e-f8684fd42e4f
> + OUTPUT_DIRECTORY = Build/LS1043aRdbPkg
> + FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> +
> +!include ../NxpQoriqLs.dsc
> +!include ../../../Silicon/NXP/LS1043A/LS1043A.dsc
> +
> +[LibraryClasses.common]
> + ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> + BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf
> + SocLib|Silicon/NXP/Chassis/LS1043aSocLib.inf
> + RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
> +
> +[PcdsFixedAtBuild.common]
> +
> + #
> + # LS1043a board Specific PCDs
> + # XX (DRAM - Region 1 2GB)
> + # (NOR - IFC Region 1 512MB)
> + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
> + gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
> + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
> +
> + #
> + # Board Specific Pcds
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
> +
> + #
> + # I2C controller Pcds
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0
> +
> + #
> + # RTC Pcds
> + #
> + gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
> + gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> + #
> + # Architectural Protocols
> + #
> + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> +
> + Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> + Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> +
> + ##
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> new file mode 100644
> index 0000000..fa6510c
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> @@ -0,0 +1,197 @@
> +# LS1043aRdbPkg.fdf
> +#
> +# FLASH layout file for LS1043a board.
> +#
> +# Copyright (c) 2016, Freescale Ltd. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into the Flash Device Image. Each FD section
> +# defines one flash "device" image. A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash" image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +################################################################################
> +
> +[FD.LS1043ARDB_EFI]
> +BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
> +Size = 0x000EC890|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
> +ErasePolarity = 1
> +BlockSize = 0x1
> +NumBlocks = 0xEC890
> +
> +################################################################################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +#
> +################################################################################
> +0x00000000|0x000EC890
> +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> +FV = FVMAIN_COMPACT
> +
> +!include ../FVRules.fdf.inc
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed within a flash
> +# device file. This section also defines order the components and modules are positioned
> +# within the image. The [FV] section consists of define statements, set statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
> +BlockSize = 0x1
> +NumBlocks = 0 # This FV gets compressed so make it just big enough
> +FvAlignment = 8 # FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF MdeModulePkg/Core/Dxe/DxeMain.inf
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +
> + #
> + # PI DXE Drivers producing Architectural Protocols (EFI Services)
> + #
> + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> +
> + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + INF Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> +
> + INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> +
> + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> +
> + #
> + # Multiple Console IO support
> + #
> + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
> +
> + #
> + # Network modules
> + #
> + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
> +!if $(NETWORK_IP6_ENABLE) == TRUE
> + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + INF NetworkPkg/TcpDxe/TcpDxe.inf
> + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> +!else
> + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> +!endif
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + INF FatPkg/FatPei/FatPei.inf
> + INF FatPkg/EnhancedFatDxe/Fat.inf
> +
> + #
> + # UEFI application (Shell Embedded Boot Loader)
> + #
> + INF ShellPkg/Application/Shell/Shell.inf
> +
> + #
> + # Bds
> + #
> + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + INF MdeModulePkg/Application/UiApp/UiApp.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment = 8
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF ArmPlatformPkg/PrePi/PeiUniCore.inf
> +
> + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> + }
> diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc
> new file mode 100644
> index 0000000..5987cd6
> --- /dev/null
> +++ b/Platform/NXP/NxpQoriqLs.dsc
> @@ -0,0 +1,412 @@
> +# @file
> +#
> +# Copyright 2017 NXP.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + #
> + # Defines for default states. These can be changed on the command line.
> + # -D FLAG=VALUE
> + #
> + PLATFORM_VERSION = 0.1
> + DSC_SPECIFICATION = 0x00010005
> + SUPPORTED_ARCHITECTURES = AARCH64
> + BUILD_TARGETS = DEBUG|RELEASE
> + SKUID_IDENTIFIER = DEFAULT
> +
> +[LibraryClasses.common]
> + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
> + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
> + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
> + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
> + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
> + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
> + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
> + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
> + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
> +
> + # Networking Requirements
> + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
> + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
> + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
> + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
> +
> + # ARM GIC400 General Interrupt Driver
> + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
> + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
> + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
> + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
> + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
> + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
> + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
> + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
> + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
> + SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
> + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
> + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
> + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
> + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
> + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
> + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
> + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
> + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
> + DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
> + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
> + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
> + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
> + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
> + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
> + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
> + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
> + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
> + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> +
> +[LibraryClasses.common.SEC]
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
> + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
> + LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
> + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
> + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
> + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
> + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
> +
> + # 1/123 faster than Stm or Vstm version
> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> +
> + # Uncomment to turn on GDB stub in SEC.
> + #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
> +
> +[LibraryClasses.common.PEIM]
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
> + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
> + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> +
> +[LibraryClasses.common.DXE_CORE]
> + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
> + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
> + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
> + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
> +
> +[LibraryClasses.common.DXE_DRIVER]
> + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
> +
> +[LibraryClasses.common.UEFI_APPLICATION]
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
> + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> +
> +[LibraryClasses.common.UEFI_DRIVER]
> + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
> + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
> + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> +
> +[LibraryClasses.common.DXE_RUNTIME_DRIVER]
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> +
> +[LibraryClasses.AARCH64]
> + #
> + # It is not possible to prevent the ARM compiler for generic intrinsic functions.
> + # This library provides the instrinsic functions generate by a given compiler.
> + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
> + #
> + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
> +
> +[BuildOptions]
> + XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7
> + GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a
> + RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu cortex-a9
> +
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
> + GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
> + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +
> +[PcdsFeatureFlag.common]
> + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
> + # It could be set FALSE to save size.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
> + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
> +
> + # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
> + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
> + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
> + gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
> +
> +[PcdsDynamicDefault.common]
> + #
> + # Set video resolution for boot options and for text setup.
> + # PlatformDxe can set the former at runtime.
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
> +
> +[PcdsDynamicHii.common.DEFAULT]
> + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
> +
> +[PcdsFixedAtBuild.common]
> + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
> + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
> + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
> + gArmPlatformTokenSpaceGuid.PcdCoreCount|1 # Only one core
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|2000000
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
> + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
> + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
> + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
> + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
> + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
> +
> +!if $(TARGET) == RELEASE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000000
> +!else
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000044
> +!endif
> +
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +
> + #
> + # Optional feature to help prevent EFI memory map fragments
> + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
> + # Values are in EFI Pages (4K). DXE Core will make sure that
> + # at least this much of each type of memory can be allocated
> + # from a single memory range. This way you only end up with
> + # maximum of two fragements for each type in the memory map
> + # (the memory used, and the free memory that was prereserved
> + # but not used).
> + #
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
> +
> + # Serial Terminal
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
> + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
> +
> + # Size of the region reserved for fixed address allocations (Reserved 32MB)
> + gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x08000000
> + gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x0
> + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x94A00000
> + gArmTokenSpaceGuid.PcdCpuResetAddress|0x94A00000
> +
> + # Timer
> + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
> +
> + # We want to use the Shell Libraries but don't want it to initialise
> + # automatically. We initialise the libraries when the command is called by the
> + # Shell.
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> +
> + # Use the serial console for both ConIn & ConOut
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000
> +!ifdef $(NO_SHELL_PROFILES)
> + gEfiShellPkgTokenSpaceGuid.PcdShellProfileMask|0x00
> +!endif #$(NO_SHELL_PROFILES)
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> + #
> + # SEC
> + #
> + ArmPlatformPkg/PrePi/PeiUniCore.inf
> + MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + }
> +
> + #
> + # DXE
> + #
> + MdeModulePkg/Core/Dxe/DxeMain.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
> + }
> + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + }
> +
> + #
> + # Architectural Protocols
> + #
> + ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> + EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> +
> + # FDT installation
> + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
> + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> + ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
> +
> + #
> + # Networking stack
> + #
> + MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
> +!if $(NETWORK_IP6_ENABLE) == TRUE
> + NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + NetworkPkg/TcpDxe/TcpDxe.inf
> + NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> +!else
> + MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> +!endif
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + FatPkg/FatPei/FatPei.inf
> + FatPkg/EnhancedFatDxe/Fat.inf
> +
> + #
> + # Bds
> + #
> + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + MdeModulePkg/Application/UiApp/UiApp.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
> + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
> + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
> + }
> + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> +
> + #
> + # Example Application
> + #
> + MdeModulePkg/Application/HelloWorld/HelloWorld.inf
> + ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> + ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> + ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> + ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> + ShellPkg/Application/Shell/Shell.inf {
> + <LibraryClasses>
> + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
> +!ifndef $(NO_SHELL_PROFILES)
> + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
> +!endif #$(NO_SHELL_PROFILES)
> + }
> +
> + ##
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dec b/Silicon/NXP/LS1043A/LS1043A.dec
> new file mode 100644
> index 0000000..f14edb2
> --- /dev/null
> +++ b/Silicon/NXP/LS1043A/LS1043A.dec
> @@ -0,0 +1,22 @@
> +# LS1043A.dec
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x00010005
> +
> +[Guids.common]
> + gNxpLs1043ATokenSpaceGuid = {0x6834fe45, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> +
> +[Includes]
> + Include
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc b/Silicon/NXP/LS1043A/LS1043A.dsc
> new file mode 100644
> index 0000000..8395dfd
> --- /dev/null
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc
> @@ -0,0 +1,73 @@
> +# LS1043A.dsc
> +# LS1043A Soc package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +[PcdsDynamicDefault.common]
> +
> + #
> + # ARM General Interrupt Controller
> + gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
> +
> +[PcdsFixedAtBuild.common]
> +
> + #
> + # CCSR Address Space and other attached Memories
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
> + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000
> + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> +
> + #
> + # Big Endian IPs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
> +
> +##
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> new file mode 100644
> index 0000000..a73e9d5
> --- /dev/null
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -0,0 +1,117 @@
> +# @file.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x00010005
> + PACKAGE_VERSION = 0.1
> +
> +[Includes]
> + .
> + Include
> +
> +[Guids.common]
> + gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> +
> +[PcdsFixedAtBuild.common]
> + #
> + # Pcds for I2C Controller
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0|UINT32|0x00000001
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000002
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000003
> +
> + #
> + # Pcds for base address and size
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
> + gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
> + gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
> + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x0|UINT64|0x00000104
> + gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
> + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
> + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
> + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
> + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
> + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0|UINT64|0x0000011A
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0|UINT64|0x0000011B
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0|UINT64|0x0000011C
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0|UINT64|0x0000011D
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x0|UINT64|0x0000011E
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x0|UINT64|0x0000011F
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x00000120
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x00000121
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x00000122
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x00000123
> + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x00000124
> + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x00000125
> + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000126
> + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000127
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000128
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129
> + gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A
> +
> + #
> + # IFC PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
> +
> + #
> + # NV Pcd
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
> + gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211
> +
> + #
> + # Platform PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
> +
> + #
> + # Clock PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
> + gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1
> +
> + #
> + # Pcds to support Big Endian IPs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
> + gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|FALSE|BOOLEAN|0x00000313
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 03/39] SocLib : Add support for initialization of peripherals
2018-04-18 15:12 ` Leif Lindholm
@ 2018-04-18 16:38 ` Meenakshi Aggarwal
2018-04-18 18:15 ` Leif Lindholm
0 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-04-18 16:38 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi
Hi Leif,
Thanks for review, responses inlined.
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Wednesday, April 18, 2018 8:42 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms 03/39] SocLib : Add support for
> initialization of peripherals
>
> On Fri, Feb 16, 2018 at 02:19:59PM +0530, Meenakshi wrote:
> > From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> >
> > Add SocInit function that initializes peripherals
> > and print board and soc information.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> > ---
> > Silicon/NXP/Chassis/Chassis.c | 388
> ++++++++++++++++++++++++++++++
> > Silicon/NXP/Chassis/Chassis.h | 144 +++++++++++
> > Silicon/NXP/Chassis/Chassis2/Chassis2.dec | 19 ++
> > Silicon/NXP/Chassis/Chassis2/SerDes.h | 68 ++++++
> > Silicon/NXP/Chassis/Chassis2/Soc.c | 172 +++++++++++++
> > Silicon/NXP/Chassis/Chassis2/Soc.h | 367
> ++++++++++++++++++++++++++++
> > Silicon/NXP/Chassis/LS1043aSocLib.inf | 47 ++++
> > Silicon/NXP/Chassis/SerDes.c | 271 +++++++++++++++++++++
> > Silicon/NXP/Include/Bitops.h | 179 ++++++++++++++
> > Silicon/NXP/LS1043A/Include/SocSerDes.h | 55 +++++
> > 10 files changed, 1710 insertions(+)
> > create mode 100644 Silicon/NXP/Chassis/Chassis.c
> > create mode 100644 Silicon/NXP/Chassis/Chassis.h
> > create mode 100644 Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> > create mode 100644 Silicon/NXP/Chassis/Chassis2/SerDes.h
> > create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.c
> > create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.h
> > create mode 100644 Silicon/NXP/Chassis/LS1043aSocLib.inf
> > create mode 100644 Silicon/NXP/Chassis/SerDes.c
> > create mode 100644 Silicon/NXP/Include/Bitops.h
> > create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
> >
> > diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c
> > new file mode 100644
> > index 0000000..9f2928b
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis/Chassis.c
> > @@ -0,0 +1,388 @@
> > +/** @file
> > + SoC specific Library containg functions to initialize various SoC
> components
> > +
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials
> > + are licensed and made available under the terms and conditions of the
> BSD License
> > + which accompanies this distribution. The full text of the license may be
> found at
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C9a50d6
> e105bc4080493208d5a53ed014%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636596611590418850&sdata=jZ0%2B2I7ul%2F8Te5ASAsABuk4O0LR
> 6%2Bn8G8avnxAvcF9k%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#include <Base.h>
> > +#include <Library/BaseLib.h>
> > +#include <Library/BeIoLib.h>
> > +#include <Library/DebugLib.h>
> > +#include <Library/IoLib.h>
> > +#include <Library/PcdLib.h>
> > +#include <Library/PrintLib.h>
> > +#include <Library/SerialPortLib.h>
> > +
> > +#include <Soc.h>
> > +
> > +#include "Chassis.h"
> > +
> > +UINT32
> > +EFIAPI
> > +GurRead (
> > + IN UINTN Address
> > + )
> > +{
> > + if (FixedPcdGetBool (PcdGurBigEndian)) {
> > + return BeMmioRead32 (Address);
> > + } else {
> > + return MmioRead32 (Address);
> > + }
> > +}
>
> So, since this pattern is being repeated in multiple modules, I think
> it would make sense to have (for now) an NXP-specific helper library
> to return a struct of function pointers accessing either
>
> I.e. something like (in a header)
>
> typedef struct _MMIO_OPERATIONS {
> MMIO_WRITE_8 Write8;
> ...
> } MMIO_OPERATIONS;
>
> and then in the .c file:
>
> STATIC MMIO_OPERATIONS SwappingFunctions = {
> SwapMmioWrite8,
> ...
> };
>
> STATIC MMIO_OPERATIONS NonSwappingFunctions = {
> MmioWrite8,
> ...
> };
>
> MMIO_OPERATIONS *GetMmioOperationsStructure (BOOL BigEndian)
> {
> if (BigEndian) {
> return &SwappingFunctions;
> else {
> return &NonSwappingFunctions;
> }
> }
>
> To be used in _this_ file as
>
> STATIC MMIO_OPERATIONS mGurOps;
>
> Initialized in some sort of Initialize() function as
> mGurOps = GetMmioOperationsStructure (FixedPcdGetBool
> (PcdGurBigEndian));
>
> This will then let us fix up whatever the final core function names
> end up being in a single place.
>
> This feedback applies also to the resubmitted watchdog driver (but
> should be a very minor change there).
>
Okay, sounds a good idea to me.
> > +
> > +/*
> > + * Structure to list available SOCs.
> > + */
> > +STATIC CPU_TYPE CpuTypeList[] = {
> > + CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
> > +};
> > +
> > +/*
> > + * Return the number of bits set
> > + */
> > +STATIC
> > +inline
> > +UINTN
> > +CountSetBits (
>
> This helper function is only used in one location.
> If there is enough in this set to break out into a generically useful
> helper library (for later consideration for inclusion in edk2 for
> example), please do so. Otherwise, please move this inline in the
> (otherwise near-empty) calling function.
>
Okay, will see what is more approproate.
> > + IN UINTN Num
> > + )
> > +{
> > + UINTN Count;
> > +
> > + Count = 0;
> > +
> > + while (Num) {
> > + Count += Num & 1;
> > + Num >>= 1;
> > + }
> > +
> > + return Count;
> > +}
> > +
> > +/*
> > + * Return the type of initiator (core or hardware accelerator)
> > + */
> > +UINT32
> > +InitiatorType (
> > + IN UINT32 Cluster,
> > + IN UINTN InitId
> > + )
> > +{
> > + CCSR_GUR *GurBase;
> > + UINT32 Idx;
> > + UINT32 Type;
> > +
> > + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> > + Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
> > + Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
> > +
> > + if (Type & TP_ITYP_AV_MASK) {
> > + return Type;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/*
> > + * Return the mask for number of cores on this SOC.
> > + */
> > +UINT32
> > +CpuMask (
> > + VOID
> > + )
> > +{
> > + CCSR_GUR *GurBase;
> > + UINTN ClusterIndex;
> > + UINTN Count;
> > + UINT32 Cluster;
> > + UINT32 Type;
> > + UINT32 Mask;
> > + UINTN InitiatorIndex;
> > +
> > + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> > + ClusterIndex = 0;
> > + Count = 0;
> > + Mask = 0;
> > +
> > + do {
> > + Cluster = GurRead ((UINTN)&GurBase-
> >TpCluster[ClusterIndex].Lower);
> > + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER;
> InitiatorIndex++) {
> > + Type = InitiatorType (Cluster, InitiatorIndex);
> > + if (Type) {
> > + if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM)
> > + Mask |= 1 << Count;
>
> Always use braces {} with if.
>
yes
> > + Count++;
> > + }
> > + }
> > + ClusterIndex++;
> > + } while (CHECK_CLUSTER (Cluster));
> > +
> > + return Mask;
> > +}
> > +
> > +/*
> > + * Return the number of cores on this SOC.
> > + */
> > +UINTN
> > +CpuNumCores (
> > + VOID
> > + )
> > +{
> > + return CountSetBits (CpuMask ());
>
> Spurious indentation. (Should be 2 spaces.)
>
> > +}
> > +
> > +/*
> > + * Return the type of core i.e. A53, A57 etc of inputted
> > + * core number.
> > + */
> > +UINT32
> > +QoriqCoreToType (
> > + IN UINTN Core
> > + )
> > +{
> > + CCSR_GUR *GurBase;
> > + UINTN ClusterIndex;
> > + UINTN Count;
> > + UINT32 Cluster;
> > + UINT32 Type;
> > + UINTN InitiatorIndex;
> > +
> > + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> > + ClusterIndex = 0;
> > + Count = 0;
> > +
> > + do {
> > + Cluster = GurRead ((UINTN)&GurBase-
> >TpCluster[ClusterIndex].Lower);
> > + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER;
> InitiatorIndex++) {
> > + Type = InitiatorType (Cluster, InitiatorIndex);
> > + if (Type) {
> > + if (Count == Core)
> > + return Type;
>
> Always braces with if.
>
> > + Count++;
> > + }
> > + }
> > + ClusterIndex++;
> > + } while (CHECK_CLUSTER (Cluster));
> > +
> > + return -1; /* cannot identify the cluster */
>
> Please use a #define for return value.
>
ok
> > +}
> > +
> > +/*
> > + * Print CPU information
> > + */
> > +VOID
> > +PrintCpuInfo (
> > + VOID
> > + )
> > +{
> > + SYS_INFO SysInfo;
> > + UINTN CoreIndex;
> > + UINTN Core;
> > + UINT32 Type;
> > + CHAR8 Buffer[100];
> > + UINTN CharCount;
> > +
> > + GetSysInfo (&SysInfo);
> > + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Clock Configuration:");
> > + SerialPortWrite ((UINT8 *) Buffer, CharCount);
>
> Why SerialPortWrite instead of Print? (Question for throughout patch.)
>
No particular reason, will replace it.
> > +
> > + ForEachCpu (CoreIndex, Core, CpuNumCores (), CpuMask ()) {
> > + if (!(CoreIndex % 3)) {
> > + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n ");
> > + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> > + }
> > +
> > + Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
> > + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "CPU%d(%a):%-4d MHz
> ", Core,
> > + Type == TY_ITYP_VERSION_A7 ? "A7 " :
> > + (Type == TY_ITYP_VERSION_A53 ? "A53" :
> > + (Type == TY_ITYP_VERSION_A57 ? "A57" :
> > + (Type == TY_ITYP_VERSION_A72 ? "A72" : " Unknown Core "))),
>
> That's a lot more nested than I like my ternaries.
> Can you rewrite as a switch statement that sets a pointer.
>
Ok
> > + SysInfo.FreqProcessor[Core] / MEGA_HZ);
>
> Please use either MEGAHERTZ or MHZ.
>
ok
> > + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> > + }
> > +
> > + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n Bus: %-4d MHz
> ",
> > + SysInfo.FreqSystemBus / MEGA_HZ);
> > + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> > + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "DDR: %-4d MT/s",
> > + SysInfo.FreqDdrBus / MEGA_HZ);
> > + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> > +
> > + if (SysInfo.FreqFman[0] != 0) {
> > + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n FMAN: %-4d
> MHz ",
> > + SysInfo.FreqFman[0] / MEGA_HZ);
> > + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> > + }
> > +
> > + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n");
> > + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> > +}
> > +
> > +/*
> > + * Return system bus frequency
> > + */
> > +UINT64
> > +GetBusFrequency (
> > + VOID
> > + )
> > +{
> > + SYS_INFO SocSysInfo;
> > +
> > + GetSysInfo (&SocSysInfo);
> > +
> > + return SocSysInfo.FreqSystemBus;
> > +}
> > +
> > +/*
> > + * Return SDXC bus frequency
> > + */
> > +UINT64
> > +GetSdxcFrequency (
> > + VOID
> > + )
> > +{
> > + SYS_INFO SocSysInfo;
> > +
> > + GetSysInfo (&SocSysInfo);
> > +
> > + return SocSysInfo.FreqSdhc;
> > +}
> > +
> > +/*
> > + * Print Soc information
> > + */
> > +VOID
> > +PrintSoc (
> > + VOID
> > + )
> > +{
> > + CHAR8 Buf[16];
> > + CCSR_GUR *GurBase;
> > + UINTN Count;
> > + UINTN Svr;
> > + UINTN Ver;
> > +
> > + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> > +
> > + Buf[0] = L'\0';
> > + Svr = GurRead ((UINTN)&GurBase->Svr);
> > + Ver = SVR_SOC_VER (Svr);
> > +
> > + for (Count = 0; Count < ARRAY_SIZE (CpuTypeList); Count++)
> > + if ((CpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
> > + AsciiStrCpy (Buf, (CONST CHAR8 *)CpuTypeList[Count].Name);
> > +
> > + if (IS_E_PROCESSOR (Svr)) {
> > + AsciiStrCat (Buf, (CONST CHAR8 *)"E");
> > + }
> > + break;
> > + }
> > +
> > + if (Count == ARRAY_SIZE (CpuTypeList)) {
> > + AsciiStrCpy (Buf, (CONST CHAR8 *)"unknown");
> > + }
> > +
> > + DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
> > + Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
> > +
> > + return;
> > +}
> > +
> > +/*
> > + * Dump RCW (Reset Control Word) on console
> > + */
> > +VOID
> > +PrintRCW (
> > + VOID
> > + )
> > +{
> > + CCSR_GUR *Base;
> > + UINTN Count;
> > + CHAR8 Buffer[100];
> > + UINTN CharCount;
> > +
> > + Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> > +
> > + /*
> > + * Display the RCW, so that no one gets confused as to what RCW
> > + * we're actually using for this boot.
> > + */
> > +
> > + CharCount = AsciiSPrint (Buffer, sizeof (Buffer),
> > + "Reset Configuration Word (RCW):");
> > + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> > + for (Count = 0; Count < ARRAY_SIZE(Base->RcwSr); Count++) {
> > + UINT32 Rcw = BeMmioRead32((UINTN)&Base->RcwSr[Count]);
> > +
> > + if ((Count % 4) == 0) {
> > + CharCount = AsciiSPrint (Buffer, sizeof (Buffer),
> > + "\n %08x:", Count * 4);
> > + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> > + }
> > +
> > + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), " %08x", Rcw);
> > + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> > + }
> > +
> > + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n");
> > + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> > +}
> > +
> > +/*
> > + * Setup SMMU in bypass mode
> > + * and also set its pagesize
> > + */
> > +VOID
> > +SmmuInit (
> > + VOID
> > + )
> > +{
> > + UINT32 Value;
> > +
> > + /* set pagesize as 64K and ssmu-500 in bypass mode */
> > + Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) |
> SACR_PAGESIZE_MASK);
> > + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> > +
> > + Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) |
> SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> > + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> > +
> > + Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) |
> SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> > + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> > +}
> > +
> > +/*
> > + * Return current Soc Name form CpuTypeList
> > + */
> > +CHAR8 *
> > +GetSocName (
> > + VOID
> > + )
> > +{
> > + UINT8 Count;
> > + UINTN Svr;
> > + UINTN Ver;
> > + CCSR_GUR *GurBase;
> > +
> > + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> > +
> > + Svr = GurRead ((UINTN)&GurBase->Svr);
> > + Ver = SVR_SOC_VER (Svr);
> > +
> > + for (Count = 0; Count < ARRAY_SIZE (CpuTypeList); Count++) {
> > + if ((CpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
> > + return (CHAR8 *)CpuTypeList[Count].Name;
> > + }
> > + }
> > +
> > + return NULL;
> > +}
> > diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h
> > new file mode 100644
> > index 0000000..4bdb4d0
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis/Chassis.h
> > @@ -0,0 +1,144 @@
> > +/** @file
> > +* Header defining the Base addresses, sizes, flags etc for chassis 1
> > +*
> > +* Copyright 2017 NXP
> > +*
> > +* This program and the accompanying materials
> > +* are licensed and made available under the terms and conditions of the
> BSD License
> > +* which accompanies this distribution. The full text of the license may be
> found at
> > +*
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C9a50d6
> e105bc4080493208d5a53ed014%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636596611590418850&sdata=jZ0%2B2I7ul%2F8Te5ASAsABuk4O0LR
> 6%2Bn8G8avnxAvcF9k%3D&reserved=0
> > +*
> > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +*
> > +**/
> > +
> > +#ifndef __CHASSIS_H__
> > +#define __CHASSIS_H__
> > +
> > +#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
> > +#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
> > +#define TP_ITYP_TYPE_ARM 0x0
> > +#define TP_ITYP_TYPE_PPC 0x1
> > +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
> > +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
> > +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
> > +#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version
> */
> > +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
> > +#define TP_INIT_PER_CLUSTER 4
> > +
> > +#define TY_ITYP_VERSION_A7 0x1
> > +#define TY_ITYP_VERSION_A53 0x2
> > +#define TY_ITYP_VERSION_A57 0x3
> > +#define TY_ITYP_VERSION_A72 0x4
> > +
> > +STATIC
> > +inline
> > +UINTN
> > +CpuMaskNext (
> > + IN UINTN Cpu,
> > + IN UINTN Mask
> > + )
> > +{
> > + for (Cpu++; !((1 << Cpu) & Mask); Cpu++)
> > + ;
> > +
> > + return Cpu;
> > +}
> > +
> > +#define ForEachCpu(Iter, Cpu, NumCpus, Mask) \
> > + for (Iter = 0, Cpu = CpuMaskNext(-1, Mask); \
> > + Iter < NumCpus; \
> > + Iter++, Cpu = CpuMaskNext(Cpu, Mask)) \
> > +
> > +#define CPU_TYPE_ENTRY(N, V, NC) \
> > + { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
> > +
> > +#define SVR_WO_E 0xFFFFFE
> > +#define SVR_LS1043A 0x879200
> > +
> > +#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> > +#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> > +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
> > +#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
> > +
> > +#define MEGA_HZ 1000000
> > +
> > +typedef struct {
> > + CHAR8 Name[16];
> > + UINT32 SocVer;
> > + UINT32 NumCores;
> > +} CPU_TYPE;
> > +
> > +typedef struct {
> > + UINTN CpuClk; /* CPU clock in Hz! */
> > + UINTN BusClk;
> > + UINTN MemClk;
> > + UINTN PciClk;
> > + UINTN SdhcClk;
> > +} SOC_CLOCK_INFO;
> > +
> > +/*
> > + * Print Soc information
> > + */
> > +VOID
> > +PrintSoc (
> > + VOID
> > + );
> > +
> > +/*
> > + * Initialize Clock structure
> > + */
> > +VOID
> > +ClockInit (
> > + VOID
> > + );
> > +
> > +/*
> > + * Setup SMMU in bypass mode
> > + * and also set its pagesize
> > + */
> > +VOID
> > +SmmuInit (
> > + VOID
> > + );
> > +
> > +/*
> > + * Print CPU information
> > + */
> > +VOID
> > +PrintCpuInfo (
> > + VOID
> > + );
> > +
> > +/*
> > + * Dump RCW (Reset Control Word) on console
> > + */
> > +VOID
> > +PrintRCW (
> > + VOID
> > + );
> > +
> > +UINT32
> > +InitiatorType (
> > + IN UINT32 Cluster,
> > + IN UINTN InitId
> > + );
> > +
> > +/*
> > + * Return the mask for number of cores on this SOC.
> > + */
> > +UINT32
> > +CpuMask (
> > + VOID
> > + );
> > +
> > +/*
> > + * Return the number of cores on this SOC.
> > + */
> > +UINTN
> > +CpuNumCores (
> > + VOID
> > + );
> > +
> > +#endif /* __CHASSIS_H__ */
> > diff --git a/Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> b/Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> > new file mode 100644
> > index 0000000..cf41b3c
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> > @@ -0,0 +1,19 @@
> > +# @file
> > +#
> > +# Copyright 2017 NXP
> > +#
> > +# This program and the accompanying materials are licensed and made
> available under
> > +# the terms and conditions of the BSD License which accompanies this
> distribution.
> > +# The full text of the license may be found at
> > +#
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C9a50d6
> e105bc4080493208d5a53ed014%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636596611590418850&sdata=jZ0%2B2I7ul%2F8Te5ASAsABuk4O0LR
> 6%2Bn8G8avnxAvcF9k%3D&reserved=0
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +#
> > +#
> > +
> > +[Defines]
> > + DEC_SPECIFICATION = 0x00010005
>
> 0x0001001a
>
OK
> > +
> > +[Includes]
> > + .
>
> Hmm. In general, this appears to be using the .dec file simply to
> tweak which "Soc.h" and "SerDes.h" file gets included in
> Silicon/NXP/Chassis/Chassis.c and Silicon/NXP/Chassis/SerDes.c
>
> First of all, a .dec is a package declaration file, and that is not
> what is being created here. So this doesn't follow expected TianoCore
> layout.
>
> Secondly, there appears to be some quite spurious differences between
> Chassis2/Soc.h and Chassis3/Soc.h: difference in indentation,
> differences in comment style, use of macros for array sizes in struct
> definitions in one and hardcoded in the other.
> Can this be cleaned up so that a
> diff -u Silicon/NXP/Chassis/Chassis2/Soc.h
> Silicon/NXP/Chassis/Chassis3/Soc.h
> describes the differences between the platforms rather than the
> differences in coding style?
>
> Finally, can Silicon/NXP/Chassis be moved across to
> Silicon/NXP/Library/SocLib, with include files under
> Silicon/NXP/Include/{Chassis2|Chassis3}?
> The different .inf files can then set a -D CHASSIS_MODEL=Chassis2 or
> -D CHASSIS_MODEL=Chassis3 in GCC:*_*_*_CC_FLAGS [BuildOptions]
> with affected source files referring to them as
> #include <Library/CHASSIS_MODEL/Soc.h>
> and
> #include <Library/CHASSIS_MODEL/SerDes.h>
> ?
>
Hmm, will try to implement same.
> > diff --git a/Silicon/NXP/Chassis/Chassis2/SerDes.h
> b/Silicon/NXP/Chassis/Chassis2/SerDes.h
> > new file mode 100644
> > index 0000000..4c874aa
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis/Chassis2/SerDes.h
> > @@ -0,0 +1,68 @@
> > +/** SerDes.h
> > + The Header file of SerDes Module for Chassis 2
> > +
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials
> > + are licensed and made available under the terms and conditions of the
> BSD License
> > + which accompanies this distribution. The full text of the license may be
> found
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C9a50d6
> e105bc4080493208d5a53ed014%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636596611590418850&sdata=jZ0%2B2I7ul%2F8Te5ASAsABuk4O0LR
> 6%2Bn8G8avnxAvcF9k%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#ifndef __SERDES_H__
> > +#define __SERDES_H__
> > +
> > +#include <Uefi/UefiBaseType.h>
> > +
> > +#define SRDS_MAX_LANES 4
> > +
> > +typedef enum {
> > + NONE = 0,
> > + PCIE1,
> > + PCIE2,
> > + PCIE3,
> > + SATA,
> > + SGMII_FM1_DTSEC1,
> > + SGMII_FM1_DTSEC2,
> > + SGMII_FM1_DTSEC5,
> > + SGMII_FM1_DTSEC6,
> > + SGMII_FM1_DTSEC9,
> > + SGMII_FM1_DTSEC10,
> > + QSGMII_FM1_A,
> > + XFI_FM1_MAC9,
> > + XFI_FM1_MAC10,
> > + SGMII_2500_FM1_DTSEC2,
> > + SGMII_2500_FM1_DTSEC5,
> > + SGMII_2500_FM1_DTSEC9,
> > + SGMII_2500_FM1_DTSEC10,
> > + SERDES_PRTCL_COUNT
> > +} SERDES_PROTOCOL;
> > +
> > +typedef enum {
> > + SRDS_1 = 0,
> > + SRDS_2,
> > + SRDS_MAX_NUM
> > +} SERDES_NUMBER;
> > +
> > +typedef struct {
> > + UINT16 Protocol;
> > + UINT8 SrdsLane[SRDS_MAX_LANES];
> > +} SERDES_CONFIG;
> > +
> > +typedef VOID
> > +(*SERDES_PROBE_LANES_CALLBACK) (
> > + IN SERDES_PROTOCOL LaneProtocol,
> > + IN VOID *Arg
> > + );
> > +
> > +VOID
> > +SerDesProbeLanes(
> > + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> > + IN VOID *Arg
> > + );
> > +
> > +#endif /* __SERDES_H */
> > diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c
> b/Silicon/NXP/Chassis/Chassis2/Soc.c
> > new file mode 100644
> > index 0000000..7f9f963
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis/Chassis2/Soc.c
> > @@ -0,0 +1,172 @@
> > +/** @Soc.c
> > + SoC specific Library containg functions to initialize various SoC
> components
> > +
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials
> > + are licensed and made available under the terms and conditions of the
> BSD License
> > + which accompanies this distribution. The full text of the license may be
> found at
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C9a50d6
> e105bc4080493208d5a53ed014%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636596611590418850&sdata=jZ0%2B2I7ul%2F8Te5ASAsABuk4O0LR
> 6%2Bn8G8avnxAvcF9k%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#include <Base.h>
> > +#include <Chassis.h>
> > +#include <Library/BaseLib.h>
> > +#include <Library/BaseMemoryLib/MemLibInternals.h>
> > +#include <Library/DebugLib.h>
> > +#include <Library/IoLib.h>
> > +#include <Library/PcdLib.h>
> > +#include <Library/PrintLib.h>
> > +#include <Library/SerialPortLib.h>
> > +
> > +#include "Soc.h"
> > +
> > +/**
> > + Calculate the frequency of various controllers and
> > + populate the passed structure with frequuencies.
> > +
> > + @param PtrSysInfo Input structure to populate with
> > + frequencies.
> > +**/
> > +VOID
> > +GetSysInfo (
> > + OUT SYS_INFO *PtrSysInfo
> > + )
> > +{
> > + CCSR_GUR *GurBase;
> > + CCSR_CLOCK *ClkBase;
> > + UINTN CpuIndex;
> > + UINT32 TempRcw;
> > + UINT32 CPllSel;
> > + UINT32 CplxPll;
> > + CONST UINT8 CoreCplxPll[8] = {
> > + [0] = 0, /* CC1 PPL / 1 */
> > + [1] = 0, /* CC1 PPL / 2 */
> > + [4] = 1, /* CC2 PPL / 1 */
> > + [5] = 1, /* CC2 PPL / 2 */
> > + };
> > +
> > + CONST UINT8 CoreCplxPllDivisor[8] = {
> > + [0] = 1, /* CC1 PPL / 1 */
> > + [1] = 2, /* CC1 PPL / 2 */
> > + [4] = 1, /* CC2 PPL / 1 */
> > + [5] = 2, /* CC2 PPL / 2 */
> > + };
> > +
> > + UINTN PllCount;
> > + UINTN FreqCPll[NUM_CC_PLLS];
> > + UINTN PllRatio[NUM_CC_PLLS];
> > + UINTN SysClk;
> > +
> > + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> > + ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
> > + SysClk = CLK_FREQ;
> > +
> > + SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> > +
> > + PtrSysInfo->FreqSystemBus = SysClk;
> > + PtrSysInfo->FreqDdrBus = SysClk;
> > +
> > + //
> > + // selects the platform clock:SYSCLK ratio and calculate
> > + // system frequency
> > + //
> > + PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0])
> >>
> > + CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> > + CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> > + //
> > + // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
> > + //
> > + PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> > + CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
> > + CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
> > +
> > + for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
> > + PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase-
> >PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
> > + if (PllRatio[PllCount] > 4) {
> > + FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
> > + } else {
> > + FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
> > + }
> > + }
> > +
> > + //
> > + // Calculate Core frequency
> > + //
> > + for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
> > + CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >>
> 27) & 0xf;
> > + CplxPll = CoreCplxPll[CPllSel];
> > +
> > + PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] /
> CoreCplxPllDivisor[CPllSel];
> > + }
> > +
> > + //
> > + // Calculate FMAN frequency
> > + //
> > + TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
> > + switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >>
> HWA_CGA_M1_CLK_SHIFT) {
> > + case 2:
> > + PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
> > + break;
> > + case 3:
> > + PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
> > + break;
> > + case 4:
> > + PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
> > + break;
> > + case 5:
> > + PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
> > + break;
> > + case 6:
> > + PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
> > + break;
> > + case 7:
> > + PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
> > + break;
> > + default:
> > + DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
> > + break;
> > + }
> > + PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32
> (PcdPlatformFreqDiv);
> > + PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32
> (PcdPlatformFreqDiv);
> > +}
> > +
> > +/**
> > + Function to initialize SoC specific constructs
> > + CPU Info
> > + SoC Personality
> > + Board Personality
> > + RCW prints
> > + **/
> > +VOID
> > +SocInit (
> > + VOID
> > + )
> > +{
> > + CHAR8 Buffer[100];
> > + UINTN CharCount;
> > +
> > + SmmuInit ();
> > +
> > + //
> > + // Early init serial Port to get board information.
> > + //
> > + SerialPortInitialize ();
> > + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\nUEFI firmware
> (version %s built at %a on %a)\n\r",
> > + (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__,
> __DATE__);
> > + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> > +
> > + PrintCpuInfo ();
> > +
> > + //
> > + // Print Reset control Word
> > + //
> > + PrintRCW ();
> > + PrintSoc ();
> > +
> > + return;
> > +}
> > diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.h
> b/Silicon/NXP/Chassis/Chassis2/Soc.h
> > new file mode 100644
> > index 0000000..10e99ab
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis/Chassis2/Soc.h
> > @@ -0,0 +1,367 @@
> > +/** Soc.h
> > +* Header defining the Base addresses, sizes, flags etc for chassis 1
> > +*
> > +* Copyright 2017 NXP
> > +*
> > +* This program and the accompanying materials
> > +* are licensed and made available under the terms and conditions of the
> BSD License
> > +* which accompanies this distribution. The full text of the license may be
> found at
> > +*
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C9a50d6
> e105bc4080493208d5a53ed014%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636596611590418850&sdata=jZ0%2B2I7ul%2F8Te5ASAsABuk4O0LR
> 6%2Bn8G8avnxAvcF9k%3D&reserved=0
> > +*
> > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +*
> > +**/
> > +
> > +#ifndef __SOC_H__
> > +#define __SOC_H__
> > +
> > +#define HWA_CGA_M1_CLK_SEL 0xe0000000
> > +#define HWA_CGA_M1_CLK_SHIFT 29
> > +
> > +#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask
> */
> > +#define NUM_CC_PLLS 2
> > +#define CLK_FREQ 100000000
> > +#define MAX_CPUS 4
> > +#define NUM_FMAN 1
> > +#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK)
> == 0x0)
> > +
> > +/* RCW SERDES MACRO */
> > +#define RCWSR_INDEX 4
> > +#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
> > +#define RCWSR_SRDS1_PRTCL_SHIFT 16
> > +#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
> > +#define RCWSR_SRDS2_PRTCL_SHIFT 0
> > +
> > +/* SMMU Defintions */
> > +#define SMMU_BASE_ADDR 0x09000000
> > +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> > +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> > +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> > +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> > +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> > +
> > +#define SCR0_USFCFG_MASK 0x00000400
> > +#define SCR0_CLIENTPD_MASK 0x00000001
> > +#define SACR_PAGESIZE_MASK 0x00010000
> > +#define IDR1_PAGESIZE_MASK 0x80000000
> > +
> > +typedef struct {
> > + UINTN FreqProcessor[MAX_CPUS];
> > + UINTN FreqSystemBus;
> > + UINTN FreqDdrBus;
> > + UINTN FreqLocalBus;
> > + UINTN FreqSdhc;
> > + UINTN FreqFman[NUM_FMAN];
> > + UINTN FreqQman;
> > +} SYS_INFO;
> > +
> > +/* Device Configuration and Pin Control */
> > +typedef struct {
> > + UINT32 PorSr1; /* POR status 1 */
> > +#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
> > + UINT32 PorSr2; /* POR status 2 */
> > + UINT8 Res008[0x20-0x8];
> > + UINT32 GppOrCr1; /* General-purpose POR configuration */
> > + UINT32 GppOrCr2;
> > + UINT32 DcfgFuseSr; /* Fuse status register */
> > + UINT8 Res02c[0x70-0x2c];
> > + UINT32 DevDisr; /* Device disable control */
> > + UINT32 DevDisr2; /* Device disable control 2 */
> > + UINT32 DevDisr3; /* Device disable control 3 */
> > + UINT32 DevDisr4; /* Device disable control 4 */
> > + UINT32 DevDisr5; /* Device disable control 5 */
> > + UINT32 DevDisr6; /* Device disable control 6 */
> > + UINT32 DevDisr7; /* Device disable control 7 */
> > + UINT8 Res08c[0x94-0x8c];
> > + UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
> > + UINT32 CoreDisrL; /* lower portion for support of 64 cores */
> > + UINT8 Res09c[0xa0-0x9c];
> > + UINT32 Pvr; /* Processor version */
> > + UINT32 Svr; /* System version */
> > + UINT32 Mvr; /* Manufacturing version */
> > + UINT8 Res0ac[0xb0-0xac];
> > + UINT32 RstCr; /* Reset control */
> > + UINT32 RstRqPblSr; /* Reset request preboot loader status */
> > + UINT8 Res0b8[0xc0-0xb8];
> > + UINT32 RstRqMr1; /* Reset request mask */
> > + UINT8 Res0c4[0xc8-0xc4];
> > + UINT32 RstRqSr1; /* Reset request status */
> > + UINT8 Res0cc[0xd4-0xcc];
> > + UINT32 RstRqWdTmrL; /* Reset request WDT mask */
> > + UINT8 Res0d8[0xdc-0xd8];
> > + UINT32 RstRqWdtSrL; /* Reset request WDT status */
> > + UINT8 Res0e0[0xe4-0xe0];
> > + UINT32 BrrL; /* Boot release */
> > + UINT8 Res0e8[0x100-0xe8];
> > + UINT32 RcwSr[16]; /* Reset control word status */
> > +#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
> > +#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
> > +#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
> > +#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
> > + UINT8 Res140[0x200-0x140];
> > + UINT32 ScratchRw[4]; /* Scratch Read/Write */
> > + UINT8 Res210[0x300-0x210];
> > + UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
> > + UINT8 Res310[0x400-0x310];
> > + UINT32 CrstSr[12];
> > + UINT8 Res430[0x500-0x430];
> > + /* PCI Express n Logical I/O Device Number register */
> > + UINT32 DcfgCcsrPex1LiodNr;
> > + UINT32 DcfgCcsrPex2LiodNr;
> > + UINT32 DcfgCcsrPex3LiodNr;
> > + UINT32 DcfgCcsrPex4LiodNr;
> > + /* RIO n Logical I/O Device Number register */
> > + UINT32 DcfgCcsrRio1LiodNr;
> > + UINT32 DcfgCcsrRio2LiodNr;
> > + UINT32 DcfgCcsrRio3LiodNr;
> > + UINT32 DcfgCcsrRio4LiodNr;
> > + /* USB Logical I/O Device Number register */
> > + UINT32 DcfgCcsrUsb1LiodNr;
> > + UINT32 DcfgCcsrUsb2LiodNr;
> > + UINT32 DcfgCcsrUsb3LiodNr;
> > + UINT32 DcfgCcsrUsb4LiodNr;
> > + /* SD/MMC Logical I/O Device Number register */
> > + UINT32 DcfgCcsrSdMmc1LiodNr;
> > + UINT32 DcfgCcsrSdMmc2LiodNr;
> > + UINT32 DcfgCcsrSdMmc3LiodNr;
> > + UINT32 DcfgCcsrSdMmc4LiodNr;
> > + /* RIO Message Unit Logical I/O Device Number register */
> > + UINT32 DcfgCcsrRiomaintLiodNr;
> > + UINT8 Res544[0x550-0x544];
> > + UINT32 SataLiodNr[4];
> > + UINT8 Res560[0x570-0x560];
> > + UINT32 DcfgCcsrMisc1LiodNr;
> > + UINT32 DcfgCcsrMisc2LiodNr;
> > + UINT32 DcfgCcsrMisc3LiodNr;
> > + UINT32 DcfgCcsrMisc4LiodNr;
> > + UINT32 DcfgCcsrDma1LiodNr;
> > + UINT32 DcfgCcsrDma2LiodNr;
> > + UINT32 DcfgCcsrDma3LiodNr;
> > + UINT32 DcfgCcsrDma4LiodNr;
> > + UINT32 DcfgCcsrSpare1LiodNr;
> > + UINT32 DcfgCcsrSpare2LiodNr;
> > + UINT32 DcfgCcsrSpare3LiodNr;
> > + UINT32 DcfgCcsrSpare4LiodNr;
> > + UINT8 Res5a0[0x600-0x5a0];
> > + UINT32 DcfgCcsrPblSr;
> > + UINT32 PamuBypENr;
> > + UINT32 DmaCr1;
> > + UINT8 Res60c[0x610-0x60c];
> > + UINT32 DcfgCcsrGenSr1;
> > + UINT32 DcfgCcsrGenSr2;
> > + UINT32 DcfgCcsrGenSr3;
> > + UINT32 DcfgCcsrGenSr4;
> > + UINT32 DcfgCcsrGenCr1;
> > + UINT32 DcfgCcsrGenCr2;
> > + UINT32 DcfgCcsrGenCr3;
> > + UINT32 DcfgCcsrGenCr4;
> > + UINT32 DcfgCcsrGenCr5;
> > + UINT32 DcfgCcsrGenCr6;
> > + UINT32 DcfgCcsrGenCr7;
> > + UINT8 Res63c[0x658-0x63c];
> > + UINT32 DcfgCcsrcGenSr1;
> > + UINT32 DcfgCcsrcGenSr0;
> > + UINT8 Res660[0x678-0x660];
> > + UINT32 DcfgCcsrcGenCr1;
> > + UINT32 DcfgCcsrcGenCr0;
> > + UINT8 Res680[0x700-0x680];
> > + UINT32 DcfgCcsrSrIoPstecr;
> > + UINT32 DcfgCcsrDcsrCr;
> > + UINT8 Res708[0x740-0x708]; /* add more registers when needed */
> > + UINT32 TpItyp[64]; /* Topology Initiator Type Register */
> > + struct {
> > + UINT32 Upper;
> > + UINT32 Lower;
> > + } TpCluster[16];
> > + UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
> > + UINT32 DcfgCcsrQmBmWarmRst;
> > + UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
> > + UINT32 DcfgCcsrReserved0;
> > + UINT32 DcfgCcsrReserved1;
> > +} CCSR_GUR;
> > +
> > +/* Supplemental Configuration Unit */
> > +typedef struct {
> > + UINT8 Res000[0x070-0x000];
> > + UINT32 Usb1Prm1Cr;
> > + UINT32 Usb1Prm2Cr;
> > + UINT32 Usb1Prm3Cr;
> > + UINT32 Usb2Prm1Cr;
> > + UINT32 Usb2Prm2Cr;
> > + UINT32 Usb2Prm3Cr;
> > + UINT32 Usb3Prm1Cr;
> > + UINT32 Usb3Prm2Cr;
> > + UINT32 Usb3Prm3Cr;
> > + UINT8 Res094[0x100-0x094];
> > + UINT32 Usb2Icid;
> > + UINT32 Usb3Icid;
> > + UINT8 Res108[0x114-0x108];
> > + UINT32 DmaIcid;
> > + UINT32 SataIcid;
> > + UINT32 Usb1Icid;
> > + UINT32 QeIcid;
> > + UINT32 SdhcIcid;
> > + UINT32 EdmaIcid;
> > + UINT32 EtrIcid;
> > + UINT32 Core0SftRst;
> > + UINT32 Core1SftRst;
> > + UINT32 Core2SftRst;
> > + UINT32 Core3SftRst;
> > + UINT8 Res140[0x158-0x140];
> > + UINT32 AltCBar;
> > + UINT32 QspiCfg;
> > + UINT8 Res160[0x180-0x160];
> > + UINT32 DmaMcr;
> > + UINT8 Res184[0x188-0x184];
> > + UINT32 GicAlign;
> > + UINT32 DebugIcid;
> > + UINT8 Res190[0x1a4-0x190];
> > + UINT32 SnpCnfGcr;
> > +#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
> > +#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
> > +#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
> > +#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
> > +#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
> > +#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
> > +#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
> > +#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
> > +#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
> > +#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
> > + UINT8 Res1a8[0x1ac-0x1a8];
> > + UINT32 IntpCr;
> > + UINT8 Res1b0[0x204-0x1b0];
> > + UINT32 CoreSrEnCr;
> > + UINT8 Res208[0x220-0x208];
> > + UINT32 RvBar00;
> > + UINT32 RvBar01;
> > + UINT32 RvBar10;
> > + UINT32 RvBar11;
> > + UINT32 RvBar20;
> > + UINT32 RvBar21;
> > + UINT32 RvBar30;
> > + UINT32 RvBar31;
> > + UINT32 LpmCsr;
> > + UINT8 Res244[0x400-0x244];
> > + UINT32 QspIdQScr;
> > + UINT32 EcgTxcMcr;
> > + UINT32 SdhcIoVSelCr;
> > + UINT32 RcwPMuxCr0;
> > + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> > + *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> > + *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
> > + Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
> > +#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
> > + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> > + *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> > + *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
> > + Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
> > +#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
> > + UINT32 UsbDrvVBusSelCr;
> > +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
> > +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
> > +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
> > + UINT32 UsbPwrFaultSelCr;
> > +#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
> > +#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
> > +#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
> > +#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
> > +#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
> > +#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
> > + UINT32 UsbRefclkSelcr1;
> > + UINT32 UsbRefclkSelcr2;
> > + UINT32 UsbRefclkSelcr3;
> > + UINT8 Res424[0x600-0x424];
> > + UINT32 ScratchRw[4];
> > + UINT8 Res610[0x680-0x610];
> > + UINT32 CoreBCr;
> > + UINT8 Res684[0x1000-0x684];
> > + UINT32 Pex1MsiIr;
> > + UINT32 Pex1MsiR;
> > + UINT8 Res1008[0x2000-0x1008];
> > + UINT32 Pex2;
> > + UINT32 Pex2MsiR;
> > + UINT8 Res2008[0x3000-0x2008];
> > + UINT32 Pex3MsiIr;
> > + UINT32 Pex3MsiR;
> > +} CCSR_SCFG;
> > +
> > +#define USB_TXVREFTUNE 0x9
> > +#define USB_SQRXTUNE 0xFC7FFFFF
> > +#define USB_PCSTXSWINGFULL 0x47
> > +#define USB_PHY_RX_EQ_VAL_1 0x0000
> > +#define USB_PHY_RX_EQ_VAL_2 0x8000
> > +#define USB_PHY_RX_EQ_VAL_3 0x8003
> > +#define USB_PHY_RX_EQ_VAL_4 0x800b
> > +
> > +/*USB_PHY_SS memory map*/
> > +typedef struct {
> > + UINT16 IpIdcodeLo;
> > + UINT16 SupIdcodeHi;
> > + UINT8 Res4[0x0006-0x0004];
> > + UINT16 RtuneDebug;
> > + UINT16 RtuneStat;
> > + UINT16 SupSsPhase;
> > + UINT16 SsFreq;
> > + UINT8 ResE[0x0020-0x000e];
> > + UINT16 Ateovrd;
> > + UINT16 MpllOvrdInLo;
> > + UINT8 Res24[0x0026-0x0024];
> > + UINT16 SscOvrdIn;
> > + UINT8 Res28[0x002A-0x0028];
> > + UINT16 LevelOvrdIn;
> > + UINT8 Res2C[0x0044-0x002C];
> > + UINT16 ScopeCount;
> > + UINT8 Res46[0x0060-0x0046];
> > + UINT16 MpllLoopCtl;
> > + UINT8 Res62[0x006C-0x0062];
> > + UINT16 SscClkCntrl;
> > + UINT8 Res6E[0x2002-0x006E];
> > + UINT16 Lane0TxOvrdInHi;
> > + UINT16 Lane0TxOvrdDrvLo;
> > + UINT8 Res2006[0x200C-0x2006];
> > + UINT16 Lane0RxOvrdInHi;
> > + UINT8 Res200E[0x2022-0x200E];
> > + UINT16 Lane0TxCmWaitTimeOvrd;
> > + UINT8 Res2024[0x202A-0x2024];
> > + UINT16 Lane0TxLbertCtl;
> > + UINT16 Lane0RxLbertCtl;
> > + UINT16 Lane0RxLbertErr;
> > + UINT8 Res2030[0x205A-0x2030];
> > + UINT16 Lane0TxAltBlock;
> > +} CCSR_USB_PHY;
> > +
> > +/* Clocking */
> > +typedef struct {
> > + struct {
> > + UINT32 ClkCnCSr; /* core cluster n clock control status */
> > + UINT8 Res004[0x0c];
> > + UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
> > + UINT8 Res014[0x0c];
> > + } ClkcSr[4];
> > + UINT8 Res040[0x780]; /* 0x100 */
> > + struct {
> > + UINT32 PllCnGSr;
> > + UINT8 Res804[0x1c];
> > + } PllCgSr[NUM_CC_PLLS];
> > + UINT8 Res840[0x1c0];
> > + UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
> > + UINT8 Resa04[0x1fc];
> > + UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
> > + UINT8 Resc04[0x1c];
> > + UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
> > + UINT8 Resc24[0x3dc];
> > +} CCSR_CLOCK;
> > +
> > +VOID
> > +GetSysInfo (
> > + OUT SYS_INFO *
> > + );
> > +
> > +UINT32
> > +EFIAPI
> > +GurRead (
> > + IN UINTN Address
> > + );
> > +
> > +#endif /* __SOC_H__ */
> > diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf
> b/Silicon/NXP/Chassis/LS1043aSocLib.inf
> > new file mode 100644
> > index 0000000..1b2f9c4
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf
> > @@ -0,0 +1,47 @@
> > +# @file
> > +#
> > +# Copyright 2017 NXP
> > +#
> > +# This program and the accompanying materials
> > +# are licensed and made available under the terms and conditions of the
> BSD License
> > +# which accompanies this distribution. The full text of the license may be
> found at
> > +#
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C9a50d6
> e105bc4080493208d5a53ed014%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636596611590418850&sdata=jZ0%2B2I7ul%2F8Te5ASAsABuk4O0LR
> 6%2Bn8G8avnxAvcF9k%3D&reserved=0
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +#
> > +#
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001A
> > + BASE_NAME = SocLib
> > + FILE_GUID = e868c5ca-9729-43ae-bff4-438c67de8c68
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = SocLib
> > +
> > +[Packages]
> > + MdeModulePkg/MdeModulePkg.dec
> > + MdePkg/MdePkg.dec
> > + Silicon/NXP/NxpQoriqLs.dec
> > + Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> > + Silicon/NXP/LS1043A/LS1043A.dec
> > +
> > +[LibraryClasses]
> > + BaseLib
> > + BeIoLib
> > + DebugLib
> > + SerialPortLib
> > +
> > +[Sources.common]
> > + Chassis.c
> > + Chassis2/Soc.c
> > + SerDes.c
> > +
> > +[FixedPcd]
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> > + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> > + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> > + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> > + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> > + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> > diff --git a/Silicon/NXP/Chassis/SerDes.c b/Silicon/NXP/Chassis/SerDes.c
> > new file mode 100644
> > index 0000000..e4578c3
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis/SerDes.c
> > @@ -0,0 +1,271 @@
> > +/** SerDes.c
> > + Provides the basic interfaces for SerDes Module
> > +
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials
> > + are licensed and made available under the terms and conditions of the
> BSD License
> > + which accompanies this distribution. The full text of the license may be
> found
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C9a50d6
> e105bc4080493208d5a53ed014%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636596611590418850&sdata=jZ0%2B2I7ul%2F8Te5ASAsABuk4O0LR
> 6%2Bn8G8avnxAvcF9k%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#include <Bitops.h>
> > +#include <Library/DebugLib.h>
> > +#include <SerDes.h>
> > +#include <SocSerDes.h>
> > +#include <Soc.h>
> > +#include <Uefi.h>
> > +
> > +/**
> > + Function to get serdes Lane protocol corresponding to
> > + serdes protocol.
> > +
> > + @param SerDes Serdes number.
> > + @param Cfg Serdes Protocol.
> > + @param Lane Serdes Lane number.
> > +
> > + @return Serdes Lane protocol.
> > +
> > +**/
> > +STATIC
> > +SERDES_PROTOCOL
> > +GetSerDesPrtcl (
> > + IN INTN SerDes,
> > + IN INTN Cfg,
> > + IN INTN Lane
> > + )
> > +{
> > + SERDES_CONFIG *Config;
> > +
> > + if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
> > + return 0;
> > + }
> > +
> > + Config = SerDesConfigTbl[SerDes];
> > + while (Config->Protocol) {
> > + if (Config->Protocol == Cfg) {
> > + return Config->SrdsLane[Lane];
> > + }
> > + Config++;
> > + }
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +/**
> > + Function to check if inputted protocol is a valid serdes protocol.
> > +
> > + @param SerDes Serdes number.
> > + @param Prtcl Serdes Protocol to be verified.
> > +
> > + @return EFI_INVALID_PARAMETER Input parameter in invalid.
> > + @return EFI_NOT_FOUND Serdes Protocol not a valid protocol.
> > + @return EFI_SUCCESS Serdes Protocol is a valid protocol.
> > +
> > +**/
> > +STATIC
> > +EFI_STATUS
> > +CheckSerDesPrtclValid (
> > + IN INTN SerDes,
> > + IN UINT32 Prtcl
> > + )
> > +{
> > + SERDES_CONFIG *Config;
> > + INTN Cnt;
> > +
> > + if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + Config = SerDesConfigTbl[SerDes];
> > + while (Config->Protocol) {
> > + if (Config->Protocol == Prtcl) {
> > + DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in
> Table\n", Prtcl));
> > + break;
> > + }
> > + Config++;
> > + }
> > +
> > + if (!Config->Protocol) {
> > + return EFI_NOT_FOUND;
> > + }
> > +
> > + for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
> > + if (Config->SrdsLane[Cnt] != NONE) {
> > + return EFI_SUCCESS;
> > + }
> > + }
> > +
> > + return EFI_NOT_FOUND;
> > +}
> > +
> > +/**
> > + Function to fill serdes map information.
> > +
> > + @param Srds Serdes number.
> > + @param SerdesProtocolMask Serdes Protocol Mask.
> > + @param SerdesProtocolShift Serdes Protocol shift value.
> > + @param SerDesPrtclMap Pointer to Serdes Protocol map.
> > +
> > +**/
> > +STATIC
> > +VOID
> > +LSSerDesMap (
> > + IN UINT32 Srds,
> > + IN UINT32 SerdesProtocolMask,
> > + IN UINT32 SerdesProtocolShift,
> > + OUT UINT64 *SerDesPrtclMap
> > + )
> > +{
> > + CCSR_GUR *Gur;
> > + UINT32 SrdsProt;
> > + INTN Lane;
> > + UINT32 Flag;
> > +
> > + Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> > + *SerDesPrtclMap = 0x0;
> > + Flag = 0;
> > +
> > + SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) &
> SerdesProtocolMask;
> > + SrdsProt >>= SerdesProtocolShift;
> > +
> > + DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
> > + Srds + 1, SrdsProt, SrdsProt));
>
> Spurious indentation.
>
Will correct
> > +
> > + if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
> > + DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
> > + Srds + 1, SrdsProt));
>
> Spurious indentation.
>
Will correct
> > + Flag++;
> > + }
> > +
> > + for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
> > + SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
> > + if (LanePrtcl >= SERDES_PRTCL_COUNT) {
> > + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n",
> LanePrtcl));
> > + Flag++;
> > + } else {
> > + *SerDesPrtclMap |= BIT (LanePrtcl);
> > + }
> > + }
> > +
> > + if (Flag) {
> > + DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
> > + } else {
> > + DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
> > + }
> > +}
> > +
> > +/**
> > + Get lane protocol on provided serdes lane and execute callback function.
> > +
> > + @param Srds Serdes number.
> > + @param SerdesProtocolMask Mask to get Serdes Protocol for Srds
> > + @param SerdesProtocolShift Shift value to get Serdes Protocol for
> Srds.
> > + @param SerDesLaneProbeCallback Pointer Callback function to be called
> for Lane protocol
> > + @param Arg Pointer to Arguments to be passed to callback
> function.
> > +
> > +**/
> > +STATIC
> > +VOID
> > +SerDesInstanceProbeLanes (
> > + IN UINT32 Srds,
> > + IN UINT32 SerdesProtocolMask,
> > + IN UINT32 SerdesProtocolShift,
> > + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> > + IN VOID *Arg
> > + )
> > +{
> > +
> > + CCSR_GUR *Gur;
> > + UINT32 SrdsProt;
> > + INTN Lane;
> > +
> > + Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
> > +
> > + SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) &
> SerdesProtocolMask;
> > + SrdsProt >>= SerdesProtocolShift;
> > +
> > + /*
> > + * Invoke callback for all lanes in the SerDes instance:
> > + */
> > + for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
> > + SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
> > + if (LanePrtcl >= SERDES_PRTCL_COUNT || LanePrtcl < NONE) {
>
> Please use parentheses rather than relying on operator precedence.
>
Ok
> > + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n",
> LanePrtcl));
> > + }
> > + else if (LanePrtcl != NONE) {
>
> else on same line as }
>
OK
> > + SerDesLaneProbeCallback (LanePrtcl, Arg);
> > + }
> > + }
> > +}
> > +
> > +/**
> > + Probe all serdes lanes for lane protocol and execute provided callback
> function.
> > +
> > + @param SerDesLaneProbeCallback Pointer Callback function to be called
> for Lane protocol
> > + @param Arg Pointer to Arguments to be passed to callback
> function.
> > +
> > +**/
> > +VOID
> > +SerDesProbeLanes (
> > + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> > + IN VOID *Arg
> > + )
> > +{
> > + SerDesInstanceProbeLanes (SRDS_1,
> > + RCWSR_SRDS1_PRTCL_MASK,
> > + RCWSR_SRDS1_PRTCL_SHIFT,
> > + SerDesLaneProbeCallback,
> > + Arg);
> > +
> > + if (PcdGetBool (PcdSerdes2Enabled)) {
> > + SerDesInstanceProbeLanes (SRDS_2,
> > + RCWSR_SRDS2_PRTCL_MASK,
> > + RCWSR_SRDS2_PRTCL_SHIFT,
> > + SerDesLaneProbeCallback,
> > + Arg);
> > + }
> > +}
> > +
> > +/**
> > + Function to return Serdes protocol map for all serdes available on board.
> > +
> > + @param SerDesPrtclMap Pointer to Serdes protocl map.
> > +
> > +**/
> > +VOID
> > +GetSerdesProtocolMaps (
> > + OUT UINT64 *SerDesPrtclMap
> > + )
> > +{
> > + LSSerDesMap (SRDS_1,
> > + RCWSR_SRDS1_PRTCL_MASK,
> > + RCWSR_SRDS1_PRTCL_SHIFT,
> > + SerDesPrtclMap);
> > +
> > + if (PcdGetBool (PcdSerdes2Enabled)) {
> > + LSSerDesMap (SRDS_2,
> > + RCWSR_SRDS2_PRTCL_MASK,
> > + RCWSR_SRDS2_PRTCL_SHIFT,
> > + SerDesPrtclMap);
> > + }
> > +
> > +}
> > +
> > +BOOLEAN
> > +IsSerDesLaneProtocolConfigured (
> > + IN UINT64 SerDesPrtclMap,
> > + IN SERDES_PROTOCOL Device
> > + )
> > +{
> > + if (Device >= SERDES_PRTCL_COUNT || Device < NONE) {
>
> Please use parentheses rather than relying on operator precedence.
>
Sure
> > + ASSERT (Device > NONE && Device < SERDES_PRTCL_COUNT);
>
> (Here as well.)
>
OK
> > + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device
> %d\n", Device));
> > + }
> > +
> > + return (SerDesPrtclMap & BIT (Device)) != 0 ;
> > +}
> > diff --git a/Silicon/NXP/Include/Bitops.h b/Silicon/NXP/Include/Bitops.h
> > new file mode 100644
> > index 0000000..beddb4e
> > --- /dev/null
> > +++ b/Silicon/NXP/Include/Bitops.h
> > @@ -0,0 +1,179 @@
> > +/** Bitops.h
> > + Header defining the general bitwise operations
> > +
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials
> > + are licensed and made available under the terms and conditions of the
> BSD License
> > + which accompanies this distribution. The full text of the license may be
> found at
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C9a50d6
> e105bc4080493208d5a53ed014%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636596611590418850&sdata=jZ0%2B2I7ul%2F8Te5ASAsABuk4O0LR
> 6%2Bn8G8avnxAvcF9k%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#ifndef __BITOPS_H__
> > +#define __BITOPS_H__
> > +
> > +#include <Library/DebugLib.h>
> > +
> > +#define MASK_LOWER_16 0xFFFF0000
> > +#define MASK_UPPER_16 0x0000FFFF
> > +#define MASK_LOWER_8 0xFF000000
> > +#define MASK_UPPER_8 0x000000FF
>
> These appear unused by the set.
>
Will check.
> > +
> > +/*
> > + * Returns the bit mask for a bit index from 0 to 31
> > + */
> > +#define BIT(_BitIndex) (0x1u << (_BitIndex))
>
> I don't see these being used for anything other than setting up BIT1
> BIT2 BIT3 and so on. We already have those in Base.h.
>
In Base.h, we have BIT1, BIT2 defined, here the requirement is to get set bit on basis of bit number, bit is not known in advance.
> > +
> > +/**
> > + * Upper32Bits - return bits 32-63 of a number
> > + * @N: the number we're accessing
> > + *
> > + * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
> > + * the "right shift count >= width of type" warning when that quantity is
> > + * 32-bits.
> > + */
> > +#define Upper32Bits(N) ((UINT32)(((N) >> 16) >> 16))
>
> 1) Compiler warnings are there for a reason.
> 2) This does not appear to be actually used.
>
> Can we just drop it?
>
Yes, we can
> > +
> > +/**
> > + * Lower32Bits - return bits 0-31 of a number
> > + * @N: the number we're accessing
> > + */
> > +#define Lower32Bits(N) ((UINT32)(N))
>
> Same here.
>
sure
> > +
> > +
> > +/*
> > + * Stores a value for a given bit field in 32-bit '_Container'
> > + */
> > +
> > +#define SET_BIT_FIELD32(_Container, _BitShift, _BitWidth, _Value) \
> > + __SET_BIT_FIELD32(_Container, \
> > + __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth), \
> > + _BitShift, \
> > + _Value)
> > +
> > +#define __SET_BIT_FIELD32(_Container, _BitMask, _BitShift, _Value) \
> > + do { \
> > + (_Container) &= ~(_BitMask); \
> > + if ((_Value) != 0) { \
> > + ASSERT(((UINT32)(_Value) << (_BitShift)) <= (_BitMask)); \
> > + (_Container) |= \
> > + ((UINT32)(_Value) << (_BitShift)) & (_BitMask); \
> > + } \
> > + } while (0)
> > +
> > +/*
> > + * Extracts the value for a given bit field in 32-bit _Container
> > + */
> > +
> > +#define GET_BIT_FIELD32(_Container, _BitShift, _BitWidth) \
> > + __GET_BIT_FIELD32(_Container, \
> > + __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth), \
> > + _BitShift)
> > +
> > +#define __GET_BIT_FIELD32(_Container, _BitMask, _BitShift) \
> > + (((UINT32)(_Container) & (_BitMask)) >> (_BitShift))
> > +
> > +#define __GEN_BIT_FIELD_MASK32(_BitShift, _BitWidth) \
> > + ((_BitWidth) < 32 ? \
> > + (((UINT32)1 << (_BitWidth)) - 1) << (_BitShift) : \
> > + ~(UINT32)0)
> > +
> > +/*
> > + *Stores a value for a given bit field in 64-bit '_Container'
> > + */
> > +#define SET_BIT_FIELD64(_Container, _BitShift, _BitWidth, _Value) \
> > + __SET_BIT_FIELD64(_Container, \
> > + __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth), \
> > + _BitShift, \
> > + _Value)
> > +
> > +#define __SET_BIT_FIELD64(_Container, _BitMask, _BitShift, _Value) \
> > + do { \
> > + (_Container) &= ~(_BitMask); \
> > + if ((_Value) != 0) { \
> > + ASSERT(((UINT64)(_Value) << (_BitShift)) <= (_BitMask)); \
> > + (_Container) |= \
> > + ((UINT64)(_Value) << (_BitShift)) & (_BitMask); \
> > + } \
> > + } while (0)
> > +
> > +/*
> > + * Extracts the value for a given bit field in 64-bit _Container
> > + */
> > +#define GET_BIT_FIELD64(_Container, _BitShift, _BitWidth) \
> > + __GET_BIT_FIELD64(_Container, \
> > + __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth), \
> > + _BitShift)
> > +
> > +#define __GET_BIT_FIELD64(_Container, _BitMask, _BitShift) \
> > + (((UINT64)(_Container) & (_BitMask)) >> (_BitShift))
> > +
> > +#define __GEN_BIT_FIELD_MASK64(_BitShift, _BitWidth) \
> > + ((_BitWidth) < 64 ? \
> > + (((UINT64)1 << (_BitWidth)) - 1) << (_BitShift) : \
> > + ~(UINT64)0)
> > +
>
> These all appear unused.
> Also, there are BitField operations in edk2 BaseLib.
>
Will remove these.
> > +/**
> > +
> > + Test If the Destination buffer sets (0->1) or clears (1->0) any bit in Source
> buffer ?
> > +
> > + @param[in] Source Source Buffer Pointer
> > + @param[in] Destination Destination Buffer Pointer
> > + @param[in] NumBytes Bytes to Compare
> > + @param[in] Set True : Test Weather Destination buffer sets any bit
> in Source buffer ?
> > + False : Test Weather Destination buffer clears any bit in
> Source buffer ?
> > +
> > + @retval TRUE Destination buffer sets/clear a bit in source buffer.
> > + @retval FALSE Destination buffer doesn't sets/clear bit in source
> buffer.
> > +
> > +**/
> > +STATIC
> > +inline
> > +BOOLEAN
> > +TestBitSetClear (
>
> This one is used, but only once, in NorFlashDxe.
> Coding Style also bans function definitions in header files.
> Can this move directly to NorFlashDxe.c?
>
Will check if needed by other modules [in later set of patches], else will move it to NorFlashDxe.
> > + IN VOID *Source,
> > + IN VOID *Destination,
> > + IN UINTN NumBytes,
> > + IN BOOLEAN Set
> > + )
> > +{
> > + UINTN Index = 0;
> > + VOID* Buffer;
> > +
> > + if (Set) {
> > + Buffer = Destination;
> > + } else {
> > + Buffer = Source;
> > + }
> > +
> > + while (Index < NumBytes) {
> > + if ((NumBytes - Index) >= 8) {
> > + if ((*((UINT64*)(Source+Index)) ^ *((UINT64*)(Destination+Index))) &
> *((UINT64*)(Buffer+Index))) {
> > + return TRUE;
> > + }
> > + Index += 8;
> > + } else if ((NumBytes - Index) >= 4) {
> > + if ((*((UINT32*)(Source+Index)) ^ *((UINT32*)(Destination+Index))) &
> *((UINT32*)(Buffer+Index))) {
> > + return TRUE;
> > + }
> > + Index += 4;
> > + } else if ((NumBytes - Index) >= 2) {
> > + if ((*((UINT16*)(Source+Index)) ^ *((UINT16*)(Destination+Index))) &
> *((UINT16*)(Buffer+Index))) {
> > + return TRUE;
> > + }
> > + Index += 2;
> > + } else if ((NumBytes - Index) >= 1) {
> > + if ((*((UINT8*)(Source+Index)) ^ *((UINT8*)(Destination+Index))) &
> *((UINT8*)(Buffer+Index))) {
> > + return TRUE;
> > + }
> > + Index += 1;
> > + }
> > + }
> > + return FALSE;
> > +}
> > +
> > +#endif
>
> On the whole, it looks like this header file can go.
>
> /
> Leif
>
> > diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h
> b/Silicon/NXP/LS1043A/Include/SocSerDes.h
> > new file mode 100644
> > index 0000000..90e165f
> > --- /dev/null
> > +++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h
> > @@ -0,0 +1,55 @@
> > +/** @file
> > + The Header file of SerDes Module for LS1043A
> > +
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials
> > + are licensed and made available under the terms and conditions of the
> BSD License
> > + which accompanies this distribution. The full text of the license may be
> found
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C9a50d6
> e105bc4080493208d5a53ed014%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636596611590418850&sdata=jZ0%2B2I7ul%2F8Te5ASAsABuk4O0LR
> 6%2Bn8G8avnxAvcF9k%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#ifndef __SOC_SERDES_H__
> > +#define __SOC_SERDES_H__
> > +
> > +#include <SerDes.h>
> > +
> > +SERDES_CONFIG SerDes1ConfigTbl[] = {
> > + /* SerDes 1 */
> > + {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } },
> > + {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
> > + {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } },
> > + {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } },
> > + {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
> > + {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 }
> },
> > + {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2,
> SGMII_FM1_DTSEC5, PCIE3 } },
> > + {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
> > + {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } },
> > + {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
> > + {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } },
> > + {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } },
> > + {0x9998, {PCIE1, PCIE2, PCIE3, SATA } },
> > + {0x6058, {PCIE1, PCIE1, PCIE2, SATA } },
> > + {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
> > + {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
> > + {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2,
> PCIE3 } },
> > + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2,
> SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> > + {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
> > + {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
> > + {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
> > + {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
> > + {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } },
> > + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2,
> SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> > + {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5,
> SGMII_FM1_DTSEC6 } },
> > + {}
> > +};
> > +
> > +SERDES_CONFIG *SerDesConfigTbl[] = {
> > + SerDes1ConfigTbl
> > +};
> > +
> > +#endif /* __SOC_SERDES_H */
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 03/39] SocLib : Add support for initialization of peripherals
2018-04-18 16:38 ` Meenakshi Aggarwal
@ 2018-04-18 18:15 ` Leif Lindholm
2018-04-19 4:59 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-18 18:15 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi
On Wed, Apr 18, 2018 at 04:38:22PM +0000, Meenakshi Aggarwal wrote:
> > > +
> > > +/*
> > > + * Returns the bit mask for a bit index from 0 to 31
> > > + */
> > > +#define BIT(_BitIndex) (0x1u << (_BitIndex))
> >
> > I don't see these being used for anything other than setting up BIT1
> > BIT2 BIT3 and so on. We already have those in Base.h.
> >
> In Base.h, we have BIT1, BIT2 defined, here the requirement is to
> get set bit on basis of bit number, bit is not known in advance.
Ah, I missed the uses in SerDes.c and saw only the ones in UsbHcd.h
(which could use the Base.h defines).
But does it really simplify anything in SerDes.c?
*SerDesPrtclMap |= BIT (LanePrtcl);
is no clearer to me than
*SerDesPrtclMap |= (1u << LanePrtcl);
Best Regards,
Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 10/39] IFC : Add Header file for IFC controller
2018-02-16 8:50 ` [PATCH edk2-platforms 10/39] IFC : Add Header file for IFC controller Meenakshi
@ 2018-04-18 18:31 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-18 18:31 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
On Fri, Feb 16, 2018 at 02:20:06PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> This header file contain IFC controller timing structure,
> chip select enum and other IFC macros.
Could you just add a comment as to what an IFC is?
(I'm guessing it's some sort of flash controller, but...)
No other comments on this patch.
/
Leif
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/Ifc.h | 420 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 420 insertions(+)
> create mode 100644 Silicon/NXP/Include/Ifc.h
>
> diff --git a/Silicon/NXP/Include/Ifc.h b/Silicon/NXP/Include/Ifc.h
> new file mode 100644
> index 0000000..0bb7230
> --- /dev/null
> +++ b/Silicon/NXP/Include/Ifc.h
> @@ -0,0 +1,420 @@
> +/** @Ifc.h
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __IFC_H__
> +#define __IFC_H__
> +
> +#include <Library/BaseLib.h>
> +#include <Uefi.h>
> +
> +#define IFC_BANK_COUNT 4
> +
> +#define IFC_CSPR_REG_LEN 148
> +#define IFC_AMASK_REG_LEN 144
> +#define IFC_CSOR_REG_LEN 144
> +#define IFC_FTIM_REG_LEN 576
> +
> +#define IFC_CSPR_USED_LEN sizeof (IFC_CSPR) * \
> + IFC_BANK_COUNT
> +
> +#define IFC_AMASK_USED_LEN sizeof (IFC_AMASK) * \
> + IFC_BANK_COUNT
> +
> +#define IFC_CSOR_USED_LEN sizeof (IFC_CSOR) * \
> + IFC_BANK_COUNT
> +
> +#define IFC_FTIM_USED_LEN sizeof (IFC_FTIM) * \
> + IFC_BANK_COUNT
> +
> +/* List of commands */
> +#define IFC_NAND_CMD_RESET 0xFF
> +#define IFC_NAND_CMD_READID 0x90
> +#define IFC_NAND_CMD_STATUS 0x70
> +#define IFC_NAND_CMD_READ0 0x00
> +#define IFC_NAND_CMD_READSTART 0x30
> +#define IFC_NAND_CMD_ERASE1 0x60
> +#define IFC_NAND_CMD_ERASE2 0xD0
> +#define IFC_NAND_CMD_SEQIN 0x80
> +#define IFC_NAND_CMD_PAGEPROG 0x10
> +#define MAX_RETRY_COUNT 150000
> +
> +
> +#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
> +
> +/*
> + * NAND Event and Error Status Register (NAND_EVTER_STAT)
> + */
> +
> +/* Operation Complete */
> +#define IFC_NAND_EVTER_STAT_OPC 0x80000000
> +
> +/* Flash Timeout Error */
> +#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
> +
> +/* Write Protect Error */
> +#define IFC_NAND_EVTER_STAT_WPER 0x04000000
> +
> +/* ECC Error */
> +#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
> +
> +/*
> + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
> + */
> +
> +/* NAND Machine specific opcodes OP0-OP14*/
> +#define IFC_NAND_FIR0_OP0 0xFC000000
> +#define IFC_NAND_FIR0_OP0_SHIFT 26
> +#define IFC_NAND_FIR0_OP1 0x03F00000
> +#define IFC_NAND_FIR0_OP1_SHIFT 20
> +#define IFC_NAND_FIR0_OP2 0x000FC000
> +#define IFC_NAND_FIR0_OP2_SHIFT 14
> +#define IFC_NAND_FIR0_OP3 0x00003F00
> +#define IFC_NAND_FIR0_OP3_SHIFT 8
> +#define IFC_NAND_FIR0_OP4 0x000000FC
> +#define IFC_NAND_FIR0_OP4_SHIFT 2
> +#define IFC_NAND_FIR1_OP5 0xFC000000
> +#define IFC_NAND_FIR1_OP5_SHIFT 26
> +#define IFC_NAND_FIR1_OP6 0x03F00000
> +#define IFC_NAND_FIR1_OP6_SHIFT 20
> +#define IFC_NAND_FIR1_OP7 0x000FC000
> +#define IFC_NAND_FIR1_OP7_SHIFT 14
> +#define IFC_NAND_FIR1_OP8 0x00003F00
> +#define IFC_NAND_FIR1_OP8_SHIFT 8
> +#define IFC_NAND_FIR1_OP9 0x000000FC
> +#define IFC_NAND_FIR1_OP9_SHIFT 2
> +#define IFC_NAND_FIR2_OP10 0xFC000000
> +#define IFC_NAND_FIR2_OP10_SHIFT 26
> +#define IFC_NAND_FIR2_OP11 0x03F00000
> +#define IFC_NAND_FIR2_OP11_SHIFT 20
> +#define IFC_NAND_FIR2_OP12 0x000FC000
> +#define IFC_NAND_FIR2_OP12_SHIFT 14
> +#define IFC_NAND_FIR2_OP13 0x00003F00
> +#define IFC_NAND_FIR2_OP13_SHIFT 8
> +#define IFC_NAND_FIR2_OP14 0x000000FC
> +#define IFC_NAND_FIR2_OP14_SHIFT 2
> +
> +/*
> + * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
> + */
> +
> +/* General purpose FCM flash command bytes CMD0-CMD7 */
> +#define IFC_NAND_FCR0_CMD0 0xFF000000
> +#define IFC_NAND_FCR0_CMD0_SHIFT 24
> +#define IFC_NAND_FCR0_CMD1 0x00FF0000
> +#define IFC_NAND_FCR0_CMD1_SHIFT 16
> +#define IFC_NAND_FCR0_CMD2 0x0000FF00
> +#define IFC_NAND_FCR0_CMD2_SHIFT 8
> +#define IFC_NAND_FCR0_CMD3 0x000000FF
> +#define IFC_NAND_FCR0_CMD3_SHIFT 0
> +#define IFC_NAND_FCR1_CMD4 0xFF000000
> +#define IFC_NAND_FCR1_CMD4_SHIFT 24
> +#define IFC_NAND_FCR1_CMD5 0x00FF0000
> +#define IFC_NAND_FCR1_CMD5_SHIFT 16
> +#define IFC_NAND_FCR1_CMD6 0x0000FF00
> +#define IFC_NAND_FCR1_CMD6_SHIFT 8
> +#define IFC_NAND_FCR1_CMD7 0x000000FF
> +#define IFC_NAND_FCR1_CMD7_SHIFT 0
> +
> +/* Timing registers for NAND Flash */
> +
> +#define IFC_FTIM0_NAND_TCCST_SHIFT 25
> +#define IFC_FTIM0_NAND_TCCST(n) ((n) << IFC_FTIM0_NAND_TCCST_SHIFT)
> +#define IFC_FTIM0_NAND_TWP_SHIFT 16
> +#define IFC_FTIM0_NAND_TWP(n) ((n) << IFC_FTIM0_NAND_TWP_SHIFT)
> +#define IFC_FTIM0_NAND_TWCHT_SHIFT 8
> +#define IFC_FTIM0_NAND_TWCHT(n) ((n) << IFC_FTIM0_NAND_TWCHT_SHIFT)
> +#define IFC_FTIM0_NAND_TWH_SHIFT 0
> +#define IFC_FTIM0_NAND_TWH(n) ((n) << IFC_FTIM0_NAND_TWH_SHIFT)
> +#define IFC_FTIM1_NAND_TADLE_SHIFT 24
> +#define IFC_FTIM1_NAND_TADLE(n) ((n) << IFC_FTIM1_NAND_TADLE_SHIFT)
> +#define IFC_FTIM1_NAND_TWBE_SHIFT 16
> +#define IFC_FTIM1_NAND_TWBE(n) ((n) << IFC_FTIM1_NAND_TWBE_SHIFT)
> +#define IFC_FTIM1_NAND_TRR_SHIFT 8
> +#define IFC_FTIM1_NAND_TRR(n) ((n) << IFC_FTIM1_NAND_TRR_SHIFT)
> +#define IFC_FTIM1_NAND_TRP_SHIFT 0
> +#define IFC_FTIM1_NAND_TRP(n) ((n) << IFC_FTIM1_NAND_TRP_SHIFT)
> +#define IFC_FTIM2_NAND_TRAD_SHIFT 21
> +#define IFC_FTIM2_NAND_TRAD(n) ((n) << IFC_FTIM2_NAND_TRAD_SHIFT)
> +#define IFC_FTIM2_NAND_TREH_SHIFT 11
> +#define IFC_FTIM2_NAND_TREH(n) ((n) << IFC_FTIM2_NAND_TREH_SHIFT)
> +#define IFC_FTIM2_NAND_TWHRE_SHIFT 0
> +#define IFC_FTIM2_NAND_TWHRE(n) ((n) << IFC_FTIM2_NAND_TWHRE_SHIFT)
> +#define IFC_FTIM3_NAND_TWW_SHIFT 24
> +#define IFC_FTIM3_NAND_TWW(n) ((n) << IFC_FTIM3_NAND_TWW_SHIFT)
> +
> +/*
> + * Flash ROW and COL Address Register (ROWn, COLn)
> + */
> +
> +/* Main/spare region locator */
> +#define IFC_NAND_COL_MS 0x80000000
> +
> +/* Column Address */
> +#define IFC_NAND_COL_CA_MASK 0x00000FFF
> +
> +#define NAND_STATUS_WP 0x80
> +
> +/*
> + * NAND Event and Error Enable Register (NAND_EVTER_EN)
> + */
> +
> +/* Operation complete event enable */
> +#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
> +
> +/* Page read complete event enable */
> +#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
> +
> +/* Flash Timeout error enable */
> +#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
> +
> +/* Write Protect error enable */
> +#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
> +
> +/* ECC error logging enable */
> +#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
> +
> +/*
> + * CSPR - Chip Select Property Register
> + */
> +
> +#define IFC_CSPR_BA 0xFFFF0000
> +#define IFC_CSPR_BA_SHIFT 16
> +#define IFC_CSPR_PORT_SIZE 0x00000180
> +#define IFC_CSPR_PORT_SIZE_SHIFT 7
> +
> +// Port Size 8 bit
> +#define IFC_CSPR_PORT_SIZE_8 0x00000080
> +
> +// Port Size 16 bit
> +#define IFC_CSPR_PORT_SIZE_16 0x00000100
> +
> +// Port Size 32 bit
> +#define IFC_CSPR_PORT_SIZE_32 0x00000180
> +
> +// Write Protect
> +#define IFC_CSPR_WP 0x00000040
> +#define IFC_CSPR_WP_SHIFT 6
> +
> +// Machine Select
> +#define IFC_CSPR_MSEL 0x00000006
> +#define IFC_CSPR_MSEL_SHIFT 1
> +
> +// NOR
> +#define IFC_CSPR_MSEL_NOR 0x00000000
> +
> +/* NAND */
> +#define IFC_CSPR_MSEL_NAND 0x00000002
> +
> +/* GPCM */
> +#define IFC_CSPR_MSEL_GPCM 0x00000004
> +
> +// Bank Valid
> +#define IFC_CSPR_V 0x00000001
> +#define IFC_CSPR_V_SHIFT 0
> +
> +/*
> + * Chip Select Option Register - NOR Flash Mode
> + */
> +
> +// Enable Address shift Mode
> +#define IFC_CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
> +
> +// Page Read Enable from NOR device
> +#define IFC_CSOR_NOR_PGRD_EN 0x10000000
> +
> +// AVD Toggle Enable during Burst Program
> +#define IFC_CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
> +
> +// Address Data Multiplexing Shift
> +#define IFC_CSOR_NOR_ADM_MASK 0x0003E000
> +#define IFC_CSOR_NOR_ADM_SHIFT_SHIFT 13
> +#define IFC_CSOR_NOR_ADM_SHIFT(n) ((n) << IFC_CSOR_NOR_ADM_SHIFT_SHIFT)
> +
> +// Type of the NOR device hooked
> +#define IFC_CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
> +#define IFC_CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
> +
> +// Time for Read Enable High to Output High Impedance
> +#define IFC_CSOR_NOR_TRHZ_MASK 0x0000001C
> +#define IFC_CSOR_NOR_TRHZ_SHIFT 2
> +#define IFC_CSOR_NOR_TRHZ_20 0x00000000
> +#define IFC_CSOR_NOR_TRHZ_40 0x00000004
> +#define IFC_CSOR_NOR_TRHZ_60 0x00000008
> +#define IFC_CSOR_NOR_TRHZ_80 0x0000000C
> +#define IFC_CSOR_NOR_TRHZ_100 0x00000010
> +
> +// Buffer control disable
> +#define IFC_CSOR_NOR_BCTLD 0x00000001
> +
> +/*
> + * Chip Select Option Register IFC_NAND Machine
> + */
> +
> +/* Enable ECC Encoder */
> +#define IFC_CSOR_NAND_ECC_ENC_EN 0x80000000
> +#define IFC_CSOR_NAND_ECC_MODE_MASK 0x30000000
> +
> +/* 4 bit correction per 520 Byte sector */
> +#define IFC_CSOR_NAND_ECC_MODE_4 0x00000000
> +
> +/* 8 bit correction per 528 Byte sector */
> +#define IFC_CSOR_NAND_ECC_MODE_8 0x10000000
> +
> +/* Enable ECC Decoder */
> +#define IFC_CSOR_NAND_ECC_DEC_EN 0x04000000
> +
> +/* Row Address Length */
> +#define IFC_CSOR_NAND_RAL_MASK 0x01800000
> +#define IFC_CSOR_NAND_RAL_SHIFT 20
> +#define IFC_CSOR_NAND_RAL_1 0x00000000
> +#define IFC_CSOR_NAND_RAL_2 0x00800000
> +#define IFC_CSOR_NAND_RAL_3 0x01000000
> +#define IFC_CSOR_NAND_RAL_4 0x01800000
> +
> +/* Page Size 512b, 2k, 4k */
> +#define IFC_CSOR_NAND_PGS_MASK 0x00180000
> +#define IFC_CSOR_NAND_PGS_SHIFT 16
> +#define IFC_CSOR_NAND_PGS_512 0x00000000
> +#define IFC_CSOR_NAND_PGS_2K 0x00080000
> +#define IFC_CSOR_NAND_PGS_4K 0x00100000
> +#define IFC_CSOR_NAND_PGS_8K 0x00180000
> +
> +/* Spare region Size */
> +#define IFC_CSOR_NAND_SPRZ_MASK 0x0000E000
> +#define IFC_CSOR_NAND_SPRZ_SHIFT 13
> +#define IFC_CSOR_NAND_SPRZ_16 0x00000000
> +#define IFC_CSOR_NAND_SPRZ_64 0x00002000
> +#define IFC_CSOR_NAND_SPRZ_128 0x00004000
> +#define IFC_CSOR_NAND_SPRZ_210 0x00006000
> +#define IFC_CSOR_NAND_SPRZ_218 0x00008000
> +#define IFC_CSOR_NAND_SPRZ_224 0x0000A000
> +#define IFC_CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
> +
> +/* Pages Per Block */
> +#define IFC_CSOR_NAND_PB_MASK 0x00000700
> +#define IFC_CSOR_NAND_PB_SHIFT 8
> +#define IFC_CSOR_NAND_PB(n) (n-5) << IFC_CSOR_NAND_PB_SHIFT
> +
> +/* Time for Read Enable High to Output High Impedance */
> +#define IFC_CSOR_NAND_TRHZ_MASK 0x0000001C
> +#define IFC_CSOR_NAND_TRHZ_SHIFT 2
> +#define IFC_CSOR_NAND_TRHZ_20 0x00000000
> +#define IFC_CSOR_NAND_TRHZ_40 0x00000004
> +#define IFC_CSOR_NAND_TRHZ_60 0x00000008
> +#define IFC_CSOR_NAND_TRHZ_80 0x0000000C
> +#define IFC_CSOR_NAND_TRHZ_100 0x00000010
> +
> +/*
> + * FTIM0 - NOR Flash Mode
> + */
> +#define IFC_FTIM0_NOR 0xF03F3F3F
> +#define IFC_FTIM0_NOR_TACSE_SHIFT 28
> +#define IFC_FTIM0_NOR_TACSE(n) ((n) << IFC_FTIM0_NOR_TACSE_SHIFT)
> +#define IFC_FTIM0_NOR_TEADC_SHIFT 16
> +#define IFC_FTIM0_NOR_TEADC(n) ((n) << IFC_FTIM0_NOR_TEADC_SHIFT)
> +#define IFC_FTIM0_NOR_TAVDS_SHIFT 8
> +#define IFC_FTIM0_NOR_TAVDS(n) ((n) << IFC_FTIM0_NOR_TAVDS_SHIFT)
> +#define IFC_FTIM0_NOR_TEAHC_SHIFT 0
> +#define IFC_FTIM0_NOR_TEAHC(n) ((n) << IFC_FTIM0_NOR_TEAHC_SHIFT)
> +
> +/*
> + * FTIM1 - NOR Flash Mode
> + */
> +#define IFC_FTIM1_NOR 0xFF003F3F
> +#define IFC_FTIM1_NOR_TACO_SHIFT 24
> +#define IFC_FTIM1_NOR_TACO(n) ((n) << IFC_FTIM1_NOR_TACO_SHIFT)
> +#define IFC_FTIM1_NOR_TRAD_NOR_SHIFT 8
> +#define IFC_FTIM1_NOR_TRAD_NOR(n) ((n) << IFC_FTIM1_NOR_TRAD_NOR_SHIFT)
> +#define IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
> +#define IFC_FTIM1_NOR_TSEQRAD_NOR(n) ((n) << IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT)
> +
> +/*
> + * FTIM2 - NOR Flash Mode
> + */
> +#define IFC_FTIM2_NOR 0x0F3CFCFF
> +#define IFC_FTIM2_NOR_TCS_SHIFT 24
> +#define IFC_FTIM2_NOR_TCS(n) ((n) << IFC_FTIM2_NOR_TCS_SHIFT)
> +#define IFC_FTIM2_NOR_TCH_SHIFT 18
> +#define IFC_FTIM2_NOR_TCH(n) ((n) << IFC_FTIM2_NOR_TCH_SHIFT)
> +#define IFC_FTIM2_NOR_TWPH_SHIFT 10
> +#define IFC_FTIM2_NOR_TWPH(n) ((n) << IFC_FTIM2_NOR_TWPH_SHIFT)
> +#define IFC_FTIM2_NOR_TWP_SHIFT 0
> +#define IFC_FTIM2_NOR_TWP(n) ((n) << IFC_FTIM2_NOR_TWP_SHIFT)
> +
> +/*
> + * FTIM0 - Normal GPCM Mode
> + */
> +#define IFC_FTIM0_GPCM 0xF03F3F3F
> +#define IFC_FTIM0_GPCM_TACSE_SHIFT 28
> +#define IFC_FTIM0_GPCM_TACSE(n) ((n) << IFC_FTIM0_GPCM_TACSE_SHIFT)
> +#define IFC_FTIM0_GPCM_TEADC_SHIFT 16
> +#define IFC_FTIM0_GPCM_TEADC(n) ((n) << IFC_FTIM0_GPCM_TEADC_SHIFT)
> +#define IFC_FTIM0_GPCM_TAVDS_SHIFT 8
> +#define IFC_FTIM0_GPCM_TAVDS(n) ((n) << IFC_FTIM0_GPCM_TAVDS_SHIFT)
> +#define IFC_FTIM0_GPCM_TEAHC_SHIFT 0
> +#define IFC_FTIM0_GPCM_TEAHC(n) ((n) << IFC_FTIM0_GPCM_TEAHC_SHIFT)
> +
> +/*
> + * FTIM1 - Normal GPCM Mode
> + */
> +#define IFC_FTIM1_GPCM 0xFF003F00
> +#define IFC_FTIM1_GPCM_TACO_SHIFT 24
> +#define IFC_FTIM1_GPCM_TACO(n) ((n) << IFC_FTIM1_GPCM_TACO_SHIFT)
> +#define IFC_FTIM1_GPCM_TRAD_SHIFT 8
> +#define IFC_FTIM1_GPCM_TRAD(n) ((n) << IFC_FTIM1_GPCM_TRAD_SHIFT)
> +
> +/*
> + * FTIM2 - Normal GPCM Mode
> + */
> +#define IFC_FTIM2_GPCM 0x0F3C00FF
> +#define IFC_FTIM2_GPCM_TCS_SHIFT 24
> +#define IFC_FTIM2_GPCM_TCS(n) ((n) << IFC_FTIM2_GPCM_TCS_SHIFT)
> +#define IFC_FTIM2_GPCM_TCH_SHIFT 18
> +#define IFC_FTIM2_GPCM_TCH(n) ((n) << IFC_FTIM2_GPCM_TCH_SHIFT)
> +#define IFC_FTIM2_GPCM_TWP_SHIFT 0
> +#define IFC_FTIM2_GPCM_TWP(n) ((n) << IFC_FTIM2_GPCM_TWP_SHIFT)
> +
> +/* Convert an address into the right format for the CSPR Registers */
> +#define IFC_CSPR_PHYS_ADDR(x) (((UINTN)x) & 0xffff0000)
> +
> +/*
> + * Address Mask Register
> + */
> +#define IFC_AMASK_MASK 0xFFFF0000
> +#define IFC_AMASK_SHIFT 16
> +#define IFC_AMASK(n) (IFC_AMASK_MASK << \
> + (HighBitSet32(n) - IFC_AMASK_SHIFT))
> +
> +typedef enum {
> + IFC_CS0 = 0,
> + IFC_CS1,
> + IFC_CS2,
> + IFC_CS3,
> + IFC_CS4,
> + IFC_CS5,
> + IFC_CS6,
> + IFC_CS7,
> + IFC_CS_MAX,
> +} IFC_CHIP_SEL;
> +
> +typedef struct {
> + UINT32 Ftim[IFC_BANK_COUNT];
> + UINT32 CsprExt;
> + UINT32 Cspr;
> + UINT32 Csor;
> + UINT32 Amask;
> + UINT8 CS;
> +} IFC_TIMINGS;
> +
> +#endif //__IFC_H__
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 11/39] LS1043/BoardLib : Add support for LS1043 BoardLib.
2018-02-16 8:50 ` [PATCH edk2-platforms 11/39] LS1043/BoardLib : Add support for LS1043 BoardLib Meenakshi
@ 2018-04-18 18:34 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-18 18:34 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
On Fri, Feb 16, 2018 at 02:20:07PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> BoardLib will contain functions specific for LS1043aRdb board.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> .../NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h | 109 +++++++++++++++++++++
> .../NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c | 69 +++++++++++++
> .../LS1043aRdbPkg/Library/BoardLib/BoardLib.inf | 31 ++++++
> 3 files changed, 209 insertions(+)
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h b/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
> new file mode 100644
> index 0000000..261867a
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
> @@ -0,0 +1,109 @@
> +/** IfcBoardSpecificLib.h
> +
> + IFC Flash Board Specific Macros and structure
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +#ifndef __IFC__BOARD_SPECIFIC_H__
> +#define __IFC__BOARD_SPECIFIC_H__
> +
> +#include <Ifc.h>
> +
> +// On board flash support
> +#define IFC_NAND_BUF_BASE 0x7E800000
> +
> +// On board Inegrated flash Controller chip select configuration
> +#define IFC_NOR_CS IFC_CS0
> +#define IFC_NAND_CS IFC_CS1
> +#define IFC_FPGA_CS IFC_CS2
> +
> +// board-specific NAND timing
> +#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x7) | \
> + IFC_FTIM0_NAND_TWP(0x18) | \
> + IFC_FTIM0_NAND_TWCHT(0x7) | \
> + IFC_FTIM0_NAND_TWH(0xa))
> +
> +#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x32) | \
> + IFC_FTIM1_NAND_TWBE(0x39) | \
> + IFC_FTIM1_NAND_TRR(0xe) | \
> + IFC_FTIM1_NAND_TRP(0x18))
> +
> +#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0xf) | \
> + IFC_FTIM2_NAND_TREH(0xa) | \
> + IFC_FTIM2_NAND_TWHRE(0x1e))
> +
> +#define NAND_FTIM3 0x0
> +
> +#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BUF_BASE) \
> + | IFC_CSPR_PORT_SIZE_8 \
> + | IFC_CSPR_MSEL_NAND \
> + | IFC_CSPR_V)
> +
> +#define NAND_CSPR_EXT 0x0
> +#define NAND_AMASK 0xFFFF0000
> +
> +#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
> + | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
> + | IFC_CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
> + | IFC_CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
> + | IFC_CSOR_NAND_PGS_2K /* Page Size = 2K */ \
> + | IFC_CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
> + | IFC_CSOR_NAND_PB(6)) /* 2^6 Pages Per Block */
> +
> +// board-specific NOR timing
> +#define NOR_FTIM0 (IFC_FTIM0_NOR_TACSE(0x1) | \
> + IFC_FTIM0_NOR_TEADC(0x1) | \
> + IFC_FTIM0_NOR_TAVDS(0x0) | \
> + IFC_FTIM0_NOR_TEAHC(0xc))
> +#define NOR_FTIM1 (IFC_FTIM1_NOR_TACO(0x1c) | \
> + IFC_FTIM1_NOR_TRAD_NOR(0xb) |\
> + IFC_FTIM1_NOR_TSEQRAD_NOR(0x9))
> +#define NOR_FTIM2 (IFC_FTIM2_NOR_TCS(0x1) | \
> + IFC_FTIM2_NOR_TCH(0x4) | \
> + IFC_FTIM2_NOR_TWPH(0x8) | \
> + IFC_FTIM2_NOR_TWP(0x10))
> +#define NOR_FTIM3 0x0
> +
> +#define NOR_CSPR (IFC_CSPR_PHYS_ADDR(FixedPcdGet64 (PcdIfcRegion1BaseAddr)) \
> + | IFC_CSPR_PORT_SIZE_16 \
> + | IFC_CSPR_MSEL_NOR \
> + | IFC_CSPR_V)
> +
> +#define NOR_CSPR_EXT 0x0
> +#define NOR_AMASK IFC_AMASK(128*1024*1024)
> +#define NOR_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) | \
> + IFC_CSOR_NOR_TRHZ_80)
> +
> +// board-specific fpga timing
> +#define FPGA_BASE_PHYS 0x7fb00000
> +#define FPGA_CSPR_EXT 0x0
> +#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
> + IFC_CSPR_PORT_SIZE_8 | \
> + IFC_CSPR_MSEL_GPCM | \
> + IFC_CSPR_V)
> +
> +#define FPGA_AMASK IFC_AMASK(64 * 1024)
> +#define FPGA_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) | \
> + IFC_CSOR_NOR_NOR_MODE_AVD_NOR | \
> + IFC_CSOR_NOR_TRHZ_80)
> +
> +#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0xf) | \
> + IFC_FTIM0_GPCM_TEADC(0xf) | \
> + IFC_FTIM0_GPCM_TEAHC(0xf))
> +#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \
> + IFC_FTIM1_GPCM_TRAD(0x3f))
> +#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \
> + IFC_FTIM2_GPCM_TCH(0xf) | \
> + IFC_FTIM2_GPCM_TWP(0xff))
> +#define FPGA_FTIM3 0x0
> +
> +#endif //__IFC__BOARD_SPECIFIC_H__
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
> new file mode 100644
> index 0000000..a101a8d
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
> @@ -0,0 +1,69 @@
> +/** @file
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <IfcBoardSpecific.h>
> +
> +VOID
> +GetIfcNorFlashTimings (
> + IN IFC_TIMINGS * NorIfcTimings
> + )
> +{
> + NorIfcTimings->Ftim[0] = NOR_FTIM0;
> + NorIfcTimings->Ftim[1] = NOR_FTIM1;
> + NorIfcTimings->Ftim[2] = NOR_FTIM2;
> + NorIfcTimings->Ftim[3] = NOR_FTIM3;
> + NorIfcTimings->Cspr = NOR_CSPR;
> + NorIfcTimings->CsprExt = NOR_CSPR_EXT;
> + NorIfcTimings->Amask = NOR_AMASK;
> + NorIfcTimings->Csor = NOR_CSOR;
> + NorIfcTimings->CS = IFC_NOR_CS;
> +
> + return ;
> +}
> +
> +VOID
> +GetIfcFpgaTimings (
> + IN IFC_TIMINGS *FpgaIfcTimings
> + )
> +{
> + FpgaIfcTimings->Ftim[0] = FPGA_FTIM0;
> + FpgaIfcTimings->Ftim[1] = FPGA_FTIM1;
> + FpgaIfcTimings->Ftim[2] = FPGA_FTIM2;
> + FpgaIfcTimings->Ftim[3] = FPGA_FTIM3;
> + FpgaIfcTimings->Cspr = FPGA_CSPR;
> + FpgaIfcTimings->CsprExt = FPGA_CSPR_EXT;
> + FpgaIfcTimings->Amask = FPGA_AMASK;
> + FpgaIfcTimings->Csor = FPGA_CSOR;
> + FpgaIfcTimings->CS = IFC_FPGA_CS;
> +
> + return;
> +}
> +
> +VOID
> +GetIfcNandFlashTimings (
> + IN IFC_TIMINGS * NandIfcTimings
> + )
> +{
> + NandIfcTimings->Ftim[0] = NAND_FTIM0;
> + NandIfcTimings->Ftim[1] = NAND_FTIM1;
> + NandIfcTimings->Ftim[2] = NAND_FTIM2;
> + NandIfcTimings->Ftim[3] = NAND_FTIM3;
> + NandIfcTimings->Cspr = NAND_CSPR;
> + NandIfcTimings->CsprExt = NAND_CSPR_EXT;
> + NandIfcTimings->Amask = NAND_AMASK;
> + NandIfcTimings->Csor = NAND_CSOR;
> + NandIfcTimings->CS = IFC_NAND_CS;
> +
> + return;
> +}
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
> new file mode 100644
> index 0000000..7d2702b
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
> @@ -0,0 +1,31 @@
> +# @file
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = BoardLib
> + FILE_GUID = 8ecefc8f-a2c4-4091-b80f-92da7c4ab37f
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = BoardLib
> +
> +[Sources.common]
> + BoardLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[FixedPcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 12/39] Silicon/NXP : Add support of IfcLib
2018-02-16 8:50 ` [PATCH edk2-platforms 12/39] Silicon/NXP : Add support of IfcLib Meenakshi
@ 2018-04-18 18:39 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-18 18:39 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
On Fri, Feb 16, 2018 at 02:20:08PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> Add support of IfcLib, it will be used to perform
> any operation on IFC controller.
Again, please describe what an IFC is.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/Library/IfcLib.h | 23 +++++
> Silicon/NXP/Library/IfcLib/IfcLib.c | 155 ++++++++++++++++++++++++++++
> Silicon/NXP/Library/IfcLib/IfcLib.h | 184 ++++++++++++++++++++++++++++++++++
> Silicon/NXP/Library/IfcLib/IfcLib.inf | 38 +++++++
> Silicon/NXP/NxpQoriqLs.dec | 1 +
> 5 files changed, 401 insertions(+)
> create mode 100644 Silicon/NXP/Include/Library/IfcLib.h
> create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.c
> create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.h
> create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.inf
>
> diff --git a/Silicon/NXP/Include/Library/IfcLib.h b/Silicon/NXP/Include/Library/IfcLib.h
> new file mode 100644
> index 0000000..f350d33
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/IfcLib.h
> @@ -0,0 +1,23 @@
> +/** @IfcLib.h
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __IFC_LIB_H__
> +#define __IFC_LIB_H__
> +
> +VOID
> +IfcInit (
> + VOID
> + );
> +
> +#endif //__IFC_LIB_H__
> diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.c b/Silicon/NXP/Library/IfcLib/IfcLib.c
> new file mode 100644
> index 0000000..97a6591
> --- /dev/null
> +++ b/Silicon/NXP/Library/IfcLib/IfcLib.c
> @@ -0,0 +1,155 @@
> +/** @IfcLib.c
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/BeIoLib.h>
> +#include <Library/IoLib.h>
> +#include "IfcLib.h"
> +
> +UINT8 mNandCS;
> +UINT8 mNorCS;
> +UINT8 mFpgaCS;
> +
> +UINT32
> +EFIAPI
> +IfcWrite (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + if (FixedPcdGetBool(PcdIfcBigEndian)) {
> + return BeMmioWrite32 (Address, Value);
> + } else {
> + return MmioWrite32 (Address, Value);
> + }
> +}
Same comment as watchdog and gur(?) for conteoller endianness handling.
> +
> +VOID
> +SetTimings (
> + IN UINT8 CS,
> + IN IFC_TIMINGS IfcTimings
> + )
> +{
> + IFC_REGS* IfcRegs;
> +
> + IfcRegs = (IFC_REGS*) PcdGet64 (PcdIfcBaseAddr);
No space after (IFC_REGS*).
> +
> + // Configure Extended chip select property registers
> + IfcWrite ((UINTN)&IfcRegs->CsprCs[CS].CsprExt, IfcTimings.CsprExt);
> +
> + // Configure Fpga timing registers
> + IfcWrite ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM0], IfcTimings.Ftim[0]);
> + IfcWrite ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM1], IfcTimings.Ftim[1]);
> + IfcWrite ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM2], IfcTimings.Ftim[2]);
> + IfcWrite ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM3], IfcTimings.Ftim[3]);
> +
> + // Configure chip select option registers
> + IfcWrite ((UINTN)&IfcRegs->CsprCs[CS].Cspr, IfcTimings.Cspr);
> +
> + // Configure address mask registers
> + IfcWrite ((UINTN)&IfcRegs->AmaskCs[CS].Amask, IfcTimings.Amask);
> +
> + // Configure chip select property registers
> + IfcWrite ((UINTN)&IfcRegs->CsorCs[CS].Csor, IfcTimings.Csor);
> +
> + return;
> +}
> +
> +VOID
> +NandInit(
> + VOID
> + )
> +{
> + IFC_REGS* IfcRegs;
> + IFC_TIMINGS NandIfcTimings;
> +
> + IfcRegs = (IFC_REGS*) PcdGet64 (PcdIfcBaseAddr);
No space after (IFC_REGS*).
/
Leif
> +
> + // Get Nand Flash Timings
> + GetIfcNandFlashTimings (&NandIfcTimings);
> +
> + // Validate chip select
> + if (NandIfcTimings.CS < IFC_CS_MAX) {
> + mNandCS = NandIfcTimings.CS;
> +
> + // clear event registers
> + IfcWrite ((UINTN)&IfcRegs->IfcNand.PgrdcmplEvtStat, ~0U);
> +
> + IfcWrite ((UINTN)&IfcRegs->IfcNand.NandEvterStat, ~0U);
> +
> + // Enable error and event for any detected errors
> + IfcWrite ((UINTN)&IfcRegs->IfcNand.NandEvterEn,
> + IFC_NAND_EVTER_EN_OPC_EN |
> + IFC_NAND_EVTER_EN_PGRDCMPL_EN |
> + IFC_NAND_EVTER_EN_FTOER_EN |
> + IFC_NAND_EVTER_EN_WPER_EN);
> + IfcWrite ((UINTN)&IfcRegs->IfcNand.Ncfgr, 0x0);
> +
> + SetTimings (mNandCS, NandIfcTimings);
> + }
> +
> + return;
> +}
> +
> +VOID
> +FpgaInit (
> + VOID
> + )
> +{
> + IFC_TIMINGS FpgaIfcTimings;
> +
> + // Get Fpga Flash Timings
> + GetIfcFpgaTimings (&FpgaIfcTimings);
> +
> + // Validate chip select
> + if (FpgaIfcTimings.CS < IFC_CS_MAX) {
> + mFpgaCS = FpgaIfcTimings.CS;
> + SetTimings (mFpgaCS, FpgaIfcTimings);
> + }
> +
> + return;
> +}
> +
> +VOID
> +NorInit (
> + VOID
> + )
> +{
> + IFC_TIMINGS NorIfcTimings;
> +
> + // Get NOR Flash Timings
> + GetIfcNorFlashTimings (&NorIfcTimings);
> +
> + // Validate chip select
> + if (NorIfcTimings.CS < IFC_CS_MAX) {
> + mNorCS = NorIfcTimings.CS;
> + SetTimings (mNorCS, NorIfcTimings);
> + }
> +
> + return;
> +}
> +
> +//
> +// IFC has NOR , NAND and FPGA
> +//
> +VOID
> +IfcInit (
> + VOID
> + )
> +{
> + NorInit();
> + NandInit();
> + FpgaInit();
> +
> + return;
> +}
> diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.h b/Silicon/NXP/Library/IfcLib/IfcLib.h
> new file mode 100644
> index 0000000..9f52576
> --- /dev/null
> +++ b/Silicon/NXP/Library/IfcLib/IfcLib.h
> @@ -0,0 +1,184 @@
> +/** @IfcLib.h
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __IFC_LIB_H__
> +#define __IFC_LIB_H__
> +
> +#include <Ifc.h>
> +#include <Uefi.h>
> +
> +#define IFC_NAND_RESERVED_SIZE FixedPcdGet32 (PcdIfcNandReservedSize)
> +
> +typedef enum {
> + IFC_FTIM0 = 0,
> + IFC_FTIM1,
> + IFC_FTIM2,
> + IFC_FTIM3,
> +} IFC_FTIMS;
> +
> +typedef struct {
> + UINT32 CsprExt;
> + UINT32 Cspr;
> + UINT32 Res;
> +} IFC_CSPR;
> +
> +typedef struct {
> + UINT32 Amask;
> + UINT32 Res[0x2];
> +} IFC_AMASK;
> +
> +typedef struct {
> + UINT32 Csor;
> + UINT32 CsorExt;
> + UINT32 Res;
> +} IFC_CSOR;
> +
> +typedef struct {
> + UINT32 Ftim[4];
> + UINT32 Res[0x8];
> +}IFC_FTIM ;
> +
> +typedef struct {
> + UINT32 Ncfgr;
> + UINT32 Res1[0x4];
> + UINT32 NandFcr0;
> + UINT32 NandFcr1;
> + UINT32 Res2[0x8];
> + UINT32 Row0;
> + UINT32 Res3;
> + UINT32 Col0;
> + UINT32 Res4;
> + UINT32 Row1;
> + UINT32 Res5;
> + UINT32 Col1;
> + UINT32 Res6;
> + UINT32 Row2;
> + UINT32 Res7;
> + UINT32 Col2;
> + UINT32 Res8;
> + UINT32 Row3;
> + UINT32 Res9;
> + UINT32 Col3;
> + UINT32 Res10[0x24];
> + UINT32 NandFbcr;
> + UINT32 Res11;
> + UINT32 NandFir0;
> + UINT32 NandFir1;
> + UINT32 nandFir2;
> + UINT32 Res12[0x10];
> + UINT32 NandCsel;
> + UINT32 Res13;
> + UINT32 NandSeqStrt;
> + UINT32 Res14;
> + UINT32 NandEvterStat;
> + UINT32 Res15;
> + UINT32 PgrdcmplEvtStat;
> + UINT32 Res16[0x2];
> + UINT32 NandEvterEn;
> + UINT32 Res17[0x2];
> + UINT32 NandEvterIntrEn;
> + UINT32 Res18[0x2];
> + UINT32 NandErattr0;
> + UINT32 NandErattr1;
> + UINT32 Res19[0x10];
> + UINT32 NandFsr;
> + UINT32 Res20;
> + UINT32 NandEccstat[4];
> + UINT32 Res21[0x20];
> + UINT32 NanNdcr;
> + UINT32 Res22[0x2];
> + UINT32 NandAutobootTrgr;
> + UINT32 Res23;
> + UINT32 NandMdr;
> + UINT32 Res24[0x5C];
> +} IFC_NAND;
> +
> +/*
> + * IFC controller NOR Machine registers
> + */
> +typedef struct {
> + UINT32 NorEvterStat;
> + UINT32 Res1[0x2];
> + UINT32 NorEvterEn;
> + UINT32 Res2[0x2];
> + UINT32 NorEvterIntrEn;
> + UINT32 Res3[0x2];
> + UINT32 NorErattr0;
> + UINT32 NorErattr1;
> + UINT32 NorErattr2;
> + UINT32 Res4[0x4];
> + UINT32 NorCr;
> + UINT32 Res5[0xEF];
> +} IFC_NOR;
> +
> +/*
> + * IFC controller GPCM Machine registers
> + */
> +typedef struct {
> + UINT32 GpcmEvterStat;
> + UINT32 Res1[0x2];
> + UINT32 GpcmEvterEn;
> + UINT32 Res2[0x2];
> + UINT32 gpcmEvterIntrEn;
> + UINT32 Res3[0x2];
> + UINT32 GpcmErattr0;
> + UINT32 GpcmErattr1;
> + UINT32 GcmErattr2;
> + UINT32 GpcmStat;
> +} IFC_GPCM;
> +
> +/*
> + * IFC Controller Registers
> + */
> +typedef struct {
> + UINT32 IfcRev;
> + UINT32 Res1[0x2];
> + IFC_CSPR CsprCs[IFC_BANK_COUNT];
> + UINT8 Res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
> + IFC_AMASK AmaskCs[IFC_BANK_COUNT];
> + UINT8 Res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
> + IFC_CSOR CsorCs[IFC_BANK_COUNT];
> + UINT8 Res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
> + IFC_FTIM FtimCs[IFC_BANK_COUNT];
> + UINT8 Res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
> + UINT32 RbStat;
> + UINT32 RbMap;
> + UINT32 WpMap;
> + UINT32 IfcGcr;
> + UINT32 Res7[0x2];
> + UINT32 CmEvter_stat;
> + UINT32 Res8[0x2];
> + UINT32 CmEvterEn;
> + UINT32 Res9[0x2];
> + UINT32 CmEvterIntrEn;
> + UINT32 Res10[0x2];
> + UINT32 CmErattr0;
> + UINT32 CmErattr1;
> + UINT32 Res11[0x2];
> + UINT32 IfcCcr;
> + UINT32 IfcCsr;
> + UINT32 DdrCcrLow;
> + UINT32 Res12[IFC_NAND_RESERVED_SIZE];
> + IFC_NAND IfcNand;
> + IFC_NOR IfcNor;
> + IFC_GPCM IfcGpcm;
> +} IFC_REGS;
> +
> +extern VOID GetIfcNorFlashTimings (IFC_TIMINGS * NorIfcTimings);
> +
> +extern VOID GetIfcFpgaTimings (IFC_TIMINGS *FpgaIfcTimings);
> +
> +extern VOID GetIfcNandFlashTimings (IFC_TIMINGS * NandIfcTimings);
> +
> +#endif //__IFC_LIB_H__
> diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.inf b/Silicon/NXP/Library/IfcLib/IfcLib.inf
> new file mode 100644
> index 0000000..170ed38
> --- /dev/null
> +++ b/Silicon/NXP/Library/IfcLib/IfcLib.inf
> @@ -0,0 +1,38 @@
> +# IfcLib.inf
> +#
> +# Component description file for IFC Library
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = IfcLib
> + FILE_GUID = a465d76c-0785-4ee7-bd72-767983d575a2
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = IfcLib
> +
> +[Sources.common]
> + IfcLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BoardLib
> + BeIoLib
> +
> +[FixedPcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index a73e9d5..43d0a71 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -77,6 +77,7 @@
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000128
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129
> gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0|UINT64|0x0000012B
>
> #
> # IFC PCDs
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 13/39] LS1043/FpgaLib : Add support for FpgaLib.
2018-02-16 8:50 ` [PATCH edk2-platforms 13/39] LS1043/FpgaLib : Add support for FpgaLib Meenakshi
@ 2018-04-18 18:43 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-18 18:43 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
On Fri, Feb 16, 2018 at 02:20:09PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> FpgaLib export FPGA_READ and FPGA_WRITE function and
> provide a function to print Board personality.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
If you send a new version, can you fix the indentation in the last few
DEBUG statements? If not, I can fix that up before committing.
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> .../NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h | 79 ++++++++++++
> .../NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c | 142 +++++++++++++++++++++
> .../NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 +++++
> 3 files changed, 252 insertions(+)
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h b/Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h
> new file mode 100644
> index 0000000..3f55a02
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h
> @@ -0,0 +1,79 @@
> +/** FpgaLib.h
> +* Header defining the LS1043a Fpga specific constants (Base addresses, sizes, flags)
> +*
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __LS1043A_FPGA_H__
> +#define __LS1043A_FPGA_H__
> +
> +/*
> + * FPGA register set of LS1043ARDB board-specific.
> + */
> +typedef struct {
> + UINT8 FpgaVersionMajor; /* 0x0 - FPGA Major Revision Register */
> + UINT8 FpgaVersionMinor; /* 0x1 - FPGA Minor Revision Register */
> + UINT8 PcbaVersion; /* 0x2 - PCBA Revision Register */
> + UINT8 SystemReset; /* 0x3 - system reset register */
> + UINT8 SoftMuxOn; /* 0x4 - Switch Control Enable Register */
> + UINT8 RcwSource1; /* 0x5 - Reset config word 1 */
> + UINT8 RcwSource2; /* 0x6 - Reset config word 1 */
> + UINT8 Vbank; /* 0x7 - Flash bank selection Control */
> + UINT8 SysclkSelect; /* 0x8 - System clock selection Control */
> + UINT8 UartSel; /* 0x9 - Uart selection Control */
> + UINT8 Sd1RefClkSel; /* 0xA - Serdes1 reference clock selection Control */
> + UINT8 TdmClkMuxSel; /* 0xB - TDM Clock Mux selection Control */
> + UINT8 SdhcSpiCsSel; /* 0xC - SDHC/SPI Chip select selection Control */
> + UINT8 StatusLed; /* 0xD - Status Led */
> + UINT8 GlobalReset; /* 0xE - Global reset */
> +} FPGA_REG_SET;
> +
> +UINT8
> +FpgaRead (
> + UINTN Reg
> + );
> +
> +VOID
> +FpgaWrite (
> + UINTN Reg,
> + UINT8 Value
> + );
> +
> +VOID
> +FpgaRevBit (
> + UINT8 *Value
> + );
> +
> +VOID
> +FpgaInit (
> + VOID
> + );
> +
> +VOID
> +PrintBoardPersonality (
> + VOID
> + );
> +
> +#define FPGA_BASE_PHYS 0x7fb00000
> +
> +#define SRC_VBANK 0x25
> +#define SRC_NAND 0x106
> +#define SRC_QSPI 0x44
> +#define SRC_SD 0x40
> +
> +#define SERDES_FREQ1 "100.00 MHz"
> +#define SERDES_FREQ2 "156.25 MHz"
> +
> +#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg))
> +#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), Value)
> +
> +#endif
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c b/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c
> new file mode 100644
> index 0000000..99d514d
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c
> @@ -0,0 +1,142 @@
> +/** @FpgaLib.c
> + Fpga Library for LS1043A-RDB board, containing functions to
> + program and read the Fpga registers.
> +
> + FPGA is connected to IFC Controller and so MMIO APIs are used
> + to read/write FPGA registers
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/FpgaLib.h>
> +#include <Library/IoLib.h>
> +
> +/**
> + Function to read FPGA register.
> +
> + @param Reg Register offset of FPGA to read.
> +
> +**/
> +UINT8
> +FpgaRead (
> + IN UINTN Reg
> + )
> +{
> + VOID *Base;
> +
> + Base = (VOID *)FPGA_BASE_PHYS;
> +
> + return MmioRead8 ((UINTN)(Base + Reg));
> +}
> +
> +/**
> + Function to write FPGA register.
> +
> + @param Reg Register offset of FPGA to write.
> + @param Value Value to be written.
> +
> +**/
> +VOID
> +FpgaWrite (
> + IN UINTN Reg,
> + IN UINT8 Value
> + )
> +{
> + VOID *Base;
> +
> + Base = (VOID *)FPGA_BASE_PHYS;
> +
> + MmioWrite8 ((UINTN)(Base + Reg), Value);
> +}
> +
> +/**
> + Function to reverse the number.
> +
> + @param *Value pointer to number to reverse.
> +
> + @retval *Value reversed value.
> +
> +**/
> +VOID
> +FpgaRevBit (
> + OUT UINT8 *Value
> + )
> +{
> + UINT8 Rev;
> + UINT8 Val;
> + UINTN Index;
> +
> + Val = *Value;
> + Rev = Val & 1;
> + for (Index = 1; Index <= 7; Index++) {
> + Val >>= 1;
> + Rev <<= 1;
> + Rev |= Val & 1;
> + }
> +
> + *Value = Rev;
> +}
> +
> +/**
> + Function to print board personality.
> +
> +**/
> +VOID
> +PrintBoardPersonality (
> + VOID
> + )
> +{
> + UINT8 RcwSrc1;
> + UINT8 RcwSrc2;
> + UINT32 RcwSrc;
> + UINT32 Sd1RefClkSel;
> +
> + RcwSrc1 = FPGA_READ(RcwSource1);
> + RcwSrc2 = FPGA_READ(RcwSource2);
> + FpgaRevBit (&RcwSrc1);
> + RcwSrc = RcwSrc1;
> + RcwSrc = (RcwSrc << 1) | RcwSrc2;
> +
> + switch (RcwSrc) {
> + case SRC_VBANK:
> + DEBUG ((DEBUG_INFO, "vBank: %d\n", FPGA_READ(Vbank)));
> + break;
> + case SRC_NAND:
> + DEBUG ((DEBUG_INFO, "NAND\n"));
> + break;
> + case SRC_QSPI:
> + DEBUG ((DEBUG_INFO, "QSPI vBank %d\n", FPGA_READ(Vbank)));
> + break;
> + case SRC_SD:
> + DEBUG ((DEBUG_INFO, "SD\n"));
> + break;
> + default:
> + DEBUG ((DEBUG_INFO, "Invalid setting of SW5\n"));
> + break;
> + }
> +
> + DEBUG ((DEBUG_INFO, "FPGA: V%x.%x\nPCBA: V%x.0\n",
> + FPGA_READ(FpgaVersionMajor),
> + FPGA_READ(FpgaVersionMinor),
> + FPGA_READ(PcbaVersion)));
> +
> + DEBUG ((DEBUG_INFO, "SERDES Reference Clocks:\n"));
> +
> + Sd1RefClkSel = FPGA_READ(Sd1RefClkSel);
> + DEBUG((DEBUG_INFO, "SD1_CLK1 = %a, SD1_CLK2 = %a\n",
> + Sd1RefClkSel ? SERDES_FREQ2 : SERDES_FREQ1, SERDES_FREQ1));
> +
> + return;
> +}
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
> new file mode 100644
> index 0000000..39e9bde
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
> @@ -0,0 +1,31 @@
> +# @FpgaLib.inf
> +#
> +# Copyright 2017 NXP
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001000A
> + BASE_NAME = FpgaLib
> + FILE_GUID = 5962d040-8b8a-11df-9a71-0002a5d5c51b
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = FpgaLib
> +
> +[Sources.common]
> + FpgaLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + IoLib
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 14/39] LS1043 : Enable support of FpgaLib.
2018-02-16 8:50 ` [PATCH edk2-platforms 14/39] LS1043 : Enable support of FpgaLib Meenakshi
@ 2018-04-18 18:43 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-18 18:43 UTC (permalink / raw)
To: Meenakshi
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Fri, Feb 16, 2018 at 02:20:10PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 3 +++
> Silicon/NXP/Chassis/Chassis2/Soc.c | 5 +++++
> Silicon/NXP/Chassis/LS1043aSocLib.inf | 2 ++
> Silicon/NXP/LS1043A/LS1043A.dsc | 2 ++
> 4 files changed, 12 insertions(+)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index 6e9e7e0..df4d917 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -38,6 +38,9 @@
> BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf
> SocLib|Silicon/NXP/Chassis/LS1043aSocLib.inf
> RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
> + IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
> + BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
> + FpgaLib|Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
>
> [PcdsFixedAtBuild.common]
>
> diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chassis2/Soc.c
> index 7f9f963..17de7e4 100644
> --- a/Silicon/NXP/Chassis/Chassis2/Soc.c
> +++ b/Silicon/NXP/Chassis/Chassis2/Soc.c
> @@ -18,6 +18,7 @@
> #include <Library/BaseLib.h>
> #include <Library/BaseMemoryLib/MemLibInternals.h>
> #include <Library/DebugLib.h>
> +#include <Library/IfcLib.h>
> #include <Library/IoLib.h>
> #include <Library/PcdLib.h>
> #include <Library/PrintLib.h>
> @@ -25,6 +26,8 @@
>
> #include "Soc.h"
>
> +extern VOID PrintBoardPersonality (VOID);
> +
> /**
> Calculate the frequency of various controllers and
> populate the passed structure with frequuencies.
> @@ -167,6 +170,8 @@ SocInit (
> //
> PrintRCW ();
> PrintSoc ();
> + IfcInit();
> + PrintBoardPersonality ();
>
> return;
> }
> diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS1043aSocLib.inf
> index 1b2f9c4..d01b353 100644
> --- a/Silicon/NXP/Chassis/LS1043aSocLib.inf
> +++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf
> @@ -31,6 +31,8 @@
> BaseLib
> BeIoLib
> DebugLib
> + FpgaLib
> + IfcLib
> SerialPortLib
>
> [Sources.common]
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc b/Silicon/NXP/LS1043A/LS1043A.dsc
> index 8395dfd..a4eb117 100644
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc
> @@ -63,11 +63,13 @@
> gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
>
> #
> # Big Endian IPs
> #
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
>
> ##
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 15/39] Silicon/NXP : Add support of NorFlashLib
2018-02-16 8:50 ` [PATCH edk2-platforms 15/39] Silicon/NXP : Add support of NorFlashLib Meenakshi
@ 2018-04-18 19:26 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-18 19:26 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
On Fri, Feb 16, 2018 at 02:20:11PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> NorFlashLib interacts with the underlying IFC NOR controller.
> This will be used by NOR driver for any information
> exchange with NOR controller.
Some of this looks generic CFI which should at some point be broken
out in its own library. Let's not worray about that for now, but I
wanted to mention it :)
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/Library/NorFlashLib.h | 77 +++
> Silicon/NXP/Include/NorFlash.h | 48 ++
> Silicon/NXP/Library/NorFlashLib/CfiCommand.h | 99 ++++
> Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c | 233 ++++++++
> Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h | 68 +++
> Silicon/NXP/Library/NorFlashLib/NorFlashLib.c | 660 +++++++++++++++++++++++
> Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf | 41 ++
> 7 files changed, 1226 insertions(+)
> create mode 100644 Silicon/NXP/Include/Library/NorFlashLib.h
> create mode 100644 Silicon/NXP/Include/NorFlash.h
> create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiCommand.h
> create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
> create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
> create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
> create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
>
> diff --git a/Silicon/NXP/Include/Library/NorFlashLib.h b/Silicon/NXP/Include/Library/NorFlashLib.h
> new file mode 100644
> index 0000000..defdc61
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/NorFlashLib.h
> @@ -0,0 +1,77 @@
> +/** @file
> +
> + Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
> + Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
> + Copyright 2017 NXP
> +
> +This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> + **/
> +
> +#ifndef _NOR_FLASH_LIB_H_
> +#define _NOR_FLASH_LIB_H_
> +
> +#include <NorFlash.h>
> +
> +#define NOR_FLASH_DEVICE_COUNT 1
> +
> +typedef struct {
> + UINTN DeviceBaseAddress; // Start address of the Device Base Address (DBA)
> + UINTN RegionBaseAddress; // Start address of one single region
> + UINTN Size;
> + UINTN BlockSize;
> + UINTN MultiByteWordCount; // Maximum Word count that can be written to Nor Flash in multi byte write
> + UINTN WordWriteTimeOut; // single byte/word timeout usec
> + UINTN BufferWriteTimeOut; // buffer write timeout usec
> + UINTN BlockEraseTimeOut; // block erase timeout usec
> + UINTN ChipEraseTimeOut; // chip erase timeout usec
> +} NorFlashDescription;
> +
> +EFI_STATUS
> +NorFlashPlatformGetDevices (
> + OUT NorFlashDescription **NorFlashDevices,
> + OUT UINT32 *Count
> + );
> +
> +EFI_STATUS
> +NorFlashPlatformFlashGetAttributes (
> + OUT NorFlashDescription *NorFlashDevices,
> + IN UINT32 Count
> + );
> +
> +EFI_STATUS
> +NorFlashPlatformWriteBuffer (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + );
> +
> +EFI_STATUS
> +NorFlashPlatformEraseSector (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN SectorAddress
> + );
> +
> +EFI_STATUS
> +NorFlashPlatformRead (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN UINTN BufferSizeInBytes,
> + OUT UINT8 *Buffer
> + );
> +
> +EFI_STATUS
> +NorFlashPlatformReset (
> + IN UINTN Instance
> + );
> +
> +#endif /* _NOR_FLASH_LIB_H_ */
> diff --git a/Silicon/NXP/Include/NorFlash.h b/Silicon/NXP/Include/NorFlash.h
> new file mode 100644
> index 0000000..888f5c1
> --- /dev/null
> +++ b/Silicon/NXP/Include/NorFlash.h
> @@ -0,0 +1,48 @@
> +/** @NorFlash.h
> +
> + Contains data structure shared by both NOR Library and Driver.
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __NOR_FLASH_H__
> +#define __NOR_FLASH_H__
> +
> +#include <Protocol/BlockIo.h>
> +#include <Protocol/FirmwareVolumeBlock.h>
> +
> +typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
> +typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Instance);
> +
> +typedef struct {
> + VENDOR_DEVICE_PATH Vendor;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} NOR_FLASH_DEVICE_PATH;
> +
> +struct _NOR_FLASH_INSTANCE {
> + UINT32 Signature;
> + EFI_HANDLE Handle;
> + BOOLEAN Initialized;
> + NOR_FLASH_INITIALIZE Initialize;
> + UINTN DeviceBaseAddress;
> + UINTN RegionBaseAddress;
> + UINTN Size;
> + EFI_LBA StartLba;
> + EFI_BLOCK_IO_PROTOCOL BlockIoProtocol;
> + EFI_BLOCK_IO_MEDIA Media;
> + BOOLEAN SupportFvb;
> + EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
> + VOID* ShadowBuffer;
> + NOR_FLASH_DEVICE_PATH DevicePath;
> +};
> +
> +
> +#endif /* __NOR_FLASH_H__ */
> diff --git a/Silicon/NXP/Library/NorFlashLib/CfiCommand.h b/Silicon/NXP/Library/NorFlashLib/CfiCommand.h
> new file mode 100644
> index 0000000..8543227
> --- /dev/null
> +++ b/Silicon/NXP/Library/NorFlashLib/CfiCommand.h
> @@ -0,0 +1,99 @@
> +/** @CfiCommand.h
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __CFI_COMMAND_H__
> +#define __CFI_COMMAND_H__
> +
> +// CFI Data "QRY"
> +#define CFI_QRY_Q 0x51
> +#define CFI_QRY_R 0x52
> +#define CFI_QRY_Y 0x59
> +#define CFI_QRY 0x515259
> +
> +#define ENTER_CFI_QUERY_MODE_ADDR 0x0055
> +#define ENTER_CFI_QUERY_MODE_CMD 0x0098
> +
> +#define CFI_QUERY_UNIQUE_QRY_STRING 0x10
> +
> +// Offsets for CFI queries
> +#define CFI_QUERY_TYP_TIMEOUT_WORD_WRITE 0x1F
> +#define CFI_QUERY_TYP_TIMEOUT_MAX_BUFFER_WRITE 0x20
> +#define CFI_QUERY_TYP_TIMEOUT_BLOCK_ERASE 0x21
> +#define CFI_QUERY_TYP_TIMEOUT_CHIP_ERASE 0x22
> +#define CFI_QUERY_MAX_TIMEOUT_WORD_WRITE 0x23
> +#define CFI_QUERY_MAX_TIMEOUT_MAX_BUFFER_WRITE 0x24
> +#define CFI_QUERY_MAX_TIMEOUT_BLOCK_ERASE 0x25
> +#define CFI_QUERY_MAX_TIMEOUT_CHIP_ERASE 0x26
> +#define CFI_QUERY_DEVICE_SIZE 0x27
> +#define CFI_QUERY_MAX_NUM_BYTES_WRITE 0x2A
> +#define CFI_QUERY_BLOCK_SIZE 0x2F
> +
> +// Unlock Address
> +#define CMD_UNLOCK_1_ADDR 0x555
> +#define CMD_UNLOCK_2_ADDR 0x2AA
> +
> +// RESET Command
> +#define CMD_RESET_FIRST 0xAA
> +#define CMD_RESET_SECOND 0x55
> +#define CMD_RESET 0xF0
> +
> +// READ Command
> +
> +// Manufacturer ID
> +#define CMD_READ_M_ID_FIRST 0xAA
> +#define CMD_READ_M_ID_SECOND 0x55
> +#define CMD_READ_M_ID_THIRD 0x90
> +#define CMD_READ_M_ID_FOURTH 0x01
> +
> +// Device ID
> +#define CMD_READ_D_ID_FIRST 0xAA
> +#define CMD_READ_D_ID_SECOND 0x55
> +#define CMD_READ_D_ID_THIRD 0x90
> +#define CMD_READ_D_ID_FOURTH 0x7E
> +#define CMD_READ_D_ID_FIFTH 0x13
> +#define CMD_READ_D_ID_SIXTH 0x00
> +
> +// WRITE Command
> +
> +// PROGRAM Command
> +#define CMD_PROGRAM_FIRST 0xAA
> +#define CMD_PROGRAM_SECOND 0x55
> +#define CMD_PROGRAM_THIRD 0xA0
> +
> +// Write Buffer Command
> +#define CMD_WRITE_TO_BUFFER_FIRST 0xAA
> +#define CMD_WRITE_TO_BUFFER_SECOND 0x55
> +#define CMD_WRITE_TO_BUFFER_THIRD 0x25
> +#define CMD_WRITE_TO_BUFFER_CONFIRM 0x29
> +
> +// ERASE Command
> +
> +// UNLOCK COMMANDS FOR ERASE
> +#define CMD_ERASE_FIRST 0xAA
> +#define CMD_ERASE_SECOND 0x55
> +#define CMD_ERASE_THIRD 0x80
> +#define CMD_ERASE_FOURTH 0xAA
> +#define CMD_ERASE_FIFTH 0x55
> +
> +// Chip Erase Command
> +#define CMD_CHIP_ERASE_SIXTH 0x10
> +
> +// Sector Erase Command
> +#define CMD_SECTOR_ERASE_SIXTH 0x30
> +
> +// SUSPEND Command
> +#define CMD_PROGRAM_OR_ERASE_SUSPEND 0xB0
> +#define CMD_PROGRAM_OR_ERASE_RESUME 0x30
> +
> +#endif // __CFI_COMMAND_H__
> diff --git a/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
> new file mode 100644
> index 0000000..632e943
> --- /dev/null
> +++ b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
> @@ -0,0 +1,233 @@
> +/** @CfiNorFlashLib.c
> +
> + Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> + **/
> +
> +#include <PiDxe.h>
> +#include <Library/ArmLib.h>
> +#include <Library/BaseLib.h>
> +
> +#include "CfiCommand.h"
> +#include "CfiNorFlashLib.h"
> +
> +FLASH_DATA
> +IfcNorFlashData (
> + IN OUT FLASH_DATA Value
> + )
> +{
> + if (FixedPcdGetBool (PcdIfcBigEndian)) {
> + return SwapBytes16 (Value);
> + } else {
> + return Value;
> + }
> +}
> +
> +/**
> + Write Val at given address.
> +
> + @param Val Data to be written.
> + @param Addr Address where data is to be written.
> +
> +**/
> +VOID
> +FlashWriteData (
> + IN FLASH_DATA Val,
> + IN UINTN Addr
> + )
> +{
> + *(volatile FLASH_DATA *)(Addr) = (Val);
> +}
> +
> +/**
> + Check endianness of IFC Controller and depending on swap
> + the data and write on given address.
> +
> + @param Val Data to be written.
> + @param Addr Address where data is to be written.
> +
> +**/
> +VOID
> +FlashWrite (
> + IN FLASH_DATA Val,
> + IN UINTN Addr
> + )
> +{
> + FLASH_DATA ShiftVal;
> +
> + ShiftVal = IfcNorFlashData (Val);
> +
> + *(volatile FLASH_DATA *)(Addr) = (ShiftVal);
> +}
> +
> +/**
> + Read data from given address.
> +
> + @param Addr Address from where data is to be read.
> +
> + @return Read Data
> +**/
> +FLASH_DATA
> +FlashReadData (
> + IN UINTN Addr
> + )
> +{
> + FLASH_DATA Val;
> +
> + Val = *(volatile FLASH_DATA *)(Addr);
> +
> + return (Val);
> +}
> +
> +/**
> + Read data from given address and depending on endianness of IFC Controller
> + swap the read data.
> +
> + @param Addr Address from where data is to be read.
> +
> + @return Read Data
> +**/
> +FLASH_DATA
> +FlashRead (
> + IN UINTN Addr
> + )
> +{
> + FLASH_DATA Val;
> + FLASH_DATA ShiftVal;
> +
> + Val = *(volatile FLASH_DATA *)(Addr);
> + ShiftVal = IfcNorFlashData (Val);
> +
> + return (ShiftVal);
> +}
Instead of the above, please use same mechanisms as watchdog, gur(?), ifc.
> +
> +STATIC
> +VOID
> +NorFlashReadCfiData (
> + IN UINTN DeviceBaseAddress,
> + IN UINTN CfiOffset,
> + IN UINT32 NumberOfShorts,
> + OUT VOID *Data
> + )
> +{
> + UINT32 Count;
> + FLASH_DATA *TmpData = (FLASH_DATA *)Data;
> +
> + for (Count = 0; Count < NumberOfShorts; Count++, TmpData++) {
> + *TmpData = FLASH_READ ((UINTN)((FLASH_DATA*)DeviceBaseAddress + CfiOffset));
> + CfiOffset++;
> + }
> +}
> +
> +/*
> + Currently we support only CFI flash devices; Bail-out otherwise
> +*/
> +EFI_STATUS
> +CfiNorFlashFlashGetAttributes (
> + OUT NorFlashDescription *NorFlashDevices,
> + IN UINT32 Index
> + )
> +{
> + UINT32 Count;
> + FLASH_DATA QryData[3];
> + FLASH_DATA BlockSize[2];
> + UINTN DeviceBaseAddress;
> + FLASH_DATA MaxNumBytes[2];
> + FLASH_DATA Size;
> + FLASH_DATA HighByteMask; // Masks High byte in a UIN16 word
> + FLASH_DATA HighByteShift; // Bitshifts needed to make a byte High Byte in a UIN16 word
> + FLASH_DATA Temp1;
> + FLASH_DATA Temp2;
> +
> + HighByteMask = 0xFF;
> + HighByteShift = 8;
> +
> + for (Count = 0; Count < Index; Count++) {
> +
> + NorFlashDevices[Count].DeviceBaseAddress = DeviceBaseAddress = PcdGet64 (PcdFlashDeviceBase64);
> +
> + // Reset flash first
> + NorFlashPlatformReset (DeviceBaseAddress);
> +
> + // Enter the CFI Query Mode
> + SEND_NOR_COMMAND (DeviceBaseAddress, ENTER_CFI_QUERY_MODE_ADDR,
> + ENTER_CFI_QUERY_MODE_CMD);
Indentation.
> +
> + ArmDataSynchronizationBarrier ();
I would prefer the use of a MemoryFence() here.
In fact, ArmDataSynchronizationBarrier () is inappropriate in this
location anyway.
> +
> + // Query the unique QRY
> + NorFlashReadCfiData (DeviceBaseAddress,
> + CFI_QUERY_UNIQUE_QRY_STRING,
> + 3,
What's 3 here? Could it be replaced by a macro or define?
> + &QryData);
Indentation.
Please have a look throughout this file.
> + if (QryData[0] != (FLASH_DATA)CFI_QRY_Q || QryData[1] !=
> + (FLASH_DATA)CFI_QRY_R || QryData[2] != (FLASH_DATA)CFI_QRY_Y ) {
Some added parentheses please.
> + DEBUG ((DEBUG_ERROR, "Not a CFI flash (QRY not recvd): "
> + "Got = 0x%04x, 0x%04x, 0x%04x\n",
> + QryData[0], QryData[1], QryData[2]));
> + return EFI_DEVICE_ERROR;
> + }
> +
> + NorFlashReadCfiData (DeviceBaseAddress, CFI_QUERY_DEVICE_SIZE,
> + 1, &Size);
What's 1 here? Could it be replaced by a macro or define?
> + // Refer CFI Specification
> + NorFlashDevices[Count].Size = 1 << Size;
> +
> + NorFlashReadCfiData (DeviceBaseAddress, CFI_QUERY_BLOCK_SIZE,
> + 2, &BlockSize);
What's 2 here? Could it be replaced by a macro or define?
> + // Refer CFI Specification
> + NorFlashDevices[Count].BlockSize = 256 * ((FLASH_DATA) ((BlockSize[1] <<
What's 256 here? Could it be replaced by a macro or define?
> + HighByteShift) | (BlockSize[0] & HighByteMask)));
> +
> + NorFlashReadCfiData (DeviceBaseAddress,
> + CFI_QUERY_MAX_NUM_BYTES_WRITE, 2, &MaxNumBytes);
> + // Refer CFI Specification
> + /* from CFI query we get the Max. number of BYTE in multi-byte write = 2^N.
> + But our Flash Library is able to read/write in WORD size (2 bytes) which
> + is why we need to CONVERT MAX BYTES TO MAX WORDS by diving it by
> + width of word size */
> + NorFlashDevices[Count].MultiByteWordCount =\
> + (1 << ((FLASH_DATA)((MaxNumBytes[1] << HighByteShift) |
> + (MaxNumBytes[0] & HighByteMask))))/sizeof(FLASH_DATA);
> +
> + NorFlashReadCfiData (DeviceBaseAddress,
> + CFI_QUERY_TYP_TIMEOUT_WORD_WRITE, 1, &Temp1);
> + NorFlashReadCfiData (DeviceBaseAddress,
> + CFI_QUERY_MAX_TIMEOUT_WORD_WRITE, 1, &Temp2);
What's 1 here? Could it be replaced by a macro or define?
(Same question repeated throughout.)
> + NorFlashDevices[Count].WordWriteTimeOut = (1U << Temp1) * (1U << Temp2);
> +
> + NorFlashReadCfiData (DeviceBaseAddress,
> + CFI_QUERY_TYP_TIMEOUT_MAX_BUFFER_WRITE, 1, &Temp1);
> + NorFlashReadCfiData (DeviceBaseAddress,
> + CFI_QUERY_MAX_TIMEOUT_MAX_BUFFER_WRITE, 1, &Temp2);
> + NorFlashDevices[Count].BufferWriteTimeOut = (1U << Temp1) * (1U << Temp2);
> +
> + NorFlashReadCfiData (DeviceBaseAddress,
> + CFI_QUERY_TYP_TIMEOUT_BLOCK_ERASE, 1, &Temp1);
> + NorFlashReadCfiData (DeviceBaseAddress,
> + CFI_QUERY_MAX_TIMEOUT_BLOCK_ERASE, 1, &Temp2);
> + NorFlashDevices[Count].BlockEraseTimeOut =
> + (1U << Temp1) * (1U << Temp2) * 1000;
* 1000 - microseconds to milliseconds?
> +
> + NorFlashReadCfiData (DeviceBaseAddress,
> + CFI_QUERY_TYP_TIMEOUT_CHIP_ERASE, 1, &Temp1);
> + NorFlashReadCfiData (DeviceBaseAddress,
> + CFI_QUERY_MAX_TIMEOUT_CHIP_ERASE, 1, &Temp2);
> + NorFlashDevices[Count].ChipEraseTimeOut =
> + (1U << Temp1) * (1U << Temp2) * 1000;
> +
> + // Put device back into Read Array mode (via Reset)
> + NorFlashPlatformReset (DeviceBaseAddress);
> + }
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
> new file mode 100644
> index 0000000..91d50f0
> --- /dev/null
> +++ b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
> @@ -0,0 +1,68 @@
> +/** @CfiNorFlashLib.h
> +
> + Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __CFI_NOR_FLASH_LIB_H__
> +#define __CFI_NOR_FLASH_LIB_H__
> +
> +#include <Library/DebugLib.h>
> +#include <Library/NorFlashLib.h>
> +
> +/*
> + * Values for the width of the port
> + */
> +#define FLASH_CFI_8BIT 0x01
> +#define FLASH_CFI_16BIT 0x02
> +#define FLASH_CFI_32BIT 0x04
> +#define FLASH_CFI_64BIT 0x08
> +
> +#define CREATE_BYTE_OFFSET(OffsetAddr) ((sizeof (FLASH_DATA)) * (OffsetAddr))
> +#define CREATE_NOR_ADDRESS(BaseAddr, OffsetAddr) ((BaseAddr) + (OffsetAddr))
> +#define FLASH_READ(Addr) FlashRead ((Addr))
> +#define FLASH_WRITE(Addr, Val) FlashWrite ((Val), (Addr))
> +#define FLASH_READ_DATA(Addr) FlashReadData ((Addr))
> +#define FLASH_WRITE_DATA(Addr, Val) FlashWriteData ((Val), (Addr))
> +#define SEND_NOR_COMMAND(BaseAddr, Offset, Cmd) FLASH_WRITE (CREATE_NOR_ADDRESS (BaseAddr, CREATE_BYTE_OFFSET (Offset)), (Cmd))
> +
> +typedef UINT16 FLASH_DATA;
> +
> +VOID
> +FlashWrite (
> + IN FLASH_DATA Val,
> + IN UINTN Addr
> + );
> +
> +FLASH_DATA
> +FlashRead (
> + IN UINTN Addr
> + );
> +
> +VOID
> +FlashWriteData (
> + IN FLASH_DATA Val,
> + IN UINTN Addr
> + );
> +
> +FLASH_DATA
> +FlashReadData (
> + IN UINTN Addr
> + );
> +
> +EFI_STATUS
> +CfiNorFlashFlashGetAttributes (
> + OUT NorFlashDescription *NorFlashDevices,
> + IN UINT32 Index
> + );
> +
> +#endif //__CFI_NOR_FLASH_LIB_H__
> diff --git a/Silicon/NXP/Library/NorFlashLib/NorFlashLib.c b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
> new file mode 100644
> index 0000000..b74e9eb
> --- /dev/null
> +++ b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
> @@ -0,0 +1,660 @@
> +/** @NorFlashLib.c
> +
> + Based on NorFlash implementation available in NorFlashDxe.c
> +
> + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
> + Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <Library/BaseMemoryLib/MemLibInternals.h>
> +#include <Library/TimerLib.h>
> +
> +#include "CfiCommand.h"
> +#include "CfiNorFlashLib.h"
> +
> +#define GET_BLOCK_OFFSET(Lba) ((Instance->RegionBaseAddress)-\
> + (Instance->DeviceBaseAddress)+((UINTN)((Lba) * Instance->Media.BlockSize)))
> +
> +NorFlashDescription mNorFlashDevices[NOR_FLASH_DEVICE_COUNT];
> +
> +STATIC VOID
> +UnlockEraseAddress (
> + IN UINTN DeviceBaseAddress
> + )
> +{ // Issue the Unlock cmds
> + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR,
> + CMD_ERASE_FIRST);
Indentation.
> +
> + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR,
> + CMD_ERASE_SECOND);
> +
> + // Issue a setup command
> + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR,
> + CMD_ERASE_THIRD);
> +
> + // Issue the Unlock cmds
> + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR,
> + CMD_ERASE_FOURTH);
> +
> + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR,
> + CMD_ERASE_FIFTH);
> +
> + return;
> +}
> +
> +STATIC
> +UINT64
> +ConvertMicroSecondsToTicks (
> + IN UINTN MicroSeconds
> + )
> +{
> + UINT64 TimerTicks64;
> +
> + TimerTicks64 = 0;
> +
> + // Calculate counter ticks that represent requested delay:
> + // = MicroSeconds x TICKS_PER_MICRO_SEC
> + // = MicroSeconds x Timer Frequency(in Hz) x 10^-6
> + // GetPerformanceCounterProperties = Get Arm Timer Frequency in Hz
> + TimerTicks64 = DivU64x32 (
> + MultU64x64 (
> + MicroSeconds,
> + GetPerformanceCounterProperties (NULL, NULL)
> + ),
> + 1000000U
> + );
> + return TimerTicks64;
> +}
> +
> +/**
> + * The following function erases a NOR flash sector.
> + **/
> +EFI_STATUS
> +NorFlashPlatformEraseSector (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN SectorAddress
> + )
> +{
> + FLASH_DATA EraseStatus1;
> + FLASH_DATA EraseStatus2;
> + UINT64 Timeout;
> + UINT64 SystemCounterVal;
> +
> + EraseStatus1 = 0;
> + EraseStatus2 = 0;
> + Timeout = 0;
> +
> + Timeout = ConvertMicroSecondsToTicks (
> + mNorFlashDevices[Instance->Media.MediaId].BlockEraseTimeOut);
Indentation.
> + // Request a sector erase by writing two unlock cycles, followed by a
> + // setup command and two additional unlock cycles
> +
> + UnlockEraseAddress (Instance->DeviceBaseAddress);
> +
> + // Now send the address of the sector to be erased
> + SEND_NOR_COMMAND (SectorAddress, 0, CMD_SECTOR_ERASE_SIXTH);
> +
> + // Wait for erase to complete
> + // Read Sector start address twice to detect bit toggle and to
> + // determine ERASE DONE (all bits are 1)
> + // Get the maximum timer ticks needed to complete the operation
> + // Check if operation is complete or not in continous loop?
> + // if complete, exit from loop
> + // if not check the ticks that have been passed from the begining of loop
> + // if Maximum Ticks allocated for operation has passed exit from loop
> +
> + SystemCounterVal = GetPerformanceCounter ();
> + Timeout += SystemCounterVal;
> + while (SystemCounterVal < Timeout) {
> + if ((EraseStatus1 = FLASH_READ (SectorAddress)) ==
> + (EraseStatus2 = FLASH_READ (SectorAddress))) {
Indentation.
> + if (0xFFFF == FLASH_READ (SectorAddress)) {
No jeopardy compares, please.
if (FLASH_READ (SectorAddress) == 0xFFFF) {
> + break;
> + }
> + }
> + SystemCounterVal = GetPerformanceCounter ();
> + }
> +
> + if (SystemCounterVal >= Timeout) {
> + DEBUG ((DEBUG_ERROR, "%a :Failed to Erase @ SectorAddress 0x%p, Timeout\n",
> + __FUNCTION__, SectorAddress));
> + return EFI_DEVICE_ERROR;
> + } else {
> + return EFI_SUCCESS;
> + }
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformWriteWord (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN WordOffset,
> + IN FLASH_DATA Word
> + )
> +{
> + UINT64 Timeout;
> + UINTN TargetAddress;
> + UINT64 SystemCounterVal;
> + FLASH_DATA Read1;
> + FLASH_DATA Read2;
> +
> + Timeout = 0;
> +
> + Timeout = ConvertMicroSecondsToTicks (
> + mNorFlashDevices[Instance->Media.MediaId].WordWriteTimeOut);
> +
> + TargetAddress = CREATE_NOR_ADDRESS (Instance->DeviceBaseAddress,
> + CREATE_BYTE_OFFSET (WordOffset));
> +
> + // Issue the Unlock cmds
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR,
> + CMD_PROGRAM_FIRST);
> +
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_2_ADDR,
> + CMD_PROGRAM_SECOND);
> +
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR,
> + CMD_PROGRAM_THIRD);
> +
> + FLASH_WRITE_DATA (TargetAddress, Word);
> +
> + // Wait for Write to Complete
> + // Read the last written address twice to detect bit toggle and
> + // to determine if date is wriiten successfully or not ?
> + // Get the maximum timer ticks needed to complete the operation
> + // Check if operation is complete or not in continous loop?
> + // if complete, exit from loop
> + // if not check the ticks that have been passed from the begining of loop
> + // if Maximum Ticks allocated for operation has passed, then exit from loop
> +
> + SystemCounterVal = GetPerformanceCounter ();
> + Timeout += SystemCounterVal;
> + while (SystemCounterVal < Timeout) {
> + if ((Read1 = FLASH_READ_DATA (TargetAddress)) ==
> + (Read2 = FLASH_READ_DATA (TargetAddress))) {
Indentation.
> + if (Word == FLASH_READ_DATA (TargetAddress)) {
> + break;
> + }
> + }
> + SystemCounterVal = GetPerformanceCounter ();
> + }
> +
> + if (SystemCounterVal >= Timeout) {
> + DEBUG ((DEBUG_ERROR, "%a: Failed to Write @ TargetAddress 0x%p, Timeout\n",
> + __FUNCTION__, TargetAddress));
> + return EFI_DEVICE_ERROR;
> + } else {
> + return EFI_SUCCESS;
> + }
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformWritePageBuffer (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN PageBufferOffset,
> + IN UINTN NumWords,
> + IN FLASH_DATA *Buffer
> + )
> +{
> + UINT64 Timeout;
> + UINTN LastWrittenAddress;
> + FLASH_DATA LastWritenData;
> + UINTN CurrentOffset;
> + UINTN EndOffset;
> + UINTN TargetAddress;
> + UINT64 SystemCounterVal;
> + FLASH_DATA Read1;
> + FLASH_DATA Read2;
> +
> + // Initialize variables
> + Timeout = 0;
> + LastWrittenAddress = 0;
> + LastWritenData = 0;
> + CurrentOffset = PageBufferOffset;
> + EndOffset = PageBufferOffset + NumWords - 1;
> + Timeout = ConvertMicroSecondsToTicks (
> + mNorFlashDevices[Instance->Media.MediaId].BufferWriteTimeOut);
> + TargetAddress = CREATE_NOR_ADDRESS (Instance->DeviceBaseAddress,
> + CREATE_BYTE_OFFSET (CurrentOffset));
> +
> + // don't try with a count of zero
> + if (!NumWords) {
> + return EFI_SUCCESS;
> + }
> + else if (NumWords == 1) {
else on same line as }
> + return NorFlashPlatformWriteWord (Instance, PageBufferOffset, *Buffer);
> + }
> +
> + // Issue the Unlock cmds
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR,
> + CMD_WRITE_TO_BUFFER_FIRST);
> +
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_2_ADDR,
> + CMD_WRITE_TO_BUFFER_SECOND);
> +
> + // Write the buffer load
> + SEND_NOR_COMMAND (TargetAddress, 0, CMD_WRITE_TO_BUFFER_THIRD);
> +
> + // Write # of locations to program
> + SEND_NOR_COMMAND (TargetAddress, 0, (NumWords - 1));
> +
> + // Load Data into Buffer
> + while (CurrentOffset <= EndOffset) {
> + LastWrittenAddress = CREATE_NOR_ADDRESS (Instance->DeviceBaseAddress,
> + CREATE_BYTE_OFFSET (CurrentOffset++));
> + LastWritenData = *Buffer++;
> +
> + // Write Data
> + FLASH_WRITE_DATA (LastWrittenAddress,LastWritenData);
> + }
> +
> + // Issue the Buffered Program Confirm command
> + SEND_NOR_COMMAND (TargetAddress, 0, CMD_WRITE_TO_BUFFER_CONFIRM);
> +
> + /* Wait for Write to Complete
> + Read the last written address twice to detect bit toggle and
> + to determine if date is wriiten successfully or not ?
> + Get the maximum timer ticks needed to complete the operation
> + Check if operation is complete or not in continous loop?
> + if complete, exit from loop
> + if not check the ticks that have been passed from the begining of loop
> + if Maximum Ticks allocated for operation has passed, then exit from loop **/
> + SystemCounterVal = GetPerformanceCounter();
> + Timeout += SystemCounterVal;
> + while (SystemCounterVal < Timeout) {
> + if ((Read1 = FLASH_READ_DATA (LastWrittenAddress)) ==
> + (Read2 = FLASH_READ_DATA (LastWrittenAddress))) {
Indentation.
> + if (LastWritenData == FLASH_READ_DATA (LastWrittenAddress)) {
> + break;
> + }
> + }
> + SystemCounterVal = GetPerformanceCounter ();
> + }
> +
> + if (SystemCounterVal >= Timeout) {
> + DEBUG ((DEBUG_ERROR, "%a: Failed to Write @LastWrittenAddress 0x%p, Timeout\n",
> + __FUNCTION__, LastWrittenAddress));
> + return EFI_DEVICE_ERROR;
> + } else {
> + return EFI_SUCCESS;
> + }
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformWriteWordAlignedAddressBuffer (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN Offset,
> + IN UINTN NumWords,
> + IN FLASH_DATA *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINTN MultiByteWordCount;
> + UINTN Mask;
> + UINTN IntWords;
> +
> + MultiByteWordCount = mNorFlashDevices[Instance->Media.MediaId].MultiByteWordCount;
> + Mask = MultiByteWordCount - 1;
> + IntWords = NumWords;
> + Status = EFI_SUCCESS;
> +
> + if (Offset & Mask) {
> + // program only as much as necessary, so pick the lower of the two numbers
> + if (NumWords < (MultiByteWordCount - (Offset & Mask))) {
> + IntWords = NumWords;
> + } else {
> + IntWords = MultiByteWordCount - (Offset & Mask);
> + }
> +
> + // program the first few to get write buffer aligned
> + Status = NorFlashPlatformWritePageBuffer (Instance, Offset, IntWords, Buffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + Offset += IntWords; // adjust pointers and counter
> + NumWords -= IntWords;
> + Buffer += IntWords;
> +
> + if (NumWords == 0) {
> + return Status;
> + }
> + }
> +
> + while (NumWords >= MultiByteWordCount) {// while big chunks to do
> + Status = NorFlashPlatformWritePageBuffer (Instance, Offset,
> + MultiByteWordCount, Buffer);
> + if (EFI_ERROR (Status)) {
> + return (Status);
> + }
> +
> + Offset += MultiByteWordCount; // adjust pointers and counter
> + NumWords -= MultiByteWordCount;
> + Buffer += MultiByteWordCount;
> + }
> + if (NumWords == 0) {
> + return (Status);
> + }
> +
> + Status = NorFlashPlatformWritePageBuffer (Instance, Offset, NumWords, Buffer);
> + return (Status);
> +}
> +
> +/**
> + Writes data to the NOR Flash using the Buffered Programming method.
> +
> + Write Buffer Programming allows the system to write a maximum of 32 bytes
> + in one programming operation. Therefore this function will only handle
> + buffers up to 32 bytes.
> + To deal with larger buffers, call this function again.
> +**/
> +EFI_STATUS
> +NorFlashPlatformWriteBuffer (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + FLASH_DATA *SrcBuffer;
> + UINTN TargetOffsetinBytes;
> + UINTN WordsToWrite;
> + UINTN Mask;
> + UINTN BufferSizeInBytes;
> + UINTN IntBytes;
> + UINT8 *CopyFrom;
> + UINT8 *CopyTo;
VOID* (x2)
> + FLASH_DATA TempWrite;
> +
> + SrcBuffer = (FLASH_DATA *)Buffer;
> + TargetOffsetinBytes = 0;
> + WordsToWrite = 0;
> + Mask = sizeof (FLASH_DATA) - 1;
> + BufferSizeInBytes = *NumBytes;
> + IntBytes = BufferSizeInBytes; // Intermediate Bytes needed to copy for alignment
> + TempWrite = 0;
> +
> + DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=%ld, Offset=0x%x, "
> + "*NumBytes=0x%x, Buffer @ 0x%08x)\n",
> + __FUNCTION__, Lba, Offset, *NumBytes, Buffer));
> +
> + TargetOffsetinBytes = GET_BLOCK_OFFSET (Lba) + (UINTN)(Offset);
> +
> + if (TargetOffsetinBytes & Mask) {
> + // Write only as much as necessary, so pick the lower of the two numbers
> + // and call it Intermediate bytes to write to make alignment proper
> + if (BufferSizeInBytes < (sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask))) {
> + IntBytes = BufferSizeInBytes;
> + } else {
> + IntBytes = sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask);
> + }
> +
> + // Read the first few to get Read buffer aligned
> + NorFlashPlatformRead (Instance, Lba, (TargetOffsetinBytes & ~Mask) -
> + GET_BLOCK_OFFSET (Lba), sizeof (TempWrite), (UINT8*)&TempWrite);
> +
> + CopyTo = (UINT8*)&TempWrite;
> + CopyTo += (TargetOffsetinBytes & Mask);
> + CopyFrom = (UINT8*)Buffer;
> +
> + InternalMemCopyMem (CopyTo, CopyFrom, IntBytes);
Please use CopyMem instead.
> +
> + Status = NorFlashPlatformWriteWordAlignedAddressBuffer (
> + Instance,
> + (UINTN)((TargetOffsetinBytes & ~Mask) / sizeof (FLASH_DATA)),
> + 1,
> + &TempWrite);
> + if (EFI_ERROR (Status)) {
> + DEBUG((DEBUG_ERROR, "%a : Failed to Write @TargetOffset 0x%x (0x%x)\n",
> + __FUNCTION__, TargetOffsetinBytes, Status));
> + goto EXIT;
> + }
> +
> + TargetOffsetinBytes += IntBytes; /* adjust pointers and counter */
> + BufferSizeInBytes -= IntBytes;
> + Buffer += IntBytes;
> +
> + if (BufferSizeInBytes == 0) {
> + goto EXIT;
> + }
> + }
> +
> + // Write the bytes to CFI width aligned address.
> + // Note we can Write number of bytes=CFI width in one operation
> + WordsToWrite = BufferSizeInBytes/sizeof (FLASH_DATA);
> + SrcBuffer = (FLASH_DATA*)Buffer;
> +
> + Status = NorFlashPlatformWriteWordAlignedAddressBuffer (
> + Instance,
> + (UINTN)(TargetOffsetinBytes/sizeof (FLASH_DATA)),
> + WordsToWrite,
> + SrcBuffer);
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a : Failed to Write @ TargetOffset 0x%x (0x%x)\n",
> + __FUNCTION__, TargetOffsetinBytes, Status));
> + goto EXIT;
> + }
> +
> + BufferSizeInBytes -= (WordsToWrite * sizeof (FLASH_DATA));
> + Buffer += (WordsToWrite*sizeof (FLASH_DATA));
> + TargetOffsetinBytes += (WordsToWrite * sizeof (FLASH_DATA));
> +
> + if (BufferSizeInBytes == 0) {
> + goto EXIT;
> + }
> +
> + // Now Write bytes that are remaining and are less than CFI width.
> + // Read the first few to get Read buffer aligned
> + NorFlashPlatformRead (
> + Instance,
> + Lba,
> + TargetOffsetinBytes - GET_BLOCK_OFFSET (Lba),
> + sizeof (TempWrite),
> + (UINT8*)&TempWrite);
> +
> + CopyFrom = (UINT8*)Buffer;
> + CopyTo = (UINT8*)&TempWrite;
> +
> + InternalMemCopyMem (CopyTo, CopyFrom, BufferSizeInBytes);
Please use CopyMem instead.
> +
> + Status = NorFlashPlatformWriteWordAlignedAddressBuffer (Instance,
> + (UINTN)(TargetOffsetinBytes/sizeof (FLASH_DATA)),
> + 1,
> + &TempWrite);
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a: Failed to Write @TargetOffset 0x%x Status=%d\n",
> + __FUNCTION__, TargetOffsetinBytes, Status));
> + goto EXIT;
> + }
> +
> +EXIT:
> + // Put device back into Read Array mode (via Reset)
> + NorFlashPlatformReset (Instance->DeviceBaseAddress);
> + return (Status);
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformRead (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN UINTN BufferSizeInBytes,
> + OUT UINT8 *Buffer
> + )
> +{
> + UINTN IntBytes;
> + UINTN Mask;
> + FLASH_DATA TempRead;
> + UINT8 *CopyFrom;
> + UINT8 *CopyTo;
Don't use UINT8* where VOID* is intended.
> + UINTN TargetOffsetinBytes;
> + FLASH_DATA *ReadData;
> + UINTN BlockSize;
> +
> + IntBytes = BufferSizeInBytes; //Intermediate Bytes needed to copy for alignment
> + Mask = sizeof (FLASH_DATA) - 1;
> + TempRead = 0;
> + TargetOffsetinBytes = (UINTN)(GET_BLOCK_OFFSET (Lba) + Offset);
> + BlockSize = Instance->Media.BlockSize;
> +
> + DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=%ld, Offset=0x%x,"
> + " BufferSizeInBytes=0x%x, Buffer @ 0x%p)\n",
> + __FUNCTION__, Lba, Offset, BufferSizeInBytes, Buffer));
> +
> + // The buffer must be valid
> + if (Buffer == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Return if we have not any byte to read
> + if (BufferSizeInBytes == 0) {
> + return EFI_SUCCESS;
> + }
> +
> + if (((Lba * BlockSize) + BufferSizeInBytes) > Instance->Size) {
> + DEBUG ((DEBUG_ERROR, "%a : Read will exceed device size.\n", __FUNCTION__));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Put device back into Read Array mode (via Reset)
> + NorFlashPlatformReset (Instance->DeviceBaseAddress);
> +
> + // First Read bytes to make buffer aligned to CFI width
> + if (TargetOffsetinBytes & Mask) {
> + // Read only as much as necessary, so pick the lower of the two numbers
> + if (BufferSizeInBytes < (sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask))) {
> + IntBytes = BufferSizeInBytes;
> + } else {
> + IntBytes = sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask);
> + }
> +
> + // Read the first few to get Read buffer aligned
> + TempRead = FLASH_READ_DATA (CREATE_NOR_ADDRESS (
> + Instance->DeviceBaseAddress,
> + CREATE_BYTE_OFFSET ((TargetOffsetinBytes & ~Mask)/sizeof (FLASH_DATA))));
> +
> + CopyFrom = (UINT8*)&TempRead;
> + CopyFrom += (TargetOffsetinBytes & Mask);
> + CopyTo = (UINT8*)Buffer;
That way you can also get rid of these casts.
> +
> + InternalMemCopyMem (CopyTo, CopyFrom, IntBytes);
Please use CopyMem instead.
> +
> + TargetOffsetinBytes += IntBytes; // adjust pointers and counter
> + BufferSizeInBytes -= IntBytes;
> + Buffer += IntBytes;
> + if (BufferSizeInBytes == 0) {
> + return EFI_SUCCESS;
> + }
> + }
> +
> + ReadData = (FLASH_DATA*)Buffer;
> +
> + // Readout the bytes from CFI width aligned address.
> + // Note we can read number of bytes=CFI width in one operation
> + while (BufferSizeInBytes >= sizeof (FLASH_DATA)) {
> + *ReadData = FLASH_READ_DATA (CREATE_NOR_ADDRESS (
> + Instance->DeviceBaseAddress,
> + CREATE_BYTE_OFFSET (TargetOffsetinBytes/sizeof (FLASH_DATA))));
> + ReadData += 1;
> + BufferSizeInBytes -= sizeof (FLASH_DATA);
> + TargetOffsetinBytes += sizeof (FLASH_DATA);
> + }
> +
> + if (BufferSizeInBytes == 0) {
> + return EFI_SUCCESS;
> + }
> +
> + // Now read bytes that are remaining and are less than CFI width.
> + CopyTo = (UINT8*)ReadData;
> + // Read the first few to get Read buffer aligned
> + TempRead = FLASH_READ_DATA (CREATE_NOR_ADDRESS (
> + Instance->DeviceBaseAddress,
> + CREATE_BYTE_OFFSET (TargetOffsetinBytes/sizeof (FLASH_DATA))));
> + CopyFrom = (UINT8*)&TempRead;
And these.
> +
> + InternalMemCopyMem (CopyTo, CopyFrom, BufferSizeInBytes);
Please use CopyMem instead.
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformReset (
> + IN UINTN DeviceBaseAddress
> + )
> +{
> + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR,
> + CMD_RESET_FIRST);
> +
> + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR,
> + CMD_RESET_SECOND);
> +
> + SEND_NOR_COMMAND (DeviceBaseAddress, 0, CMD_RESET);
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformGetDevices (
> + OUT NorFlashDescription **NorFlashDevices,
> + OUT UINT32 *Count
> + )
> +{
> + if ((NorFlashDevices == NULL) || (Count == NULL)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Get the number of NOR flash devices supported
> + *NorFlashDevices = mNorFlashDevices;
> + *Count = NOR_FLASH_DEVICE_COUNT;
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformFlashGetAttributes (
> + OUT NorFlashDescription *NorFlashDevices,
> + IN UINT32 Count
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 Index;
> +
> + if ((NorFlashDevices == NULL) || (Count == 0)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Check the attributes of the NOR flash slave we are connected to.
> + // Currently we support only CFI flash devices. Bail-out otherwise.
> + Status = CfiNorFlashFlashGetAttributes (NorFlashDevices, Count);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + // Limit the Size of Nor Flash that can be programmed
> + for (Index = 0; Index < Count; Index++) {
> + NorFlashDevices[Index].RegionBaseAddress = PcdGet64 (PcdFlashReservedRegionBase64);
> + NorFlashDevices[Index].Size -= (NorFlashDevices[Index].RegionBaseAddress -
> + NorFlashDevices[Index].DeviceBaseAddress);
> + if((NorFlashDevices[Index].RegionBaseAddress - NorFlashDevices[Index].DeviceBaseAddress) %
> + NorFlashDevices[Index].BlockSize) {
> + DEBUG ((DEBUG_ERROR, "%a : Reserved Region(0x%p) doesn't start "
> + "from block boundry(0x%08x)\n", __FUNCTION__,
> + (UINTN)NorFlashDevices[Index].RegionBaseAddress,
> + (UINT32)NorFlashDevices[Index].BlockSize));
> + return EFI_DEVICE_ERROR;
> + }
> + }
> + return Status;
> +}
> diff --git a/Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
> new file mode 100644
> index 0000000..403766a
> --- /dev/null
> +++ b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
> @@ -0,0 +1,41 @@
> +# @NorFlashLib.inf
> +#
> +# Component description file for NorFlashLib module
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = NorFlashLib
> + FILE_GUID = f3176a49-dde1-450d-a909-8580c03b9ba8
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = NorFlashLib
> +
> +[Sources.common]
> + NorFlashLib.c
> + CfiNorFlashLib.c
Please sort alphabetically.
> +
> +[LibraryClasses]
> + ArmLib
> + TimerLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[Pcd.common]
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 03/39] SocLib : Add support for initialization of peripherals
2018-04-18 18:15 ` Leif Lindholm
@ 2018-04-19 4:59 ` Meenakshi Aggarwal
0 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-04-19 4:59 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Wednesday, April 18, 2018 11:45 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms 03/39] SocLib : Add support for
> initialization of peripherals
>
> On Wed, Apr 18, 2018 at 04:38:22PM +0000, Meenakshi Aggarwal wrote:
> > > > +
> > > > +/*
> > > > + * Returns the bit mask for a bit index from 0 to 31
> > > > + */
> > > > +#define BIT(_BitIndex) (0x1u << (_BitIndex))
> > >
> > > I don't see these being used for anything other than setting up BIT1
> > > BIT2 BIT3 and so on. We already have those in Base.h.
> > >
> > In Base.h, we have BIT1, BIT2 defined, here the requirement is to
> > get set bit on basis of bit number, bit is not known in advance.
>
> Ah, I missed the uses in SerDes.c and saw only the ones in UsbHcd.h
> (which could use the Base.h defines).
>
> But does it really simplify anything in SerDes.c?
>
> *SerDesPrtclMap |= BIT (LanePrtcl);
>
> is no clearer to me than
>
> *SerDesPrtclMap |= (1u << LanePrtcl);
>
This can also be used.
> Best Regards,
>
> Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 17/39] LS1043 : Enable NOR driver for LS1043aRDB package.
2018-02-16 8:50 ` [PATCH edk2-platforms 17/39] LS1043 : Enable NOR driver for LS1043aRDB package Meenakshi
@ 2018-04-19 9:54 ` Leif Lindholm
2018-04-19 10:14 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 9:54 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
On Fri, Feb 16, 2018 at 02:20:13PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Will this one require any changes to build (and work correctly)
against current edk2?
If not:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
/
Leif
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 16 +++++++++++++++-
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 9 ++++++++-
> 2 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index df4d917..7708e0a 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -41,6 +41,7 @@
> IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
> BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
> FpgaLib|Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
> + NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
>
> [PcdsFixedAtBuild.common]
>
> @@ -70,6 +71,13 @@
> gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
> gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
>
> + #
> + # NV Storage PCDs.
> + #
> + gArmTokenSpaceGuid.PcdVFPEnabled|1
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000
> +
> ################################################################################
> #
> # Components Section - list of all EDK II Modules needed by this Platform
> @@ -79,9 +87,15 @@
> #
> # Architectural Protocols
> #
> - MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> +
> + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf{
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
> + }
> + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
>
> Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> + Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
>
> ##
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> index fa6510c..6b5b63f 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> @@ -55,6 +55,7 @@ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> FV = FVMAIN_COMPACT
>
> !include ../FVRules.fdf.inc
> +!include VarStore.fdf.inc
> ################################################################################
> #
> # FV Section
> @@ -103,7 +104,8 @@ READ_LOCK_STATUS = TRUE
> INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> - INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
>
> INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> @@ -123,6 +125,11 @@ READ_LOCK_STATUS = TRUE
> INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
>
> #
> + # NOR Driver
> + #
> + INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> +
> + #
> # Network modules
> #
> INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 18/39] Silicon/NXP:Add LS1046ARDB SoCLib Support
2018-02-16 8:50 ` [PATCH edk2-platforms 18/39] Silicon/NXP:Add LS1046ARDB SoCLib Support Meenakshi
@ 2018-04-19 10:00 ` Leif Lindholm
2018-04-19 10:05 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 10:00 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Vabhav
On Fri, Feb 16, 2018 at 02:20:14PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> On LS1046A NXP SoC,Provide Functions to initialize peripherals
> ,print board, soc information.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 +
> Silicon/NXP/Chassis/Chassis.c | 1 +
> Silicon/NXP/Chassis/Chassis.h | 1 +
> Silicon/NXP/Chassis/Chassis2/Soc.c | 51 ++++++++++++++++++++-
> Silicon/NXP/Chassis/LS1043aSocLib.inf | 2 +
> Silicon/NXP/Chassis/LS1046aSocLib.inf | 51 +++++++++++++++++++++
> Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 ++++++++++++++++++++++
> Silicon/NXP/LS1046A/LS1046A.dec | 22 +++++++++
> Silicon/NXP/LS1046A/LS1046A.dsc | 68 ++++++++++++++++++++++++++++
> Silicon/NXP/NxpQoriqLs.dec | 2 +
> 10 files changed, 253 insertions(+), 1 deletion(-)
> create mode 100644 Silicon/NXP/Chassis/LS1046aSocLib.inf
> create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
> create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index 7708e0a..b2b514e 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -59,6 +59,7 @@
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
> + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|TRUE
>
> #
> # I2C controller Pcds
> diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c
> index 9f2928b..ce07fdc 100644
> --- a/Silicon/NXP/Chassis/Chassis.c
> +++ b/Silicon/NXP/Chassis/Chassis.c
> @@ -44,6 +44,7 @@ GurRead (
> */
> STATIC CPU_TYPE CpuTypeList[] = {
> CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
> + CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
> };
>
> /*
> diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h
> index 4bdb4d0..0beb44c 100644
> --- a/Silicon/NXP/Chassis/Chassis.h
> +++ b/Silicon/NXP/Chassis/Chassis.h
> @@ -56,6 +56,7 @@ CpuMaskNext (
>
> #define SVR_WO_E 0xFFFFFE
> #define SVR_LS1043A 0x879200
> +#define SVR_LS1046A 0x870700
>
> #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> #define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chassis2/Soc.c
> index 17de7e4..658df2d 100644
> --- a/Silicon/NXP/Chassis/Chassis2/Soc.c
> +++ b/Silicon/NXP/Chassis/Chassis2/Soc.c
> @@ -17,6 +17,7 @@
> #include <Chassis.h>
> #include <Library/BaseLib.h>
> #include <Library/BaseMemoryLib/MemLibInternals.h>
> +#include <Library/BeIoLib.h>
> #include <Library/DebugLib.h>
> #include <Library/IfcLib.h>
> #include <Library/IoLib.h>
> @@ -139,6 +140,44 @@ GetSysInfo (
> }
>
> /**
> + Function to select pins depending upon pcd using supplemental
> + configuration unit(SCFG) extended RCW controlled pinmux control
> + register which contains the bits to provide pin multiplexing control.
> + This register is reset on HRESET.
> + **/
> +VOID
> +ConfigScfgMux (VOID)
> +{
> + CCSR_SCFG *Scfg;
> + UINT32 UsbPwrFault;
> +
> + Scfg = (VOID *)PcdGet64 (PcdScfgBaseAddr);
> + // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
> + // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
> +
> + // LS1043A
> + // Configures functionality of the IIC4_SCL to USB3_DRVVBUS
> + // Configures functionality of the IIC4_SDA to USB3_PWRFAULT
> +
> + // LS1046A
> + // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
> + if (PcdGetBool (PcdMuxToUsb3)) {
> + BeMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_SELCR_USB);
> + } else {
> + BeMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB);
> + }
> + BeMmioWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, CCSR_SCFG_USBDRVVBUS_SELCR_USB1);
> + UsbPwrFault = (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
> + CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) |
> + (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
> + CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) |
> + (CCSR_SCFG_USBPWRFAULT_SHARED <<
> + CCSR_SCFG_USBPWRFAULT_USB1_SHIFT);
Can you change indentation like so?:
UsbPwrFault = (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) |
(CCSR_SCFG_USBPWRFAULT_DEDICATED <<
CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) |
(CCSR_SCFG_USBPWRFAULT_SHARED <<
CCSR_SCFG_USBPWRFAULT_USB1_SHIFT);
> + BeMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
> + BeMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
> +}
> +
> +/**
> Function to initialize SoC specific constructs
> CPU Info
> SoC Personality
> @@ -170,8 +209,18 @@ SocInit (
> //
> PrintRCW ();
> PrintSoc ();
> - IfcInit();
> + IfcInit ();
Please fix the whitespace in the originating patch, even if I missed
it on review :)
> PrintBoardPersonality ();
> + //
> + // Due to the extensive functionality present on the chip and the limited number of external
> + // signals available, several functional blocks share signal resources through multiplexing.
> + // In this case when there is alternate functionality between multiple functional blocks,
> + // the signal's function is determined at the chip level (rather than at the block level)
> + // typically by a reset configuration word (RCW) option. Some of the signals' function are
> + // determined externel to RCW at Power-on Reset Sequence.
> + //
> + ConfigScfgMux ();
> +
>
> return;
> }
> diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS1043aSocLib.inf
> index d01b353..71fa0a8 100644
> --- a/Silicon/NXP/Chassis/LS1043aSocLib.inf
> +++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf
> @@ -47,3 +47,5 @@
> gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3
> diff --git a/Silicon/NXP/Chassis/LS1046aSocLib.inf b/Silicon/NXP/Chassis/LS1046aSocLib.inf
> new file mode 100644
> index 0000000..11eeb97
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/LS1046aSocLib.inf
> @@ -0,0 +1,51 @@
> +# @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = SocLib
> + FILE_GUID = ddd5f950-8816-4d38-8f98-f42b07333f78
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SocLib
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> + Silicon/NXP/LS1046A/LS1046A.dec
Can you sort these packages alphabetically please?
> +
> +[LibraryClasses]
> + BaseLib
> + BeIoLib
> + DebugLib
> + FpgaLib
> + IfcLib
> + SerialPortLib
> +
> +[Sources.common]
> + Chassis.c
> + Chassis2/Soc.c
> + SerDes.c
> +
> +[FixedPcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3
Can you sort these Pcds alphabetically please?
> diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h b/Silicon/NXP/LS1046A/Include/SocSerDes.h
> new file mode 100644
> index 0000000..a0b5576
> --- /dev/null
> +++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h
> @@ -0,0 +1,55 @@
> +/** @file
> + The Header file of SerDes Module
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __LS1046A_SERDES_H__
> +#define __LS1046A_SERDES_H__
> +
> +#include <SerDes.h>
> +
> +SERDES_CONFIG SerDes1ConfigTbl[] = {
> + /* SerDes 1 */
Indentation should be two spaces, throughout the file.
> + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE } },
> + {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE } },
> + {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6 } },
> + {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6 } },
> + {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, SGMII_FM1_DTSEC6 } },
> + {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {}
> +};
> +
> +SERDES_CONFIG SerDes2ConfigTbl[] = {
> + /* SerDes 2 */
> + {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1 } },
> + {0x5559, {PCIE1, PCIE2, PCIE3, SATA } },
> + {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3 } },
> + {0x5506, {PCIE1, PCIE2, NONE, PCIE3 } },
> + {0x0506, {NONE, PCIE2, NONE, PCIE3 } },
> + {0x0559, {NONE, PCIE2, PCIE3, SATA } },
> + {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA } },
> + {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3 } },
> + {}
> +};
> +
> +SERDES_CONFIG *SerDesConfigTbl[] = {
> + SerDes1ConfigTbl,
> + SerDes2ConfigTbl
> +};
> +
> +#endif /* __LS1046A_SERDES_H */
> diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec
> new file mode 100644
> index 0000000..e266aad
> --- /dev/null
> +++ b/Silicon/NXP/LS1046A/LS1046A.dec
> @@ -0,0 +1,22 @@
> +# LS1046A.dec
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x00010005
0x0001001a
/
Leif
> +
> +[Guids.common]
> + gNxpLs1046ATokenSpaceGuid = {0x8d7ffac8, 0xb4d5, 0x43c3, {0xaa, 0x27, 0x84, 0xbc, 0x12, 0x01, 0x28, 0x10}}
> +
> +[Includes]
> + Include
> diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc b/Silicon/NXP/LS1046A/LS1046A.dsc
> new file mode 100644
> index 0000000..9f87028
> --- /dev/null
> +++ b/Silicon/NXP/LS1046A/LS1046A.dsc
> @@ -0,0 +1,68 @@
> +# LS1046A.dsc
> +# LS1046A Soc package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +[PcdsDynamicDefault.common]
> +
> + #
> + # ARM General Interrupt Controller
> + gArmTokenSpaceGuid.PcdGicDistributorBase|0x01410000
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01420000
> +
> +[PcdsFixedAtBuild.common]
> +
> + #
> + # CCSR Address Space and other attached Memories
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
> + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000
> + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
> +
> +##
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 43d0a71..39753e7 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -30,6 +30,7 @@
> gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0|UINT32|0x00000001
> gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000002
> gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000003
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT32|0x00000004
>
> #
> # Pcds for base address and size
> @@ -101,6 +102,7 @@
> #
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
> gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
> + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE|BOOLEAN|0x00000253
>
> #
> # Clock PCDs
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 18/39] Silicon/NXP:Add LS1046ARDB SoCLib Support
2018-04-19 10:00 ` Leif Lindholm
@ 2018-04-19 10:05 ` Meenakshi Aggarwal
2018-04-19 10:20 ` Leif Lindholm
0 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-04-19 10:05 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi, Vabhav Sharma
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Thursday, April 19, 2018 3:31 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
> <vabhav.sharma@nxp.com>
> Subject: Re: [PATCH edk2-platforms 18/39] Silicon/NXP:Add LS1046ARDB
> SoCLib Support
>
> On Fri, Feb 16, 2018 at 02:20:14PM +0530, Meenakshi wrote:
> > From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> >
> > On LS1046A NXP SoC,Provide Functions to initialize peripherals
> > ,print board, soc information.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> > ---
> > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 +
> > Silicon/NXP/Chassis/Chassis.c | 1 +
> > Silicon/NXP/Chassis/Chassis.h | 1 +
> > Silicon/NXP/Chassis/Chassis2/Soc.c | 51 ++++++++++++++++++++-
> > Silicon/NXP/Chassis/LS1043aSocLib.inf | 2 +
> > Silicon/NXP/Chassis/LS1046aSocLib.inf | 51 +++++++++++++++++++++
> > Silicon/NXP/LS1046A/Include/SocSerDes.h | 55
> ++++++++++++++++++++++
> > Silicon/NXP/LS1046A/LS1046A.dec | 22 +++++++++
> > Silicon/NXP/LS1046A/LS1046A.dsc | 68
> ++++++++++++++++++++++++++++
> > Silicon/NXP/NxpQoriqLs.dec | 2 +
> > 10 files changed, 253 insertions(+), 1 deletion(-)
> > create mode 100644 Silicon/NXP/Chassis/LS1046aSocLib.inf
> > create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
> > create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
> > create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc
> >
> > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > index 7708e0a..b2b514e 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > @@ -59,6 +59,7 @@
> > gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> > gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
> > gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
> > + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|TRUE
> >
> > #
> > # I2C controller Pcds
> > diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c
> > index 9f2928b..ce07fdc 100644
> > --- a/Silicon/NXP/Chassis/Chassis.c
> > +++ b/Silicon/NXP/Chassis/Chassis.c
> > @@ -44,6 +44,7 @@ GurRead (
> > */
> > STATIC CPU_TYPE CpuTypeList[] = {
> > CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
> > + CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
> > };
> >
> > /*
> > diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h
> > index 4bdb4d0..0beb44c 100644
> > --- a/Silicon/NXP/Chassis/Chassis.h
> > +++ b/Silicon/NXP/Chassis/Chassis.h
> > @@ -56,6 +56,7 @@ CpuMaskNext (
> >
> > #define SVR_WO_E 0xFFFFFE
> > #define SVR_LS1043A 0x879200
> > +#define SVR_LS1046A 0x870700
> >
> > #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> > #define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> > diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c
> b/Silicon/NXP/Chassis/Chassis2/Soc.c
> > index 17de7e4..658df2d 100644
> > --- a/Silicon/NXP/Chassis/Chassis2/Soc.c
> > +++ b/Silicon/NXP/Chassis/Chassis2/Soc.c
> > @@ -17,6 +17,7 @@
> > #include <Chassis.h>
> > #include <Library/BaseLib.h>
> > #include <Library/BaseMemoryLib/MemLibInternals.h>
> > +#include <Library/BeIoLib.h>
> > #include <Library/DebugLib.h>
> > #include <Library/IfcLib.h>
> > #include <Library/IoLib.h>
> > @@ -139,6 +140,44 @@ GetSysInfo (
> > }
> >
> > /**
> > + Function to select pins depending upon pcd using supplemental
> > + configuration unit(SCFG) extended RCW controlled pinmux control
> > + register which contains the bits to provide pin multiplexing control.
> > + This register is reset on HRESET.
> > + **/
> > +VOID
> > +ConfigScfgMux (VOID)
> > +{
> > + CCSR_SCFG *Scfg;
> > + UINT32 UsbPwrFault;
> > +
> > + Scfg = (VOID *)PcdGet64 (PcdScfgBaseAddr);
> > + // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
> > + // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
> > +
> > + // LS1043A
> > + // Configures functionality of the IIC4_SCL to USB3_DRVVBUS
> > + // Configures functionality of the IIC4_SDA to USB3_PWRFAULT
> > +
> > + // LS1046A
> > + // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
> > + if (PcdGetBool (PcdMuxToUsb3)) {
> > + BeMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0,
> CCSR_SCFG_RCWPMUXCRO_SELCR_USB);
> > + } else {
> > + BeMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0,
> CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB);
> > + }
> > + BeMmioWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr,
> CCSR_SCFG_USBDRVVBUS_SELCR_USB1);
> > + UsbPwrFault = (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
> > + CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) |
> > + (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
> > + CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) |
> > + (CCSR_SCFG_USBPWRFAULT_SHARED <<
> > + CCSR_SCFG_USBPWRFAULT_USB1_SHIFT);
>
> Can you change indentation like so?:
>
> UsbPwrFault = (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
> CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) |
> (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
> CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) |
> (CCSR_SCFG_USBPWRFAULT_SHARED <<
> CCSR_SCFG_USBPWRFAULT_USB1_SHIFT);
>
I will accommodate all other changes except I am not getting the difference between above two.
Please tell a bit about the change.
> > + BeMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
> > + BeMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
> > +}
> > +
> > +/**
> > Function to initialize SoC specific constructs
> > CPU Info
> > SoC Personality
> > @@ -170,8 +209,18 @@ SocInit (
> > //
> > PrintRCW ();
> > PrintSoc ();
> > - IfcInit();
> > + IfcInit ();
>
> Please fix the whitespace in the originating patch, even if I missed
> it on review :)
>
> > PrintBoardPersonality ();
> > + //
> > + // Due to the extensive functionality present on the chip and the limited
> number of external
> > + // signals available, several functional blocks share signal resources
> through multiplexing.
> > + // In this case when there is alternate functionality between multiple
> functional blocks,
> > + // the signal's function is determined at the chip level (rather than at the
> block level)
> > + // typically by a reset configuration word (RCW) option. Some of the
> signals' function are
> > + // determined externel to RCW at Power-on Reset Sequence.
> > + //
> > + ConfigScfgMux ();
> > +
> >
> > return;
> > }
> > diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf
> b/Silicon/NXP/Chassis/LS1043aSocLib.inf
> > index d01b353..71fa0a8 100644
> > --- a/Silicon/NXP/Chassis/LS1043aSocLib.inf
> > +++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf
> > @@ -47,3 +47,5 @@
> > gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> > gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> > gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> > + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
> > + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3
> > diff --git a/Silicon/NXP/Chassis/LS1046aSocLib.inf
> b/Silicon/NXP/Chassis/LS1046aSocLib.inf
> > new file mode 100644
> > index 0000000..11eeb97
> > --- /dev/null
> > +++ b/Silicon/NXP/Chassis/LS1046aSocLib.inf
> > @@ -0,0 +1,51 @@
> > +# @file
> > +#
> > +# Copyright 2017 NXP
> > +#
> > +# This program and the accompanying materials
> > +# are licensed and made available under the terms and conditions of the
> BSD License
> > +# which accompanies this distribution. The full text of the license may be
> found at
> > +#
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Ca9914b
> f14bf84646966b08d5a5dc7082%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636597288562189295&sdata=G6LgZGpCSbRKR2vhaQ8gwTRIwed7%
> 2FNkm7DsL7kvgYTs%3D&reserved=0
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +#
> > +#
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001A
> > + BASE_NAME = SocLib
> > + FILE_GUID = ddd5f950-8816-4d38-8f98-f42b07333f78
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = SocLib
> > +
> > +[Packages]
> > + MdeModulePkg/MdeModulePkg.dec
> > + MdePkg/MdePkg.dec
> > + Silicon/NXP/NxpQoriqLs.dec
> > + Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> > + Silicon/NXP/LS1046A/LS1046A.dec
>
> Can you sort these packages alphabetically please?
>
> > +
> > +[LibraryClasses]
> > + BaseLib
> > + BeIoLib
> > + DebugLib
> > + FpgaLib
> > + IfcLib
> > + SerialPortLib
> > +
> > +[Sources.common]
> > + Chassis.c
> > + Chassis2/Soc.c
> > + SerDes.c
> > +
> > +[FixedPcd]
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> > + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> > + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> > + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> > + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> > + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> > + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
> > + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3
>
> Can you sort these Pcds alphabetically please?
>
> > diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h
> b/Silicon/NXP/LS1046A/Include/SocSerDes.h
> > new file mode 100644
> > index 0000000..a0b5576
> > --- /dev/null
> > +++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h
> > @@ -0,0 +1,55 @@
> > +/** @file
> > + The Header file of SerDes Module
> > +
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials
> > + are licensed and made available under the terms and conditions of the
> BSD License
> > + which accompanies this distribution. The full text of the license may be
> found
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Ca9914b
> f14bf84646966b08d5a5dc7082%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636597288562189295&sdata=G6LgZGpCSbRKR2vhaQ8gwTRIwed7%
> 2FNkm7DsL7kvgYTs%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#ifndef __LS1046A_SERDES_H__
> > +#define __LS1046A_SERDES_H__
> > +
> > +#include <SerDes.h>
> > +
> > +SERDES_CONFIG SerDes1ConfigTbl[] = {
> > + /* SerDes 1 */
>
> Indentation should be two spaces, throughout the file.
>
> > + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
> SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> > + {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5,
> SGMII_FM1_DTSEC6 } },
> > + {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10,
> SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> > + {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10,
> SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> > + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
> SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> > + {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE } },
> > + {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE }
> },
> > + {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1,
> SGMII_FM1_DTSEC6 } },
> > + {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
> PCIE1, SGMII_FM1_DTSEC6 } },
> > + {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1,
> SGMII_FM1_DTSEC6 } },
> > + {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,
> SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> > + {}
> > +};
> > +
> > +SERDES_CONFIG SerDes2ConfigTbl[] = {
> > + /* SerDes 2 */
> > + {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1 } },
> > + {0x5559, {PCIE1, PCIE2, PCIE3, SATA } },
> > + {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3 } },
> > + {0x5506, {PCIE1, PCIE2, NONE, PCIE3 } },
> > + {0x0506, {NONE, PCIE2, NONE, PCIE3 } },
> > + {0x0559, {NONE, PCIE2, PCIE3, SATA } },
> > + {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA } },
> > + {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3 } },
> > + {}
> > +};
> > +
> > +SERDES_CONFIG *SerDesConfigTbl[] = {
> > + SerDes1ConfigTbl,
> > + SerDes2ConfigTbl
> > +};
> > +
> > +#endif /* __LS1046A_SERDES_H */
> > diff --git a/Silicon/NXP/LS1046A/LS1046A.dec
> b/Silicon/NXP/LS1046A/LS1046A.dec
> > new file mode 100644
> > index 0000000..e266aad
> > --- /dev/null
> > +++ b/Silicon/NXP/LS1046A/LS1046A.dec
> > @@ -0,0 +1,22 @@
> > +# LS1046A.dec
> > +#
> > +# Copyright 2017 NXP
> > +#
> > +# This program and the accompanying materials are licensed and made
> available under
> > +# the terms and conditions of the BSD License which accompanies this
> distribution.
> > +# The full text of the license may be found at
> > +#
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Ca9914b
> f14bf84646966b08d5a5dc7082%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636597288562189295&sdata=G6LgZGpCSbRKR2vhaQ8gwTRIwed7%
> 2FNkm7DsL7kvgYTs%3D&reserved=0
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +#
> > +#
> > +
> > +[Defines]
> > + DEC_SPECIFICATION = 0x00010005
>
> 0x0001001a
>
> /
> Leif
>
> > +
> > +[Guids.common]
> > + gNxpLs1046ATokenSpaceGuid = {0x8d7ffac8, 0xb4d5, 0x43c3, {0xaa,
> 0x27, 0x84, 0xbc, 0x12, 0x01, 0x28, 0x10}}
> > +
> > +[Includes]
> > + Include
> > diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc
> b/Silicon/NXP/LS1046A/LS1046A.dsc
> > new file mode 100644
> > index 0000000..9f87028
> > --- /dev/null
> > +++ b/Silicon/NXP/LS1046A/LS1046A.dsc
> > @@ -0,0 +1,68 @@
> > +# LS1046A.dsc
> > +# LS1046A Soc package.
> > +#
> > +# Copyright 2017 NXP
> > +#
> > +# This program and the accompanying materials
> > +# are licensed and made available under the terms and conditions of the
> BSD License
> > +# which accompanies this distribution. The full text of the license may be
> found at
> > +#
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Ca9914b
> f14bf84646966b08d5a5dc7082%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636597288562189295&sdata=G6LgZGpCSbRKR2vhaQ8gwTRIwed7%
> 2FNkm7DsL7kvgYTs%3D&reserved=0
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +#
> > +#
> > +
> >
> +#########################################################
> #######################
> > +#
> > +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> > +#
> >
> +#########################################################
> #######################
> > +[PcdsDynamicDefault.common]
> > +
> > + #
> > + # ARM General Interrupt Controller
> > + gArmTokenSpaceGuid.PcdGicDistributorBase|0x01410000
> > + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01420000
> > +
> > +[PcdsFixedAtBuild.common]
> > +
> > + #
> > + # CCSR Address Space and other attached Memories
> > + #
> > + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
> > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
> > + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
> > + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
> > + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000
> > + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
> > + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
> > + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> > + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> > + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> > + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
> > +
> > +##
> > diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> > index 43d0a71..39753e7 100644
> > --- a/Silicon/NXP/NxpQoriqLs.dec
> > +++ b/Silicon/NXP/NxpQoriqLs.dec
> > @@ -30,6 +30,7 @@
> > gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0|UINT32|0x00000001
> > gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000002
> >
> gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000003
> > +
> gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT32|0x00000004
> >
> > #
> > # Pcds for base address and size
> > @@ -101,6 +102,7 @@
> > #
> >
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
> >
> gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x0000
> 0251
> > +
> gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE|BOOLEAN|0x00000253
> >
> > #
> > # Clock PCDs
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for PCF2129 Real Time Clock Library
2018-02-16 8:50 ` [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for PCF2129 Real Time Clock Library Meenakshi
@ 2018-04-19 10:11 ` Leif Lindholm
2018-04-19 12:33 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 10:11 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Vabhav
On Fri, Feb 16, 2018 at 02:20:15PM +0530, Meenakshi wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Library to provide functions for NXP pcf2129 real time clock library
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> ---
> Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h | 43 +++
> Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c | 330 +++++++++++++++++++++
> .../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf | 47 +++
> 3 files changed, 420 insertions(+)
> create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
>
> diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> new file mode 100644
> index 0000000..735f697
> --- /dev/null
> +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> @@ -0,0 +1,43 @@
> +/** Pcf2129Rtc.h
> +*
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __PCF2129RTC_H__
> +#define __PCF2129RTC_H__
> +
> +/*
> + * RTC register addresses
> + */
> +#define PCF2129_CTRL1_REG_ADDR 0x00 // Control Register 1
> +#define PCF2129_CTRL2_REG_ADDR 0x01 // Control Register 2
> +#define PCF2129_CTRL3_REG_ADDR 0x02 // Control Register 3
> +#define PCF2129_SEC_REG_ADDR 0x03
> +#define PCF2129_MIN_REG_ADDR 0x04
> +#define PCF2129_HR_REG_ADDR 0x05
> +#define PCF2129_DAY_REG_ADDR 0x06
> +#define PCF2129_WEEKDAY_REG_ADDR 0x07
> +#define PCF2129_MON_REG_ADDR 0x08
> +#define PCF2129_YR_REG_ADDR 0x09
> +
> +#define PCF2129_CTRL3_BIT_BLF BIT2 /* Battery Low Flag*/
> +
> +// Define EPOCH (1998-JANUARY-01) in the Julian Date representation
> +#define EPOCH_JULIAN_DATE 2450815
> +
> +typedef struct {
> + UINTN OperationCount;
> + EFI_I2C_OPERATION SetAddressOp;
> + EFI_I2C_OPERATION GetSetDateTimeOp;
> +} RTC_I2C_REQUEST;
> +
> +#endif // __PCF2129RTC_H__
> diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> new file mode 100644
> index 0000000..2e21014
> --- /dev/null
> +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> @@ -0,0 +1,330 @@
> +/** @PCF2129RtcLib.c
> + Implement EFI RealTimeClock with runtime services via RTC Lib for PCF2129 RTC.
> +
> + Based on RTC implementation available in
> + EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
> +
> + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/RealTimeClockLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +#include <Protocol/I2cMaster.h>
> +
> +#include "Pcf2129Rtc.h"
> +
> +STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
> +
> +/**
> + returns Day of the week [0-6] 0=Sunday
> + Don't try to provide a Year that's before 1998, please !
(You should probably add an assert for that, in that case.)
> + **/
> +UINTN
> +EfiTimeToWday (
This looks like a completely generic function. Could it be submitted
to edk2 EmbeddedPkg/Library/TimeBaseLib?
> + IN EFI_TIME *Time
> + )
> +{
> + UINTN MonthDiff;
> + UINTN Year;
> + UINTN Month;
> + UINTN JulianDate; // Absolute Julian Date representation of the supplied Time
> + UINTN EpochDays; // Number of days elapsed since EPOCH_JULIAN_DAY
> +
> + MonthDiff = (14 - Time->Month) / 12 ;
> + Year = Time->Year + 4800 - MonthDiff;
> + Month = Time->Month + (12*MonthDiff) - 3;
> +
> + JulianDate = Time->Day + ((153*Month + 2)/5) + (365*Year) + (Year/4) - (Year/100) + (Year/400) - 32045;
> +
> + ASSERT (JulianDate >= EPOCH_JULIAN_DATE);
> + EpochDays = JulianDate - EPOCH_JULIAN_DATE;
> +
> + // 4=1/1/1998 was a Thursday
Extra space in indentation.
> +
> + return (EpochDays + 4) % 7;
> +}
> +
> +/**
> + Write RTC register.
> +
> + @param RtcRegAddr Register offset of RTC to write.
> + @param Val Value to be written
> +
> +**/
> +
> +STATIC
> +VOID
> +RtcWrite (
> + IN UINT8 RtcRegAddr,
> + IN UINT8 Val
> + )
> +{
> + RTC_I2C_REQUEST Req;
> + EFI_STATUS Status;
> +
> + Req.OperationCount = 2;
> +
> + Req.SetAddressOp.Flags = 0;
> + Req.SetAddressOp.LengthInBytes = 0;
> + Req.SetAddressOp.Buffer = &RtcRegAddr;
> +
> + Req.GetSetDateTimeOp.Flags = 0;
> + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
> + Req.GetSetDateTimeOp.Buffer = &Val;
> +
> + Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
> + (VOID *)&Req,
> + NULL, NULL);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
> + }
> +
> +}
> +
> +/**
> + Returns the current time and date information, and the time-keeping capabilities
> + of the hardware platform.
> +
> + @param Time A pointer to storage to receive a snapshot of the current time.
> + @param Capabilities An optional pointer to a buffer to receive the real time clock
> + device's capabilities.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_INVALID_PARAMETER Time is NULL.
> + @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
> +
> +**/
> +
> +EFI_STATUS
> +EFIAPI
> +LibGetTime (
> + OUT EFI_TIME *Time,
> + OUT EFI_TIME_CAPABILITIES *Capabilities
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 Buffer[10];
> + RTC_I2C_REQUEST Req;
> + UINT8 RtcRegAddr;
> +
> + Status = EFI_SUCCESS;
> + RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
> + Buffer[0] = 0;
> +
> + if (mI2cMaster == NULL) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + RtcWrite (PCF2129_CTRL1_REG_ADDR, Buffer[0]);
> +
> + if (Time == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Req.OperationCount = 2;
> +
> + Req.SetAddressOp.Flags = 0;
> + Req.SetAddressOp.LengthInBytes = 0;
> + Req.SetAddressOp.Buffer = &RtcRegAddr;
> +
> + Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
> + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Buffer);
> + Req.GetSetDateTimeOp.Buffer = Buffer;
> +
> + Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
> + (VOID *)&Req,
> + NULL, NULL);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
> + }
> +
> + if (Buffer[PCF2129_CTRL3_REG_ADDR] & PCF2129_CTRL3_BIT_BLF) {
> + DEBUG((DEBUG_INFO, "### Warning: RTC battery status low, check/replace RTC battery.\n"));
> + }
> +
> + Time->Nanosecond = 0;
> + Time->Second = BcdToDecimal8 (Buffer[PCF2129_SEC_REG_ADDR] & 0x7F);
> + Time->Minute = BcdToDecimal8 (Buffer[PCF2129_MIN_REG_ADDR] & 0x7F);
> + Time->Hour = BcdToDecimal8 (Buffer[PCF2129_HR_REG_ADDR] & 0x3F);
> + Time->Day = BcdToDecimal8 (Buffer[PCF2129_DAY_REG_ADDR] & 0x3F);
> + Time->Month = BcdToDecimal8 (Buffer[PCF2129_MON_REG_ADDR] & 0x1F);
Ideally, I would like to see #defines for these masks.
> + Time->Year = BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]) + ( BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]) >= 98 ? 1900 : 2000);
That is a very long line.
It could be shortened substantially by using a temporary variable for
BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]).
> +
> + return Status;
> +}
> +
> +/**
> + Sets the current local time and date information.
> +
> + @param Time A pointer to the current time.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_INVALID_PARAMETER A time field is out of range.
> + @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
> +
> +**/
> +
> +EFI_STATUS
> +EFIAPI
> +LibSetTime (
> + IN EFI_TIME *Time
> + )
> +{
> + UINT8 Buffer[8];
> + UINT8 Index;
> + EFI_STATUS Status;
> + RTC_I2C_REQUEST Req;
> + UINT8 RtcRegAddr;
> +
> + Index = 0;
> + Status = EFI_SUCCESS;
> + RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
> +
> + if (mI2cMaster == NULL) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + // start register address
> + Buffer[Index++] = PCF2129_SEC_REG_ADDR;
> +
> + // hours, minutes and seconds
> + Buffer[Index++] = DecimalToBcd8 (Time->Second);
> + Buffer[Index++] = DecimalToBcd8 (Time->Minute);
> + Buffer[Index++] = DecimalToBcd8 (Time->Hour);
> + Buffer[Index++] = DecimalToBcd8 (Time->Day);
> + Buffer[Index++] = EfiTimeToWday (Time) & 0x07;
Why mask at the call site?
/
Leif
> + Buffer[Index++] = DecimalToBcd8 (Time->Month);
> + Buffer[Index++] = DecimalToBcd8 (Time->Year % 100);
> +
> + Req.OperationCount = 2;
> + Req.SetAddressOp.Flags = 0;
> + Req.SetAddressOp.LengthInBytes = 0;
> + Req.SetAddressOp.Buffer = &RtcRegAddr;
> +
> + Req.GetSetDateTimeOp.Flags = 0;
> + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Buffer);
> + Req.GetSetDateTimeOp.Buffer = Buffer;
> +
> + Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
> + (VOID *)&Req,
> + NULL, NULL);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
> + return Status;
> + }
> +
> + return Status;
> +}
> +
> +
> +/**
> + Returns the current wakeup alarm clock setting.
> +
> + @param Enabled Indicates if the alarm is currently enabled or disabled.
> + @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
> + @param Time The current alarm setting.
> +
> + @retval EFI_SUCCESS The alarm settings were returned.
> + @retval EFI_INVALID_PARAMETER Any parameter is NULL.
> + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
> + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibGetWakeupTime (
> + OUT BOOLEAN *Enabled,
> + OUT BOOLEAN *Pending,
> + OUT EFI_TIME *Time
> + )
> +{
> + // Not a required feature
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> +/**
> + Sets the system wakeup alarm clock time.
> +
> + @param Enabled Enable or disable the wakeup alarm.
> + @param Time If Enable is TRUE, the time to set the wakeup alarm for.
> +
> + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
> + Enable is FALSE, then the wakeup alarm was disabled.
> + @retval EFI_INVALID_PARAMETER A time field is out of range.
> + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
> + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibSetWakeupTime (
> + IN BOOLEAN Enabled,
> + OUT EFI_TIME *Time
> + )
> +{
> + // Not a required feature
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + This is the declaration of an EFI image entry point. This can be the entry point to an application
> + written to this specification, an EFI boot service driver, or an EFI runtime driver.
> +
> + @param ImageHandle Handle that identifies the loaded image.
> + @param SystemTable System Table for this image.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_DEVICE_ERROR The operation could not be started.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibRtcInitialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> +
> + EFI_STATUS Status;
> + EFI_I2C_MASTER_PROTOCOL *I2cMaster;
> + UINTN BusFrequency;
> +
> + Status = gBS->LocateProtocol (&gEfiI2cMasterProtocolGuid, NULL, (VOID **)&I2cMaster);
> +
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = I2cMaster->Reset (I2cMaster);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
> + __FUNCTION__, Status));
> + return Status;
> + }
> +
> + BusFrequency = FixedPcdGet32 (PcdI2cSpeed);
> + Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
> + __FUNCTION__, Status));
> + return Status;
> + }
> +
> + mI2cMaster = I2cMaster;
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
> new file mode 100644
> index 0000000..873bcea
> --- /dev/null
> +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
> @@ -0,0 +1,47 @@
> +#/** @Pcf2129RtcLib.inf
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = Pcf2129RtcLib
> + FILE_GUID = B661E02D-A90B-42AB-A5F9-CF841AAA43D9
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = RealTimeClockLib
> +
> +
> +[Sources.common]
> + Pcf2129RtcLib.c
> +
> +[Packages]
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + DebugLib
> + UefiBootServicesTableLib
> + UefiLib
> +
> +[Protocols]
> + gEfiDriverBindingProtocolGuid ## CONSUMES
> + gEfiI2cMasterProtocolGuid ## CONSUMES
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress
> +
> +[Depex]
> + gEfiI2cMasterProtocolGuid
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 17/39] LS1043 : Enable NOR driver for LS1043aRDB package.
2018-04-19 9:54 ` Leif Lindholm
@ 2018-04-19 10:14 ` Meenakshi Aggarwal
0 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-04-19 10:14 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi
Yes, it needs changes corresponding to commit 6281a2ed3bb3ffe57ed54cabd9a31dcf13b415f8.
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Thursday, April 19, 2018 3:25 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms 17/39] LS1043 : Enable NOR driver for
> LS1043aRDB package.
>
> On Fri, Feb 16, 2018 at 02:20:13PM +0530, Meenakshi wrote:
> > From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> Will this one require any changes to build (and work correctly)
> against current edk2?
>
> If not:
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>
> /
> Leif
>
> > ---
> > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 16
> +++++++++++++++-
> > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 9 ++++++++-
> > 2 files changed, 23 insertions(+), 2 deletions(-)
> >
> > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > index df4d917..7708e0a 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> > @@ -41,6 +41,7 @@
> > IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
> > BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
> > FpgaLib|Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
> > + NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
> >
> > [PcdsFixedAtBuild.common]
> >
> > @@ -70,6 +71,13 @@
> > gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
> > gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
> >
> > + #
> > + # NV Storage PCDs.
> > + #
> > + gArmTokenSpaceGuid.PcdVFPEnabled|1
> > + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000
> > +
> gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000
> > +
> >
> ##########################################################
> ######################
> > #
> > # Components Section - list of all EDK II Modules needed by this Platform
> > @@ -79,9 +87,15 @@
> > #
> > # Architectural Protocols
> > #
> > -
> MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntime
> Dxe.inf
> > +
> > +
> MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf{
> > + <LibraryClasses>
> > + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
> > + }
> > +
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.in
> f
> >
> > Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> > Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> > + Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> >
> > ##
> > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> > index fa6510c..6b5b63f 100644
> > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> > @@ -55,6 +55,7 @@
> gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> > FV = FVMAIN_COMPACT
> >
> > !include ../FVRules.fdf.inc
> > +!include VarStore.fdf.inc
> >
> ##########################################################
> ######################
> > #
> > # FV Section
> > @@ -103,7 +104,8 @@ READ_LOCK_STATUS = TRUE
> > INF
> MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> > INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> > INF
> EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter
> .inf
> > - INF
> MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntime
> Dxe.inf
> > + INF
> MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> > + INF
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.in
> f
> > INF
> MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntime
> Dxe.inf
> >
> > INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> > @@ -123,6 +125,11 @@ READ_LOCK_STATUS = TRUE
> > INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
> >
> > #
> > + # NOR Driver
> > + #
> > + INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> > +
> > + #
> > # Network modules
> > #
> > INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 18/39] Silicon/NXP:Add LS1046ARDB SoCLib Support
2018-04-19 10:05 ` Meenakshi Aggarwal
@ 2018-04-19 10:20 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 10:20 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi, Vabhav Sharma
On Thu, Apr 19, 2018 at 10:05:45AM +0000, Meenakshi Aggarwal wrote:
> > CCSR_SCFG_USBDRVVBUS_SELCR_USB1);
> > > + UsbPwrFault = (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
> > > + CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) |
> > > + (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
> > > + CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) |
> > > + (CCSR_SCFG_USBPWRFAULT_SHARED <<
> > > + CCSR_SCFG_USBPWRFAULT_USB1_SHIFT);
> >
> > Can you change indentation like so?:
> >
> > UsbPwrFault = (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
> > CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) |
> > (CCSR_SCFG_USBPWRFAULT_DEDICATED <<
> > CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) |
> > (CCSR_SCFG_USBPWRFAULT_SHARED <<
> > CCSR_SCFG_USBPWRFAULT_USB1_SHIFT);
> >
> I will accommodate all other changes except I am not getting the
> difference between above two. Please tell a bit about the change.
Apologies, I could have been more clear.
First of all, it makes the relation between the items within
parameters immediately obvious. It is a continuation of the statement
within the parentheses.
Secondly, it aligns up all of the CCSR_SCFG_USBPWRFAULT_, which makes
it a lot easier to see that all the prefixes are the same.
In summary, it makes code review easier.
Best Regards,
Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for PCF2129 Real Time Clock Library
2018-04-19 10:11 ` Leif Lindholm
@ 2018-04-19 12:33 ` Meenakshi Aggarwal
2018-04-19 13:47 ` Leif Lindholm
0 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-04-19 12:33 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi, Vabhav Sharma
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Thursday, April 19, 2018 3:42 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
> <vabhav.sharma@nxp.com>
> Subject: Re: [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for
> PCF2129 Real Time Clock Library
>
> On Fri, Feb 16, 2018 at 02:20:15PM +0530, Meenakshi wrote:
> > From: Vabhav <vabhav.sharma@nxp.com>
> >
> > Library to provide functions for NXP pcf2129 real time clock library
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> > ---
> > Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h | 43 +++
> > Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c | 330
> +++++++++++++++++++++
> > .../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf | 47 +++
> > 3 files changed, 420 insertions(+)
> > create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> > create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> > create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
> >
> > diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> > new file mode 100644
> > index 0000000..735f697
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> > @@ -0,0 +1,43 @@
> > +/** Pcf2129Rtc.h
> > +*
> > +* Copyright 2017 NXP
> > +*
> > +* This program and the accompanying materials
> > +* are licensed and made available under the terms and conditions of the
> BSD License
> > +* which accompanies this distribution. The full text of the license may be
> found at
> > +*
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cac3a81
> 31870a4f555cbc08d5a5ddfdc8%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636597295251146941&sdata=WheF7lR6B7iBUJBG2TGfGzJoiVhO%2F
> I1VZywt3l%2FeXug%3D&reserved=0
> > +*
> > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +*
> > +**/
> > +
> > +#ifndef __PCF2129RTC_H__
> > +#define __PCF2129RTC_H__
> > +
> > +/*
> > + * RTC register addresses
> > + */
> > +#define PCF2129_CTRL1_REG_ADDR 0x00 // Control Register 1
> > +#define PCF2129_CTRL2_REG_ADDR 0x01 // Control Register 2
> > +#define PCF2129_CTRL3_REG_ADDR 0x02 // Control Register 3
> > +#define PCF2129_SEC_REG_ADDR 0x03
> > +#define PCF2129_MIN_REG_ADDR 0x04
> > +#define PCF2129_HR_REG_ADDR 0x05
> > +#define PCF2129_DAY_REG_ADDR 0x06
> > +#define PCF2129_WEEKDAY_REG_ADDR 0x07
> > +#define PCF2129_MON_REG_ADDR 0x08
> > +#define PCF2129_YR_REG_ADDR 0x09
> > +
> > +#define PCF2129_CTRL3_BIT_BLF BIT2 /* Battery Low Flag*/
> > +
> > +// Define EPOCH (1998-JANUARY-01) in the Julian Date representation
> > +#define EPOCH_JULIAN_DATE 2450815
> > +
> > +typedef struct {
> > + UINTN OperationCount;
> > + EFI_I2C_OPERATION SetAddressOp;
> > + EFI_I2C_OPERATION GetSetDateTimeOp;
> > +} RTC_I2C_REQUEST;
> > +
> > +#endif // __PCF2129RTC_H__
> > diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> > new file mode 100644
> > index 0000000..2e21014
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> > @@ -0,0 +1,330 @@
> > +/** @PCF2129RtcLib.c
> > + Implement EFI RealTimeClock with runtime services via RTC Lib for
> PCF2129 RTC.
> > +
> > + Based on RTC implementation available in
> > + EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
> > +
> > + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials
> > + are licensed and made available under the terms and conditions of the
> BSD License
> > + which accompanies this distribution. The full text of the license may be
> found at
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cac3a81
> 31870a4f555cbc08d5a5ddfdc8%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636597295251146941&sdata=WheF7lR6B7iBUJBG2TGfGzJoiVhO%2F
> I1VZywt3l%2FeXug%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#include <PiDxe.h>
> > +#include <Base.h>
> > +#include <Library/BaseLib.h>
> > +#include <Library/DebugLib.h>
> > +#include <Library/RealTimeClockLib.h>
> > +#include <Library/UefiBootServicesTableLib.h>
> > +#include <Library/UefiLib.h>
> > +#include <Protocol/I2cMaster.h>
> > +
> > +#include "Pcf2129Rtc.h"
> > +
> > +STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
> > +
> > +/**
> > + returns Day of the week [0-6] 0=Sunday
> > + Don't try to provide a Year that's before 1998, please !
>
> (You should probably add an assert for that, in that case.)
>
OK
> > + **/
> > +UINTN
> > +EfiTimeToWday (
>
> This looks like a completely generic function. Could it be submitted
> to edk2 EmbeddedPkg/Library/TimeBaseLib?
>
Will send
> > + IN EFI_TIME *Time
> > + )
> > +{
> > + UINTN MonthDiff;
> > + UINTN Year;
> > + UINTN Month;
> > + UINTN JulianDate; // Absolute Julian Date representation of the
> supplied Time
> > + UINTN EpochDays; // Number of days elapsed since
> EPOCH_JULIAN_DAY
> > +
> > + MonthDiff = (14 - Time->Month) / 12 ;
> > + Year = Time->Year + 4800 - MonthDiff;
> > + Month = Time->Month + (12*MonthDiff) - 3;
> > +
> > + JulianDate = Time->Day + ((153*Month + 2)/5) + (365*Year) + (Year/4) -
> (Year/100) + (Year/400) - 32045;
> > +
> > + ASSERT (JulianDate >= EPOCH_JULIAN_DATE);
> > + EpochDays = JulianDate - EPOCH_JULIAN_DATE;
> > +
> > + // 4=1/1/1998 was a Thursday
>
> Extra space in indentation.
Will correct, thanks for catching.
>
> > +
> > + return (EpochDays + 4) % 7;
> > +}
> > +
> > +/**
> > + Write RTC register.
> > +
> > + @param RtcRegAddr Register offset of RTC to write.
> > + @param Val Value to be written
> > +
> > +**/
> > +
> > +STATIC
> > +VOID
> > +RtcWrite (
> > + IN UINT8 RtcRegAddr,
> > + IN UINT8 Val
> > + )
> > +{
> > + RTC_I2C_REQUEST Req;
> > + EFI_STATUS Status;
> > +
> > + Req.OperationCount = 2;
> > +
> > + Req.SetAddressOp.Flags = 0;
> > + Req.SetAddressOp.LengthInBytes = 0;
> > + Req.SetAddressOp.Buffer = &RtcRegAddr;
> > +
> > + Req.GetSetDateTimeOp.Flags = 0;
> > + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
> > + Req.GetSetDateTimeOp.Buffer = &Val;
> > +
> > + Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8
> (PcdI2cSlaveAddress),
> > + (VOID *)&Req,
> > + NULL, NULL);
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n",
> RtcRegAddr));
> > + }
> > +
> > +}
> > +
> > +/**
> > + Returns the current time and date information, and the time-keeping
> capabilities
> > + of the hardware platform.
> > +
> > + @param Time A pointer to storage to receive a snapshot of the
> current time.
> > + @param Capabilities An optional pointer to a buffer to receive the
> real time clock
> > + device's capabilities.
> > +
> > + @retval EFI_SUCCESS The operation completed successfully.
> > + @retval EFI_INVALID_PARAMETER Time is NULL.
> > + @retval EFI_DEVICE_ERROR The time could not be retrieved due to
> hardware error.
> > +
> > +**/
> > +
> > +EFI_STATUS
> > +EFIAPI
> > +LibGetTime (
> > + OUT EFI_TIME *Time,
> > + OUT EFI_TIME_CAPABILITIES *Capabilities
> > + )
> > +{
> > + EFI_STATUS Status;
> > + UINT8 Buffer[10];
> > + RTC_I2C_REQUEST Req;
> > + UINT8 RtcRegAddr;
> > +
> > + Status = EFI_SUCCESS;
> > + RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
> > + Buffer[0] = 0;
> > +
> > + if (mI2cMaster == NULL) {
> > + return EFI_DEVICE_ERROR;
> > + }
> > +
> > + RtcWrite (PCF2129_CTRL1_REG_ADDR, Buffer[0]);
> > +
> > + if (Time == NULL) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + Req.OperationCount = 2;
> > +
> > + Req.SetAddressOp.Flags = 0;
> > + Req.SetAddressOp.LengthInBytes = 0;
> > + Req.SetAddressOp.Buffer = &RtcRegAddr;
> > +
> > + Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
> > + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Buffer);
> > + Req.GetSetDateTimeOp.Buffer = Buffer;
> > +
> > + Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8
> (PcdI2cSlaveAddress),
> > + (VOID *)&Req,
> > + NULL, NULL);
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n",
> RtcRegAddr));
> > + }
> > +
> > + if (Buffer[PCF2129_CTRL3_REG_ADDR] & PCF2129_CTRL3_BIT_BLF) {
> > + DEBUG((DEBUG_INFO, "### Warning: RTC battery status low,
> check/replace RTC battery.\n"));
> > + }
> > +
> > + Time->Nanosecond = 0;
> > + Time->Second = BcdToDecimal8 (Buffer[PCF2129_SEC_REG_ADDR] &
> 0x7F);
> > + Time->Minute = BcdToDecimal8 (Buffer[PCF2129_MIN_REG_ADDR] &
> 0x7F);
> > + Time->Hour = BcdToDecimal8 (Buffer[PCF2129_HR_REG_ADDR] & 0x3F);
> > + Time->Day = BcdToDecimal8 (Buffer[PCF2129_DAY_REG_ADDR] & 0x3F);
> > + Time->Month = BcdToDecimal8 (Buffer[PCF2129_MON_REG_ADDR] &
> 0x1F);
>
> Ideally, I would like to see #defines for these masks.
>
Will define macro
> > + Time->Year = BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]) + (
> BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]) >= 98 ? 1900 : 2000);
>
> That is a very long line.
> It could be shortened substantially by using a temporary variable for
> BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]).
>
Sure
> > +
> > + return Status;
> > +}
> > +
> > +/**
> > + Sets the current local time and date information.
> > +
> > + @param Time A pointer to the current time.
> > +
> > + @retval EFI_SUCCESS The operation completed successfully.
> > + @retval EFI_INVALID_PARAMETER A time field is out of range.
> > + @retval EFI_DEVICE_ERROR The time could not be set due due to
> hardware error.
> > +
> > +**/
> > +
> > +EFI_STATUS
> > +EFIAPI
> > +LibSetTime (
> > + IN EFI_TIME *Time
> > + )
> > +{
> > + UINT8 Buffer[8];
> > + UINT8 Index;
> > + EFI_STATUS Status;
> > + RTC_I2C_REQUEST Req;
> > + UINT8 RtcRegAddr;
> > +
> > + Index = 0;
> > + Status = EFI_SUCCESS;
> > + RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
> > +
> > + if (mI2cMaster == NULL) {
> > + return EFI_DEVICE_ERROR;
> > + }
> > +
> > + // start register address
> > + Buffer[Index++] = PCF2129_SEC_REG_ADDR;
> > +
> > + // hours, minutes and seconds
> > + Buffer[Index++] = DecimalToBcd8 (Time->Second);
> > + Buffer[Index++] = DecimalToBcd8 (Time->Minute);
> > + Buffer[Index++] = DecimalToBcd8 (Time->Hour);
> > + Buffer[Index++] = DecimalToBcd8 (Time->Day);
> > + Buffer[Index++] = EfiTimeToWday (Time) & 0x07;
>
> Why mask at the call site?
>
In GetTime function, data is been read from RTC device so we need to mask the unnecessary bits
[as described in RTC registers] while
In SetTime, we are receiving the appropriate buffer so no need to mask the data.
> /
> Leif
>
> > + Buffer[Index++] = DecimalToBcd8 (Time->Month);
> > + Buffer[Index++] = DecimalToBcd8 (Time->Year % 100);
> > +
> > + Req.OperationCount = 2;
> > + Req.SetAddressOp.Flags = 0;
> > + Req.SetAddressOp.LengthInBytes = 0;
> > + Req.SetAddressOp.Buffer = &RtcRegAddr;
> > +
> > + Req.GetSetDateTimeOp.Flags = 0;
> > + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Buffer);
> > + Req.GetSetDateTimeOp.Buffer = Buffer;
> > +
> > + Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8
> (PcdI2cSlaveAddress),
> > + (VOID *)&Req,
> > + NULL, NULL);
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n",
> RtcRegAddr));
> > + return Status;
> > + }
> > +
> > + return Status;
> > +}
> > +
> > +
> > +/**
> > + Returns the current wakeup alarm clock setting.
> > +
> > + @param Enabled Indicates if the alarm is currently enabled or
> disabled.
> > + @param Pending Indicates if the alarm signal is pending and
> requires acknowledgement.
> > + @param Time The current alarm setting.
> > +
> > + @retval EFI_SUCCESS The alarm settings were returned.
> > + @retval EFI_INVALID_PARAMETER Any parameter is NULL.
> > + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved
> due to a hardware error.
> > + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this
> platform.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +LibGetWakeupTime (
> > + OUT BOOLEAN *Enabled,
> > + OUT BOOLEAN *Pending,
> > + OUT EFI_TIME *Time
> > + )
> > +{
> > + // Not a required feature
> > + return EFI_UNSUPPORTED;
> > +}
> > +
> > +
> > +/**
> > + Sets the system wakeup alarm clock time.
> > +
> > + @param Enabled Enable or disable the wakeup alarm.
> > + @param Time If Enable is TRUE, the time to set the wakeup
> alarm for.
> > +
> > + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was
> enabled. If
> > + Enable is FALSE, then the wakeup alarm was disabled.
> > + @retval EFI_INVALID_PARAMETER A time field is out of range.
> > + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to
> a hardware error.
> > + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this
> platform.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +LibSetWakeupTime (
> > + IN BOOLEAN Enabled,
> > + OUT EFI_TIME *Time
> > + )
> > +{
> > + // Not a required feature
> > + return EFI_UNSUPPORTED;
> > +}
> > +
> > +/**
> > + This is the declaration of an EFI image entry point. This can be the entry
> point to an application
> > + written to this specification, an EFI boot service driver, or an EFI runtime
> driver.
> > +
> > + @param ImageHandle Handle that identifies the loaded image.
> > + @param SystemTable System Table for this image.
> > +
> > + @retval EFI_SUCCESS The operation completed successfully.
> > + @retval EFI_DEVICE_ERROR The operation could not be started.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +LibRtcInitialize (
> > + IN EFI_HANDLE ImageHandle,
> > + IN EFI_SYSTEM_TABLE *SystemTable
> > + )
> > +{
> > +
> > + EFI_STATUS Status;
> > + EFI_I2C_MASTER_PROTOCOL *I2cMaster;
> > + UINTN BusFrequency;
> > +
> > + Status = gBS->LocateProtocol (&gEfiI2cMasterProtocolGuid, NULL, (VOID
> **)&I2cMaster);
> > +
> > + ASSERT_EFI_ERROR (Status);
> > +
> > + Status = I2cMaster->Reset (I2cMaster);
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
> > + __FUNCTION__, Status));
> > + return Status;
> > + }
> > +
> > + BusFrequency = FixedPcdGet32 (PcdI2cSpeed);
> > + Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed -
> %r\n",
> > + __FUNCTION__, Status));
> > + return Status;
> > + }
> > +
> > + mI2cMaster = I2cMaster;
> > +
> > + return EFI_SUCCESS;
> > +}
> > diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
> b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
> > new file mode 100644
> > index 0000000..873bcea
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
> > @@ -0,0 +1,47 @@
> > +#/** @Pcf2129RtcLib.inf
> > +#
> > +# Copyright 2017 NXP
> > +#
> > +# This program and the accompanying materials
> > +# are licensed and made available under the terms and conditions of the
> BSD License
> > +# which accompanies this distribution. The full text of the license may be
> found at
> > +#
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cac3a81
> 31870a4f555cbc08d5a5ddfdc8%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636597295251146941&sdata=WheF7lR6B7iBUJBG2TGfGzJoiVhO%2F
> I1VZywt3l%2FeXug%3D&reserved=0
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +#
> > +#
> > +#**/
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001A
> > + BASE_NAME = Pcf2129RtcLib
> > + FILE_GUID = B661E02D-A90B-42AB-A5F9-CF841AAA43D9
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = RealTimeClockLib
> > +
> > +
> > +[Sources.common]
> > + Pcf2129RtcLib.c
> > +
> > +[Packages]
> > + EmbeddedPkg/EmbeddedPkg.dec
> > + MdePkg/MdePkg.dec
> > + Silicon/NXP/NxpQoriqLs.dec
> > +
> > +[LibraryClasses]
> > + DebugLib
> > + UefiBootServicesTableLib
> > + UefiLib
> > +
> > +[Protocols]
> > + gEfiDriverBindingProtocolGuid ## CONSUMES
> > + gEfiI2cMasterProtocolGuid ## CONSUMES
> > +
> > +[Pcd]
> > + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus
> > + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
> > + gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress
> > +
> > +[Depex]
> > + gEfiI2cMasterProtocolGuid
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for PCF2129 Real Time Clock Library
2018-04-19 12:33 ` Meenakshi Aggarwal
@ 2018-04-19 13:47 ` Leif Lindholm
2018-04-20 3:20 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 13:47 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi, Vabhav Sharma
On Thu, Apr 19, 2018 at 12:33:50PM +0000, Meenakshi Aggarwal wrote:
> > > +EFI_STATUS
> > > +EFIAPI
> > > +LibSetTime (
> > > + IN EFI_TIME *Time
> > > + )
> > > +{
> > > + UINT8 Buffer[8];
> > > + UINT8 Index;
> > > + EFI_STATUS Status;
> > > + RTC_I2C_REQUEST Req;
> > > + UINT8 RtcRegAddr;
> > > +
> > > + Index = 0;
> > > + Status = EFI_SUCCESS;
> > > + RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
> > > +
> > > + if (mI2cMaster == NULL) {
> > > + return EFI_DEVICE_ERROR;
> > > + }
> > > +
> > > + // start register address
> > > + Buffer[Index++] = PCF2129_SEC_REG_ADDR;
> > > +
> > > + // hours, minutes and seconds
> > > + Buffer[Index++] = DecimalToBcd8 (Time->Second);
> > > + Buffer[Index++] = DecimalToBcd8 (Time->Minute);
> > > + Buffer[Index++] = DecimalToBcd8 (Time->Hour);
> > > + Buffer[Index++] = DecimalToBcd8 (Time->Day);
> > > + Buffer[Index++] = EfiTimeToWday (Time) & 0x07;
> >
> > Why mask at the call site?
> >
> In GetTime function, data is been read from RTC device so we need to
> mask the unnecessary bits
> [as described in RTC registers] while
> In SetTime, we are receiving the appropriate buffer so no need to
> mask the data.
But EfiTimeToWday returns an integer in the range 0-6:
return (EpochDays + 4) % 7;
Anding the result of that with 0x7 has no effect.
/
Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 20/39] Platform/NXP: LS1046A RDB Board Library
2018-02-16 8:50 ` [PATCH edk2-platforms 20/39] Platform/NXP: LS1046A RDB Board Library Meenakshi
@ 2018-04-19 13:49 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 13:49 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Vabhav
On Fri, Feb 16, 2018 at 02:20:16PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> Library to provide board specific timings for LS1046ARDB
> board with interfacing to IFC controller for accessing
> FPGA and NAND.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> .../NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h | 83 ++++++++++++++++++++++
> .../NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c | 61 ++++++++++++++++
> .../LS1046aRdbPkg/Library/BoardLib/BoardLib.inf | 31 ++++++++
> 3 files changed, 175 insertions(+)
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
>
> diff --git a/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h b/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
> new file mode 100644
> index 0000000..e15100d
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
> @@ -0,0 +1,83 @@
> +/** IfcBoardSpecificLib.h
> +
> + IFC Flash Board Specific Macros and structure
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +#ifndef __IFC__BOARD_SPECIFIC_H__
> +#define __IFC__BOARD_SPECIFIC_H__
> +
> +#include <Ifc.h>
> +
> +// On board flash support
> +#define IFC_NAND_BUF_BASE 0x7E800000
> +
> +// On board Inegrated flash Controller chip select configuration
> +#define IFC_NOR_CS IFC_CS_MAX
> +#define IFC_NAND_CS IFC_CS0
> +#define IFC_FPGA_CS IFC_CS2
> +
> +// board-specific NAND timing
> +#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x7) | \
> + IFC_FTIM0_NAND_TWP(0x18) | \
> + IFC_FTIM0_NAND_TWCHT(0x7) | \
> + IFC_FTIM0_NAND_TWH(0xa))
> +
> +#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x32) | \
> + IFC_FTIM1_NAND_TWBE(0x39) | \
> + IFC_FTIM1_NAND_TRR(0xe) | \
> + IFC_FTIM1_NAND_TRP(0x18))
> +
> +#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0xf) | \
> + IFC_FTIM2_NAND_TREH(0xa) | \
> + IFC_FTIM2_NAND_TWHRE(0x1e))
> +
> +#define NAND_FTIM3 0x0
> +
> +#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BUF_BASE) \
> + | IFC_CSPR_PORT_SIZE_8 \
> + | IFC_CSPR_MSEL_NAND \
> + | IFC_CSPR_V)
> +
> +#define NAND_CSPR_EXT 0x0
> +#define NAND_AMASK 0xFFFF0000
> +
> +#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
> + | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
> + | IFC_CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
> + | IFC_CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
> + | IFC_CSOR_NAND_PGS_4K /* Page Size = 4K */ \
> + | IFC_CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
> + | IFC_CSOR_NAND_PB(6)) /* 2^6 Pages Per Block */
> +
> +// board-specific fpga timing
> +#define FPGA_BASE_PHYS 0x7fb00000
> +#define FPGA_CSPR_EXT 0x0
> +#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
> + IFC_CSPR_PORT_SIZE_8 | \
> + IFC_CSPR_MSEL_GPCM | \
> + IFC_CSPR_V)
> +
> +#define FPGA_AMASK IFC_AMASK(64 * 1024)
> +#define FPGA_CSOR IFC_CSOR_NOR_ADM_SHIFT(16)
> +
> +#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0x0e) | \
> + IFC_FTIM0_GPCM_TEADC(0x0e) | \
> + IFC_FTIM0_GPCM_TEAHC(0x0e))
> +#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \
> + IFC_FTIM1_GPCM_TRAD(0x3f))
> +#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \
> + IFC_FTIM2_GPCM_TCH(0xf) | \
> + IFC_FTIM2_GPCM_TWP(0x3E))
> +#define FPGA_FTIM3 0x0
> +
> +#endif //__IFC__BOARD_SPECIFIC_H__
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
> new file mode 100644
> index 0000000..0971935
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
> @@ -0,0 +1,61 @@
> +/** @file
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <IfcBoardSpecific.h>
> +
> +VOID
> +GetIfcNorFlashTimings (
> + IN IFC_TIMINGS * NorIfcTimings
> + )
> +{
> + NorIfcTimings->CS = IFC_NOR_CS;
> +
> + return ;
> +}
> +
> +VOID
> +GetIfcFpgaTimings (
> + IN IFC_TIMINGS *FpgaIfcTimings
> + )
> +{
> + FpgaIfcTimings->Ftim[0] = FPGA_FTIM0;
> + FpgaIfcTimings->Ftim[1] = FPGA_FTIM1;
> + FpgaIfcTimings->Ftim[2] = FPGA_FTIM2;
> + FpgaIfcTimings->Ftim[3] = FPGA_FTIM3;
> + FpgaIfcTimings->Cspr = FPGA_CSPR;
> + FpgaIfcTimings->CsprExt = FPGA_CSPR_EXT;
> + FpgaIfcTimings->Amask = FPGA_AMASK;
> + FpgaIfcTimings->Csor = FPGA_CSOR;
> + FpgaIfcTimings->CS = IFC_FPGA_CS;
> +
> + return;
> +}
> +
> +VOID
> +GetIfcNandFlashTimings (
> + IN IFC_TIMINGS * NandIfcTimings
> + )
> +{
> + NandIfcTimings->Ftim[0] = NAND_FTIM0;
> + NandIfcTimings->Ftim[1] = NAND_FTIM1;
> + NandIfcTimings->Ftim[2] = NAND_FTIM2;
> + NandIfcTimings->Ftim[3] = NAND_FTIM3;
> + NandIfcTimings->Cspr = NAND_CSPR;
> + NandIfcTimings->CsprExt = NAND_CSPR_EXT;
> + NandIfcTimings->Amask = NAND_AMASK;
> + NandIfcTimings->Csor = NAND_CSOR;
> + NandIfcTimings->CS = IFC_NAND_CS;
> +
> + return;
> +}
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
> new file mode 100644
> index 0000000..151c383
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
> @@ -0,0 +1,31 @@
> +# @file
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = BoardLib
> + FILE_GUID = 66041dab-97b4-4b45-b9b4-1209a2d55d7a
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = BoardLib
> +
> +[Sources.common]
> + BoardLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[FixedPcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 21/39] Platform/NXP: Add ArmPlatformLib for LS1046A
2018-02-16 8:50 ` [PATCH edk2-platforms 21/39] Platform/NXP: Add ArmPlatformLib for LS1046A Meenakshi
@ 2018-04-19 13:53 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 13:53 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Vabhav
On Fri, Feb 16, 2018 at 02:20:17PM +0530, Meenakshi wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Adding support of ArmPlatformLib for NXP LS1046ARDB board
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> .../Library/PlatformLib/ArmPlatformLib.c | 105 ++++++++++++++
> .../Library/PlatformLib/ArmPlatformLib.inf | 66 +++++++++
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 35 +++++
> .../Library/PlatformLib/NxpQoriqLsMem.c | 152 +++++++++++++++++++++
> 4 files changed, 358 insertions(+)
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> new file mode 100644
> index 0000000..a0bb01d
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> @@ -0,0 +1,105 @@
> +/** ArmPlatformLib.c
> +*
> +* Contains board initialization functions.
> +*
> +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
> +*
> +* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +extern VOID SocInit (VOID);
> +
> +/**
> + Return the current Boot Mode
> +
> + This function returns the boot reason on the platform
> +
> +**/
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> + VOID
> + )
> +{
> + return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +/**
> + Placeholder for Platform Initialization
> +**/
> +EFI_STATUS
> +ArmPlatformInitialize (
> + IN UINTN MpId
> + )
> +{
> + SocInit ();
> +
> + return EFI_SUCCESS;
Indentation 2 spaces.
With that fixed:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> +}
> +
> +ARM_CORE_INFO LS1046aMpCoreInfoCTA72x4[] = {
> + {
> + // Cluster 0, Core 0
> + 0x0, 0x0,
> +
> + // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (UINT64)0xFFFFFFFF
> + },
> +};
> +
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> + OUT UINTN *CoreCount,
> + OUT ARM_CORE_INFO **ArmCoreTable
> + )
> +{
> + *CoreCount = sizeof (LS1046aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
> + *ArmCoreTable = LS1046aMpCoreInfoCTA72x4;
> +
> + return EFI_SUCCESS;
> +}
> +
> +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> +
> +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gArmMpCoreInfoPpiGuid,
> + &mMpCoreInfoPpi
> + }
> +};
> +
> +VOID
> +ArmPlatformGetPlatformPpiList (
> + OUT UINTN *PpiListSize,
> + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
> + )
> +{
> + *PpiListSize = sizeof (gPlatformPpiTable);
> + *PpiList = gPlatformPpiTable;
> +}
> +
> +
> +UINTN
> +ArmPlatformGetCorePosition (
> + IN UINTN MpId
> + )
> +{
> + return 1;
> +}
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> new file mode 100644
> index 0000000..49b57fc
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> @@ -0,0 +1,66 @@
> +# @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PlatformLib
> + FILE_GUID = 05a9029b-266f-421d-bb46-0e8385c64aa0
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ArmPlatformLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + ArmLib
> + SocLib
> +
> +[Sources.common]
> + NxpQoriqLsHelper.S | GCC
> + NxpQoriqLsMem.c
> + ArmPlatformLib.c
> +
> +[Ppis]
> + gArmMpCoreInfoPpiGuid
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdArmPrimaryCore
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> new file mode 100644
> index 0000000..6d54091
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> @@ -0,0 +1,35 @@
> +# @file
> +#
> +# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <AutoGen.h>
> +
> +.text
> +.align 2
> +
> +GCC_ASM_IMPORT(ArmReadMpidr)
> +
> +ASM_FUNC(ArmPlatformIsPrimaryCore)
> + tst x0, #3
> + cset x0, eq
> + ret
> +
> +ASM_FUNC(ArmPlatformPeiBootAction)
> + ret
> +
> +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
> + MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
> + ldrh w0, [x0]
> + ret
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> new file mode 100644
> index 0000000..64c5612
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> @@ -0,0 +1,152 @@
> +/** NxpQoriqLsMem.c
> +*
> +* Board memory specific Library.
> +*
> +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
> +*
> +* Copyright (c) 2011, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
> +
> +/**
> + Return the Virtual Memory Map of your platform
> +
> + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
> +
> + @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
> + Virtual Memory mapping. This array must be ended by a zero-filled
> + entry
> +
> +**/
> +
> +VOID
> +ArmPlatformGetVirtualMemoryMap (
> + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
> + )
> +{
> + UINTN Index;
> + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> +
> + Index = 0;
> +
> + ASSERT (VirtualMemoryMap != NULL);
> +
> + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
> + EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
> +
> + if (VirtualMemoryTable == NULL) {
> + return;
> + }
> +
> + // DRAM1 (Must be 1st entry)
> + VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // CCSR Space
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // IFC region 1
> + //
> + // A-009241 : Unaligned write transactions to IFC may result in corruption of data
> + // Affects : IFC
> + // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
> + // writes on external IFC interface that can corrupt data on external flash.
> + // Impact : Data corruption on external flash may happen in case of unaligned writes to
> + // IFC memory space.
> + // Workaround: Following are the workarounds:
> + // For write transactions from core, IFC interface memories (including IFC SRAM)
> + // should be configured as device type memory in MMU.
> + // For write transactions from non-core masters (like system DMA), the address
> + // should be 16 byte aligned and the data size should be multiple of 16 bytes.
> + //
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // QMAN SWP
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // BMAN SWP
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // IFC region 2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DRAM2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram2Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // PCIe1
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe3
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DRAM3
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram3BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram3BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram3Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // QSPI region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // End of Table
> + VirtualMemoryTable[++Index].PhysicalBase = 0;
> + VirtualMemoryTable[Index].VirtualBase = 0;
> + VirtualMemoryTable[Index].Length = 0;
> + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
> +
> + ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> + *VirtualMemoryMap = VirtualMemoryTable;
> +}
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 22/39] Platform/NXP: LS1046 RDB Board FPGA library
2018-02-16 8:50 ` [PATCH edk2-platforms 22/39] Platform/NXP: LS1046 RDB Board FPGA library Meenakshi
@ 2018-04-19 14:44 ` Leif Lindholm
2018-06-04 4:10 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 14:44 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Vabhav
On Fri, Feb 16, 2018 at 02:20:18PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> Library to provide functions for accessing FPGA
> on LS1046ARDB board.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
I compare this one to LS1043aRdbPkg/Library/FpgaLib, and the
differences in the .c file are
--- Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c 2018-04-18 15:13:08.507949763 +0100
+++ Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c 2018-04-18 15:13:08.531949605 +0100
@@ -1,5 +1,5 @@
/** @FpgaLib.c
- Fpga Library for LS1043A-RDB board, containing functions to
+ Fpga Library for LS1046A-RDB board, containing functions to
program and read the Fpga registers.
FPGA is connected to IFC Controller and so MMIO APIs are used
@@ -137,6 +137,8 @@
Sd1RefClkSel = FPGA_READ(Sd1RefClkSel);
DEBUG((DEBUG_INFO, "SD1_CLK1 = %a, SD1_CLK2 = %a\n",
Sd1RefClkSel ? SERDES_FREQ2 : SERDES_FREQ1, SERDES_FREQ1));
+ DEBUG((DEBUG_INFO, "SD2_CLK1 = %a, SD2_CLK2 = %a\n",
+ SERDES_FREQ1, SERDES_FREQ1));
return;
}
Could these two libraries be merged into a single LS104xx variant?
The LS2088a one seems to have substantial differences, so that makes
sense to keep separate.
No other comments on this patch.
/
Leif
> ---
> .../NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h | 97 ++++++++++++++
> .../NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c | 144 +++++++++++++++++++++
> .../NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf | 32 +++++
> 3 files changed, 273 insertions(+)
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
>
> diff --git a/Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h b/Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
> new file mode 100644
> index 0000000..c8f7411
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
> @@ -0,0 +1,97 @@
> +/** FpgaLib.h
> +* Header defining the LS1046a Fpga specific constants (Base addresses, sizes, flags)
> +*
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __LS1046A_FPGA_H__
> +#define __LS1046A_FPGA_H__
> +
> +/**
> + FPGA register set of LS1046ARDB board-specific.
> + **/
> +typedef struct {
> + UINT8 FpgaVersionMajor; // 0x0 - FPGA Major Revision Register
> + UINT8 FpgaVersionMinor; // 0x1 - FPGA Minor Revision Register
> + UINT8 PcbaVersion; // 0x2 - PCBA Revision Register
> + UINT8 SystemReset; // 0x3 - system reset register
> + UINT8 SoftMuxOn; // 0x4 - Switch Control Enable Register
> + UINT8 RcwSource1; // 0x5 - Reset config word 1
> + UINT8 RcwSource2; // 0x6 - Reset config word 1
> + UINT8 Vbank; // 0x7 - Flash bank selection Control
> + UINT8 SysclkSelect; // 0x8 - System clock selection Control
> + UINT8 UartSel; // 0x9 - Uart selection Control
> + UINT8 Sd1RefClkSel; // 0xA - Serdes1 reference clock selection Control
> + UINT8 TdmClkMuxSel; // 0xB - TDM Clock Mux selection Control
> + UINT8 SdhcSpiCsSel; // 0xC - SDHC/SPI Chip select selection Control
> + UINT8 StatusLed; // 0xD - Status Led
> + UINT8 GlobalReset; // 0xE - Global reset
> + UINT8 SdEmmc; // 0xF - SD or EMMC Interface Control Regsiter
> + UINT8 VddEn; // 0x10 - VDD Voltage Control Enable Register
> + UINT8 VddSel; // 0x11 - VDD Voltage Control Register
> +} FPGA_REG_SET;
> +
> +/**
> + Function to read FPGA register.
> +**/
> +UINT8
> +FpgaRead (
> + UINTN Reg
> + );
> +
> +/**
> + Function to write FPGA register.
> +**/
> +VOID
> +FpgaWrite (
> + UINTN Reg,
> + UINT8 Value
> + );
> +
> +/**
> + Function to read FPGA revision.
> +**/
> +VOID
> +FpgaRevBit (
> + UINT8 *Value
> + );
> +
> +/**
> + Function to initialize FPGA timings.
> +**/
> +VOID
> +FpgaInit (
> + VOID
> + );
> +
> +/**
> + Function to print board personality.
> +**/
> +VOID
> +PrintBoardPersonality (
> + VOID
> + );
> +
> +#define FPGA_BASE_PHYS 0x7fb00000
> +
> +#define SRC_VBANK 0x25
> +#define SRC_NAND 0x106
> +#define SRC_QSPI 0x44
> +#define SRC_SD 0x40
> +
> +#define SERDES_FREQ1 "100.00 MHz"
> +#define SERDES_FREQ2 "156.25 MHz"
> +
> +#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg))
> +#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), Value)
> +
> +#endif
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c b/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c
> new file mode 100644
> index 0000000..90cc1ea
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c
> @@ -0,0 +1,144 @@
> +/** @FpgaLib.c
> + Fpga Library for LS1046A-RDB board, containing functions to
> + program and read the Fpga registers.
> +
> + FPGA is connected to IFC Controller and so MMIO APIs are used
> + to read/write FPGA registers
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/FpgaLib.h>
> +#include <Library/IoLib.h>
> +
> +/**
> + Function to read FPGA register.
> +
> + @param Reg Register offset of FPGA to read.
> +
> +**/
> +UINT8
> +FpgaRead (
> + IN UINTN Reg
> + )
> +{
> + VOID *Base;
> +
> + Base = (VOID *)FPGA_BASE_PHYS;
> +
> + return MmioRead8 ((UINTN)(Base + Reg));
> +}
> +
> +/**
> + Function to write FPGA register.
> +
> + @param Reg Register offset of FPGA to write.
> + @param Value Value to be written.
> +
> +**/
> +VOID
> +FpgaWrite (
> + IN UINTN Reg,
> + IN UINT8 Value
> + )
> +{
> + VOID *Base;
> +
> + Base = (VOID *)FPGA_BASE_PHYS;
> +
> + MmioWrite8 ((UINTN)(Base + Reg), Value);
> +}
> +
> +/**
> + Function to reverse the number.
> +
> + @param *Value pointer to number to reverse.
> +
> + @retval *Value reversed value.
> +
> +**/
> +VOID
> +FpgaRevBit (
> + OUT UINT8 *Value
> + )
> +{
> + UINT8 Rev;
> + UINT8 Val;
> + UINTN Index;
> +
> + Val = *Value;
> + Rev = Val & 1;
> + for (Index = 1; Index <= 7; Index++) {
> + Val >>= 1;
> + Rev <<= 1;
> + Rev |= Val & 1;
> + }
> +
> + *Value = Rev;
> +}
> +
> +/**
> + Function to print board personality.
> +
> +**/
> +VOID
> +PrintBoardPersonality (
> + VOID
> + )
> +{
> + UINT8 RcwSrc1;
> + UINT8 RcwSrc2;
> + UINT32 RcwSrc;
> + UINT32 Sd1RefClkSel;
> +
> + RcwSrc1 = FPGA_READ(RcwSource1);
> + RcwSrc2 = FPGA_READ(RcwSource2);
> + FpgaRevBit (&RcwSrc1);
> + RcwSrc = RcwSrc1;
> + RcwSrc = (RcwSrc << 1) | RcwSrc2;
> +
> + switch (RcwSrc) {
> + case SRC_VBANK:
> + DEBUG ((DEBUG_INFO, "vBank: %d\n", FPGA_READ(Vbank)));
> + break;
> + case SRC_NAND:
> + DEBUG ((DEBUG_INFO, "NAND\n"));
> + break;
> + case SRC_QSPI:
> + DEBUG ((DEBUG_INFO, "QSPI vBank %d\n", FPGA_READ(Vbank)));
> + break;
> + case SRC_SD:
> + DEBUG ((DEBUG_INFO, "SD\n"));
> + break;
> + default:
> + DEBUG ((DEBUG_INFO, "Invalid setting of SW5\n"));
> + break;
> + }
> +
> + DEBUG ((DEBUG_INFO, "FPGA: V%x.%x\nPCBA: V%x.0\n",
> + FPGA_READ(FpgaVersionMajor),
> + FPGA_READ(FpgaVersionMinor),
> + FPGA_READ(PcbaVersion)));
> +
> + DEBUG ((DEBUG_INFO, "SERDES Reference Clocks:\n"));
> +
> + Sd1RefClkSel = FPGA_READ(Sd1RefClkSel);
> + DEBUG((DEBUG_INFO, "SD1_CLK1 = %a, SD1_CLK2 = %a\n",
> + Sd1RefClkSel ? SERDES_FREQ2 : SERDES_FREQ1, SERDES_FREQ1));
> + DEBUG((DEBUG_INFO, "SD2_CLK1 = %a, SD2_CLK2 = %a\n",
> + SERDES_FREQ1, SERDES_FREQ1));
> +
> + return;
> +}
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
> new file mode 100644
> index 0000000..afc41e3
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
> @@ -0,0 +1,32 @@
> +# @FpgaLib.inf
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001000A
> + BASE_NAME = FpgaLib
> + FILE_GUID = 6e06ebbf-3a1d-47be-b4f6-1d82f2a9ac73
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = FpgaLib
> +
> +[Sources.common]
> + FpgaLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + IoLib
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 23/39] Platform/NXP: Compilation for LS1046A RDB Board
2018-02-16 8:50 ` [PATCH edk2-platforms 23/39] Platform/NXP: Compilation for LS1046A RDB Board Meenakshi
@ 2018-04-19 14:54 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 14:54 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Vabhav
On Fri, Feb 16, 2018 at 02:20:19PM +0530, Meenakshi wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Adding firmware device,description and declaration files to enable
> compilation for NXP LS1046ARDB board.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
No comments on this beyond the aforementioned include handling and
varstore changes for upstream.
/
Leif
> ---
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec | 29 ++++
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 94 +++++++++++++
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 197 +++++++++++++++++++++++++++
> 3 files changed, 320 insertions(+)
> create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
> create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
>
> diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
> new file mode 100644
> index 0000000..a872ade
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
> @@ -0,0 +1,29 @@
> +# LS1046aRdbPkg.dec
> +# LS1046a board package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + PACKAGE_NAME = LS1046aRdbPkg
> + PACKAGE_GUID = c0c8d5e4-f63b-4470-89bc-73c13c13b247
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +# Supported Module Types:
> +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
> diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> new file mode 100644
> index 0000000..36002d5
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> @@ -0,0 +1,94 @@
> +# LS1046aRdbPkg.dsc
> +#
> +# LS1046ARDB Board package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + #
> + # Defines for default states. These can be changed on the command line.
> + # -D FLAG=VALUE
> + #
> + PLATFORM_NAME = LS1046aRdbPkg
> + PLATFORM_GUID = 43920156-3f3b-4199-9b29-c6db1fb792b0
> + OUTPUT_DIRECTORY = Build/LS1046aRdbPkg
> + FLASH_DEFINITION = Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> +
> +!include ../NxpQoriqLs.dsc
> +!include ../../../Silicon/NXP/LS1046A/LS1046A.dsc
> +
> +[LibraryClasses.common]
> + ArmPlatformLib|Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> + BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf
> + SocLib|Silicon/NXP/Chassis/LS1046aSocLib.inf
> + RealTimeClockLib|Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
> + IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
> + BoardLib|Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
> + FpgaLib|Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
> +
> +[PcdsFixedAtBuild.common]
> +
> + #
> + # LS1046a board Specific PCDs
> + # XX (DRAM - Region 1 2GB)
> + # (NOR - IFC Region 1 512MB)
> + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
> + gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
> + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
> +
> + #
> + # Board Specific Pcds
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x2
> +
> + #
> + # Big Endian IPs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
> +
> + #
> + # I2C controller Pcds
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|3
> +
> + #
> + # RTC Pcds
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|100000
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> + #
> + # Architectural Protocols
> + #
> + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> +
> + Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> + Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> +
> + ##
> diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> new file mode 100644
> index 0000000..834e3a4
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> @@ -0,0 +1,197 @@
> +# LS1046aRdbPkg.fdf
> +#
> +# FLASH layout file for LS1046a board.
> +#
> +# Copyright (c) 2016, Freescale Ltd. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into the Flash Device Image. Each FD section
> +# defines one flash "device" image. A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash" image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +################################################################################
> +
> +[FD.LS1046ARDB_EFI]
> +BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
> +Size = 0x000EC890|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
> +ErasePolarity = 1
> +BlockSize = 0x1
> +NumBlocks = 0xEC890
> +
> +################################################################################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +#
> +################################################################################
> +0x00000000|0x000EC890
> +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> +FV = FVMAIN_COMPACT
> +
> +!include ../FVRules.fdf.inc
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed within a flash
> +# device file. This section also defines order the components and modules are positioned
> +# within the image. The [FV] section consists of define statements, set statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
> +BlockSize = 0x1
> +NumBlocks = 0 # This FV gets compressed so make it just big enough
> +FvAlignment = 8 # FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF MdeModulePkg/Core/Dxe/DxeMain.inf
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +
> + #
> + # PI DXE Drivers producing Architectural Protocols (EFI Services)
> + #
> + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> +
> + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + INF Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> +
> + INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> +
> + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> +
> + #
> + # Multiple Console IO support
> + #
> + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
> +
> + #
> + # Network modules
> + #
> + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
> +!if $(NETWORK_IP6_ENABLE) == TRUE
> + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + INF NetworkPkg/TcpDxe/TcpDxe.inf
> + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> +!else
> + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> +!endif
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + INF FatPkg/FatPei/FatPei.inf
> + INF FatPkg/EnhancedFatDxe/Fat.inf
> +
> + #
> + # UEFI application (Shell Embedded Boot Loader)
> + #
> + INF ShellPkg/Application/Shell/Shell.inf
> +
> + #
> + # Bds
> + #
> + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + INF MdeModulePkg/Application/UiApp/UiApp.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment = 8
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF ArmPlatformPkg/PrePi/PeiUniCore.inf
> +
> + FILE FV_IMAGE = c1c1e1a2-3879-4b5e-9dd1-3df2ce60d8ec {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> + }
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 24/39] Silicon/NXP:SocLib support for initialization of peripherals
2018-02-16 8:50 ` [PATCH edk2-platforms 24/39] Silicon/NXP:SocLib support for initialization of peripherals Meenakshi
@ 2018-04-19 15:20 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 15:20 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Wasim Khan
A few style comments in addition to the requested layout changes.
On Fri, Feb 16, 2018 at 02:20:20PM +0530, Meenakshi wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
>
> Added SocInit function that initializes peripherals
> and print board and soc information for LS2088ARDB Board.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> ---
> Silicon/NXP/Chassis/Chassis.c | 35 ++++++
> Silicon/NXP/Chassis/Chassis.h | 17 +++
> Silicon/NXP/Chassis/Chassis3/Chassis3.dec | 19 ++++
> Silicon/NXP/Chassis/Chassis3/SerDes.h | 91 +++++++++++++++
> Silicon/NXP/Chassis/Chassis3/Soc.c | 180 ++++++++++++++++++++++++++++++
> Silicon/NXP/Chassis/Chassis3/Soc.h | 150 +++++++++++++++++++++++++
> Silicon/NXP/Chassis/LS2088aSocLib.inf | 48 ++++++++
> Silicon/NXP/LS2088A/Include/SocSerDes.h | 67 +++++++++++
> 8 files changed, 607 insertions(+)
> create mode 100644 Silicon/NXP/Chassis/Chassis3/Chassis3.dec
> create mode 100644 Silicon/NXP/Chassis/Chassis3/SerDes.h
> create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.c
> create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.h
> create mode 100644 Silicon/NXP/Chassis/LS2088aSocLib.inf
> create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h
>
> diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c
> index ce07fdc..b63efdc 100644
> --- a/Silicon/NXP/Chassis/Chassis.c
> +++ b/Silicon/NXP/Chassis/Chassis.c
> @@ -45,6 +45,7 @@ GurRead (
> STATIC CPU_TYPE CpuTypeList[] = {
> CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
> CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
> + CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
> };
>
> /*
> @@ -142,6 +143,40 @@ CpuNumCores (
> }
>
> /*
> + * Return core's cluster
> + */
> +UINT32
> +QoriqCoreToCluster (
> + IN UINTN Core
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINTN ClusterIndex;
> + UINTN Count;
> + UINT32 Cluster;
> + UINT32 Type;
> + UINTN InitiatorIndex;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClusterIndex = 0;
> + Count = 0;
> + do {
> + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> + Type = InitiatorType (Cluster, InitiatorIndex);
> + if (Type) {
> + if (Count == Core)
Always {} with if.
> + return ClusterIndex;
> + Count++;
> + }
> + }
> + ClusterIndex++;
> + } while (CHECK_CLUSTER (Cluster));
> +
> + return -1; // cannot identify the cluster
> +}
> +
> +/*
> * Return the type of core i.e. A53, A57 etc of inputted
> * core number.
> */
> diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h
> index 0beb44c..974fefb 100644
> --- a/Silicon/NXP/Chassis/Chassis.h
> +++ b/Silicon/NXP/Chassis/Chassis.h
> @@ -57,6 +57,7 @@ CpuMaskNext (
> #define SVR_WO_E 0xFFFFFE
> #define SVR_LS1043A 0x879200
> #define SVR_LS1046A 0x870700
> +#define SVR_LS2088A 0x870901
>
> #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> #define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> @@ -142,4 +143,20 @@ CpuNumCores (
> VOID
> );
>
> +/*
> + * Return the type of initiator for core/hardware accelerator for given core index.
> + */
> +UINT32
> +QoriqCoreToType (
> + IN UINTN Core
> + );
> +
> +/*
> + * Return the cluster of initiator for core/hardware accelerator for given core index.
> + */
> +UINT32
> +QoriqCoreToCluster (
> + IN UINTN Core
> + );
> +
> #endif /* __CHASSIS_H__ */
> diff --git a/Silicon/NXP/Chassis/Chassis3/Chassis3.dec b/Silicon/NXP/Chassis/Chassis3/Chassis3.dec
> new file mode 100644
> index 0000000..cf41b3c
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/Chassis3/Chassis3.dec
> @@ -0,0 +1,19 @@
> +# @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x00010005
0x0001001a
> +
> +[Includes]
> + .
> diff --git a/Silicon/NXP/Chassis/Chassis3/SerDes.h b/Silicon/NXP/Chassis/Chassis3/SerDes.h
> new file mode 100644
> index 0000000..a77ddd5
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/Chassis3/SerDes.h
> @@ -0,0 +1,91 @@
> +/** SerDes.h
> + The Header file of SerDes Module for Chassis 3
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __SERDES_H__
> +#define __SERDES_H__
> +
> +#include <Uefi/UefiBaseType.h>
> +
> +#define SRDS_MAX_LANES 8
> +
> +//
> +// SerDes lane protocols/devices
> +//
> +typedef enum {
> + NONE = 0,
> + PCIE1,
> + PCIE2,
> + PCIE3,
> + PCIE4,
> + SATA1,
> + SATA2,
> + XAUI1,
> + XAUI2,
> + XFI1,
> + XFI2,
> + XFI3,
> + XFI4,
> + XFI5,
> + XFI6,
> + XFI7,
> + XFI8,
> + SGMII1,
> + SGMII2,
> + SGMII3,
> + SGMII4,
> + SGMII5,
> + SGMII6,
> + SGMII7,
> + SGMII8,
> + SGMII9,
> + SGMII10,
> + SGMII11,
> + SGMII12,
> + SGMII13,
> + SGMII14,
> + SGMII15,
> + SGMII16,
> + QSGMII_A,
> + QSGMII_B,
> + QSGMII_C,
> + QSGMII_D,
> + // Number of entries in this enum
> + SERDES_PRTCL_COUNT
> +} SERDES_PROTOCOL;
> +
> +typedef enum {
> + SRDS_1 = 0,
> + SRDS_2,
> + SRDS_MAX_NUM
> +} SERDES_NUMBER;
> +
> +typedef struct {
> + UINT16 Protocol;
> + UINT8 SrdsLane[SRDS_MAX_LANES];
> +} SERDES_CONFIG;
> +
> +typedef VOID
> +(*SERDES_PROBE_LANES_CALLBACK) (
> + IN SERDES_PROTOCOL LaneProtocol,
> + IN VOID *Arg
> + );
> +
> +VOID
> +SerDesProbeLanes(
> + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> + IN VOID *Arg
> + );
> +
> +#endif /* __SERDES_H */
> diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.c b/Silicon/NXP/Chassis/Chassis3/Soc.c
> new file mode 100644
> index 0000000..ed6c3cc
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/Chassis3/Soc.c
> @@ -0,0 +1,180 @@
> +/** @Soc.c
> + SoC specific Library containg functions to initialize various SoC components
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Chassis.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib/MemLibInternals.h>
Please use CopyMem directly instead.
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +#include "Soc.h"
> +
> +VOID
> +GetSysInfo (
> + OUT SYS_INFO *PtrSysInfo
> + )
> +{
> + UINT32 Index;
> + CCSR_GUR *GurBase;
> + CCSR_CLT_CTRL *ClkBase;
> + CCSR_CLK_CLUSTER *ClkGrp[2] = {
> + (VOID *) (FSL_CLK_GRPA_ADDR),
> + (VOID *) (FSL_CLK_GRPB_ADDR)
> + };
> +
> + const UINT8 CoreCplxPll[16] = {
CONST
> + [0] = 0, // CC1 PPL / 1
> + [1] = 0, // CC1 PPL / 2
> + [2] = 0, // CC1 PPL / 4
> + [4] = 1, // CC2 PPL / 1
> + [5] = 1, // CC2 PPL / 2
> + [6] = 1, // CC2 PPL / 4
> + [8] = 2, // CC3 PPL / 1
> + [9] = 2, // CC3 PPL / 2
> + [10] = 2, // CC3 PPL / 4
> + [12] = 3, // CC4 PPL / 1
> + [13] = 3, // CC4 PPL / 2
> + [14] = 3, // CC4 PPL / 4
> + };
> +
> + const UINT8 CoreCplxPllDivisor[16] = {
> + [0] = 1, // CC1 PPL / 1
> + [1] = 2, // CC1 PPL / 2
> + [2] = 4, // CC1 PPL / 4
> + [4] = 1, // CC2 PPL / 1
> + [5] = 2, // CC2 PPL / 2
> + [6] = 4, // CC2 PPL / 4
> + [8] = 1, // CC3 PPL / 1
> + [9] = 2, // CC3 PPL / 2
> + [10] = 4, // CC3 PPL / 4
> + [12] = 1, // CC4 PPL / 1
> + [13] = 2, // CC4 PPL / 2
> + [14] = 4, // CC4 PPL / 4
> + };
> +
> + INT32 CcGroup[12] = FSL_CLUSTER_CLOCKS;
> + UINTN PllCount;
> + UINTN Cluster;
> + UINTN FreqCPll[NUM_CC_PLLS];
> + UINTN PllRatio[NUM_CC_PLLS];
> + UINTN SysClk;
> + UINT32 Cpu;
> + UINT32 CPllSel;
> + UINT32 CplxPll;
> + VOID *Offset;
> +
> + SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
> + SysClk = CLK_FREQ;
> +
> + PtrSysInfo->FreqSystemBus = SysClk;
> + PtrSysInfo->FreqDdrBus = PcdGet64 (PcdDdrClk);
> + PtrSysInfo->FreqDdrBus2 = PcdGet64 (PcdDdrClk);
> +
> + //
> + // selects the platform clock:SYSCLK ratio and calculate
> + // system frequency
> + //
> + PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> + CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT) &
> + CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK;
Indent like so?:
PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT) &
CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK;
> +
> + //
> + // Platform clock is half of platform PLL
> + //
> + PtrSysInfo->FreqSystemBus /= PcdGet32 (PcdPlatformFreqDiv);
> +
> + //
> + // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
> + //
> + PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> + CHASSIS3_RCWSR_0_MEM_PLL_RAT_SHIFT) &
> + CHASSIS3_RCWSR_0_MEM_PLL_RAT_MASK;
> + PtrSysInfo->FreqDdrBus2 *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> + CHASSIS3_RCWSR_0_MEM2_PLL_RAT_SHIFT) &
> + CHASSIS3_RCWSR_0_MEM2_PLL_RAT_MASK;
Same indentation change above, x2?
> +
> + for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
> + Offset = (VOID *)((UINTN)ClkGrp[PllCount/3] +
> + __builtin_offsetof (CCSR_CLK_CLUSTER, PllnGsr[PllCount%3].Gsr));
> + PllRatio[PllCount] = (GurRead ((UINTN)Offset) >> 1) & 0x3f;
> + FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
> + }
> +
> + //
> + // Calculate Core frequency
> + //
> + ForEachCpu (Index, Cpu, CpuNumCores (), CpuMask ()) {
> + Cluster = QoriqCoreToCluster (Cpu);
> + ASSERT_EFI_ERROR (Cluster);
> + CPllSel = (GurRead ((UINTN)&ClkBase->ClkCnCsr[Cluster].Csr) >> 27) & 0xf;
> + CplxPll = CoreCplxPll[CPllSel];
> + CplxPll += CcGroup[Cluster] - 1;
> + PtrSysInfo->FreqProcessor[Cpu] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
> + }
> + PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
> +}
> +
> +/**
> + Perform the early initialization.
> + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
> +
> +**/
> +VOID
> +SocInit (
> + VOID
> + )
> +{
> + CHAR8 Buffer[100];
> + UINTN CharCount;
> +
> + //
> + // Initialize SMMU
> + //
> + SmmuInit ();
> +
> + //
> + // Initialize the Serial Port.
> + // Early serial port initialization is required to print RCW, Soc and CPU infomation at
> + // the begining of UEFI boot.
> + //
> + SerialPortInitialize ();
> +
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\nUEFI firmware (version %s built at %a on %a)\n\r",
Can you move the format string to the line below, indented, to keep
line length down?
> + (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__);
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> +
> + //
> + // Print CPU information
> + //
> + PrintCpuInfo ();
> +
> + //
> + // Print Reset Controll Word
> + //
> + PrintRCW ();
> +
> + //
> + // Print Soc Personality information
> + //
> + PrintSoc ();
> +}
> +
> diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.h b/Silicon/NXP/Chassis/Chassis3/Soc.h
> new file mode 100644
> index 0000000..0e892fb
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/Chassis3/Soc.h
> @@ -0,0 +1,150 @@
> +/** Soc.h
> +* Header defining the Base addresses, sizes, flags etc for chassis 1
> +*
> +* Copyright (c) 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __SOC_H__
> +#define __SOC_H__
> +
> +#define MAX_CPUS 16
> +#define FSL_CLK_GRPA_ADDR 0x01300000
> +#define FSL_CLK_GRPB_ADDR 0x01310000
> +#define NUM_CC_PLLS 6
> +#define CLK_FREQ 100000000
> +
> +#define FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } /* LS208x */
> +#define TP_CLUSTER_EOC_MASK 0x80000000 /* Mask for End of clusters */
> +#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) != TP_CLUSTER_EOC_MASK)
> +
> +// RCW SERDES MACRO
> +#define RCWSR_INDEX 28
> +#define RCWSR_SRDS1_PRTCL_MASK 0x00ff0000
> +#define RCWSR_SRDS1_PRTCL_SHIFT 16
> +#define RCWSR_SRDS2_PRTCL_MASK 0xff000000
> +#define RCWSR_SRDS2_PRTCL_SHIFT 24
> +
> +// SMMU Defintions
> +#define SMMU_BASE_ADDR 0x05000000
> +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> +
> +#define SACR_PAGESIZE_MASK 0x00010000
> +#define SCR0_CLIENTPD_MASK 0x00000001
> +#define SCR0_USFCFG_MASK 0x00000400
> +
> +typedef struct {
> + UINTN FreqProcessor[MAX_CPUS];
> + UINTN FreqSystemBus;
> + UINTN FreqDdrBus;
> + UINTN FreqDdrBus2;
> + UINTN FreqLocalBus;
> + UINTN FreqSdhc;
> + UINTN FreqFman[1];
> + UINTN FreqQman;
> + UINTN FreqPme;
> +}SYS_INFO;
> +
> +///
> +/// Device Configuration and Pin Control
> +///
> +typedef struct {
> + UINT32 PorSr1; // POR status register 1
> + UINT32 PorSr2; // POR status register 2
> + UINT8 Res008[0x20-0x8];
Just a note here: I see what this is doing, it is perfectly legal C,
and I don't see anything in the code style banning it.
But I don't think I've come across it before :)
/
Leif
> + UINT32 GppOrCr1; // General-purpose POR configuration register
> + UINT32 GppOrCr2; // General-purpose POR configuration register 2
> + UINT32 DcfgFuseSr; // Fuse status register */
> + UINT32 GppOrCr3;
> + UINT32 GppOrCr4;
> + UINT8 Res034[0x70-0x34];
> + UINT32 DevDisr; // Device disable control register
> + UINT32 DevDisr2; // Device disable control register 2
> + UINT32 DevDisr3; // Device disable control register 3
> + UINT32 DevDisr4; // Device disable control register 4
> + UINT32 DevDisr5; // Device disable control register 5
> + UINT32 DevDisr6; // Device disable control register 6
> + UINT32 DevDisr7; // Device disable control register 7
> + UINT8 Res08c[0x90-0x8c];
> + UINT32 CoreDisrUpper; // CORE DISR Uppper for support of 64 cores
> + UINT32 CoreDisrLower; // CORE DISR Lower for support of 64 cores
> + UINT8 Res098[0xa0-0x98];
> + UINT32 Pvr; // Processor version
> + UINT32 Svr; // System version
> + UINT32 Mvr; // Manufacturing version
> + UINT8 Res0ac[0x100-0xac];
> + UINT32 RcwSr[32]; // Reset control word status
> +#define CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT 2
> +#define CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK 0x1f
> +#define CHASSIS3_RCWSR_0_MEM_PLL_RAT_SHIFT 10
> +#define CHASSIS3_RCWSR_0_MEM_PLL_RAT_MASK 0x3f
> +#define CHASSIS3_RCWSR_0_MEM2_PLL_RAT_SHIFT 18
> +#define CHASSIS3_RCWSR_0_MEM2_PLL_RAT_MASK 0x3f
> + UINT8 Res180[0x200-0x180];
> + UINT32 ScratchRw[32]; // Scratch Read/Write
> + UINT8 Res280[0x300-0x280];
> + UINT32 ScratchW1R[4]; // Scratch Read (Write once)
> + UINT8 Res310[0x400-0x310];
> + UINT32 BootLocPtrL; // Low addr : Boot location pointer
> + UINT32 BootLocPtrH; // High addr : Boot location pointer
> + UINT8 Res408[0x500-0x408];
> + UINT8 Res500[0x740-0x500];
> + UINT32 TpItyp[64];
> + struct {
> + UINT32 Upper;
> + UINT32 Lower;
> + } TpCluster[3];
> + UINT8 Res858[0x1000-0x858];
> +} CCSR_GUR;
> +
> +///
> +/// Clocking
> +///
> +typedef struct {
> + struct {
> + UINT32 Csr; // core cluster n clock control status
> + UINT8 Res04[0x20-0x04];
> + } ClkCnCsr[8];
> +} CCSR_CLT_CTRL;
> +
> +///
> +/// Clock Cluster
> +///
> +typedef struct {
> + struct {
> + UINT8 Res00[0x10];
> + UINT32 Csr; // core cluster n clock control status
> + UINT8 Res14[0x20-0x14];
> + } HwnCsr[3];
> + UINT8 Res60[0x80-0x60];
> + struct {
> + UINT32 Gsr; // core cluster n clock general status
> + UINT8 Res84[0xa0-0x84];
> + } PllnGsr[3];
> + UINT8 Rese0[0x100-0xe0];
> +} CCSR_CLK_CLUSTER;
> +
> +VOID
> +GetSysInfo (
> + OUT SYS_INFO *
> + );
> +
> +UINT32
> +EFIAPI
> +GurRead (
> + IN UINTN Address
> + );
> +
> +#endif /* __SOC_H__ */
> diff --git a/Silicon/NXP/Chassis/LS2088aSocLib.inf b/Silicon/NXP/Chassis/LS2088aSocLib.inf
> new file mode 100644
> index 0000000..8a4da50
> --- /dev/null
> +++ b/Silicon/NXP/Chassis/LS2088aSocLib.inf
> @@ -0,0 +1,48 @@
> +# @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = SocLib
> + FILE_GUID = 3b233a6a-0ee1-42a3-a7f7-c285b5ba80dc
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SocLib
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/Chassis/Chassis3/Chassis3.dec
> + Silicon/NXP/LS2088A/LS2088A.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BeIoLib
> + DebugLib
> + SerialPortLib
> +
> +[Sources.common]
> + Chassis.c
> + Chassis3/Soc.c
> + SerDes.c
> +
> +[FixedPcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDdrClk
> diff --git a/Silicon/NXP/LS2088A/Include/SocSerDes.h b/Silicon/NXP/LS2088A/Include/SocSerDes.h
> new file mode 100644
> index 0000000..f631ccb
> --- /dev/null
> +++ b/Silicon/NXP/LS2088A/Include/SocSerDes.h
> @@ -0,0 +1,67 @@
> +/** @file
> + The Header file of SerDes Module for LS2088A
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __SOC_SERDES_H__
> +#define __SOC_SERDES_H__
> +
> +#include <SerDes.h>
> +
> +SERDES_CONFIG SerDes1ConfigTbl[] = {
> + // SerDes 1
> + { 0x03, { PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
> + { 0x05, { PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
> + { 0x07, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
> + { 0x09, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
> + { 0x0A, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
> + { 0x0C, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
> + { 0x0E, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
> + { 0x26, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
> + { 0x28, { SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
> + { 0x2A, { XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
> + { 0x2B, { SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
> + { 0x32, { XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
> + { 0x33, { PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B, QSGMII_A } },
> + { 0x35, { QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
> + {}
> +};
> +
> +SERDES_CONFIG SerDes2ConfigTbl[] = {
> + // SerDes 2
> + { 0x07, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
> + { 0x09, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
> + { 0x0A, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
> + { 0x0C, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
> + { 0x0E, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
> + { 0x3D, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
> + { 0x3E, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
> + { 0x3F, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
> + { 0x40, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
> + { 0x41, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
> + { 0x42, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
> + { 0x43, { PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
> + { 0x44, { PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
> + { 0x45, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, PCIE4 } },
> + { 0x47, { PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, SGMII16 } },
> + { 0x49, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } },
> + { 0x4A, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } },
> + {}
> +};
> +
> +SERDES_CONFIG *SerDesConfigTbl[] = {
> + SerDes1ConfigTbl,
> + SerDes2ConfigTbl
> +};
> +
> +#endif /* __SOC_SERDES_H */
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 25/39] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB
2018-02-16 8:50 ` [PATCH edk2-platforms 25/39] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB Meenakshi
@ 2018-04-19 15:59 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 15:59 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Wasim Khan
On Fri, Feb 16, 2018 at 02:20:21PM +0530, Meenakshi wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
>
> Add support of ArmPlatformLib for NXP LS2088ARDB board
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> .../Library/PlatformLib/ArmPlatformLib.c | 106 ++++++++++++
> .../Library/PlatformLib/ArmPlatformLib.inf | 77 +++++++++
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 35 ++++
> .../Library/PlatformLib/NxpQoriqLsMem.c | 189 +++++++++++++++++++++
> 4 files changed, 407 insertions(+)
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> new file mode 100644
> index 0000000..90f14ba
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> @@ -0,0 +1,106 @@
> +/** ArmPlatformLib.c
> +*
> +* Contains board initialization functions.
> +*
> +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
> +*
> +* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +extern VOID SocInit (VOID);
> +
> +/**
> + Return the current Boot Mode
> +
> + This function returns the boot reason on the platform
> +
> +**/
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> + VOID
> + )
> +{
> + return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +/**
> + Placeholder for Platform Initialization
> +
> +**/
> +EFI_STATUS
> +ArmPlatformInitialize (
> + IN UINTN MpId
> + )
> +{
> + SocInit ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +ARM_CORE_INFO LS2088aMpCoreInfoCTA72x4[] = {
> + {
> + // Cluster 0, Core 0
> + 0x0, 0x0,
> +
> + // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (UINT64)0xFFFFFFFF
> + },
> +};
> +
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> + OUT UINTN *CoreCount,
> + OUT ARM_CORE_INFO **ArmCoreTable
> + )
> +{
> + *CoreCount = sizeof (LS2088aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
> + *ArmCoreTable = LS2088aMpCoreInfoCTA72x4;
> +
> + return EFI_SUCCESS;
> +}
> +
> +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> +
> +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gArmMpCoreInfoPpiGuid,
> + &mMpCoreInfoPpi
> + }
> +};
> +
> +VOID
> +ArmPlatformGetPlatformPpiList (
> + OUT UINTN *PpiListSize,
> + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
> + )
> +{
> + *PpiListSize = sizeof (gPlatformPpiTable);
> + *PpiList = gPlatformPpiTable;
> +}
> +
> +
> +UINTN
> +ArmPlatformGetCorePosition (
> + IN UINTN MpId
> + )
> +{
> + return 1;
> +}
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> new file mode 100644
> index 0000000..f5e5abd
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> @@ -0,0 +1,77 @@
> +#/** @file
> +#
> +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PlatformLib
> + FILE_GUID = d1361285-8a47-421c-9efd-6b262c9093fc
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ArmPlatformLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + ArmLib
> + SocLib
> +
> +[Sources.common]
> + ArmPlatformLib.c
> + NxpQoriqLsHelper.S | GCC
> + NxpQoriqLsMem.c
> +
> +
> +[Ppis]
> + gArmMpCoreInfoPpiGuid
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdArmPrimaryCore
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
> + gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsCacheSize
> +
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> new file mode 100644
> index 0000000..1917b02
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> @@ -0,0 +1,35 @@
> +#/** @file
> +#
> +# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#**/
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <AutoGen.h>
> +
> +.text
> +.align 2
> +
> +GCC_ASM_IMPORT(ArmReadMpidr)
> +
> +ASM_FUNC(ArmPlatformIsPrimaryCore)
> + tst x0, #3
> + cset x0, eq
> + ret
> +
> +ASM_FUNC(ArmPlatformPeiBootAction)
> + ret
> +
> +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
> + MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
> + ldrh w0, [x0]
> + ret
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> new file mode 100644
> index 0000000..ccb49f6
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> @@ -0,0 +1,189 @@
> +/** NxpQoriqLsMem.c
> +*
> +* Board memory specific Library.
> +*
> +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
> +*
> +* Copyright (c) 2011, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
> +
> +//
> +// Calculate the MC (Management Complex) base address and DDR size based on
> +// if the MC is loaded in DDR low memory region or in DDR high memory region.
> +//
> +#if FixedPcdGetBool (PcdMcHighMemSupport)
> +#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemSize) - FixedPcdGet64 (PcdDpaa2McRamSize)
> +#define MC_BASE_ADDR FixedPcdGet64 (PcdDram2BaseAddr) + DDR_MEM_SIZE
> +#else
> +#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemSize)
> +#define MC_BASE_ADDR FixedPcdGet64 (PcdDram1BaseAddr) - FixedPcdGet64 (PcdDpaa2McRamSize)
> +#endif
> +
> +
> +/**
> + Return the Virtual Memory Map of your platform
> +
> + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
> +
> + @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
> + Virtual Memory mapping. This array must be ended by a zero-filled
> + entry
> +
> +**/
> +
> +VOID
> +ArmPlatformGetVirtualMemoryMap (
> + IN ARM_MEMORY_REGION_DESCRIPTOR ** VirtualMemoryMap
> + )
> +{
> + UINTN Index;
> + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> +
> + Index = 0;
> +
> + ASSERT (VirtualMemoryMap != NULL);
> +
> + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
> + EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
> +
> + if (VirtualMemoryTable == NULL) {
> + return;
> + }
> +
> + // DRAM1 (Must be 1st entry)
> + VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
> +
> + // CCSR Space
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // IFC region 1
> + //
> + // A-009241 : Unaligned write transactions to IFC may result in corruption of data
> + // Affects : IFC
> + // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
> + // writes on external IFC interface that can corrupt data on external flash.
> + // Impact : Data corruption on external flash may happen in case of unaligned writes to
> + // IFC memory space.
> + // Workaround: Following are the workarounds:
> + // For write transactions from core, IFC interface memories (including IFC SRAM)
> + // should be configured as device type memory in MMU.
> + // For write transactions from non-core masters (like system DMA), the address
> + // should be 16 byte aligned and the data size should be multiple of 16 bytes.
> + //
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // IFC region 2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // QSPI region 1
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // QSPI region 2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegion2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegion2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegion2Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // DRAM2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr);
> + VirtualMemoryTable[Index].Length = DDR_MEM_SIZE;
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
> +
> + // MC private DRAM
> + VirtualMemoryTable[++Index].PhysicalBase = MC_BASE_ADDR;
> + VirtualMemoryTable[Index].VirtualBase = MC_BASE_ADDR;
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2McRamSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe1
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe3
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe4
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp4BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp4BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp4BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DPAA2 MC Portals region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2McPortalBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2McPortalBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2McPortalSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DPAA2 NI Portals region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2NiPortalsBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2NiPortalsBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2NiPortalsSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DPAA2 QBMAN Portals - cache enabled region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
> +
> + // DPAA2 QBMAN Portals - cache inhibited region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2QBmanPortalSize) - FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // End of Table
> + VirtualMemoryTable[++Index].PhysicalBase = 0;
> + VirtualMemoryTable[Index].VirtualBase = 0;
> + VirtualMemoryTable[Index].Length = 0;
> + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
> +
> + ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> + *VirtualMemoryMap = VirtualMemoryTable;
> +}
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 26/39] Silicon/Maxim: DS3232 RTC Library Support
2018-02-16 8:50 ` [PATCH edk2-platforms 26/39] Silicon/Maxim: DS3232 RTC Library Support Meenakshi
@ 2018-04-19 16:02 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 16:02 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Wasim Khan
On Fri, Feb 16, 2018 at 02:20:22PM +0530, Meenakshi wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
>
> Add Maxim DS3232 RTC Library support
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h | 49 +++
> Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c | 370 +++++++++++++++++++++
> .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec | 31 ++
> .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf | 49 +++
> 4 files changed, 499 insertions(+)
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
>
> diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
> new file mode 100644
> index 0000000..cd1a321
> --- /dev/null
> +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
> @@ -0,0 +1,49 @@
> +/** Ds3232Rtc.h
> +*
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __DS3232RTC_H__
> +#define __DS3232RTC_H__
> +
> +//RTC time register
> +#define DS3232_SEC_REG_ADDR 0x00
> +#define DS3232_MIN_REG_ADDR 0x01
> +#define DS3232_HR_REG_ADDR 0x02
> +#define DS3232_DAY_REG_ADDR 0x03
> +#define DS3232_DATE_REG_ADDR 0x04
> +#define DS3232_MON_REG_ADDR 0x05
> +#define DS3232_YR_REG_ADDR 0x06
> +
> +#define DS3232_SEC_BIT_CH 0x80 // Clock Halt (in Register 0)
> +
> +//RTC control register
> +#define DS3232_CTL_REG_ADDR 0x0e
> +#define DS3232_STAT_REG_ADDR 0x0f
> +
> +#define START_YEAR 1970
> +#define END_YEAR 2070
> +
> +//TIME MASKS
> +#define MASK_SEC 0x7F
> +#define MASK_MIN 0x7F
> +#define MASK_HOUR 0x3F
> +#define MASK_DAY 0x3F
> +#define MASK_MONTH 0x1F
> +
> +typedef struct {
> + UINTN OperationCount;
> + EFI_I2C_OPERATION SetAddressOp;
> + EFI_I2C_OPERATION GetSetDateTimeOp;
> +} RTC_I2C_REQUEST;
> +
> +#endif // __DS3232RTC_H__
> diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
> new file mode 100644
> index 0000000..1a852e9
> --- /dev/null
> +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
> @@ -0,0 +1,370 @@
> +/** Ds3232RtcLib.c
> +* Implement EFI RealTimeClock via RTC Lib for DS3232 RTC.
> +*
> +* Based on RTC implementation available in
> +* EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
> +*
> +* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <PiDxe.h>
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/RealTimeClockLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +#include <Protocol/I2cMaster.h>
> +
> +#include "Ds3232Rtc.h"
> +
> +STATIC VOID *mDriverEventRegistration;
> +STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
> +
> +/**
> + Read RTC register.
> +
> + @param SlaveDeviceAddress Slave device address offset of RTC to be read.
> + @param RtcRegAddr Register offset of RTC to be read.
> +
> + @retval Register Value read
> +
> +**/
> +STATIC
> +UINT8
> +RtcRead (
> + IN UINT8 SlaveDeviceAddress,
> + IN UINT8 RtcRegAddr
> + )
> +{
> + RTC_I2C_REQUEST Req;
> + EFI_STATUS Status;
> + UINT8 Val;
> +
> + Val = 0;
> +
> + Req.OperationCount = 2;
> +
> + Req.SetAddressOp.Flags = 0;
> + Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
> + Req.SetAddressOp.Buffer = &RtcRegAddr;
> +
> + Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
> + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
> + Req.GetSetDateTimeOp.Buffer = &Val;
> +
> + Status = mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress,
> + (VOID *)&Req,
> + NULL, NULL);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
> + }
> +
> + return Val;
> +}
> +
> +/**
> + Write RTC register.
> +
> + @param SlaveDeviceAddress Slave device address offset of RTC to be read.
> + @param RtcRegAddr Register offset of RTC to write.
> + @param Val Value to be written
> +
> +**/
> +STATIC
> +VOID
> +RtcWrite (
> + IN UINT8 SlaveDeviceAddress,
> + IN UINT8 RtcRegAddr,
> + IN UINT8 Val
> + )
> +{
> + RTC_I2C_REQUEST Req;
> + EFI_STATUS Status;
> +
> + Req.OperationCount = 2;
> +
> + Req.SetAddressOp.Flags = 0;
> + Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
> + Req.SetAddressOp.Buffer = &RtcRegAddr;
> +
> + Req.GetSetDateTimeOp.Flags = 0;
> + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
> + Req.GetSetDateTimeOp.Buffer = &Val;
> +
> + Status = mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress,
> + (VOID *)&Req,
> + NULL, NULL);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
> + }
> +}
> +
> +/**
> + Configure the MUX device connected to I2C.
> +
> + @param RegValue Value to write on mux device register address
> +
> +**/
> +VOID
> +ConfigureMuxDevice (
> + IN UINT8 RegValue
> + )
> +{
> + RtcWrite (FixedPcdGet8 (PcdMuxDeviceAddress), FixedPcdGet8 (PcdMuxControlRegOffset), RegValue);
> +}
> +
> +/**
> + Returns the current time and date information, and the time-keeping capabilities
> + of the hardware platform.
> +
> + @param Time A pointer to storage to receive a snapshot of the current time.
> + @param Capabilities An optional pointer to a buffer to receive the real time clock
> + device's capabilities.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_INVALID_PARAMETER Time is NULL.
> + @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibGetTime (
> + OUT EFI_TIME *Time,
> + OUT EFI_TIME_CAPABILITIES *Capabilities
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 Second;
> + UINT8 Minute;
> + UINT8 Hour;
> + UINT8 Day;
> + UINT8 Month;
> + UINT8 Year;
> +
> + if (mI2cMaster == NULL) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + Status = EFI_SUCCESS;
> +
> + //
> + // Check if the I2C device is connected though a MUX device.
> + //
> + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
> + // Switch to the channel connected to Ds3232 RTC
> + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxRtcChannelValue));
> + }
> +
> + Second = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR);
> + Minute = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MIN_REG_ADDR);
> + Hour = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_HR_REG_ADDR);
> + Day = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_DATE_REG_ADDR);
> + Month = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MON_REG_ADDR);
> + Year = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_YR_REG_ADDR);
> +
> + if (Second & DS3232_SEC_BIT_CH) {
> + DEBUG ((DEBUG_ERROR, "### Warning: RTC oscillator has stopped\n"));
> + /* clear the CH flag */
> + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR,
> + RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR) & ~DS3232_SEC_BIT_CH);
> + Status = EFI_DEVICE_ERROR;
> + goto EXIT;
> + }
> +
> + Time->Second = BcdToDecimal8 (Second & MASK_SEC);
> + Time->Minute = BcdToDecimal8 (Minute & MASK_MIN);
> + Time->Hour = BcdToDecimal8 (Hour & MASK_HOUR);
> + Time->Day = BcdToDecimal8 (Day & MASK_DAY);
> + Time->Month = BcdToDecimal8 (Month & MASK_MONTH);
> +
> + //
> + // RTC can save year 1970 to 2069
> + // On writing Year, save year % 100
> + // On Reading reversing the operation e.g. 2012
> + // write = 12 (2012 % 100)
> + // read = 2012 (12 + 2000)
> + //
> + Time->Year = BcdToDecimal8 (Year) +
> + (BcdToDecimal8 (Year) >= 70 ? START_YEAR - 70 : END_YEAR -70);
> +
> +EXIT:
> + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
> + // Switch to the default channel
> + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxDefaultChannelValue));
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Sets the current local time and date information.
> +
> + @param Time A pointer to the current time.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_INVALID_PARAMETER A time field is out of range.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibSetTime (
> + IN EFI_TIME *Time
> + )
> +{
> + if (mI2cMaster == NULL) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + if (Time->Year < START_YEAR || Time->Year >= END_YEAR){
> + DEBUG ((DEBUG_ERROR, "WARNING: Year should be between 1970 and 2069!\n"));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Check if the I2C device is connected though a MUX device.
> + //
> + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
> + // Switch to the channel connected to Ds3232 RTC
> + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxRtcChannelValue));
> + }
> +
> + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_YR_REG_ADDR, DecimalToBcd8 (Time->Year % 100));
> + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MON_REG_ADDR, DecimalToBcd8 (Time->Month));
> + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_DATE_REG_ADDR, DecimalToBcd8 (Time->Day));
> + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_HR_REG_ADDR, DecimalToBcd8 (Time->Hour));
> + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MIN_REG_ADDR, DecimalToBcd8 (Time->Minute));
> + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR, DecimalToBcd8 (Time->Second));
> +
> + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
> + // Switch to the default channel
> + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxDefaultChannelValue));
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Returns the current wakeup alarm clock setting.
> +
> + @param Enabled Indicates if the alarm is currently enabled or disabled.
> + @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
> + @param Time The current alarm setting.
> +
> + @retval EFI_SUCCESS The alarm settings were returned.
> + @retval EFI_INVALID_PARAMETER Any parameter is NULL.
> + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibGetWakeupTime (
> + OUT BOOLEAN *Enabled,
> + OUT BOOLEAN *Pending,
> + OUT EFI_TIME *Time
> + )
> +{
> + // Currently not supporting this feature.
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + Sets the system wakeup alarm clock time.
> +
> + @param Enabled Enable or disable the wakeup alarm.
> + @param Time If Enable is TRUE, the time to set the wakeup alarm for.
> +
> + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
> + Enable is FALSE, then the wakeup alarm was disabled.
> + @retval EFI_INVALID_PARAMETER A time field is out of range.
> + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
> + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibSetWakeupTime (
> + IN BOOLEAN Enabled,
> + OUT EFI_TIME *Time
> + )
> +{
> + // Currently not supporting this feature.
> + return EFI_UNSUPPORTED;
> +}
> +
> +STATIC
> +VOID
> +I2cDriverRegistrationEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EFI_STATUS Status;
> + EFI_I2C_MASTER_PROTOCOL *I2cMaster;
> + UINTN BusFrequency;
> +
> + Status = gBS->LocateProtocol (&gEfiI2cMasterProtocolGuid, NULL, (VOID **)&I2cMaster);
> +
> + gBS->CloseEvent (Event);
> +
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = I2cMaster->Reset (I2cMaster);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
> + __FUNCTION__, Status));
> + return;
> + }
> +
> + BusFrequency = FixedPcdGet16 (PcdI2cBusFrequency);
> + Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
> + __FUNCTION__, Status));
> + return;
> + }
> +
> + mI2cMaster = I2cMaster;
> +}
> +
> +/**
> + This is the declaration of an EFI image entry point. This can be the entry point to an application
> + written to this specification, an EFI boot service driver.
> +
> + @param ImageHandle Handle that identifies the loaded image.
> + @param SystemTable System Table for this image.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibRtcInitialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + //
> + // Register a protocol registration notification callback on the driver
> + // binding protocol so we can attempt to connect our I2C master to it
> + // as soon as it appears.
> + //
> + EfiCreateProtocolNotifyEvent (
> + &gEfiI2cMasterProtocolGuid,
> + TPL_CALLBACK,
> + I2cDriverRegistrationEvent,
> + NULL,
> + &mDriverEventRegistration);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> new file mode 100644
> index 0000000..4471d57
> --- /dev/null
> +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> @@ -0,0 +1,31 @@
> +#/** @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#**/
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x0001001A
> + PACKAGE_NAME = Ds3232RtcLib
> + PACKAGE_GUID = 0b4192f7-e404-4019-b2e5-1e6004da3313
> + PACKAGE_VERSION = 0.1
> +
> +[Guids]
> + gDs3232RtcLibTokenSpaceGuid = { 0x7960fc51, 0x0832, 0x4f0b, { 0xb4, 0x22, 0x53, 0x87, 0x03, 0xaa, 0x85, 0xda }}
> +
> +[PcdsFixedAtBuild]
> + gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001
> + gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002
> + gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed|FALSE|BOOLEAN|0x00000003
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress|0|UINT8|0x00000004
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset|0|UINT8|0x00000005
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0|UINT8|0x00000006
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0|UINT8|0x00000007
> diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> new file mode 100644
> index 0000000..9cac100
> --- /dev/null
> +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> @@ -0,0 +1,49 @@
> +# @Ds3232RtcLib.inf
> +#
> +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = Ds3232RtcLib
> + FILE_GUID = 97f1f2c2-51e1-47ad-9660-70b33da1fe71
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = RealTimeClockLib
> +
> +[Sources.common]
> + Ds3232RtcLib.c
> +
> +[Packages]
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> +
> +[LibraryClasses]
> + DebugLib
> + UefiBootServicesTableLib
> + UefiLib
> +
> +[Protocols]
> + gEfiI2cMasterProtocolGuid ## CONSUMES
> +
> +[FixedPcd]
> + gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress
> + gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency
> + gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue
> +
> +[Depex]
> + gEfiI2cMasterProtocolGuid
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 27/39] Compilation : Add the fdf, dsc and dec files
2018-02-16 8:50 ` [PATCH edk2-platforms 27/39] Compilation : Add the fdf, dsc and dec files Meenakshi
@ 2018-04-19 16:28 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 16:28 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Wasim Khan
On Fri, Feb 16, 2018 at 02:20:23PM +0530, Meenakshi wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
>
> The firmware device, description and declaration files for LS2088 board
>
Apart from the varstore and include handling change, can you bump the
DEC_SPECIFICATION entry to 0x0001001a?
Nothing else on this patch.
/
Leif
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> ---
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec | 29 ++++
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 100 ++++++++++++++
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 198 +++++++++++++++++++++++++++
> Silicon/NXP/LS2088A/LS2088A.dec | 22 +++
> Silicon/NXP/LS2088A/LS2088A.dsc | 71 ++++++++++
> Silicon/NXP/NxpQoriqLs.dec | 13 ++
> 6 files changed, 433 insertions(+)
> create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
> create mode 100755 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> create mode 100644 Silicon/NXP/LS2088A/LS2088A.dec
> create mode 100644 Silicon/NXP/LS2088A/LS2088A.dsc
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
> new file mode 100644
> index 0000000..93d2e5a
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
> @@ -0,0 +1,29 @@
> +# LS2088aRdbPkg.dec
> +# LS2088a board package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + PACKAGE_NAME = LS2088aRdbPkg
> + PACKAGE_GUID = 474e0c59-5f77-4060-82dd-9025ee4f4939
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +# Supported Module Types:
> +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> new file mode 100755
> index 0000000..c0a802d
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> @@ -0,0 +1,100 @@
> +# LS2088aRdbPkg.dsc
> +#
> +# LS2088ARDB Board package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + #
> + # Defines for default states. These can be changed on the command line.
> + # -D FLAG=VALUE
> + #
> + PLATFORM_NAME = LS2088aRdbPkg
> + PLATFORM_GUID = be06d8bc-05eb-44d6-b39f-191e93617ebd
> + OUTPUT_DIRECTORY = Build/LS2088aRdbPkg
> + FLASH_DEFINITION = Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> + DEFINE MC_HIGH_MEM = TRUE
> +
> +!include ../NxpQoriqLs.dsc
> +!include ../../../Silicon/NXP/LS2088A/LS2088A.dsc
> +
> +[LibraryClasses.common]
> + ArmPlatformLib|Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> + BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf
> + SocLib|Silicon/NXP/Chassis/LS2088aSocLib.inf
> + RealTimeClockLib|Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> +
> +[PcdsFixedAtBuild.common]
> +
> +!if $(MC_HIGH_MEM) == TRUE # Management Complex loaded at the end of DDR2
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000 # Actual base address (0x0080000000)
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000 # 2 GB
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x80000000 # 2GB (PcdDpaa2McRamSize must be 512MB aligned)
> + gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|1
> + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0080000000 # Actual base
> + gArmTokenSpaceGuid.PcdSystemMemorySize|0x0080000000 # 2G
> +!else
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x00A0000000 # Actual base address (0x0080000000) + 512MB
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0060000000 # 2GB - 512MB
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x20000000 # 512MB (Fixed)
> + gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|0
> + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00A0000000 # Actual base + 512MB
> + gArmTokenSpaceGuid.PcdSystemMemorySize|0x0060000000 # 2G - 512MB
> +!endif
> + gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x380000000 # 14 GB
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x8080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x8800000000 # 512 GB
> + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
> +
> + #
> + # Board Specific Pcds
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0600
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x2
> + gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|133333333
> +
> + #
> + # I2C controller Pcds
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0
> +
> + #
> + # RTC Pcds
> + #
> + gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
> + gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
> + gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed|TRUE
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress|0x75
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset|0x09
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0x09
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0x08
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> + #
> + # Architectural Protocols
> + #
> + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
> + Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> new file mode 100644
> index 0000000..14072a6
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> @@ -0,0 +1,198 @@
> +# LS2088aRdbPkg.fdf
> +#
> +# FLASH layout file for LS2088a board.
> +#
> +# Copyright (c) 2016, Freescale Ltd. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into the Flash Device Image. Each FD section
> +# defines one flash "device" image. A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash" image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +################################################################################
> +
> +[FD.LS2088aRdb_EFI]
> +BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
> +Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
> +ErasePolarity = 1
> +BlockSize = 0x1
> +NumBlocks = 0x00100000
> +
> +################################################################################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +#
> +################################################################################
> +0x00000000|0x00100000
> +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> +FV = FVMAIN_COMPACT
> +
> +!include ../FVRules.fdf.inc
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed within a flash
> +# device file. This section also defines order the components and modules are positioned
> +# within the image. The [FV] section consists of define statements, set statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
> +BlockSize = 0x1
> +NumBlocks = 0 # This FV gets compressed so make it just big enough
> +FvAlignment = 8 # FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF MdeModulePkg/Core/Dxe/DxeMain.inf
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +
> + #
> + # PI DXE Drivers producing Architectural Protocols (EFI Services)
> + #
> + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> +
> + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
> + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> +
> + INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> +
> + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> +
> + #
> + # Multiple Console IO support
> + #
> + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
> +
> + #
> + # Network modules
> + #
> + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
> +!if $(NETWORK_IP6_ENABLE) == TRUE
> + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + INF NetworkPkg/TcpDxe/TcpDxe.inf
> + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> +!else
> + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> +!endif
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + INF FatPkg/FatPei/FatPei.inf
> + INF FatPkg/EnhancedFatDxe/Fat.inf
> +
> + #
> + # UEFI application (Shell Embedded Boot Loader)
> + #
> + INF ShellPkg/Application/Shell/Shell.inf
> +
> + #
> + # Bds
> + #
> + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + INF MdeModulePkg/Application/UiApp/UiApp.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment = 8
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF ArmPlatformPkg/PrePi/PeiUniCore.inf
> +
> + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> + }
> +
> diff --git a/Silicon/NXP/LS2088A/LS2088A.dec b/Silicon/NXP/LS2088A/LS2088A.dec
> new file mode 100644
> index 0000000..8539c63
> --- /dev/null
> +++ b/Silicon/NXP/LS2088A/LS2088A.dec
> @@ -0,0 +1,22 @@
> +# LS2088A.dec
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x00010005
> +
> +[Guids.common]
> + gNxpLs2088ATokenSpaceGuid = {0xaf770da7, 0x264c, 0x4857, {0x9d, 0xed, 0x56, 0x5e, 0x2c, 0x08, 0x7e, 0x26}}
> +
> +[Includes]
> + Include
> diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc b/Silicon/NXP/LS2088A/LS2088A.dsc
> new file mode 100644
> index 0000000..8f7dbb5
> --- /dev/null
> +++ b/Silicon/NXP/LS2088A/LS2088A.dsc
> @@ -0,0 +1,71 @@
> +# LS2088A.dsc
> +# LS2088A Soc package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +[PcdsDynamicDefault.common]
> +
> + #
> + # ARM General Interrupt Controller
> + gArmTokenSpaceGuid.PcdGicDistributorBase|0x6000000
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x6100000
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x00
> +
> +[PcdsFixedAtBuild.common]
> +
> + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0C000000
> + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|266666666 #266MHz
> +
> + #
> + # ARM L2x0 PCDs
> + gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x10900000
> +
> + #
> + # CCSR Address Space and other attached Memories
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x1370000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x30000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x10000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x510000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0xF0000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x3EEA
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x20000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x10000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x400000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x10000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x2000000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000 # 32 GB
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x2800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 # 32 GB
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x3000000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 # 32 GB
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x3800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x800000000 # 32 GB
> + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x8080000000 # Extended System Memory Base
> + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0380000000 # 14GB Extended System Memory Size
> + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x3100000
> + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x10000
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x1E00000
> + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x02140000
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02000000
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> +
> +##
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 39753e7..3cb476d 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -92,6 +92,18 @@
> gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
>
> #
> + # DPAA2 PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x0|UINT64|0x000001E0
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalBaseAddr|0x0|UINT64|0x000001E1
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalSize|0x0|UINT64|0x000001E2
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsBaseAddr|0x0|UINT64|0x000001E3
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsSize|0x0|UINT64|0x000001E4
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsBaseAddr|0x0|UINT64|0x000001E5
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalSize|0x0|UINT64|0x000001E6
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsCacheSize|0x0|UINT64|0x000001E7
> +
> + #
> # NV Pcd
> #
> gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
> @@ -102,6 +114,7 @@
> #
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
> gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
> + gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|FALSE|BOOLEAN|0x00000252
> gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE|BOOLEAN|0x00000253
>
> #
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 28/39] Platform/NXP: LS2088A RDB Board Library
2018-02-16 8:50 ` [PATCH edk2-platforms 28/39] Platform/NXP: LS2088A RDB Board Library Meenakshi
@ 2018-04-19 16:28 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 16:28 UTC (permalink / raw)
To: Meenakshi
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Wasim Khan
On Fri, Feb 16, 2018 at 02:20:24PM +0530, Meenakshi wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
>
> Library to provide board specific timings for LS2088ARDB
> board with interfacing to IFC controller for accessing
> NOR, NAND and FPGA.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> .../NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h | 114 +++++++++++++++++++++
> .../NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c | 69 +++++++++++++
> .../LS2088aRdbPkg/Library/BoardLib/BoardLib.inf | 28 +++++
> 3 files changed, 211 insertions(+)
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h b/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
> new file mode 100644
> index 0000000..174a242
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
> @@ -0,0 +1,114 @@
> +/** IfcBoardSpecificLib.h
> +
> + IFC Flash Board Specific Macros and structure
> +
> + Copyright 2017-2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +#ifndef __IFC__BOARD_SPECIFIC_H__
> +#define __IFC__BOARD_SPECIFIC_H__
> +
> +#include <Ifc.h>
> +
> +// On board flash support
> +#define IFC_NAND_BUF_BASE 0x530000000ULL
> +
> +// On board Inegrated flash Controller chip select configuration
> +#define IFC_NOR_CS IFC_CS0
> +#define IFC_NAND_CS IFC_CS2
> +#define IFC_FPGA_CS IFC_CS3
> +
> +
> +/* board-specific NAND timing */
> +#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x0e) | \
> + IFC_FTIM0_NAND_TWP(0x30) | \
> + IFC_FTIM0_NAND_TWCHT(0x0e) | \
> + IFC_FTIM0_NAND_TWH(0x14))
> +
> +#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x64) | \
> + IFC_FTIM1_NAND_TWBE(0xab) | \
> + IFC_FTIM1_NAND_TRR(0x1c) | \
> + IFC_FTIM1_NAND_TRP(0x30))
> +
> +#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0x1e) | \
> + IFC_FTIM2_NAND_TREH(0x14) | \
> + IFC_FTIM2_NAND_TWHRE(0x3c))
> +
> +#define NAND_FTIM3 0x0
> +
> +#define IFC_NAND_BASE_PHYS 0x30000000
> +#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BASE_PHYS) \
> + | IFC_CSPR_PORT_SIZE_8 \
> + | IFC_CSPR_MSEL_NAND \
> + | IFC_CSPR_V)
> +
> +#define NAND_CSPR_EXT 0x0
> +#define NAND_AMASK 0xFFFF0000
> +
> +#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
> + | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
> + | IFC_CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
> + | IFC_CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
> + | IFC_CSOR_NAND_PGS_4K /* Page Size = 4K */ \
> + | IFC_CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
> + | IFC_CSOR_NAND_PB(7)) /* 2^7 Pages Per Block */
> +
> +// board-specific NOR timing
> +#define NOR_FTIM0 (IFC_FTIM0_NOR_TACSE(0x4) | \
> + IFC_FTIM0_NOR_TEADC(0x5) | \
> + IFC_FTIM0_NOR_TEAHC(0x5))
> +
> +#define NOR_FTIM1 (IFC_FTIM1_NOR_TACO(0x35) | \
> + IFC_FTIM1_NOR_TRAD_NOR(0x1a) | \
> + IFC_FTIM1_NOR_TSEQRAD_NOR(0x13))
> +
> +#define NOR_FTIM2 (IFC_FTIM2_NOR_TCS(0x4) | \
> + IFC_FTIM2_NOR_TCH(0x4) | \
> + IFC_FTIM2_NOR_TWPH(0xe) | \
> + IFC_FTIM2_NOR_TWP(0x1c))
> +
> +#define NOR_FTIM3 0x04000000
> +
> +#define IFC_FLASH_BASE_PHYS 0x80000000
> +#define NOR_CSPR (IFC_CSPR_PHYS_ADDR(IFC_FLASH_BASE_PHYS) \
> + | IFC_CSPR_PORT_SIZE_16 \
> + | IFC_CSPR_MSEL_NOR \
> + | IFC_CSPR_V)
> +
> +#define NOR_CSPR_EXT 0x0
> +#define NOR_AMASK IFC_AMASK(128*1024*1024)
> +#define NOR_CSOR IFC_CSOR_NOR_ADM_SHIFT(12)
> +
> +// board-specific fpga timing
> +#define FPGA_BASE_PHYS 0x20000000
> +#define FPGA_CSPR_EXT 0x0
> +#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
> + IFC_CSPR_PORT_SIZE_8 | \
> + IFC_CSPR_MSEL_GPCM | \
> + IFC_CSPR_V)
> +
> +#define FPGA_AMASK IFC_AMASK(64 * 1024)
> +#define FPGA_CSOR IFC_CSOR_NOR_ADM_SHIFT(12)
> +
> +#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0xe) | \
> + IFC_FTIM0_GPCM_TEADC(0xe) | \
> + IFC_FTIM0_GPCM_TEAHC(0xe))
> +
> +#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \
> + IFC_FTIM1_GPCM_TRAD(0x3f))
> +
> +#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \
> + IFC_FTIM2_GPCM_TCH(0xf) | \
> + IFC_FTIM2_GPCM_TWP(0x3e))
> +
> +#define FPGA_FTIM3 0x0
> +
> +#endif //__IFC__BOARD_SPECIFIC_H__
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
> new file mode 100644
> index 0000000..936b789
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
> @@ -0,0 +1,69 @@
> +/** @file
> +
> + Copyright 2017-2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <IfcBoardSpecific.h>
> +
> +VOID
> +GetIfcNorFlashTimings (
> + IN IFC_TIMINGS * NorIfcTimings
> + )
> +{
> + NorIfcTimings->Ftim[0] = NOR_FTIM0;
> + NorIfcTimings->Ftim[1] = NOR_FTIM1;
> + NorIfcTimings->Ftim[2] = NOR_FTIM2;
> + NorIfcTimings->Ftim[3] = NOR_FTIM3;
> + NorIfcTimings->Cspr = NOR_CSPR;
> + NorIfcTimings->CsprExt = NOR_CSPR_EXT;
> + NorIfcTimings->Amask = NOR_AMASK;
> + NorIfcTimings->Csor = NOR_CSOR;
> + NorIfcTimings->CS = IFC_NOR_CS;
> +
> + return ;
> +}
> +
> +VOID
> +GetIfcFpgaTimings (
> + IN IFC_TIMINGS *FpgaIfcTimings
> + )
> +{
> + FpgaIfcTimings->Ftim[0] = FPGA_FTIM0;
> + FpgaIfcTimings->Ftim[1] = FPGA_FTIM1;
> + FpgaIfcTimings->Ftim[2] = FPGA_FTIM2;
> + FpgaIfcTimings->Ftim[3] = FPGA_FTIM3;
> + FpgaIfcTimings->Cspr = FPGA_CSPR;
> + FpgaIfcTimings->CsprExt = FPGA_CSPR_EXT;
> + FpgaIfcTimings->Amask = FPGA_AMASK;
> + FpgaIfcTimings->Csor = FPGA_CSOR;
> + FpgaIfcTimings->CS = IFC_FPGA_CS;
> +
> + return;
> +}
> +
> +VOID
> +GetIfcNandFlashTimings (
> + IN IFC_TIMINGS * NandIfcTimings
> + )
> +{
> + NandIfcTimings->Ftim[0] = NAND_FTIM0;
> + NandIfcTimings->Ftim[1] = NAND_FTIM1;
> + NandIfcTimings->Ftim[2] = NAND_FTIM2;
> + NandIfcTimings->Ftim[3] = NAND_FTIM3;
> + NandIfcTimings->Cspr = NAND_CSPR;
> + NandIfcTimings->CsprExt = NAND_CSPR_EXT;
> + NandIfcTimings->Amask = NAND_AMASK;
> + NandIfcTimings->Csor = NAND_CSOR;
> + NandIfcTimings->CS = IFC_NAND_CS;
> +
> + return;
> +}
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
> new file mode 100644
> index 0000000..5df84b1
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
> @@ -0,0 +1,28 @@
> +# @file
> +#
> +# Copyright 2017-2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = BoardLib
> + FILE_GUID = 13eacf2a-4338-48f4-88de-6ce4618e1a53
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = BoardLib
> +
> +[Sources.common]
> + BoardLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 29/39] Platform/NXP: LS2088 RDB Board FPGA library
2018-02-16 8:50 ` [PATCH edk2-platforms 29/39] Platform/NXP: LS2088 RDB Board FPGA library Meenakshi
@ 2018-04-19 16:30 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 16:30 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Wasim Khan
On Fri, Feb 16, 2018 at 02:20:25PM +0530, Meenakshi wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
>
> Library to provide functions for accessing FPGA
> on LS2088ARDB board.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> ---
> .../NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h | 166 +++++++++++++++++++++
> .../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c | 115 ++++++++++++++
> .../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 ++++
> 3 files changed, 312 insertions(+)
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h b/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
> new file mode 100644
> index 0000000..84d1f02
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
> @@ -0,0 +1,166 @@
> +/** FpgaLib.h
> +* Header defining the LS2088a Fpga specific constants (Base addresses, sizes, flags)
> +*
> +* Copyright 2017-2018 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __LS2088A_FPGA_H__
> +#define __LS2088A_FPGA_H__
> +
> +typedef enum {
> + CLK_66,
> + CLK_83,
> + CLK_100,
> + CLK_125,
> + CLK_133
> +} SYSTEM_CLOCK;
> +
> +/*
> + * FPGA register set of LS2088ARDB board-specific.
> + */
> +typedef struct {
> + UINT8 Id; // ID value uniquely identifying each QorIQ board type
> + UINT8 Arch; // Board Version
> + UINT8 Ver; // FPGA Version
> + UINT8 Model; // Programming Model
> + UINT8 Minor; // Minor Revision Number
> + UINT8 CtlSys;
> + UINT8 Aux;
> + UINT8 ClkSpd;
> + UINT8 StatDut;
> + UINT8 StatSys;
> + UINT8 StatAlrm;
> + UINT8 Present;
> + UINT8 Present2;
> + UINT8 RcwCtl;
> + UINT8 CtlLed;
> + UINT8 I2cBlk;
> + UINT8 RcfgCtl;
> + UINT8 RcfgSt;
> + UINT8 DcmAd;
> + UINT8 DcmDa;
> + UINT8 Dcmd;
> + UINT8 Dmsg;
> + UINT8 Gdc;
> + UINT8 Gdd;
> + UINT8 Dmack;
> + UINT8 Res1[6];
> + UINT8 Watch;
> + UINT8 PwrCtl[2];
> + UINT8 Res2[2];
> + UINT8 PwrStat[4];
> + UINT8 Res3[8];
> + UINT8 ClkSpd2[2];
> + UINT8 Res4[2];
> + UINT8 Sclk[3];
> + UINT8 Res5;
> + UINT8 Dclk[3];
> + UINT8 Res6;
> + UINT8 ClkDspd[3];
> + UINT8 Res7;
> + UINT8 RstCtl;
> + UINT8 RstStat;
> + UINT8 RstRsn;
> + UINT8 RstFrc[2];
> + UINT8 Res8[11];
> + UINT8 BrdCfg[16];
> + UINT8 DutCfg[16];
> + UINT8 RcwAd[2];
> + UINT8 RcwData;
> + UINT8 Res9[5];
> + UINT8 PostCtl;
> + UINT8 PostStat;
> + UINT8 PostDat[2];
> + UINT8 Pid[4];
> + UINT8 GpioIo[4];
> + UINT8 GpioDir[4];
> + UINT8 Res10[20];
> + UINT8 RjtagCtl;
> + UINT8 RjtagDat;
> + UINT8 Res11[2];
> + UINT8 TrigSrc[4];
> + UINT8 TrigDst[4];
> + UINT8 TrigStat;
> + UINT8 Res12[3];
> + UINT8 TrigCtr[4];
> + UINT8 Res13[16];
> + UINT8 ClkFreq[6];
> + UINT8 ResC6[8];
> + UINT8 ClkBase[2];
> + UINT8 ResD0[8];
> + UINT8 Cms[2];
> + UINT8 ResC0[6];
> + UINT8 Aux2[4];
> + UINT8 Res14[10];
> + UINT8 AuxAd;
> + UINT8 AuxDa;
> + UINT8 Res15[16];
> +} FPGA_REG_SET;
> +
> +/**
> + Function to read FPGA register.
> +**/
> +UINT8
> +FpgaRead (
> + UINTN Reg
> + );
> +
> +/**
> + Function to write FPGA register.
> +**/
> +VOID
> +FpgaWrite (
> + UINTN Reg,
> + UINT8 Value
> + );
> +
> +/**
> + Function to initialize FPGA timings.
> +**/
> +VOID
> +FpgaInit (
> + VOID
> + );
> +
> +/**
> + Function to get system clock frequency.
> +**/
> +UINTN
> +GetBoardSysClk (
> + VOID
> + );
> +
> +/**
> + Function to print board personality.
> +**/
> +VOID
> +PrintBoardPersonality (
> + VOID
> + );
> +
> +#define FPGA_BASE_PHYS 0x520000000
> +
> +//SYSCLK
> +#define FPGA_CLK_MASK 0x0F // FPGA Clock Mask
> +#define SYSCLK_66_MHZ 66000000
> +#define SYSCLK_83_MHZ 83000000
> +#define SYSCLK_100_MHZ 100000000
> +#define SYSCLK_125_MHZ 125000000
> +#define SYSCLK_133_MHZ 133000000
> +
> +#define FPGA_VBANK_MASK 0x07
> +#define FPGA_CS_MASK 0x08
> +
> +#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg))
> +#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), Value)
> +
> +#endif // __LS2088A_FPGA_H__
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
> new file mode 100644
> index 0000000..8948c21
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
> @@ -0,0 +1,115 @@
> +/** @FpgaLib.c
> + Fpga Library for LS2088A-RDB board, containing functions to
> + program and read the Fpga registers.
> +
> + FPGA is connected to IFC Controller and so MMIO APIs are used
> + to read/write FPGA registers
> +
> + Copyright 2017-2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/FpgaLib.h>
> +#include <Library/IoLib.h>
> +
> +/**
> + Function to read FPGA register.
> +
> + @param Reg Register offset of FPGA to read.
> +
> +**/
> +UINT8
> +FpgaRead (
> + IN UINTN Reg
> + )
> +{
> + VOID *Base;
> +
> + Base = (VOID *)FPGA_BASE_PHYS;
> +
> + return MmioRead8 ((UINTN)(Base + Reg));
> +}
> +
> +/**
> + Function to write FPGA register.
> +
> + @param Reg Register offset of FPGA to write.
> + @param Value Value to be written.
> +
> +**/
> +VOID
> +FpgaWrite (
> + IN UINTN Reg,
> + IN UINT8 Value
> + )
> +{
> + VOID *Base;
> +
> + Base = (VOID *)FPGA_BASE_PHYS;
> +
> + MmioWrite8 ((UINTN)(Base + Reg), Value);
> +}
> +
> +/**
> + Function to get board system clock frequency.
> +
> +**/
> +UINTN
> +GetBoardSysClk (
> + VOID
> + )
> +{
> + UINT8 SysclkConf;
> + SysclkConf = FPGA_READ (BrdCfg[1]);
> + switch (SysclkConf & FPGA_CLK_MASK) {
> + case CLK_66:
> + return SYSCLK_66_MHZ;
> + case CLK_83:
> + return SYSCLK_83_MHZ;
> + case CLK_100:
> + return SYSCLK_100_MHZ;
> + case CLK_125:
> + return SYSCLK_125_MHZ;
> + case CLK_133:
> + return SYSCLK_133_MHZ;
> + }
> + return SYSCLK_100_MHZ;
> +}
> +
> +/**
> + Function to print board personality.
> +
> +**/
> +VOID
> +PrintBoardPersonality (
> + VOID
> + )
> +{
> + UINT8 SwitchConf;
> + SwitchConf = FPGA_READ (Arch);
> +
> + DEBUG ((DEBUG_INFO, "Board Arch: V%d, ", SwitchConf >> 4));
> + DEBUG ((DEBUG_INFO, "Board version: %c, boot from ",
> + (SwitchConf & 0xf) + 'A'));
> +
> + SwitchConf = FPGA_READ (BrdCfg[0]);
> +
> + if (SwitchConf & FPGA_CS_MASK)
> + DEBUG ((DEBUG_INFO, "NAND\n"));
> + else
> + DEBUG ((DEBUG_INFO, "vBank: %d\n", (SwitchConf & FPGA_VBANK_MASK)));
> +
> + DEBUG ((DEBUG_INFO, "FPGA: v%d.%d\n", FPGA_READ (Ver),
> + FPGA_READ (Minor)));
> +}
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
> new file mode 100644
> index 0000000..e70723a
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
> @@ -0,0 +1,31 @@
> +# @FpgaLib.inf
> +#
> +# Copyright 2017-2018 NXP
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001000A
0x0001001a
With that change:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> + BASE_NAME = FpgaLib
> + FILE_GUID = dd2ce2f3-f219-4b57-82fd-f1ff8ae8bf5a
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = FpgaLib
> +
> +[Sources.common]
> + FpgaLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + IoLib
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 30/39] LS2088 : Enable support of FpgaLib
2018-02-16 8:50 ` [PATCH edk2-platforms 30/39] LS2088 : Enable support of FpgaLib Meenakshi
@ 2018-04-19 16:31 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 16:31 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Wasim Khan
On Fri, Feb 16, 2018 at 02:20:26PM +0530, Meenakshi wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 3 +++
> Silicon/NXP/Chassis/Chassis3/Soc.c | 18 +++++++++++++++++-
> Silicon/NXP/Chassis/Chassis3/Soc.h | 1 -
> Silicon/NXP/Chassis/LS2088aSocLib.inf | 2 ++
> Silicon/NXP/LS2088A/LS2088A.dsc | 1 +
> 5 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> index c0a802d..7894925 100755
> --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> @@ -39,6 +39,9 @@
> BeIoLib|Silicon/NXP/Library/BeIoLib/BeIoLib.inf
> SocLib|Silicon/NXP/Chassis/LS2088aSocLib.inf
> RealTimeClockLib|Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> + IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
> + BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
> + FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
>
> [PcdsFixedAtBuild.common]
>
> diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.c b/Silicon/NXP/Chassis/Chassis3/Soc.c
> index ed6c3cc..dbb1884 100644
> --- a/Silicon/NXP/Chassis/Chassis3/Soc.c
> +++ b/Silicon/NXP/Chassis/Chassis3/Soc.c
> @@ -18,6 +18,7 @@
> #include <Library/BaseLib.h>
> #include <Library/BaseMemoryLib/MemLibInternals.h>
> #include <Library/DebugLib.h>
> +#include <Library/IfcLib.h>
> #include <Library/IoLib.h>
> #include <Library/PcdLib.h>
> #include <Library/PrintLib.h>
> @@ -25,6 +26,9 @@
>
> #include "Soc.h"
>
> +extern VOID PrintBoardPersonality (VOID);
> +extern UINTN GetBoardSysClk (VOID);
> +
> VOID
> GetSysInfo (
> OUT SYS_INFO *PtrSysInfo
> @@ -83,7 +87,7 @@ GetSysInfo (
>
> GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
> - SysClk = CLK_FREQ;
> + SysClk = GetBoardSysClk ();
>
> PtrSysInfo->FreqSystemBus = SysClk;
> PtrSysInfo->FreqDdrBus = PcdGet64 (PcdDdrClk);
> @@ -152,6 +156,13 @@ SocInit (
> SmmuInit ();
>
> //
> + // Perform IFC Initialization.
> + // Early IFC initialization is required to set timings required for fpga initilzation to
> + // get system clock frequency, board info etc.
> + //
> + IfcInit ();
> +
> + //
> // Initialize the Serial Port.
> // Early serial port initialization is required to print RCW, Soc and CPU infomation at
> // the begining of UEFI boot.
> @@ -176,5 +187,10 @@ SocInit (
> // Print Soc Personality information
> //
> PrintSoc ();
> +
> + //
> + // Print Board Personality information
> + //
> + PrintBoardPersonality ();
> }
>
> diff --git a/Silicon/NXP/Chassis/Chassis3/Soc.h b/Silicon/NXP/Chassis/Chassis3/Soc.h
> index 0e892fb..c3ac1d5 100644
> --- a/Silicon/NXP/Chassis/Chassis3/Soc.h
> +++ b/Silicon/NXP/Chassis/Chassis3/Soc.h
> @@ -20,7 +20,6 @@
> #define FSL_CLK_GRPA_ADDR 0x01300000
> #define FSL_CLK_GRPB_ADDR 0x01310000
> #define NUM_CC_PLLS 6
> -#define CLK_FREQ 100000000
>
> #define FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } /* LS208x */
> #define TP_CLUSTER_EOC_MASK 0x80000000 /* Mask for End of clusters */
> diff --git a/Silicon/NXP/Chassis/LS2088aSocLib.inf b/Silicon/NXP/Chassis/LS2088aSocLib.inf
> index 8a4da50..3111d49 100644
> --- a/Silicon/NXP/Chassis/LS2088aSocLib.inf
> +++ b/Silicon/NXP/Chassis/LS2088aSocLib.inf
> @@ -31,6 +31,8 @@
> BaseLib
> BeIoLib
> DebugLib
> + FpgaLib
> + IfcLib
> SerialPortLib
>
> [Sources.common]
> diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc b/Silicon/NXP/LS2088A/LS2088A.dsc
> index 8f7dbb5..2cff40f 100644
> --- a/Silicon/NXP/LS2088A/LS2088A.dsc
> +++ b/Silicon/NXP/LS2088A/LS2088A.dsc
> @@ -67,5 +67,6 @@
> gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02000000
> gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000
>
> ##
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 31/39] LS2088ARDB: Enable NOR driver and Runtime Services
2018-02-16 8:50 ` [PATCH edk2-platforms 31/39] LS2088ARDB: Enable NOR driver and Runtime Services Meenakshi
@ 2018-04-19 16:32 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 16:32 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Wasim Khan
On Fri, Feb 16, 2018 at 02:20:27PM +0530, Meenakshi wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
>
> Enable NOR driver and Runtime Services for LS2088ARDB Platform
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Ah, I guess the varstore changes may actually happen to this patch.
No other comments on this.
/
Leif
> ---
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 15 ++++-
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 6 +-
> Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc | 99 ++++++++++++++++++++++++++++
> 3 files changed, 118 insertions(+), 2 deletions(-)
> create mode 100644 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> index 7894925..60449b5 100755
> --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> @@ -42,6 +42,7 @@
> IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
> BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
> FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
> + NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
>
> [PcdsFixedAtBuild.common]
>
> @@ -89,6 +90,13 @@
> gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0x09
> gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0x08
>
> + #
> + # NV Storage PCDs.
> + #
> + gArmTokenSpaceGuid.PcdVFPEnabled|1
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x580000000
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x580300000
> +
> ################################################################################
> #
> # Components Section - list of all EDK II Modules needed by this Platform
> @@ -98,6 +106,11 @@
> #
> # Architectural Protocols
> #
> - MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf{
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
> + }
> + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> + Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> index 14072a6..785f88b 100644
> --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> @@ -55,6 +55,7 @@ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> FV = FVMAIN_COMPACT
>
> !include ../FVRules.fdf.inc
> +!include VarStore.fdf.inc
> ################################################################################
> #
> # FV Section
> @@ -103,7 +104,8 @@ READ_LOCK_STATUS = TRUE
> INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> - INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
>
> INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> @@ -122,6 +124,8 @@ READ_LOCK_STATUS = TRUE
> INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
>
> + INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> +
> #
> # Network modules
> #
> diff --git a/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
> new file mode 100644
> index 0000000..7d35042
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
> @@ -0,0 +1,99 @@
> +## @file
> +# FDF include file with FD definition that defines an empty variable store.
> +#
> +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
> +# Copyright (C) 2014, Red Hat, Inc.
> +# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
> +# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
> +# Copyright 2017-2018 NXP.
> +#
> +# This program and the accompanying materials are licensed and made available
> +# under the terms and conditions of the BSD License which accompanies this
> +# distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> +# IMPLIED.
> +#
> +##
> +
> +[FD.LS2088aRdbNv_EFI]
> +
> +BaseAddress = 0x580300000|gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase #The base address of the FLASH device
> +Size = 0x000C0000|gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize #The size in bytes of the FLASH device
> +ErasePolarity = 1
> +BlockSize = 0x1
> +NumBlocks = 0xC0000
> +
> +#
> +# Place NV Storage just above Platform Data Base
> +#
> +DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
> +DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
> +DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
> +DEFINE FTW_WORKING_SIZE = 0x00040000
> +DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
> +DEFINE FTW_SPARE_SIZE = 0x00040000
> +
> +#############################################################################
> +# LS2088ARDB NVRAM Area
> +# LS2088ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
> +#############################################################################
> +
> +
> +$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +#NV_VARIABLE_STORE
> +DATA = {
> + ## This is the EFI_FIRMWARE_VOLUME_HEADER
> + # ZeroVector []
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + # FileSystemGuid: gEfiSystemNvDataFvGuid =
> + # { 0xFFF12B8D, 0x7696, 0x4C8B,
> + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
> + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
> + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
> + # FvLength: 0xC0000
> + 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
> + # Signature "_FVH" # Attributes
> + 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
> + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
> + 0x48, 0x00, 0xFA, 0xF5, 0x00, 0x00, 0x00, 0x02,
> + # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
> + 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
> + # Blockmap[1]: End
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + ## This is the VARIABLE_STORE_HEADER
> + # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
> + # Signature: gEfiAuthenticatedVariableGuid =
> + # { 0xaaf32c78, 0x947b, 0x439a,
> + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
> + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
> + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
> + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
> + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
> + # This can speed up the Variable Dispatch a bit.
> + 0xB8, 0xFF, 0x03, 0x00,
> + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
> + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +#NV_FTW_WORKING
> +DATA = {
> + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
> + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
> + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
> + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
> + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
> + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
> + # WriteQueueSize: UINT64
> + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +#NV_FTW_SPARE
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 32/39] Silicon/NXP: Implement PciSegmentLib to support multiple RCs
2018-02-16 8:50 ` [PATCH edk2-platforms 32/39] Silicon/NXP: Implement PciSegmentLib to support multiple RCs Meenakshi
@ 2018-04-19 19:27 ` Leif Lindholm
2018-04-20 6:40 ` Vabhav Sharma
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-19 19:27 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Vabhav
On Fri, Feb 16, 2018 at 02:20:28PM +0530, Meenakshi wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Multiple root complex support is not provided by standard library
> PciLib/PciExpressLib/PciSegmentLib, Reimplementing it and provide
> function for reading/writing into PCIe configuration Space.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/Pcie.h | 143 +++++
> Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 604 +++++++++++++++++++++
> .../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 41 ++
> 3 files changed, 788 insertions(+)
> create mode 100644 Silicon/NXP/Include/Pcie.h
> create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>
> diff --git a/Silicon/NXP/Include/Pcie.h b/Silicon/NXP/Include/Pcie.h
> new file mode 100644
> index 0000000..a7e6f9b
> --- /dev/null
> +++ b/Silicon/NXP/Include/Pcie.h
> @@ -0,0 +1,143 @@
> +/** @file
> + PCI memory configuration for NXP
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __PCI_H__
> +#define __PCI_H__
I'm not super happy about reusing such a generic name for the include
guard - or really even the filename. (MdePkg/Include/Pci.h has
_PCI_H_.)
Could you rename this header NxpPcie.h and change the include guard to
_NXP_PCIE_H_?
> +
> +// Segment 0
> +#define PCI_SEG0_NUM 0
> +
> +#define PCI_SEG0_BUSNUM_MIN 0x0
> +#define PCI_SEG0_BUSNUM_MAX 0xff
> +
> +#define PCI_SEG0_PORTIO_MIN 0x0
> +#define PCI_SEG0_PORTIO_MAX 0xffff
> +
> +#define PCI_SEG0_MMIO32_MIN 0x40000000
> +#define PCI_SEG0_MMIO32_MAX 0x4fffffff
> +#define PCI_SEG0_MMIO64_MIN PCI_SEG0_MMIO_MEMBASE + SEG_MEM_SIZE
> +#define PCI_SEG0_MMIO64_MAX PCI_SEG0_MMIO_MEMBASE + SEG_MEM_LIMIT
> +#define PCI_SEG0_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp1BaseAddr)
> +
> +#define PCI_SEG0_DBI_BASE 0x03400000
> +
> +// Segment 1
> +#define PCI_SEG1_NUM 1
> +
> +#define PCI_SEG1_BUSNUM_MIN 0x0
> +#define PCI_SEG1_BUSNUM_MAX 0xff
> +
> +#define PCI_SEG1_PORTIO_MIN 0x10000
> +#define PCI_SEG1_PORTIO_MAX 0x1ffff
> +
> +#define PCI_SEG1_MMIO32_MIN 0x50000000
> +#define PCI_SEG1_MMIO32_MAX 0x5fffffff
> +#define PCI_SEG1_MMIO64_MIN PCI_SEG1_MMIO_MEMBASE + SEG_MEM_SIZE
> +#define PCI_SEG1_MMIO64_MAX PCI_SEG1_MMIO_MEMBASE + SEG_MEM_LIMIT
> +#define PCI_SEG1_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp2BaseAddr)
> +
> +#define PCI_SEG1_DBI_BASE 0x03500000
> +
> +// Segment 2
> +#define PCI_SEG2_NUM 2
> +
> +#define PCI_SEG2_BUSNUM_MIN 0x0
> +#define PCI_SEG2_BUSNUM_MAX 0xff
> +
> +#define PCI_SEG2_PORTIO_MIN 0x20000
> +#define PCI_SEG2_PORTIO_MAX 0x2ffff
> +
> +#define PCI_SEG2_MMIO32_MIN 0x60000000
> +#define PCI_SEG2_MMIO32_MAX 0x6fffffff
> +#define PCI_SEG2_MMIO64_MIN PCI_SEG2_MMIO_MEMBASE + SEG_MEM_SIZE
> +#define PCI_SEG2_MMIO64_MAX PCI_SEG2_MMIO_MEMBASE + SEG_MEM_LIMIT
> +#define PCI_SEG2_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp3BaseAddr)
> +
> +#define PCI_SEG2_DBI_BASE 0x03600000
> +
> +// Segment 3
> +#define PCI_SEG3_NUM 3
> +
> +#define PCI_SEG3_BUSNUM_MIN 0x0
> +#define PCI_SEG3_BUSNUM_MAX 0xff
> +
> +#define PCI_SEG3_PORTIO_MIN 0x30000
> +#define PCI_SEG3_PORTIO_MAX 0x3ffff
> +
> +#define PCI_SEG3_MMIO32_MIN 0x70000000
> +#define PCI_SEG3_MMIO32_MAX 0x7fffffff
> +#define PCI_SEG3_MMIO64_MIN PCI_SEG3_MMIO_MEMBASE + SEG_MEM_SIZE
> +#define PCI_SEG3_MMIO64_MAX PCI_SEG3_MMIO_MEMBASE + SEG_MEM_LIMIT
> +#define PCI_SEG3_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp4BaseAddr)
> +
> +#define PCI_SEG3_DBI_BASE 0x03700000
> +
> +// Segment configuration
> +#define SEG_CFG_SIZE 0x00001000
> +#define SEG_CFG_BUS 0x00000000
> +#define SEG_MEM_SIZE 0x40000000
> +#define SEG_MEM_LIMIT 0x7fffffff
> +#define SEG_MEM_BUS 0x40000000
> +#define SEG_IO_SIZE 0x00010000
> +#define SEG_IO_BUS 0x00000000
> +#define PCI_BASE_DIFF 0x800000000
> +#define PCI_DBI_SIZE_DIFF 0x100000
> +#define PCI_SEG0_PHY_CFG0_BASE PCI_SEG0_MMIO_MEMBASE
> +#define PCI_SEG0_PHY_CFG1_BASE PCI_SEG0_PHY_CFG0_BASE + SEG_CFG_SIZE
> +#define PCI_SEG0_PHY_MEM_BASE PCI_SEG0_MMIO64_MIN
> +#define PCI_SEG0_PHY_IO_BASE PCI_SEG0_MMIO_MEMBASE + SEG_IO_SIZE
> +
> +// iATU configuration
> +#define IATU_VIEWPORT_OFF 0x900
> +#define IATU_VIEWPORT_OUTBOUND 0
> +
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
> +
> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31
> +
> +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
> +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
> +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914
> +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918
> +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C
> +
> +#define IATU_REGION_INDEX0 0x0
> +#define IATU_REGION_INDEX1 0x1
> +#define IATU_REGION_INDEX2 0x2
> +#define IATU_REGION_INDEX3 0x3
> +
> +// PCIe Controller configuration
> +#define NUM_PCIE_CONTROLLER FixedPcdGet32 (PcdNumPciController)
> +#define PCI_LUT_DBG FixedPcdGet32 (PcdPcieLutDbg)
> +#define PCI_LUT_BASE FixedPcdGet32 (PcdPcieLutBase)
> +#define LTSSM_STATE_MASK 0x3f
> +#define LTSSM_PCIE_L0 0x11
> +#define PCI_LINK_CAP 0x7c
> +#define PCI_LINK_SPEED_MASK 0xf
> +#define PCI_CLASS_BRIDGE_PCI 0x6040010
> +#define PCI_CLASS_DEVICE 0x8
> +#define PCI_DBI_RO_WR_EN 0x8bc
> +#define PCI_BASE_ADDRESS_0 0x10
> +
> +VOID GetSerdesProtocolMaps (UINT64 *);
> +
> +BOOLEAN IsSerDesLaneProtocolConfigured (UINT64, UINT16);
> +
> +#endif
> diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> new file mode 100644
> index 0000000..acb614d
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> @@ -0,0 +1,604 @@
> +/** @file
> + PCI Segment Library for NXP SoCs with multiple RCs
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials are
> + licensed and made available under the terms and conditions of
> + the BSD License which accompanies this distribution. The full
> + text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/PciSegmentLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Pcie.h>
> +
> +typedef enum {
> + PciCfgWidthUint8 = 0,
> + PciCfgWidthUint16,
> + PciCfgWidthUint32,
> + PciCfgWidthMax
> +} PCI_CFG_WIDTH;
> +
> +/**
> + Assert the validity of a PCI Segment address.
> + A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
> +
> + @param A The address to validate.
> + @param M Additional bits to assert to be zero.
> +
> +**/
> +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
> + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
> +
> +/**
> + Function to return PCIe Physical Address(PCIe view) or Controller
> + Address(CPU view) for different RCs
> +
> + @param Address Address passed from bus layer.
> + @param Segment Segment number for Root Complex.
> +
> + @return Return PCIe CPU or Controller address.
> +
> +**/
> +STATIC
> +UINT64
> +PciSegmentLibGetConfigBase (
> + IN UINT64 Address,
> + IN UINT16 Segment
> + )
> +{
> +
> + switch (Segment) {
> + // Root Complex 1
> + case PCI_SEG0_NUM:
> + // Reading bus number(bits 20-27)
> + if ((Address >> 20) & 1) {
> + return PCI_SEG0_MMIO_MEMBASE;
> + } else {
> + // On Bus 0 RCs are connected
> + return PCI_SEG0_DBI_BASE;
> + }
> + // Root Complex 2
> + case PCI_SEG1_NUM:
> + // Reading bus number(bits 20-27)
> + if ((Address >> 20) & 1) {
> + return PCI_SEG1_MMIO_MEMBASE;
> + } else {
> + // On Bus 0 RCs are connected
> + return PCI_SEG1_DBI_BASE;
> + }
> + // Root Complex 3
> + case PCI_SEG2_NUM:
> + // Reading bus number(bits 20-27)
> + if ((Address >> 20) & 1) {
> + return PCI_SEG2_MMIO_MEMBASE;
> + } else {
> + // On Bus 0 RCs are connected
> + return PCI_SEG2_DBI_BASE;
> + }
> + // Root Complex 4
> + case PCI_SEG3_NUM:
> + // Reading bus number(bits 20-27)
> + if ((Address >> 20) & 1) {
> + return PCI_SEG3_MMIO_MEMBASE;
> + } else {
> + // On Bus 0 RCs are connected
> + return PCI_SEG3_DBI_BASE;
> + }
> + default:
> + return 0;
> + }
> +
> +}
> +
> +/**
> + Internal worker function to read a PCI configuration register.
> +
> + @param Address The address that encodes the Segment, PCI Bus, Device,
> + Function and Register.
> + @param Width The width of data to read
> +
> + @return The value read from the PCI configuration register.
> +
> +**/
> +STATIC
> +UINT32
> +PciSegmentLibReadWorker (
> + IN UINT64 Address,
> + IN PCI_CFG_WIDTH Width
> + )
> +{
> + UINT64 Base;
> + UINT16 Offset;
> + UINT16 Segment;
> +
> + //
> + // Reading Segment number(47-32) bits in Address
> + //
> + Segment = (Address >> 32);
> + //
> + // Reading Function(12-0) bits in Address
> + //
> + Offset = (Address & 0xfff );
> +
> + Base = PciSegmentLibGetConfigBase (Address, Segment);
> +
> + //
> + // ignore devices > 0 on bus 0
> + //
> + if ((Address & 0xff00000) == 0 && (Address & 0xf8000) != 0) {
> + return MAX_UINT32;
> + }
> +
> + //
> + // ignore device > 0 on bus 1
> + //
> + if ((Address & 0xfe00000) == 0 && (Address & 0xf8000) != 0) {
> + return MAX_UINT32;
> + }
> +
> + switch (Width) {
> + case PciCfgWidthUint8:
> + return MmioRead8 (Base + (UINT8)Offset);
> + case PciCfgWidthUint16:
> + return MmioRead16 (Base + (UINT16)Offset);
> + case PciCfgWidthUint32:
> + return MmioRead32 (Base + (UINT32)Offset);
> + default:
> + ASSERT (FALSE);
> + }
> +
> + return CHAR_NULL;
> +}
> +
> +/**
> + Internal worker function to writes a PCI configuration register.
> +
> + @param Address The address that encodes the Segment, PCI Bus, Device,
> + Function and Register.
> + @param Width The width of data to write
> + @param Data The value to write.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +STATIC
> +UINT32
> +PciSegmentLibWriteWorker (
> + IN UINT64 Address,
> + IN PCI_CFG_WIDTH Width,
> + IN UINT32 Data
> + )
> +{
> + UINT64 Base;
> + UINT32 Offset;
> + UINT16 Segment;
> +
> + //
> + // Reading Segment number(47-32 bits) in Address
> + Segment = (Address >> 32);
> + //
> + // Reading Function(12-0 bits) in Address
> + //
> + Offset = (Address & 0xfff );
Spurious space after 0xfff.
Could we have some macros and #defines instead of live-coded values in
this function?
> +
> + Base = PciSegmentLibGetConfigBase (Address, Segment);
> +
> + //
> + // ignore devices > 0 on bus 0
> + //
> + if ((Address & 0xff00000) == 0 && (Address & 0xf8000) != 0) {
> + return Data;
> + }
> +
> + //
> + // ignore device > 0 on bus 1
> + //
> + if ((Address & 0xfe00000) == 0 && (Address & 0xf8000) != 0) {
> + return MAX_UINT32;
> + }
> +
> + switch (Width) {
> + case PciCfgWidthUint8:
> + MmioWrite8 (Base + (UINT8)Offset, Data);
> + break;
> + case PciCfgWidthUint16:
> + MmioWrite16 (Base + (UINT16)Offset, Data);
> + break;
> + case PciCfgWidthUint32:
> + MmioWrite32 (Base + (UINT16)Offset, Data);
> + break;
> + default:
> + ASSERT (FALSE);
> + }
> +
> + return Data;
> +}
> +
> +/**
> + Register a PCI device so PCI configuration registers may be accessed after
> + SetVirtualAddressMap().
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Bus, Device,
> + Function and Register.
> +
> + @retval RETURN_SUCCESS The PCI device was registered for runtime access.
> + @retval RETURN_UNSUPPORTED An attempt was made to call this function
> + after ExitBootServices().
> + @retval RETURN_UNSUPPORTED The resources required to access the PCI device
> + at runtime could not be mapped.
> + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
> + complete the registration.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +PciSegmentRegisterForRuntimeAccess (
> + IN UINTN Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> + return RETURN_UNSUPPORTED;
> +}
> +
> +/**
> + Reads an 8-bit PCI configuration register.
> +
> + Reads and returns the 8-bit PCI configuration register specified by Address.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function,
> + and Register.
> +
> + @return The 8-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentRead8 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +
> + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
> +}
> +
> +/**
> + Writes an 8-bit PCI configuration register.
> +
> + Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
> + Value is returned. This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param Value The value to write.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentWrite8 (
> + IN UINT64 Address,
> + IN UINT8 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +
> + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
> +}
> +
> +/**
> + Reads a 16-bit PCI configuration register.
> +
> + Reads and returns the 16-bit PCI configuration register specified by Address.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +
> + @return The 16-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentRead16 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> +
> + return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
> +}
> +
> +/**
> + Writes a 16-bit PCI configuration register.
> +
> + Writes the 16-bit PCI configuration register specified by Address with the
> + value specified by Value.
> +
> + Value is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param Value The value to write.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentWrite16 (
> + IN UINT64 Address,
> + IN UINT16 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> +
> + return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
> +}
> +
> +/**
> + Reads a 32-bit PCI configuration register.
> +
> + Reads and returns the 32-bit PCI configuration register specified by Address.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function,
> + and Register.
> +
> + @return The 32-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentRead32 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> +
> + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
> +}
> +
> +/**
> + Writes a 32-bit PCI configuration register.
> +
> + Writes the 32-bit PCI configuration register specified by Address with the
> + value specified by Value.
> +
> + Value is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param Value The value to write.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentWrite32 (
> + IN UINT64 Address,
> + IN UINT32 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> +
> + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
> +}
> +
> +/**
> + Reads a range of PCI configuration registers into a caller supplied buffer.
> +
> + Reads the range of PCI configuration registers specified by StartAddress and
> + Size into the buffer specified by Buffer. This function only allows the PCI
> + configuration registers from a single PCI function to be read. Size is
> + returned.
> +
> + If any reserved bits in StartAddress are set, then ASSERT().
> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> + If Size > 0 and Buffer is NULL, then ASSERT().
> +
> + @param StartAddress The starting address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> + @param Size The size in bytes of the transfer.
> + @param Buffer The pointer to a buffer receiving the data read.
> +
> + @return Size
> +
> +**/
> +UINTN
> +EFIAPI
> +PciSegmentReadBuffer (
> + IN UINT64 StartAddress,
> + IN UINTN Size,
> + OUT VOID *Buffer
> + )
> +{
> + UINTN ReturnValue;
> +
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
> + // 0xFFF is used as limit for 4KB config space
> + ASSERT (((StartAddress & 0xFFF) + Size) <= SIZE_4KB);
> +
> + if (Size == 0) {
> + return Size;
> + }
> +
> + ASSERT (Buffer != NULL);
> +
> + //
> + // Save Size for return
> + //
> + ReturnValue = Size;
> +
> + if ((StartAddress & BIT0) != 0) {
> + //
> + // Read a byte if StartAddress is byte aligned
> + //
> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
Why volatile on Buffer?
> + StartAddress += sizeof (UINT8);
> + Size -= sizeof (UINT8);
> + Buffer = (UINT8*)Buffer + BIT0;
sizeof (UINT8) instead of BIT0?
And this is a VOID *, so can just write.
Buffer += sizeof (UINT8);
> + }
> +
> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> + //
> + // Read a word if StartAddress is word aligned
> + //
> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + BIT0;
That is a very confusing use of pointer arithmetic.
Buffer += sizeof (UINT16);
> + }
> +
> + while (Size >= sizeof (UINT32)) {
> + //
> + // Read as many double words as possible
> + //
> + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
> + StartAddress += sizeof (UINT32);
> + Size -= sizeof (UINT32);
> + Buffer = (UINT32*)Buffer + BIT0;
Buffer += sizeof (UINT32);
> + }
> +
> + if (Size >= sizeof (UINT16)) {
> + //
> + // Read the last remaining word if exist
> + //
> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + BIT0;
Buffer += sizeof (UINT16);
> + }
> +
> + if (Size >= sizeof (UINT8)) {
> + //
> + // Read the last remaining byte if exist
> + //
> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
There is that scary volatile again.
> + }
> +
> + return ReturnValue;
> +}
> +
> +
> +/**
> + Copies the data in a caller supplied buffer to a specified range of PCI
> + configuration space.
> +
> + Writes the range of PCI configuration registers specified by StartAddress and
> + Size from the buffer specified by Buffer. This function only allows the PCI
> + configuration registers from a single PCI function to be written. Size is
> + returned.
> +
> + If any reserved bits in StartAddress are set, then ASSERT().
> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> + If Size > 0 and Buffer is NULL, then ASSERT().
> +
> + @param StartAddress The starting address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> + @param Size The size in bytes of the transfer.
> + @param Buffer The pointer to a buffer containing the data to write.
> +
> + @return The parameter of Size.
> +
> +**/
> +UINTN
> +EFIAPI
> +PciSegmentWriteBuffer (
> + IN UINT64 StartAddress,
> + IN UINTN Size,
> + IN VOID *Buffer
> + )
> +{
> + UINTN ReturnValue;
> +
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
> + // 0xFFF is used as limit for 4KB config space
> + ASSERT (((StartAddress & 0xFFF) + Size) <= SIZE_4KB);
Can you use (SIZE_4KB - 1) instead of 0xFFF?
> +
> + if (Size == 0) {
> + return Size;
> + }
> +
> + ASSERT (Buffer != NULL);
> +
> + //
> + // Save Size for return
> + //
> + ReturnValue = Size;
> +
> + if ((StartAddress & BIT0) != 0) {
> + //
> + // Write a byte if StartAddress is byte aligned
> + //
> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> + StartAddress += sizeof (UINT8);
> + Size -= sizeof (UINT8);
> + Buffer = (UINT8*)Buffer + BIT0;
Same comments for Buffer pointer update as previous function,
throughout.
/
Leif
> + }
> +
> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> + //
> + // Write a word if StartAddress is word aligned
> + //
> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + BIT0;
> + }
> +
> + while (Size >= sizeof (UINT32)) {
> + //
> + // Write as many double words as possible
> + //
> + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
> + StartAddress += sizeof (UINT32);
> + Size -= sizeof (UINT32);
> + Buffer = (UINT32*)Buffer + BIT0;
> + }
> +
> + if (Size >= sizeof (UINT16)) {
> + //
> + // Write the last remaining word if exist
> + //
> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer = (UINT16*)Buffer + BIT0;
> + }
> +
> + if (Size >= sizeof (UINT8)) {
> + //
> + // Write the last remaining byte if exist
> + //
> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> + }
> +
> + return ReturnValue;
> +}
> diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> new file mode 100644
> index 0000000..1ac83d4
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> @@ -0,0 +1,41 @@
> +## @file
> +# PCI Segment Library for NXP SoCs with multiple RCs
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php.
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PciSegmentLib
> + FILE_GUID = c9f59261-5a60-4a4c-82f6-1f520442e100
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciSegmentLib
> +
> +[Sources]
> + PciSegmentLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + IoLib
> + PcdLib
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for PCF2129 Real Time Clock Library
2018-04-19 13:47 ` Leif Lindholm
@ 2018-04-20 3:20 ` Meenakshi Aggarwal
0 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-04-20 3:20 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi, Vabhav Sharma
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Thursday, April 19, 2018 7:17 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
> <vabhav.sharma@nxp.com>
> Subject: Re: [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for
> PCF2129 Real Time Clock Library
>
> On Thu, Apr 19, 2018 at 12:33:50PM +0000, Meenakshi Aggarwal wrote:
> > > > +EFI_STATUS
> > > > +EFIAPI
> > > > +LibSetTime (
> > > > + IN EFI_TIME *Time
> > > > + )
> > > > +{
> > > > + UINT8 Buffer[8];
> > > > + UINT8 Index;
> > > > + EFI_STATUS Status;
> > > > + RTC_I2C_REQUEST Req;
> > > > + UINT8 RtcRegAddr;
> > > > +
> > > > + Index = 0;
> > > > + Status = EFI_SUCCESS;
> > > > + RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
> > > > +
> > > > + if (mI2cMaster == NULL) {
> > > > + return EFI_DEVICE_ERROR;
> > > > + }
> > > > +
> > > > + // start register address
> > > > + Buffer[Index++] = PCF2129_SEC_REG_ADDR;
> > > > +
> > > > + // hours, minutes and seconds
> > > > + Buffer[Index++] = DecimalToBcd8 (Time->Second);
> > > > + Buffer[Index++] = DecimalToBcd8 (Time->Minute);
> > > > + Buffer[Index++] = DecimalToBcd8 (Time->Hour);
> > > > + Buffer[Index++] = DecimalToBcd8 (Time->Day);
> > > > + Buffer[Index++] = EfiTimeToWday (Time) & 0x07;
> > >
> > > Why mask at the call site?
> > >
> > In GetTime function, data is been read from RTC device so we need to
> > mask the unnecessary bits
> > [as described in RTC registers] while
> > In SetTime, we are receiving the appropriate buffer so no need to
> > mask the data.
>
> But EfiTimeToWday returns an integer in the range 0-6:
> return (EpochDays + 4) % 7;
>
> Anding the result of that with 0x7 has no effect.
>
I will check this.
> /
> Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 32/39] Silicon/NXP: Implement PciSegmentLib to support multiple RCs
2018-04-19 19:27 ` Leif Lindholm
@ 2018-04-20 6:40 ` Vabhav Sharma
2018-04-20 12:41 ` Leif Lindholm
0 siblings, 1 reply; 254+ messages in thread
From: Vabhav Sharma @ 2018-04-20 6:40 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi
>-----Original Message-----
>From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
>Sent: Friday, April 20, 2018 12:57 AM
>To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
><udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
><vabhav.sharma@nxp.com>
>Subject: Re: [PATCH edk2-platforms 32/39] Silicon/NXP: Implement
>PciSegmentLib to support multiple RCs
>
>On Fri, Feb 16, 2018 at 02:20:28PM +0530, Meenakshi wrote:
>> From: Vabhav <vabhav.sharma@nxp.com>
>>
>> Multiple root complex support is not provided by standard library
>> PciLib/PciExpressLib/PciSegmentLib, Reimplementing it and provide
>> function for reading/writing into PCIe configuration Space.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
>> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>> ---
>> Silicon/NXP/Include/Pcie.h | 143 +++++
>> Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 604
>+++++++++++++++++++++
>> .../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 41 ++
>> 3 files changed, 788 insertions(+)
>> create mode 100644 Silicon/NXP/Include/Pcie.h create mode 100644
>> Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
>> create mode 100644
>> Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>>
>> diff --git a/Silicon/NXP/Include/Pcie.h b/Silicon/NXP/Include/Pcie.h
>> new file mode 100644 index 0000000..a7e6f9b
>> --- /dev/null
>> +++ b/Silicon/NXP/Include/Pcie.h
>> @@ -0,0 +1,143 @@
>> +/** @file
>> + PCI memory configuration for NXP
>> +
>> + Copyright 2018 NXP
>> +
>> + This program and the accompanying materials are licensed and made
>> + available under the terms and conditions of the BSD License which
>> + accompanies this distribution. The full text of the license may be
>> + found at
>https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fopensou
>rce.org%2Flicenses%2Fbsd-
>license.php&data=02%7C01%7Cvabhav.sharma%40nxp.com%7C081a2ebc43af4a
>daaf8e08d5a62b9921%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6
>36597628604269440&sdata=kt661HfkUD2E3sYswy0I4vVFTV3%2Fq%2FiM%2BiW
>egCISP%2BU%3D&reserved=0.
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#ifndef __PCI_H__
>> +#define __PCI_H__
>
>I'm not super happy about reusing such a generic name for the include guard - or
>really even the filename. (MdePkg/Include/Pci.h has
>_PCI_H_.)
>
>Could you rename this header NxpPcie.h and change the include guard to
>_NXP_PCIE_H_?
I see, Sure.
>
>> +
>> +// Segment 0
>> +#define PCI_SEG0_NUM 0
>> +
>> +#define PCI_SEG0_BUSNUM_MIN 0x0
>> +#define PCI_SEG0_BUSNUM_MAX 0xff
>> +
>> +#define PCI_SEG0_PORTIO_MIN 0x0
>> +#define PCI_SEG0_PORTIO_MAX 0xffff
>> +
>> +#define PCI_SEG0_MMIO32_MIN 0x40000000
>> +#define PCI_SEG0_MMIO32_MAX 0x4fffffff
>> +#define PCI_SEG0_MMIO64_MIN PCI_SEG0_MMIO_MEMBASE +
>SEG_MEM_SIZE
>> +#define PCI_SEG0_MMIO64_MAX PCI_SEG0_MMIO_MEMBASE +
>SEG_MEM_LIMIT
>> +#define PCI_SEG0_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp1BaseAddr)
>> +
>> +#define PCI_SEG0_DBI_BASE 0x03400000
>> +
>> +// Segment 1
>> +#define PCI_SEG1_NUM 1
>> +
>> +#define PCI_SEG1_BUSNUM_MIN 0x0
>> +#define PCI_SEG1_BUSNUM_MAX 0xff
>> +
>> +#define PCI_SEG1_PORTIO_MIN 0x10000
>> +#define PCI_SEG1_PORTIO_MAX 0x1ffff
>> +
>> +#define PCI_SEG1_MMIO32_MIN 0x50000000
>> +#define PCI_SEG1_MMIO32_MAX 0x5fffffff
>> +#define PCI_SEG1_MMIO64_MIN PCI_SEG1_MMIO_MEMBASE +
>SEG_MEM_SIZE
>> +#define PCI_SEG1_MMIO64_MAX PCI_SEG1_MMIO_MEMBASE +
>SEG_MEM_LIMIT
>> +#define PCI_SEG1_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp2BaseAddr)
>> +
>> +#define PCI_SEG1_DBI_BASE 0x03500000
>> +
>> +// Segment 2
>> +#define PCI_SEG2_NUM 2
>> +
>> +#define PCI_SEG2_BUSNUM_MIN 0x0
>> +#define PCI_SEG2_BUSNUM_MAX 0xff
>> +
>> +#define PCI_SEG2_PORTIO_MIN 0x20000
>> +#define PCI_SEG2_PORTIO_MAX 0x2ffff
>> +
>> +#define PCI_SEG2_MMIO32_MIN 0x60000000
>> +#define PCI_SEG2_MMIO32_MAX 0x6fffffff
>> +#define PCI_SEG2_MMIO64_MIN PCI_SEG2_MMIO_MEMBASE +
>SEG_MEM_SIZE
>> +#define PCI_SEG2_MMIO64_MAX PCI_SEG2_MMIO_MEMBASE +
>SEG_MEM_LIMIT
>> +#define PCI_SEG2_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp3BaseAddr)
>> +
>> +#define PCI_SEG2_DBI_BASE 0x03600000
>> +
>> +// Segment 3
>> +#define PCI_SEG3_NUM 3
>> +
>> +#define PCI_SEG3_BUSNUM_MIN 0x0
>> +#define PCI_SEG3_BUSNUM_MAX 0xff
>> +
>> +#define PCI_SEG3_PORTIO_MIN 0x30000
>> +#define PCI_SEG3_PORTIO_MAX 0x3ffff
>> +
>> +#define PCI_SEG3_MMIO32_MIN 0x70000000
>> +#define PCI_SEG3_MMIO32_MAX 0x7fffffff
>> +#define PCI_SEG3_MMIO64_MIN PCI_SEG3_MMIO_MEMBASE +
>SEG_MEM_SIZE
>> +#define PCI_SEG3_MMIO64_MAX PCI_SEG3_MMIO_MEMBASE +
>SEG_MEM_LIMIT
>> +#define PCI_SEG3_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp4BaseAddr)
>> +
>> +#define PCI_SEG3_DBI_BASE 0x03700000
>> +
>> +// Segment configuration
>> +#define SEG_CFG_SIZE 0x00001000
>> +#define SEG_CFG_BUS 0x00000000
>> +#define SEG_MEM_SIZE 0x40000000
>> +#define SEG_MEM_LIMIT 0x7fffffff
>> +#define SEG_MEM_BUS 0x40000000
>> +#define SEG_IO_SIZE 0x00010000
>> +#define SEG_IO_BUS 0x00000000
>> +#define PCI_BASE_DIFF 0x800000000
>> +#define PCI_DBI_SIZE_DIFF 0x100000
>> +#define PCI_SEG0_PHY_CFG0_BASE PCI_SEG0_MMIO_MEMBASE
>> +#define PCI_SEG0_PHY_CFG1_BASE PCI_SEG0_PHY_CFG0_BASE +
>SEG_CFG_SIZE
>> +#define PCI_SEG0_PHY_MEM_BASE PCI_SEG0_MMIO64_MIN
>> +#define PCI_SEG0_PHY_IO_BASE PCI_SEG0_MMIO_MEMBASE +
>SEG_IO_SIZE
>> +
>> +// iATU configuration
>> +#define IATU_VIEWPORT_OFF 0x900
>> +#define IATU_VIEWPORT_OUTBOUND 0
>> +
>> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904
>> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0
>> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
>> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 #define
>> +IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
>> +
>> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
>> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31
>> +
>> +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
>> +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
>> +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914
>> +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918
>> +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C
>> +
>> +#define IATU_REGION_INDEX0 0x0
>> +#define IATU_REGION_INDEX1 0x1
>> +#define IATU_REGION_INDEX2 0x2
>> +#define IATU_REGION_INDEX3 0x3
>> +
>> +// PCIe Controller configuration
>> +#define NUM_PCIE_CONTROLLER FixedPcdGet32 (PcdNumPciController)
>> +#define PCI_LUT_DBG FixedPcdGet32 (PcdPcieLutDbg)
>> +#define PCI_LUT_BASE FixedPcdGet32 (PcdPcieLutBase)
>> +#define LTSSM_STATE_MASK 0x3f
>> +#define LTSSM_PCIE_L0 0x11
>> +#define PCI_LINK_CAP 0x7c
>> +#define PCI_LINK_SPEED_MASK 0xf
>> +#define PCI_CLASS_BRIDGE_PCI 0x6040010
>> +#define PCI_CLASS_DEVICE 0x8
>> +#define PCI_DBI_RO_WR_EN 0x8bc
>> +#define PCI_BASE_ADDRESS_0 0x10
>> +
>> +VOID GetSerdesProtocolMaps (UINT64 *);
>> +
>> +BOOLEAN IsSerDesLaneProtocolConfigured (UINT64, UINT16);
>> +
>> +#endif
>> diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
>> b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
>> new file mode 100644
>> index 0000000..acb614d
>> --- /dev/null
>> +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
>> @@ -0,0 +1,604 @@
>> +/** @file
>> + PCI Segment Library for NXP SoCs with multiple RCs
>> +
>> + Copyright 2018 NXP
>> +
>> + This program and the accompanying materials are licensed and made
>> + available under the terms and conditions of the BSD License which
>> + accompanies this distribution. The full text of the license may be
>> + found at
>> +
>https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fopensou
>rce.org%2Flicenses%2Fbsd-
>license.php&data=02%7C01%7Cvabhav.sharma%40nxp.com%7C081a2ebc43af4a
>daaf8e08d5a62b9921%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6
>36597628604269440&sdata=kt661HfkUD2E3sYswy0I4vVFTV3%2Fq%2FiM%2BiW
>egCISP%2BU%3D&reserved=0.
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#include <Base.h>
>> +#include <Library/PciSegmentLib.h>
>> +#include <Library/BaseLib.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/PcdLib.h>
>> +#include <Pcie.h>
>> +
>> +typedef enum {
>> + PciCfgWidthUint8 = 0,
>> + PciCfgWidthUint16,
>> + PciCfgWidthUint32,
>> + PciCfgWidthMax
>> +} PCI_CFG_WIDTH;
>> +
>> +/**
>> + Assert the validity of a PCI Segment address.
>> + A valid PCI Segment address should not contain 1's in bits 28..31
>> +and 48..63
>> +
>> + @param A The address to validate.
>> + @param M Additional bits to assert to be zero.
>> +
>> +**/
>> +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
>> + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
>> +
>> +/**
>> + Function to return PCIe Physical Address(PCIe view) or Controller
>> + Address(CPU view) for different RCs
>> +
>> + @param Address Address passed from bus layer.
>> + @param Segment Segment number for Root Complex.
>> +
>> + @return Return PCIe CPU or Controller address.
>> +
>> +**/
>> +STATIC
>> +UINT64
>> +PciSegmentLibGetConfigBase (
>> + IN UINT64 Address,
>> + IN UINT16 Segment
>> + )
>> +{
>> +
>> + switch (Segment) {
>> + // Root Complex 1
>> + case PCI_SEG0_NUM:
>> + // Reading bus number(bits 20-27)
>> + if ((Address >> 20) & 1) {
>> + return PCI_SEG0_MMIO_MEMBASE;
>> + } else {
>> + // On Bus 0 RCs are connected
>> + return PCI_SEG0_DBI_BASE;
>> + }
>> + // Root Complex 2
>> + case PCI_SEG1_NUM:
>> + // Reading bus number(bits 20-27)
>> + if ((Address >> 20) & 1) {
>> + return PCI_SEG1_MMIO_MEMBASE;
>> + } else {
>> + // On Bus 0 RCs are connected
>> + return PCI_SEG1_DBI_BASE;
>> + }
>> + // Root Complex 3
>> + case PCI_SEG2_NUM:
>> + // Reading bus number(bits 20-27)
>> + if ((Address >> 20) & 1) {
>> + return PCI_SEG2_MMIO_MEMBASE;
>> + } else {
>> + // On Bus 0 RCs are connected
>> + return PCI_SEG2_DBI_BASE;
>> + }
>> + // Root Complex 4
>> + case PCI_SEG3_NUM:
>> + // Reading bus number(bits 20-27)
>> + if ((Address >> 20) & 1) {
>> + return PCI_SEG3_MMIO_MEMBASE;
>> + } else {
>> + // On Bus 0 RCs are connected
>> + return PCI_SEG3_DBI_BASE;
>> + }
>> + default:
>> + return 0;
>> + }
>> +
>> +}
>> +
>> +/**
>> + Internal worker function to read a PCI configuration register.
>> +
>> + @param Address The address that encodes the Segment, PCI Bus, Device,
>> + Function and Register.
>> + @param Width The width of data to read
>> +
>> + @return The value read from the PCI configuration register.
>> +
>> +**/
>> +STATIC
>> +UINT32
>> +PciSegmentLibReadWorker (
>> + IN UINT64 Address,
>> + IN PCI_CFG_WIDTH Width
>> + )
>> +{
>> + UINT64 Base;
>> + UINT16 Offset;
>> + UINT16 Segment;
>> +
>> + //
>> + // Reading Segment number(47-32) bits in Address // Segment =
>> + (Address >> 32); // // Reading Function(12-0) bits in Address //
>> + Offset = (Address & 0xfff );
>> +
>> + Base = PciSegmentLibGetConfigBase (Address, Segment);
>> +
>> + //
>> + // ignore devices > 0 on bus 0
>> + //
>> + if ((Address & 0xff00000) == 0 && (Address & 0xf8000) != 0) {
>> + return MAX_UINT32;
>> + }
>> +
>> + //
>> + // ignore device > 0 on bus 1
>> + //
>> + if ((Address & 0xfe00000) == 0 && (Address & 0xf8000) != 0) {
>> + return MAX_UINT32;
>> + }
>> +
>> + switch (Width) {
>> + case PciCfgWidthUint8:
>> + return MmioRead8 (Base + (UINT8)Offset); case PciCfgWidthUint16:
>> + return MmioRead16 (Base + (UINT16)Offset); case
>> + PciCfgWidthUint32:
>> + return MmioRead32 (Base + (UINT32)Offset);
>> + default:
>> + ASSERT (FALSE);
>> + }
>> +
>> + return CHAR_NULL;
>> +}
>> +
>> +/**
>> + Internal worker function to writes a PCI configuration register.
>> +
>> + @param Address The address that encodes the Segment, PCI Bus, Device,
>> + Function and Register.
>> + @param Width The width of data to write
>> + @param Data The value to write.
>> +
>> + @return The value written to the PCI configuration register.
>> +
>> +**/
>> +STATIC
>> +UINT32
>> +PciSegmentLibWriteWorker (
>> + IN UINT64 Address,
>> + IN PCI_CFG_WIDTH Width,
>> + IN UINT32 Data
>> + )
>> +{
>> + UINT64 Base;
>> + UINT32 Offset;
>> + UINT16 Segment;
>> +
>> + //
>> + // Reading Segment number(47-32 bits) in Address Segment =
>> + (Address >> 32); // // Reading Function(12-0 bits) in Address //
>> + Offset = (Address & 0xfff );
>
>Spurious space after 0xfff.
Alright, Thanks.
Same applies to PciSegmentLibReadWorker()
>
>Could we have some macros and #defines instead of live-coded values in this
>function?
Sure, I assume Similar changes in PciSegmentLibReadWorker() required.
>
>> +
>> + Base = PciSegmentLibGetConfigBase (Address, Segment);
>> +
>> + //
>> + // ignore devices > 0 on bus 0
>> + //
>> + if ((Address & 0xff00000) == 0 && (Address & 0xf8000) != 0) {
>> + return Data;
>> + }
>> +
>> + //
>> + // ignore device > 0 on bus 1
>> + //
>> + if ((Address & 0xfe00000) == 0 && (Address & 0xf8000) != 0) {
>> + return MAX_UINT32;
>> + }
>> +
>> + switch (Width) {
>> + case PciCfgWidthUint8:
>> + MmioWrite8 (Base + (UINT8)Offset, Data);
>> + break;
>> + case PciCfgWidthUint16:
>> + MmioWrite16 (Base + (UINT16)Offset, Data);
>> + break;
>> + case PciCfgWidthUint32:
>> + MmioWrite32 (Base + (UINT16)Offset, Data);
>> + break;
>> + default:
>> + ASSERT (FALSE);
>> + }
>> +
>> + return Data;
>> +}
>> +
>> +/**
>> + Register a PCI device so PCI configuration registers may be
>> +accessed after
>> + SetVirtualAddressMap().
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> +
>> + @param Address The address that encodes the PCI Bus, Device,
>> + Function and Register.
>> +
>> + @retval RETURN_SUCCESS The PCI device was registered for runtime
>access.
>> + @retval RETURN_UNSUPPORTED An attempt was made to call this
>function
>> + after ExitBootServices().
>> + @retval RETURN_UNSUPPORTED The resources required to access the
>PCI device
>> + at runtime could not be mapped.
>> + @retval RETURN_OUT_OF_RESOURCES There are not enough resources
>available to
>> + complete the registration.
>> +
>> +**/
>> +RETURN_STATUS
>> +EFIAPI
>> +PciSegmentRegisterForRuntimeAccess (
>> + IN UINTN Address
>> + )
>> +{
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
>> + return RETURN_UNSUPPORTED;
>> +}
>> +
>> +/**
>> + Reads an 8-bit PCI configuration register.
>> +
>> + Reads and returns the 8-bit PCI configuration register specified by Address.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> +
>> + @param Address The address that encodes the PCI Segment, Bus, Device,
>Function,
>> + and Register.
>> +
>> + @return The 8-bit PCI configuration register specified by Address.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +PciSegmentRead8 (
>> + IN UINT64 Address
>> + )
>> +{
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
>> +
>> + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
>> +}
>> +
>> +/**
>> + Writes an 8-bit PCI configuration register.
>> +
>> + Writes the 8-bit PCI configuration register specified by Address with the value
>specified by Value.
>> + Value is returned. This function must guarantee that all PCI read and write
>operations are serialized.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> +
>> + @param Address The address that encodes the PCI Segment, Bus, Device,
>Function, and Register.
>> + @param Value The value to write.
>> +
>> + @return The value written to the PCI configuration register.
>> +
>> +**/
>> +UINT8
>> +EFIAPI
>> +PciSegmentWrite8 (
>> + IN UINT64 Address,
>> + IN UINT8 Value
>> + )
>> +{
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
>> +
>> + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8,
>> +Value); }
>> +
>> +/**
>> + Reads a 16-bit PCI configuration register.
>> +
>> + Reads and returns the 16-bit PCI configuration register specified by Address.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> +
>> + @param Address The address that encodes the PCI Segment, Bus, Device,
>Function, and Register.
>> +
>> + @return The 16-bit PCI configuration register specified by Address.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +PciSegmentRead16 (
>> + IN UINT64 Address
>> + )
>> +{
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
>> +
>> + return (UINT16) PciSegmentLibReadWorker (Address,
>> +PciCfgWidthUint16); }
>> +
>> +/**
>> + Writes a 16-bit PCI configuration register.
>> +
>> + Writes the 16-bit PCI configuration register specified by Address
>> + with the value specified by Value.
>> +
>> + Value is returned.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> +
>> + @param Address The address that encodes the PCI Segment, Bus, Device,
>Function, and Register.
>> + @param Value The value to write.
>> +
>> + @return The parameter of Value.
>> +
>> +**/
>> +UINT16
>> +EFIAPI
>> +PciSegmentWrite16 (
>> + IN UINT64 Address,
>> + IN UINT16 Value
>> + )
>> +{
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
>> +
>> + return (UINT16) PciSegmentLibWriteWorker (Address,
>> +PciCfgWidthUint16, Value); }
>> +
>> +/**
>> + Reads a 32-bit PCI configuration register.
>> +
>> + Reads and returns the 32-bit PCI configuration register specified by Address.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 32-bit boundary, then ASSERT().
>> +
>> + @param Address The address that encodes the PCI Segment, Bus, Device,
>Function,
>> + and Register.
>> +
>> + @return The 32-bit PCI configuration register specified by Address.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +PciSegmentRead32 (
>> + IN UINT64 Address
>> + )
>> +{
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
>> +
>> + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32); }
>> +
>> +/**
>> + Writes a 32-bit PCI configuration register.
>> +
>> + Writes the 32-bit PCI configuration register specified by Address
>> + with the value specified by Value.
>> +
>> + Value is returned.
>> +
>> + If any reserved bits in Address are set, then ASSERT().
>> + If Address is not aligned on a 32-bit boundary, then ASSERT().
>> +
>> + @param Address The address that encodes the PCI Segment, Bus, Device,
>> + Function, and Register.
>> + @param Value The value to write.
>> +
>> + @return The parameter of Value.
>> +
>> +**/
>> +UINT32
>> +EFIAPI
>> +PciSegmentWrite32 (
>> + IN UINT64 Address,
>> + IN UINT32 Value
>> + )
>> +{
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
>> +
>> + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32,
>> +Value); }
>> +
>> +/**
>> + Reads a range of PCI configuration registers into a caller supplied buffer.
>> +
>> + Reads the range of PCI configuration registers specified by
>> + StartAddress and Size into the buffer specified by Buffer. This
>> + function only allows the PCI configuration registers from a single
>> + PCI function to be read. Size is returned.
>> +
>> + If any reserved bits in StartAddress are set, then ASSERT().
>> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
>> + If Size > 0 and Buffer is NULL, then ASSERT().
>> +
>> + @param StartAddress The starting address that encodes the PCI Segment,
>Bus,
>> + Device, Function and Register.
>> + @param Size The size in bytes of the transfer.
>> + @param Buffer The pointer to a buffer receiving the data read.
>> +
>> + @return Size
>> +
>> +**/
>> +UINTN
>> +EFIAPI
>> +PciSegmentReadBuffer (
>> + IN UINT64 StartAddress,
>> + IN UINTN Size,
>> + OUT VOID *Buffer
>> + )
>> +{
>> + UINTN ReturnValue;
>> +
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); // 0xFFF is
>> + used as limit for 4KB config space ASSERT (((StartAddress & 0xFFF)
>> + + Size) <= SIZE_4KB);
>> +
>> + if (Size == 0) {
>> + return Size;
>> + }
>> +
>> + ASSERT (Buffer != NULL);
>> +
>> + //
>> + // Save Size for return
>> + //
>> + ReturnValue = Size;
>> +
>> + if ((StartAddress & BIT0) != 0) {
>> + //
>> + // Read a byte if StartAddress is byte aligned
>> + //
>> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
>
>Why volatile on Buffer?
I took reference from Socionext, Not required .
PCIe region has device attribute.
>
>> + StartAddress += sizeof (UINT8);
>> + Size -= sizeof (UINT8);
>> + Buffer = (UINT8*)Buffer + BIT0;
>
>sizeof (UINT8) instead of BIT0?
>
>And this is a VOID *, so can just write.
> Buffer += sizeof (UINT8);
>
Yes,Sure.
>> + }
>> +
>> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
>> + //
>> + // Read a word if StartAddress is word aligned
>> + //
>> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
>> + StartAddress += sizeof (UINT16);
>> + Size -= sizeof (UINT16);
>> + Buffer = (UINT16*)Buffer + BIT0;
>
>That is a very confusing use of pointer arithmetic.
> Buffer += sizeof (UINT16);
>
Agree, alright.
>> + }
>> +
>> + while (Size >= sizeof (UINT32)) {
>> + //
>> + // Read as many double words as possible
>> + //
>> + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
>> + StartAddress += sizeof (UINT32);
>> + Size -= sizeof (UINT32);
>> + Buffer = (UINT32*)Buffer + BIT0;
>
> Buffer += sizeof (UINT32);
Ok
>
>> + }
>> +
>> + if (Size >= sizeof (UINT16)) {
>> + //
>> + // Read the last remaining word if exist
>> + //
>> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
>> + StartAddress += sizeof (UINT16);
>> + Size -= sizeof (UINT16);
>> + Buffer = (UINT16*)Buffer + BIT0;
>
> Buffer += sizeof (UINT16);
Ok
>
>> + }
>> +
>> + if (Size >= sizeof (UINT8)) {
>> + //
>> + // Read the last remaining byte if exist
>> + //
>> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
>
>There is that scary volatile again.
Not required.
>
>> + }
>> +
>> + return ReturnValue;
>> +}
>> +
>> +
>> +/**
>> + Copies the data in a caller supplied buffer to a specified range of
>> +PCI
>> + configuration space.
>> +
>> + Writes the range of PCI configuration registers specified by
>> + StartAddress and Size from the buffer specified by Buffer. This
>> + function only allows the PCI configuration registers from a single
>> + PCI function to be written. Size is returned.
>> +
>> + If any reserved bits in StartAddress are set, then ASSERT().
>> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
>> + If Size > 0 and Buffer is NULL, then ASSERT().
>> +
>> + @param StartAddress The starting address that encodes the PCI Segment,
>Bus,
>> + Device, Function and Register.
>> + @param Size The size in bytes of the transfer.
>> + @param Buffer The pointer to a buffer containing the data to write.
>> +
>> + @return The parameter of Size.
>> +
>> +**/
>> +UINTN
>> +EFIAPI
>> +PciSegmentWriteBuffer (
>> + IN UINT64 StartAddress,
>> + IN UINTN Size,
>> + IN VOID *Buffer
>> + )
>> +{
>> + UINTN ReturnValue;
>> +
>> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); // 0xFFF is
>> + used as limit for 4KB config space ASSERT (((StartAddress & 0xFFF)
>> + + Size) <= SIZE_4KB);
>
>Can you use (SIZE_4KB - 1) instead of 0xFFF?
Yes,Sure.
>
>> +
>> + if (Size == 0) {
>> + return Size;
>> + }
>> +
>> + ASSERT (Buffer != NULL);
>> +
>> + //
>> + // Save Size for return
>> + //
>> + ReturnValue = Size;
>> +
>> + if ((StartAddress & BIT0) != 0) {
>> + //
>> + // Write a byte if StartAddress is byte aligned
>> + //
>> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
>> + StartAddress += sizeof (UINT8);
>> + Size -= sizeof (UINT8);
>> + Buffer = (UINT8*)Buffer + BIT0;
>
>Same comments for Buffer pointer update as previous function, throughout.
Ok
>
>/
> Leif
>
>> + }
>> +
>> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
>> + //
>> + // Write a word if StartAddress is word aligned
>> + //
>> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
>> + StartAddress += sizeof (UINT16);
>> + Size -= sizeof (UINT16);
>> + Buffer = (UINT16*)Buffer + BIT0;
>> + }
>> +
>> + while (Size >= sizeof (UINT32)) {
>> + //
>> + // Write as many double words as possible
>> + //
>> + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
>> + StartAddress += sizeof (UINT32);
>> + Size -= sizeof (UINT32);
>> + Buffer = (UINT32*)Buffer + BIT0;
>> + }
>> +
>> + if (Size >= sizeof (UINT16)) {
>> + //
>> + // Write the last remaining word if exist
>> + //
>> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
>> + StartAddress += sizeof (UINT16);
>> + Size -= sizeof (UINT16);
>> + Buffer = (UINT16*)Buffer + BIT0;
>> + }
>> +
>> + if (Size >= sizeof (UINT8)) {
>> + //
>> + // Write the last remaining byte if exist
>> + //
>> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); }
>> +
>> + return ReturnValue;
>> +}
>> diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>> b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>> new file mode 100644
>> index 0000000..1ac83d4
>> --- /dev/null
>> +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>> @@ -0,0 +1,41 @@
>> +## @file
>> +# PCI Segment Library for NXP SoCs with multiple RCs # # Copyright
>> +2018 NXP # # This program and the accompanying materials # are
>> +licensed and made available under the terms and conditions of the BSD
>> +License # which accompanies this distribution. The full text of the
>> +license may be found at #
>https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fopensou
>rce.org%2Flicenses%2Fbsd-
>license.php&data=02%7C01%7Cvabhav.sharma%40nxp.com%7C081a2ebc43af4a
>daaf8e08d5a62b9921%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6
>36597628604269440&sdata=kt661HfkUD2E3sYswy0I4vVFTV3%2Fq%2FiM%2BiW
>egCISP%2BU%3D&reserved=0.
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
>EITHER EXPRESS OR IMPLIED.
>> +#
>> +#
>> +##
>> +
>> +[Defines]
>> + INF_VERSION = 0x0001001A
>> + BASE_NAME = PciSegmentLib
>> + FILE_GUID = c9f59261-5a60-4a4c-82f6-1f520442e100
>> + MODULE_TYPE = BASE
>> + VERSION_STRING = 1.0
>> + LIBRARY_CLASS = PciSegmentLib
>> +
>> +[Sources]
>> + PciSegmentLib.c
>> +
>> +[Packages]
>> + MdePkg/MdePkg.dec
>> + Silicon/NXP/NxpQoriqLs.dec
>> +
>> +[LibraryClasses]
>> + BaseLib
>> + DebugLib
>> + IoLib
>> + PcdLib
>> +
>> +[Pcd]
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
>> --
>> 1.9.1
>>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 33/39] Silicon/NXP: Implement PciHostBridgeLib support
2018-02-16 8:50 ` [PATCH edk2-platforms 33/39] Silicon/NXP: Implement PciHostBridgeLib support Meenakshi
@ 2018-04-20 8:34 ` Ard Biesheuvel
2018-04-24 12:17 ` Vabhav Sharma
2018-04-20 14:54 ` Leif Lindholm
1 sibling, 1 reply; 254+ messages in thread
From: Ard Biesheuvel @ 2018-04-20 8:34 UTC (permalink / raw)
To: Meenakshi
Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org,
Udit Kumar, Varun Sethi, Vabhav
On 16 February 2018 at 09:50, Meenakshi <meenakshi.aggarwal@nxp.com> wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Implement the library that exposes the PCIe root complexes to the
> generic PCI host bridge driver,Putting SoC Specific low level init
> code for the RCs.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 618 +++++++++++++++++++++
> .../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 50 ++
> 2 files changed, 668 insertions(+)
> create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>
> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> new file mode 100644
> index 0000000..e6f9b7c
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> @@ -0,0 +1,618 @@
> +/** @file
> + PCI Host Bridge Library instance for NXP SoCs
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <IndustryStandard/Pci22.h>
> +#include <Library/BeIoLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PciHostBridgeLib.h>
> +#include <Pcie.h>
> +#include <Protocol/PciHostBridgeResourceAllocation.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +
> +#pragma pack(1)
> +typedef struct {
> + ACPI_HID_DEVICE_PATH AcpiDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
> +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
> +#pragma pack ()
> +
> +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG0_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG1_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG2_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG3_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + }
> +};
> +
> +STATIC
> +GLOBAL_REMOVE_IF_UNREFERENCED
> +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
> + L"Mem", L"I/O", L"Bus"
> +};
> +
> +#define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | \
> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE
> +
> +#define PCI_SUPPORT_ATTRIBUTES EFI_PCI_ATTRIBUTE_ISA_IO_16 | \
> + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
> + EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
> + EFI_PCI_ATTRIBUTE_VGA_IO_16 | \
> + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
> +
> +PCI_ROOT_BRIDGE mPciRootBridges[] = {
> + {
> + PCI_SEG0_NUM, // Segment
> + PCI_SUPPORT_ATTRIBUTES, // Supports
> + PCI_SUPPORT_ATTRIBUTES, // Attributes
> + FALSE, // DmaAbove4G
Why is this disabled? The root bridge driver will have to do bounce
buffering when performing DMA on memory > 4 GB.
> + FALSE, // NoExtendedConfigSpace
> + FALSE, // ResourceAssigned
> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
> + { PCI_SEG0_BUSNUM_MIN,
> + PCI_SEG0_BUSNUM_MAX }, // Bus
> + { PCI_SEG0_PORTIO_MIN,
> + PCI_SEG0_PORTIO_MAX }, // Io
> + { PCI_SEG0_MMIO32_MIN,
> + PCI_SEG0_MMIO32_MAX }, // Mem
> + { PCI_SEG0_MMIO64_MIN,
> + PCI_SEG0_MMIO64_MAX }, // MemAbove4G
> + { MAX_UINT64, 0x0 }, // PMem
> + { MAX_UINT64, 0x0 }, // PMemAbove4G
> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG0_NUM]
> + }, {
> + PCI_SEG1_NUM, // Segment
> + PCI_SUPPORT_ATTRIBUTES, // Supports
> + PCI_SUPPORT_ATTRIBUTES, // Attributes
> + FALSE, // DmaAbove4G
> + FALSE, // NoExtendedConfigSpace
> + FALSE, // ResourceAssigned
> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
> + { PCI_SEG1_BUSNUM_MIN,
> + PCI_SEG1_BUSNUM_MAX }, // Bus
> + { PCI_SEG1_PORTIO_MIN,
> + PCI_SEG1_PORTIO_MAX }, // Io
> + { PCI_SEG1_MMIO32_MIN,
> + PCI_SEG1_MMIO32_MAX }, // Mem
> + { PCI_SEG1_MMIO64_MIN,
> + PCI_SEG1_MMIO64_MAX }, // MemAbove4G
> + { MAX_UINT64, 0x0 }, // PMem
> + { MAX_UINT64, 0x0 }, // PMemAbove4G
> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG1_NUM]
> + }, {
> + PCI_SEG2_NUM, // Segment
> + PCI_SUPPORT_ATTRIBUTES, // Supports
> + PCI_SUPPORT_ATTRIBUTES, // Attributes
> + FALSE, // DmaAbove4G
> + FALSE, // NoExtendedConfigSpace
> + FALSE, // ResourceAssigned
> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
> + { PCI_SEG2_BUSNUM_MIN,
> + PCI_SEG2_BUSNUM_MAX }, // Bus
> + { PCI_SEG2_PORTIO_MIN,
> + PCI_SEG2_PORTIO_MAX }, // Io
> + { PCI_SEG2_MMIO32_MIN,
> + PCI_SEG2_MMIO32_MAX }, // Mem
> + { PCI_SEG2_MMIO64_MIN,
> + PCI_SEG2_MMIO64_MAX }, // MemAbove4G
> + { MAX_UINT64, 0x0 }, // PMem
> + { MAX_UINT64, 0x0 }, // PMemAbove4G
> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG2_NUM]
> + }, {
> + PCI_SEG3_NUM, // Segment
> + PCI_SUPPORT_ATTRIBUTES, // Supports
> + PCI_SUPPORT_ATTRIBUTES, // Attributes
> + FALSE, // DmaAbove4G
> + FALSE, // NoExtendedConfigSpace
> + FALSE, // ResourceAssigned
> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
> + { PCI_SEG3_BUSNUM_MIN,
> + PCI_SEG3_BUSNUM_MAX }, // Bus
> + { PCI_SEG3_PORTIO_MIN,
> + PCI_SEG3_PORTIO_MAX }, // Io
> + { PCI_SEG3_MMIO32_MIN,
> + PCI_SEG3_MMIO32_MAX }, // Mem
> + { PCI_SEG3_MMIO64_MIN,
> + PCI_SEG3_MMIO64_MAX }, // MemAbove4G
> + { MAX_UINT64, 0x0 }, // PMem
> + { MAX_UINT64, 0x0 }, // PMemAbove4G
> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG3_NUM]
> + }
> +};
> +
> +/**
> + Function to set-up iATU outbound window for PCIe controller
> +
> + @param Dbi Address of PCIe host controller.
> + @param Idx Index of iATU outbound window.
> + @param Type Type(Cfg0/Cfg1/Mem/IO) of iATU outbound window.
> + @param Phys PCIe controller phy address for outbound window.
> + @param BusAdr PCIe controller bus address for outbound window.
> + @param Pcie Size of PCIe controller space(Cfg0/Cfg1/Mem/IO).
> +
> +**/
> +STATIC
> +VOID
> +PcieIatuOutboundSet (
> + IN EFI_PHYSICAL_ADDRESS Dbi,
> + IN UINT32 Idx,
> + IN UINT32 Type,
> + IN UINT64 Phys,
> + IN UINT64 BusAddr,
> + IN UINT64 Size
> + )
> +{
> + MmioWrite32 (Dbi + IATU_VIEWPORT_OFF,
> + (UINT32)(IATU_VIEWPORT_OUTBOUND | Idx));
> + MmioWrite32 (Dbi + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
> + (UINT32)Phys);
> + MmioWrite32 (Dbi + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(Phys >> 32));
> + MmioWrite32 (Dbi + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(Phys + Size - BIT0));
> + MmioWrite32 (Dbi + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
> + (UINT32)BusAddr);
> + MmioWrite32 (Dbi + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(BusAddr >> 32));
> + MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
> + (UINT32)Type);
> + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
> + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN);
> +}
> +
> +/**
> + Function to check PCIe controller LTSSM state
> +
> + @param Pcie Address of PCIe host controller.
> +
> +**/
> +STATIC
> +INTN
> +PcieLinkState (
> + IN EFI_PHYSICAL_ADDRESS Pcie
> + )
> +{
> + UINT32 State;
> +
> + //
> + // Reading PCIe controller LTSSM state
> + //
> + if (FeaturePcdGet (PcdPciLutBigEndian)) {
> + State = BeMmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
> + LTSSM_STATE_MASK;
> + } else {
> + State = MmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
> + LTSSM_STATE_MASK;
> + }
> +
> + if (State < LTSSM_PCIE_L0) {
> + DEBUG ((DEBUG_INFO," Pcie Link error. LTSSM=0x%2x\n", State));
> + return EFI_SUCCESS;
> + }
> +
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + Helper function to check PCIe link state
> +
> + @param Pcie Address of PCIe host controller.
> +
> +**/
> +STATIC
> +INTN
> +PcieLinkUp (
> + IN EFI_PHYSICAL_ADDRESS Pcie
> + )
> +{
> + INTN State;
> + UINT32 Cap;
> +
> + State = PcieLinkState (Pcie);
> + if (State) {
> + return State;
> + }
> +
> + //
> + // Try to download speed to gen1
> + //
> + Cap = MmioRead32 ((UINTN)Pcie + PCI_LINK_CAP);
> + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, (UINT32)(Cap & (~PCI_LINK_SPEED_MASK)) | BIT0);
> + State = PcieLinkState (Pcie);
> + if (State) {
> + return State;
> + }
> +
> + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, Cap);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function checks whether PCIe is enabled or not
> + depending upon SoC serdes protocol map
> +
> + @param PcieNum PCIe number.
> +
> + @return The PCIe number enabled in map.
> + @return FALSE PCIe number is disabled in map.
> +
> +**/
> +STATIC
> +BOOLEAN
> +IsPcieNumEnabled(
> + IN UINTN PcieNum
> + )
> +{
> + UINT64 SerDes1ProtocolMap;
> +
> + SerDes1ProtocolMap = 0x0;
> +
> + //
> + // Reading serdes map
> + //
> + GetSerdesProtocolMaps (&SerDes1ProtocolMap);
> +
> + //
> + // Verify serdes line is configured in the map
> + //
> + if (PcieNum < NUM_PCIE_CONTROLLER) {
> + return IsSerDesLaneProtocolConfigured (SerDes1ProtocolMap, (PcieNum + BIT0));
> + } else {
> + DEBUG ((DEBUG_ERROR, "Device not supported\n"));
> + }
> +
> + return FALSE;
> +}
> +
> +/**
> + Function to set-up iATU outbound window for PCIe controller
> +
> + @param Pcie Address of PCIe host controller
> + @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
> + @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
> + @param MemBase PCIe controller phy address Memory Space.
> + @param IoBase PCIe controller phy address IO Space.
> +**/
> +STATIC
> +VOID
> +PcieSetupAtu (
> + IN EFI_PHYSICAL_ADDRESS Pcie,
> + IN EFI_PHYSICAL_ADDRESS Cfg0Base,
> + IN EFI_PHYSICAL_ADDRESS Cfg1Base,
> + IN EFI_PHYSICAL_ADDRESS MemBase,
> + IN EFI_PHYSICAL_ADDRESS IoBase
> + )
> +{
> +
> + //
> + // iATU : OUTBOUND WINDOW 0 : CFG0
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX0,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
> + Cfg0Base,
> + SEG_CFG_BUS,
> + SEG_CFG_SIZE);
> +
> + //
> + // iATU : OUTBOUND WINDOW 1 : CFG1
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX1,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
> + Cfg1Base,
> + SEG_CFG_BUS,
> + SEG_CFG_SIZE);
> + //
> + // iATU 2 : OUTBOUND WINDOW 2 : MEM
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX2,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
> + MemBase,
> + SEG_MEM_BUS,
> + SEG_MEM_SIZE);
> +
> + //
> + // iATU 3 : OUTBOUND WINDOW 3: IO
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX3,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
> + IoBase,
> + SEG_IO_BUS,
> + SEG_IO_SIZE);
> +
What happened to the 64-bit MMIO window?
> +}
> +
> +/**
> + Helper function to set-up PCIe controller
> +
> + @param Pcie Address of PCIe host controller
> + @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
> + @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
> + @param MemBase PCIe controller phy address Memory Space.
> + @param IoBase PCIe controller phy address IO Space.
> +
> +**/
> +STATIC
> +VOID
> +PcieSetupCntrl (
> + IN EFI_PHYSICAL_ADDRESS Pcie,
> + IN EFI_PHYSICAL_ADDRESS Cfg0Base,
> + IN EFI_PHYSICAL_ADDRESS Cfg1Base,
> + IN EFI_PHYSICAL_ADDRESS MemBase,
> + IN EFI_PHYSICAL_ADDRESS IoBase
> + )
> +{
> + //
> + // iATU outbound set-up
> + //
> + PcieSetupAtu (Pcie, Cfg0Base, Cfg1Base, MemBase, IoBase);
> +
> + //
> + // program correct class for RC
> + //
> + MmioWrite32 ((UINTN)Pcie + PCI_BASE_ADDRESS_0, (BIT0 - BIT0));
> + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)BIT0);
> + MmioWrite32 ((UINTN)Pcie + PCI_CLASS_DEVICE, (UINT32)PCI_CLASS_BRIDGE_PCI);
> + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)(BIT0 - BIT0));
> +}
> +
> +/**
> + Return all the root bridge instances in an array.
> +
> + @param Count Return the count of root bridge instances.
> +
> + @return All the root bridge instances in an array.
> +
> +**/
> +PCI_ROOT_BRIDGE *
> +EFIAPI
> +PciHostBridgeGetRootBridges (
> + OUT UINTN *Count
> + )
> +{
> + UINTN Idx;
> + INTN LinkUp;
> + UINT64 PciPhyMemAddr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyCfg0Addr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyCfg1Addr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyIoAddr[NUM_PCIE_CONTROLLER];
> + UINT64 Regs[NUM_PCIE_CONTROLLER];
> +
> + *Count = 0;
> +
> + //
> + // Filling local array for
> + // PCIe controller Physical address space for Cfg0,Cfg1,Mem,IO
> + // Host Contoller address
> + //
> + for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
> + PciPhyMemAddr[Idx] = PCI_SEG0_PHY_MEM_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyCfg0Addr[Idx] = PCI_SEG0_PHY_CFG0_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyCfg1Addr[Idx] = PCI_SEG0_PHY_CFG1_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyIoAddr [Idx] = PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx);
> + Regs[Idx] = PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx);
> + }
> +
> + for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
> + //
> + // Verify PCIe controller is enabled in Soc Serdes Map
> + //
> + if (!IsPcieNumEnabled (Idx)) {
> + DEBUG ((DEBUG_ERROR, "PCIE%d is disabled\n", (Idx + BIT0)));
> + //
> + // Continue with other PCIe controller
> + //
> + continue;
> + }
> + DEBUG ((DEBUG_INFO, "PCIE%d is Enabled\n", Idx + BIT0));
> +
> + //
> + // Verify PCIe controller LTSSM state
> + //
> + LinkUp = PcieLinkUp(Regs[Idx]);
> + if (!LinkUp) {
> + //
> + // Let the user know there's no PCIe link
> + //
> + DEBUG ((DEBUG_INFO,"no link, regs @ 0x%lx\n", Regs[Idx]));
> + //
> + // Continue with other PCIe controller
> + //
> + continue;
> + }
> + DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + BIT0));
> +
> + //
> + // Function to set up address translation unit outbound window for
> + // PCIe Controller
> + //
> + PcieSetupCntrl (Regs[Idx],
> + PciPhyCfg0Addr[Idx],
> + PciPhyCfg1Addr[Idx],
> + PciPhyMemAddr[Idx],
> + PciPhyIoAddr[Idx]);
> + *Count += BIT0;
> + break;
> + }
> +
> + if (*Count == 0) {
> + return NULL;
> + } else {
> + return &mPciRootBridges[Idx];
> + }
> +}
> +
> +/**
> + Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
> +
> + @param Bridges The root bridge instances array.
> + @param Count The count of the array.
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeFreeRootBridges (
> + PCI_ROOT_BRIDGE *Bridges,
> + UINTN Count
> + )
> +{
> +}
> +
> +/**
> + Inform the platform that the resource conflict happens.
> +
> + @param HostBridgeHandle Handle of the Host Bridge.
> + @param Configuration Pointer to PCI I/O and PCI memory resource
> + descriptors. The Configuration contains the resources
> + for all the root bridges. The resource for each root
> + bridge is terminated with END descriptor and an
> + additional END is appended indicating the end of the
> + entire resources. The resource descriptor field
> + values follow the description in
> + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
> + .SubmitResources().
> +
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeResourceConflict (
> + EFI_HANDLE HostBridgeHandle,
> + VOID *Configuration
> + )
> +{
> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
> + UINTN RootBridgeIndex;
> + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
> +
> + RootBridgeIndex = 0;
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
> + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
> + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
> + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
> + ASSERT (Descriptor->ResType <
> + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));
> + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
> + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
> + Descriptor->AddrLen, Descriptor->AddrRangeMax
> + ));
> + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
> + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
> + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
> + ((Descriptor->SpecificFlag &
> + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
> + ) != 0) ? L" (Prefetchable)" : L""
> + ));
> + }
> + }
> + //
> + // Skip the END descriptor for root bridge
> + //
> + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
> + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
> + );
> + }
> +
> + return;
> +}
> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> new file mode 100644
> index 0000000..f08ac60
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> @@ -0,0 +1,50 @@
> +## @file
> +# PCI Host Bridge Library instance for NXP ARM SOC
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials are licensed and made available
> +# under the terms and conditions of the BSD License which accompanies this
> +# distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> +# IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PciHostBridgeLib
> + FILE_GUID = f4c99bcc-5c95-49ad-b0f3-fc5b611dc9c1
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciHostBridgeLib
> +
> +[Sources]
> + PciHostBridgeLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> +
> +[LibraryClasses]
> + DebugLib
> + DevicePathLib
> + MemoryAllocationLib
> + PcdLib
> + SocLib
> + UefiBootServicesTableLib
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 34/39] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
2018-02-16 8:50 ` [PATCH edk2-platforms 34/39] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL Meenakshi
@ 2018-04-20 8:40 ` Ard Biesheuvel
2018-04-24 12:26 ` Vabhav Sharma
2018-04-20 15:15 ` Leif Lindholm
1 sibling, 1 reply; 254+ messages in thread
From: Ard Biesheuvel @ 2018-04-20 8:40 UTC (permalink / raw)
To: Meenakshi
Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org,
Udit Kumar, Varun Sethi, Vabhav
On 16 February 2018 at 09:50, Meenakshi <meenakshi.aggarwal@nxp.com> wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> NXP SOC has mutiple PCIe RCs,Adding respective implementation of
> EFI_CPU_IO2_PROTOCOL to provide Memory Space Read/Write functions
> used by generic Host Bridge Driver including correct value for
> the translation offset during MMIO accesses
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
This driver looks completely wrong to me: MMIO access is memory
mapped, and given that you don't implement PCI to CPU translation of
MMIO accesses, the memory read and write functions should not perform
any translation at all, and just relay the accesses. On the other
hand, the I/O accessors are not implemented at all, and these are the
ones that require translation, given that the I/O port addresses in
the CPU space need translation to MMIO addressess.
Also, you don't seem to be using the PcdPciExp?BaseAddr PCDs anywhere,
so you can drop them from the .dsc
> ---
> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 529 ++++++++++++++++++++++
> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 ++
> 2 files changed, 577 insertions(+)
> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>
> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> new file mode 100644
> index 0000000..b5fb72c
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> @@ -0,0 +1,529 @@
> +/** @file
> + Produces the CPU I/O 2 Protocol.
> +
> + Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Pcie.h>
> +#include <Protocol/CpuIo2.h>
> +
> +#define MAX_IO_PORT_ADDRESS PCI_SEG2_PORTIO_MAX
> +
> +//
> +// Handle for the CPU I/O 2 Protocol
> +//
> +STATIC EFI_HANDLE mHandle;
> +
> +//
> +// Lookup table for increment values based on transfer widths
> +//
> +STATIC CONST UINT8 mInStride[] = {
> + 1, // EfiCpuIoWidthUint8
> + 2, // EfiCpuIoWidthUint16
> + 4, // EfiCpuIoWidthUint32
> + 8, // EfiCpuIoWidthUint64
> + 0, // EfiCpuIoWidthFifoUint8
> + 0, // EfiCpuIoWidthFifoUint16
> + 0, // EfiCpuIoWidthFifoUint32
> + 0, // EfiCpuIoWidthFifoUint64
> + 1, // EfiCpuIoWidthFillUint8
> + 2, // EfiCpuIoWidthFillUint16
> + 4, // EfiCpuIoWidthFillUint32
> + 8 // EfiCpuIoWidthFillUint64
> +};
> +
> +//
> +// Lookup table for increment values based on transfer widths
> +//
> +STATIC CONST UINT8 mOutStride[] = {
> + 1, // EfiCpuIoWidthUint8
> + 2, // EfiCpuIoWidthUint16
> + 4, // EfiCpuIoWidthUint32
> + 8, // EfiCpuIoWidthUint64
> + 1, // EfiCpuIoWidthFifoUint8
> + 2, // EfiCpuIoWidthFifoUint16
> + 4, // EfiCpuIoWidthFifoUint32
> + 8, // EfiCpuIoWidthFifoUint64
> + 0, // EfiCpuIoWidthFillUint8
> + 0, // EfiCpuIoWidthFillUint16
> + 0, // EfiCpuIoWidthFillUint32
> + 0 // EfiCpuIoWidthFillUint64
> +};
> +
> +/**
> + Check parameters to a CPU I/O 2 Protocol service request.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[in] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The parameters for this request pass the checks.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +CpuIoCheckParameter (
> + IN BOOLEAN MmioOperation,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + UINT64 MaxCount;
> + UINT64 Limit;
> +
> + //
> + // Check to see if Buffer is NULL
> + //
> + if (Buffer == NULL) {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Check to see if Width is in the valid range
> + //
> + if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // For FIFO type, the target address won't increase during the access,
> + // so treat Count as 1
> + //
> + if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
> + Count = 1;
> + }
> +
> + //
> + // Check to see if Width is in the valid range for I/O Port operations
> + //
> + Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
> + if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Check to see if Address is aligned
> + //
> + if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Check to see if any address associated with this transfer exceeds the maximum
> + // allowed address. The maximum address implied by the parameters passed in is
> + // Address + Size * Count. If the following condition is met, then the transfer
> + // is not supported.
> + //
> + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
> + //
> + // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
> + // can also be the maximum integer value supported by the CPU, this range
> + // check must be adjusted to avoid all oveflow conditions.
> + //
> + Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
> + if (Count == 0) {
> + if (Address > Limit) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> + } else {
> + MaxCount = RShiftU64 (Limit, Width);
> + if (MaxCount < (Count - 1)) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> + }
> +
> + //
> + // Check to see if Buffer is aligned
> + //
> + if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Reads memory-mapped registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[out] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuMemoryServiceRead (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 InStride;
> + UINT8 OutStride;
> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
> + UINT8 *Uint8Buffer;
> +
> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if ((Address >= PCI_SEG0_MMIO32_MIN) &&
> + (Address <= PCI_SEG0_MMIO32_MAX)) {
> + Address += PCI_SEG0_MMIO_MEMBASE;
> + } else if ((Address >= PCI_SEG1_MMIO32_MIN) &&
> + (Address <= PCI_SEG1_MMIO32_MAX)) {
> + Address += PCI_SEG1_MMIO_MEMBASE;
> + } else if ((Address >= PCI_SEG2_MMIO32_MIN) &&
> + (Address <= PCI_SEG2_MMIO32_MAX)) {
> + Address += PCI_SEG2_MMIO_MEMBASE;
> + } else if ((Address >= PCI_SEG3_MMIO32_MIN) &&
> + (Address <= PCI_SEG3_MMIO32_MAX)) {
> + Address += PCI_SEG3_MMIO_MEMBASE;
> + } else {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Select loop based on the width of the transfer
> + //
> + InStride = mInStride[Width];
> + OutStride = mOutStride[Width];
> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
> + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
> + if (OperationWidth == EfiCpuIoWidthUint8) {
> + *Uint8Buffer = MmioRead8 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
> + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
> + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
> + *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Writes memory-mapped registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[in] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuMemoryServiceWrite (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 InStride;
> + UINT8 OutStride;
> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
> + UINT8 *Uint8Buffer;
> +
> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if ((Address >= PCI_SEG0_MMIO32_MIN) &&
> + (Address <= PCI_SEG0_MMIO32_MAX)) {
> + Address += PCI_SEG0_MMIO_MEMBASE;
> + } else if ((Address >= PCI_SEG1_MMIO32_MIN) &&
> + (Address <= PCI_SEG1_MMIO32_MAX)) {
> + Address += PCI_SEG1_MMIO_MEMBASE;
> + } else if ((Address >= PCI_SEG2_MMIO32_MIN) &&
> + (Address <= PCI_SEG2_MMIO32_MAX)) {
> + Address += PCI_SEG2_MMIO_MEMBASE;
> + } else if ((Address >= PCI_SEG3_MMIO32_MIN) &&
> + (Address <= PCI_SEG3_MMIO32_MAX)) {
> + Address += PCI_SEG3_MMIO_MEMBASE;
> + } else {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Select loop based on the width of the transfer
> + //
> + InStride = mInStride[Width];
> + OutStride = mOutStride[Width];
> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
> + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
> + if (OperationWidth == EfiCpuIoWidthUint8) {
> + MmioWrite8 ((UINTN)Address, *Uint8Buffer);
> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
> + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
> + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
> + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Reads I/O registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[out] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuIoServiceRead (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Write I/O registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[in] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuIoServiceWrite (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +//
> +// CPU I/O 2 Protocol instance
> +//
> +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
> + {
> + CpuMemoryServiceRead,
> + CpuMemoryServiceWrite
> + },
> + {
> + CpuIoServiceRead,
> + CpuIoServiceWrite
> + }
> +};
> +
> +
> +/**
> + The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
> +
> + @param[in] ImageHandle The firmware allocated handle for the EFI image.
> + @param[in] SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The entry point is executed successfully.
> + @retval other Some error occurs when executing this entry point.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PciCpuIo2Initialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> +
> + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &mHandle,
> + &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
> + NULL
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> new file mode 100644
> index 0000000..25a1db1
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> @@ -0,0 +1,48 @@
> +## @file
> +# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PciCpuIo2Dxe
> + FILE_GUID = 7bff18d7-9aae-434b-9c06-f10a7e157eac
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PciCpuIo2Initialize
> +
> +[Sources]
> + PciCpuIo2Dxe.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + IoLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> +
> +[Protocols]
> + gEfiCpuIo2ProtocolGuid ## PRODUCES
> +
> +[Depex]
> + TRUE
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 32/39] Silicon/NXP: Implement PciSegmentLib to support multiple RCs
2018-04-20 6:40 ` Vabhav Sharma
@ 2018-04-20 12:41 ` Leif Lindholm
2018-04-24 12:30 ` Vabhav Sharma
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-20 12:41 UTC (permalink / raw)
To: Vabhav Sharma
Cc: Meenakshi Aggarwal, ard.biesheuvel@linaro.org,
edk2-devel@lists.01.org, Udit Kumar, Varun Sethi
On Fri, Apr 20, 2018 at 06:40:27AM +0000, Vabhav Sharma wrote:
>
>
> >-----Original Message-----
> >From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> >Sent: Friday, April 20, 2018 12:57 AM
> >To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> >Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> ><udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
> ><vabhav.sharma@nxp.com>
> >Subject: Re: [PATCH edk2-platforms 32/39] Silicon/NXP: Implement
> >PciSegmentLib to support multiple RCs
> >
> >On Fri, Feb 16, 2018 at 02:20:28PM +0530, Meenakshi wrote:
> >> From: Vabhav <vabhav.sharma@nxp.com>
> >>
> >> Multiple root complex support is not provided by standard library
> >> PciLib/PciExpressLib/PciSegmentLib, Reimplementing it and provide
> >> function for reading/writing into PCIe configuration Space.
> >>
> >> Contributed-under: TianoCore Contribution Agreement 1.1
> >> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> >> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> >> ---
> >> Silicon/NXP/Include/Pcie.h | 143 +++++
> >> Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 604
> >+++++++++++++++++++++
> >> .../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 41 ++
> >> 3 files changed, 788 insertions(+)
> >> create mode 100644 Silicon/NXP/Include/Pcie.h create mode 100644
> >> Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> >> create mode 100644
> >> Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> >>
> >> diff --git a/Silicon/NXP/Include/Pcie.h b/Silicon/NXP/Include/Pcie.h
> >> new file mode 100644 index 0000000..a7e6f9b
> >> --- /dev/null
> >> +++ b/Silicon/NXP/Include/Pcie.h
> >> @@ -0,0 +1,143 @@
> >> +/** @file
> >> + PCI memory configuration for NXP
> >> +
> >> + Copyright 2018 NXP
> >> +
> >> + This program and the accompanying materials are licensed and made
> >> + available under the terms and conditions of the BSD License which
> >> + accompanies this distribution. The full text of the license may be
> >> + found at
> >https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fopensou
> >rce.org%2Flicenses%2Fbsd-
> >license.php&data=02%7C01%7Cvabhav.sharma%40nxp.com%7C081a2ebc43af4a
> >daaf8e08d5a62b9921%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6
> >36597628604269440&sdata=kt661HfkUD2E3sYswy0I4vVFTV3%2Fq%2FiM%2BiW
> >egCISP%2BU%3D&reserved=0.
> >> +
> >> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> >> + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> >EXPRESS OR IMPLIED.
> >> +
> >> +**/
> >> +
> >> +#ifndef __PCI_H__
> >> +#define __PCI_H__
> >
> >I'm not super happy about reusing such a generic name for the include guard - or
> >really even the filename. (MdePkg/Include/Pci.h has
> >_PCI_H_.)
> >
> >Could you rename this header NxpPcie.h and change the include guard to
> >_NXP_PCIE_H_?
> I see, Sure.
> >
> >> +
> >> +// Segment 0
> >> +#define PCI_SEG0_NUM 0
> >> +
> >> +#define PCI_SEG0_BUSNUM_MIN 0x0
> >> +#define PCI_SEG0_BUSNUM_MAX 0xff
> >> +
> >> +#define PCI_SEG0_PORTIO_MIN 0x0
> >> +#define PCI_SEG0_PORTIO_MAX 0xffff
> >> +
> >> +#define PCI_SEG0_MMIO32_MIN 0x40000000
> >> +#define PCI_SEG0_MMIO32_MAX 0x4fffffff
> >> +#define PCI_SEG0_MMIO64_MIN PCI_SEG0_MMIO_MEMBASE +
> >SEG_MEM_SIZE
> >> +#define PCI_SEG0_MMIO64_MAX PCI_SEG0_MMIO_MEMBASE +
> >SEG_MEM_LIMIT
> >> +#define PCI_SEG0_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp1BaseAddr)
> >> +
> >> +#define PCI_SEG0_DBI_BASE 0x03400000
> >> +
> >> +// Segment 1
> >> +#define PCI_SEG1_NUM 1
> >> +
> >> +#define PCI_SEG1_BUSNUM_MIN 0x0
> >> +#define PCI_SEG1_BUSNUM_MAX 0xff
> >> +
> >> +#define PCI_SEG1_PORTIO_MIN 0x10000
> >> +#define PCI_SEG1_PORTIO_MAX 0x1ffff
> >> +
> >> +#define PCI_SEG1_MMIO32_MIN 0x50000000
> >> +#define PCI_SEG1_MMIO32_MAX 0x5fffffff
> >> +#define PCI_SEG1_MMIO64_MIN PCI_SEG1_MMIO_MEMBASE +
> >SEG_MEM_SIZE
> >> +#define PCI_SEG1_MMIO64_MAX PCI_SEG1_MMIO_MEMBASE +
> >SEG_MEM_LIMIT
> >> +#define PCI_SEG1_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp2BaseAddr)
> >> +
> >> +#define PCI_SEG1_DBI_BASE 0x03500000
> >> +
> >> +// Segment 2
> >> +#define PCI_SEG2_NUM 2
> >> +
> >> +#define PCI_SEG2_BUSNUM_MIN 0x0
> >> +#define PCI_SEG2_BUSNUM_MAX 0xff
> >> +
> >> +#define PCI_SEG2_PORTIO_MIN 0x20000
> >> +#define PCI_SEG2_PORTIO_MAX 0x2ffff
> >> +
> >> +#define PCI_SEG2_MMIO32_MIN 0x60000000
> >> +#define PCI_SEG2_MMIO32_MAX 0x6fffffff
> >> +#define PCI_SEG2_MMIO64_MIN PCI_SEG2_MMIO_MEMBASE +
> >SEG_MEM_SIZE
> >> +#define PCI_SEG2_MMIO64_MAX PCI_SEG2_MMIO_MEMBASE +
> >SEG_MEM_LIMIT
> >> +#define PCI_SEG2_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp3BaseAddr)
> >> +
> >> +#define PCI_SEG2_DBI_BASE 0x03600000
> >> +
> >> +// Segment 3
> >> +#define PCI_SEG3_NUM 3
> >> +
> >> +#define PCI_SEG3_BUSNUM_MIN 0x0
> >> +#define PCI_SEG3_BUSNUM_MAX 0xff
> >> +
> >> +#define PCI_SEG3_PORTIO_MIN 0x30000
> >> +#define PCI_SEG3_PORTIO_MAX 0x3ffff
> >> +
> >> +#define PCI_SEG3_MMIO32_MIN 0x70000000
> >> +#define PCI_SEG3_MMIO32_MAX 0x7fffffff
> >> +#define PCI_SEG3_MMIO64_MIN PCI_SEG3_MMIO_MEMBASE +
> >SEG_MEM_SIZE
> >> +#define PCI_SEG3_MMIO64_MAX PCI_SEG3_MMIO_MEMBASE +
> >SEG_MEM_LIMIT
> >> +#define PCI_SEG3_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp4BaseAddr)
> >> +
> >> +#define PCI_SEG3_DBI_BASE 0x03700000
> >> +
> >> +// Segment configuration
> >> +#define SEG_CFG_SIZE 0x00001000
> >> +#define SEG_CFG_BUS 0x00000000
> >> +#define SEG_MEM_SIZE 0x40000000
> >> +#define SEG_MEM_LIMIT 0x7fffffff
> >> +#define SEG_MEM_BUS 0x40000000
> >> +#define SEG_IO_SIZE 0x00010000
> >> +#define SEG_IO_BUS 0x00000000
> >> +#define PCI_BASE_DIFF 0x800000000
> >> +#define PCI_DBI_SIZE_DIFF 0x100000
> >> +#define PCI_SEG0_PHY_CFG0_BASE PCI_SEG0_MMIO_MEMBASE
> >> +#define PCI_SEG0_PHY_CFG1_BASE PCI_SEG0_PHY_CFG0_BASE +
> >SEG_CFG_SIZE
> >> +#define PCI_SEG0_PHY_MEM_BASE PCI_SEG0_MMIO64_MIN
> >> +#define PCI_SEG0_PHY_IO_BASE PCI_SEG0_MMIO_MEMBASE +
> >SEG_IO_SIZE
> >> +
> >> +// iATU configuration
> >> +#define IATU_VIEWPORT_OFF 0x900
> >> +#define IATU_VIEWPORT_OUTBOUND 0
> >> +
> >> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904
> >> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0
> >> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
> >> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4 #define
> >> +IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
> >> +
> >> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
> >> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31
> >> +
> >> +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
> >> +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
> >> +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914
> >> +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918
> >> +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C
> >> +
> >> +#define IATU_REGION_INDEX0 0x0
> >> +#define IATU_REGION_INDEX1 0x1
> >> +#define IATU_REGION_INDEX2 0x2
> >> +#define IATU_REGION_INDEX3 0x3
> >> +
> >> +// PCIe Controller configuration
> >> +#define NUM_PCIE_CONTROLLER FixedPcdGet32 (PcdNumPciController)
> >> +#define PCI_LUT_DBG FixedPcdGet32 (PcdPcieLutDbg)
> >> +#define PCI_LUT_BASE FixedPcdGet32 (PcdPcieLutBase)
> >> +#define LTSSM_STATE_MASK 0x3f
> >> +#define LTSSM_PCIE_L0 0x11
> >> +#define PCI_LINK_CAP 0x7c
> >> +#define PCI_LINK_SPEED_MASK 0xf
> >> +#define PCI_CLASS_BRIDGE_PCI 0x6040010
> >> +#define PCI_CLASS_DEVICE 0x8
> >> +#define PCI_DBI_RO_WR_EN 0x8bc
> >> +#define PCI_BASE_ADDRESS_0 0x10
> >> +
> >> +VOID GetSerdesProtocolMaps (UINT64 *);
> >> +
> >> +BOOLEAN IsSerDesLaneProtocolConfigured (UINT64, UINT16);
> >> +
> >> +#endif
> >> diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> >> b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> >> new file mode 100644
> >> index 0000000..acb614d
> >> --- /dev/null
> >> +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> >> @@ -0,0 +1,604 @@
> >> +/** @file
> >> + PCI Segment Library for NXP SoCs with multiple RCs
> >> +
> >> + Copyright 2018 NXP
> >> +
> >> + This program and the accompanying materials are licensed and made
> >> + available under the terms and conditions of the BSD License which
> >> + accompanies this distribution. The full text of the license may be
> >> + found at
> >> +
> >https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fopensou
> >rce.org%2Flicenses%2Fbsd-
> >license.php&data=02%7C01%7Cvabhav.sharma%40nxp.com%7C081a2ebc43af4a
> >daaf8e08d5a62b9921%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6
> >36597628604269440&sdata=kt661HfkUD2E3sYswy0I4vVFTV3%2Fq%2FiM%2BiW
> >egCISP%2BU%3D&reserved=0.
> >> +
> >> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> >> + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> >EXPRESS OR IMPLIED.
> >> +
> >> +**/
> >> +
> >> +#include <Base.h>
> >> +#include <Library/PciSegmentLib.h>
> >> +#include <Library/BaseLib.h>
> >> +#include <Library/DebugLib.h>
> >> +#include <Library/IoLib.h>
> >> +#include <Library/PcdLib.h>
> >> +#include <Pcie.h>
> >> +
> >> +typedef enum {
> >> + PciCfgWidthUint8 = 0,
> >> + PciCfgWidthUint16,
> >> + PciCfgWidthUint32,
> >> + PciCfgWidthMax
> >> +} PCI_CFG_WIDTH;
> >> +
> >> +/**
> >> + Assert the validity of a PCI Segment address.
> >> + A valid PCI Segment address should not contain 1's in bits 28..31
> >> +and 48..63
> >> +
> >> + @param A The address to validate.
> >> + @param M Additional bits to assert to be zero.
> >> +
> >> +**/
> >> +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
> >> + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
> >> +
> >> +/**
> >> + Function to return PCIe Physical Address(PCIe view) or Controller
> >> + Address(CPU view) for different RCs
> >> +
> >> + @param Address Address passed from bus layer.
> >> + @param Segment Segment number for Root Complex.
> >> +
> >> + @return Return PCIe CPU or Controller address.
> >> +
> >> +**/
> >> +STATIC
> >> +UINT64
> >> +PciSegmentLibGetConfigBase (
> >> + IN UINT64 Address,
> >> + IN UINT16 Segment
> >> + )
> >> +{
> >> +
> >> + switch (Segment) {
> >> + // Root Complex 1
> >> + case PCI_SEG0_NUM:
> >> + // Reading bus number(bits 20-27)
> >> + if ((Address >> 20) & 1) {
> >> + return PCI_SEG0_MMIO_MEMBASE;
> >> + } else {
> >> + // On Bus 0 RCs are connected
> >> + return PCI_SEG0_DBI_BASE;
> >> + }
> >> + // Root Complex 2
> >> + case PCI_SEG1_NUM:
> >> + // Reading bus number(bits 20-27)
> >> + if ((Address >> 20) & 1) {
> >> + return PCI_SEG1_MMIO_MEMBASE;
> >> + } else {
> >> + // On Bus 0 RCs are connected
> >> + return PCI_SEG1_DBI_BASE;
> >> + }
> >> + // Root Complex 3
> >> + case PCI_SEG2_NUM:
> >> + // Reading bus number(bits 20-27)
> >> + if ((Address >> 20) & 1) {
> >> + return PCI_SEG2_MMIO_MEMBASE;
> >> + } else {
> >> + // On Bus 0 RCs are connected
> >> + return PCI_SEG2_DBI_BASE;
> >> + }
> >> + // Root Complex 4
> >> + case PCI_SEG3_NUM:
> >> + // Reading bus number(bits 20-27)
> >> + if ((Address >> 20) & 1) {
> >> + return PCI_SEG3_MMIO_MEMBASE;
> >> + } else {
> >> + // On Bus 0 RCs are connected
> >> + return PCI_SEG3_DBI_BASE;
> >> + }
> >> + default:
> >> + return 0;
> >> + }
> >> +
> >> +}
> >> +
> >> +/**
> >> + Internal worker function to read a PCI configuration register.
> >> +
> >> + @param Address The address that encodes the Segment, PCI Bus, Device,
> >> + Function and Register.
> >> + @param Width The width of data to read
> >> +
> >> + @return The value read from the PCI configuration register.
> >> +
> >> +**/
> >> +STATIC
> >> +UINT32
> >> +PciSegmentLibReadWorker (
> >> + IN UINT64 Address,
> >> + IN PCI_CFG_WIDTH Width
> >> + )
> >> +{
> >> + UINT64 Base;
> >> + UINT16 Offset;
> >> + UINT16 Segment;
> >> +
> >> + //
> >> + // Reading Segment number(47-32) bits in Address // Segment =
> >> + (Address >> 32); // // Reading Function(12-0) bits in Address //
> >> + Offset = (Address & 0xfff );
> >> +
> >> + Base = PciSegmentLibGetConfigBase (Address, Segment);
> >> +
> >> + //
> >> + // ignore devices > 0 on bus 0
> >> + //
> >> + if ((Address & 0xff00000) == 0 && (Address & 0xf8000) != 0) {
> >> + return MAX_UINT32;
> >> + }
> >> +
> >> + //
> >> + // ignore device > 0 on bus 1
> >> + //
> >> + if ((Address & 0xfe00000) == 0 && (Address & 0xf8000) != 0) {
> >> + return MAX_UINT32;
> >> + }
> >> +
> >> + switch (Width) {
> >> + case PciCfgWidthUint8:
> >> + return MmioRead8 (Base + (UINT8)Offset); case PciCfgWidthUint16:
Sorry - I missed thie before but spotted it while scrolling through
the reply: This cast of the offset is not only unnecessary, it is a
bug - offset is masked with 0xfff above, meaning it carries 12 bits of
value. Casting it to UINT8 discards the top 4.
(And because an explicit cast amounts to the same as telling the
compiler "I know better than you", this does not even result in a
warning.)
Anyway, please drop this and the subsequent two casts.
> >> + return MmioRead16 (Base + (UINT16)Offset); case
> >> + PciCfgWidthUint32:
> >> + return MmioRead32 (Base + (UINT32)Offset);
> >> + default:
> >> + ASSERT (FALSE);
> >> + }
> >> +
> >> + return CHAR_NULL;
> >> +}
> >> +
> >> +/**
> >> + Internal worker function to writes a PCI configuration register.
> >> +
> >> + @param Address The address that encodes the Segment, PCI Bus, Device,
> >> + Function and Register.
> >> + @param Width The width of data to write
> >> + @param Data The value to write.
> >> +
> >> + @return The value written to the PCI configuration register.
> >> +
> >> +**/
> >> +STATIC
> >> +UINT32
> >> +PciSegmentLibWriteWorker (
> >> + IN UINT64 Address,
> >> + IN PCI_CFG_WIDTH Width,
> >> + IN UINT32 Data
> >> + )
> >> +{
> >> + UINT64 Base;
> >> + UINT32 Offset;
> >> + UINT16 Segment;
> >> +
> >> + //
> >> + // Reading Segment number(47-32 bits) in Address Segment =
> >> + (Address >> 32); // // Reading Function(12-0 bits) in Address //
> >> + Offset = (Address & 0xfff );
> >
> >Spurious space after 0xfff.
> Alright, Thanks.
> Same applies to PciSegmentLibReadWorker()
> >
> >Could we have some macros and #defines instead of live-coded values in this
> >function?
>
> Sure, I assume Similar changes in PciSegmentLibReadWorker() required.
Err, yes please.
Umm, actually - the base functionality of those two functions are
identical (which is why I must have missed the ReadWorker with a
double page-down). Could that be turned into a helper function that
calculates addresses and offsets, called by readworker and writeworker
separately?
> >> +
> >> + Base = PciSegmentLibGetConfigBase (Address, Segment);
> >> +
> >> + //
> >> + // ignore devices > 0 on bus 0
> >> + //
> >> + if ((Address & 0xff00000) == 0 && (Address & 0xf8000) != 0) {
> >> + return Data;
> >> + }
> >> +
> >> + //
> >> + // ignore device > 0 on bus 1
> >> + //
> >> + if ((Address & 0xfe00000) == 0 && (Address & 0xf8000) != 0) {
> >> + return MAX_UINT32;
> >> + }
> >> +
> >> + switch (Width) {
> >> + case PciCfgWidthUint8:
> >> + MmioWrite8 (Base + (UINT8)Offset, Data);
(Same problem with the casts here.)
> >> + break;
> >> + case PciCfgWidthUint16:
> >> + MmioWrite16 (Base + (UINT16)Offset, Data);
> >> + break;
> >> + case PciCfgWidthUint32:
> >> + MmioWrite32 (Base + (UINT16)Offset, Data);
/
Leif
> >> + break;
> >> + default:
> >> + ASSERT (FALSE);
> >> + }
> >> +
> >> + return Data;
> >> +}
> >> +
> >> +/**
> >> + Register a PCI device so PCI configuration registers may be
> >> +accessed after
> >> + SetVirtualAddressMap().
> >> +
> >> + If any reserved bits in Address are set, then ASSERT().
> >> +
> >> + @param Address The address that encodes the PCI Bus, Device,
> >> + Function and Register.
> >> +
> >> + @retval RETURN_SUCCESS The PCI device was registered for runtime
> >access.
> >> + @retval RETURN_UNSUPPORTED An attempt was made to call this
> >function
> >> + after ExitBootServices().
> >> + @retval RETURN_UNSUPPORTED The resources required to access the
> >PCI device
> >> + at runtime could not be mapped.
> >> + @retval RETURN_OUT_OF_RESOURCES There are not enough resources
> >available to
> >> + complete the registration.
> >> +
>> +**/
> >> +RETURN_STATUS
> >> +EFIAPI
> >> +PciSegmentRegisterForRuntimeAccess (
> >> + IN UINTN Address
> >> + )
> >> +{
> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> >> + return RETURN_UNSUPPORTED;
> >> +}
> >> +
> >> +/**
> >> + Reads an 8-bit PCI configuration register.
> >> +
> >> + Reads and returns the 8-bit PCI configuration register specified by Address.
> >> +
> >> + If any reserved bits in Address are set, then ASSERT().
> >> +
> >> + @param Address The address that encodes the PCI Segment, Bus, Device,
> >Function,
> >> + and Register.
> >> +
> >> + @return The 8-bit PCI configuration register specified by Address.
> >> +
> >> +**/
> >> +UINT8
> >> +EFIAPI
> >> +PciSegmentRead8 (
> >> + IN UINT64 Address
> >> + )
> >> +{
> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> >> +
> >> + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
> >> +}
> >> +
> >> +/**
> >> + Writes an 8-bit PCI configuration register.
> >> +
> >> + Writes the 8-bit PCI configuration register specified by Address with the value
> >specified by Value.
> >> + Value is returned. This function must guarantee that all PCI read and write
> >operations are serialized.
> >> +
> >> + If any reserved bits in Address are set, then ASSERT().
> >> +
> >> + @param Address The address that encodes the PCI Segment, Bus, Device,
> >Function, and Register.
> >> + @param Value The value to write.
> >> +
> >> + @return The value written to the PCI configuration register.
> >> +
> >> +**/
> >> +UINT8
> >> +EFIAPI
> >> +PciSegmentWrite8 (
> >> + IN UINT64 Address,
> >> + IN UINT8 Value
> >> + )
> >> +{
> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> >> +
> >> + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8,
> >> +Value); }
> >> +
> >> +/**
> >> + Reads a 16-bit PCI configuration register.
> >> +
> >> + Reads and returns the 16-bit PCI configuration register specified by Address.
> >> +
> >> + If any reserved bits in Address are set, then ASSERT().
> >> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> >> +
> >> + @param Address The address that encodes the PCI Segment, Bus, Device,
> >Function, and Register.
> >> +
> >> + @return The 16-bit PCI configuration register specified by Address.
> >> +
> >> +**/
> >> +UINT16
> >> +EFIAPI
> >> +PciSegmentRead16 (
> >> + IN UINT64 Address
> >> + )
> >> +{
> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> >> +
> >> + return (UINT16) PciSegmentLibReadWorker (Address,
> >> +PciCfgWidthUint16); }
> >> +
> >> +/**
> >> + Writes a 16-bit PCI configuration register.
> >> +
> >> + Writes the 16-bit PCI configuration register specified by Address
> >> + with the value specified by Value.
> >> +
> >> + Value is returned.
> >> +
> >> + If any reserved bits in Address are set, then ASSERT().
> >> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> >> +
> >> + @param Address The address that encodes the PCI Segment, Bus, Device,
> >Function, and Register.
> >> + @param Value The value to write.
> >> +
> >> + @return The parameter of Value.
> >> +
> >> +**/
> >> +UINT16
> >> +EFIAPI
> >> +PciSegmentWrite16 (
> >> + IN UINT64 Address,
> >> + IN UINT16 Value
> >> + )
> >> +{
> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> >> +
> >> + return (UINT16) PciSegmentLibWriteWorker (Address,
> >> +PciCfgWidthUint16, Value); }
> >> +
> >> +/**
> >> + Reads a 32-bit PCI configuration register.
> >> +
> >> + Reads and returns the 32-bit PCI configuration register specified by Address.
> >> +
> >> + If any reserved bits in Address are set, then ASSERT().
> >> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> >> +
> >> + @param Address The address that encodes the PCI Segment, Bus, Device,
> >Function,
> >> + and Register.
> >> +
> >> + @return The 32-bit PCI configuration register specified by Address.
> >> +
> >> +**/
> >> +UINT32
> >> +EFIAPI
> >> +PciSegmentRead32 (
> >> + IN UINT64 Address
> >> + )
> >> +{
> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> >> +
> >> + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32); }
> >> +
> >> +/**
> >> + Writes a 32-bit PCI configuration register.
> >> +
> >> + Writes the 32-bit PCI configuration register specified by Address
> >> + with the value specified by Value.
> >> +
> >> + Value is returned.
> >> +
> >> + If any reserved bits in Address are set, then ASSERT().
> >> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> >> +
> >> + @param Address The address that encodes the PCI Segment, Bus, Device,
> >> + Function, and Register.
> >> + @param Value The value to write.
> >> +
> >> + @return The parameter of Value.
> >> +
> >> +**/
> >> +UINT32
> >> +EFIAPI
> >> +PciSegmentWrite32 (
> >> + IN UINT64 Address,
> >> + IN UINT32 Value
> >> + )
> >> +{
> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> >> +
> >> + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32,
> >> +Value); }
> >> +
> >> +/**
> >> + Reads a range of PCI configuration registers into a caller supplied buffer.
> >> +
> >> + Reads the range of PCI configuration registers specified by
> >> + StartAddress and Size into the buffer specified by Buffer. This
> >> + function only allows the PCI configuration registers from a single
> >> + PCI function to be read. Size is returned.
> >> +
> >> + If any reserved bits in StartAddress are set, then ASSERT().
> >> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> >> + If Size > 0 and Buffer is NULL, then ASSERT().
> >> +
> >> + @param StartAddress The starting address that encodes the PCI Segment,
> >Bus,
> >> + Device, Function and Register.
> >> + @param Size The size in bytes of the transfer.
> >> + @param Buffer The pointer to a buffer receiving the data read.
> >> +
> >> + @return Size
> >> +
> >> +**/
> >> +UINTN
> >> +EFIAPI
> >> +PciSegmentReadBuffer (
> >> + IN UINT64 StartAddress,
> >> + IN UINTN Size,
> >> + OUT VOID *Buffer
> >> + )
> >> +{
> >> + UINTN ReturnValue;
> >> +
> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); // 0xFFF is
> >> + used as limit for 4KB config space ASSERT (((StartAddress & 0xFFF)
> >> + + Size) <= SIZE_4KB);
> >> +
> >> + if (Size == 0) {
> >> + return Size;
> >> + }
> >> +
> >> + ASSERT (Buffer != NULL);
> >> +
> >> + //
> >> + // Save Size for return
> >> + //
> >> + ReturnValue = Size;
> >> +
> >> + if ((StartAddress & BIT0) != 0) {
> >> + //
> >> + // Read a byte if StartAddress is byte aligned
> >> + //
> >> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
> >
> >Why volatile on Buffer?
> I took reference from Socionext, Not required .
> PCIe region has device attribute.
> >
> >> + StartAddress += sizeof (UINT8);
> >> + Size -= sizeof (UINT8);
> >> + Buffer = (UINT8*)Buffer + BIT0;
> >
> >sizeof (UINT8) instead of BIT0?
> >
> >And this is a VOID *, so can just write.
> > Buffer += sizeof (UINT8);
> >
> Yes,Sure.
> >> + }
> >> +
> >> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> >> + //
> >> + // Read a word if StartAddress is word aligned
> >> + //
> >> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> >> + StartAddress += sizeof (UINT16);
> >> + Size -= sizeof (UINT16);
> >> + Buffer = (UINT16*)Buffer + BIT0;
> >
> >That is a very confusing use of pointer arithmetic.
> > Buffer += sizeof (UINT16);
> >
> Agree, alright.
> >> + }
> >> +
> >> + while (Size >= sizeof (UINT32)) {
> >> + //
> >> + // Read as many double words as possible
> >> + //
> >> + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
> >> + StartAddress += sizeof (UINT32);
> >> + Size -= sizeof (UINT32);
> >> + Buffer = (UINT32*)Buffer + BIT0;
> >
> > Buffer += sizeof (UINT32);
> Ok
> >
> >> + }
> >> +
> >> + if (Size >= sizeof (UINT16)) {
> >> + //
> >> + // Read the last remaining word if exist
> >> + //
> >> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> >> + StartAddress += sizeof (UINT16);
> >> + Size -= sizeof (UINT16);
> >> + Buffer = (UINT16*)Buffer + BIT0;
> >
> > Buffer += sizeof (UINT16);
> Ok
> >
> >> + }
> >> +
> >> + if (Size >= sizeof (UINT8)) {
> >> + //
> >> + // Read the last remaining byte if exist
> >> + //
> >> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
> >
> >There is that scary volatile again.
> Not required.
> >
> >> + }
> >> +
> >> + return ReturnValue;
> >> +}
> >> +
> >> +
> >> +/**
> >> + Copies the data in a caller supplied buffer to a specified range of
> >> +PCI
> >> + configuration space.
> >> +
> >> + Writes the range of PCI configuration registers specified by
> >> + StartAddress and Size from the buffer specified by Buffer. This
> >> + function only allows the PCI configuration registers from a single
> >> + PCI function to be written. Size is returned.
> >> +
> >> + If any reserved bits in StartAddress are set, then ASSERT().
> >> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> >> + If Size > 0 and Buffer is NULL, then ASSERT().
> >> +
> >> + @param StartAddress The starting address that encodes the PCI Segment,
> >Bus,
> >> + Device, Function and Register.
> >> + @param Size The size in bytes of the transfer.
> >> + @param Buffer The pointer to a buffer containing the data to write.
> >> +
> >> + @return The parameter of Size.
> >> +
> >> +**/
> >> +UINTN
> >> +EFIAPI
> >> +PciSegmentWriteBuffer (
> >> + IN UINT64 StartAddress,
> >> + IN UINTN Size,
> >> + IN VOID *Buffer
> >> + )
> >> +{
> >> + UINTN ReturnValue;
> >> +
> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); // 0xFFF is
> >> + used as limit for 4KB config space ASSERT (((StartAddress & 0xFFF)
> >> + + Size) <= SIZE_4KB);
> >
> >Can you use (SIZE_4KB - 1) instead of 0xFFF?
> Yes,Sure.
> >
> >> +
> >> + if (Size == 0) {
> >> + return Size;
> >> + }
> >> +
> >> + ASSERT (Buffer != NULL);
> >> +
> >> + //
> >> + // Save Size for return
> >> + //
> >> + ReturnValue = Size;
> >> +
> >> + if ((StartAddress & BIT0) != 0) {
> >> + //
> >> + // Write a byte if StartAddress is byte aligned
> >> + //
> >> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> >> + StartAddress += sizeof (UINT8);
> >> + Size -= sizeof (UINT8);
> >> + Buffer = (UINT8*)Buffer + BIT0;
> >
> >Same comments for Buffer pointer update as previous function, throughout.
> Ok
> >
> >/
> > Leif
> >
> >> + }
> >> +
> >> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> >> + //
> >> + // Write a word if StartAddress is word aligned
> >> + //
> >> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> >> + StartAddress += sizeof (UINT16);
> >> + Size -= sizeof (UINT16);
> >> + Buffer = (UINT16*)Buffer + BIT0;
> >> + }
> >> +
> >> + while (Size >= sizeof (UINT32)) {
> >> + //
> >> + // Write as many double words as possible
> >> + //
> >> + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
> >> + StartAddress += sizeof (UINT32);
> >> + Size -= sizeof (UINT32);
> >> + Buffer = (UINT32*)Buffer + BIT0;
> >> + }
> >> +
> >> + if (Size >= sizeof (UINT16)) {
> >> + //
> >> + // Write the last remaining word if exist
> >> + //
> >> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> >> + StartAddress += sizeof (UINT16);
> >> + Size -= sizeof (UINT16);
> >> + Buffer = (UINT16*)Buffer + BIT0;
> >> + }
> >> +
> >> + if (Size >= sizeof (UINT8)) {
> >> + //
> >> + // Write the last remaining byte if exist
> >> + //
> >> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); }
> >> +
> >> + return ReturnValue;
> >> +}
> >> diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> >> b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> >> new file mode 100644
> >> index 0000000..1ac83d4
> >> --- /dev/null
> >> +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> >> @@ -0,0 +1,41 @@
> >> +## @file
> >> +# PCI Segment Library for NXP SoCs with multiple RCs # # Copyright
> >> +2018 NXP # # This program and the accompanying materials # are
> >> +licensed and made available under the terms and conditions of the BSD
> >> +License # which accompanies this distribution. The full text of the
> >> +license may be found at #
> >https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fopensou
> >rce.org%2Flicenses%2Fbsd-
> >license.php&data=02%7C01%7Cvabhav.sharma%40nxp.com%7C081a2ebc43af4a
> >daaf8e08d5a62b9921%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6
> >36597628604269440&sdata=kt661HfkUD2E3sYswy0I4vVFTV3%2Fq%2FiM%2BiW
> >egCISP%2BU%3D&reserved=0.
> >> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> >> +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> >EITHER EXPRESS OR IMPLIED.
> >> +#
> >> +#
> >> +##
> >> +
> >> +[Defines]
> >> + INF_VERSION = 0x0001001A
> >> + BASE_NAME = PciSegmentLib
> >> + FILE_GUID = c9f59261-5a60-4a4c-82f6-1f520442e100
> >> + MODULE_TYPE = BASE
> >> + VERSION_STRING = 1.0
> >> + LIBRARY_CLASS = PciSegmentLib
> >> +
> >> +[Sources]
> >> + PciSegmentLib.c
> >> +
> >> +[Packages]
> >> + MdePkg/MdePkg.dec
> >> + Silicon/NXP/NxpQoriqLs.dec
> >> +
> >> +[LibraryClasses]
> >> + BaseLib
> >> + DebugLib
> >> + IoLib
> >> + PcdLib
> >> +
> >> +[Pcd]
> >> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> >> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> >> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> >> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> >> --
> >> 1.9.1
> >>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 33/39] Silicon/NXP: Implement PciHostBridgeLib support
2018-02-16 8:50 ` [PATCH edk2-platforms 33/39] Silicon/NXP: Implement PciHostBridgeLib support Meenakshi
2018-04-20 8:34 ` Ard Biesheuvel
@ 2018-04-20 14:54 ` Leif Lindholm
2018-04-24 12:32 ` Vabhav Sharma
1 sibling, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-20 14:54 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Vabhav
My only comment in addition to Ard's comments/questions:
Use same endianness handling here as for preceding patches?
/
Leif
On Fri, Feb 16, 2018 at 02:20:29PM +0530, Meenakshi wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Implement the library that exposes the PCIe root complexes to the
> generic PCI host bridge driver,Putting SoC Specific low level init
> code for the RCs.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 618 +++++++++++++++++++++
> .../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 50 ++
> 2 files changed, 668 insertions(+)
> create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>
> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> new file mode 100644
> index 0000000..e6f9b7c
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> @@ -0,0 +1,618 @@
> +/** @file
> + PCI Host Bridge Library instance for NXP SoCs
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <IndustryStandard/Pci22.h>
> +#include <Library/BeIoLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PciHostBridgeLib.h>
> +#include <Pcie.h>
> +#include <Protocol/PciHostBridgeResourceAllocation.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +
> +#pragma pack(1)
> +typedef struct {
> + ACPI_HID_DEVICE_PATH AcpiDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
> +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
> +#pragma pack ()
> +
> +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG0_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG1_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG2_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG3_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + }
> +};
> +
> +STATIC
> +GLOBAL_REMOVE_IF_UNREFERENCED
> +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
> + L"Mem", L"I/O", L"Bus"
> +};
> +
> +#define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | \
> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE
> +
> +#define PCI_SUPPORT_ATTRIBUTES EFI_PCI_ATTRIBUTE_ISA_IO_16 | \
> + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
> + EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
> + EFI_PCI_ATTRIBUTE_VGA_IO_16 | \
> + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
> +
> +PCI_ROOT_BRIDGE mPciRootBridges[] = {
> + {
> + PCI_SEG0_NUM, // Segment
> + PCI_SUPPORT_ATTRIBUTES, // Supports
> + PCI_SUPPORT_ATTRIBUTES, // Attributes
> + FALSE, // DmaAbove4G
> + FALSE, // NoExtendedConfigSpace
> + FALSE, // ResourceAssigned
> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
> + { PCI_SEG0_BUSNUM_MIN,
> + PCI_SEG0_BUSNUM_MAX }, // Bus
> + { PCI_SEG0_PORTIO_MIN,
> + PCI_SEG0_PORTIO_MAX }, // Io
> + { PCI_SEG0_MMIO32_MIN,
> + PCI_SEG0_MMIO32_MAX }, // Mem
> + { PCI_SEG0_MMIO64_MIN,
> + PCI_SEG0_MMIO64_MAX }, // MemAbove4G
> + { MAX_UINT64, 0x0 }, // PMem
> + { MAX_UINT64, 0x0 }, // PMemAbove4G
> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG0_NUM]
> + }, {
> + PCI_SEG1_NUM, // Segment
> + PCI_SUPPORT_ATTRIBUTES, // Supports
> + PCI_SUPPORT_ATTRIBUTES, // Attributes
> + FALSE, // DmaAbove4G
> + FALSE, // NoExtendedConfigSpace
> + FALSE, // ResourceAssigned
> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
> + { PCI_SEG1_BUSNUM_MIN,
> + PCI_SEG1_BUSNUM_MAX }, // Bus
> + { PCI_SEG1_PORTIO_MIN,
> + PCI_SEG1_PORTIO_MAX }, // Io
> + { PCI_SEG1_MMIO32_MIN,
> + PCI_SEG1_MMIO32_MAX }, // Mem
> + { PCI_SEG1_MMIO64_MIN,
> + PCI_SEG1_MMIO64_MAX }, // MemAbove4G
> + { MAX_UINT64, 0x0 }, // PMem
> + { MAX_UINT64, 0x0 }, // PMemAbove4G
> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG1_NUM]
> + }, {
> + PCI_SEG2_NUM, // Segment
> + PCI_SUPPORT_ATTRIBUTES, // Supports
> + PCI_SUPPORT_ATTRIBUTES, // Attributes
> + FALSE, // DmaAbove4G
> + FALSE, // NoExtendedConfigSpace
> + FALSE, // ResourceAssigned
> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
> + { PCI_SEG2_BUSNUM_MIN,
> + PCI_SEG2_BUSNUM_MAX }, // Bus
> + { PCI_SEG2_PORTIO_MIN,
> + PCI_SEG2_PORTIO_MAX }, // Io
> + { PCI_SEG2_MMIO32_MIN,
> + PCI_SEG2_MMIO32_MAX }, // Mem
> + { PCI_SEG2_MMIO64_MIN,
> + PCI_SEG2_MMIO64_MAX }, // MemAbove4G
> + { MAX_UINT64, 0x0 }, // PMem
> + { MAX_UINT64, 0x0 }, // PMemAbove4G
> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG2_NUM]
> + }, {
> + PCI_SEG3_NUM, // Segment
> + PCI_SUPPORT_ATTRIBUTES, // Supports
> + PCI_SUPPORT_ATTRIBUTES, // Attributes
> + FALSE, // DmaAbove4G
> + FALSE, // NoExtendedConfigSpace
> + FALSE, // ResourceAssigned
> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
> + { PCI_SEG3_BUSNUM_MIN,
> + PCI_SEG3_BUSNUM_MAX }, // Bus
> + { PCI_SEG3_PORTIO_MIN,
> + PCI_SEG3_PORTIO_MAX }, // Io
> + { PCI_SEG3_MMIO32_MIN,
> + PCI_SEG3_MMIO32_MAX }, // Mem
> + { PCI_SEG3_MMIO64_MIN,
> + PCI_SEG3_MMIO64_MAX }, // MemAbove4G
> + { MAX_UINT64, 0x0 }, // PMem
> + { MAX_UINT64, 0x0 }, // PMemAbove4G
> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG3_NUM]
> + }
> +};
> +
> +/**
> + Function to set-up iATU outbound window for PCIe controller
> +
> + @param Dbi Address of PCIe host controller.
> + @param Idx Index of iATU outbound window.
> + @param Type Type(Cfg0/Cfg1/Mem/IO) of iATU outbound window.
> + @param Phys PCIe controller phy address for outbound window.
> + @param BusAdr PCIe controller bus address for outbound window.
> + @param Pcie Size of PCIe controller space(Cfg0/Cfg1/Mem/IO).
> +
> +**/
> +STATIC
> +VOID
> +PcieIatuOutboundSet (
> + IN EFI_PHYSICAL_ADDRESS Dbi,
> + IN UINT32 Idx,
> + IN UINT32 Type,
> + IN UINT64 Phys,
> + IN UINT64 BusAddr,
> + IN UINT64 Size
> + )
> +{
> + MmioWrite32 (Dbi + IATU_VIEWPORT_OFF,
> + (UINT32)(IATU_VIEWPORT_OUTBOUND | Idx));
> + MmioWrite32 (Dbi + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
> + (UINT32)Phys);
> + MmioWrite32 (Dbi + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(Phys >> 32));
> + MmioWrite32 (Dbi + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(Phys + Size - BIT0));
> + MmioWrite32 (Dbi + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
> + (UINT32)BusAddr);
> + MmioWrite32 (Dbi + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(BusAddr >> 32));
> + MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
> + (UINT32)Type);
> + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
> + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN);
> +}
> +
> +/**
> + Function to check PCIe controller LTSSM state
> +
> + @param Pcie Address of PCIe host controller.
> +
> +**/
> +STATIC
> +INTN
> +PcieLinkState (
> + IN EFI_PHYSICAL_ADDRESS Pcie
> + )
> +{
> + UINT32 State;
> +
> + //
> + // Reading PCIe controller LTSSM state
> + //
> + if (FeaturePcdGet (PcdPciLutBigEndian)) {
> + State = BeMmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
> + LTSSM_STATE_MASK;
> + } else {
> + State = MmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
> + LTSSM_STATE_MASK;
> + }
> +
> + if (State < LTSSM_PCIE_L0) {
> + DEBUG ((DEBUG_INFO," Pcie Link error. LTSSM=0x%2x\n", State));
> + return EFI_SUCCESS;
> + }
> +
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + Helper function to check PCIe link state
> +
> + @param Pcie Address of PCIe host controller.
> +
> +**/
> +STATIC
> +INTN
> +PcieLinkUp (
> + IN EFI_PHYSICAL_ADDRESS Pcie
> + )
> +{
> + INTN State;
> + UINT32 Cap;
> +
> + State = PcieLinkState (Pcie);
> + if (State) {
> + return State;
> + }
> +
> + //
> + // Try to download speed to gen1
> + //
> + Cap = MmioRead32 ((UINTN)Pcie + PCI_LINK_CAP);
> + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, (UINT32)(Cap & (~PCI_LINK_SPEED_MASK)) | BIT0);
> + State = PcieLinkState (Pcie);
> + if (State) {
> + return State;
> + }
> +
> + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, Cap);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function checks whether PCIe is enabled or not
> + depending upon SoC serdes protocol map
> +
> + @param PcieNum PCIe number.
> +
> + @return The PCIe number enabled in map.
> + @return FALSE PCIe number is disabled in map.
> +
> +**/
> +STATIC
> +BOOLEAN
> +IsPcieNumEnabled(
> + IN UINTN PcieNum
> + )
> +{
> + UINT64 SerDes1ProtocolMap;
> +
> + SerDes1ProtocolMap = 0x0;
> +
> + //
> + // Reading serdes map
> + //
> + GetSerdesProtocolMaps (&SerDes1ProtocolMap);
> +
> + //
> + // Verify serdes line is configured in the map
> + //
> + if (PcieNum < NUM_PCIE_CONTROLLER) {
> + return IsSerDesLaneProtocolConfigured (SerDes1ProtocolMap, (PcieNum + BIT0));
> + } else {
> + DEBUG ((DEBUG_ERROR, "Device not supported\n"));
> + }
> +
> + return FALSE;
> +}
> +
> +/**
> + Function to set-up iATU outbound window for PCIe controller
> +
> + @param Pcie Address of PCIe host controller
> + @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
> + @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
> + @param MemBase PCIe controller phy address Memory Space.
> + @param IoBase PCIe controller phy address IO Space.
> +**/
> +STATIC
> +VOID
> +PcieSetupAtu (
> + IN EFI_PHYSICAL_ADDRESS Pcie,
> + IN EFI_PHYSICAL_ADDRESS Cfg0Base,
> + IN EFI_PHYSICAL_ADDRESS Cfg1Base,
> + IN EFI_PHYSICAL_ADDRESS MemBase,
> + IN EFI_PHYSICAL_ADDRESS IoBase
> + )
> +{
> +
> + //
> + // iATU : OUTBOUND WINDOW 0 : CFG0
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX0,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
> + Cfg0Base,
> + SEG_CFG_BUS,
> + SEG_CFG_SIZE);
> +
> + //
> + // iATU : OUTBOUND WINDOW 1 : CFG1
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX1,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
> + Cfg1Base,
> + SEG_CFG_BUS,
> + SEG_CFG_SIZE);
> + //
> + // iATU 2 : OUTBOUND WINDOW 2 : MEM
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX2,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
> + MemBase,
> + SEG_MEM_BUS,
> + SEG_MEM_SIZE);
> +
> + //
> + // iATU 3 : OUTBOUND WINDOW 3: IO
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX3,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
> + IoBase,
> + SEG_IO_BUS,
> + SEG_IO_SIZE);
> +
> +}
> +
> +/**
> + Helper function to set-up PCIe controller
> +
> + @param Pcie Address of PCIe host controller
> + @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
> + @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
> + @param MemBase PCIe controller phy address Memory Space.
> + @param IoBase PCIe controller phy address IO Space.
> +
> +**/
> +STATIC
> +VOID
> +PcieSetupCntrl (
> + IN EFI_PHYSICAL_ADDRESS Pcie,
> + IN EFI_PHYSICAL_ADDRESS Cfg0Base,
> + IN EFI_PHYSICAL_ADDRESS Cfg1Base,
> + IN EFI_PHYSICAL_ADDRESS MemBase,
> + IN EFI_PHYSICAL_ADDRESS IoBase
> + )
> +{
> + //
> + // iATU outbound set-up
> + //
> + PcieSetupAtu (Pcie, Cfg0Base, Cfg1Base, MemBase, IoBase);
> +
> + //
> + // program correct class for RC
> + //
> + MmioWrite32 ((UINTN)Pcie + PCI_BASE_ADDRESS_0, (BIT0 - BIT0));
> + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)BIT0);
> + MmioWrite32 ((UINTN)Pcie + PCI_CLASS_DEVICE, (UINT32)PCI_CLASS_BRIDGE_PCI);
> + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)(BIT0 - BIT0));
> +}
> +
> +/**
> + Return all the root bridge instances in an array.
> +
> + @param Count Return the count of root bridge instances.
> +
> + @return All the root bridge instances in an array.
> +
> +**/
> +PCI_ROOT_BRIDGE *
> +EFIAPI
> +PciHostBridgeGetRootBridges (
> + OUT UINTN *Count
> + )
> +{
> + UINTN Idx;
> + INTN LinkUp;
> + UINT64 PciPhyMemAddr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyCfg0Addr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyCfg1Addr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyIoAddr[NUM_PCIE_CONTROLLER];
> + UINT64 Regs[NUM_PCIE_CONTROLLER];
> +
> + *Count = 0;
> +
> + //
> + // Filling local array for
> + // PCIe controller Physical address space for Cfg0,Cfg1,Mem,IO
> + // Host Contoller address
> + //
> + for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
> + PciPhyMemAddr[Idx] = PCI_SEG0_PHY_MEM_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyCfg0Addr[Idx] = PCI_SEG0_PHY_CFG0_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyCfg1Addr[Idx] = PCI_SEG0_PHY_CFG1_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyIoAddr [Idx] = PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx);
> + Regs[Idx] = PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx);
> + }
> +
> + for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
> + //
> + // Verify PCIe controller is enabled in Soc Serdes Map
> + //
> + if (!IsPcieNumEnabled (Idx)) {
> + DEBUG ((DEBUG_ERROR, "PCIE%d is disabled\n", (Idx + BIT0)));
> + //
> + // Continue with other PCIe controller
> + //
> + continue;
> + }
> + DEBUG ((DEBUG_INFO, "PCIE%d is Enabled\n", Idx + BIT0));
> +
> + //
> + // Verify PCIe controller LTSSM state
> + //
> + LinkUp = PcieLinkUp(Regs[Idx]);
> + if (!LinkUp) {
> + //
> + // Let the user know there's no PCIe link
> + //
> + DEBUG ((DEBUG_INFO,"no link, regs @ 0x%lx\n", Regs[Idx]));
> + //
> + // Continue with other PCIe controller
> + //
> + continue;
> + }
> + DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + BIT0));
> +
> + //
> + // Function to set up address translation unit outbound window for
> + // PCIe Controller
> + //
> + PcieSetupCntrl (Regs[Idx],
> + PciPhyCfg0Addr[Idx],
> + PciPhyCfg1Addr[Idx],
> + PciPhyMemAddr[Idx],
> + PciPhyIoAddr[Idx]);
> + *Count += BIT0;
> + break;
> + }
> +
> + if (*Count == 0) {
> + return NULL;
> + } else {
> + return &mPciRootBridges[Idx];
> + }
> +}
> +
> +/**
> + Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
> +
> + @param Bridges The root bridge instances array.
> + @param Count The count of the array.
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeFreeRootBridges (
> + PCI_ROOT_BRIDGE *Bridges,
> + UINTN Count
> + )
> +{
> +}
> +
> +/**
> + Inform the platform that the resource conflict happens.
> +
> + @param HostBridgeHandle Handle of the Host Bridge.
> + @param Configuration Pointer to PCI I/O and PCI memory resource
> + descriptors. The Configuration contains the resources
> + for all the root bridges. The resource for each root
> + bridge is terminated with END descriptor and an
> + additional END is appended indicating the end of the
> + entire resources. The resource descriptor field
> + values follow the description in
> + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
> + .SubmitResources().
> +
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeResourceConflict (
> + EFI_HANDLE HostBridgeHandle,
> + VOID *Configuration
> + )
> +{
> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
> + UINTN RootBridgeIndex;
> + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
> +
> + RootBridgeIndex = 0;
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
> + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
> + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
> + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
> + ASSERT (Descriptor->ResType <
> + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));
> + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
> + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
> + Descriptor->AddrLen, Descriptor->AddrRangeMax
> + ));
> + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
> + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
> + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
> + ((Descriptor->SpecificFlag &
> + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
> + ) != 0) ? L" (Prefetchable)" : L""
> + ));
> + }
> + }
> + //
> + // Skip the END descriptor for root bridge
> + //
> + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
> + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
> + );
> + }
> +
> + return;
> +}
> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> new file mode 100644
> index 0000000..f08ac60
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> @@ -0,0 +1,50 @@
> +## @file
> +# PCI Host Bridge Library instance for NXP ARM SOC
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials are licensed and made available
> +# under the terms and conditions of the BSD License which accompanies this
> +# distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> +# IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PciHostBridgeLib
> + FILE_GUID = f4c99bcc-5c95-49ad-b0f3-fc5b611dc9c1
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciHostBridgeLib
> +
> +[Sources]
> + PciHostBridgeLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> +
> +[LibraryClasses]
> + DebugLib
> + DevicePathLib
> + MemoryAllocationLib
> + PcdLib
> + SocLib
> + UefiBootServicesTableLib
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 34/39] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
2018-02-16 8:50 ` [PATCH edk2-platforms 34/39] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL Meenakshi
2018-04-20 8:40 ` Ard Biesheuvel
@ 2018-04-20 15:15 ` Leif Lindholm
2018-04-24 12:40 ` Vabhav Sharma
1 sibling, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-20 15:15 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Vabhav
On Fri, Feb 16, 2018 at 02:20:30PM +0530, Meenakshi wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> NXP SOC has mutiple PCIe RCs,Adding respective implementation of
> EFI_CPU_IO2_PROTOCOL to provide Memory Space Read/Write functions
> used by generic Host Bridge Driver including correct value for
> the translation offset during MMIO accesses
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 529 ++++++++++++++++++++++
> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 ++
> 2 files changed, 577 insertions(+)
> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>
> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> new file mode 100644
> index 0000000..b5fb72c
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> @@ -0,0 +1,529 @@
> +/** @file
> + Produces the CPU I/O 2 Protocol.
> +
> + Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Pcie.h>
> +#include <Protocol/CpuIo2.h>
> +
> +#define MAX_IO_PORT_ADDRESS PCI_SEG2_PORTIO_MAX
> +
> +//
> +// Handle for the CPU I/O 2 Protocol
> +//
> +STATIC EFI_HANDLE mHandle;
> +
> +//
> +// Lookup table for increment values based on transfer widths
> +//
> +STATIC CONST UINT8 mInStride[] = {
> + 1, // EfiCpuIoWidthUint8
> + 2, // EfiCpuIoWidthUint16
> + 4, // EfiCpuIoWidthUint32
> + 8, // EfiCpuIoWidthUint64
> + 0, // EfiCpuIoWidthFifoUint8
> + 0, // EfiCpuIoWidthFifoUint16
> + 0, // EfiCpuIoWidthFifoUint32
> + 0, // EfiCpuIoWidthFifoUint64
> + 1, // EfiCpuIoWidthFillUint8
> + 2, // EfiCpuIoWidthFillUint16
> + 4, // EfiCpuIoWidthFillUint32
> + 8 // EfiCpuIoWidthFillUint64
> +};
> +
> +//
> +// Lookup table for increment values based on transfer widths
> +//
> +STATIC CONST UINT8 mOutStride[] = {
> + 1, // EfiCpuIoWidthUint8
> + 2, // EfiCpuIoWidthUint16
> + 4, // EfiCpuIoWidthUint32
> + 8, // EfiCpuIoWidthUint64
> + 1, // EfiCpuIoWidthFifoUint8
> + 2, // EfiCpuIoWidthFifoUint16
> + 4, // EfiCpuIoWidthFifoUint32
> + 8, // EfiCpuIoWidthFifoUint64
> + 0, // EfiCpuIoWidthFillUint8
> + 0, // EfiCpuIoWidthFillUint16
> + 0, // EfiCpuIoWidthFillUint32
> + 0 // EfiCpuIoWidthFillUint64
> +};
> +
> +/**
> + Check parameters to a CPU I/O 2 Protocol service request.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[in] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The parameters for this request pass the checks.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +CpuIoCheckParameter (
> + IN BOOLEAN MmioOperation,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + UINT64 MaxCount;
> + UINT64 Limit;
> +
> + //
> + // Check to see if Buffer is NULL
> + //
> + if (Buffer == NULL) {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Check to see if Width is in the valid range
> + //
> + if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // For FIFO type, the target address won't increase during the access,
> + // so treat Count as 1
> + //
> + if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
> + Count = 1;
> + }
> +
> + //
> + // Check to see if Width is in the valid range for I/O Port operations
> + //
> + Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
> + if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Check to see if Address is aligned
> + //
> + if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Check to see if any address associated with this transfer exceeds the maximum
> + // allowed address. The maximum address implied by the parameters passed in is
> + // Address + Size * Count. If the following condition is met, then the transfer
> + // is not supported.
> + //
> + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
> + //
> + // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
> + // can also be the maximum integer value supported by the CPU, this range
> + // check must be adjusted to avoid all oveflow conditions.
> + //
> + Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
> + if (Count == 0) {
> + if (Address > Limit) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> + } else {
> + MaxCount = RShiftU64 (Limit, Width);
> + if (MaxCount < (Count - 1)) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> + }
> +
> + //
> + // Check to see if Buffer is aligned
> + //
> + if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Reads memory-mapped registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[out] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuMemoryServiceRead (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 InStride;
> + UINT8 OutStride;
> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
> + UINT8 *Uint8Buffer;
> +
> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if ((Address >= PCI_SEG0_MMIO32_MIN) &&
> + (Address <= PCI_SEG0_MMIO32_MAX)) {
> + Address += PCI_SEG0_MMIO_MEMBASE;
> + } else if ((Address >= PCI_SEG1_MMIO32_MIN) &&
> + (Address <= PCI_SEG1_MMIO32_MAX)) {
> + Address += PCI_SEG1_MMIO_MEMBASE;
> + } else if ((Address >= PCI_SEG2_MMIO32_MIN) &&
> + (Address <= PCI_SEG2_MMIO32_MAX)) {
> + Address += PCI_SEG2_MMIO_MEMBASE;
> + } else if ((Address >= PCI_SEG3_MMIO32_MIN) &&
> + (Address <= PCI_SEG3_MMIO32_MAX)) {
> + Address += PCI_SEG3_MMIO_MEMBASE;
> + } else {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Select loop based on the width of the transfer
> + //
> + InStride = mInStride[Width];
> + OutStride = mOutStride[Width];
> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
> + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
Could you move the Address and Uint8Buffer updates to the end of the
loop, in order to get the line length down?
> + if (OperationWidth == EfiCpuIoWidthUint8) {
> + *Uint8Buffer = MmioRead8 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
> + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
> + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
> + *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Writes memory-mapped registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[in] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuMemoryServiceWrite (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 InStride;
> + UINT8 OutStride;
> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
> + UINT8 *Uint8Buffer;
> +
> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if ((Address >= PCI_SEG0_MMIO32_MIN) &&
> + (Address <= PCI_SEG0_MMIO32_MAX)) {
> + Address += PCI_SEG0_MMIO_MEMBASE;
> + } else if ((Address >= PCI_SEG1_MMIO32_MIN) &&
> + (Address <= PCI_SEG1_MMIO32_MAX)) {
> + Address += PCI_SEG1_MMIO_MEMBASE;
> + } else if ((Address >= PCI_SEG2_MMIO32_MIN) &&
> + (Address <= PCI_SEG2_MMIO32_MAX)) {
> + Address += PCI_SEG2_MMIO_MEMBASE;
> + } else if ((Address >= PCI_SEG3_MMIO32_MIN) &&
> + (Address <= PCI_SEG3_MMIO32_MAX)) {
> + Address += PCI_SEG3_MMIO_MEMBASE;
> + } else {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
The block above looks identical with the previous function.
Break out as a separate helper function?
> +
> + //
> + // Select loop based on the width of the transfer
> + //
> + InStride = mInStride[Width];
> + OutStride = mOutStride[Width];
> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
> + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
Move Address/Uint8Buffer updates to end of loop?
(I think the use of Uint8Buffer is completely redundant here. Buffer
could be used directly.)
/
Leif
> + if (OperationWidth == EfiCpuIoWidthUint8) {
> + MmioWrite8 ((UINTN)Address, *Uint8Buffer);
> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
> + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
> + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
> + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Reads I/O registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[out] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuIoServiceRead (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Write I/O registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[in] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuIoServiceWrite (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +//
> +// CPU I/O 2 Protocol instance
> +//
> +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
> + {
> + CpuMemoryServiceRead,
> + CpuMemoryServiceWrite
> + },
> + {
> + CpuIoServiceRead,
> + CpuIoServiceWrite
> + }
> +};
> +
> +
> +/**
> + The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
> +
> + @param[in] ImageHandle The firmware allocated handle for the EFI image.
> + @param[in] SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The entry point is executed successfully.
> + @retval other Some error occurs when executing this entry point.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PciCpuIo2Initialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> +
> + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &mHandle,
> + &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
> + NULL
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> new file mode 100644
> index 0000000..25a1db1
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> @@ -0,0 +1,48 @@
> +## @file
> +# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PciCpuIo2Dxe
> + FILE_GUID = 7bff18d7-9aae-434b-9c06-f10a7e157eac
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PciCpuIo2Initialize
> +
> +[Sources]
> + PciCpuIo2Dxe.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + IoLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> +
> +[Protocols]
> + gEfiCpuIo2ProtocolGuid ## PRODUCES
> +
> +[Depex]
> + TRUE
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 35/39] Compilation: Update the fdf, dsc and dec files.
2018-02-16 8:50 ` [PATCH edk2-platforms 35/39] Compilation: Update the fdf, dsc and dec files Meenakshi
@ 2018-04-20 15:22 ` Leif Lindholm
2018-04-24 12:47 ` Vabhav Sharma
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-20 15:22 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Vabhav
On Fri, Feb 16, 2018 at 02:20:31PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> LS1043A PCIe compilation and update firmware device,
> description and declaration files.Defining Embedded Package
> PCD which should be at least 20 for 64K PCIe IO size required
> for CPU hob during PEI phase to Add IO space post PEI phase.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 16 ++++++++++++++++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 9 +++++++++
> .../LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++
> .../LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
> Platform/NXP/NxpQoriqLs.dsc | 7 +++++++
> Silicon/NXP/LS1043A/LS1043A.dsc | 4 ++++
> Silicon/NXP/NxpQoriqLs.dec | 10 ++++++++++
> 7 files changed, 54 insertions(+)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index b2b514e..8cbaf88 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -42,6 +42,8 @@
> BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
> FpgaLib|Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
> NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
> + PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> + PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>
> [PcdsFixedAtBuild.common]
>
> @@ -79,6 +81,13 @@
> gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000
> gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000
>
> + #
> + # PCI PCDs.
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x10000
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x7FC
> +
> ################################################################################
> #
> # Components Section - list of all EDK II Modules needed by this Platform
> @@ -99,4 +108,11 @@
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
>
> + Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
> + }
> + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> ##
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> index 6b5b63f..7993bf1 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> @@ -130,6 +130,13 @@ READ_LOCK_STATUS = TRUE
> INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
>
> #
> + # PCI
> + #
> + INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> + #
> # Network modules
> #
> INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> @@ -154,6 +161,8 @@ READ_LOCK_STATUS = TRUE
> INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> !endif
>
> + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
> +
I'm pretty OK with most of these random updates squashed into one
file, but the TftpDynamicCommand is something I generally don't like
to see included by default.
Other platforms put this inside a conditional statement:
!ifdef $(INCLUDE_TFTP_COMMAND)
INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
!endif
so that it can be included when -D INCLUDE_TFTP_COMMAND=1 is added to
the build command line.
But beyond that, there is no mention of this addition in the commit
message. So please add a notice, or break this specific item out as a
separate patch.
> #
> # FAT filesystem + GPT/MBR partitioning
> #
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> index 7feac56..f2c8b66 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> @@ -65,3 +65,5 @@
> gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> index 64c5612..1ef3292 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> @@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap (
> VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> + // ROM Space
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdRomBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> // IFC region 1
> //
> // A-009241 : Unaligned write transactions to IFC may result in corruption of data
> diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc
> index 5987cd6..f5bb2e9 100644
> --- a/Platform/NXP/NxpQoriqLs.dsc
> +++ b/Platform/NXP/NxpQoriqLs.dsc
> @@ -244,6 +244,8 @@
>
> gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
>
> + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|20
> +
> #
> # Optional feature to help prevent EFI memory map fragments
> # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
> @@ -409,4 +411,9 @@
> !endif #$(NO_SHELL_PROFILES)
> }
>
> + #
> + # TFTP Shell Command
> + #
> + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
> +
Same comment, conditional?
/
Leif
> ##
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc b/Silicon/NXP/LS1043A/LS1043A.dsc
> index a4eb117..f3220fa 100644
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc
> @@ -64,6 +64,9 @@
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3
> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
>
> #
> # Big Endian IPs
> @@ -71,5 +74,6 @@
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE
>
> ##
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 3cb476d..a3508b5 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -79,6 +79,16 @@
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129
> gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0|UINT64|0x0000012B
> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x0|UINT64|0x0000012C
> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x0|UINT64|0x0000012D
> +
> + #
> + # PCI PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x000001D0
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x000001D1
> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE|BOOLEAN|0x000001D2
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|0|UINT32|0x000001D3
>
> #
> # IFC PCDs
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 36/39] DWC3 : Add DWC3 USB controller initialization driver.
2018-02-16 8:50 ` [PATCH edk2-platforms 36/39] DWC3 : Add DWC3 USB controller initialization driver Meenakshi
@ 2018-04-20 15:30 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-20 15:30 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi
Minor comments below.
On Fri, Feb 16, 2018 at 02:20:32PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> Add support of DWC3 controller driver which
> Performs DWC3 controller initialization and
> Register itself as NonDiscoverableMmioDevice
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c | 219 +++++++++++++++++++++++++++
> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h | 142 +++++++++++++++++
> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf | 48 ++++++
> Silicon/NXP/NxpQoriqLs.dec | 5 +
> 4 files changed, 414 insertions(+)
> create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
> create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
> create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
>
> diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
> new file mode 100644
> index 0000000..b08e19c
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
> @@ -0,0 +1,219 @@
> +/** @file
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Bitops.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/NonDiscoverableDeviceRegistrationLib.h>
> +
> +#include "UsbHcd.h"
> +
> +STATIC
> +VOID
> +XhciSetBeatBurstLength (
> + IN UINTN UsbReg
> + )
> +{
> + Dwc3 *Dwc3Reg;
> +
> + Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET);
> +
> + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GSBusCfg0, ~USB3_ENABLE_BEAT_BURST_MASK,
> + USB3_ENABLE_BEAT_BURST);
> + MmioOr32 ((UINTN)&Dwc3Reg->GSBusCfg1, USB3_SET_BEAT_BURST_LIMIT);
> +
> + return;
> +}
> +
> +STATIC
> +VOID
> +Dwc3SetFladj (
> + IN Dwc3 *Dwc3Reg,
> + IN UINT32 Val
> + )
> +{
> + MmioOr32 ((UINTN)&Dwc3Reg->GFLAdj, GFLADJ_30MHZ_REG_SEL |
> + GFLADJ_30MHZ(Val));
> +}
> +
> +VOID
> +Dwc3SetMode (
> + IN Dwc3 *Dwc3Reg,
> + IN UINT32 Mode
> + )
> +{
> + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GCtl,
> + ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
> + DWC3_GCTL_PRTCAPDIR(Mode));
> +}
> +
> +STATIC
> +VOID
> +Dwc3CoreSoftReset (
> + IN Dwc3 *Dwc3Reg
> + )
> +{
> + MmioOr32 ((UINTN)&Dwc3Reg->GCtl, DWC3_GCTL_CORESOFTRESET);
> + MmioOr32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
> + MmioOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
> + MmioAnd32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], ~DWC3_GUSB3PIPECTL_PHYSOFTRST);
> + MmioAnd32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg, ~DWC3_GUSB2PHYCFG_PHYSOFTRST);
> + MmioAnd32 ((UINTN)&Dwc3Reg->GCtl, ~DWC3_GCTL_CORESOFTRESET);
> +
> + return;
> +}
> +
> +STATIC
> +EFI_STATUS
> +Dwc3CoreInit (
> + IN Dwc3 *Dwc3Reg
> + )
> +{
> + UINT32 Revision;
> + UINT32 Reg;
> + UINTN Dwc3Hwparams1;
> +
> + Revision = MmioRead32 ((UINTN)&Dwc3Reg->GSnpsId);
> + //
> + // This should read as 0x5533, ascii of U3(DWC_usb3) followed by revision number
> + //
> + if ((Revision & DWC3_GSNPSID_MASK) != DWC3_SYNOPSIS_ID) {
Should this be _SYNOPSYS_ rather than _SYNOPSIS_?
> + DEBUG ((DEBUG_ERROR,"This is not a DesignWare USB3 DRD Core.\n"));
> + return EFI_NOT_FOUND;
> + }
> +
> + Dwc3CoreSoftReset (Dwc3Reg);
> +
> + Reg = MmioRead32 ((UINTN)&Dwc3Reg->GCtl);
> + Reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
> + Reg &= ~DWC3_GCTL_DISSCRAMBLE;
> +
> + Dwc3Hwparams1 = MmioRead32 ((UINTN)&Dwc3Reg->GHwParams1);
> +
> + if (DWC3_GHWPARAMS1_EN_PWROPT(Dwc3Hwparams1) == DWC3_GHWPARAMS1_EN_PWROPT_CLK) {
> + Reg &= ~DWC3_GCTL_DSBLCLKGTNG;
> + } else {
> + DEBUG ((DEBUG_ERROR,"No power optimization available.\n"));
> + }
> +
> + if ((Revision & DWC3_RELEASE_MASK) < DWC3_RELEASE_190a) {
> + Reg |= DWC3_GCTL_U2RSTECN;
> + }
> +
> + MmioWrite32 ((UINTN)&Dwc3Reg->GCtl, Reg);
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +XhciCoreInit (
> + IN UINTN UsbReg
> + )
> +{
> + EFI_STATUS Status;
> + Dwc3 *Dwc3Reg;
> +
> + Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET);
> +
> + Status = Dwc3CoreInit (Dwc3Reg);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "Dwc3CoreInit Failed for controller 0x%x (0x%x) \n",
> + UsbReg, Status));
> + return Status;
> + }
> +
> + Dwc3SetMode (Dwc3Reg, DWC3_GCTL_PRTCAP_HOST);
> +
> + Dwc3SetFladj (Dwc3Reg, GFLADJ_30MHZ_DEFAULT);
> +
> + return Status;
> +}
> +
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +InitializeUsbController (
> + IN UINTN UsbReg
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = XhciCoreInit (UsbReg);
> +
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Change beat burst and outstanding pipelined transfers requests
> + //
> + XhciSetBeatBurstLength (UsbReg);
> +
> + return Status;
> +}
> +
> +/**
> + The Entry Point of module. It follows the standard UEFI driver model.
> +
> + @param[in] ImageHandle The firmware allocated handle for the EFI image.
> + @param[in] SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The entry point is executed successfully.
> + @retval other Some error occurs when executing this entry point.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeUsbHcd (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 NumUsbController;
> + UINT32 ControllerAddr;
> +
> + Status = EFI_SUCCESS;
> + NumUsbController = PcdGet32 (PcdNumUsbController);
> +
> + while (NumUsbController) {
> + NumUsbController--;
> + ControllerAddr = PcdGet32 (PcdUsbBaseAddr) +
> + (NumUsbController * PcdGet32 (PcdUsbSize));
> +
> + Status = InitializeUsbController (ControllerAddr);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "USB Controller initialization Failed for %d (0x%x)\n",
> + ControllerAddr, Status));
> + continue;
> + }
> +
> + Status = RegisterNonDiscoverableMmioDevice (
> + NonDiscoverableDeviceTypeXhci,
> + NonDiscoverableDeviceDmaTypeNonCoherent,
> + NULL,
> + NULL,
> + 1,
> + ControllerAddr, PcdGet32 (PcdUsbSize)
> + );
> +
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "Failed to register USB device (0x%x) with error 0x%x \n",
> + ControllerAddr, Status));
> + }
> + }
> +
> + return Status;
> +}
> diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
> new file mode 100644
> index 0000000..3237f5d
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
> @@ -0,0 +1,142 @@
> +/** @file
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __USB_HCD__
> +#define __USB_HCD__
> +
> +/* Global constants */
> +#define DWC3_GSNPSID_MASK 0xffff0000
> +#define DWC3_SYNOPSIS_ID 0x55330000
> +#define DWC3_RELEASE_MASK 0xffff
> +#define DWC3_REG_OFFSET 0xC100
> +#define DWC3_RELEASE_190a 0x190a
> +
> +/* Global Configuration Register */
> +#define DWC3_GCTL_U2RSTECN BIT(16)
> +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
> +#define DWC3_GCTL_PRTCAP_HOST 1
> +#define DWC3_GCTL_PRTCAP_OTG 3
> +#define DWC3_GCTL_CORESOFTRESET BIT(11)
> +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
> +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
> +#define DWC3_GCTL_DISSCRAMBLE BIT(3)
> +#define DWC3_GCTL_DSBLCLKGTNG BIT(0)
> +
> +/* Global HWPARAMS1 Register */
> +#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
> +#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
> +
> +/* Global USB2 PHY Configuration Register */
> +#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
> +
> +/* Global USB3 PIPE Control Register */
> +#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
> +
> +/* Global Frame Length Adjustment Register */
> +#define GFLADJ_30MHZ_REG_SEL BIT(7)
> +#define GFLADJ_30MHZ(n) ((n) & 0x3f)
> +#define GFLADJ_30MHZ_DEFAULT 0x20
> +
> +/* Default to the FSL XHCI defines */
> +#define USB3_ENABLE_BEAT_BURST 0xF
> +#define USB3_ENABLE_BEAT_BURST_MASK 0xFF
> +#define USB3_SET_BEAT_BURST_LIMIT 0xF00
> +
> +typedef struct {
> + UINT32 GEvntAdrLo;
> + UINT32 GEvntAdrHi;
> + UINT32 GEvntSiz;
> + UINT32 GEvntCount;
> +} GEventBuffer;
Generally, typedeffed structs are given
UPPERCASE_NAMES_WITH_UNDERSCORES in edk2.
(Applies throughout.)
> +
> +typedef struct {
> + UINT32 DDepCmdPar2;
> + UINT32 DDepCmdPar1;
> + UINT32 DDepCmdPar0;
> + UINT32 DDepCmd;
> +} DPhysicalEndpoint;
> +
> +typedef struct {
> + UINT32 GSBusCfg0;
> + UINT32 GSBusCfg1;
> + UINT32 GTxThrCfg;
> + UINT32 GRxThrCfg;
> + UINT32 GCtl;
> + UINT32 Res1;
> + UINT32 GSts;
> + UINT32 Res2;
> + UINT32 GSnpsId;
> + UINT32 GGpio;
> + UINT32 GUid;
> + UINT32 GUctl;
> + UINT64 GBusErrAddr;
> + UINT64 GPrtbImap;
> + UINT32 GHwParams0;
> + UINT32 GHwParams1;
> + UINT32 GHwParams2;
> + UINT32 GHwParams3;
> + UINT32 GHwParams4;
> + UINT32 GHwParams5;
> + UINT32 GHwParams6;
> + UINT32 GHwParams7;
> + UINT32 GDbgFifoSpace;
> + UINT32 GDbgLtssm;
> + UINT32 GDbgLnmcc;
> + UINT32 GDbgBmu;
> + UINT32 GDbgLspMux;
> + UINT32 GDbgLsp;
> + UINT32 GDbgEpInfo0;
> + UINT32 GDbgEpInfo1;
> + UINT64 GPrtbImapHs;
> + UINT64 GPrtbImapFs;
> + UINT32 Res3[28];
> + UINT32 GUsb2PhyCfg[16];
> + UINT32 GUsb2I2cCtl[16];
> + UINT32 GUsb2PhyAcc[16];
> + UINT32 GUsb3PipeCtl[16];
> + UINT32 GTxFifoSiz[32];
> + UINT32 GRxFifoSiz[32];
> + GEventBuffer GEvntBuf[32];
> + UINT32 GHwParams8;
> + UINT32 Res4[11];
> + UINT32 GFLAdj;
> + UINT32 Res5[51];
> + UINT32 DCfg;
> + UINT32 DCtl;
> + UINT32 DEvten;
> + UINT32 DSts;
> + UINT32 DGCmdPar;
> + UINT32 DGCmd;
> + UINT32 Res6[2];
> + UINT32 DAlepena;
> + UINT32 Res7[55];
> + DPhysicalEndpoint DPhyEpCmd[32];
> + UINT32 Res8[128];
> + UINT32 OCfg;
> + UINT32 OCtl;
> + UINT32 OEvt;
> + UINT32 OEvtEn;
> + UINT32 OSts;
> + UINT32 Res9[3];
> + UINT32 AdpCfg;
> + UINT32 AdpCtl;
> + UINT32 AdpEvt;
> + UINT32 AdpEvten;
> + UINT32 BcCfg;
> + UINT32 Res10;
> + UINT32 BcEvt;
> + UINT32 BcEvten;
> +} Dwc3;
> +
> +#endif
> diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
> new file mode 100644
> index 0000000..cefb8bd
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
> @@ -0,0 +1,48 @@
> +# UsbHcd.inf
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001000A
0x0001001a
/
Leif
> + BASE_NAME = UsbHcdDxe
> + FILE_GUID = 196e7c2a-37b2-4b85-8683-718588952449
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = InitializeUsbHcd
> +
> +[Sources.common]
> + UsbHcd.c
> +
> +[Packages]
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + DebugLib
> + IoLib
> + MemoryAllocationLib
> + NonDiscoverableDeviceRegistrationLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> +
> +[FixedPcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController
> + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize
> +
> +[Depex]
> + TRUE
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index a3508b5..90e9957 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -83,6 +83,11 @@
> gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x0|UINT64|0x0000012D
>
> #
> + # USB PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|0|UINT32|0x00000170
> +
> + #
> # PCI PCDs
> #
> gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x000001D0
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 37/39] LS2088 : Enable support of USB controller
2018-02-16 8:50 ` [PATCH edk2-platforms 37/39] LS2088 : Enable support of USB controller Meenakshi
@ 2018-04-20 15:30 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-20 15:30 UTC (permalink / raw)
To: Meenakshi
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Fri, Feb 16, 2018 at 02:20:33PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> Enable support of USB drives on ls2088 board.
> LS2088 has DWC3 controller
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 1 +
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 13 +++++++++++++
> Platform/NXP/NxpQoriqLs.dsc | 12 ++++++++++++
> Silicon/NXP/LS2088A/LS2088A.dsc | 1 +
> 4 files changed, 27 insertions(+)
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> index 60449b5..4d32ea5 100755
> --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> @@ -114,3 +114,4 @@
> ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> + Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> index 785f88b..8688d85 100644
> --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> @@ -151,6 +151,19 @@ READ_LOCK_STATUS = TRUE
> INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> !endif
>
> + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
> +
> + #
> + # USB Support
> + #
> + INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
> + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +
> + INF Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
> +
> #
> # FAT filesystem + GPT/MBR partitioning
> #
> diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc
> index f5bb2e9..18e8cde 100644
> --- a/Platform/NXP/NxpQoriqLs.dsc
> +++ b/Platform/NXP/NxpQoriqLs.dsc
> @@ -99,6 +99,7 @@
> VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
> NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
> CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
>
> [LibraryClasses.common.SEC]
> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> @@ -367,6 +368,17 @@
> !endif
>
> #
> + # USB Support
> + #
> + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
> + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +
> + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
> +
> + #
> # FAT filesystem + GPT/MBR partitioning
> #
> MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc b/Silicon/NXP/LS2088A/LS2088A.dsc
> index 2cff40f..0d8fd82 100644
> --- a/Silicon/NXP/LS2088A/LS2088A.dsc
> +++ b/Silicon/NXP/LS2088A/LS2088A.dsc
> @@ -68,5 +68,6 @@
> gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000
> + gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|2
>
> ##
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 38/39] Platform/NXP:PCIe enablement for LS1046A RDB
2018-02-16 8:50 ` [PATCH edk2-platforms 38/39] Platform/NXP:PCIe enablement for LS1046A RDB Meenakshi
@ 2018-04-20 15:33 ` Leif Lindholm
2018-04-24 12:48 ` Vabhav Sharma
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-20 15:33 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Vabhav
On Fri, Feb 16, 2018 at 02:20:34PM +0530, Meenakshi wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Compilation: Update the fdf, dsc and dec files.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> ---
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 15 +++++++++++++++
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 9 +++++++++
> .../LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++
> .../NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
> Silicon/NXP/LS1046A/LS1046A.dsc | 3 +++
> 5 files changed, 35 insertions(+)
>
> diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> index 36002d5..231207d 100644
> --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> @@ -41,6 +41,8 @@
> IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
> BoardLib|Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
> FpgaLib|Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
> + PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> + PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>
> [PcdsFixedAtBuild.common]
>
> @@ -65,6 +67,7 @@
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE
>
> #
> # I2C controller Pcds
> @@ -77,6 +80,12 @@
> gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51
> gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|100000
>
> + #
> + # PCI PCDs.
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x80000
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC
> ################################################################################
> #
> # Components Section - list of all EDK II Modules needed by this Platform
> @@ -90,5 +99,11 @@
>
> Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> + Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
> + }
> + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
>
> ##
> diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> index 834e3a4..3351a06 100644
> --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> @@ -123,6 +123,13 @@ READ_LOCK_STATUS = TRUE
> INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
>
> #
> + # PCI
> + #
> + INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> + #
> # Network modules
> #
> INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> @@ -147,6 +154,8 @@ READ_LOCK_STATUS = TRUE
> INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> !endif
>
> + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
> +
Same comment as for previous platform(s): please conditionalise and
mention in commit message.
/
Leif
> #
> # FAT filesystem + GPT/MBR partitioning
> #
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> index 49b57fc..5e09757 100644
> --- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> @@ -42,6 +42,8 @@
> gArmTokenSpaceGuid.PcdArmPrimaryCore
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> index 64c5612..1ef3292 100644
> --- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> @@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap (
> VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> + // ROM Space
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdRomBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> // IFC region 1
> //
> // A-009241 : Unaligned write transactions to IFC may result in corruption of data
> diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc b/Silicon/NXP/LS1046A/LS1046A.dsc
> index 9f87028..59a6150 100644
> --- a/Silicon/NXP/LS1046A/LS1046A.dsc
> +++ b/Silicon/NXP/LS1046A/LS1046A.dsc
> @@ -64,5 +64,8 @@
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3
> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
>
> ##
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 39/39] Platform/NXP:PCIe enablement for LS2088A RDB
2018-02-16 8:50 ` [PATCH edk2-platforms 39/39] Platform/NXP:PCIe enablement for LS2088A RDB Meenakshi
@ 2018-04-20 15:36 ` Leif Lindholm
2018-04-24 12:50 ` Vabhav Sharma
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-20 15:36 UTC (permalink / raw)
To: Meenakshi; +Cc: ard.biesheuvel, edk2-devel, udit.kumar, v.sethi, Vabhav
On Fri, Feb 16, 2018 at 02:20:35PM +0530, Meenakshi wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Compilation: Update the fdf, dsc and dec files.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> ---
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 17 +++++++++++++++++
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 9 +++++++++
> .../Library/PlatformLib/ArmPlatformLib.inf | 2 ++
> .../LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
> Silicon/NXP/LS2088A/LS2088A.dsc | 3 +++
> 5 files changed, 37 insertions(+)
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> index 4d32ea5..1ae55d4 100755
> --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> @@ -43,6 +43,8 @@
> BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
> FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
> NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
> + PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> + PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>
> [PcdsFixedAtBuild.common]
>
> @@ -97,6 +99,13 @@
> gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x580000000
> gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x580300000
>
> + #
> + # PCI PCDs.
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x80000
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC
> +
> ################################################################################
> #
> # Components Section - list of all EDK II Modules needed by this Platform
> @@ -115,3 +124,11 @@
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
> + Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
> + }
> + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> + ##
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> index 8688d85..35a79bd 100644
> --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> @@ -127,6 +127,13 @@ READ_LOCK_STATUS = TRUE
> INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
>
> #
> + # PCI
> + #
> + INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> + #
> # Network modules
> #
> INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> @@ -153,6 +160,8 @@ READ_LOCK_STATUS = TRUE
>
> INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
>
> + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
> +
Same comment as previously platforms: please conditionalise and
mention in commit message.
(Please add some detail to commit message in general about what is
being enabled.)
/
Leif
> #
> # USB Support
> #
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> index f5e5abd..0b836a8 100644
> --- a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> @@ -44,6 +44,8 @@
> gArmTokenSpaceGuid.PcdArmPrimaryCore
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> index ccb49f6..8b2145b 100644
> --- a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> @@ -80,6 +80,12 @@ ArmPlatformGetVirtualMemoryMap (
> VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> + // ROM Space
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdRomBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> // IFC region 1
> //
> // A-009241 : Unaligned write transactions to IFC may result in corruption of data
> diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc b/Silicon/NXP/LS2088A/LS2088A.dsc
> index 0d8fd82..831edea 100644
> --- a/Silicon/NXP/LS2088A/LS2088A.dsc
> +++ b/Silicon/NXP/LS2088A/LS2088A.dsc
> @@ -69,5 +69,8 @@
> gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000
> gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|2
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|4
> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
>
> ##
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (39 preceding siblings ...)
2018-04-17 16:44 ` [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Leif Lindholm
@ 2018-04-20 16:15 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
41 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-04-20 16:15 UTC (permalink / raw)
To: Meenakshi
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
Allright, that is all the feedback we have to give on this set.
Thank you for this contribution.
However, for such a large patch set, it would be very much appreciated
if you could put v2 on a publicly accessible git branch and include a
link in the cover letter.
Best Regards,
Leif
On Fri, Feb 16, 2018 at 02:19:56PM +0530, Meenakshi wrote:
> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> We have combined all patches which were sent earlier[in multiple patch sets]
> in one patch set incorporating review comments recieved till now.
> This will help in keeping track of patches.
>
> Following patches will add support of NXP SoCs[LS1043, LS1046 and LS2088] in edk2-platforms.
>
> Our directory structure will be:
>
> |-- Platform
> | |-- NXP
> | | |-- build.sh
> | | |-- Env.cshrc
> | | |-- FVRules.fdf.inc
> | | |-- LS1043aRdbPkg
> | | | |-- Include
> | | | | `-- Library
> | | | |-- Library
> | | | |-- LS1043aRdbPkg.dec
> | | | |-- LS1043aRdbPkg.dsc
> | | | |-- LS1043aRdbPkg.fdf
> | | | `-- VarStore.fdf.inc
> | | |-- LS1046aRdbPkg
> | | | |-- Include
> | | | | `-- Library
> | | | |-- Library
> | | | |-- LS1046aRdbPkg.dec
> | | | |-- LS1046aRdbPkg.dsc
> | | | `-- LS1046aRdbPkg.fdf
> | | |-- LS2088aRdbPkg
> | | | |-- Include
> | | | | `-- Library
> | | | |-- Library
> | | | |-- LS2088aRdbPkg.dec
> | | | |-- LS2088aRdbPkg.dsc
> | | | |-- LS2088aRdbPkg.fdf
> | | | `-- VarStore.fdf.inc
> | | |-- NxpQoriqLs.dsc
> | | `-- Readme.md
> |-- Silicon
> | |-- Maxim
> | | `-- Library
> | | |-- Ds1307RtcLib
> | | | |-- Ds1307RtcLib.dec
> | | `-- Ds3232RtcLib
> | | |-- Ds3232RtcLib.dec
> | |-- NXP
> | | |-- Chassis
> | | | |-- Chassis2
> | | | | |-- Chassis2.dec
> | | | |-- Chassis3
> | | | | |-- Chassis3.dec
> | | |-- Drivers
> | | |-- Include
> | | | |-- Library
> | | |-- Library
> | | |-- LS1043A
> | | | |-- Include
> | | | |-- LS1043A.dec
> | | | `-- LS1043A.dsc
> | | |-- LS1046A
> | | | |-- Include
> | | | |-- LS1046A.dec
> | | | `-- LS1046A.dsc
> | | |-- LS2088A
> | | | |-- Include
> | | | |-- LS2088A.dec
> | | | `-- LS2088A.dsc
> | | `-- NxpQoriqLs.dec
>
>
> In Silicon/NXP, we are keeping our SoC specific information and all Drivers and Library
> which are used by SoCs.
>
> Platform/NXP/ will host our board packages and build script.
>
> Board specific libraries and header files will reside inside board package.
>
> This patch add support of LS1043, LS1046 and LS2088 RDB boards.
>
>
> Looking forward for your kind support in upstreaming our boards in edk2-platforms.
>
>
> Meenakshi Aggarwal (23):
> Silicon/NXP: Add support for Big Endian Mmio APIs
> Silicon/NXP : Add support for Watchdog driver
> SocLib : Add support for initialization of peripherals
> Silicon/NXP : Add support for DUART library
> Silicon/NXP: Add support for I2c driver
> Silicon/Maxim : Add support for DS1307 RTC library
> Platform/NXP: Add support for ArmPlatformLib
> Compilation : Add the fdf, dsc and dec files.
> Build : Add build script and environment script
> IFC : Add Header file for IFC controller
> LS1043/BoardLib : Add support for LS1043 BoardLib.
> Silicon/NXP : Add support of IfcLib
> LS1043/FpgaLib : Add support for FpgaLib.
> LS1043 : Enable support of FpgaLib.
> Silicon/NXP : Add support of NorFlashLib
> Silicon/NXP : Add NOR driver.
> LS1043 : Enable NOR driver for LS1043aRDB package.
> Silicon/NXP:Add LS1046ARDB SoCLib Support
> Platform/NXP: LS1046A RDB Board Library
> Platform/NXP: LS1046 RDB Board FPGA library
> Compilation: Update the fdf, dsc and dec files.
> DWC3 : Add DWC3 USB controller initialization driver.
> LS2088 : Enable support of USB controller
>
> Vabhav (8):
> Silicon/NXP:Add support for PCF2129 Real Time Clock Library
> Platform/NXP: Add ArmPlatformLib for LS1046A
> Platform/NXP: Compilation for LS1046A RDB Board
> Silicon/NXP: Implement PciSegmentLib to support multiple RCs
> Silicon/NXP: Implement PciHostBridgeLib support
> Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
> Platform/NXP:PCIe enablement for LS1046A RDB
> Platform/NXP:PCIe enablement for LS2088A RDB
>
> Wasim Khan (8):
> Silicon/NXP:SocLib support for initialization of peripherals
> Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB
> Silicon/Maxim: DS3232 RTC Library Support
> Compilation : Add the fdf, dsc and dec files
> Platform/NXP: LS2088A RDB Board Library
> Platform/NXP: LS2088 RDB Board FPGA library
> LS2088 : Enable support of FpgaLib
> LS2088ARDB: Enable NOR driver and Runtime Services
>
> Platform/NXP/Env.cshrc | 78 ++
> Platform/NXP/FVRules.fdf.inc | 99 +++
> .../NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h | 109 +++
> .../NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h | 79 ++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 29 +
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 118 +++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 213 ++++++
> .../NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c | 69 ++
> .../LS1043aRdbPkg/Library/BoardLib/BoardLib.inf | 31 +
> .../NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c | 142 ++++
> .../NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 +
> .../Library/PlatformLib/ArmPlatformLib.c | 105 +++
> .../Library/PlatformLib/ArmPlatformLib.inf | 69 ++
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 38 +
> .../Library/PlatformLib/NxpQoriqLsMem.c | 158 ++++
> Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 98 +++
> .../NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h | 83 +++
> .../NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h | 97 +++
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec | 29 +
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 109 +++
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 206 ++++++
> .../NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c | 61 ++
> .../LS1046aRdbPkg/Library/BoardLib/BoardLib.inf | 31 +
> .../NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c | 144 ++++
> .../NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf | 32 +
> .../Library/PlatformLib/ArmPlatformLib.c | 105 +++
> .../Library/PlatformLib/ArmPlatformLib.inf | 68 ++
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 35 +
> .../Library/PlatformLib/NxpQoriqLsMem.c | 158 ++++
> .../NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h | 114 +++
> .../NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h | 166 +++++
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec | 29 +
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 134 ++++
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 224 ++++++
> .../NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c | 69 ++
> .../LS2088aRdbPkg/Library/BoardLib/BoardLib.inf | 28 +
> .../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c | 115 +++
> .../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 +
> .../Library/PlatformLib/ArmPlatformLib.c | 106 +++
> .../Library/PlatformLib/ArmPlatformLib.inf | 79 ++
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 35 +
> .../Library/PlatformLib/NxpQoriqLsMem.c | 195 +++++
> Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc | 99 +++
> Platform/NXP/NxpQoriqLs.dsc | 431 +++++++++++
> Platform/NXP/Readme.md | 17 +
> Platform/NXP/build.sh | 117 +++
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h | 59 ++
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 329 +++++++++
> .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec | 26 +
> .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf | 45 ++
> Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h | 49 ++
> Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c | 370 ++++++++++
> .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec | 31 +
> .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf | 49 ++
> Silicon/NXP/Chassis/Chassis.c | 424 +++++++++++
> Silicon/NXP/Chassis/Chassis.h | 162 +++++
> Silicon/NXP/Chassis/Chassis2/Chassis2.dec | 19 +
> Silicon/NXP/Chassis/Chassis2/SerDes.h | 68 ++
> Silicon/NXP/Chassis/Chassis2/Soc.c | 226 ++++++
> Silicon/NXP/Chassis/Chassis2/Soc.h | 367 ++++++++++
> Silicon/NXP/Chassis/Chassis3/Chassis3.dec | 19 +
> Silicon/NXP/Chassis/Chassis3/SerDes.h | 91 +++
> Silicon/NXP/Chassis/Chassis3/Soc.c | 196 +++++
> Silicon/NXP/Chassis/Chassis3/Soc.h | 149 ++++
> Silicon/NXP/Chassis/LS1043aSocLib.inf | 51 ++
> Silicon/NXP/Chassis/LS1046aSocLib.inf | 51 ++
> Silicon/NXP/Chassis/LS2088aSocLib.inf | 50 ++
> Silicon/NXP/Chassis/SerDes.c | 271 +++++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 726 +++++++++++++++++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 65 ++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 55 ++
> .../NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c | 258 +++++++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c | 438 +++++++++++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h | 146 ++++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf | 66 ++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c | 805 +++++++++++++++++++++
> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 529 ++++++++++++++
> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 ++
> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c | 219 ++++++
> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h | 142 ++++
> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf | 48 ++
> Silicon/NXP/Drivers/WatchDog/WatchDog.c | 459 ++++++++++++
> Silicon/NXP/Drivers/WatchDog/WatchDog.h | 39 +
> Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf | 47 ++
> Silicon/NXP/Include/Bitops.h | 179 +++++
> Silicon/NXP/Include/Ifc.h | 420 +++++++++++
> Silicon/NXP/Include/Library/BeIoLib.h | 332 +++++++++
> Silicon/NXP/Include/Library/IfcLib.h | 23 +
> Silicon/NXP/Include/Library/NorFlashLib.h | 77 ++
> Silicon/NXP/Include/NorFlash.h | 48 ++
> Silicon/NXP/Include/Pcie.h | 143 ++++
> Silicon/NXP/LS1043A/Include/SocSerDes.h | 55 ++
> Silicon/NXP/LS1043A/LS1043A.dec | 22 +
> Silicon/NXP/LS1043A/LS1043A.dsc | 79 ++
> Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 ++
> Silicon/NXP/LS1046A/LS1046A.dec | 22 +
> Silicon/NXP/LS1046A/LS1046A.dsc | 71 ++
> Silicon/NXP/LS2088A/Include/SocSerDes.h | 67 ++
> Silicon/NXP/LS2088A/LS2088A.dec | 22 +
> Silicon/NXP/LS2088A/LS2088A.dsc | 76 ++
> Silicon/NXP/Library/BeIoLib/BeIoLib.c | 400 ++++++++++
> Silicon/NXP/Library/BeIoLib/BeIoLib.inf | 31 +
> Silicon/NXP/Library/DUartPortLib/DUart.h | 128 ++++
> Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 370 ++++++++++
> Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 41 ++
> Silicon/NXP/Library/IfcLib/IfcLib.c | 155 ++++
> Silicon/NXP/Library/IfcLib/IfcLib.h | 184 +++++
> Silicon/NXP/Library/IfcLib/IfcLib.inf | 38 +
> Silicon/NXP/Library/NorFlashLib/CfiCommand.h | 99 +++
> Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c | 233 ++++++
> Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h | 68 ++
> Silicon/NXP/Library/NorFlashLib/NorFlashLib.c | 660 +++++++++++++++++
> Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf | 41 ++
> Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h | 43 ++
> Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c | 330 +++++++++
> .../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf | 47 ++
> .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 618 ++++++++++++++++
> .../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 50 ++
> Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 604 ++++++++++++++++
> .../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 41 ++
> Silicon/NXP/NxpQoriqLs.dec | 148 ++++
> 121 files changed, 17825 insertions(+)
> create mode 100755 Platform/NXP/Env.cshrc
> create mode 100644 Platform/NXP/FVRules.fdf.inc
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/Library/FpgaLib.h
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
> create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
> create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
> create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
> create mode 100755 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
> create mode 100644 Platform/NXP/NxpQoriqLs.dsc
> create mode 100644 Platform/NXP/Readme.md
> create mode 100755 Platform/NXP/build.sh
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> create mode 100644 Silicon/NXP/Chassis/Chassis.c
> create mode 100644 Silicon/NXP/Chassis/Chassis.h
> create mode 100644 Silicon/NXP/Chassis/Chassis2/Chassis2.dec
> create mode 100644 Silicon/NXP/Chassis/Chassis2/SerDes.h
> create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.c
> create mode 100644 Silicon/NXP/Chassis/Chassis2/Soc.h
> create mode 100644 Silicon/NXP/Chassis/Chassis3/Chassis3.dec
> create mode 100644 Silicon/NXP/Chassis/Chassis3/SerDes.h
> create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.c
> create mode 100644 Silicon/NXP/Chassis/Chassis3/Soc.h
> create mode 100644 Silicon/NXP/Chassis/LS1043aSocLib.inf
> create mode 100644 Silicon/NXP/Chassis/LS1046aSocLib.inf
> create mode 100644 Silicon/NXP/Chassis/LS2088aSocLib.inf
> create mode 100644 Silicon/NXP/Chassis/SerDes.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c
> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
> create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
> create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> create mode 100644 Silicon/NXP/Include/Bitops.h
> create mode 100644 Silicon/NXP/Include/Ifc.h
> create mode 100644 Silicon/NXP/Include/Library/BeIoLib.h
> create mode 100644 Silicon/NXP/Include/Library/IfcLib.h
> create mode 100644 Silicon/NXP/Include/Library/NorFlashLib.h
> create mode 100644 Silicon/NXP/Include/NorFlash.h
> create mode 100644 Silicon/NXP/Include/Pcie.h
> create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
> create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc
> create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
> create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc
> create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/LS2088A/LS2088A.dec
> create mode 100644 Silicon/NXP/LS2088A/LS2088A.dsc
> create mode 100644 Silicon/NXP/Library/BeIoLib/BeIoLib.c
> create mode 100644 Silicon/NXP/Library/BeIoLib/BeIoLib.inf
> create mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
> create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.c
> create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.h
> create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.inf
> create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiCommand.h
> create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
> create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
> create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
> create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
> create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
> create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> create mode 100644 Silicon/NXP/NxpQoriqLs.dec
>
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver
2018-04-17 16:36 ` Leif Lindholm
@ 2018-04-23 8:21 ` Meenakshi Aggarwal
2018-04-23 8:38 ` Leif Lindholm
0 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-04-23 8:21 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Tuesday, April 17, 2018 10:07 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c
> driver
>
> On Fri, Feb 16, 2018 at 02:20:01PM +0530, Meenakshi wrote:
> > From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> >
> > I2C driver produces gEfiI2cMasterProtocolGuid which can be
> > used by other modules.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> > ---
> > Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 726
> ++++++++++++++++++++++++++++++++++
> > Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 65 +++
> > Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 55 +++
> > 3 files changed, 846 insertions(+)
> > create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> >
> > diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > new file mode 100644
> > index 0000000..80a8826
> > --- /dev/null
> > +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> > @@ -0,0 +1,726 @@
> > +/** I2cDxe.c
> > + I2c driver APIs for read, write, initialize, set speed and reset
> > +
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials
> > + are licensed and made available under the terms and conditions of the
> BSD License
> > + which accompanies this distribution. The full text of the license may be
> found at
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cf09845
> 08e3e6425a971708d5a48171ca%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636595798265709617&sdata=lqPp%2BaHIRYNO%2B9buGRqcgvffpW
> nWzpIEpeLwdxPhZAk%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#include <Library/DebugLib.h>
> > +#include <Library/IoLib.h>
> > +#include <Library/TimerLib.h>
> > +#include <Library/UefiBootServicesTableLib.h>
> > +#include <Library/UefiLib.h>
> > +
> > +#include <Protocol/I2cMaster.h>
> > +
> > +#include "I2cDxe.h"
> > +
> > +STATIC CONST UINT16 ClkDiv[60][2] = {
> > + { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
> > + { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
> > + { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
> > + { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
> > + { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
> > + { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
> > + { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
> > + { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
> > + { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
> > + { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
> > + { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
> > + { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 },{ 1280, 0x35 },
> > + { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
> > + { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
> > + { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
> > +};
> > +
> > +/**
> > + Calculate and return proper clock divider
> > +
> > + @param Rate clock rate
> > +
> > + @retval ClkDiv Value used to get frequency divider value
> > +
> > +**/
> > +STATIC
> > +UINT8
> > +GetClkDiv (
> > + IN UINT32 Rate
> > + )
> > +{
> > + UINTN ClkRate;
> > + UINT32 Div;
> > + UINT8 ClkDivx;
> > +
> > + ClkRate = GetBusFrequency ();
> > +
> > + Div = (ClkRate + Rate - 1) / Rate;
> > +
> > + if (Div < ClkDiv[0][0]) {
> > + ClkDivx = 0;
> > + } else if (Div > ClkDiv[ARRAY_SIZE (ClkDiv) - 1][0]){
> > + ClkDivx = ARRAY_SIZE (ClkDiv) - 1;
> > + } else {
> > + for (ClkDivx = 0; ClkDiv[ClkDivx][0] < Div; ClkDivx++);
> > + }
> > +
> > + return ClkDivx;
> > +}
> > +
> > +/**
> > + Function used to check if i2c is in mentioned state or not
> > +
> > + @param I2cRegs Pointer to I2C registers
> > + @param State i2c state need to be checked
> > +
> > + @retval EFI_NOT_READY Arbitration was lost
> > + @retval EFI_TIMEOUT Timeout occured
> > + @retval CurrState Value of state register
> > +
> > +**/
> > +STATIC
> > +EFI_STATUS
> > +WaitForI2cState (
> > + IN I2C_REGS *I2cRegs,
> > + IN UINT32 State
> > + )
> > +{
> > + UINT8 CurrState;
> > + UINT64 Cnt;
> > +
> > + for (Cnt = 0; Cnt < 50000; Cnt++) {
> > + MemoryFence ();
> > + CurrState = MmioRead8 ((UINTN)&I2cRegs->I2cSr);
> > + if (CurrState & I2C_SR_IAL) {
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, CurrState | I2C_SR_IAL);
> > + return EFI_NOT_READY;
> > + }
> > +
> > + if ((CurrState & (State >> 8)) == (UINT8)State) {
> > + return CurrState;
> > + }
> > + }
> > +
> > + return EFI_TIMEOUT;
> > +}
> > +
> > +/**
> > + Function to transfer byte on i2c
> > +
> > + @param I2cRegs Pointer to i2c registers
> > + @param Byte Byte to be transferred on i2c bus
> > +
> > + @retval EFI_NOT_READY Arbitration was lost
> > + @retval EFI_TIMEOUT Timeout occured
> > + @retval EFI_NOT_FOUND ACK was not recieved
> > + @retval EFI_SUCCESS Data transfer was succesful
> > +
> > +**/
> > +STATIC
> > +EFI_STATUS
> > +TransferByte (
> > + IN I2C_REGS *I2cRegs,
> > + IN UINT8 Byte
> > + )
> > +{
> > + EFI_STATUS Ret;
> > +
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cDr, Byte);
> > +
> > + Ret = WaitForI2cState (I2cRegs, IIF);
> > + if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
> > + return Ret;
> > + }
> > +
> > + if (Ret & I2C_SR_RX_NO_AK) {
> > + return EFI_NOT_FOUND;
> > + }
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +/**
> > + Function to stop transaction on i2c bus
> > +
> > + @param I2cRegs Pointer to i2c registers
> > +
> > + @retval EFI_NOT_READY Arbitration was lost
> > + @retval EFI_TIMEOUT Timeout occured
> > + @retval EFI_SUCCESS Stop operation was successful
> > +
> > +**/
> > +STATIC
> > +EFI_STATUS
> > +I2cStop (
> > + IN I2C_REGS *I2cRegs
> > + )
> > +{
> > + INT32 Ret;
> > + UINT32 Temp;
> > +
> > + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> > +
> > + Temp &= ~(I2C_CR_MSTA | I2C_CR_MTX);
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> > +
> > + Ret = WaitForI2cState (I2cRegs, BUS_IDLE);
> > +
> > + if (Ret < 0) {
> > + return Ret;
> > + } else {
> > + return EFI_SUCCESS;
> > + }
> > +}
> > +
> > +/**
> > + Function to send start signal, Chip Address and
> > + memory offset
> > +
> > + @param I2cRegs Pointer to i2c base registers
> > + @param Chip Chip Address
> > + @param Offset Slave memory's offset
> > + @param Alen length of chip address
> > +
> > + @retval EFI_NOT_READY Arbitration lost
> > + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined
> time
> > + @retval EFI_NOT_FOUND ACK was not recieved
> > + @retval EFI_SUCCESS Read was successful
> > +
> > +**/
> > +STATIC
> > +EFI_STATUS
> > +InitTransfer (
> > + IN I2C_REGS *I2cRegs,
> > + IN UINT8 Chip,
> > + IN UINT32 Offset,
> > + IN INT32 Alen
> > + )
> > +{
> > + UINT32 Temp;
> > + EFI_STATUS Ret;
> > +
> > + // Enable I2C controller
> > + if (MmioRead8 ((UINTN)&I2cRegs->I2cCr) & I2C_CR_IDIS) {
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IEN);
> > + }
> > +
> > + if (MmioRead8 ((UINTN)&I2cRegs->I2cAdr) == (Chip << 1)) {
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cAdr, (Chip << 1) ^ 2);
> > + }
> > +
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> > + Ret = WaitForI2cState (I2cRegs, BUS_IDLE);
> > + if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
> > + return Ret;
> > + }
> > +
> > + // Start I2C transaction
> > + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> > + // set to master mode
> > + Temp |= I2C_CR_MSTA;
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> > +
> > + Ret = WaitForI2cState (I2cRegs, BUS_BUSY);
> > + if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
> > + return Ret;
> > + }
> > +
> > + Temp |= I2C_CR_MTX | I2C_CR_TX_NO_AK;
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> > +
> > + // write slave Address
> > + Ret = TransferByte (I2cRegs, Chip << 1);
> > + if (Ret != EFI_SUCCESS) {
> > + return Ret;
> > + }
> > +
> > + if (Alen >= 0) {
> > + while (Alen--) {
> > + Ret = TransferByte (I2cRegs, (Offset >> (Alen * 8)) & 0xff);
> > + if (Ret != EFI_SUCCESS)
> > + return Ret;
> > + }
> > + }
> > + return EFI_SUCCESS;
> > +}
> > +
> > +/**
> > + Function to check if i2c bus is idle
> > +
> > + @param Base Pointer to base address of I2c controller
> > +
> > + @retval EFI_SUCCESS
> > +
> > +**/
> > +STATIC
> > +INT32
> > +I2cBusIdle (
> > + IN VOID *Base
> > + )
> > +{
> > + return EFI_SUCCESS;
> > +}
> > +
> > +/**
> > + Function to initiate data transfer on i2c bus
> > +
> > + @param I2cRegs Pointer to i2c base registers
> > + @param Chip Chip Address
> > + @param Offset Slave memory's offset
> > + @param Alen length of chip address
> > +
> > + @retval EFI_NOT_READY Arbitration lost
> > + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined
> time
> > + @retval EFI_NOT_FOUND ACK was not recieved
> > + @retval EFI_SUCCESS Read was successful
> > +
> > +**/
> > +STATIC
> > +EFI_STATUS
> > +InitDataTransfer (
> > + IN I2C_REGS *I2cRegs,
> > + IN UINT8 Chip,
> > + IN UINT32 Offset,
> > + IN INT32 Alen
> > + )
> > +{
> > + EFI_STATUS Status;
> > + INT32 Retry;
> > +
> > + for (Retry = 0; Retry < 3; Retry++) {
> > + Status = InitTransfer (I2cRegs, Chip, Offset, Alen);
> > + if (Status == EFI_SUCCESS) {
> > + return EFI_SUCCESS;
> > + }
> > +
> > + I2cStop (I2cRegs);
> > +
> > + if (EFI_NOT_FOUND == Status) {
> > + return Status;
> > + }
> > +
> > + // Disable controller
> > + if (Status != EFI_NOT_READY) {
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
> > + }
> > +
> > + if (I2cBusIdle (I2cRegs) < 0) {
> > + break;
> > + }
> > + }
> > + return Status;
> > +}
> > +
> > +/**
> > + Function to read data using i2c bus
> > +
> > + @param I2cBus I2c Controller number
> > + @param Chip Address of slave device from where data to be read
> > + @param Offset Offset of slave memory
> > + @param Alen Address length of slave
> > + @param Buffer A pointer to the destination buffer for the data
> > + @param Len Length of data to be read
> > +
> > + @retval EFI_NOT_READY Arbitration lost
> > + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined
> time
> > + @retval EFI_NOT_FOUND ACK was not recieved
> > + @retval EFI_SUCCESS Read was successful
> > +
> > +**/
> > +STATIC
> > +EFI_STATUS
> > +I2cDataRead (
> > + IN UINT32 I2cBus,
> > + IN UINT8 Chip,
> > + IN UINT32 Offset,
> > + IN UINT32 Alen,
> > + IN UINT8 *Buffer,
> > + IN UINT32 Len
> > + )
> > +{
> > + EFI_STATUS Status;
> > + UINT32 Temp;
> > + INT32 I;
> > + I2C_REGS *I2cRegs;
> > +
> > + I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
> > + (I2cBus * FixedPcdGet32 (PcdI2cSize))));
>
> Please get rid of this hardcoded base address and use NonDiscoverable
> Have a look at Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/ and
> Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/
> for example.
>
I have checked SynQuacer code and i dont see its adding much advantage.
There also base address is hard coded SYNQUACER_I2C1_BASE in PlatformDxe driver.
What we can do is, instead of using pcds here, we can define address in nxp's i2c struct itself
and use from there.
> > +
> > + Status = InitDataTransfer (I2cRegs, Chip, Offset, Alen);
> > + if (Status != EFI_SUCCESS) {
> > + return Status;
> > + }
> > +
> > + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> > + Temp |= I2C_CR_RSTA;
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> > +
> > + Status = TransferByte (I2cRegs, (Chip << 1) | 1);
> > + if (Status != EFI_SUCCESS) {
> > + I2cStop (I2cRegs);
> > + return Status;
> > + }
> > +
> > + // setup bus to read data
> > + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> > + Temp &= ~(I2C_CR_MTX | I2C_CR_TX_NO_AK);
> > + if (Len == 1) {
> > + Temp |= I2C_CR_TX_NO_AK;
> > + }
> > +
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> > +
> > + // Dummy Read to initiate recieve operation
> > + MmioRead8 ((UINTN)&I2cRegs->I2cDr);
> > +
> > + for (I = 0; I < Len; I++) {
> > + Status = WaitForI2cState (I2cRegs, IIF);
> > + if ((Status == EFI_TIMEOUT) || (Status == EFI_NOT_READY)) {
> > + I2cStop (I2cRegs);
> > + return Status;
> > + }
> > + //
> > + // It must generate STOP before read I2DR to prevent
> > + // controller from generating another clock cycle
> > + //
> > + if (I == (Len - 1)) {
> > + I2cStop (I2cRegs);
> > + } else if (I == (Len - 2)) {
> > + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> > + Temp |= I2C_CR_TX_NO_AK;
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> > + }
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> > + Buffer[I] = MmioRead8 ((UINTN)&I2cRegs->I2cDr);
> > + }
> > +
> > + I2cStop (I2cRegs);
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +/**
> > + Function to write data using i2c bus
> > +
> > + @param I2cBus I2c Controller number
> > + @param Chip Address of slave device where data to be written
> > + @param Offset Offset of slave memory
> > + @param Alen Address length of slave
> > + @param Buffer A pointer to the source buffer for the data
> > + @param Len Length of data to be write
> > +
> > + @retval EFI_NOT_READY Arbitration lost
> > + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined
> time
> > + @retval EFI_NOT_FOUND ACK was not recieved
> > + @retval EFI_SUCCESS Read was successful
> > +
> > +**/
> > +STATIC
> > +EFI_STATUS
> > +I2cDataWrite (
> > + IN UINT32 I2cBus,
> > + IN UINT8 Chip,
> > + IN UINT32 Offset,
> > + IN INT32 Alen,
> > + OUT UINT8 *Buffer,
> > + IN INT32 Len
> > + )
> > +{
> > + EFI_STATUS Status;
> > + I2C_REGS *I2cRegs;
> > + INT32 I;
> > +
> > + I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
> > + (I2cBus * FixedPcdGet32 (PcdI2cSize))));
> > +
> > + Status = InitDataTransfer (I2cRegs, Chip, Offset, Alen);
> > + if (Status != EFI_SUCCESS) {
> > + return Status;
> > + }
> > +
> > + // Write operation
> > + for (I = 0; I < Len; I++) {
> > + Status = TransferByte (I2cRegs, Buffer[I]);
> > + if (Status != EFI_SUCCESS) {
> > + break;
> > + }
> > + }
> > +
> > + I2cStop (I2cRegs);
> > + return Status;
> > +}
> > +
> > +/**
> > + Function to set i2c bus frequency
> > +
> > + @param This Pointer to I2c master protocol
> > + @param BusClockHertz value to be set
> > +
> > + @retval EFI_SUCCESS Operation successfull
> > +**/
> > +
> > +EFI_STATUS
> > +EFIAPI
> > +SetBusFrequency (
> > + IN CONST EFI_I2C_MASTER_PROTOCOL *This,
> > + IN OUT UINTN *BusClockHertz
> > + )
> > +{
> > + I2C_REGS *I2cRegs;
> > + UINT8 ClkId;
> > + UINT8 SpeedId;
> > +
> > + I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
> > + (PcdGet32 (PcdI2cBus) * FixedPcdGet32 (PcdI2cSize))));
> > +
> > + ClkId = GetClkDiv (*BusClockHertz);
> > + SpeedId = ClkDiv[ClkId][1];
> > +
> > + // Store divider value
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cFdr, SpeedId);
> > +
> > + MemoryFence ();
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +/**
> > + Function to reset I2c Controller
> > +
> > + @param This Pointer to I2c master protocol
> > +
> > + @return EFI_SUCCESS Operation successfull
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +Reset (
> > + IN CONST EFI_I2C_MASTER_PROTOCOL *This
> > + )
> > +{
> > + I2C_REGS *I2cRegs;
> > +
> > + I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
> > + (PcdGet32 (PcdI2cBus) * FixedPcdGet32 (PcdI2cSize))));
> > +
> > + // Reset module
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
> > + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, 0);
> > +
> > + MemoryFence ();
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +EFI_STATUS
> > +EFIAPI
> > +StartRequest (
> > + IN CONST EFI_I2C_MASTER_PROTOCOL *This,
> > + IN UINTN SlaveAddress,
> > + IN EFI_I2C_REQUEST_PACKET *RequestPacket,
> > + IN EFI_EVENT Event OPTIONAL,
> > + OUT EFI_STATUS *I2cStatus OPTIONAL
> > + )
> > +{
> > + UINT32 Count;
> > + INT32 Ret;
> > + UINT32 Length;
> > + UINT8 *Buffer;
> > + UINT32 Flag;
> > + UINT32 RegAddress;
> > + UINT32 OffsetLength;
> > +
> > + RegAddress = 0;
> > +
> > + if (RequestPacket->OperationCount <= 0) {
> > + DEBUG ((DEBUG_ERROR,"%a: Operation count is not valid %d\n",
> > + __FUNCTION__, RequestPacket->OperationCount));
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + OffsetLength = RequestPacket->Operation[0].LengthInBytes;
> > + RegAddress = *RequestPacket->Operation[0].Buffer;
> > +
> > + for (Count = 1; Count < RequestPacket->OperationCount; Count++) {
> > + Flag = RequestPacket->Operation[Count].Flags;
> > + Length = RequestPacket->Operation[Count].LengthInBytes;
> > + Buffer = RequestPacket->Operation[Count].Buffer;
> > +
> > + if (Length <= 0) {
> > + DEBUG ((DEBUG_ERROR,"%a: Invalid length of buffer %d\n",
> > + __FUNCTION__, Length));
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + if (Flag == I2C_FLAG_READ) {
> > + Ret = I2cDataRead (PcdGet32 (PcdI2cBus), SlaveAddress,
> > + RegAddress, OffsetLength, Buffer, Length);
> > + if (Ret != EFI_SUCCESS) {
> > + DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n",
> > + __FUNCTION__, Ret));
> > + return Ret;
> > + }
> > + } else if (Flag == I2C_FLAG_WRITE) {
> > + Ret = I2cDataWrite (PcdGet32 (PcdI2cBus), SlaveAddress,
> > + RegAddress, OffsetLength, Buffer, Length);
> > + if (Ret != EFI_SUCCESS) {
> > + DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n",
> > + __FUNCTION__, Ret));
> > + return Ret;
> > + }
> > + } else {
> > + DEBUG ((DEBUG_ERROR,"%a: Invalid Flag %d\n",
> > + __FUNCTION__, Flag));
> > + return EFI_INVALID_PARAMETER;
> > + }
> > + }
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +CONST EFI_I2C_CONTROLLER_CAPABILITIES I2cControllerCapabilities = {
> > + 0,
> > + 0,
> > + 0,
> > + 0
> > +};
> > +
> > +STATIC EFI_I2C_MASTER_PROTOCOL gI2c = {
> > + ///
> > + /// Set the clock frequency for the I2C bus.
> > + ///
> > + SetBusFrequency,
> > + ///
> > + /// Reset the I2C host controller.
> > + ///
> > + Reset,
> > + ///
> > + /// Start an I2C transaction in master mode on the host controller.
> > + ///
> > + StartRequest,
> > + ///
> > + /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure
> containing
> > + /// the capabilities of the I2C host controller.
> > + ///
> > + &I2cControllerCapabilities
> > +};
> > +
> > +STATIC I2C_DEVICE_PATH gDevicePath = {
> > + {
> > + {
> > + HARDWARE_DEVICE_PATH, HW_VENDOR_DP,
> > + {
> > + sizeof (VENDOR_DEVICE_PATH), 0
> > + }
> > + },
> > + EFI_CALLER_ID_GUID
> > + },
> > + {
> > + END_DEVICE_PATH_TYPE,
> > + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> > + {
> > + sizeof (EFI_DEVICE_PATH_PROTOCOL), 0
> > + }
> > + }
> > +};
> > +
> > +/**
> > + The Entry Point for I2C driver.
> > +
> > + @param[in] ImageHandle The firmware allocated handle for the EFI
> image.
> > + @param[in] SystemTable A pointer to the EFI System Table.
> > +
> > + @retval EFI_SUCCESS The entry point is executed successfully.
> > + @retval other Some error occurs when executing this entry point.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +I2cDxeEntryPoint (
> > + IN EFI_HANDLE ImageHandle,
> > + IN EFI_SYSTEM_TABLE *SystemTable
> > + )
> > +{
> > + EFI_STATUS Status;
> > +
> > + //
> > + // Install I2c Master protocol on this controller
> > + //
> > + Status = gBS->InstallMultipleProtocolInterfaces (
> > + &ImageHandle,
>
> Indentation - + 2 spaces.
>
> > + &gEfiI2cMasterProtocolGuid,
> > + (VOID**)&gI2c,
> > + &gEfiDevicePathProtocolGuid,
> > + &gDevicePath,
> > + NULL
> > + );
> > +
> > + ASSERT_EFI_ERROR (Status);
> > +
> > + return Status;
> > +}
> > +
> > +/**
> > + Unload function for the I2c Driver.
> > +
> > + @param ImageHandle[in] The allocated handle for the EFI image
> > +
> > + @retval EFI_SUCCESS The driver was unloaded successfully
> > + @retval EFI_INVALID_PARAMETER ImageHandle is not a valid image
> handle.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +I2cDxeUnload (
> > + IN EFI_HANDLE ImageHandle
> > + )
> > +{
> > + EFI_STATUS Status;
> > + EFI_HANDLE *HandleBuffer;
> > + UINTN HandleCount;
> > + UINTN Index;
> > +
> > + //
> > + // Retrieve all I2c handles in the handle database
> > + //
> > + Status = gBS->LocateHandleBuffer (ByProtocol,
> > + &gEfiI2cMasterProtocolGuid,
> > + NULL,
> > + &HandleCount,
> > + &HandleBuffer);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > +
> > + //
> > + // Disconnect the driver from the handles in the handle database
> > + //
> > + for (Index = 0; Index < HandleCount; Index++) {
> > + Status = gBS->DisconnectController (HandleBuffer[Index],
> > + gImageHandle,
> > + NULL);
> > + }
> > +
> > + //
> > + // Free the handle array
> > + //
> > + gBS->FreePool (HandleBuffer);
> > +
> > + //
> > + // Uninstall protocols installed by the driver in its entrypoint
> > + //
> > + Status = gBS->UninstallMultipleProtocolInterfaces (ImageHandle,
> > + &gEfiI2cMasterProtocolGuid, &gI2c,
> > + &gEfiDevicePathProtocolGuid, &gDevicePath,
> > + NULL);
> > +
> > + return Status;
> > +}
> > diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > new file mode 100644
> > index 0000000..4a562d3
> > --- /dev/null
> > +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> > @@ -0,0 +1,65 @@
> > +/** I2cDxe.h
> > + Header defining the constant, base address amd function for I2C
> controller
> > +
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials
> > + are licensed and made available under the terms and conditions of the
> BSD License
> > + which accompanies this distribution. The full text of the license may be
> found at
> > +
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cf09845
> 08e3e6425a971708d5a48171ca%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636595798265709617&sdata=lqPp%2BaHIRYNO%2B9buGRqcgvffpW
> nWzpIEpeLwdxPhZAk%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#ifndef __I2C_DXE_H___
>
> Typo in include guard, making it not a guard. (Extra '_'.)
>
> > +#define __I2C_DXE_H__
> > +
> > +#include <Uefi.h>
> > +
> > +#define I2C_CR_IIEN (1 << 6)
> > +#define I2C_CR_MSTA (1 << 5)
> > +#define I2C_CR_MTX (1 << 4)
> > +#define I2C_CR_TX_NO_AK (1 << 3)
> > +#define I2C_CR_RSTA (1 << 2)
> > +
> > +#define I2C_SR_ICF (1 << 7)
> > +#define I2C_SR_IBB (1 << 5)
> > +#define I2C_SR_IAL (1 << 4)
> > +#define I2C_SR_IIF (1 << 1)
> > +#define I2C_SR_RX_NO_AK (1 << 0)
> > +
> > +#define I2C_CR_IEN (0 << 7)
> > +#define I2C_CR_IDIS (1 << 7)
> > +#define I2C_SR_IIF_CLEAR (1 << 1)
> > +
> > +#define BUS_IDLE (0 | (I2C_SR_IBB << 8))
> > +#define BUS_BUSY (I2C_SR_IBB | (I2C_SR_IBB << 8))
> > +#define IIF (I2C_SR_IIF | (I2C_SR_IIF << 8))
> > +
> > +#define I2C_FLAG_WRITE 0x0
> > +
> > +typedef struct {
> > + VENDOR_DEVICE_PATH Guid;
> > + EFI_DEVICE_PATH_PROTOCOL End;
> > +} I2C_DEVICE_PATH;
> > +
> > +/**
> > + Record defining i2c registers
> > +**/
> > +typedef struct {
> > + UINT8 I2cAdr;
> > + UINT8 I2cFdr;
> > + UINT8 I2cCr;
> > + UINT8 I2cSr;
> > + UINT8 I2cDr;
> > +} I2C_REGS ;
> > +
> > +extern
> > +UINT64
> > +GetBusFrequency (
> > + VOID
> > + );
> > +
> > +#endif
> > diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> > new file mode 100644
> > index 0000000..ceb1b11
> > --- /dev/null
> > +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> > @@ -0,0 +1,55 @@
> > +# @file
> > +#
> > +# Component description file for I2c driver
> > +#
> > +# Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
> > +# Copyright 2017 NXP
> > +#
> > +# This program and the accompanying materials
> > +# are licensed and made available under the terms and conditions of the
> BSD License
> > +# which accompanies this distribution. The full text of the license may be
> found at
> > +#
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cf09845
> 08e3e6425a971708d5a48171ca%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0
> %7C0%7C636595798265709617&sdata=lqPp%2BaHIRYNO%2B9buGRqcgvffpW
> nWzpIEpeLwdxPhZAk%3D&reserved=0
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +#
> > +#
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001A
> > + BASE_NAME = I2cDxe
> > + FILE_GUID = 5f2927ba-1b04-4d5f-8bef-2b50c635d1e7
> > + MODULE_TYPE = DXE_DRIVER
> > + VERSION_STRING = 1.0
> > + ENTRY_POINT = I2cDxeEntryPoint
> > + UNLOAD = I2cDxeUnload
> > +
> > +[Sources.common]
> > + I2cDxe.c
> > +
> > +[LibraryClasses]
> > + ArmLib
> > + IoLib
> > + MemoryAllocationLib
> > + PcdLib
> > + SocLib
> > + TimerLib
> > + UefiDriverEntryPoint
> > + UefiLib
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > + Silicon/NXP/NxpQoriqLs.dec
> > +
> > +[Protocols]
> > + gEfiI2cMasterProtocolGuid
> > +
> > +[Pcd]
> > + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus
> > + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
> > + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> > + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> > + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
> > +
> > +[Depex]
> > + TRUE
>
> Migrating to NonDiscoverableDeviceRegistrationLib should also let you
> get rid of this hardcoded depex.
>
> /
> Leif
>
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver
2018-04-23 8:21 ` Meenakshi Aggarwal
@ 2018-04-23 8:38 ` Leif Lindholm
2018-04-23 10:34 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-04-23 8:38 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi
On Mon, Apr 23, 2018 at 08:21:22AM +0000, Meenakshi Aggarwal wrote:
> > > +/**
> > > + Function to read data using i2c bus
> > > +
> > > + @param I2cBus I2c Controller number
> > > + @param Chip Address of slave device from where data to be read
> > > + @param Offset Offset of slave memory
> > > + @param Alen Address length of slave
> > > + @param Buffer A pointer to the destination buffer for the data
> > > + @param Len Length of data to be read
> > > +
> > > + @retval EFI_NOT_READY Arbitration lost
> > > + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined
> > time
> > > + @retval EFI_NOT_FOUND ACK was not recieved
> > > + @retval EFI_SUCCESS Read was successful
> > > +
> > > +**/
> > > +STATIC
> > > +EFI_STATUS
> > > +I2cDataRead (
> > > + IN UINT32 I2cBus,
> > > + IN UINT8 Chip,
> > > + IN UINT32 Offset,
> > > + IN UINT32 Alen,
> > > + IN UINT8 *Buffer,
> > > + IN UINT32 Len
> > > + )
> > > +{
> > > + EFI_STATUS Status;
> > > + UINT32 Temp;
> > > + INT32 I;
> > > + I2C_REGS *I2cRegs;
> > > +
> > > + I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
> > > + (I2cBus * FixedPcdGet32 (PcdI2cSize))));
> >
> > Please get rid of this hardcoded base address and use NonDiscoverable
> > Have a look at Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/ and
> > Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/
> > for example.
> >
> I have checked SynQuacer code and i dont see its adding much advantage.
What it gives is the ability to cover more than one controller by this
driver, regardless of whether you need it for this particular platform
port or not.
> There also base address is hard coded SYNQUACER_I2C1_BASE in
> PlatformDxe driver.
Yes, the PlatformDxe driver statically instantiates dynamic drivers
for non-discoverable buses. But there is no longer any hard-coded
addresses in the device driver itself.
/
Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver
2018-04-23 8:38 ` Leif Lindholm
@ 2018-04-23 10:34 ` Meenakshi Aggarwal
2018-04-23 13:39 ` Ard Biesheuvel
0 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-04-23 10:34 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi
Hi Leif
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Monday, April 23, 2018 2:08 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c
> driver
>
> On Mon, Apr 23, 2018 at 08:21:22AM +0000, Meenakshi Aggarwal wrote:
> > > > +/**
> > > > + Function to read data using i2c bus
> > > > +
> > > > + @param I2cBus I2c Controller number
> > > > + @param Chip Address of slave device from where data to be
> read
> > > > + @param Offset Offset of slave memory
> > > > + @param Alen Address length of slave
> > > > + @param Buffer A pointer to the destination buffer for the data
> > > > + @param Len Length of data to be read
> > > > +
> > > > + @retval EFI_NOT_READY Arbitration lost
> > > > + @retval EFI_TIMEOUT Failed to initialize data transfer in
> predefined
> > > time
> > > > + @retval EFI_NOT_FOUND ACK was not recieved
> > > > + @retval EFI_SUCCESS Read was successful
> > > > +
> > > > +**/
> > > > +STATIC
> > > > +EFI_STATUS
> > > > +I2cDataRead (
> > > > + IN UINT32 I2cBus,
> > > > + IN UINT8 Chip,
> > > > + IN UINT32 Offset,
> > > > + IN UINT32 Alen,
> > > > + IN UINT8 *Buffer,
> > > > + IN UINT32 Len
> > > > + )
> > > > +{
> > > > + EFI_STATUS Status;
> > > > + UINT32 Temp;
> > > > + INT32 I;
> > > > + I2C_REGS *I2cRegs;
> > > > +
> > > > + I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
> > > > + (I2cBus * FixedPcdGet32 (PcdI2cSize))));
> > >
> > > Please get rid of this hardcoded base address and use NonDiscoverable
> > > Have a look at Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/ and
> > > Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/
> > > for example.
> > >
> > I have checked SynQuacer code and i dont see its adding much advantage.
>
> What it gives is the ability to cover more than one controller by this
> driver, regardless of whether you need it for this particular platform
> port or not.
>
Current board needs one controller.
In case of multiple controller, we can use a loop to install multiple protocols and
If needed then our preference would be to use I2c enumeration protocol.
This will allow to use correct controller for connected devices.
With sample implementation of SynQuacer code,
Please advise, how a right controller is being connected to driver
e.g. we are registering two controllers mI2c0Desc and mI2c1Desc and
both are exporting same protocols.
Its user, RTC lib just checking gEfiI2cMasterProtocolGuid. There is possibility
to connect with any of the controller. I dont see in code where it is assuring connection with right controller.
And how we can assure we are connecting to the correct controller.
> > There also base address is hard coded SYNQUACER_I2C1_BASE in
> > PlatformDxe driver.
>
> Yes, the PlatformDxe driver statically instantiates dynamic drivers
> for non-discoverable buses. But there is no longer any hard-coded
> addresses in the device driver itself.
>
> /
> Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver
2018-04-23 10:34 ` Meenakshi Aggarwal
@ 2018-04-23 13:39 ` Ard Biesheuvel
2018-04-23 15:50 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Ard Biesheuvel @ 2018-04-23 13:39 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: Leif Lindholm, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi
On 23 April 2018 at 12:34, Meenakshi Aggarwal
<meenakshi.aggarwal@nxp.com> wrote:
> Hi Leif
>
>> -----Original Message-----
>> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
>> Sent: Monday, April 23, 2018 2:08 PM
>> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>> Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
>> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
>> Subject: Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c
>> driver
>>
>> On Mon, Apr 23, 2018 at 08:21:22AM +0000, Meenakshi Aggarwal wrote:
>> > > > +/**
>> > > > + Function to read data using i2c bus
>> > > > +
>> > > > + @param I2cBus I2c Controller number
>> > > > + @param Chip Address of slave device from where data to be
>> read
>> > > > + @param Offset Offset of slave memory
>> > > > + @param Alen Address length of slave
>> > > > + @param Buffer A pointer to the destination buffer for the data
>> > > > + @param Len Length of data to be read
>> > > > +
>> > > > + @retval EFI_NOT_READY Arbitration lost
>> > > > + @retval EFI_TIMEOUT Failed to initialize data transfer in
>> predefined
>> > > time
>> > > > + @retval EFI_NOT_FOUND ACK was not recieved
>> > > > + @retval EFI_SUCCESS Read was successful
>> > > > +
>> > > > +**/
>> > > > +STATIC
>> > > > +EFI_STATUS
>> > > > +I2cDataRead (
>> > > > + IN UINT32 I2cBus,
>> > > > + IN UINT8 Chip,
>> > > > + IN UINT32 Offset,
>> > > > + IN UINT32 Alen,
>> > > > + IN UINT8 *Buffer,
>> > > > + IN UINT32 Len
>> > > > + )
>> > > > +{
>> > > > + EFI_STATUS Status;
>> > > > + UINT32 Temp;
>> > > > + INT32 I;
>> > > > + I2C_REGS *I2cRegs;
>> > > > +
>> > > > + I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
>> > > > + (I2cBus * FixedPcdGet32 (PcdI2cSize))));
>> > >
>> > > Please get rid of this hardcoded base address and use NonDiscoverable
>> > > Have a look at Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/ and
>> > > Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/
>> > > for example.
>> > >
>> > I have checked SynQuacer code and i dont see its adding much advantage.
>>
>> What it gives is the ability to cover more than one controller by this
>> driver, regardless of whether you need it for this particular platform
>> port or not.
>>
> Current board needs one controller.
It is not about what the board wants. It is about reusing code.
If you implemented a driver using the UEFI driver model, you get all
the binding machinery for free, and you only need to declare the
existence of a controller and the core will bind and discover drivers.
This also allows you to unbind a driver from a single controller, for
instance, and keeping the other connections alive.
> In case of multiple controller, we can use a loop to install multiple protocols and
> If needed then our preference would be to use I2c enumeration protocol.
> This will allow to use correct controller for connected devices.
>
I2C enumeration protocol has nothing to do with this.
> With sample implementation of SynQuacer code,
> Please advise, how a right controller is being connected to driver
> e.g. we are registering two controllers mI2c0Desc and mI2c1Desc and
> both are exporting same protocols.
> Its user, RTC lib just checking gEfiI2cMasterProtocolGuid. There is possibility
> to connect with any of the controller. I dont see in code where it is assuring connection with right controller.
> And how we can assure we are connecting to the correct controller.
>
The PCF8563 RTC driver has a special GUIDed protocol that identifies
the I2C controller that has the RTC connected to it. This goes outside
of the UDM because RTC is an architectural protocol. Note that the
SynQuacer I2C driver is a DXE_RUNTIME_DRIVER module that supports boot
time and runtime I2C support for controllers, the latter especially
for things like RTC and varstore support over I2C.
>> > There also base address is hard coded SYNQUACER_I2C1_BASE in
>> > PlatformDxe driver.
>>
>> Yes, the PlatformDxe driver statically instantiates dynamic drivers
>> for non-discoverable buses. But there is no longer any hard-coded
>> addresses in the device driver itself.
>>
>> /
>> Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver
2018-04-23 13:39 ` Ard Biesheuvel
@ 2018-04-23 15:50 ` Meenakshi Aggarwal
2018-04-23 15:53 ` Ard Biesheuvel
0 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-04-23 15:50 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Leif Lindholm, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi
Hi Ard
> -----Original Message-----
> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]
> Sent: Monday, April 23, 2018 7:10 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>; edk2-devel@lists.01.org; Udit
> Kumar <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c
> driver
>
> On 23 April 2018 at 12:34, Meenakshi Aggarwal
> <meenakshi.aggarwal@nxp.com> wrote:
> > Hi Leif
> >
> >> -----Original Message-----
> >> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> >> Sent: Monday, April 23, 2018 2:08 PM
> >> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> >> Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> >> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
> >> Subject: Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for
> I2c
> >> driver
> >>
> >> On Mon, Apr 23, 2018 at 08:21:22AM +0000, Meenakshi Aggarwal wrote:
> >> > > > +/**
> >> > > > + Function to read data using i2c bus
> >> > > > +
> >> > > > + @param I2cBus I2c Controller number
> >> > > > + @param Chip Address of slave device from where data to
> be
> >> read
> >> > > > + @param Offset Offset of slave memory
> >> > > > + @param Alen Address length of slave
> >> > > > + @param Buffer A pointer to the destination buffer for the
> data
> >> > > > + @param Len Length of data to be read
> >> > > > +
> >> > > > + @retval EFI_NOT_READY Arbitration lost
> >> > > > + @retval EFI_TIMEOUT Failed to initialize data transfer in
> >> predefined
> >> > > time
> >> > > > + @retval EFI_NOT_FOUND ACK was not recieved
> >> > > > + @retval EFI_SUCCESS Read was successful
> >> > > > +
> >> > > > +**/
> >> > > > +STATIC
> >> > > > +EFI_STATUS
> >> > > > +I2cDataRead (
> >> > > > + IN UINT32 I2cBus,
> >> > > > + IN UINT8 Chip,
> >> > > > + IN UINT32 Offset,
> >> > > > + IN UINT32 Alen,
> >> > > > + IN UINT8 *Buffer,
> >> > > > + IN UINT32 Len
> >> > > > + )
> >> > > > +{
> >> > > > + EFI_STATUS Status;
> >> > > > + UINT32 Temp;
> >> > > > + INT32 I;
> >> > > > + I2C_REGS *I2cRegs;
> >> > > > +
> >> > > > + I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
> >> > > > + (I2cBus * FixedPcdGet32 (PcdI2cSize))));
> >> > >
> >> > > Please get rid of this hardcoded base address and use
> NonDiscoverable
> >> > > Have a look at Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/ and
> >> > > Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/
> >> > > for example.
> >> > >
> >> > I have checked SynQuacer code and i dont see its adding much
> advantage.
> >>
> >> What it gives is the ability to cover more than one controller by this
> >> driver, regardless of whether you need it for this particular platform
> >> port or not.
> >>
> > Current board needs one controller.
>
> It is not about what the board wants. It is about reusing code.
>
Ideally, we should reuse as much as possible,
> If you implemented a driver using the UEFI driver model, you get all
> the binding machinery for free, and you only need to declare the
> existence of a controller and the core will bind and discover drivers.
But in case of this particular driver, even if we are using UEFI driver model.
Then from code perspective more or less, we need same code to declare i2c master
Protocol.
> This also allows you to unbind a driver from a single controller, for
> instance, and keeping the other connections alive.
>
I don't see any case in which we need to unbind driver for i2c.
Coming back to implementation part, there are some
advantages using UEFI driver model. At present we
are not using those features for i2c driver but if you think we should have these in code.
We will add this support.
> > In case of multiple controller, we can use a loop to install multiple protocols
> and
> > If needed then our preference would be to use I2c enumeration protocol.
> > This will allow to use correct controller for connected devices.
> >
>
> I2C enumeration protocol has nothing to do with this.
>
> > With sample implementation of SynQuacer code,
> > Please advise, how a right controller is being connected to driver
> > e.g. we are registering two controllers mI2c0Desc and mI2c1Desc and
> > both are exporting same protocols.
> > Its user, RTC lib just checking gEfiI2cMasterProtocolGuid. There is
> possibility
> > to connect with any of the controller. I dont see in code where it is assuring
> connection with right controller.
> > And how we can assure we are connecting to the correct controller.
> >
>
> The PCF8563 RTC driver has a special GUIDed protocol that identifies
> the I2C controller that has the RTC connected to it. This goes outside
> of the UDM because RTC is an architectural protocol. Note that the
> SynQuacer I2C driver is a DXE_RUNTIME_DRIVER module that supports boot
> time and runtime I2C support for controllers, the latter especially
> for things like RTC and varstore support over I2C.
>
I don’t say much on this because this is implementation , which can vary mind to mind.
But in order to maintain many controllers
and devices on the top of it, my preference would be to
go with bus configuration and bus enumeration protocol.
You can say, why to complicate the code, when this can be done
in easy way.
> >> > There also base address is hard coded SYNQUACER_I2C1_BASE in
> >> > PlatformDxe driver.
> >>
> >> Yes, the PlatformDxe driver statically instantiates dynamic drivers
> >> for non-discoverable buses. But there is no longer any hard-coded
> >> addresses in the device driver itself.
> >>
> >> /
> >> Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver
2018-04-23 15:50 ` Meenakshi Aggarwal
@ 2018-04-23 15:53 ` Ard Biesheuvel
0 siblings, 0 replies; 254+ messages in thread
From: Ard Biesheuvel @ 2018-04-23 15:53 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: Leif Lindholm, edk2-devel@lists.01.org, Udit Kumar, Varun Sethi
On 23 April 2018 at 17:50, Meenakshi Aggarwal
<meenakshi.aggarwal@nxp.com> wrote:
> Hi Ard
>
>> -----Original Message-----
>> From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]
>> Sent: Monday, April 23, 2018 7:10 PM
>> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>> Cc: Leif Lindholm <leif.lindholm@linaro.org>; edk2-devel@lists.01.org; Udit
>> Kumar <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
>> Subject: Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c
>> driver
>>
>> On 23 April 2018 at 12:34, Meenakshi Aggarwal
>> <meenakshi.aggarwal@nxp.com> wrote:
>> > Hi Leif
>> >
>> >> -----Original Message-----
>> >> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
>> >> Sent: Monday, April 23, 2018 2:08 PM
>> >> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>> >> Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
>> >> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
>> >> Subject: Re: [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for
>> I2c
>> >> driver
>> >>
>> >> On Mon, Apr 23, 2018 at 08:21:22AM +0000, Meenakshi Aggarwal wrote:
>> >> > > > +/**
>> >> > > > + Function to read data using i2c bus
>> >> > > > +
>> >> > > > + @param I2cBus I2c Controller number
>> >> > > > + @param Chip Address of slave device from where data to
>> be
>> >> read
>> >> > > > + @param Offset Offset of slave memory
>> >> > > > + @param Alen Address length of slave
>> >> > > > + @param Buffer A pointer to the destination buffer for the
>> data
>> >> > > > + @param Len Length of data to be read
>> >> > > > +
>> >> > > > + @retval EFI_NOT_READY Arbitration lost
>> >> > > > + @retval EFI_TIMEOUT Failed to initialize data transfer in
>> >> predefined
>> >> > > time
>> >> > > > + @retval EFI_NOT_FOUND ACK was not recieved
>> >> > > > + @retval EFI_SUCCESS Read was successful
>> >> > > > +
>> >> > > > +**/
>> >> > > > +STATIC
>> >> > > > +EFI_STATUS
>> >> > > > +I2cDataRead (
>> >> > > > + IN UINT32 I2cBus,
>> >> > > > + IN UINT8 Chip,
>> >> > > > + IN UINT32 Offset,
>> >> > > > + IN UINT32 Alen,
>> >> > > > + IN UINT8 *Buffer,
>> >> > > > + IN UINT32 Len
>> >> > > > + )
>> >> > > > +{
>> >> > > > + EFI_STATUS Status;
>> >> > > > + UINT32 Temp;
>> >> > > > + INT32 I;
>> >> > > > + I2C_REGS *I2cRegs;
>> >> > > > +
>> >> > > > + I2cRegs = (I2C_REGS *)(FixedPcdGet64 (PcdI2c0BaseAddr +
>> >> > > > + (I2cBus * FixedPcdGet32 (PcdI2cSize))));
>> >> > >
>> >> > > Please get rid of this hardcoded base address and use
>> NonDiscoverable
>> >> > > Have a look at Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/ and
>> >> > > Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/
>> >> > > for example.
>> >> > >
>> >> > I have checked SynQuacer code and i dont see its adding much
>> advantage.
>> >>
>> >> What it gives is the ability to cover more than one controller by this
>> >> driver, regardless of whether you need it for this particular platform
>> >> port or not.
>> >>
>> > Current board needs one controller.
>>
>> It is not about what the board wants. It is about reusing code.
>>
> Ideally, we should reuse as much as possible,
>
>> If you implemented a driver using the UEFI driver model, you get all
>> the binding machinery for free, and you only need to declare the
>> existence of a controller and the core will bind and discover drivers.
>
> But in case of this particular driver, even if we are using UEFI driver model.
> Then from code perspective more or less, we need same code to declare i2c master
> Protocol.
>
>> This also allows you to unbind a driver from a single controller, for
>> instance, and keeping the other connections alive.
>>
>
>
> I don't see any case in which we need to unbind driver for i2c.
>
> Coming back to implementation part, there are some
> advantages using UEFI driver model. At present we
> are not using those features for i2c driver but if you think we should have these in code.
> We will add this support.
>
>> > In case of multiple controller, we can use a loop to install multiple protocols
>> and
>> > If needed then our preference would be to use I2c enumeration protocol.
>> > This will allow to use correct controller for connected devices.
>> >
>>
>> I2C enumeration protocol has nothing to do with this.
>>
>> > With sample implementation of SynQuacer code,
>> > Please advise, how a right controller is being connected to driver
>> > e.g. we are registering two controllers mI2c0Desc and mI2c1Desc and
>> > both are exporting same protocols.
>> > Its user, RTC lib just checking gEfiI2cMasterProtocolGuid. There is
>> possibility
>> > to connect with any of the controller. I dont see in code where it is assuring
>> connection with right controller.
>> > And how we can assure we are connecting to the correct controller.
>> >
>>
>> The PCF8563 RTC driver has a special GUIDed protocol that identifies
>> the I2C controller that has the RTC connected to it. This goes outside
>> of the UDM because RTC is an architectural protocol. Note that the
>> SynQuacer I2C driver is a DXE_RUNTIME_DRIVER module that supports boot
>> time and runtime I2C support for controllers, the latter especially
>> for things like RTC and varstore support over I2C.
>>
>
> I don’t say much on this because this is implementation , which can vary mind to mind.
> But in order to maintain many controllers
> and devices on the top of it, my preference would be to
> go with bus configuration and bus enumeration protocol.
>
> You can say, why to complicate the code, when this can be done
> in easy way.
>
You are correct: the I2C enumeration and platform protocols should be
used in all cases *except* when we are dealing with a I2C device that
is used to produce an architectural protocol that is exposed to the OS
as a runtime service. This is why the PCF8563 invokes the I2C master
protocol directly rather than the I2C I/O protocol.
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 33/39] Silicon/NXP: Implement PciHostBridgeLib support
2018-04-20 8:34 ` Ard Biesheuvel
@ 2018-04-24 12:17 ` Vabhav Sharma
0 siblings, 0 replies; 254+ messages in thread
From: Vabhav Sharma @ 2018-04-24 12:17 UTC (permalink / raw)
To: Ard Biesheuvel, Meenakshi Aggarwal
Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org,
Udit Kumar, Varun Sethi
>-----Original Message-----
>From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]
>Sent: Friday, April 20, 2018 2:05 PM
>To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
><michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar
><udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
><vabhav.sharma@nxp.com>
>Subject: Re: [PATCH edk2-platforms 33/39] Silicon/NXP: Implement
>PciHostBridgeLib support
>
>On 16 February 2018 at 09:50, Meenakshi <meenakshi.aggarwal@nxp.com>
>wrote:
>> From: Vabhav <vabhav.sharma@nxp.com>
>>
>> Implement the library that exposes the PCIe root complexes to the
>> generic PCI host bridge driver,Putting SoC Specific low level init
>> code for the RCs.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
>> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>> ---
>> .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 618
>+++++++++++++++++++++
>> .../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 50 ++
>> 2 files changed, 668 insertions(+)
>> create mode 100644
>> Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
>> create mode 100644
>> Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>>
>> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
>> b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
>> new file mode 100644
>> index 0000000..e6f9b7c
>> --- /dev/null
>> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
>> @@ -0,0 +1,618 @@
>> +/** @file
>> + PCI Host Bridge Library instance for NXP SoCs
>> +
>> + Copyright 2018 NXP
>> +
>> + This program and the accompanying materials are licensed and made
>> + available under the terms and conditions of the BSD License which
>> + accompanies this distribution. The full text of the license may be
>> + found at
>https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fopensou
>rce.org%2Flicenses%2Fbsd-
>license.php&data=02%7C01%7Cvabhav.sharma%40nxp.com%7C44d0e1dcd1014
>e3dc13308d5a6999342%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C
>636598100906238234&sdata=sX%2BPAAKHQN41oqF8BnYLdIVKYYLgIMqWBNqPs
>9D3NdE%3D&reserved=0.
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#include <PiDxe.h>
>> +#include <IndustryStandard/Pci22.h>
>> +#include <Library/BeIoLib.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/DevicePathLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/MemoryAllocationLib.h> #include <Library/PcdLib.h>
>> +#include <Library/PciHostBridgeLib.h> #include <Pcie.h> #include
>> +<Protocol/PciHostBridgeResourceAllocation.h>
>> +#include <Protocol/PciRootBridgeIo.h>
>> +
>> +#pragma pack(1)
>> +typedef struct {
>> + ACPI_HID_DEVICE_PATH AcpiDevicePath;
>> + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; }
>> +EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; #pragma pack ()
>> +
>> +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH
>> +mEfiPciRootBridgeDevicePath[] = {
>> + {
>> + {
>> + {
>> + ACPI_DEVICE_PATH,
>> + ACPI_DP,
>> + {
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
>> + }
>> + },
>> + EISA_PNP_ID (0x0A08), // PCI Express
>> + PCI_SEG0_NUM
>> + },
>> +
>> + {
>> + END_DEVICE_PATH_TYPE,
>> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
>> + {
>> + END_DEVICE_PATH_LENGTH,
>> + 0
>> + }
>> + }
>> + },
>> + {
>> + {
>> + {
>> + ACPI_DEVICE_PATH,
>> + ACPI_DP,
>> + {
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
>> + }
>> + },
>> + EISA_PNP_ID (0x0A08), // PCI Express
>> + PCI_SEG1_NUM
>> + },
>> +
>> + {
>> + END_DEVICE_PATH_TYPE,
>> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
>> + {
>> + END_DEVICE_PATH_LENGTH,
>> + 0
>> + }
>> + }
>> + },
>> + {
>> + {
>> + {
>> + ACPI_DEVICE_PATH,
>> + ACPI_DP,
>> + {
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
>> + }
>> + },
>> + EISA_PNP_ID (0x0A08), // PCI Express
>> + PCI_SEG2_NUM
>> + },
>> +
>> + {
>> + END_DEVICE_PATH_TYPE,
>> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
>> + {
>> + END_DEVICE_PATH_LENGTH,
>> + 0
>> + }
>> + }
>> + },
>> + {
>> + {
>> + {
>> + ACPI_DEVICE_PATH,
>> + ACPI_DP,
>> + {
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
>> + }
>> + },
>> + EISA_PNP_ID (0x0A08), // PCI Express
>> + PCI_SEG3_NUM
>> + },
>> +
>> + {
>> + END_DEVICE_PATH_TYPE,
>> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
>> + {
>> + END_DEVICE_PATH_LENGTH,
>> + 0
>> + }
>> + }
>> + }
>> +};
>> +
>> +STATIC
>> +GLOBAL_REMOVE_IF_UNREFERENCED
>> +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
>> + L"Mem", L"I/O", L"Bus"
>> +};
>> +
>> +#define PCI_ALLOCATION_ATTRIBUTES
>EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | \
>> +
>> +EFI_PCI_HOST_BRIDGE_MEM64_DECODE
>> +
>> +#define PCI_SUPPORT_ATTRIBUTES EFI_PCI_ATTRIBUTE_ISA_IO_16 | \
>> + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
>> + EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
>> + EFI_PCI_ATTRIBUTE_VGA_IO_16 | \
>> +
>> +EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
>> +
>> +PCI_ROOT_BRIDGE mPciRootBridges[] = {
>> + {
>> + PCI_SEG0_NUM, // Segment
>> + PCI_SUPPORT_ATTRIBUTES, // Supports
>> + PCI_SUPPORT_ATTRIBUTES, // Attributes
>> + FALSE, // DmaAbove4G
>
>Why is this disabled? The root bridge driver will have to do bounce buffering
>when performing DMA on memory > 4 GB.
Ok.
>
>> + FALSE, // NoExtendedConfigSpace
>> + FALSE, // ResourceAssigned
>> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
>> + { PCI_SEG0_BUSNUM_MIN,
>> + PCI_SEG0_BUSNUM_MAX }, // Bus
>> + { PCI_SEG0_PORTIO_MIN,
>> + PCI_SEG0_PORTIO_MAX }, // Io
>> + { PCI_SEG0_MMIO32_MIN,
>> + PCI_SEG0_MMIO32_MAX }, // Mem
>> + { PCI_SEG0_MMIO64_MIN,
>> + PCI_SEG0_MMIO64_MAX }, // MemAbove4G
>> + { MAX_UINT64, 0x0 }, // PMem
>> + { MAX_UINT64, 0x0 }, // PMemAbove4G
>> + (EFI_DEVICE_PATH_PROTOCOL
>> +*)&mEfiPciRootBridgeDevicePath[PCI_SEG0_NUM]
>> + }, {
>> + PCI_SEG1_NUM, // Segment
>> + PCI_SUPPORT_ATTRIBUTES, // Supports
>> + PCI_SUPPORT_ATTRIBUTES, // Attributes
>> + FALSE, // DmaAbove4G
>> + FALSE, // NoExtendedConfigSpace
>> + FALSE, // ResourceAssigned
>> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
>> + { PCI_SEG1_BUSNUM_MIN,
>> + PCI_SEG1_BUSNUM_MAX }, // Bus
>> + { PCI_SEG1_PORTIO_MIN,
>> + PCI_SEG1_PORTIO_MAX }, // Io
>> + { PCI_SEG1_MMIO32_MIN,
>> + PCI_SEG1_MMIO32_MAX }, // Mem
>> + { PCI_SEG1_MMIO64_MIN,
>> + PCI_SEG1_MMIO64_MAX }, // MemAbove4G
>> + { MAX_UINT64, 0x0 }, // PMem
>> + { MAX_UINT64, 0x0 }, // PMemAbove4G
>> + (EFI_DEVICE_PATH_PROTOCOL
>> +*)&mEfiPciRootBridgeDevicePath[PCI_SEG1_NUM]
>> + }, {
>> + PCI_SEG2_NUM, // Segment
>> + PCI_SUPPORT_ATTRIBUTES, // Supports
>> + PCI_SUPPORT_ATTRIBUTES, // Attributes
>> + FALSE, // DmaAbove4G
>> + FALSE, // NoExtendedConfigSpace
>> + FALSE, // ResourceAssigned
>> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
>> + { PCI_SEG2_BUSNUM_MIN,
>> + PCI_SEG2_BUSNUM_MAX }, // Bus
>> + { PCI_SEG2_PORTIO_MIN,
>> + PCI_SEG2_PORTIO_MAX }, // Io
>> + { PCI_SEG2_MMIO32_MIN,
>> + PCI_SEG2_MMIO32_MAX }, // Mem
>> + { PCI_SEG2_MMIO64_MIN,
>> + PCI_SEG2_MMIO64_MAX }, // MemAbove4G
>> + { MAX_UINT64, 0x0 }, // PMem
>> + { MAX_UINT64, 0x0 }, // PMemAbove4G
>> + (EFI_DEVICE_PATH_PROTOCOL
>> +*)&mEfiPciRootBridgeDevicePath[PCI_SEG2_NUM]
>> + }, {
>> + PCI_SEG3_NUM, // Segment
>> + PCI_SUPPORT_ATTRIBUTES, // Supports
>> + PCI_SUPPORT_ATTRIBUTES, // Attributes
>> + FALSE, // DmaAbove4G
>> + FALSE, // NoExtendedConfigSpace
>> + FALSE, // ResourceAssigned
>> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
>> + { PCI_SEG3_BUSNUM_MIN,
>> + PCI_SEG3_BUSNUM_MAX }, // Bus
>> + { PCI_SEG3_PORTIO_MIN,
>> + PCI_SEG3_PORTIO_MAX }, // Io
>> + { PCI_SEG3_MMIO32_MIN,
>> + PCI_SEG3_MMIO32_MAX }, // Mem
>> + { PCI_SEG3_MMIO64_MIN,
>> + PCI_SEG3_MMIO64_MAX }, // MemAbove4G
>> + { MAX_UINT64, 0x0 }, // PMem
>> + { MAX_UINT64, 0x0 }, // PMemAbove4G
>> + (EFI_DEVICE_PATH_PROTOCOL
>> +*)&mEfiPciRootBridgeDevicePath[PCI_SEG3_NUM]
>> + }
>> +};
>> +
>> +/**
>> + Function to set-up iATU outbound window for PCIe controller
>> +
>> + @param Dbi Address of PCIe host controller.
>> + @param Idx Index of iATU outbound window.
>> + @param Type Type(Cfg0/Cfg1/Mem/IO) of iATU outbound window.
>> + @param Phys PCIe controller phy address for outbound window.
>> + @param BusAdr PCIe controller bus address for outbound window.
>> + @param Pcie Size of PCIe controller space(Cfg0/Cfg1/Mem/IO).
>> +
>> +**/
>> +STATIC
>> +VOID
>> +PcieIatuOutboundSet (
>> + IN EFI_PHYSICAL_ADDRESS Dbi,
>> + IN UINT32 Idx,
>> + IN UINT32 Type,
>> + IN UINT64 Phys,
>> + IN UINT64 BusAddr,
>> + IN UINT64 Size
>> + )
>> +{
>> + MmioWrite32 (Dbi + IATU_VIEWPORT_OFF,
>> + (UINT32)(IATU_VIEWPORT_OUTBOUND | Idx));
>> + MmioWrite32 (Dbi + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
>> + (UINT32)Phys);
>> + MmioWrite32 (Dbi + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
>> + (UINT32)(Phys >> 32));
>> + MmioWrite32 (Dbi + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
>> + (UINT32)(Phys + Size - BIT0));
>> + MmioWrite32 (Dbi + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
>> + (UINT32)BusAddr);
>> + MmioWrite32 (Dbi + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
>> + (UINT32)(BusAddr >> 32));
>> + MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
>> + (UINT32)Type);
>> + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
>> + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN);
>> +}
>> +
>> +/**
>> + Function to check PCIe controller LTSSM state
>> +
>> + @param Pcie Address of PCIe host controller.
>> +
>> +**/
>> +STATIC
>> +INTN
>> +PcieLinkState (
>> + IN EFI_PHYSICAL_ADDRESS Pcie
>> + )
>> +{
>> + UINT32 State;
>> +
>> + //
>> + // Reading PCIe controller LTSSM state // if (FeaturePcdGet
>> + (PcdPciLutBigEndian)) {
>> + State = BeMmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
>> + LTSSM_STATE_MASK;
>> + } else {
>> + State = MmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
>> + LTSSM_STATE_MASK;
>> + }
>> +
>> + if (State < LTSSM_PCIE_L0) {
>> + DEBUG ((DEBUG_INFO," Pcie Link error. LTSSM=0x%2x\n", State));
>> + return EFI_SUCCESS;
>> + }
>> +
>> + return EFI_UNSUPPORTED;
>> +}
>> +
>> +/**
>> + Helper function to check PCIe link state
>> +
>> + @param Pcie Address of PCIe host controller.
>> +
>> +**/
>> +STATIC
>> +INTN
>> +PcieLinkUp (
>> + IN EFI_PHYSICAL_ADDRESS Pcie
>> + )
>> +{
>> + INTN State;
>> + UINT32 Cap;
>> +
>> + State = PcieLinkState (Pcie);
>> + if (State) {
>> + return State;
>> + }
>> +
>> + //
>> + // Try to download speed to gen1
>> + //
>> + Cap = MmioRead32 ((UINTN)Pcie + PCI_LINK_CAP);
>> + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, (UINT32)(Cap &
>> + (~PCI_LINK_SPEED_MASK)) | BIT0); State = PcieLinkState (Pcie); if
>> + (State) {
>> + return State;
>> + }
>> +
>> + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, Cap);
>> +
>> + return EFI_SUCCESS;
>> +}
>> +
>> +/**
>> + This function checks whether PCIe is enabled or not
>> + depending upon SoC serdes protocol map
>> +
>> + @param PcieNum PCIe number.
>> +
>> + @return The PCIe number enabled in map.
>> + @return FALSE PCIe number is disabled in map.
>> +
>> +**/
>> +STATIC
>> +BOOLEAN
>> +IsPcieNumEnabled(
>> + IN UINTN PcieNum
>> + )
>> +{
>> + UINT64 SerDes1ProtocolMap;
>> +
>> + SerDes1ProtocolMap = 0x0;
>> +
>> + //
>> + // Reading serdes map
>> + //
>> + GetSerdesProtocolMaps (&SerDes1ProtocolMap);
>> +
>> + //
>> + // Verify serdes line is configured in the map // if (PcieNum <
>> + NUM_PCIE_CONTROLLER) {
>> + return IsSerDesLaneProtocolConfigured (SerDes1ProtocolMap,
>> + (PcieNum + BIT0)); } else {
>> + DEBUG ((DEBUG_ERROR, "Device not supported\n")); }
>> +
>> + return FALSE;
>> +}
>> +
>> +/**
>> + Function to set-up iATU outbound window for PCIe controller
>> +
>> + @param Pcie Address of PCIe host controller
>> + @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
>> + @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
>> + @param MemBase PCIe controller phy address Memory Space.
>> + @param IoBase PCIe controller phy address IO Space.
>> +**/
>> +STATIC
>> +VOID
>> +PcieSetupAtu (
>> + IN EFI_PHYSICAL_ADDRESS Pcie,
>> + IN EFI_PHYSICAL_ADDRESS Cfg0Base,
>> + IN EFI_PHYSICAL_ADDRESS Cfg1Base,
>> + IN EFI_PHYSICAL_ADDRESS MemBase,
>> + IN EFI_PHYSICAL_ADDRESS IoBase
>> + )
>> +{
>> +
>> + //
>> + // iATU : OUTBOUND WINDOW 0 : CFG0
>> + //
>> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX0,
>> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
>> + Cfg0Base,
>> + SEG_CFG_BUS,
>> + SEG_CFG_SIZE);
>> +
>> + //
>> + // iATU : OUTBOUND WINDOW 1 : CFG1
>> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX1,
>> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
>> + Cfg1Base,
>> + SEG_CFG_BUS,
>> + SEG_CFG_SIZE); // // iATU 2 : OUTBOUND
>> + WINDOW 2 : MEM // PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX2,
>> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
>> + MemBase,
>> + SEG_MEM_BUS,
>> + SEG_MEM_SIZE);
>> +
>> + //
>> + // iATU 3 : OUTBOUND WINDOW 3: IO
>> + //
>> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX3,
>> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
>> + IoBase,
>> + SEG_IO_BUS,
>> + SEG_IO_SIZE);
>> +
>
>What happened to the 64-bit MMIO window?
I will add it.
>
>> +}
>> +
>> +/**
>> + Helper function to set-up PCIe controller
>> +
>> + @param Pcie Address of PCIe host controller
>> + @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
>> + @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
>> + @param MemBase PCIe controller phy address Memory Space.
>> + @param IoBase PCIe controller phy address IO Space.
>> +
>> +**/
>> +STATIC
>> +VOID
>> +PcieSetupCntrl (
>> + IN EFI_PHYSICAL_ADDRESS Pcie,
>> + IN EFI_PHYSICAL_ADDRESS Cfg0Base,
>> + IN EFI_PHYSICAL_ADDRESS Cfg1Base,
>> + IN EFI_PHYSICAL_ADDRESS MemBase,
>> + IN EFI_PHYSICAL_ADDRESS IoBase
>> + )
>> +{
>> + //
>> + // iATU outbound set-up
>> + //
>> + PcieSetupAtu (Pcie, Cfg0Base, Cfg1Base, MemBase, IoBase);
>> +
>> + //
>> + // program correct class for RC
>> + //
>> + MmioWrite32 ((UINTN)Pcie + PCI_BASE_ADDRESS_0, (BIT0 - BIT0));
>> + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)BIT0);
>> + MmioWrite32 ((UINTN)Pcie + PCI_CLASS_DEVICE,
>> +(UINT32)PCI_CLASS_BRIDGE_PCI);
>> + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)(BIT0 -
>> +BIT0)); }
>> +
>> +/**
>> + Return all the root bridge instances in an array.
>> +
>> + @param Count Return the count of root bridge instances.
>> +
>> + @return All the root bridge instances in an array.
>> +
>> +**/
>> +PCI_ROOT_BRIDGE *
>> +EFIAPI
>> +PciHostBridgeGetRootBridges (
>> + OUT UINTN *Count
>> + )
>> +{
>> + UINTN Idx;
>> + INTN LinkUp;
>> + UINT64 PciPhyMemAddr[NUM_PCIE_CONTROLLER];
>> + UINT64 PciPhyCfg0Addr[NUM_PCIE_CONTROLLER];
>> + UINT64 PciPhyCfg1Addr[NUM_PCIE_CONTROLLER];
>> + UINT64 PciPhyIoAddr[NUM_PCIE_CONTROLLER];
>> + UINT64 Regs[NUM_PCIE_CONTROLLER];
>> +
>> + *Count = 0;
>> +
>> + //
>> + // Filling local array for
>> + // PCIe controller Physical address space for Cfg0,Cfg1,Mem,IO //
>> + Host Contoller address // for (Idx = 0; Idx <
>> + NUM_PCIE_CONTROLLER; Idx++) {
>> + PciPhyMemAddr[Idx] = PCI_SEG0_PHY_MEM_BASE + (PCI_BASE_DIFF * Idx);
>> + PciPhyCfg0Addr[Idx] = PCI_SEG0_PHY_CFG0_BASE + (PCI_BASE_DIFF * Idx);
>> + PciPhyCfg1Addr[Idx] = PCI_SEG0_PHY_CFG1_BASE + (PCI_BASE_DIFF * Idx);
>> + PciPhyIoAddr [Idx] = PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx);
>> + Regs[Idx] = PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx); }
>> +
>> + for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
>> + //
>> + // Verify PCIe controller is enabled in Soc Serdes Map
>> + //
>> + if (!IsPcieNumEnabled (Idx)) {
>> + DEBUG ((DEBUG_ERROR, "PCIE%d is disabled\n", (Idx + BIT0)));
>> + //
>> + // Continue with other PCIe controller
>> + //
>> + continue;
>> + }
>> + DEBUG ((DEBUG_INFO, "PCIE%d is Enabled\n", Idx + BIT0));
>> +
>> + //
>> + // Verify PCIe controller LTSSM state
>> + //
>> + LinkUp = PcieLinkUp(Regs[Idx]);
>> + if (!LinkUp) {
>> + //
>> + // Let the user know there's no PCIe link
>> + //
>> + DEBUG ((DEBUG_INFO,"no link, regs @ 0x%lx\n", Regs[Idx]));
>> + //
>> + // Continue with other PCIe controller
>> + //
>> + continue;
>> + }
>> + DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + BIT0));
>> +
>> + //
>> + // Function to set up address translation unit outbound window for
>> + // PCIe Controller
>> + //
>> + PcieSetupCntrl (Regs[Idx],
>> + PciPhyCfg0Addr[Idx],
>> + PciPhyCfg1Addr[Idx],
>> + PciPhyMemAddr[Idx],
>> + PciPhyIoAddr[Idx]);
>> + *Count += BIT0;
>> + break;
>> + }
>> +
>> + if (*Count == 0) {
>> + return NULL;
>> + } else {
>> + return &mPciRootBridges[Idx];
>> + }
>> +}
>> +
>> +/**
>> + Free the root bridge instances array returned from
>PciHostBridgeGetRootBridges().
>> +
>> + @param Bridges The root bridge instances array.
>> + @param Count The count of the array.
>> +**/
>> +VOID
>> +EFIAPI
>> +PciHostBridgeFreeRootBridges (
>> + PCI_ROOT_BRIDGE *Bridges,
>> + UINTN Count
>> + )
>> +{
>> +}
>> +
>> +/**
>> + Inform the platform that the resource conflict happens.
>> +
>> + @param HostBridgeHandle Handle of the Host Bridge.
>> + @param Configuration Pointer to PCI I/O and PCI memory resource
>> + descriptors. The Configuration contains the resources
>> + for all the root bridges. The resource for each root
>> + bridge is terminated with END descriptor and an
>> + additional END is appended indicating the end of the
>> + entire resources. The resource descriptor field
>> + values follow the description in
>> + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
>> + .SubmitResources().
>> +
>> +**/
>> +VOID
>> +EFIAPI
>> +PciHostBridgeResourceConflict (
>> + EFI_HANDLE HostBridgeHandle,
>> + VOID *Configuration
>> + )
>> +{
>> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
>> + UINTN RootBridgeIndex;
>> + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict
>> +happens!\n"));
>> +
>> + RootBridgeIndex = 0;
>> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
>> + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
>> + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
>> + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR;
>Descriptor++) {
>> + ASSERT (Descriptor->ResType <
>> + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));
>> + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
>> + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
>> + Descriptor->AddrLen, Descriptor->AddrRangeMax
>> + ));
>> + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
>> + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
>> + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
>> + ((Descriptor->SpecificFlag &
>> +
>EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
>> + ) != 0) ? L" (Prefetchable)" : L""
>> + ));
>> + }
>> + }
>> + //
>> + // Skip the END descriptor for root bridge
>> + //
>> + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
>> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
>> + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
>> + );
>> + }
>> +
>> + return;
>> +}
>> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>> b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>> new file mode 100644
>> index 0000000..f08ac60
>> --- /dev/null
>> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>> @@ -0,0 +1,50 @@
>> +## @file
>> +# PCI Host Bridge Library instance for NXP ARM SOC # # Copyright
>> +2018 NXP # # This program and the accompanying materials are
>> +licensed and made available # under the terms and conditions of the
>> +BSD License which accompanies this # distribution. The full text of
>> +the license may be found at #
>> +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
>> +nsource.org%2Flicenses%2Fbsd-
>license.php&data=02%7C01%7Cvabhav.sharma
>>
>+%40nxp.com%7C44d0e1dcd1014e3dc13308d5a6999342%7C686ea1d3bc2b4c6f
>a92cd
>>
>+99c5c301635%7C0%7C0%7C636598100906238234&sdata=sX%2BPAAKHQN41o
>qF8BnYL
>> +dIVKYYLgIMqWBNqPs9D3NdE%3D&reserved=0
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
>EITHER
>> +EXPRESS OR # IMPLIED.
>> +#
>> +#
>> +##
>> +
>> +[Defines]
>> + INF_VERSION = 0x0001001A
>> + BASE_NAME = PciHostBridgeLib
>> + FILE_GUID = f4c99bcc-5c95-49ad-b0f3-fc5b611dc9c1
>> + MODULE_TYPE = BASE
>> + VERSION_STRING = 1.0
>> + LIBRARY_CLASS = PciHostBridgeLib
>> +
>> +[Sources]
>> + PciHostBridgeLib.c
>> +
>> +[Packages]
>> + MdePkg/MdePkg.dec
>> + MdeModulePkg/MdeModulePkg.dec
>> + Silicon/NXP/NxpQoriqLs.dec
>> + Silicon/NXP/Chassis/Chassis2/Chassis2.dec
>> +
>> +[LibraryClasses]
>> + DebugLib
>> + DevicePathLib
>> + MemoryAllocationLib
>> + PcdLib
>> + SocLib
>> + UefiBootServicesTableLib
>> +
>> +[Pcd]
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian
>> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController
>> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase
>> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
>> --
>> 1.9.1
>>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 34/39] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
2018-04-20 8:40 ` Ard Biesheuvel
@ 2018-04-24 12:26 ` Vabhav Sharma
2018-04-24 12:33 ` Ard Biesheuvel
0 siblings, 1 reply; 254+ messages in thread
From: Vabhav Sharma @ 2018-04-24 12:26 UTC (permalink / raw)
To: Ard Biesheuvel, Meenakshi Aggarwal
Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org,
Udit Kumar, Varun Sethi
>-----Original Message-----
>From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]
>Sent: Friday, April 20, 2018 2:11 PM
>To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
><michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar
><udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
><vabhav.sharma@nxp.com>
>Subject: Re: [PATCH edk2-platforms 34/39] Silicon/NXP: Implement
>EFI_CPU_IO2_PROTOCOL
>
>On 16 February 2018 at 09:50, Meenakshi <meenakshi.aggarwal@nxp.com>
>wrote:
>> From: Vabhav <vabhav.sharma@nxp.com>
>>
>> NXP SOC has mutiple PCIe RCs,Adding respective implementation of
>> EFI_CPU_IO2_PROTOCOL to provide Memory Space Read/Write functions used
>> by generic Host Bridge Driver including correct value for the
>> translation offset during MMIO accesses
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
>> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
>This driver looks completely wrong to me: MMIO access is memory mapped, and
>given that you don't implement PCI to CPU translation of MMIO accesses, the
>memory read and write functions should not perform any translation at all, and
>just relay the accesses. On the other hand, the I/O accessors are not
>implemented at all, and these are the ones that require translation, given that the
>I/O port addresses in the CPU space need translation to MMIO addressess.
On NXP SoC, Mapping between CPU view and PCIe view is not 1:1 and require CPU view translation for MMIO regions access, Accordingly translation is added during memory read/write services.
Bus driver relays the address range where PCIe device Bar region is split from, Translation is required for relaying it to correct PCIe controller cpu view address.
>
>Also, you don't seem to be using the PcdPciExp?BaseAddr PCDs anywhere, so you
>can drop them from the .dsc
No, It's used for checking the access to MMIO32 region and CPU view base address varies between different NXP SoCs
>
>> ---
>> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 529
>++++++++++++++++++++++
>> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 ++
>> 2 files changed, 577 insertions(+)
>> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>>
>> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>> b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>> new file mode 100644
>> index 0000000..b5fb72c
>> --- /dev/null
>> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>> @@ -0,0 +1,529 @@
>> +/** @file
>> + Produces the CPU I/O 2 Protocol.
>> +
>> + Copyright (c) 2009 - 2012, Intel Corporation. All rights
>> + reserved.<BR> Copyright (c) 2016, Linaro Ltd. All rights
>> + reserved.<BR> Copyright 2018 NXP
>> +
>> + This program and the accompanying materials are licensed and made
>> + available under the terms and conditions of the BSD License which
>> + accompanies this distribution. The full text of the license may be
>> + found at
>> +
>> + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop
>> + ensource.org%2Flicenses%2Fbsd-license.php&data=02%7C01%7Cvabhav.shar
>> +
>ma%40nxp.com%7C4507c0726b244ad6476d08d5a69a64ee%7C686ea1d3bc2b4c
>6fa9
>> +
>2cd99c5c301635%7C0%7C0%7C636598104414046440&sdata=IFSU0%2FeTdWrw
>gg0f
>> + 0Lq2qSVGgogG68tYZevrRmC%2BkV8%3D&reserved=0
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#include <Library/BaseLib.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/PcdLib.h>
>> +#include <Library/UefiBootServicesTableLib.h>
>> +#include <Pcie.h>
>> +#include <Protocol/CpuIo2.h>
>> +
>> +#define MAX_IO_PORT_ADDRESS PCI_SEG2_PORTIO_MAX
>> +
>> +//
>> +// Handle for the CPU I/O 2 Protocol
>> +//
>> +STATIC EFI_HANDLE mHandle;
>> +
>> +//
>> +// Lookup table for increment values based on transfer widths //
>> +STATIC CONST UINT8 mInStride[] = {
>> + 1, // EfiCpuIoWidthUint8
>> + 2, // EfiCpuIoWidthUint16
>> + 4, // EfiCpuIoWidthUint32
>> + 8, // EfiCpuIoWidthUint64
>> + 0, // EfiCpuIoWidthFifoUint8
>> + 0, // EfiCpuIoWidthFifoUint16
>> + 0, // EfiCpuIoWidthFifoUint32
>> + 0, // EfiCpuIoWidthFifoUint64
>> + 1, // EfiCpuIoWidthFillUint8
>> + 2, // EfiCpuIoWidthFillUint16
>> + 4, // EfiCpuIoWidthFillUint32
>> + 8 // EfiCpuIoWidthFillUint64
>> +};
>> +
>> +//
>> +// Lookup table for increment values based on transfer widths //
>> +STATIC CONST UINT8 mOutStride[] = {
>> + 1, // EfiCpuIoWidthUint8
>> + 2, // EfiCpuIoWidthUint16
>> + 4, // EfiCpuIoWidthUint32
>> + 8, // EfiCpuIoWidthUint64
>> + 1, // EfiCpuIoWidthFifoUint8
>> + 2, // EfiCpuIoWidthFifoUint16
>> + 4, // EfiCpuIoWidthFifoUint32
>> + 8, // EfiCpuIoWidthFifoUint64
>> + 0, // EfiCpuIoWidthFillUint8
>> + 0, // EfiCpuIoWidthFillUint16
>> + 0, // EfiCpuIoWidthFillUint32
>> + 0 // EfiCpuIoWidthFillUint64
>> +};
>> +
>> +/**
>> + Check parameters to a CPU I/O 2 Protocol service request.
>> +
>> + The I/O operations are carried out exactly as requested. The caller
>> + is responsible for satisfying any alignment and I/O width
>> + restrictions that a PI System on a platform might require. For
>> + example on some platforms, width requests of
>> + EfiCpuIoWidthUint64 do not work.
>> +
>> + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O
>Port operation.
>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>> + @param[in] Address The base address of the I/O operation.
>> + @param[in] Count The number of I/O operations to perform. The
>number of
>> + bytes moved is Width size * Count, starting at Address.
>> + @param[in] Buffer For read operations, the destination buffer to store
>the results.
>> + For write operations, the source buffer from which to write
>data.
>> +
>> + @retval EFI_SUCCESS The parameters for this request pass the checks.
>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>Width,
>> + and Count is not valid for this PI system.
>> +
>> +**/
>> +STATIC
>> +EFI_STATUS
>> +CpuIoCheckParameter (
>> + IN BOOLEAN MmioOperation,
>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>> + IN UINT64 Address,
>> + IN UINTN Count,
>> + IN VOID *Buffer
>> + )
>> +{
>> + UINT64 MaxCount;
>> + UINT64 Limit;
>> +
>> + //
>> + // Check to see if Buffer is NULL
>> + //
>> + if (Buffer == NULL) {
>> + ASSERT (FALSE);
>> + return EFI_INVALID_PARAMETER;
>> + }
>> +
>> + //
>> + // Check to see if Width is in the valid range // if
>> + ((UINT32)Width >= EfiCpuIoWidthMaximum) {
>> + ASSERT (FALSE);
>> + return EFI_INVALID_PARAMETER;
>> + }
>> +
>> + //
>> + // For FIFO type, the target address won't increase during the
>> + access, // so treat Count as 1 // if (Width >=
>> + EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
>> + Count = 1;
>> + }
>> +
>> + //
>> + // Check to see if Width is in the valid range for I/O Port
>> + operations // Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
>> + if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
>> + ASSERT (FALSE);
>> + return EFI_INVALID_PARAMETER;
>> + }
>> +
>> + //
>> + // Check to see if Address is aligned // if ((Address &
>> + (UINT64)(mInStride[Width] - 1)) != 0) {
>> + ASSERT (FALSE);
>> + return EFI_UNSUPPORTED;
>> + }
>> +
>> + //
>> + // Check to see if any address associated with this transfer
>> + exceeds the maximum // allowed address. The maximum address
>> + implied by the parameters passed in is // Address + Size * Count.
>> + If the following condition is met, then the transfer // is not supported.
>> + //
>> + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS :
>MAX_IO_PORT_ADDRESS) + 1
>> + //
>> + // Since MAX_ADDRESS can be the maximum integer value supported by
>> + the CPU and Count // can also be the maximum integer value
>> + supported by the CPU, this range // check must be adjusted to avoid all
>oveflow conditions.
>> + //
>> + Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); if
>> + (Count == 0) {
>> + if (Address > Limit) {
>> + ASSERT (FALSE);
>> + return EFI_UNSUPPORTED;
>> + }
>> + } else {
>> + MaxCount = RShiftU64 (Limit, Width);
>> + if (MaxCount < (Count - 1)) {
>> + ASSERT (FALSE);
>> + return EFI_UNSUPPORTED;
>> + }
>> + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
>> + ASSERT (FALSE);
>> + return EFI_UNSUPPORTED;
>> + }
>> + }
>> +
>> + //
>> + // Check to see if Buffer is aligned // if (((UINTN)Buffer &
>> + ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
>> + ASSERT (FALSE);
>> + return EFI_UNSUPPORTED;
>> + }
>> +
>> + return EFI_SUCCESS;
>> +}
>> +
>> +/**
>> + Reads memory-mapped registers.
>> +
>> + The I/O operations are carried out exactly as requested. The caller
>> + is responsible for satisfying any alignment and I/O width
>> + restrictions that a PI System on a platform might require. For
>> + example on some platforms, width requests of
>> + EfiCpuIoWidthUint64 do not work.
>> +
>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and
>> + Buffer are incremented for each of the Count operations that is performed.
>> +
>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>> + Buffer is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times on the
>same Address.
>> +
>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>> + Address is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times from the
>first element of Buffer.
>> +
>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>> + @param[in] Address The base address of the I/O operation.
>> + @param[in] Count The number of I/O operations to perform. The number
>of
>> + bytes moved is Width size * Count, starting at Address.
>> + @param[out] Buffer For read operations, the destination buffer to store the
>results.
>> + For write operations, the source buffer from which to write data.
>> +
>> + @retval EFI_SUCCESS The data was read from or written to the PI
>system.
>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>Width,
>> + and Count is not valid for this PI system.
>> +
>> +**/
>> +STATIC
>> +EFI_STATUS
>> +EFIAPI
>> +CpuMemoryServiceRead (
>> + IN EFI_CPU_IO2_PROTOCOL *This,
>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>> + IN UINT64 Address,
>> + IN UINTN Count,
>> + OUT VOID *Buffer
>> + )
>> +{
>> + EFI_STATUS Status;
>> + UINT8 InStride;
>> + UINT8 OutStride;
>> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
>> + UINT8 *Uint8Buffer;
>> +
>> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
>> + if (EFI_ERROR (Status)) {
>> + return Status;
>> + }
>> +
>> + if ((Address >= PCI_SEG0_MMIO32_MIN) &&
>> + (Address <= PCI_SEG0_MMIO32_MAX)) {
>> + Address += PCI_SEG0_MMIO_MEMBASE; } else if ((Address >=
>> + PCI_SEG1_MMIO32_MIN) &&
>> + (Address <= PCI_SEG1_MMIO32_MAX)) {
>> + Address += PCI_SEG1_MMIO_MEMBASE; } else if ((Address >=
>> + PCI_SEG2_MMIO32_MIN) &&
>> + (Address <= PCI_SEG2_MMIO32_MAX)) {
>> + Address += PCI_SEG2_MMIO_MEMBASE; } else if ((Address >=
>> + PCI_SEG3_MMIO32_MIN) &&
>> + (Address <= PCI_SEG3_MMIO32_MAX)) {
>> + Address += PCI_SEG3_MMIO_MEMBASE; } else {
>> + ASSERT (FALSE);
>> + return EFI_INVALID_PARAMETER;
>> + }
>> +
>> + //
>> + // Select loop based on the width of the transfer
>> + //
>> + InStride = mInStride[Width];
>> + OutStride = mOutStride[Width];
>> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
>> + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer +=
>OutStride, Count--) {
>> + if (OperationWidth == EfiCpuIoWidthUint8) {
>> + *Uint8Buffer = MmioRead8 ((UINTN)Address);
>> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
>> + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
>> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
>> + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
>> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
>> + *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
>> + }
>> + }
>> + return EFI_SUCCESS;
>> +}
>> +
>> +/**
>> + Writes memory-mapped registers.
>> +
>> + The I/O operations are carried out exactly as requested. The caller
>> + is responsible for satisfying any alignment and I/O width
>> + restrictions that a PI System on a platform might require. For
>> + example on some platforms, width requests of
>> + EfiCpuIoWidthUint64 do not work.
>> +
>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and
>> + Buffer are incremented for each of the Count operations that is performed.
>> +
>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>> + Buffer is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times on the
>same Address.
>> +
>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>> + Address is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times from the
>first element of Buffer.
>> +
>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>> + @param[in] Address The base address of the I/O operation.
>> + @param[in] Count The number of I/O operations to perform. The number
>of
>> + bytes moved is Width size * Count, starting at Address.
>> + @param[in] Buffer For read operations, the destination buffer to store the
>results.
>> + For write operations, the source buffer from which to write data.
>> +
>> + @retval EFI_SUCCESS The data was read from or written to the PI
>system.
>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>Width,
>> + and Count is not valid for this PI system.
>> +
>> +**/
>> +STATIC
>> +EFI_STATUS
>> +EFIAPI
>> +CpuMemoryServiceWrite (
>> + IN EFI_CPU_IO2_PROTOCOL *This,
>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>> + IN UINT64 Address,
>> + IN UINTN Count,
>> + IN VOID *Buffer
>> + )
>> +{
>> + EFI_STATUS Status;
>> + UINT8 InStride;
>> + UINT8 OutStride;
>> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
>> + UINT8 *Uint8Buffer;
>> +
>> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
>> + if (EFI_ERROR (Status)) {
>> + return Status;
>> + }
>> +
>> + if ((Address >= PCI_SEG0_MMIO32_MIN) &&
>> + (Address <= PCI_SEG0_MMIO32_MAX)) {
>> + Address += PCI_SEG0_MMIO_MEMBASE; } else if ((Address >=
>> + PCI_SEG1_MMIO32_MIN) &&
>> + (Address <= PCI_SEG1_MMIO32_MAX)) {
>> + Address += PCI_SEG1_MMIO_MEMBASE; } else if ((Address >=
>> + PCI_SEG2_MMIO32_MIN) &&
>> + (Address <= PCI_SEG2_MMIO32_MAX)) {
>> + Address += PCI_SEG2_MMIO_MEMBASE; } else if ((Address >=
>> + PCI_SEG3_MMIO32_MIN) &&
>> + (Address <= PCI_SEG3_MMIO32_MAX)) {
>> + Address += PCI_SEG3_MMIO_MEMBASE; } else {
>> + ASSERT (FALSE);
>> + return EFI_INVALID_PARAMETER;
>> + }
>> +
>> + //
>> + // Select loop based on the width of the transfer
>> + //
>> + InStride = mInStride[Width];
>> + OutStride = mOutStride[Width];
>> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
>> + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer +=
>OutStride, Count--) {
>> + if (OperationWidth == EfiCpuIoWidthUint8) {
>> + MmioWrite8 ((UINTN)Address, *Uint8Buffer);
>> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
>> + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
>> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
>> + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
>> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
>> + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
>> + }
>> + }
>> + return EFI_SUCCESS;
>> +}
>> +
>> +/**
>> + Reads I/O registers.
>> +
>> + The I/O operations are carried out exactly as requested. The caller
>> + is responsible for satisfying any alignment and I/O width
>> + restrictions that a PI System on a platform might require. For
>> + example on some platforms, width requests of
>> + EfiCpuIoWidthUint64 do not work.
>> +
>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and
>> + Buffer are incremented for each of the Count operations that is performed.
>> +
>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>> + Buffer is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times on the
>same Address.
>> +
>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>> + Address is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times from the
>first element of Buffer.
>> +
>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>> + @param[in] Address The base address of the I/O operation.
>> + @param[in] Count The number of I/O operations to perform. The number
>of
>> + bytes moved is Width size * Count, starting at Address.
>> + @param[out] Buffer For read operations, the destination buffer to store the
>results.
>> + For write operations, the source buffer from which to write data.
>> +
>> + @retval EFI_SUCCESS The data was read from or written to the PI
>system.
>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>Width,
>> + and Count is not valid for this PI system.
>> +
>> +**/
>> +STATIC
>> +EFI_STATUS
>> +EFIAPI
>> +CpuIoServiceRead (
>> + IN EFI_CPU_IO2_PROTOCOL *This,
>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>> + IN UINT64 Address,
>> + IN UINTN Count,
>> + OUT VOID *Buffer
>> + )
>> +{
>> + return EFI_SUCCESS;
>> +}
>> +
>> +/**
>> + Write I/O registers.
>> +
>> + The I/O operations are carried out exactly as requested. The caller
>> + is responsible for satisfying any alignment and I/O width
>> + restrictions that a PI System on a platform might require. For
>> + example on some platforms, width requests of
>> + EfiCpuIoWidthUint64 do not work.
>> +
>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and
>> + Buffer are incremented for each of the Count operations that is performed.
>> +
>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>> + Buffer is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times on the
>same Address.
>> +
>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>> + Address is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times from the
>first element of Buffer.
>> +
>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>> + @param[in] Address The base address of the I/O operation.
>> + @param[in] Count The number of I/O operations to perform. The number
>of
>> + bytes moved is Width size * Count, starting at Address.
>> + @param[in] Buffer For read operations, the destination buffer to store the
>results.
>> + For write operations, the source buffer from which to write data.
>> +
>> + @retval EFI_SUCCESS The data was read from or written to the PI
>system.
>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>Width,
>> + and Count is not valid for this PI system.
>> +
>> +**/
>> +STATIC
>> +EFI_STATUS
>> +EFIAPI
>> +CpuIoServiceWrite (
>> + IN EFI_CPU_IO2_PROTOCOL *This,
>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>> + IN UINT64 Address,
>> + IN UINTN Count,
>> + IN VOID *Buffer
>> + )
>> +{
>> + return EFI_SUCCESS;
>> +}
>> +
>> +//
>> +// CPU I/O 2 Protocol instance
>> +//
>> +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
>> + {
>> + CpuMemoryServiceRead,
>> + CpuMemoryServiceWrite
>> + },
>> + {
>> + CpuIoServiceRead,
>> + CpuIoServiceWrite
>> + }
>> +};
>> +
>> +
>> +/**
>> + The user Entry Point for module CpuIo2Dxe. The user code starts with this
>function.
>> +
>> + @param[in] ImageHandle The firmware allocated handle for the EFI image.
>> + @param[in] SystemTable A pointer to the EFI System Table.
>> +
>> + @retval EFI_SUCCESS The entry point is executed successfully.
>> + @retval other Some error occurs when executing this entry point.
>> +
>> +**/
>> +EFI_STATUS
>> +EFIAPI
>> +PciCpuIo2Initialize (
>> + IN EFI_HANDLE ImageHandle,
>> + IN EFI_SYSTEM_TABLE *SystemTable
>> + )
>> +{
>> + EFI_STATUS Status;
>> +
>> + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
>> + Status = gBS->InstallMultipleProtocolInterfaces (
>> + &mHandle,
>> + &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
>> + NULL
>> + );
>> + ASSERT_EFI_ERROR (Status);
>> +
>> + return Status;
>> +}
>> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>> b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>> new file mode 100644
>> index 0000000..25a1db1
>> --- /dev/null
>> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>> @@ -0,0 +1,48 @@
>> +## @file
>> +# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
>> +#
>> +# Copyright 2018 NXP
>> +#
>> +# This program and the accompanying materials # are licensed and made
>> +available under the terms and conditions of the BSD License # which
>> +accompanies this distribution. The full text of the license may be
>> +found at #
>> +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
>> +nsource.org%2Flicenses%2Fbsd-
>license.php&data=02%7C01%7Cvabhav.sharma
>>
>+%40nxp.com%7C4507c0726b244ad6476d08d5a69a64ee%7C686ea1d3bc2b4c6f
>a92cd
>>
>+99c5c301635%7C0%7C0%7C636598104414046440&sdata=IFSU0%2FeTdWrwgg
>0f0Lq2
>> +qSVGgogG68tYZevrRmC%2BkV8%3D&reserved=0
>> +#
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>> +#
>> +##
>> +
>> +[Defines]
>> + INF_VERSION = 0x0001001A
>> + BASE_NAME = PciCpuIo2Dxe
>> + FILE_GUID = 7bff18d7-9aae-434b-9c06-f10a7e157eac
>> + MODULE_TYPE = DXE_DRIVER
>> + VERSION_STRING = 1.0
>> + ENTRY_POINT = PciCpuIo2Initialize
>> +
>> +[Sources]
>> + PciCpuIo2Dxe.c
>> +
>> +[Packages]
>> + MdePkg/MdePkg.dec
>> + Silicon/NXP/NxpQoriqLs.dec
>> +
>> +[LibraryClasses]
>> + BaseLib
>> + DebugLib
>> + IoLib
>> + UefiBootServicesTableLib
>> + UefiDriverEntryPoint
>> +
>> +[Pcd]
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
>> +
>> +[Protocols]
>> + gEfiCpuIo2ProtocolGuid ## PRODUCES
>> +
>> +[Depex]
>> + TRUE
>> --
>> 1.9.1
>>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 32/39] Silicon/NXP: Implement PciSegmentLib to support multiple RCs
2018-04-20 12:41 ` Leif Lindholm
@ 2018-04-24 12:30 ` Vabhav Sharma
0 siblings, 0 replies; 254+ messages in thread
From: Vabhav Sharma @ 2018-04-24 12:30 UTC (permalink / raw)
To: Leif Lindholm
Cc: Meenakshi Aggarwal, ard.biesheuvel@linaro.org,
edk2-devel@lists.01.org, Udit Kumar, Varun Sethi
>-----Original Message-----
>From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
>Sent: Friday, April 20, 2018 6:12 PM
>To: Vabhav Sharma <vabhav.sharma@nxp.com>
>Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>;
>ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
><udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>
>Subject: Re: [PATCH edk2-platforms 32/39] Silicon/NXP: Implement
>PciSegmentLib to support multiple RCs
>
>On Fri, Apr 20, 2018 at 06:40:27AM +0000, Vabhav Sharma wrote:
>>
>>
>> >-----Original Message-----
>> >From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
>> >Sent: Friday, April 20, 2018 12:57 AM
>> >To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>> >Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
>> ><udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
>> ><vabhav.sharma@nxp.com>
>> >Subject: Re: [PATCH edk2-platforms 32/39] Silicon/NXP: Implement
>> >PciSegmentLib to support multiple RCs
>> >
>> >On Fri, Feb 16, 2018 at 02:20:28PM +0530, Meenakshi wrote:
>> >> From: Vabhav <vabhav.sharma@nxp.com>
>> >>
>> >> Multiple root complex support is not provided by standard library
>> >> PciLib/PciExpressLib/PciSegmentLib, Reimplementing it and provide
>> >> function for reading/writing into PCIe configuration Space.
>> >>
>> >> Contributed-under: TianoCore Contribution Agreement 1.1
>> >> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
>> >> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>> >> ---
>> >> Silicon/NXP/Include/Pcie.h | 143 +++++
>> >> Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 604
>> >+++++++++++++++++++++
>> >> .../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 41 ++
>> >> 3 files changed, 788 insertions(+) create mode 100644
>> >> Silicon/NXP/Include/Pcie.h create mode 100644
>> >> Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
>> >> create mode 100644
>> >> Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>> >>
>> >> diff --git a/Silicon/NXP/Include/Pcie.h
>> >> b/Silicon/NXP/Include/Pcie.h new file mode 100644 index
>> >> 0000000..a7e6f9b
>> >> --- /dev/null
>> >> +++ b/Silicon/NXP/Include/Pcie.h
>> >> @@ -0,0 +1,143 @@
>> >> +/** @file
>> >> + PCI memory configuration for NXP
>> >> +
>> >> + Copyright 2018 NXP
>> >> +
>> >> + This program and the accompanying materials are licensed and
>> >> + made available under the terms and conditions of the BSD License
>> >> + which accompanies this distribution. The full text of the
>> >> + license may be found at
>> >https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
>> >nsou
>> >rce.org%2Flicenses%2Fbsd-
>>
>>license.php&data=02%7C01%7Cvabhav.sharma%40nxp.com%7C081a2ebc43af4
>a
>>
>>daaf8e08d5a62b9921%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C
>6
>>
>>36597628604269440&sdata=kt661HfkUD2E3sYswy0I4vVFTV3%2Fq%2FiM%2Bi
>W
>> >egCISP%2BU%3D&reserved=0.
>> >> +
>> >> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> >> + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
>EITHER
>> >EXPRESS OR IMPLIED.
>> >> +
>> >> +**/
>> >> +
>> >> +#ifndef __PCI_H__
>> >> +#define __PCI_H__
>> >
>> >I'm not super happy about reusing such a generic name for the include
>> >guard - or really even the filename. (MdePkg/Include/Pci.h has
>> >_PCI_H_.)
>> >
>> >Could you rename this header NxpPcie.h and change the include guard
>> >to _NXP_PCIE_H_?
>> I see, Sure.
>> >
>> >> +
>> >> +// Segment 0
>> >> +#define PCI_SEG0_NUM 0
>> >> +
>> >> +#define PCI_SEG0_BUSNUM_MIN 0x0
>> >> +#define PCI_SEG0_BUSNUM_MAX 0xff
>> >> +
>> >> +#define PCI_SEG0_PORTIO_MIN 0x0
>> >> +#define PCI_SEG0_PORTIO_MAX 0xffff
>> >> +
>> >> +#define PCI_SEG0_MMIO32_MIN 0x40000000
>> >> +#define PCI_SEG0_MMIO32_MAX 0x4fffffff
>> >> +#define PCI_SEG0_MMIO64_MIN PCI_SEG0_MMIO_MEMBASE +
>> >SEG_MEM_SIZE
>> >> +#define PCI_SEG0_MMIO64_MAX PCI_SEG0_MMIO_MEMBASE +
>> >SEG_MEM_LIMIT
>> >> +#define PCI_SEG0_MMIO_MEMBASE FixedPcdGet64
>(PcdPciExp1BaseAddr)
>> >> +
>> >> +#define PCI_SEG0_DBI_BASE 0x03400000
>> >> +
>> >> +// Segment 1
>> >> +#define PCI_SEG1_NUM 1
>> >> +
>> >> +#define PCI_SEG1_BUSNUM_MIN 0x0
>> >> +#define PCI_SEG1_BUSNUM_MAX 0xff
>> >> +
>> >> +#define PCI_SEG1_PORTIO_MIN 0x10000
>> >> +#define PCI_SEG1_PORTIO_MAX 0x1ffff
>> >> +
>> >> +#define PCI_SEG1_MMIO32_MIN 0x50000000
>> >> +#define PCI_SEG1_MMIO32_MAX 0x5fffffff
>> >> +#define PCI_SEG1_MMIO64_MIN PCI_SEG1_MMIO_MEMBASE +
>> >SEG_MEM_SIZE
>> >> +#define PCI_SEG1_MMIO64_MAX PCI_SEG1_MMIO_MEMBASE +
>> >SEG_MEM_LIMIT
>> >> +#define PCI_SEG1_MMIO_MEMBASE FixedPcdGet64
>(PcdPciExp2BaseAddr)
>> >> +
>> >> +#define PCI_SEG1_DBI_BASE 0x03500000
>> >> +
>> >> +// Segment 2
>> >> +#define PCI_SEG2_NUM 2
>> >> +
>> >> +#define PCI_SEG2_BUSNUM_MIN 0x0
>> >> +#define PCI_SEG2_BUSNUM_MAX 0xff
>> >> +
>> >> +#define PCI_SEG2_PORTIO_MIN 0x20000
>> >> +#define PCI_SEG2_PORTIO_MAX 0x2ffff
>> >> +
>> >> +#define PCI_SEG2_MMIO32_MIN 0x60000000
>> >> +#define PCI_SEG2_MMIO32_MAX 0x6fffffff
>> >> +#define PCI_SEG2_MMIO64_MIN PCI_SEG2_MMIO_MEMBASE +
>> >SEG_MEM_SIZE
>> >> +#define PCI_SEG2_MMIO64_MAX PCI_SEG2_MMIO_MEMBASE +
>> >SEG_MEM_LIMIT
>> >> +#define PCI_SEG2_MMIO_MEMBASE FixedPcdGet64
>(PcdPciExp3BaseAddr)
>> >> +
>> >> +#define PCI_SEG2_DBI_BASE 0x03600000
>> >> +
>> >> +// Segment 3
>> >> +#define PCI_SEG3_NUM 3
>> >> +
>> >> +#define PCI_SEG3_BUSNUM_MIN 0x0
>> >> +#define PCI_SEG3_BUSNUM_MAX 0xff
>> >> +
>> >> +#define PCI_SEG3_PORTIO_MIN 0x30000
>> >> +#define PCI_SEG3_PORTIO_MAX 0x3ffff
>> >> +
>> >> +#define PCI_SEG3_MMIO32_MIN 0x70000000
>> >> +#define PCI_SEG3_MMIO32_MAX 0x7fffffff
>> >> +#define PCI_SEG3_MMIO64_MIN PCI_SEG3_MMIO_MEMBASE +
>> >SEG_MEM_SIZE
>> >> +#define PCI_SEG3_MMIO64_MAX PCI_SEG3_MMIO_MEMBASE +
>> >SEG_MEM_LIMIT
>> >> +#define PCI_SEG3_MMIO_MEMBASE FixedPcdGet64
>(PcdPciExp4BaseAddr)
>> >> +
>> >> +#define PCI_SEG3_DBI_BASE 0x03700000
>> >> +
>> >> +// Segment configuration
>> >> +#define SEG_CFG_SIZE 0x00001000
>> >> +#define SEG_CFG_BUS 0x00000000
>> >> +#define SEG_MEM_SIZE 0x40000000
>> >> +#define SEG_MEM_LIMIT 0x7fffffff
>> >> +#define SEG_MEM_BUS 0x40000000
>> >> +#define SEG_IO_SIZE 0x00010000
>> >> +#define SEG_IO_BUS 0x00000000
>> >> +#define PCI_BASE_DIFF 0x800000000
>> >> +#define PCI_DBI_SIZE_DIFF 0x100000
>> >> +#define PCI_SEG0_PHY_CFG0_BASE PCI_SEG0_MMIO_MEMBASE
>> >> +#define PCI_SEG0_PHY_CFG1_BASE PCI_SEG0_PHY_CFG0_BASE +
>> >SEG_CFG_SIZE
>> >> +#define PCI_SEG0_PHY_MEM_BASE PCI_SEG0_MMIO64_MIN
>> >> +#define PCI_SEG0_PHY_IO_BASE PCI_SEG0_MMIO_MEMBASE +
>> >SEG_IO_SIZE
>> >> +
>> >> +// iATU configuration
>> >> +#define IATU_VIEWPORT_OFF 0x900
>> >> +#define IATU_VIEWPORT_OUTBOUND 0
>> >> +
>> >> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904
>> >> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0
>> >> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
>> >> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4
>#define
>> >> +IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
>> >> +
>> >> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
>> >> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31
>> >> +
>> >> +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
>> >> +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
>> >> +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914
>> >> +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918
>> >> +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C
>> >> +
>> >> +#define IATU_REGION_INDEX0 0x0
>> >> +#define IATU_REGION_INDEX1 0x1
>> >> +#define IATU_REGION_INDEX2 0x2
>> >> +#define IATU_REGION_INDEX3 0x3
>> >> +
>> >> +// PCIe Controller configuration
>> >> +#define NUM_PCIE_CONTROLLER FixedPcdGet32 (PcdNumPciController)
>> >> +#define PCI_LUT_DBG FixedPcdGet32 (PcdPcieLutDbg)
>> >> +#define PCI_LUT_BASE FixedPcdGet32 (PcdPcieLutBase)
>> >> +#define LTSSM_STATE_MASK 0x3f
>> >> +#define LTSSM_PCIE_L0 0x11
>> >> +#define PCI_LINK_CAP 0x7c
>> >> +#define PCI_LINK_SPEED_MASK 0xf
>> >> +#define PCI_CLASS_BRIDGE_PCI 0x6040010
>> >> +#define PCI_CLASS_DEVICE 0x8
>> >> +#define PCI_DBI_RO_WR_EN 0x8bc
>> >> +#define PCI_BASE_ADDRESS_0 0x10
>> >> +
>> >> +VOID GetSerdesProtocolMaps (UINT64 *);
>> >> +
>> >> +BOOLEAN IsSerDesLaneProtocolConfigured (UINT64, UINT16);
>> >> +
>> >> +#endif
>> >> diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
>> >> b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
>> >> new file mode 100644
>> >> index 0000000..acb614d
>> >> --- /dev/null
>> >> +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
>> >> @@ -0,0 +1,604 @@
>> >> +/** @file
>> >> + PCI Segment Library for NXP SoCs with multiple RCs
>> >> +
>> >> + Copyright 2018 NXP
>> >> +
>> >> + This program and the accompanying materials are licensed and
>> >> + made available under the terms and conditions of the BSD License
>> >> + which accompanies this distribution. The full text of the
>> >> + license may be found at
>> >> +
>> >https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
>> >nsou
>> >rce.org%2Flicenses%2Fbsd-
>>
>>license.php&data=02%7C01%7Cvabhav.sharma%40nxp.com%7C081a2ebc43af4
>a
>>
>>daaf8e08d5a62b9921%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C
>6
>>
>>36597628604269440&sdata=kt661HfkUD2E3sYswy0I4vVFTV3%2Fq%2FiM%2Bi
>W
>> >egCISP%2BU%3D&reserved=0.
>> >> +
>> >> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> >> + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
>EITHER
>> >EXPRESS OR IMPLIED.
>> >> +
>> >> +**/
>> >> +
>> >> +#include <Base.h>
>> >> +#include <Library/PciSegmentLib.h> #include <Library/BaseLib.h>
>> >> +#include <Library/DebugLib.h> #include <Library/IoLib.h> #include
>> >> +<Library/PcdLib.h> #include <Pcie.h>
>> >> +
>> >> +typedef enum {
>> >> + PciCfgWidthUint8 = 0,
>> >> + PciCfgWidthUint16,
>> >> + PciCfgWidthUint32,
>> >> + PciCfgWidthMax
>> >> +} PCI_CFG_WIDTH;
>> >> +
>> >> +/**
>> >> + Assert the validity of a PCI Segment address.
>> >> + A valid PCI Segment address should not contain 1's in bits
>> >> +28..31 and 48..63
>> >> +
>> >> + @param A The address to validate.
>> >> + @param M Additional bits to assert to be zero.
>> >> +
>> >> +**/
>> >> +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
>> >> + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
>> >> +
>> >> +/**
>> >> + Function to return PCIe Physical Address(PCIe view) or
>> >> +Controller
>> >> + Address(CPU view) for different RCs
>> >> +
>> >> + @param Address Address passed from bus layer.
>> >> + @param Segment Segment number for Root Complex.
>> >> +
>> >> + @return Return PCIe CPU or Controller address.
>> >> +
>> >> +**/
>> >> +STATIC
>> >> +UINT64
>> >> +PciSegmentLibGetConfigBase (
>> >> + IN UINT64 Address,
>> >> + IN UINT16 Segment
>> >> + )
>> >> +{
>> >> +
>> >> + switch (Segment) {
>> >> + // Root Complex 1
>> >> + case PCI_SEG0_NUM:
>> >> + // Reading bus number(bits 20-27)
>> >> + if ((Address >> 20) & 1) {
>> >> + return PCI_SEG0_MMIO_MEMBASE;
>> >> + } else {
>> >> + // On Bus 0 RCs are connected
>> >> + return PCI_SEG0_DBI_BASE;
>> >> + }
>> >> + // Root Complex 2
>> >> + case PCI_SEG1_NUM:
>> >> + // Reading bus number(bits 20-27)
>> >> + if ((Address >> 20) & 1) {
>> >> + return PCI_SEG1_MMIO_MEMBASE;
>> >> + } else {
>> >> + // On Bus 0 RCs are connected
>> >> + return PCI_SEG1_DBI_BASE;
>> >> + }
>> >> + // Root Complex 3
>> >> + case PCI_SEG2_NUM:
>> >> + // Reading bus number(bits 20-27)
>> >> + if ((Address >> 20) & 1) {
>> >> + return PCI_SEG2_MMIO_MEMBASE;
>> >> + } else {
>> >> + // On Bus 0 RCs are connected
>> >> + return PCI_SEG2_DBI_BASE;
>> >> + }
>> >> + // Root Complex 4
>> >> + case PCI_SEG3_NUM:
>> >> + // Reading bus number(bits 20-27)
>> >> + if ((Address >> 20) & 1) {
>> >> + return PCI_SEG3_MMIO_MEMBASE;
>> >> + } else {
>> >> + // On Bus 0 RCs are connected
>> >> + return PCI_SEG3_DBI_BASE;
>> >> + }
>> >> + default:
>> >> + return 0;
>> >> + }
>> >> +
>> >> +}
>> >> +
>> >> +/**
>> >> + Internal worker function to read a PCI configuration register.
>> >> +
>> >> + @param Address The address that encodes the Segment, PCI Bus, Device,
>> >> + Function and Register.
>> >> + @param Width The width of data to read
>> >> +
>> >> + @return The value read from the PCI configuration register.
>> >> +
>> >> +**/
>> >> +STATIC
>> >> +UINT32
>> >> +PciSegmentLibReadWorker (
>> >> + IN UINT64 Address,
>> >> + IN PCI_CFG_WIDTH Width
>> >> + )
>> >> +{
>> >> + UINT64 Base;
>> >> + UINT16 Offset;
>> >> + UINT16 Segment;
>> >> +
>> >> + //
>> >> + // Reading Segment number(47-32) bits in Address // Segment =
>> >> + (Address >> 32); // // Reading Function(12-0) bits in Address
>> >> + // Offset = (Address & 0xfff );
>> >> +
>> >> + Base = PciSegmentLibGetConfigBase (Address, Segment);
>> >> +
>> >> + //
>> >> + // ignore devices > 0 on bus 0
>> >> + //
>> >> + if ((Address & 0xff00000) == 0 && (Address & 0xf8000) != 0) {
>> >> + return MAX_UINT32;
>> >> + }
>> >> +
>> >> + //
>> >> + // ignore device > 0 on bus 1
>> >> + //
>> >> + if ((Address & 0xfe00000) == 0 && (Address & 0xf8000) != 0) {
>> >> + return MAX_UINT32;
>> >> + }
>> >> +
>> >> + switch (Width) {
>> >> + case PciCfgWidthUint8:
>> >> + return MmioRead8 (Base + (UINT8)Offset); case PciCfgWidthUint16:
>
>Sorry - I missed thie before but spotted it while scrolling through the reply: This
>cast of the offset is not only unnecessary, it is a bug - offset is masked with 0xfff
>above, meaning it carries 12 bits of value. Casting it to UINT8 discards the top 4.
>
>(And because an explicit cast amounts to the same as telling the compiler "I know
>better than you", this does not even result in a
>warning.)
>
>Anyway, please drop this and the subsequent two casts.
>
Yes you are right, Thanks.
I will update.
>> >> + return MmioRead16 (Base + (UINT16)Offset); case
>> >> + PciCfgWidthUint32:
>> >> + return MmioRead32 (Base + (UINT32)Offset);
>> >> + default:
>> >> + ASSERT (FALSE);
>> >> + }
>> >> +
>> >> + return CHAR_NULL;
>> >> +}
>> >> +
>> >> +/**
>> >> + Internal worker function to writes a PCI configuration register.
>> >> +
>> >> + @param Address The address that encodes the Segment, PCI Bus, Device,
>> >> + Function and Register.
>> >> + @param Width The width of data to write
>> >> + @param Data The value to write.
>> >> +
>> >> + @return The value written to the PCI configuration register.
>> >> +
>> >> +**/
>> >> +STATIC
>> >> +UINT32
>> >> +PciSegmentLibWriteWorker (
>> >> + IN UINT64 Address,
>> >> + IN PCI_CFG_WIDTH Width,
>> >> + IN UINT32 Data
>> >> + )
>> >> +{
>> >> + UINT64 Base;
>> >> + UINT32 Offset;
>> >> + UINT16 Segment;
>> >> +
>> >> + //
>> >> + // Reading Segment number(47-32 bits) in Address Segment =
>> >> + (Address >> 32); // // Reading Function(12-0 bits) in Address
>> >> + // Offset = (Address & 0xfff );
>> >
>> >Spurious space after 0xfff.
>> Alright, Thanks.
>> Same applies to PciSegmentLibReadWorker()
>> >
>> >Could we have some macros and #defines instead of live-coded values
>> >in this function?
>>
>> Sure, I assume Similar changes in PciSegmentLibReadWorker() required.
>
>Err, yes please.
>Umm, actually - the base functionality of those two functions are identical (which
>is why I must have missed the ReadWorker with a double page-down). Could that
>be turned into a helper function that calculates addresses and offsets, called by
>readworker and writeworker separately?
Ok, Yes I will incorporate the changes for offset and address calculation.
>
>> >> +
>> >> + Base = PciSegmentLibGetConfigBase (Address, Segment);
>> >> +
>> >> + //
>> >> + // ignore devices > 0 on bus 0
>> >> + //
>> >> + if ((Address & 0xff00000) == 0 && (Address & 0xf8000) != 0) {
>> >> + return Data;
>> >> + }
>> >> +
>> >> + //
>> >> + // ignore device > 0 on bus 1
>> >> + //
>> >> + if ((Address & 0xfe00000) == 0 && (Address & 0xf8000) != 0) {
>> >> + return MAX_UINT32;
>> >> + }
>> >> +
>> >> + switch (Width) {
>> >> + case PciCfgWidthUint8:
>> >> + MmioWrite8 (Base + (UINT8)Offset, Data);
>
>(Same problem with the casts here.)
Ok,I will update
Thanks.
>
>> >> + break;
>> >> + case PciCfgWidthUint16:
>> >> + MmioWrite16 (Base + (UINT16)Offset, Data);
>> >> + break;
>> >> + case PciCfgWidthUint32:
>> >> + MmioWrite32 (Base + (UINT16)Offset, Data);
>
>/
> Leif
>
>> >> + break;
>> >> + default:
>> >> + ASSERT (FALSE);
>> >> + }
>> >> +
>> >> + return Data;
>> >> +}
>> >> +
>> >> +/**
>> >> + Register a PCI device so PCI configuration registers may be
>> >> +accessed after
>> >> + SetVirtualAddressMap().
>> >> +
>> >> + If any reserved bits in Address are set, then ASSERT().
>> >> +
>> >> + @param Address The address that encodes the PCI Bus, Device,
>> >> + Function and Register.
>> >> +
>> >> + @retval RETURN_SUCCESS The PCI device was registered for
>runtime
>> >access.
>> >> + @retval RETURN_UNSUPPORTED An attempt was made to call this
>> >function
>> >> + after ExitBootServices().
>> >> + @retval RETURN_UNSUPPORTED The resources required to access the
>> >PCI device
>> >> + at runtime could not be mapped.
>> >> + @retval RETURN_OUT_OF_RESOURCES There are not enough resources
>> >available to
>> >> + complete the registration.
>> >> +
> >> +**/
>> >> +RETURN_STATUS
>> >> +EFIAPI
>> >> +PciSegmentRegisterForRuntimeAccess (
>> >> + IN UINTN Address
>> >> + )
>> >> +{
>> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
>> >> + return RETURN_UNSUPPORTED;
>> >> +}
>> >> +
>> >> +/**
>> >> + Reads an 8-bit PCI configuration register.
>> >> +
>> >> + Reads and returns the 8-bit PCI configuration register specified by Address.
>> >> +
>> >> + If any reserved bits in Address are set, then ASSERT().
>> >> +
>> >> + @param Address The address that encodes the PCI Segment, Bus,
>Device,
>> >Function,
>> >> + and Register.
>> >> +
>> >> + @return The 8-bit PCI configuration register specified by Address.
>> >> +
>> >> +**/
>> >> +UINT8
>> >> +EFIAPI
>> >> +PciSegmentRead8 (
>> >> + IN UINT64 Address
>> >> + )
>> >> +{
>> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
>> >> +
>> >> + return (UINT8) PciSegmentLibReadWorker (Address,
>> >> +PciCfgWidthUint8); }
>> >> +
>> >> +/**
>> >> + Writes an 8-bit PCI configuration register.
>> >> +
>> >> + Writes the 8-bit PCI configuration register specified by Address
>> >> + with the value
>> >specified by Value.
>> >> + Value is returned. This function must guarantee that all PCI
>> >> + read and write
>> >operations are serialized.
>> >> +
>> >> + If any reserved bits in Address are set, then ASSERT().
>> >> +
>> >> + @param Address The address that encodes the PCI Segment, Bus,
>Device,
>> >Function, and Register.
>> >> + @param Value The value to write.
>> >> +
>> >> + @return The value written to the PCI configuration register.
>> >> +
>> >> +**/
>> >> +UINT8
>> >> +EFIAPI
>> >> +PciSegmentWrite8 (
>> >> + IN UINT64 Address,
>> >> + IN UINT8 Value
>> >> + )
>> >> +{
>> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
>> >> +
>> >> + return (UINT8) PciSegmentLibWriteWorker (Address,
>> >> +PciCfgWidthUint8, Value); }
>> >> +
>> >> +/**
>> >> + Reads a 16-bit PCI configuration register.
>> >> +
>> >> + Reads and returns the 16-bit PCI configuration register specified by
>Address.
>> >> +
>> >> + If any reserved bits in Address are set, then ASSERT().
>> >> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> >> +
>> >> + @param Address The address that encodes the PCI Segment, Bus,
>Device,
>> >Function, and Register.
>> >> +
>> >> + @return The 16-bit PCI configuration register specified by Address.
>> >> +
>> >> +**/
>> >> +UINT16
>> >> +EFIAPI
>> >> +PciSegmentRead16 (
>> >> + IN UINT64 Address
>> >> + )
>> >> +{
>> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
>> >> +
>> >> + return (UINT16) PciSegmentLibReadWorker (Address,
>> >> +PciCfgWidthUint16); }
>> >> +
>> >> +/**
>> >> + Writes a 16-bit PCI configuration register.
>> >> +
>> >> + Writes the 16-bit PCI configuration register specified by
>> >> + Address with the value specified by Value.
>> >> +
>> >> + Value is returned.
>> >> +
>> >> + If any reserved bits in Address are set, then ASSERT().
>> >> + If Address is not aligned on a 16-bit boundary, then ASSERT().
>> >> +
>> >> + @param Address The address that encodes the PCI Segment, Bus,
>Device,
>> >Function, and Register.
>> >> + @param Value The value to write.
>> >> +
>> >> + @return The parameter of Value.
>> >> +
>> >> +**/
>> >> +UINT16
>> >> +EFIAPI
>> >> +PciSegmentWrite16 (
>> >> + IN UINT64 Address,
>> >> + IN UINT16 Value
>> >> + )
>> >> +{
>> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
>> >> +
>> >> + return (UINT16) PciSegmentLibWriteWorker (Address,
>> >> +PciCfgWidthUint16, Value); }
>> >> +
>> >> +/**
>> >> + Reads a 32-bit PCI configuration register.
>> >> +
>> >> + Reads and returns the 32-bit PCI configuration register specified by
>Address.
>> >> +
>> >> + If any reserved bits in Address are set, then ASSERT().
>> >> + If Address is not aligned on a 32-bit boundary, then ASSERT().
>> >> +
>> >> + @param Address The address that encodes the PCI Segment, Bus,
>Device,
>> >Function,
>> >> + and Register.
>> >> +
>> >> + @return The 32-bit PCI configuration register specified by Address.
>> >> +
>> >> +**/
>> >> +UINT32
>> >> +EFIAPI
>> >> +PciSegmentRead32 (
>> >> + IN UINT64 Address
>> >> + )
>> >> +{
>> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
>> >> +
>> >> + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32); }
>> >> +
>> >> +/**
>> >> + Writes a 32-bit PCI configuration register.
>> >> +
>> >> + Writes the 32-bit PCI configuration register specified by
>> >> + Address with the value specified by Value.
>> >> +
>> >> + Value is returned.
>> >> +
>> >> + If any reserved bits in Address are set, then ASSERT().
>> >> + If Address is not aligned on a 32-bit boundary, then ASSERT().
>> >> +
>> >> + @param Address The address that encodes the PCI Segment, Bus,
>Device,
>> >> + Function, and Register.
>> >> + @param Value The value to write.
>> >> +
>> >> + @return The parameter of Value.
>> >> +
>> >> +**/
>> >> +UINT32
>> >> +EFIAPI
>> >> +PciSegmentWrite32 (
>> >> + IN UINT64 Address,
>> >> + IN UINT32 Value
>> >> + )
>> >> +{
>> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
>> >> +
>> >> + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32,
>> >> +Value); }
>> >> +
>> >> +/**
>> >> + Reads a range of PCI configuration registers into a caller supplied buffer.
>> >> +
>> >> + Reads the range of PCI configuration registers specified by
>> >> + StartAddress and Size into the buffer specified by Buffer. This
>> >> + function only allows the PCI configuration registers from a
>> >> + single PCI function to be read. Size is returned.
>> >> +
>> >> + If any reserved bits in StartAddress are set, then ASSERT().
>> >> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
>> >> + If Size > 0 and Buffer is NULL, then ASSERT().
>> >> +
>> >> + @param StartAddress The starting address that encodes the PCI
>> >> + Segment,
>> >Bus,
>> >> + Device, Function and Register.
>> >> + @param Size The size in bytes of the transfer.
>> >> + @param Buffer The pointer to a buffer receiving the data read.
>> >> +
>> >> + @return Size
>> >> +
>> >> +**/
>> >> +UINTN
>> >> +EFIAPI
>> >> +PciSegmentReadBuffer (
>> >> + IN UINT64 StartAddress,
>> >> + IN UINTN Size,
>> >> + OUT VOID *Buffer
>> >> + )
>> >> +{
>> >> + UINTN ReturnValue;
>> >> +
>> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); // 0xFFF
>> >> + is used as limit for 4KB config space ASSERT (((StartAddress &
>> >> + 0xFFF)
>> >> + + Size) <= SIZE_4KB);
>> >> +
>> >> + if (Size == 0) {
>> >> + return Size;
>> >> + }
>> >> +
>> >> + ASSERT (Buffer != NULL);
>> >> +
>> >> + //
>> >> + // Save Size for return
>> >> + //
>> >> + ReturnValue = Size;
>> >> +
>> >> + if ((StartAddress & BIT0) != 0) {
>> >> + //
>> >> + // Read a byte if StartAddress is byte aligned
>> >> + //
>> >> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
>> >
>> >Why volatile on Buffer?
>> I took reference from Socionext, Not required .
>> PCIe region has device attribute.
>> >
>> >> + StartAddress += sizeof (UINT8);
>> >> + Size -= sizeof (UINT8);
>> >> + Buffer = (UINT8*)Buffer + BIT0;
>> >
>> >sizeof (UINT8) instead of BIT0?
>> >
>> >And this is a VOID *, so can just write.
>> > Buffer += sizeof (UINT8);
>> >
>> Yes,Sure.
>> >> + }
>> >> +
>> >> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
>> >> + //
>> >> + // Read a word if StartAddress is word aligned
>> >> + //
>> >> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
>> >> + StartAddress += sizeof (UINT16);
>> >> + Size -= sizeof (UINT16);
>> >> + Buffer = (UINT16*)Buffer + BIT0;
>> >
>> >That is a very confusing use of pointer arithmetic.
>> > Buffer += sizeof (UINT16);
>> >
>> Agree, alright.
>> >> + }
>> >> +
>> >> + while (Size >= sizeof (UINT32)) {
>> >> + //
>> >> + // Read as many double words as possible
>> >> + //
>> >> + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
>> >> + StartAddress += sizeof (UINT32);
>> >> + Size -= sizeof (UINT32);
>> >> + Buffer = (UINT32*)Buffer + BIT0;
>> >
>> > Buffer += sizeof (UINT32);
>> Ok
>> >
>> >> + }
>> >> +
>> >> + if (Size >= sizeof (UINT16)) {
>> >> + //
>> >> + // Read the last remaining word if exist
>> >> + //
>> >> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
>> >> + StartAddress += sizeof (UINT16);
>> >> + Size -= sizeof (UINT16);
>> >> + Buffer = (UINT16*)Buffer + BIT0;
>> >
>> > Buffer += sizeof (UINT16);
>> Ok
>> >
>> >> + }
>> >> +
>> >> + if (Size >= sizeof (UINT8)) {
>> >> + //
>> >> + // Read the last remaining byte if exist
>> >> + //
>> >> + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
>> >
>> >There is that scary volatile again.
>> Not required.
>> >
>> >> + }
>> >> +
>> >> + return ReturnValue;
>> >> +}
>> >> +
>> >> +
>> >> +/**
>> >> + Copies the data in a caller supplied buffer to a specified range
>> >> +of PCI
>> >> + configuration space.
>> >> +
>> >> + Writes the range of PCI configuration registers specified by
>> >> + StartAddress and Size from the buffer specified by Buffer. This
>> >> + function only allows the PCI configuration registers from a
>> >> + single PCI function to be written. Size is returned.
>> >> +
>> >> + If any reserved bits in StartAddress are set, then ASSERT().
>> >> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
>> >> + If Size > 0 and Buffer is NULL, then ASSERT().
>> >> +
>> >> + @param StartAddress The starting address that encodes the PCI
>> >> + Segment,
>> >Bus,
>> >> + Device, Function and Register.
>> >> + @param Size The size in bytes of the transfer.
>> >> + @param Buffer The pointer to a buffer containing the data to write.
>> >> +
>> >> + @return The parameter of Size.
>> >> +
>> >> +**/
>> >> +UINTN
>> >> +EFIAPI
>> >> +PciSegmentWriteBuffer (
>> >> + IN UINT64 StartAddress,
>> >> + IN UINTN Size,
>> >> + IN VOID *Buffer
>> >> + )
>> >> +{
>> >> + UINTN ReturnValue;
>> >> +
>> >> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); // 0xFFF
>> >> + is used as limit for 4KB config space ASSERT (((StartAddress &
>> >> + 0xFFF)
>> >> + + Size) <= SIZE_4KB);
>> >
>> >Can you use (SIZE_4KB - 1) instead of 0xFFF?
>> Yes,Sure.
>> >
>> >> +
>> >> + if (Size == 0) {
>> >> + return Size;
>> >> + }
>> >> +
>> >> + ASSERT (Buffer != NULL);
>> >> +
>> >> + //
>> >> + // Save Size for return
>> >> + //
>> >> + ReturnValue = Size;
>> >> +
>> >> + if ((StartAddress & BIT0) != 0) {
>> >> + //
>> >> + // Write a byte if StartAddress is byte aligned
>> >> + //
>> >> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
>> >> + StartAddress += sizeof (UINT8);
>> >> + Size -= sizeof (UINT8);
>> >> + Buffer = (UINT8*)Buffer + BIT0;
>> >
>> >Same comments for Buffer pointer update as previous function, throughout.
>> Ok
>> >
>> >/
>> > Leif
>> >
>> >> + }
>> >> +
>> >> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
>> >> + //
>> >> + // Write a word if StartAddress is word aligned
>> >> + //
>> >> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
>> >> + StartAddress += sizeof (UINT16);
>> >> + Size -= sizeof (UINT16);
>> >> + Buffer = (UINT16*)Buffer + BIT0; }
>> >> +
>> >> + while (Size >= sizeof (UINT32)) {
>> >> + //
>> >> + // Write as many double words as possible
>> >> + //
>> >> + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
>> >> + StartAddress += sizeof (UINT32);
>> >> + Size -= sizeof (UINT32);
>> >> + Buffer = (UINT32*)Buffer + BIT0; }
>> >> +
>> >> + if (Size >= sizeof (UINT16)) {
>> >> + //
>> >> + // Write the last remaining word if exist
>> >> + //
>> >> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
>> >> + StartAddress += sizeof (UINT16);
>> >> + Size -= sizeof (UINT16);
>> >> + Buffer = (UINT16*)Buffer + BIT0; }
>> >> +
>> >> + if (Size >= sizeof (UINT8)) {
>> >> + //
>> >> + // Write the last remaining byte if exist
>> >> + //
>> >> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); }
>> >> +
>> >> + return ReturnValue;
>> >> +}
>> >> diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>> >> b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>> >> new file mode 100644
>> >> index 0000000..1ac83d4
>> >> --- /dev/null
>> >> +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>> >> @@ -0,0 +1,41 @@
>> >> +## @file
>> >> +# PCI Segment Library for NXP SoCs with multiple RCs # #
>> >> +Copyright
>> >> +2018 NXP # # This program and the accompanying materials # are
>> >> +licensed and made available under the terms and conditions of the
>> >> +BSD License # which accompanies this distribution. The full text
>> >> +of the license may be found at #
>> >https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
>> >nsou
>> >rce.org%2Flicenses%2Fbsd-
>>
>>license.php&data=02%7C01%7Cvabhav.sharma%40nxp.com%7C081a2ebc43af4
>a
>>
>>daaf8e08d5a62b9921%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C
>6
>>
>>36597628604269440&sdata=kt661HfkUD2E3sYswy0I4vVFTV3%2Fq%2FiM%2Bi
>W
>> >egCISP%2BU%3D&reserved=0.
>> >> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> >> +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
>> >EITHER EXPRESS OR IMPLIED.
>> >> +#
>> >> +#
>> >> +##
>> >> +
>> >> +[Defines]
>> >> + INF_VERSION = 0x0001001A
>> >> + BASE_NAME = PciSegmentLib
>> >> + FILE_GUID = c9f59261-5a60-4a4c-82f6-1f520442e100
>> >> + MODULE_TYPE = BASE
>> >> + VERSION_STRING = 1.0
>> >> + LIBRARY_CLASS = PciSegmentLib
>> >> +
>> >> +[Sources]
>> >> + PciSegmentLib.c
>> >> +
>> >> +[Packages]
>> >> + MdePkg/MdePkg.dec
>> >> + Silicon/NXP/NxpQoriqLs.dec
>> >> +
>> >> +[LibraryClasses]
>> >> + BaseLib
>> >> + DebugLib
>> >> + IoLib
>> >> + PcdLib
>> >> +
>> >> +[Pcd]
>> >> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
>> >> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
>> >> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
>> >> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
>> >> --
>> >> 1.9.1
>> >>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 33/39] Silicon/NXP: Implement PciHostBridgeLib support
2018-04-20 14:54 ` Leif Lindholm
@ 2018-04-24 12:32 ` Vabhav Sharma
0 siblings, 0 replies; 254+ messages in thread
From: Vabhav Sharma @ 2018-04-24 12:32 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi
>-----Original Message-----
>From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
>Sent: Friday, April 20, 2018 8:24 PM
>To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
><udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
><vabhav.sharma@nxp.com>
>Subject: Re: [PATCH edk2-platforms 33/39] Silicon/NXP: Implement
>PciHostBridgeLib support
>
>My only comment in addition to Ard's comments/questions:
>Use same endianness handling here as for preceding patches?
>
>/
> Leif
On NXP SoCs PCIe IP is LE except link state register access for which endianness is taken care.
>
>On Fri, Feb 16, 2018 at 02:20:29PM +0530, Meenakshi wrote:
>> From: Vabhav <vabhav.sharma@nxp.com>
>>
>> Implement the library that exposes the PCIe root complexes to the
>> generic PCI host bridge driver,Putting SoC Specific low level init
>> code for the RCs.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
>> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>> ---
>> .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 618
>+++++++++++++++++++++
>> .../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 50 ++
>> 2 files changed, 668 insertions(+)
>> create mode 100644
>> Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
>> create mode 100644
>> Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>>
>> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
>> b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
>> new file mode 100644
>> index 0000000..e6f9b7c
>> --- /dev/null
>> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
>> @@ -0,0 +1,618 @@
>> +/** @file
>> + PCI Host Bridge Library instance for NXP SoCs
>> +
>> + Copyright 2018 NXP
>> +
>> + This program and the accompanying materials are licensed and made
>> + available under the terms and conditions of the BSD License which
>> + accompanies this distribution. The full text of the license may be
>> + found at
>https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fopensou
>rce.org%2Flicenses%2Fbsd-
>license.php&data=02%7C01%7Cvabhav.sharma%40nxp.com%7C90628d666bad4
>6bf6dde08d5a6ce8fe0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C
>636598328488287967&sdata=6Jwkzr%2BkvDURRF%2FQ8rvSN1OBggJNg14NGh
>W5s3WkuFM%3D&reserved=0.
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#include <PiDxe.h>
>> +#include <IndustryStandard/Pci22.h>
>> +#include <Library/BeIoLib.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/DevicePathLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/MemoryAllocationLib.h> #include <Library/PcdLib.h>
>> +#include <Library/PciHostBridgeLib.h> #include <Pcie.h> #include
>> +<Protocol/PciHostBridgeResourceAllocation.h>
>> +#include <Protocol/PciRootBridgeIo.h>
>> +
>> +#pragma pack(1)
>> +typedef struct {
>> + ACPI_HID_DEVICE_PATH AcpiDevicePath;
>> + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; }
>> +EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; #pragma pack ()
>> +
>> +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH
>> +mEfiPciRootBridgeDevicePath[] = {
>> + {
>> + {
>> + {
>> + ACPI_DEVICE_PATH,
>> + ACPI_DP,
>> + {
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
>> + }
>> + },
>> + EISA_PNP_ID (0x0A08), // PCI Express
>> + PCI_SEG0_NUM
>> + },
>> +
>> + {
>> + END_DEVICE_PATH_TYPE,
>> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
>> + {
>> + END_DEVICE_PATH_LENGTH,
>> + 0
>> + }
>> + }
>> + },
>> + {
>> + {
>> + {
>> + ACPI_DEVICE_PATH,
>> + ACPI_DP,
>> + {
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
>> + }
>> + },
>> + EISA_PNP_ID (0x0A08), // PCI Express
>> + PCI_SEG1_NUM
>> + },
>> +
>> + {
>> + END_DEVICE_PATH_TYPE,
>> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
>> + {
>> + END_DEVICE_PATH_LENGTH,
>> + 0
>> + }
>> + }
>> + },
>> + {
>> + {
>> + {
>> + ACPI_DEVICE_PATH,
>> + ACPI_DP,
>> + {
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
>> + }
>> + },
>> + EISA_PNP_ID (0x0A08), // PCI Express
>> + PCI_SEG2_NUM
>> + },
>> +
>> + {
>> + END_DEVICE_PATH_TYPE,
>> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
>> + {
>> + END_DEVICE_PATH_LENGTH,
>> + 0
>> + }
>> + }
>> + },
>> + {
>> + {
>> + {
>> + ACPI_DEVICE_PATH,
>> + ACPI_DP,
>> + {
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
>> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
>> + }
>> + },
>> + EISA_PNP_ID (0x0A08), // PCI Express
>> + PCI_SEG3_NUM
>> + },
>> +
>> + {
>> + END_DEVICE_PATH_TYPE,
>> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
>> + {
>> + END_DEVICE_PATH_LENGTH,
>> + 0
>> + }
>> + }
>> + }
>> +};
>> +
>> +STATIC
>> +GLOBAL_REMOVE_IF_UNREFERENCED
>> +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
>> + L"Mem", L"I/O", L"Bus"
>> +};
>> +
>> +#define PCI_ALLOCATION_ATTRIBUTES
>EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | \
>> +
>> +EFI_PCI_HOST_BRIDGE_MEM64_DECODE
>> +
>> +#define PCI_SUPPORT_ATTRIBUTES EFI_PCI_ATTRIBUTE_ISA_IO_16 | \
>> + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
>> + EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
>> + EFI_PCI_ATTRIBUTE_VGA_IO_16 | \
>> +
>> +EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
>> +
>> +PCI_ROOT_BRIDGE mPciRootBridges[] = {
>> + {
>> + PCI_SEG0_NUM, // Segment
>> + PCI_SUPPORT_ATTRIBUTES, // Supports
>> + PCI_SUPPORT_ATTRIBUTES, // Attributes
>> + FALSE, // DmaAbove4G
>> + FALSE, // NoExtendedConfigSpace
>> + FALSE, // ResourceAssigned
>> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
>> + { PCI_SEG0_BUSNUM_MIN,
>> + PCI_SEG0_BUSNUM_MAX }, // Bus
>> + { PCI_SEG0_PORTIO_MIN,
>> + PCI_SEG0_PORTIO_MAX }, // Io
>> + { PCI_SEG0_MMIO32_MIN,
>> + PCI_SEG0_MMIO32_MAX }, // Mem
>> + { PCI_SEG0_MMIO64_MIN,
>> + PCI_SEG0_MMIO64_MAX }, // MemAbove4G
>> + { MAX_UINT64, 0x0 }, // PMem
>> + { MAX_UINT64, 0x0 }, // PMemAbove4G
>> + (EFI_DEVICE_PATH_PROTOCOL
>> +*)&mEfiPciRootBridgeDevicePath[PCI_SEG0_NUM]
>> + }, {
>> + PCI_SEG1_NUM, // Segment
>> + PCI_SUPPORT_ATTRIBUTES, // Supports
>> + PCI_SUPPORT_ATTRIBUTES, // Attributes
>> + FALSE, // DmaAbove4G
>> + FALSE, // NoExtendedConfigSpace
>> + FALSE, // ResourceAssigned
>> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
>> + { PCI_SEG1_BUSNUM_MIN,
>> + PCI_SEG1_BUSNUM_MAX }, // Bus
>> + { PCI_SEG1_PORTIO_MIN,
>> + PCI_SEG1_PORTIO_MAX }, // Io
>> + { PCI_SEG1_MMIO32_MIN,
>> + PCI_SEG1_MMIO32_MAX }, // Mem
>> + { PCI_SEG1_MMIO64_MIN,
>> + PCI_SEG1_MMIO64_MAX }, // MemAbove4G
>> + { MAX_UINT64, 0x0 }, // PMem
>> + { MAX_UINT64, 0x0 }, // PMemAbove4G
>> + (EFI_DEVICE_PATH_PROTOCOL
>> +*)&mEfiPciRootBridgeDevicePath[PCI_SEG1_NUM]
>> + }, {
>> + PCI_SEG2_NUM, // Segment
>> + PCI_SUPPORT_ATTRIBUTES, // Supports
>> + PCI_SUPPORT_ATTRIBUTES, // Attributes
>> + FALSE, // DmaAbove4G
>> + FALSE, // NoExtendedConfigSpace
>> + FALSE, // ResourceAssigned
>> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
>> + { PCI_SEG2_BUSNUM_MIN,
>> + PCI_SEG2_BUSNUM_MAX }, // Bus
>> + { PCI_SEG2_PORTIO_MIN,
>> + PCI_SEG2_PORTIO_MAX }, // Io
>> + { PCI_SEG2_MMIO32_MIN,
>> + PCI_SEG2_MMIO32_MAX }, // Mem
>> + { PCI_SEG2_MMIO64_MIN,
>> + PCI_SEG2_MMIO64_MAX }, // MemAbove4G
>> + { MAX_UINT64, 0x0 }, // PMem
>> + { MAX_UINT64, 0x0 }, // PMemAbove4G
>> + (EFI_DEVICE_PATH_PROTOCOL
>> +*)&mEfiPciRootBridgeDevicePath[PCI_SEG2_NUM]
>> + }, {
>> + PCI_SEG3_NUM, // Segment
>> + PCI_SUPPORT_ATTRIBUTES, // Supports
>> + PCI_SUPPORT_ATTRIBUTES, // Attributes
>> + FALSE, // DmaAbove4G
>> + FALSE, // NoExtendedConfigSpace
>> + FALSE, // ResourceAssigned
>> + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes
>> + { PCI_SEG3_BUSNUM_MIN,
>> + PCI_SEG3_BUSNUM_MAX }, // Bus
>> + { PCI_SEG3_PORTIO_MIN,
>> + PCI_SEG3_PORTIO_MAX }, // Io
>> + { PCI_SEG3_MMIO32_MIN,
>> + PCI_SEG3_MMIO32_MAX }, // Mem
>> + { PCI_SEG3_MMIO64_MIN,
>> + PCI_SEG3_MMIO64_MAX }, // MemAbove4G
>> + { MAX_UINT64, 0x0 }, // PMem
>> + { MAX_UINT64, 0x0 }, // PMemAbove4G
>> + (EFI_DEVICE_PATH_PROTOCOL
>> +*)&mEfiPciRootBridgeDevicePath[PCI_SEG3_NUM]
>> + }
>> +};
>> +
>> +/**
>> + Function to set-up iATU outbound window for PCIe controller
>> +
>> + @param Dbi Address of PCIe host controller.
>> + @param Idx Index of iATU outbound window.
>> + @param Type Type(Cfg0/Cfg1/Mem/IO) of iATU outbound window.
>> + @param Phys PCIe controller phy address for outbound window.
>> + @param BusAdr PCIe controller bus address for outbound window.
>> + @param Pcie Size of PCIe controller space(Cfg0/Cfg1/Mem/IO).
>> +
>> +**/
>> +STATIC
>> +VOID
>> +PcieIatuOutboundSet (
>> + IN EFI_PHYSICAL_ADDRESS Dbi,
>> + IN UINT32 Idx,
>> + IN UINT32 Type,
>> + IN UINT64 Phys,
>> + IN UINT64 BusAddr,
>> + IN UINT64 Size
>> + )
>> +{
>> + MmioWrite32 (Dbi + IATU_VIEWPORT_OFF,
>> + (UINT32)(IATU_VIEWPORT_OUTBOUND | Idx));
>> + MmioWrite32 (Dbi + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
>> + (UINT32)Phys);
>> + MmioWrite32 (Dbi + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
>> + (UINT32)(Phys >> 32));
>> + MmioWrite32 (Dbi + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
>> + (UINT32)(Phys + Size - BIT0));
>> + MmioWrite32 (Dbi + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
>> + (UINT32)BusAddr);
>> + MmioWrite32 (Dbi + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
>> + (UINT32)(BusAddr >> 32));
>> + MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
>> + (UINT32)Type);
>> + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
>> + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN);
>> +}
>> +
>> +/**
>> + Function to check PCIe controller LTSSM state
>> +
>> + @param Pcie Address of PCIe host controller.
>> +
>> +**/
>> +STATIC
>> +INTN
>> +PcieLinkState (
>> + IN EFI_PHYSICAL_ADDRESS Pcie
>> + )
>> +{
>> + UINT32 State;
>> +
>> + //
>> + // Reading PCIe controller LTSSM state // if (FeaturePcdGet
>> + (PcdPciLutBigEndian)) {
>> + State = BeMmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
>> + LTSSM_STATE_MASK;
>> + } else {
>> + State = MmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
>> + LTSSM_STATE_MASK;
>> + }
>> +
>> + if (State < LTSSM_PCIE_L0) {
>> + DEBUG ((DEBUG_INFO," Pcie Link error. LTSSM=0x%2x\n", State));
>> + return EFI_SUCCESS;
>> + }
>> +
>> + return EFI_UNSUPPORTED;
>> +}
>> +
>> +/**
>> + Helper function to check PCIe link state
>> +
>> + @param Pcie Address of PCIe host controller.
>> +
>> +**/
>> +STATIC
>> +INTN
>> +PcieLinkUp (
>> + IN EFI_PHYSICAL_ADDRESS Pcie
>> + )
>> +{
>> + INTN State;
>> + UINT32 Cap;
>> +
>> + State = PcieLinkState (Pcie);
>> + if (State) {
>> + return State;
>> + }
>> +
>> + //
>> + // Try to download speed to gen1
>> + //
>> + Cap = MmioRead32 ((UINTN)Pcie + PCI_LINK_CAP);
>> + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, (UINT32)(Cap &
>> + (~PCI_LINK_SPEED_MASK)) | BIT0); State = PcieLinkState (Pcie); if
>> + (State) {
>> + return State;
>> + }
>> +
>> + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, Cap);
>> +
>> + return EFI_SUCCESS;
>> +}
>> +
>> +/**
>> + This function checks whether PCIe is enabled or not
>> + depending upon SoC serdes protocol map
>> +
>> + @param PcieNum PCIe number.
>> +
>> + @return The PCIe number enabled in map.
>> + @return FALSE PCIe number is disabled in map.
>> +
>> +**/
>> +STATIC
>> +BOOLEAN
>> +IsPcieNumEnabled(
>> + IN UINTN PcieNum
>> + )
>> +{
>> + UINT64 SerDes1ProtocolMap;
>> +
>> + SerDes1ProtocolMap = 0x0;
>> +
>> + //
>> + // Reading serdes map
>> + //
>> + GetSerdesProtocolMaps (&SerDes1ProtocolMap);
>> +
>> + //
>> + // Verify serdes line is configured in the map // if (PcieNum <
>> + NUM_PCIE_CONTROLLER) {
>> + return IsSerDesLaneProtocolConfigured (SerDes1ProtocolMap,
>> + (PcieNum + BIT0)); } else {
>> + DEBUG ((DEBUG_ERROR, "Device not supported\n")); }
>> +
>> + return FALSE;
>> +}
>> +
>> +/**
>> + Function to set-up iATU outbound window for PCIe controller
>> +
>> + @param Pcie Address of PCIe host controller
>> + @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
>> + @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
>> + @param MemBase PCIe controller phy address Memory Space.
>> + @param IoBase PCIe controller phy address IO Space.
>> +**/
>> +STATIC
>> +VOID
>> +PcieSetupAtu (
>> + IN EFI_PHYSICAL_ADDRESS Pcie,
>> + IN EFI_PHYSICAL_ADDRESS Cfg0Base,
>> + IN EFI_PHYSICAL_ADDRESS Cfg1Base,
>> + IN EFI_PHYSICAL_ADDRESS MemBase,
>> + IN EFI_PHYSICAL_ADDRESS IoBase
>> + )
>> +{
>> +
>> + //
>> + // iATU : OUTBOUND WINDOW 0 : CFG0
>> + //
>> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX0,
>> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
>> + Cfg0Base,
>> + SEG_CFG_BUS,
>> + SEG_CFG_SIZE);
>> +
>> + //
>> + // iATU : OUTBOUND WINDOW 1 : CFG1
>> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX1,
>> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
>> + Cfg1Base,
>> + SEG_CFG_BUS,
>> + SEG_CFG_SIZE); // // iATU 2 : OUTBOUND
>> + WINDOW 2 : MEM // PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX2,
>> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
>> + MemBase,
>> + SEG_MEM_BUS,
>> + SEG_MEM_SIZE);
>> +
>> + //
>> + // iATU 3 : OUTBOUND WINDOW 3: IO
>> + //
>> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX3,
>> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
>> + IoBase,
>> + SEG_IO_BUS,
>> + SEG_IO_SIZE);
>> +
>> +}
>> +
>> +/**
>> + Helper function to set-up PCIe controller
>> +
>> + @param Pcie Address of PCIe host controller
>> + @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
>> + @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
>> + @param MemBase PCIe controller phy address Memory Space.
>> + @param IoBase PCIe controller phy address IO Space.
>> +
>> +**/
>> +STATIC
>> +VOID
>> +PcieSetupCntrl (
>> + IN EFI_PHYSICAL_ADDRESS Pcie,
>> + IN EFI_PHYSICAL_ADDRESS Cfg0Base,
>> + IN EFI_PHYSICAL_ADDRESS Cfg1Base,
>> + IN EFI_PHYSICAL_ADDRESS MemBase,
>> + IN EFI_PHYSICAL_ADDRESS IoBase
>> + )
>> +{
>> + //
>> + // iATU outbound set-up
>> + //
>> + PcieSetupAtu (Pcie, Cfg0Base, Cfg1Base, MemBase, IoBase);
>> +
>> + //
>> + // program correct class for RC
>> + //
>> + MmioWrite32 ((UINTN)Pcie + PCI_BASE_ADDRESS_0, (BIT0 - BIT0));
>> + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)BIT0);
>> + MmioWrite32 ((UINTN)Pcie + PCI_CLASS_DEVICE,
>> +(UINT32)PCI_CLASS_BRIDGE_PCI);
>> + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)(BIT0 -
>> +BIT0)); }
>> +
>> +/**
>> + Return all the root bridge instances in an array.
>> +
>> + @param Count Return the count of root bridge instances.
>> +
>> + @return All the root bridge instances in an array.
>> +
>> +**/
>> +PCI_ROOT_BRIDGE *
>> +EFIAPI
>> +PciHostBridgeGetRootBridges (
>> + OUT UINTN *Count
>> + )
>> +{
>> + UINTN Idx;
>> + INTN LinkUp;
>> + UINT64 PciPhyMemAddr[NUM_PCIE_CONTROLLER];
>> + UINT64 PciPhyCfg0Addr[NUM_PCIE_CONTROLLER];
>> + UINT64 PciPhyCfg1Addr[NUM_PCIE_CONTROLLER];
>> + UINT64 PciPhyIoAddr[NUM_PCIE_CONTROLLER];
>> + UINT64 Regs[NUM_PCIE_CONTROLLER];
>> +
>> + *Count = 0;
>> +
>> + //
>> + // Filling local array for
>> + // PCIe controller Physical address space for Cfg0,Cfg1,Mem,IO //
>> + Host Contoller address // for (Idx = 0; Idx <
>> + NUM_PCIE_CONTROLLER; Idx++) {
>> + PciPhyMemAddr[Idx] = PCI_SEG0_PHY_MEM_BASE + (PCI_BASE_DIFF * Idx);
>> + PciPhyCfg0Addr[Idx] = PCI_SEG0_PHY_CFG0_BASE + (PCI_BASE_DIFF * Idx);
>> + PciPhyCfg1Addr[Idx] = PCI_SEG0_PHY_CFG1_BASE + (PCI_BASE_DIFF * Idx);
>> + PciPhyIoAddr [Idx] = PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx);
>> + Regs[Idx] = PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx); }
>> +
>> + for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
>> + //
>> + // Verify PCIe controller is enabled in Soc Serdes Map
>> + //
>> + if (!IsPcieNumEnabled (Idx)) {
>> + DEBUG ((DEBUG_ERROR, "PCIE%d is disabled\n", (Idx + BIT0)));
>> + //
>> + // Continue with other PCIe controller
>> + //
>> + continue;
>> + }
>> + DEBUG ((DEBUG_INFO, "PCIE%d is Enabled\n", Idx + BIT0));
>> +
>> + //
>> + // Verify PCIe controller LTSSM state
>> + //
>> + LinkUp = PcieLinkUp(Regs[Idx]);
>> + if (!LinkUp) {
>> + //
>> + // Let the user know there's no PCIe link
>> + //
>> + DEBUG ((DEBUG_INFO,"no link, regs @ 0x%lx\n", Regs[Idx]));
>> + //
>> + // Continue with other PCIe controller
>> + //
>> + continue;
>> + }
>> + DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + BIT0));
>> +
>> + //
>> + // Function to set up address translation unit outbound window for
>> + // PCIe Controller
>> + //
>> + PcieSetupCntrl (Regs[Idx],
>> + PciPhyCfg0Addr[Idx],
>> + PciPhyCfg1Addr[Idx],
>> + PciPhyMemAddr[Idx],
>> + PciPhyIoAddr[Idx]);
>> + *Count += BIT0;
>> + break;
>> + }
>> +
>> + if (*Count == 0) {
>> + return NULL;
>> + } else {
>> + return &mPciRootBridges[Idx];
>> + }
>> +}
>> +
>> +/**
>> + Free the root bridge instances array returned from
>PciHostBridgeGetRootBridges().
>> +
>> + @param Bridges The root bridge instances array.
>> + @param Count The count of the array.
>> +**/
>> +VOID
>> +EFIAPI
>> +PciHostBridgeFreeRootBridges (
>> + PCI_ROOT_BRIDGE *Bridges,
>> + UINTN Count
>> + )
>> +{
>> +}
>> +
>> +/**
>> + Inform the platform that the resource conflict happens.
>> +
>> + @param HostBridgeHandle Handle of the Host Bridge.
>> + @param Configuration Pointer to PCI I/O and PCI memory resource
>> + descriptors. The Configuration contains the resources
>> + for all the root bridges. The resource for each root
>> + bridge is terminated with END descriptor and an
>> + additional END is appended indicating the end of the
>> + entire resources. The resource descriptor field
>> + values follow the description in
>> + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
>> + .SubmitResources().
>> +
>> +**/
>> +VOID
>> +EFIAPI
>> +PciHostBridgeResourceConflict (
>> + EFI_HANDLE HostBridgeHandle,
>> + VOID *Configuration
>> + )
>> +{
>> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
>> + UINTN RootBridgeIndex;
>> + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict
>> +happens!\n"));
>> +
>> + RootBridgeIndex = 0;
>> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
>> + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
>> + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
>> + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR;
>Descriptor++) {
>> + ASSERT (Descriptor->ResType <
>> + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));
>> + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
>> + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
>> + Descriptor->AddrLen, Descriptor->AddrRangeMax
>> + ));
>> + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
>> + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
>> + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
>> + ((Descriptor->SpecificFlag &
>> +
>EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
>> + ) != 0) ? L" (Prefetchable)" : L""
>> + ));
>> + }
>> + }
>> + //
>> + // Skip the END descriptor for root bridge
>> + //
>> + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
>> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
>> + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
>> + );
>> + }
>> +
>> + return;
>> +}
>> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>> b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>> new file mode 100644
>> index 0000000..f08ac60
>> --- /dev/null
>> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>> @@ -0,0 +1,50 @@
>> +## @file
>> +# PCI Host Bridge Library instance for NXP ARM SOC # # Copyright
>> +2018 NXP # # This program and the accompanying materials are
>> +licensed and made available # under the terms and conditions of the
>> +BSD License which accompanies this # distribution. The full text of
>> +the license may be found at #
>> +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
>> +nsource.org%2Flicenses%2Fbsd-
>license.php&data=02%7C01%7Cvabhav.sharma
>>
>+%40nxp.com%7C90628d666bad46bf6dde08d5a6ce8fe0%7C686ea1d3bc2b4c6fa
>92cd
>>
>+99c5c301635%7C0%7C0%7C636598328488287967&sdata=6Jwkzr%2BkvDURRF
>%2FQ8r
>> +vSN1OBggJNg14NGhW5s3WkuFM%3D&reserved=0
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
>EITHER
>> +EXPRESS OR # IMPLIED.
>> +#
>> +#
>> +##
>> +
>> +[Defines]
>> + INF_VERSION = 0x0001001A
>> + BASE_NAME = PciHostBridgeLib
>> + FILE_GUID = f4c99bcc-5c95-49ad-b0f3-fc5b611dc9c1
>> + MODULE_TYPE = BASE
>> + VERSION_STRING = 1.0
>> + LIBRARY_CLASS = PciHostBridgeLib
>> +
>> +[Sources]
>> + PciHostBridgeLib.c
>> +
>> +[Packages]
>> + MdePkg/MdePkg.dec
>> + MdeModulePkg/MdeModulePkg.dec
>> + Silicon/NXP/NxpQoriqLs.dec
>> + Silicon/NXP/Chassis/Chassis2/Chassis2.dec
>> +
>> +[LibraryClasses]
>> + DebugLib
>> + DevicePathLib
>> + MemoryAllocationLib
>> + PcdLib
>> + SocLib
>> + UefiBootServicesTableLib
>> +
>> +[Pcd]
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian
>> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController
>> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase
>> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
>> --
>> 1.9.1
>>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 34/39] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
2018-04-24 12:26 ` Vabhav Sharma
@ 2018-04-24 12:33 ` Ard Biesheuvel
2018-04-24 13:36 ` Vabhav Sharma
0 siblings, 1 reply; 254+ messages in thread
From: Ard Biesheuvel @ 2018-04-24 12:33 UTC (permalink / raw)
To: Vabhav Sharma
Cc: Meenakshi Aggarwal, Leif Lindholm, Kinney, Michael D,
edk2-devel@lists.01.org, Udit Kumar, Varun Sethi
On 24 April 2018 at 14:26, Vabhav Sharma <vabhav.sharma@nxp.com> wrote:
>
>
>>-----Original Message-----
>>From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]
>>Sent: Friday, April 20, 2018 2:11 PM
>>To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>>Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
>><michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar
>><udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
>><vabhav.sharma@nxp.com>
>>Subject: Re: [PATCH edk2-platforms 34/39] Silicon/NXP: Implement
>>EFI_CPU_IO2_PROTOCOL
>>
>>On 16 February 2018 at 09:50, Meenakshi <meenakshi.aggarwal@nxp.com>
>>wrote:
>>> From: Vabhav <vabhav.sharma@nxp.com>
>>>
>>> NXP SOC has mutiple PCIe RCs,Adding respective implementation of
>>> EFI_CPU_IO2_PROTOCOL to provide Memory Space Read/Write functions used
>>> by generic Host Bridge Driver including correct value for the
>>> translation offset during MMIO accesses
>>>
>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
>>> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>>
>>This driver looks completely wrong to me: MMIO access is memory mapped, and
>>given that you don't implement PCI to CPU translation of MMIO accesses, the
>>memory read and write functions should not perform any translation at all, and
>>just relay the accesses. On the other hand, the I/O accessors are not
>>implemented at all, and these are the ones that require translation, given that the
>>I/O port addresses in the CPU space need translation to MMIO addressess.
>
> On NXP SoC, Mapping between CPU view and PCIe view is not 1:1 and require CPU view translation for MMIO regions access, Accordingly translation is added during memory read/write services.
> Bus driver relays the address range where PCIe device Bar region is split from, Translation is required for relaying it to correct PCIe controller cpu view address.
>
You cannot implement this only in the EFI_CPU_IO2_PROTOCOL driver.
That way, EFI_PCI_IO_PROTOCOL.GetBarAttributes() will return resource
descriptors with untranslated addresses, breaking drivers that rely on
this information.
If your PCIe implementation relies on MMIO translation, please refer
to the recently merged code in EDK2 and edk2-platforms implementing
this for Socionext SynQuacer.
>>
>>Also, you don't seem to be using the PcdPciExp?BaseAddr PCDs anywhere, so you
>>can drop them from the .dsc
> No, It's used for checking the access to MMIO32 region and CPU view base address varies between different NXP SoCs
>>
>>> ---
>>> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 529
>>++++++++++++++++++++++
>>> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 ++
>>> 2 files changed, 577 insertions(+)
>>> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>>> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>>>
>>> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>>> b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>>> new file mode 100644
>>> index 0000000..b5fb72c
>>> --- /dev/null
>>> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>>> @@ -0,0 +1,529 @@
>>> +/** @file
>>> + Produces the CPU I/O 2 Protocol.
>>> +
>>> + Copyright (c) 2009 - 2012, Intel Corporation. All rights
>>> + reserved.<BR> Copyright (c) 2016, Linaro Ltd. All rights
>>> + reserved.<BR> Copyright 2018 NXP
>>> +
>>> + This program and the accompanying materials are licensed and made
>>> + available under the terms and conditions of the BSD License which
>>> + accompanies this distribution. The full text of the license may be
>>> + found at
>>> +
>>> + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop
>>> + ensource.org%2Flicenses%2Fbsd-license.php&data=02%7C01%7Cvabhav.shar
>>> +
>>ma%40nxp.com%7C4507c0726b244ad6476d08d5a69a64ee%7C686ea1d3bc2b4c
>>6fa9
>>> +
>>2cd99c5c301635%7C0%7C0%7C636598104414046440&sdata=IFSU0%2FeTdWrw
>>gg0f
>>> + 0Lq2qSVGgogG68tYZevrRmC%2BkV8%3D&reserved=0
>>> +
>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>> + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>>EXPRESS OR IMPLIED.
>>> +
>>> +**/
>>> +
>>> +#include <Library/BaseLib.h>
>>> +#include <Library/DebugLib.h>
>>> +#include <Library/IoLib.h>
>>> +#include <Library/PcdLib.h>
>>> +#include <Library/UefiBootServicesTableLib.h>
>>> +#include <Pcie.h>
>>> +#include <Protocol/CpuIo2.h>
>>> +
>>> +#define MAX_IO_PORT_ADDRESS PCI_SEG2_PORTIO_MAX
>>> +
>>> +//
>>> +// Handle for the CPU I/O 2 Protocol
>>> +//
>>> +STATIC EFI_HANDLE mHandle;
>>> +
>>> +//
>>> +// Lookup table for increment values based on transfer widths //
>>> +STATIC CONST UINT8 mInStride[] = {
>>> + 1, // EfiCpuIoWidthUint8
>>> + 2, // EfiCpuIoWidthUint16
>>> + 4, // EfiCpuIoWidthUint32
>>> + 8, // EfiCpuIoWidthUint64
>>> + 0, // EfiCpuIoWidthFifoUint8
>>> + 0, // EfiCpuIoWidthFifoUint16
>>> + 0, // EfiCpuIoWidthFifoUint32
>>> + 0, // EfiCpuIoWidthFifoUint64
>>> + 1, // EfiCpuIoWidthFillUint8
>>> + 2, // EfiCpuIoWidthFillUint16
>>> + 4, // EfiCpuIoWidthFillUint32
>>> + 8 // EfiCpuIoWidthFillUint64
>>> +};
>>> +
>>> +//
>>> +// Lookup table for increment values based on transfer widths //
>>> +STATIC CONST UINT8 mOutStride[] = {
>>> + 1, // EfiCpuIoWidthUint8
>>> + 2, // EfiCpuIoWidthUint16
>>> + 4, // EfiCpuIoWidthUint32
>>> + 8, // EfiCpuIoWidthUint64
>>> + 1, // EfiCpuIoWidthFifoUint8
>>> + 2, // EfiCpuIoWidthFifoUint16
>>> + 4, // EfiCpuIoWidthFifoUint32
>>> + 8, // EfiCpuIoWidthFifoUint64
>>> + 0, // EfiCpuIoWidthFillUint8
>>> + 0, // EfiCpuIoWidthFillUint16
>>> + 0, // EfiCpuIoWidthFillUint32
>>> + 0 // EfiCpuIoWidthFillUint64
>>> +};
>>> +
>>> +/**
>>> + Check parameters to a CPU I/O 2 Protocol service request.
>>> +
>>> + The I/O operations are carried out exactly as requested. The caller
>>> + is responsible for satisfying any alignment and I/O width
>>> + restrictions that a PI System on a platform might require. For
>>> + example on some platforms, width requests of
>>> + EfiCpuIoWidthUint64 do not work.
>>> +
>>> + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O
>>Port operation.
>>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>>> + @param[in] Address The base address of the I/O operation.
>>> + @param[in] Count The number of I/O operations to perform. The
>>number of
>>> + bytes moved is Width size * Count, starting at Address.
>>> + @param[in] Buffer For read operations, the destination buffer to store
>>the results.
>>> + For write operations, the source buffer from which to write
>>data.
>>> +
>>> + @retval EFI_SUCCESS The parameters for this request pass the checks.
>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>Width,
>>> + and Count is not valid for this PI system.
>>> +
>>> +**/
>>> +STATIC
>>> +EFI_STATUS
>>> +CpuIoCheckParameter (
>>> + IN BOOLEAN MmioOperation,
>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>> + IN UINT64 Address,
>>> + IN UINTN Count,
>>> + IN VOID *Buffer
>>> + )
>>> +{
>>> + UINT64 MaxCount;
>>> + UINT64 Limit;
>>> +
>>> + //
>>> + // Check to see if Buffer is NULL
>>> + //
>>> + if (Buffer == NULL) {
>>> + ASSERT (FALSE);
>>> + return EFI_INVALID_PARAMETER;
>>> + }
>>> +
>>> + //
>>> + // Check to see if Width is in the valid range // if
>>> + ((UINT32)Width >= EfiCpuIoWidthMaximum) {
>>> + ASSERT (FALSE);
>>> + return EFI_INVALID_PARAMETER;
>>> + }
>>> +
>>> + //
>>> + // For FIFO type, the target address won't increase during the
>>> + access, // so treat Count as 1 // if (Width >=
>>> + EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
>>> + Count = 1;
>>> + }
>>> +
>>> + //
>>> + // Check to see if Width is in the valid range for I/O Port
>>> + operations // Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
>>> + if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
>>> + ASSERT (FALSE);
>>> + return EFI_INVALID_PARAMETER;
>>> + }
>>> +
>>> + //
>>> + // Check to see if Address is aligned // if ((Address &
>>> + (UINT64)(mInStride[Width] - 1)) != 0) {
>>> + ASSERT (FALSE);
>>> + return EFI_UNSUPPORTED;
>>> + }
>>> +
>>> + //
>>> + // Check to see if any address associated with this transfer
>>> + exceeds the maximum // allowed address. The maximum address
>>> + implied by the parameters passed in is // Address + Size * Count.
>>> + If the following condition is met, then the transfer // is not supported.
>>> + //
>>> + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS :
>>MAX_IO_PORT_ADDRESS) + 1
>>> + //
>>> + // Since MAX_ADDRESS can be the maximum integer value supported by
>>> + the CPU and Count // can also be the maximum integer value
>>> + supported by the CPU, this range // check must be adjusted to avoid all
>>oveflow conditions.
>>> + //
>>> + Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); if
>>> + (Count == 0) {
>>> + if (Address > Limit) {
>>> + ASSERT (FALSE);
>>> + return EFI_UNSUPPORTED;
>>> + }
>>> + } else {
>>> + MaxCount = RShiftU64 (Limit, Width);
>>> + if (MaxCount < (Count - 1)) {
>>> + ASSERT (FALSE);
>>> + return EFI_UNSUPPORTED;
>>> + }
>>> + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
>>> + ASSERT (FALSE);
>>> + return EFI_UNSUPPORTED;
>>> + }
>>> + }
>>> +
>>> + //
>>> + // Check to see if Buffer is aligned // if (((UINTN)Buffer &
>>> + ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
>>> + ASSERT (FALSE);
>>> + return EFI_UNSUPPORTED;
>>> + }
>>> +
>>> + return EFI_SUCCESS;
>>> +}
>>> +
>>> +/**
>>> + Reads memory-mapped registers.
>>> +
>>> + The I/O operations are carried out exactly as requested. The caller
>>> + is responsible for satisfying any alignment and I/O width
>>> + restrictions that a PI System on a platform might require. For
>>> + example on some platforms, width requests of
>>> + EfiCpuIoWidthUint64 do not work.
>>> +
>>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and
>>> + Buffer are incremented for each of the Count operations that is performed.
>>> +
>>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>>> + Buffer is incremented for each of the Count operations that is
>>> + performed. The read or write operation is performed Count times on the
>>same Address.
>>> +
>>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>>> + Address is incremented for each of the Count operations that is
>>> + performed. The read or write operation is performed Count times from the
>>first element of Buffer.
>>> +
>>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>>> + @param[in] Address The base address of the I/O operation.
>>> + @param[in] Count The number of I/O operations to perform. The number
>>of
>>> + bytes moved is Width size * Count, starting at Address.
>>> + @param[out] Buffer For read operations, the destination buffer to store the
>>results.
>>> + For write operations, the source buffer from which to write data.
>>> +
>>> + @retval EFI_SUCCESS The data was read from or written to the PI
>>system.
>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>Width,
>>> + and Count is not valid for this PI system.
>>> +
>>> +**/
>>> +STATIC
>>> +EFI_STATUS
>>> +EFIAPI
>>> +CpuMemoryServiceRead (
>>> + IN EFI_CPU_IO2_PROTOCOL *This,
>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>> + IN UINT64 Address,
>>> + IN UINTN Count,
>>> + OUT VOID *Buffer
>>> + )
>>> +{
>>> + EFI_STATUS Status;
>>> + UINT8 InStride;
>>> + UINT8 OutStride;
>>> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
>>> + UINT8 *Uint8Buffer;
>>> +
>>> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
>>> + if (EFI_ERROR (Status)) {
>>> + return Status;
>>> + }
>>> +
>>> + if ((Address >= PCI_SEG0_MMIO32_MIN) &&
>>> + (Address <= PCI_SEG0_MMIO32_MAX)) {
>>> + Address += PCI_SEG0_MMIO_MEMBASE; } else if ((Address >=
>>> + PCI_SEG1_MMIO32_MIN) &&
>>> + (Address <= PCI_SEG1_MMIO32_MAX)) {
>>> + Address += PCI_SEG1_MMIO_MEMBASE; } else if ((Address >=
>>> + PCI_SEG2_MMIO32_MIN) &&
>>> + (Address <= PCI_SEG2_MMIO32_MAX)) {
>>> + Address += PCI_SEG2_MMIO_MEMBASE; } else if ((Address >=
>>> + PCI_SEG3_MMIO32_MIN) &&
>>> + (Address <= PCI_SEG3_MMIO32_MAX)) {
>>> + Address += PCI_SEG3_MMIO_MEMBASE; } else {
>>> + ASSERT (FALSE);
>>> + return EFI_INVALID_PARAMETER;
>>> + }
>>> +
>>> + //
>>> + // Select loop based on the width of the transfer
>>> + //
>>> + InStride = mInStride[Width];
>>> + OutStride = mOutStride[Width];
>>> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
>>> + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer +=
>>OutStride, Count--) {
>>> + if (OperationWidth == EfiCpuIoWidthUint8) {
>>> + *Uint8Buffer = MmioRead8 ((UINTN)Address);
>>> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
>>> + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
>>> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
>>> + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
>>> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
>>> + *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
>>> + }
>>> + }
>>> + return EFI_SUCCESS;
>>> +}
>>> +
>>> +/**
>>> + Writes memory-mapped registers.
>>> +
>>> + The I/O operations are carried out exactly as requested. The caller
>>> + is responsible for satisfying any alignment and I/O width
>>> + restrictions that a PI System on a platform might require. For
>>> + example on some platforms, width requests of
>>> + EfiCpuIoWidthUint64 do not work.
>>> +
>>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and
>>> + Buffer are incremented for each of the Count operations that is performed.
>>> +
>>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>>> + Buffer is incremented for each of the Count operations that is
>>> + performed. The read or write operation is performed Count times on the
>>same Address.
>>> +
>>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>>> + Address is incremented for each of the Count operations that is
>>> + performed. The read or write operation is performed Count times from the
>>first element of Buffer.
>>> +
>>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>>> + @param[in] Address The base address of the I/O operation.
>>> + @param[in] Count The number of I/O operations to perform. The number
>>of
>>> + bytes moved is Width size * Count, starting at Address.
>>> + @param[in] Buffer For read operations, the destination buffer to store the
>>results.
>>> + For write operations, the source buffer from which to write data.
>>> +
>>> + @retval EFI_SUCCESS The data was read from or written to the PI
>>system.
>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>Width,
>>> + and Count is not valid for this PI system.
>>> +
>>> +**/
>>> +STATIC
>>> +EFI_STATUS
>>> +EFIAPI
>>> +CpuMemoryServiceWrite (
>>> + IN EFI_CPU_IO2_PROTOCOL *This,
>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>> + IN UINT64 Address,
>>> + IN UINTN Count,
>>> + IN VOID *Buffer
>>> + )
>>> +{
>>> + EFI_STATUS Status;
>>> + UINT8 InStride;
>>> + UINT8 OutStride;
>>> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
>>> + UINT8 *Uint8Buffer;
>>> +
>>> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
>>> + if (EFI_ERROR (Status)) {
>>> + return Status;
>>> + }
>>> +
>>> + if ((Address >= PCI_SEG0_MMIO32_MIN) &&
>>> + (Address <= PCI_SEG0_MMIO32_MAX)) {
>>> + Address += PCI_SEG0_MMIO_MEMBASE; } else if ((Address >=
>>> + PCI_SEG1_MMIO32_MIN) &&
>>> + (Address <= PCI_SEG1_MMIO32_MAX)) {
>>> + Address += PCI_SEG1_MMIO_MEMBASE; } else if ((Address >=
>>> + PCI_SEG2_MMIO32_MIN) &&
>>> + (Address <= PCI_SEG2_MMIO32_MAX)) {
>>> + Address += PCI_SEG2_MMIO_MEMBASE; } else if ((Address >=
>>> + PCI_SEG3_MMIO32_MIN) &&
>>> + (Address <= PCI_SEG3_MMIO32_MAX)) {
>>> + Address += PCI_SEG3_MMIO_MEMBASE; } else {
>>> + ASSERT (FALSE);
>>> + return EFI_INVALID_PARAMETER;
>>> + }
>>> +
>>> + //
>>> + // Select loop based on the width of the transfer
>>> + //
>>> + InStride = mInStride[Width];
>>> + OutStride = mOutStride[Width];
>>> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
>>> + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer +=
>>OutStride, Count--) {
>>> + if (OperationWidth == EfiCpuIoWidthUint8) {
>>> + MmioWrite8 ((UINTN)Address, *Uint8Buffer);
>>> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
>>> + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
>>> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
>>> + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
>>> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
>>> + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
>>> + }
>>> + }
>>> + return EFI_SUCCESS;
>>> +}
>>> +
>>> +/**
>>> + Reads I/O registers.
>>> +
>>> + The I/O operations are carried out exactly as requested. The caller
>>> + is responsible for satisfying any alignment and I/O width
>>> + restrictions that a PI System on a platform might require. For
>>> + example on some platforms, width requests of
>>> + EfiCpuIoWidthUint64 do not work.
>>> +
>>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and
>>> + Buffer are incremented for each of the Count operations that is performed.
>>> +
>>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>>> + Buffer is incremented for each of the Count operations that is
>>> + performed. The read or write operation is performed Count times on the
>>same Address.
>>> +
>>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>>> + Address is incremented for each of the Count operations that is
>>> + performed. The read or write operation is performed Count times from the
>>first element of Buffer.
>>> +
>>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>>> + @param[in] Address The base address of the I/O operation.
>>> + @param[in] Count The number of I/O operations to perform. The number
>>of
>>> + bytes moved is Width size * Count, starting at Address.
>>> + @param[out] Buffer For read operations, the destination buffer to store the
>>results.
>>> + For write operations, the source buffer from which to write data.
>>> +
>>> + @retval EFI_SUCCESS The data was read from or written to the PI
>>system.
>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>Width,
>>> + and Count is not valid for this PI system.
>>> +
>>> +**/
>>> +STATIC
>>> +EFI_STATUS
>>> +EFIAPI
>>> +CpuIoServiceRead (
>>> + IN EFI_CPU_IO2_PROTOCOL *This,
>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>> + IN UINT64 Address,
>>> + IN UINTN Count,
>>> + OUT VOID *Buffer
>>> + )
>>> +{
>>> + return EFI_SUCCESS;
>>> +}
>>> +
>>> +/**
>>> + Write I/O registers.
>>> +
>>> + The I/O operations are carried out exactly as requested. The caller
>>> + is responsible for satisfying any alignment and I/O width
>>> + restrictions that a PI System on a platform might require. For
>>> + example on some platforms, width requests of
>>> + EfiCpuIoWidthUint64 do not work.
>>> +
>>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and
>>> + Buffer are incremented for each of the Count operations that is performed.
>>> +
>>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>>> + Buffer is incremented for each of the Count operations that is
>>> + performed. The read or write operation is performed Count times on the
>>same Address.
>>> +
>>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>>> + Address is incremented for each of the Count operations that is
>>> + performed. The read or write operation is performed Count times from the
>>first element of Buffer.
>>> +
>>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>>> + @param[in] Address The base address of the I/O operation.
>>> + @param[in] Count The number of I/O operations to perform. The number
>>of
>>> + bytes moved is Width size * Count, starting at Address.
>>> + @param[in] Buffer For read operations, the destination buffer to store the
>>results.
>>> + For write operations, the source buffer from which to write data.
>>> +
>>> + @retval EFI_SUCCESS The data was read from or written to the PI
>>system.
>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>Width,
>>> + and Count is not valid for this PI system.
>>> +
>>> +**/
>>> +STATIC
>>> +EFI_STATUS
>>> +EFIAPI
>>> +CpuIoServiceWrite (
>>> + IN EFI_CPU_IO2_PROTOCOL *This,
>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>> + IN UINT64 Address,
>>> + IN UINTN Count,
>>> + IN VOID *Buffer
>>> + )
>>> +{
>>> + return EFI_SUCCESS;
>>> +}
>>> +
>>> +//
>>> +// CPU I/O 2 Protocol instance
>>> +//
>>> +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
>>> + {
>>> + CpuMemoryServiceRead,
>>> + CpuMemoryServiceWrite
>>> + },
>>> + {
>>> + CpuIoServiceRead,
>>> + CpuIoServiceWrite
>>> + }
>>> +};
>>> +
>>> +
>>> +/**
>>> + The user Entry Point for module CpuIo2Dxe. The user code starts with this
>>function.
>>> +
>>> + @param[in] ImageHandle The firmware allocated handle for the EFI image.
>>> + @param[in] SystemTable A pointer to the EFI System Table.
>>> +
>>> + @retval EFI_SUCCESS The entry point is executed successfully.
>>> + @retval other Some error occurs when executing this entry point.
>>> +
>>> +**/
>>> +EFI_STATUS
>>> +EFIAPI
>>> +PciCpuIo2Initialize (
>>> + IN EFI_HANDLE ImageHandle,
>>> + IN EFI_SYSTEM_TABLE *SystemTable
>>> + )
>>> +{
>>> + EFI_STATUS Status;
>>> +
>>> + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
>>> + Status = gBS->InstallMultipleProtocolInterfaces (
>>> + &mHandle,
>>> + &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
>>> + NULL
>>> + );
>>> + ASSERT_EFI_ERROR (Status);
>>> +
>>> + return Status;
>>> +}
>>> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>>> b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>>> new file mode 100644
>>> index 0000000..25a1db1
>>> --- /dev/null
>>> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>>> @@ -0,0 +1,48 @@
>>> +## @file
>>> +# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
>>> +#
>>> +# Copyright 2018 NXP
>>> +#
>>> +# This program and the accompanying materials # are licensed and made
>>> +available under the terms and conditions of the BSD License # which
>>> +accompanies this distribution. The full text of the license may be
>>> +found at #
>>> +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
>>> +nsource.org%2Flicenses%2Fbsd-
>>license.php&data=02%7C01%7Cvabhav.sharma
>>>
>>+%40nxp.com%7C4507c0726b244ad6476d08d5a69a64ee%7C686ea1d3bc2b4c6f
>>a92cd
>>>
>>+99c5c301635%7C0%7C0%7C636598104414046440&sdata=IFSU0%2FeTdWrwgg
>>0f0Lq2
>>> +qSVGgogG68tYZevrRmC%2BkV8%3D&reserved=0
>>> +#
>>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>> +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>>EXPRESS OR IMPLIED.
>>> +#
>>> +##
>>> +
>>> +[Defines]
>>> + INF_VERSION = 0x0001001A
>>> + BASE_NAME = PciCpuIo2Dxe
>>> + FILE_GUID = 7bff18d7-9aae-434b-9c06-f10a7e157eac
>>> + MODULE_TYPE = DXE_DRIVER
>>> + VERSION_STRING = 1.0
>>> + ENTRY_POINT = PciCpuIo2Initialize
>>> +
>>> +[Sources]
>>> + PciCpuIo2Dxe.c
>>> +
>>> +[Packages]
>>> + MdePkg/MdePkg.dec
>>> + Silicon/NXP/NxpQoriqLs.dec
>>> +
>>> +[LibraryClasses]
>>> + BaseLib
>>> + DebugLib
>>> + IoLib
>>> + UefiBootServicesTableLib
>>> + UefiDriverEntryPoint
>>> +
>>> +[Pcd]
>>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
>>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
>>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
>>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
>>> +
>>> +[Protocols]
>>> + gEfiCpuIo2ProtocolGuid ## PRODUCES
>>> +
>>> +[Depex]
>>> + TRUE
>>> --
>>> 1.9.1
>>>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 34/39] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
2018-04-20 15:15 ` Leif Lindholm
@ 2018-04-24 12:40 ` Vabhav Sharma
0 siblings, 0 replies; 254+ messages in thread
From: Vabhav Sharma @ 2018-04-24 12:40 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi
>-----Original Message-----
>From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
>Sent: Friday, April 20, 2018 8:46 PM
>To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
><udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
><vabhav.sharma@nxp.com>
>Subject: Re: [PATCH edk2-platforms 34/39] Silicon/NXP: Implement
>EFI_CPU_IO2_PROTOCOL
>
>On Fri, Feb 16, 2018 at 02:20:30PM +0530, Meenakshi wrote:
>> From: Vabhav <vabhav.sharma@nxp.com>
>>
>> NXP SOC has mutiple PCIe RCs,Adding respective implementation of
>> EFI_CPU_IO2_PROTOCOL to provide Memory Space Read/Write functions used
>> by generic Host Bridge Driver including correct value for the
>> translation offset during MMIO accesses
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
>> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>> ---
>> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 529
>++++++++++++++++++++++
>> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 ++
>> 2 files changed, 577 insertions(+)
>> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>>
>> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>> b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>> new file mode 100644
>> index 0000000..b5fb72c
>> --- /dev/null
>> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>> @@ -0,0 +1,529 @@
>> +/** @file
>> + Produces the CPU I/O 2 Protocol.
>> +
>> + Copyright (c) 2009 - 2012, Intel Corporation. All rights
>> + reserved.<BR> Copyright (c) 2016, Linaro Ltd. All rights
>> + reserved.<BR> Copyright 2018 NXP
>> +
>> + This program and the accompanying materials are licensed and made
>> + available under the terms and conditions of the BSD License which
>> + accompanies this distribution. The full text of the license may be
>> + found at
>> +
>> + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop
>> + ensource.org%2Flicenses%2Fbsd-license.php&data=02%7C01%7Cvabhav.shar
>> +
>ma%40nxp.com%7C42500fab2cd1447bbe6308d5a6d19d8b%7C686ea1d3bc2b4c
>6fa9
>> +
>2cd99c5c301635%7C0%7C0%7C636598341623135085&sdata=Zo6s2LhxPSElw4F
>XsV
>> + 7%2Bx3Veb5yptglf1UQiA%2FNRRc4%3D&reserved=0
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#include <Library/BaseLib.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/PcdLib.h>
>> +#include <Library/UefiBootServicesTableLib.h>
>> +#include <Pcie.h>
>> +#include <Protocol/CpuIo2.h>
>> +
>> +#define MAX_IO_PORT_ADDRESS PCI_SEG2_PORTIO_MAX
>> +
>> +//
>> +// Handle for the CPU I/O 2 Protocol
>> +//
>> +STATIC EFI_HANDLE mHandle;
>> +
>> +//
>> +// Lookup table for increment values based on transfer widths //
>> +STATIC CONST UINT8 mInStride[] = {
>> + 1, // EfiCpuIoWidthUint8
>> + 2, // EfiCpuIoWidthUint16
>> + 4, // EfiCpuIoWidthUint32
>> + 8, // EfiCpuIoWidthUint64
>> + 0, // EfiCpuIoWidthFifoUint8
>> + 0, // EfiCpuIoWidthFifoUint16
>> + 0, // EfiCpuIoWidthFifoUint32
>> + 0, // EfiCpuIoWidthFifoUint64
>> + 1, // EfiCpuIoWidthFillUint8
>> + 2, // EfiCpuIoWidthFillUint16
>> + 4, // EfiCpuIoWidthFillUint32
>> + 8 // EfiCpuIoWidthFillUint64
>> +};
>> +
>> +//
>> +// Lookup table for increment values based on transfer widths //
>> +STATIC CONST UINT8 mOutStride[] = {
>> + 1, // EfiCpuIoWidthUint8
>> + 2, // EfiCpuIoWidthUint16
>> + 4, // EfiCpuIoWidthUint32
>> + 8, // EfiCpuIoWidthUint64
>> + 1, // EfiCpuIoWidthFifoUint8
>> + 2, // EfiCpuIoWidthFifoUint16
>> + 4, // EfiCpuIoWidthFifoUint32
>> + 8, // EfiCpuIoWidthFifoUint64
>> + 0, // EfiCpuIoWidthFillUint8
>> + 0, // EfiCpuIoWidthFillUint16
>> + 0, // EfiCpuIoWidthFillUint32
>> + 0 // EfiCpuIoWidthFillUint64
>> +};
>> +
>> +/**
>> + Check parameters to a CPU I/O 2 Protocol service request.
>> +
>> + The I/O operations are carried out exactly as requested. The caller
>> + is responsible for satisfying any alignment and I/O width
>> + restrictions that a PI System on a platform might require. For
>> + example on some platforms, width requests of
>> + EfiCpuIoWidthUint64 do not work.
>> +
>> + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O
>Port operation.
>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>> + @param[in] Address The base address of the I/O operation.
>> + @param[in] Count The number of I/O operations to perform. The
>number of
>> + bytes moved is Width size * Count, starting at Address.
>> + @param[in] Buffer For read operations, the destination buffer to store
>the results.
>> + For write operations, the source buffer from which to write
>data.
>> +
>> + @retval EFI_SUCCESS The parameters for this request pass the checks.
>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>Width,
>> + and Count is not valid for this PI system.
>> +
>> +**/
>> +STATIC
>> +EFI_STATUS
>> +CpuIoCheckParameter (
>> + IN BOOLEAN MmioOperation,
>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>> + IN UINT64 Address,
>> + IN UINTN Count,
>> + IN VOID *Buffer
>> + )
>> +{
>> + UINT64 MaxCount;
>> + UINT64 Limit;
>> +
>> + //
>> + // Check to see if Buffer is NULL
>> + //
>> + if (Buffer == NULL) {
>> + ASSERT (FALSE);
>> + return EFI_INVALID_PARAMETER;
>> + }
>> +
>> + //
>> + // Check to see if Width is in the valid range // if
>> + ((UINT32)Width >= EfiCpuIoWidthMaximum) {
>> + ASSERT (FALSE);
>> + return EFI_INVALID_PARAMETER;
>> + }
>> +
>> + //
>> + // For FIFO type, the target address won't increase during the
>> + access, // so treat Count as 1 // if (Width >=
>> + EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
>> + Count = 1;
>> + }
>> +
>> + //
>> + // Check to see if Width is in the valid range for I/O Port
>> + operations // Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
>> + if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
>> + ASSERT (FALSE);
>> + return EFI_INVALID_PARAMETER;
>> + }
>> +
>> + //
>> + // Check to see if Address is aligned // if ((Address &
>> + (UINT64)(mInStride[Width] - 1)) != 0) {
>> + ASSERT (FALSE);
>> + return EFI_UNSUPPORTED;
>> + }
>> +
>> + //
>> + // Check to see if any address associated with this transfer
>> + exceeds the maximum // allowed address. The maximum address
>> + implied by the parameters passed in is // Address + Size * Count.
>> + If the following condition is met, then the transfer // is not supported.
>> + //
>> + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS :
>MAX_IO_PORT_ADDRESS) + 1
>> + //
>> + // Since MAX_ADDRESS can be the maximum integer value supported by
>> + the CPU and Count // can also be the maximum integer value
>> + supported by the CPU, this range // check must be adjusted to avoid all
>oveflow conditions.
>> + //
>> + Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); if
>> + (Count == 0) {
>> + if (Address > Limit) {
>> + ASSERT (FALSE);
>> + return EFI_UNSUPPORTED;
>> + }
>> + } else {
>> + MaxCount = RShiftU64 (Limit, Width);
>> + if (MaxCount < (Count - 1)) {
>> + ASSERT (FALSE);
>> + return EFI_UNSUPPORTED;
>> + }
>> + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
>> + ASSERT (FALSE);
>> + return EFI_UNSUPPORTED;
>> + }
>> + }
>> +
>> + //
>> + // Check to see if Buffer is aligned // if (((UINTN)Buffer &
>> + ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
>> + ASSERT (FALSE);
>> + return EFI_UNSUPPORTED;
>> + }
>> +
>> + return EFI_SUCCESS;
>> +}
>> +
>> +/**
>> + Reads memory-mapped registers.
>> +
>> + The I/O operations are carried out exactly as requested. The caller
>> + is responsible for satisfying any alignment and I/O width
>> + restrictions that a PI System on a platform might require. For
>> + example on some platforms, width requests of
>> + EfiCpuIoWidthUint64 do not work.
>> +
>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and
>> + Buffer are incremented for each of the Count operations that is performed.
>> +
>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>> + Buffer is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times on the
>same Address.
>> +
>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>> + Address is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times from the
>first element of Buffer.
>> +
>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>> + @param[in] Address The base address of the I/O operation.
>> + @param[in] Count The number of I/O operations to perform. The number
>of
>> + bytes moved is Width size * Count, starting at Address.
>> + @param[out] Buffer For read operations, the destination buffer to store the
>results.
>> + For write operations, the source buffer from which to write data.
>> +
>> + @retval EFI_SUCCESS The data was read from or written to the PI
>system.
>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>Width,
>> + and Count is not valid for this PI system.
>> +
>> +**/
>> +STATIC
>> +EFI_STATUS
>> +EFIAPI
>> +CpuMemoryServiceRead (
>> + IN EFI_CPU_IO2_PROTOCOL *This,
>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>> + IN UINT64 Address,
>> + IN UINTN Count,
>> + OUT VOID *Buffer
>> + )
>> +{
>> + EFI_STATUS Status;
>> + UINT8 InStride;
>> + UINT8 OutStride;
>> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
>> + UINT8 *Uint8Buffer;
>> +
>> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
>> + if (EFI_ERROR (Status)) {
>> + return Status;
>> + }
>> +
>> + if ((Address >= PCI_SEG0_MMIO32_MIN) &&
>> + (Address <= PCI_SEG0_MMIO32_MAX)) {
>> + Address += PCI_SEG0_MMIO_MEMBASE; } else if ((Address >=
>> + PCI_SEG1_MMIO32_MIN) &&
>> + (Address <= PCI_SEG1_MMIO32_MAX)) {
>> + Address += PCI_SEG1_MMIO_MEMBASE; } else if ((Address >=
>> + PCI_SEG2_MMIO32_MIN) &&
>> + (Address <= PCI_SEG2_MMIO32_MAX)) {
>> + Address += PCI_SEG2_MMIO_MEMBASE; } else if ((Address >=
>> + PCI_SEG3_MMIO32_MIN) &&
>> + (Address <= PCI_SEG3_MMIO32_MAX)) {
>> + Address += PCI_SEG3_MMIO_MEMBASE; } else {
>> + ASSERT (FALSE);
>> + return EFI_INVALID_PARAMETER;
>> + }
>> +
>> + //
>> + // Select loop based on the width of the transfer // InStride =
>> + mInStride[Width]; OutStride = mOutStride[Width]; OperationWidth =
>> + (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); for (Uint8Buffer =
>> + Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride,
>> + Count--) {
>
>Could you move the Address and Uint8Buffer updates to the end of the loop, in
>order to get the line length down?
Ok, I will update
>
>> + if (OperationWidth == EfiCpuIoWidthUint8) {
>> + *Uint8Buffer = MmioRead8 ((UINTN)Address);
>> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
>> + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
>> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
>> + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
>> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
>> + *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
>> + }
>> + }
>> + return EFI_SUCCESS;
>> +}
>> +
>> +/**
>> + Writes memory-mapped registers.
>> +
>> + The I/O operations are carried out exactly as requested. The caller
>> + is responsible for satisfying any alignment and I/O width
>> + restrictions that a PI System on a platform might require. For
>> + example on some platforms, width requests of
>> + EfiCpuIoWidthUint64 do not work.
>> +
>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and
>> + Buffer are incremented for each of the Count operations that is performed.
>> +
>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>> + Buffer is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times on the
>same Address.
>> +
>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>> + Address is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times from the
>first element of Buffer.
>> +
>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>> + @param[in] Address The base address of the I/O operation.
>> + @param[in] Count The number of I/O operations to perform. The number
>of
>> + bytes moved is Width size * Count, starting at Address.
>> + @param[in] Buffer For read operations, the destination buffer to store the
>results.
>> + For write operations, the source buffer from which to write data.
>> +
>> + @retval EFI_SUCCESS The data was read from or written to the PI
>system.
>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>Width,
>> + and Count is not valid for this PI system.
>> +
>> +**/
>> +STATIC
>> +EFI_STATUS
>> +EFIAPI
>> +CpuMemoryServiceWrite (
>> + IN EFI_CPU_IO2_PROTOCOL *This,
>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>> + IN UINT64 Address,
>> + IN UINTN Count,
>> + IN VOID *Buffer
>> + )
>> +{
>> + EFI_STATUS Status;
>> + UINT8 InStride;
>> + UINT8 OutStride;
>> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
>> + UINT8 *Uint8Buffer;
>> +
>> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
>> + if (EFI_ERROR (Status)) {
>> + return Status;
>> + }
>> +
>> + if ((Address >= PCI_SEG0_MMIO32_MIN) &&
>> + (Address <= PCI_SEG0_MMIO32_MAX)) {
>> + Address += PCI_SEG0_MMIO_MEMBASE; } else if ((Address >=
>> + PCI_SEG1_MMIO32_MIN) &&
>> + (Address <= PCI_SEG1_MMIO32_MAX)) {
>> + Address += PCI_SEG1_MMIO_MEMBASE; } else if ((Address >=
>> + PCI_SEG2_MMIO32_MIN) &&
>> + (Address <= PCI_SEG2_MMIO32_MAX)) {
>> + Address += PCI_SEG2_MMIO_MEMBASE; } else if ((Address >=
>> + PCI_SEG3_MMIO32_MIN) &&
>> + (Address <= PCI_SEG3_MMIO32_MAX)) {
>> + Address += PCI_SEG3_MMIO_MEMBASE; } else {
>> + ASSERT (FALSE);
>> + return EFI_INVALID_PARAMETER;
>> + }
>
>The block above looks identical with the previous function.
>Break out as a separate helper function?
Ok, Yes sure.
>
>> +
>> + //
>> + // Select loop based on the width of the transfer // InStride =
>> + mInStride[Width]; OutStride = mOutStride[Width]; OperationWidth =
>> + (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); for (Uint8Buffer =
>> + Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride,
>> + Count--) {
>
>Move Address/Uint8Buffer updates to end of loop?
>(I think the use of Uint8Buffer is completely redundant here. Buffer could be used
>directly.)
>
>/
> Leif
Ok, Reference is taken from Socionext,
I will update it.
>
>> + if (OperationWidth == EfiCpuIoWidthUint8) {
>> + MmioWrite8 ((UINTN)Address, *Uint8Buffer);
>> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
>> + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
>> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
>> + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
>> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
>> + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
>> + }
>> + }
>> + return EFI_SUCCESS;
>> +}
>> +
>> +/**
>> + Reads I/O registers.
>> +
>> + The I/O operations are carried out exactly as requested. The caller
>> + is responsible for satisfying any alignment and I/O width
>> + restrictions that a PI System on a platform might require. For
>> + example on some platforms, width requests of
>> + EfiCpuIoWidthUint64 do not work.
>> +
>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and
>> + Buffer are incremented for each of the Count operations that is performed.
>> +
>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>> + Buffer is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times on the
>same Address.
>> +
>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>> + Address is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times from the
>first element of Buffer.
>> +
>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>> + @param[in] Address The base address of the I/O operation.
>> + @param[in] Count The number of I/O operations to perform. The number
>of
>> + bytes moved is Width size * Count, starting at Address.
>> + @param[out] Buffer For read operations, the destination buffer to store the
>results.
>> + For write operations, the source buffer from which to write data.
>> +
>> + @retval EFI_SUCCESS The data was read from or written to the PI
>system.
>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>Width,
>> + and Count is not valid for this PI system.
>> +
>> +**/
>> +STATIC
>> +EFI_STATUS
>> +EFIAPI
>> +CpuIoServiceRead (
>> + IN EFI_CPU_IO2_PROTOCOL *This,
>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>> + IN UINT64 Address,
>> + IN UINTN Count,
>> + OUT VOID *Buffer
>> + )
>> +{
>> + return EFI_SUCCESS;
>> +}
>> +
>> +/**
>> + Write I/O registers.
>> +
>> + The I/O operations are carried out exactly as requested. The caller
>> + is responsible for satisfying any alignment and I/O width
>> + restrictions that a PI System on a platform might require. For
>> + example on some platforms, width requests of
>> + EfiCpuIoWidthUint64 do not work.
>> +
>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and
>> + Buffer are incremented for each of the Count operations that is performed.
>> +
>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>> + Buffer is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times on the
>same Address.
>> +
>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>> + Address is incremented for each of the Count operations that is
>> + performed. The read or write operation is performed Count times from the
>first element of Buffer.
>> +
>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>> + @param[in] Address The base address of the I/O operation.
>> + @param[in] Count The number of I/O operations to perform. The number
>of
>> + bytes moved is Width size * Count, starting at Address.
>> + @param[in] Buffer For read operations, the destination buffer to store the
>results.
>> + For write operations, the source buffer from which to write data.
>> +
>> + @retval EFI_SUCCESS The data was read from or written to the PI
>system.
>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>Width,
>> + and Count is not valid for this PI system.
>> +
>> +**/
>> +STATIC
>> +EFI_STATUS
>> +EFIAPI
>> +CpuIoServiceWrite (
>> + IN EFI_CPU_IO2_PROTOCOL *This,
>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>> + IN UINT64 Address,
>> + IN UINTN Count,
>> + IN VOID *Buffer
>> + )
>> +{
>> + return EFI_SUCCESS;
>> +}
>> +
>> +//
>> +// CPU I/O 2 Protocol instance
>> +//
>> +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
>> + {
>> + CpuMemoryServiceRead,
>> + CpuMemoryServiceWrite
>> + },
>> + {
>> + CpuIoServiceRead,
>> + CpuIoServiceWrite
>> + }
>> +};
>> +
>> +
>> +/**
>> + The user Entry Point for module CpuIo2Dxe. The user code starts with this
>function.
>> +
>> + @param[in] ImageHandle The firmware allocated handle for the EFI image.
>> + @param[in] SystemTable A pointer to the EFI System Table.
>> +
>> + @retval EFI_SUCCESS The entry point is executed successfully.
>> + @retval other Some error occurs when executing this entry point.
>> +
>> +**/
>> +EFI_STATUS
>> +EFIAPI
>> +PciCpuIo2Initialize (
>> + IN EFI_HANDLE ImageHandle,
>> + IN EFI_SYSTEM_TABLE *SystemTable
>> + )
>> +{
>> + EFI_STATUS Status;
>> +
>> + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
>> + Status = gBS->InstallMultipleProtocolInterfaces (
>> + &mHandle,
>> + &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
>> + NULL
>> + );
>> + ASSERT_EFI_ERROR (Status);
>> +
>> + return Status;
>> +}
>> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>> b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>> new file mode 100644
>> index 0000000..25a1db1
>> --- /dev/null
>> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>> @@ -0,0 +1,48 @@
>> +## @file
>> +# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
>> +#
>> +# Copyright 2018 NXP
>> +#
>> +# This program and the accompanying materials # are licensed and made
>> +available under the terms and conditions of the BSD License # which
>> +accompanies this distribution. The full text of the license may be
>> +found at #
>> +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
>> +nsource.org%2Flicenses%2Fbsd-
>license.php&data=02%7C01%7Cvabhav.sharma
>>
>+%40nxp.com%7C42500fab2cd1447bbe6308d5a6d19d8b%7C686ea1d3bc2b4c6f
>a92cd
>>
>+99c5c301635%7C0%7C0%7C636598341623135085&sdata=Zo6s2LhxPSElw4FXs
>V7%2B
>> +x3Veb5yptglf1UQiA%2FNRRc4%3D&reserved=0
>> +#
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>> +#
>> +##
>> +
>> +[Defines]
>> + INF_VERSION = 0x0001001A
>> + BASE_NAME = PciCpuIo2Dxe
>> + FILE_GUID = 7bff18d7-9aae-434b-9c06-f10a7e157eac
>> + MODULE_TYPE = DXE_DRIVER
>> + VERSION_STRING = 1.0
>> + ENTRY_POINT = PciCpuIo2Initialize
>> +
>> +[Sources]
>> + PciCpuIo2Dxe.c
>> +
>> +[Packages]
>> + MdePkg/MdePkg.dec
>> + Silicon/NXP/NxpQoriqLs.dec
>> +
>> +[LibraryClasses]
>> + BaseLib
>> + DebugLib
>> + IoLib
>> + UefiBootServicesTableLib
>> + UefiDriverEntryPoint
>> +
>> +[Pcd]
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
>> +
>> +[Protocols]
>> + gEfiCpuIo2ProtocolGuid ## PRODUCES
>> +
>> +[Depex]
>> + TRUE
>> --
>> 1.9.1
>>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 35/39] Compilation: Update the fdf, dsc and dec files.
2018-04-20 15:22 ` Leif Lindholm
@ 2018-04-24 12:47 ` Vabhav Sharma
0 siblings, 0 replies; 254+ messages in thread
From: Vabhav Sharma @ 2018-04-24 12:47 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi
>-----Original Message-----
>From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
>Sent: Friday, April 20, 2018 8:53 PM
>To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
><udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
><vabhav.sharma@nxp.com>
>Subject: Re: [PATCH edk2-platforms 35/39] Compilation: Update the fdf, dsc and
>dec files.
>
>On Fri, Feb 16, 2018 at 02:20:31PM +0530, Meenakshi wrote:
>> From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>>
>> LS1043A PCIe compilation and update firmware device, description and
>> declaration files.Defining Embedded Package PCD which should be at
>> least 20 for 64K PCIe IO size required for CPU hob during PEI phase to
>> Add IO space post PEI phase.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
>> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>> ---
>> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 16
>++++++++++++++++
>> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 9 +++++++++
>> .../LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++
>> .../LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
>> Platform/NXP/NxpQoriqLs.dsc | 7 +++++++
>> Silicon/NXP/LS1043A/LS1043A.dsc | 4 ++++
>> Silicon/NXP/NxpQoriqLs.dec | 10 ++++++++++
>> 7 files changed, 54 insertions(+)
>>
>> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
>> b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
>> index b2b514e..8cbaf88 100644
>> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
>> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
>> @@ -42,6 +42,8 @@
>> BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
>> FpgaLib|Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf
>> NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
>> + PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>> +
>> + PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeL
>> + ib.inf
>>
>> [PcdsFixedAtBuild.common]
>>
>> @@ -79,6 +81,13 @@
>> gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000
>> gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000
>>
>> + #
>> + # PCI PCDs.
>> + #
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
>> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x10000
>> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x7FC
>> +
>>
>>
>##################################################################
>####
>> ##########
>> #
>> # Components Section - list of all EDK II Modules needed by this
>> Platform @@ -99,4 +108,11 @@
>> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
>> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
>>
>> + Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>> + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
>> + <PcdsFixedAtBuild>
>> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
>> + }
>> + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
>> +
>> ##
>> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
>> b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
>> index 6b5b63f..7993bf1 100644
>> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
>> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
>> @@ -130,6 +130,13 @@ READ_LOCK_STATUS = TRUE
>> INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
>>
>> #
>> + # PCI
>> + #
>> + INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>> + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
>> + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
>> +
>> + #
>> # Network modules
>> #
>> INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
>> @@ -154,6 +161,8 @@ READ_LOCK_STATUS = TRUE
>> INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
>> !endif
>>
>> + INF
>> +
>ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
>> +
>
>I'm pretty OK with most of these random updates squashed into one file, but the
>TftpDynamicCommand is something I generally don't like to see included by
>default.
>
>Other platforms put this inside a conditional statement:
>
>!ifdef $(INCLUDE_TFTP_COMMAND)
> INF
>ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
>!endif
>
>so that it can be included when -D INCLUDE_TFTP_COMMAND=1 is added to the
>build command line.
>
>But beyond that, there is no mention of this addition in the commit message. So
>please add a notice, or break this specific item out as a separate patch.
Alright agree, I will update for conditional inclusion and submit as separate patch.
>
>> #
>> # FAT filesystem + GPT/MBR partitioning
>> #
>> diff --git
>> a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
>> b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
>> index 7feac56..f2c8b66 100644
>> ---
>> a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
>> +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.in
>> +++ f
>> @@ -65,3 +65,5 @@
>> gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
>> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
>> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
>> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize
>> diff --git
>> a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>> b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>> index 64c5612..1ef3292 100644
>> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>> +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>> @@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap (
>> VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
>> VirtualMemoryTable[Index].Attributes =
>ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>>
>> + // ROM Space
>> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
>> + (PcdRomBaseAddr); VirtualMemoryTable[Index].VirtualBase =
>FixedPcdGet64 (PcdRomBaseAddr);
>> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
>> + VirtualMemoryTable[Index].Attributes =
>ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> // IFC region 1
>> //
>> // A-009241 : Unaligned write transactions to IFC may result in corruption of
>data
>> diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc
>> index 5987cd6..f5bb2e9 100644
>> --- a/Platform/NXP/NxpQoriqLs.dsc
>> +++ b/Platform/NXP/NxpQoriqLs.dsc
>> @@ -244,6 +244,8 @@
>>
>> gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
>>
>> + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|20
>> +
>> #
>> # Optional feature to help prevent EFI memory map fragments
>> # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
>> @@ -409,4 +411,9 @@
>> !endif #$(NO_SHELL_PROFILES)
>> }
>>
>> + #
>> + # TFTP Shell Command
>> + #
>> +
>ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
>> +
>
>Same comment, conditional?
>
>/
> Leif
>
Ok, Sure.
>> ##
>> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc
>> b/Silicon/NXP/LS1043A/LS1043A.dsc index a4eb117..f3220fa 100644
>> --- a/Silicon/NXP/LS1043A/LS1043A.dsc
>> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc
>> @@ -64,6 +64,9 @@
>> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
>> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
>> gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
>> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3
>> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
>> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
>>
>> #
>> # Big Endian IPs
>> @@ -71,5 +74,6 @@
>> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
>> gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
>> gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE
>>
>> ##
>> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
>> index 3cb476d..a3508b5 100644
>> --- a/Silicon/NXP/NxpQoriqLs.dec
>> +++ b/Silicon/NXP/NxpQoriqLs.dec
>> @@ -79,6 +79,16 @@
>> gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129
>> gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A
>> gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0|UINT64|0x0000012B
>> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x0|UINT64|0x0000012C
>> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x0|UINT64|0x0000012D
>> +
>> + #
>> + # PCI PCDs
>> + #
>> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x000001D0
>> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x000001D1
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE|BOOLEAN|0x000001D2
>> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|0|UINT32|0x000001D3
>>
>> #
>> # IFC PCDs
>> --
>> 1.9.1
>>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 38/39] Platform/NXP:PCIe enablement for LS1046A RDB
2018-04-20 15:33 ` Leif Lindholm
@ 2018-04-24 12:48 ` Vabhav Sharma
0 siblings, 0 replies; 254+ messages in thread
From: Vabhav Sharma @ 2018-04-24 12:48 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi
>-----Original Message-----
>From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
>Sent: Friday, April 20, 2018 9:03 PM
>To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
><udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
><vabhav.sharma@nxp.com>
>Subject: Re: [PATCH edk2-platforms 38/39] Platform/NXP:PCIe enablement for
>LS1046A RDB
>
>On Fri, Feb 16, 2018 at 02:20:34PM +0530, Meenakshi wrote:
>> From: Vabhav <vabhav.sharma@nxp.com>
>>
>> Compilation: Update the fdf, dsc and dec files.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
>> ---
>> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 15
>+++++++++++++++
>> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 9 +++++++++
>> .../LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++
>> .../NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
>> Silicon/NXP/LS1046A/LS1046A.dsc | 3 +++
>> 5 files changed, 35 insertions(+)
>>
>> diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
>> b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
>> index 36002d5..231207d 100644
>> --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
>> +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
>> @@ -41,6 +41,8 @@
>> IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
>> BoardLib|Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
>> FpgaLib|Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
>> + PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>> +
>> + PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeL
>> + ib.inf
>>
>> [PcdsFixedAtBuild.common]
>>
>> @@ -65,6 +67,7 @@
>> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
>> gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
>> gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE
>>
>> #
>> # I2C controller Pcds
>> @@ -77,6 +80,12 @@
>> gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51
>> gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|100000
>>
>> + #
>> + # PCI PCDs.
>> + #
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
>> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x80000
>> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC
>>
>>
>##################################################################
>####
>> ##########
>> #
>> # Components Section - list of all EDK II Modules needed by this
>> Platform @@ -90,5 +99,11 @@
>>
>> Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
>> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
>> + Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>> + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
>> + <PcdsFixedAtBuild>
>> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
>> + }
>> + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
>>
>> ##
>> diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
>> b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
>> index 834e3a4..3351a06 100644
>> --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
>> +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
>> @@ -123,6 +123,13 @@ READ_LOCK_STATUS = TRUE
>> INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
>>
>> #
>> + # PCI
>> + #
>> + INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>> + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
>> + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
>> +
>> + #
>> # Network modules
>> #
>> INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
>> @@ -147,6 +154,8 @@ READ_LOCK_STATUS = TRUE
>> INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
>> !endif
>>
>> + INF
>> +
>ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
>> +
>
>Same comment as for previous platform(s): please conditionalise and mention in
>commit message.
>
>/
> Leif
Ok, I will update it.
>
>> #
>> # FAT filesystem + GPT/MBR partitioning
>> #
>> diff --git
>> a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
>> b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
>> index 49b57fc..5e09757 100644
>> ---
>> a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
>> +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.in
>> +++ f
>> @@ -42,6 +42,8 @@
>> gArmTokenSpaceGuid.PcdArmPrimaryCore
>> gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
>> gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
>> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize
>> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
>> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
>> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
>> diff --git
>> a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>> b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>> index 64c5612..1ef3292 100644
>> --- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>> +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>> @@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap (
>> VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
>> VirtualMemoryTable[Index].Attributes =
>ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>>
>> + // ROM Space
>> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
>> + (PcdRomBaseAddr); VirtualMemoryTable[Index].VirtualBase =
>FixedPcdGet64 (PcdRomBaseAddr);
>> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
>> + VirtualMemoryTable[Index].Attributes =
>ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> // IFC region 1
>> //
>> // A-009241 : Unaligned write transactions to IFC may result in corruption of
>data
>> diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc
>> b/Silicon/NXP/LS1046A/LS1046A.dsc index 9f87028..59a6150 100644
>> --- a/Silicon/NXP/LS1046A/LS1046A.dsc
>> +++ b/Silicon/NXP/LS1046A/LS1046A.dsc
>> @@ -64,5 +64,8 @@
>> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
>> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
>> gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
>> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3
>> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
>> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
>>
>> ##
>> --
>> 1.9.1
>>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 39/39] Platform/NXP:PCIe enablement for LS2088A RDB
2018-04-20 15:36 ` Leif Lindholm
@ 2018-04-24 12:50 ` Vabhav Sharma
0 siblings, 0 replies; 254+ messages in thread
From: Vabhav Sharma @ 2018-04-24 12:50 UTC (permalink / raw)
To: Leif Lindholm, Meenakshi Aggarwal
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi
>-----Original Message-----
>From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
>Sent: Friday, April 20, 2018 9:06 PM
>To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
><udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
><vabhav.sharma@nxp.com>
>Subject: Re: [PATCH edk2-platforms 39/39] Platform/NXP:PCIe enablement for
>LS2088A RDB
>
>On Fri, Feb 16, 2018 at 02:20:35PM +0530, Meenakshi wrote:
>> From: Vabhav <vabhav.sharma@nxp.com>
>>
>> Compilation: Update the fdf, dsc and dec files.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
>> ---
>> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 17
>+++++++++++++++++
>> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 9 +++++++++
>> .../Library/PlatformLib/ArmPlatformLib.inf | 2 ++
>> .../LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
>> Silicon/NXP/LS2088A/LS2088A.dsc | 3 +++
>> 5 files changed, 37 insertions(+)
>>
>> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
>> b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
>> index 4d32ea5..1ae55d4 100755
>> --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
>> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
>> @@ -43,6 +43,8 @@
>> BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
>> FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
>> NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
>> + PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>> +
>> + PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeL
>> + ib.inf
>>
>> [PcdsFixedAtBuild.common]
>>
>> @@ -97,6 +99,13 @@
>> gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x580000000
>> gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x580300000
>>
>> + #
>> + # PCI PCDs.
>> + #
>> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
>> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x80000
>> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC
>> +
>>
>>
>##################################################################
>####
>> ##########
>> #
>> # Components Section - list of all EDK II Modules needed by this
>> Platform @@ -115,3 +124,11 @@
>> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
>> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
>> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
>> + Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>> + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
>> + <PcdsFixedAtBuild>
>> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
>> + }
>> + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
>> +
>> + ##
>> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
>> b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
>> index 8688d85..35a79bd 100644
>> --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
>> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
>> @@ -127,6 +127,13 @@ READ_LOCK_STATUS = TRUE
>> INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
>>
>> #
>> + # PCI
>> + #
>> + INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>> + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
>> + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
>> +
>> + #
>> # Network modules
>> #
>> INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
>> @@ -153,6 +160,8 @@ READ_LOCK_STATUS = TRUE
>>
>> INF
>>
>MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDev
>> iceDxe.inf
>>
>> + INF
>> +
>ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
>> +
>
>Same comment as previously platforms: please conditionalise and mention in
>commit message.
>(Please add some detail to commit message in general about what is being
>enabled.)
>
>/
> Leif
Ok , Updated in header
I will update in commit message
Thanks.
>
>> #
>> # USB Support
>> #
>> diff --git
>> a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
>> b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
>> index f5e5abd..0b836a8 100644
>> ---
>> a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
>> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.in
>> +++ f
>> @@ -44,6 +44,8 @@
>> gArmTokenSpaceGuid.PcdArmPrimaryCore
>> gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
>> gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
>> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
>> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize
>> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
>> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
>> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
>> diff --git
>> a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>> b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>> index ccb49f6..8b2145b 100644
>> --- a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>> @@ -80,6 +80,12 @@ ArmPlatformGetVirtualMemoryMap (
>> VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
>> VirtualMemoryTable[Index].Attributes =
>ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>>
>> + // ROM Space
>> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64
>> + (PcdRomBaseAddr); VirtualMemoryTable[Index].VirtualBase =
>FixedPcdGet64 (PcdRomBaseAddr);
>> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
>> + VirtualMemoryTable[Index].Attributes =
>ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> // IFC region 1
>> //
>> // A-009241 : Unaligned write transactions to IFC may result in corruption of
>data
>> diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc
>> b/Silicon/NXP/LS2088A/LS2088A.dsc index 0d8fd82..831edea 100644
>> --- a/Silicon/NXP/LS2088A/LS2088A.dsc
>> +++ b/Silicon/NXP/LS2088A/LS2088A.dsc
>> @@ -69,5 +69,8 @@
>> gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
>> gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000
>> gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|2
>> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|4
>> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
>> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
>>
>> ##
>> --
>> 1.9.1
>>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 34/39] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
2018-04-24 12:33 ` Ard Biesheuvel
@ 2018-04-24 13:36 ` Vabhav Sharma
2018-04-24 14:02 ` Ard Biesheuvel
0 siblings, 1 reply; 254+ messages in thread
From: Vabhav Sharma @ 2018-04-24 13:36 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Meenakshi Aggarwal, Leif Lindholm, Kinney, Michael D,
edk2-devel@lists.01.org, Udit Kumar, Varun Sethi
>-----Original Message-----
>From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]
>Sent: Tuesday, April 24, 2018 6:04 PM
>To: Vabhav Sharma <vabhav.sharma@nxp.com>
>Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Leif Lindholm
><leif.lindholm@linaro.org>; Kinney, Michael D <michael.d.kinney@intel.com>;
>edk2-devel@lists.01.org; Udit Kumar <udit.kumar@nxp.com>; Varun Sethi
><V.Sethi@nxp.com>
>Subject: Re: [PATCH edk2-platforms 34/39] Silicon/NXP: Implement
>EFI_CPU_IO2_PROTOCOL
>
>On 24 April 2018 at 14:26, Vabhav Sharma <vabhav.sharma@nxp.com> wrote:
>>
>>
>>>-----Original Message-----
>>>From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]
>>>Sent: Friday, April 20, 2018 2:11 PM
>>>To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>>>Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
>>><michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar
>>><udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
>>><vabhav.sharma@nxp.com>
>>>Subject: Re: [PATCH edk2-platforms 34/39] Silicon/NXP: Implement
>>>EFI_CPU_IO2_PROTOCOL
>>>
>>>On 16 February 2018 at 09:50, Meenakshi <meenakshi.aggarwal@nxp.com>
>>>wrote:
>>>> From: Vabhav <vabhav.sharma@nxp.com>
>>>>
>>>> NXP SOC has mutiple PCIe RCs,Adding respective implementation of
>>>> EFI_CPU_IO2_PROTOCOL to provide Memory Space Read/Write functions
>>>> used by generic Host Bridge Driver including correct value for the
>>>> translation offset during MMIO accesses
>>>>
>>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>>> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
>>>> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>>>
>>>This driver looks completely wrong to me: MMIO access is memory
>>>mapped, and given that you don't implement PCI to CPU translation of
>>>MMIO accesses, the memory read and write functions should not perform
>>>any translation at all, and just relay the accesses. On the other
>>>hand, the I/O accessors are not implemented at all, and these are the
>>>ones that require translation, given that the I/O port addresses in the CPU
>space need translation to MMIO addressess.
>>
>> On NXP SoC, Mapping between CPU view and PCIe view is not 1:1 and require
>CPU view translation for MMIO regions access, Accordingly translation is added
>during memory read/write services.
>> Bus driver relays the address range where PCIe device Bar region is split from,
>Translation is required for relaying it to correct PCIe controller cpu view address.
>>
>
>You cannot implement this only in the EFI_CPU_IO2_PROTOCOL driver.
>That way, EFI_PCI_IO_PROTOCOL.GetBarAttributes() will return resource
>descriptors with untranslated addresses, breaking drivers that rely on this
>information.
>
>If your PCIe implementation relies on MMIO translation, please refer to the
>recently merged code in EDK2 and edk2-platforms implementing this for
>Socionext SynQuacer.
Ok, PciIo->GetBarAttributes is expected to return CPU view address.
Are you referring to edk2 commit 74d0a33(Address translation support added to generic PciHostBridge driver)? Submitted patch development is done prior to this commit.
I will refer the commits for Socionext SynQuacer in edk2-platforms for MMIO translation.
>
>
>>>
>>>Also, you don't seem to be using the PcdPciExp?BaseAddr PCDs anywhere,
>>>so you can drop them from the .dsc
>> No, It's used for checking the access to MMIO32 region and CPU view
>> base address varies between different NXP SoCs
>>>
>>>> ---
>>>> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 529
>>>++++++++++++++++++++++
>>>> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 ++
>>>> 2 files changed, 577 insertions(+)
>>>> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>>>> create mode 100644
>>>> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>>>>
>>>> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>>>> b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>>>> new file mode 100644
>>>> index 0000000..b5fb72c
>>>> --- /dev/null
>>>> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>>>> @@ -0,0 +1,529 @@
>>>> +/** @file
>>>> + Produces the CPU I/O 2 Protocol.
>>>> +
>>>> + Copyright (c) 2009 - 2012, Intel Corporation. All rights
>>>> + reserved.<BR> Copyright (c) 2016, Linaro Ltd. All rights
>>>> + reserved.<BR> Copyright 2018 NXP
>>>> +
>>>> + This program and the accompanying materials are licensed and
>>>> + made available under the terms and conditions of the BSD License
>>>> + which accompanies this distribution. The full text of the license
>>>> + may be found at
>>>> +
>>>> + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
>>>> + op
>>>> + ensource.org%2Flicenses%2Fbsd-
>license.php&data=02%7C01%7Cvabhav.sh
>>>> + ar
>>>> +
>>>ma%40nxp.com%7C4507c0726b244ad6476d08d5a69a64ee%7C686ea1d3bc2b
>4c
>>>6fa9
>>>> +
>>>2cd99c5c301635%7C0%7C0%7C636598104414046440&sdata=IFSU0%2FeTdW
>rw
>>>gg0f
>>>> + 0Lq2qSVGgogG68tYZevrRmC%2BkV8%3D&reserved=0
>>>> +
>>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>>> + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
>EITHER
>>>EXPRESS OR IMPLIED.
>>>> +
>>>> +**/
>>>> +
>>>> +#include <Library/BaseLib.h>
>>>> +#include <Library/DebugLib.h>
>>>> +#include <Library/IoLib.h>
>>>> +#include <Library/PcdLib.h>
>>>> +#include <Library/UefiBootServicesTableLib.h>
>>>> +#include <Pcie.h>
>>>> +#include <Protocol/CpuIo2.h>
>>>> +
>>>> +#define MAX_IO_PORT_ADDRESS PCI_SEG2_PORTIO_MAX
>>>> +
>>>> +//
>>>> +// Handle for the CPU I/O 2 Protocol // STATIC EFI_HANDLE mHandle;
>>>> +
>>>> +//
>>>> +// Lookup table for increment values based on transfer widths //
>>>> +STATIC CONST UINT8 mInStride[] = {
>>>> + 1, // EfiCpuIoWidthUint8
>>>> + 2, // EfiCpuIoWidthUint16
>>>> + 4, // EfiCpuIoWidthUint32
>>>> + 8, // EfiCpuIoWidthUint64
>>>> + 0, // EfiCpuIoWidthFifoUint8
>>>> + 0, // EfiCpuIoWidthFifoUint16
>>>> + 0, // EfiCpuIoWidthFifoUint32
>>>> + 0, // EfiCpuIoWidthFifoUint64
>>>> + 1, // EfiCpuIoWidthFillUint8
>>>> + 2, // EfiCpuIoWidthFillUint16
>>>> + 4, // EfiCpuIoWidthFillUint32
>>>> + 8 // EfiCpuIoWidthFillUint64
>>>> +};
>>>> +
>>>> +//
>>>> +// Lookup table for increment values based on transfer widths //
>>>> +STATIC CONST UINT8 mOutStride[] = {
>>>> + 1, // EfiCpuIoWidthUint8
>>>> + 2, // EfiCpuIoWidthUint16
>>>> + 4, // EfiCpuIoWidthUint32
>>>> + 8, // EfiCpuIoWidthUint64
>>>> + 1, // EfiCpuIoWidthFifoUint8
>>>> + 2, // EfiCpuIoWidthFifoUint16
>>>> + 4, // EfiCpuIoWidthFifoUint32
>>>> + 8, // EfiCpuIoWidthFifoUint64
>>>> + 0, // EfiCpuIoWidthFillUint8
>>>> + 0, // EfiCpuIoWidthFillUint16
>>>> + 0, // EfiCpuIoWidthFillUint32
>>>> + 0 // EfiCpuIoWidthFillUint64
>>>> +};
>>>> +
>>>> +/**
>>>> + Check parameters to a CPU I/O 2 Protocol service request.
>>>> +
>>>> + The I/O operations are carried out exactly as requested. The
>>>> + caller is responsible for satisfying any alignment and I/O width
>>>> + restrictions that a PI System on a platform might require. For
>>>> + example on some platforms, width requests of
>>>> + EfiCpuIoWidthUint64 do not work.
>>>> +
>>>> + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for
>>>> + I/O
>>>Port operation.
>>>> + @param[in] Width Signifies the width of the I/O or Memory
>operation.
>>>> + @param[in] Address The base address of the I/O operation.
>>>> + @param[in] Count The number of I/O operations to perform. The
>>>number of
>>>> + bytes moved is Width size * Count, starting at Address.
>>>> + @param[in] Buffer For read operations, the destination buffer to store
>>>the results.
>>>> + For write operations, the source buffer
>>>> + from which to write
>>>data.
>>>> +
>>>> + @retval EFI_SUCCESS The parameters for this request pass the
>checks.
>>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given
>Width.
>>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>>Width,
>>>> + and Count is not valid for this PI system.
>>>> +
>>>> +**/
>>>> +STATIC
>>>> +EFI_STATUS
>>>> +CpuIoCheckParameter (
>>>> + IN BOOLEAN MmioOperation,
>>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>>> + IN UINT64 Address,
>>>> + IN UINTN Count,
>>>> + IN VOID *Buffer
>>>> + )
>>>> +{
>>>> + UINT64 MaxCount;
>>>> + UINT64 Limit;
>>>> +
>>>> + //
>>>> + // Check to see if Buffer is NULL // if (Buffer == NULL) {
>>>> + ASSERT (FALSE);
>>>> + return EFI_INVALID_PARAMETER;
>>>> + }
>>>> +
>>>> + //
>>>> + // Check to see if Width is in the valid range // if
>>>> + ((UINT32)Width >= EfiCpuIoWidthMaximum) {
>>>> + ASSERT (FALSE);
>>>> + return EFI_INVALID_PARAMETER;
>>>> + }
>>>> +
>>>> + //
>>>> + // For FIFO type, the target address won't increase during the
>>>> + access, // so treat Count as 1 // if (Width >=
>>>> + EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
>>>> + Count = 1;
>>>> + }
>>>> +
>>>> + //
>>>> + // Check to see if Width is in the valid range for I/O Port
>>>> + operations // Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
>>>> + if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
>>>> + ASSERT (FALSE);
>>>> + return EFI_INVALID_PARAMETER;
>>>> + }
>>>> +
>>>> + //
>>>> + // Check to see if Address is aligned // if ((Address &
>>>> + (UINT64)(mInStride[Width] - 1)) != 0) {
>>>> + ASSERT (FALSE);
>>>> + return EFI_UNSUPPORTED;
>>>> + }
>>>> +
>>>> + //
>>>> + // Check to see if any address associated with this transfer
>>>> + exceeds the maximum // allowed address. The maximum address
>>>> + implied by the parameters passed in is // Address + Size * Count.
>>>> + If the following condition is met, then the transfer // is not supported.
>>>> + //
>>>> + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS :
>>>MAX_IO_PORT_ADDRESS) + 1
>>>> + //
>>>> + // Since MAX_ADDRESS can be the maximum integer value supported
>>>> + by the CPU and Count // can also be the maximum integer value
>>>> + supported by the CPU, this range // check must be adjusted to
>>>> + avoid all
>>>oveflow conditions.
>>>> + //
>>>> + Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); if
>>>> + (Count == 0) {
>>>> + if (Address > Limit) {
>>>> + ASSERT (FALSE);
>>>> + return EFI_UNSUPPORTED;
>>>> + }
>>>> + } else {
>>>> + MaxCount = RShiftU64 (Limit, Width);
>>>> + if (MaxCount < (Count - 1)) {
>>>> + ASSERT (FALSE);
>>>> + return EFI_UNSUPPORTED;
>>>> + }
>>>> + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
>>>> + ASSERT (FALSE);
>>>> + return EFI_UNSUPPORTED;
>>>> + }
>>>> + }
>>>> +
>>>> + //
>>>> + // Check to see if Buffer is aligned // if (((UINTN)Buffer &
>>>> + ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
>>>> + ASSERT (FALSE);
>>>> + return EFI_UNSUPPORTED;
>>>> + }
>>>> +
>>>> + return EFI_SUCCESS;
>>>> +}
>>>> +
>>>> +/**
>>>> + Reads memory-mapped registers.
>>>> +
>>>> + The I/O operations are carried out exactly as requested. The
>>>> + caller is responsible for satisfying any alignment and I/O width
>>>> + restrictions that a PI System on a platform might require. For
>>>> + example on some platforms, width requests of
>>>> + EfiCpuIoWidthUint64 do not work.
>>>> +
>>>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>>>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address
>>>> + and Buffer are incremented for each of the Count operations that is
>performed.
>>>> +
>>>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>>>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>>>> + Buffer is incremented for each of the Count operations that is
>>>> + performed. The read or write operation is performed Count times
>>>> + on the
>>>same Address.
>>>> +
>>>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>>>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>>>> + Address is incremented for each of the Count operations that is
>>>> + performed. The read or write operation is performed Count times
>>>> + from the
>>>first element of Buffer.
>>>> +
>>>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>>>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>>>> + @param[in] Address The base address of the I/O operation.
>>>> + @param[in] Count The number of I/O operations to perform. The
>number
>>>of
>>>> + bytes moved is Width size * Count, starting at Address.
>>>> + @param[out] Buffer For read operations, the destination buffer to store
>the
>>>results.
>>>> + For write operations, the source buffer from which to write
>data.
>>>> +
>>>> + @retval EFI_SUCCESS The data was read from or written to the PI
>>>system.
>>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given
>Width.
>>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>>Width,
>>>> + and Count is not valid for this PI system.
>>>> +
>>>> +**/
>>>> +STATIC
>>>> +EFI_STATUS
>>>> +EFIAPI
>>>> +CpuMemoryServiceRead (
>>>> + IN EFI_CPU_IO2_PROTOCOL *This,
>>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>>> + IN UINT64 Address,
>>>> + IN UINTN Count,
>>>> + OUT VOID *Buffer
>>>> + )
>>>> +{
>>>> + EFI_STATUS Status;
>>>> + UINT8 InStride;
>>>> + UINT8 OutStride;
>>>> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
>>>> + UINT8 *Uint8Buffer;
>>>> +
>>>> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count,
>>>> + Buffer); if (EFI_ERROR (Status)) {
>>>> + return Status;
>>>> + }
>>>> +
>>>> + if ((Address >= PCI_SEG0_MMIO32_MIN) &&
>>>> + (Address <= PCI_SEG0_MMIO32_MAX)) {
>>>> + Address += PCI_SEG0_MMIO_MEMBASE; } else if ((Address >=
>>>> + PCI_SEG1_MMIO32_MIN) &&
>>>> + (Address <= PCI_SEG1_MMIO32_MAX)) {
>>>> + Address += PCI_SEG1_MMIO_MEMBASE; } else if ((Address >=
>>>> + PCI_SEG2_MMIO32_MIN) &&
>>>> + (Address <= PCI_SEG2_MMIO32_MAX)) {
>>>> + Address += PCI_SEG2_MMIO_MEMBASE; } else if ((Address >=
>>>> + PCI_SEG3_MMIO32_MIN) &&
>>>> + (Address <= PCI_SEG3_MMIO32_MAX)) {
>>>> + Address += PCI_SEG3_MMIO_MEMBASE; } else {
>>>> + ASSERT (FALSE);
>>>> + return EFI_INVALID_PARAMETER;
>>>> + }
>>>> +
>>>> + //
>>>> + // Select loop based on the width of the transfer // InStride =
>>>> + mInStride[Width]; OutStride = mOutStride[Width]; OperationWidth
>>>> + = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); for (Uint8Buffer =
>>>> + Buffer; Count > 0; Address += InStride, Uint8Buffer +=
>>>OutStride, Count--) {
>>>> + if (OperationWidth == EfiCpuIoWidthUint8) {
>>>> + *Uint8Buffer = MmioRead8 ((UINTN)Address);
>>>> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
>>>> + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
>>>> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
>>>> + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
>>>> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
>>>> + *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
>>>> + }
>>>> + }
>>>> + return EFI_SUCCESS;
>>>> +}
>>>> +
>>>> +/**
>>>> + Writes memory-mapped registers.
>>>> +
>>>> + The I/O operations are carried out exactly as requested. The
>>>> + caller is responsible for satisfying any alignment and I/O width
>>>> + restrictions that a PI System on a platform might require. For
>>>> + example on some platforms, width requests of
>>>> + EfiCpuIoWidthUint64 do not work.
>>>> +
>>>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>>>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address
>>>> + and Buffer are incremented for each of the Count operations that is
>performed.
>>>> +
>>>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>>>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>>>> + Buffer is incremented for each of the Count operations that is
>>>> + performed. The read or write operation is performed Count times
>>>> + on the
>>>same Address.
>>>> +
>>>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>>>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>>>> + Address is incremented for each of the Count operations that is
>>>> + performed. The read or write operation is performed Count times
>>>> + from the
>>>first element of Buffer.
>>>> +
>>>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>>>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>>>> + @param[in] Address The base address of the I/O operation.
>>>> + @param[in] Count The number of I/O operations to perform. The
>number
>>>of
>>>> + bytes moved is Width size * Count, starting at Address.
>>>> + @param[in] Buffer For read operations, the destination buffer to store
>the
>>>results.
>>>> + For write operations, the source buffer from which to write
>data.
>>>> +
>>>> + @retval EFI_SUCCESS The data was read from or written to the PI
>>>system.
>>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given
>Width.
>>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>>Width,
>>>> + and Count is not valid for this PI system.
>>>> +
>>>> +**/
>>>> +STATIC
>>>> +EFI_STATUS
>>>> +EFIAPI
>>>> +CpuMemoryServiceWrite (
>>>> + IN EFI_CPU_IO2_PROTOCOL *This,
>>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>>> + IN UINT64 Address,
>>>> + IN UINTN Count,
>>>> + IN VOID *Buffer
>>>> + )
>>>> +{
>>>> + EFI_STATUS Status;
>>>> + UINT8 InStride;
>>>> + UINT8 OutStride;
>>>> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
>>>> + UINT8 *Uint8Buffer;
>>>> +
>>>> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count,
>>>> + Buffer); if (EFI_ERROR (Status)) {
>>>> + return Status;
>>>> + }
>>>> +
>>>> + if ((Address >= PCI_SEG0_MMIO32_MIN) &&
>>>> + (Address <= PCI_SEG0_MMIO32_MAX)) {
>>>> + Address += PCI_SEG0_MMIO_MEMBASE; } else if ((Address >=
>>>> + PCI_SEG1_MMIO32_MIN) &&
>>>> + (Address <= PCI_SEG1_MMIO32_MAX)) {
>>>> + Address += PCI_SEG1_MMIO_MEMBASE; } else if ((Address >=
>>>> + PCI_SEG2_MMIO32_MIN) &&
>>>> + (Address <= PCI_SEG2_MMIO32_MAX)) {
>>>> + Address += PCI_SEG2_MMIO_MEMBASE; } else if ((Address >=
>>>> + PCI_SEG3_MMIO32_MIN) &&
>>>> + (Address <= PCI_SEG3_MMIO32_MAX)) {
>>>> + Address += PCI_SEG3_MMIO_MEMBASE; } else {
>>>> + ASSERT (FALSE);
>>>> + return EFI_INVALID_PARAMETER;
>>>> + }
>>>> +
>>>> + //
>>>> + // Select loop based on the width of the transfer // InStride =
>>>> + mInStride[Width]; OutStride = mOutStride[Width]; OperationWidth
>>>> + = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); for (Uint8Buffer =
>>>> + Buffer; Count > 0; Address += InStride, Uint8Buffer +=
>>>OutStride, Count--) {
>>>> + if (OperationWidth == EfiCpuIoWidthUint8) {
>>>> + MmioWrite8 ((UINTN)Address, *Uint8Buffer);
>>>> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
>>>> + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
>>>> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
>>>> + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
>>>> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
>>>> + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
>>>> + }
>>>> + }
>>>> + return EFI_SUCCESS;
>>>> +}
>>>> +
>>>> +/**
>>>> + Reads I/O registers.
>>>> +
>>>> + The I/O operations are carried out exactly as requested. The
>>>> + caller is responsible for satisfying any alignment and I/O width
>>>> + restrictions that a PI System on a platform might require. For
>>>> + example on some platforms, width requests of
>>>> + EfiCpuIoWidthUint64 do not work.
>>>> +
>>>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>>>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address
>>>> + and Buffer are incremented for each of the Count operations that is
>performed.
>>>> +
>>>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>>>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>>>> + Buffer is incremented for each of the Count operations that is
>>>> + performed. The read or write operation is performed Count times
>>>> + on the
>>>same Address.
>>>> +
>>>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>>>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>>>> + Address is incremented for each of the Count operations that is
>>>> + performed. The read or write operation is performed Count times
>>>> + from the
>>>first element of Buffer.
>>>> +
>>>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>>>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>>>> + @param[in] Address The base address of the I/O operation.
>>>> + @param[in] Count The number of I/O operations to perform. The
>number
>>>of
>>>> + bytes moved is Width size * Count, starting at Address.
>>>> + @param[out] Buffer For read operations, the destination buffer to store
>the
>>>results.
>>>> + For write operations, the source buffer from which to write
>data.
>>>> +
>>>> + @retval EFI_SUCCESS The data was read from or written to the PI
>>>system.
>>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given
>Width.
>>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>>Width,
>>>> + and Count is not valid for this PI system.
>>>> +
>>>> +**/
>>>> +STATIC
>>>> +EFI_STATUS
>>>> +EFIAPI
>>>> +CpuIoServiceRead (
>>>> + IN EFI_CPU_IO2_PROTOCOL *This,
>>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>>> + IN UINT64 Address,
>>>> + IN UINTN Count,
>>>> + OUT VOID *Buffer
>>>> + )
>>>> +{
>>>> + return EFI_SUCCESS;
>>>> +}
>>>> +
>>>> +/**
>>>> + Write I/O registers.
>>>> +
>>>> + The I/O operations are carried out exactly as requested. The
>>>> + caller is responsible for satisfying any alignment and I/O width
>>>> + restrictions that a PI System on a platform might require. For
>>>> + example on some platforms, width requests of
>>>> + EfiCpuIoWidthUint64 do not work.
>>>> +
>>>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>>>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address
>>>> + and Buffer are incremented for each of the Count operations that is
>performed.
>>>> +
>>>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>>>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>>>> + Buffer is incremented for each of the Count operations that is
>>>> + performed. The read or write operation is performed Count times
>>>> + on the
>>>same Address.
>>>> +
>>>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>>>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>>>> + Address is incremented for each of the Count operations that is
>>>> + performed. The read or write operation is performed Count times
>>>> + from the
>>>first element of Buffer.
>>>> +
>>>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>>>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>>>> + @param[in] Address The base address of the I/O operation.
>>>> + @param[in] Count The number of I/O operations to perform. The
>number
>>>of
>>>> + bytes moved is Width size * Count, starting at Address.
>>>> + @param[in] Buffer For read operations, the destination buffer to store
>the
>>>results.
>>>> + For write operations, the source buffer from which to write
>data.
>>>> +
>>>> + @retval EFI_SUCCESS The data was read from or written to the PI
>>>system.
>>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given
>Width.
>>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>>Width,
>>>> + and Count is not valid for this PI system.
>>>> +
>>>> +**/
>>>> +STATIC
>>>> +EFI_STATUS
>>>> +EFIAPI
>>>> +CpuIoServiceWrite (
>>>> + IN EFI_CPU_IO2_PROTOCOL *This,
>>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>>> + IN UINT64 Address,
>>>> + IN UINTN Count,
>>>> + IN VOID *Buffer
>>>> + )
>>>> +{
>>>> + return EFI_SUCCESS;
>>>> +}
>>>> +
>>>> +//
>>>> +// CPU I/O 2 Protocol instance
>>>> +//
>>>> +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
>>>> + {
>>>> + CpuMemoryServiceRead,
>>>> + CpuMemoryServiceWrite
>>>> + },
>>>> + {
>>>> + CpuIoServiceRead,
>>>> + CpuIoServiceWrite
>>>> + }
>>>> +};
>>>> +
>>>> +
>>>> +/**
>>>> + The user Entry Point for module CpuIo2Dxe. The user code starts
>>>> +with this
>>>function.
>>>> +
>>>> + @param[in] ImageHandle The firmware allocated handle for the EFI
>image.
>>>> + @param[in] SystemTable A pointer to the EFI System Table.
>>>> +
>>>> + @retval EFI_SUCCESS The entry point is executed successfully.
>>>> + @retval other Some error occurs when executing this entry point.
>>>> +
>>>> +**/
>>>> +EFI_STATUS
>>>> +EFIAPI
>>>> +PciCpuIo2Initialize (
>>>> + IN EFI_HANDLE ImageHandle,
>>>> + IN EFI_SYSTEM_TABLE *SystemTable
>>>> + )
>>>> +{
>>>> + EFI_STATUS Status;
>>>> +
>>>> + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL,
>>>> + &gEfiCpuIo2ProtocolGuid); Status = gBS->InstallMultipleProtocolInterfaces
>(
>>>> + &mHandle,
>>>> + &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
>>>> + NULL
>>>> + );
>>>> + ASSERT_EFI_ERROR (Status);
>>>> +
>>>> + return Status;
>>>> +}
>>>> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>>>> b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>>>> new file mode 100644
>>>> index 0000000..25a1db1
>>>> --- /dev/null
>>>> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>>>> @@ -0,0 +1,48 @@
>>>> +## @file
>>>> +# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
>>>> +#
>>>> +# Copyright 2018 NXP
>>>> +#
>>>> +# This program and the accompanying materials # are licensed and
>>>> +made available under the terms and conditions of the BSD License #
>>>> +which accompanies this distribution. The full text of the license
>>>> +may be found at #
>>>> +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fo
>>>> +pe
>>>> +nsource.org%2Flicenses%2Fbsd-
>>>license.php&data=02%7C01%7Cvabhav.sharma
>>>>
>>>+%40nxp.com%7C4507c0726b244ad6476d08d5a69a64ee%7C686ea1d3bc2b4c
>6f
>>>a92cd
>>>>
>>>+99c5c301635%7C0%7C0%7C636598104414046440&sdata=IFSU0%2FeTdWrw
>gg
>>>0f0Lq2
>>>> +qSVGgogG68tYZevrRmC%2BkV8%3D&reserved=0
>>>> +#
>>>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>>> +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
>EITHER
>>>EXPRESS OR IMPLIED.
>>>> +#
>>>> +##
>>>> +
>>>> +[Defines]
>>>> + INF_VERSION = 0x0001001A
>>>> + BASE_NAME = PciCpuIo2Dxe
>>>> + FILE_GUID = 7bff18d7-9aae-434b-9c06-f10a7e157eac
>>>> + MODULE_TYPE = DXE_DRIVER
>>>> + VERSION_STRING = 1.0
>>>> + ENTRY_POINT = PciCpuIo2Initialize
>>>> +
>>>> +[Sources]
>>>> + PciCpuIo2Dxe.c
>>>> +
>>>> +[Packages]
>>>> + MdePkg/MdePkg.dec
>>>> + Silicon/NXP/NxpQoriqLs.dec
>>>> +
>>>> +[LibraryClasses]
>>>> + BaseLib
>>>> + DebugLib
>>>> + IoLib
>>>> + UefiBootServicesTableLib
>>>> + UefiDriverEntryPoint
>>>> +
>>>> +[Pcd]
>>>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
>>>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
>>>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
>>>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
>>>> +
>>>> +[Protocols]
>>>> + gEfiCpuIo2ProtocolGuid ## PRODUCES
>>>> +
>>>> +[Depex]
>>>> + TRUE
>>>> --
>>>> 1.9.1
>>>>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 34/39] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
2018-04-24 13:36 ` Vabhav Sharma
@ 2018-04-24 14:02 ` Ard Biesheuvel
0 siblings, 0 replies; 254+ messages in thread
From: Ard Biesheuvel @ 2018-04-24 14:02 UTC (permalink / raw)
To: Vabhav Sharma
Cc: Meenakshi Aggarwal, Leif Lindholm, Kinney, Michael D,
edk2-devel@lists.01.org, Udit Kumar, Varun Sethi
On 24 April 2018 at 15:36, Vabhav Sharma <vabhav.sharma@nxp.com> wrote:
>
>
>>-----Original Message-----
>>From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]
>>Sent: Tuesday, April 24, 2018 6:04 PM
>>To: Vabhav Sharma <vabhav.sharma@nxp.com>
>>Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>; Leif Lindholm
>><leif.lindholm@linaro.org>; Kinney, Michael D <michael.d.kinney@intel.com>;
>>edk2-devel@lists.01.org; Udit Kumar <udit.kumar@nxp.com>; Varun Sethi
>><V.Sethi@nxp.com>
>>Subject: Re: [PATCH edk2-platforms 34/39] Silicon/NXP: Implement
>>EFI_CPU_IO2_PROTOCOL
>>
>>On 24 April 2018 at 14:26, Vabhav Sharma <vabhav.sharma@nxp.com> wrote:
>>>
>>>
>>>>-----Original Message-----
>>>>From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]
>>>>Sent: Friday, April 20, 2018 2:11 PM
>>>>To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>>>>Cc: Leif Lindholm <leif.lindholm@linaro.org>; Kinney, Michael D
>>>><michael.d.kinney@intel.com>; edk2-devel@lists.01.org; Udit Kumar
>>>><udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
>>>><vabhav.sharma@nxp.com>
>>>>Subject: Re: [PATCH edk2-platforms 34/39] Silicon/NXP: Implement
>>>>EFI_CPU_IO2_PROTOCOL
>>>>
>>>>On 16 February 2018 at 09:50, Meenakshi <meenakshi.aggarwal@nxp.com>
>>>>wrote:
>>>>> From: Vabhav <vabhav.sharma@nxp.com>
>>>>>
>>>>> NXP SOC has mutiple PCIe RCs,Adding respective implementation of
>>>>> EFI_CPU_IO2_PROTOCOL to provide Memory Space Read/Write functions
>>>>> used by generic Host Bridge Driver including correct value for the
>>>>> translation offset during MMIO accesses
>>>>>
>>>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>>>> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
>>>>> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>>>>
>>>>This driver looks completely wrong to me: MMIO access is memory
>>>>mapped, and given that you don't implement PCI to CPU translation of
>>>>MMIO accesses, the memory read and write functions should not perform
>>>>any translation at all, and just relay the accesses. On the other
>>>>hand, the I/O accessors are not implemented at all, and these are the
>>>>ones that require translation, given that the I/O port addresses in the CPU
>>space need translation to MMIO addressess.
>>>
>>> On NXP SoC, Mapping between CPU view and PCIe view is not 1:1 and require
>>CPU view translation for MMIO regions access, Accordingly translation is added
>>during memory read/write services.
>>> Bus driver relays the address range where PCIe device Bar region is split from,
>>Translation is required for relaying it to correct PCIe controller cpu view address.
>>>
>>
>>You cannot implement this only in the EFI_CPU_IO2_PROTOCOL driver.
>>That way, EFI_PCI_IO_PROTOCOL.GetBarAttributes() will return resource
>>descriptors with untranslated addresses, breaking drivers that rely on this
>>information.
>>
>>If your PCIe implementation relies on MMIO translation, please refer to the
>>recently merged code in EDK2 and edk2-platforms implementing this for
>>Socionext SynQuacer.
> Ok, PciIo->GetBarAttributes is expected to return CPU view address.
Yes
> Are you referring to edk2 commit 74d0a33(Address translation support added to generic PciHostBridge driver)? Submitted patch development is done prior to this commit.
I understand. But that does not make your code correct.
> I will refer the commits for Socionext SynQuacer in edk2-platforms for MMIO translation.
Yes please. And I/O translation needs to be implemented as well.
>>>>
>>>>Also, you don't seem to be using the PcdPciExp?BaseAddr PCDs anywhere,
>>>>so you can drop them from the .dsc
>>> No, It's used for checking the access to MMIO32 region and CPU view
>>> base address varies between different NXP SoCs
>>>>
>>>>> ---
>>>>> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 529
>>>>++++++++++++++++++++++
>>>>> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 ++
>>>>> 2 files changed, 577 insertions(+)
>>>>> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>>>>> create mode 100644
>>>>> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>>>>>
>>>>> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>>>>> b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>>>>> new file mode 100644
>>>>> index 0000000..b5fb72c
>>>>> --- /dev/null
>>>>> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
>>>>> @@ -0,0 +1,529 @@
>>>>> +/** @file
>>>>> + Produces the CPU I/O 2 Protocol.
>>>>> +
>>>>> + Copyright (c) 2009 - 2012, Intel Corporation. All rights
>>>>> + reserved.<BR> Copyright (c) 2016, Linaro Ltd. All rights
>>>>> + reserved.<BR> Copyright 2018 NXP
>>>>> +
>>>>> + This program and the accompanying materials are licensed and
>>>>> + made available under the terms and conditions of the BSD License
>>>>> + which accompanies this distribution. The full text of the license
>>>>> + may be found at
>>>>> +
>>>>> + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
>>>>> + op
>>>>> + ensource.org%2Flicenses%2Fbsd-
>>license.php&data=02%7C01%7Cvabhav.sh
>>>>> + ar
>>>>> +
>>>>ma%40nxp.com%7C4507c0726b244ad6476d08d5a69a64ee%7C686ea1d3bc2b
>>4c
>>>>6fa9
>>>>> +
>>>>2cd99c5c301635%7C0%7C0%7C636598104414046440&sdata=IFSU0%2FeTdW
>>rw
>>>>gg0f
>>>>> + 0Lq2qSVGgogG68tYZevrRmC%2BkV8%3D&reserved=0
>>>>> +
>>>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>>>> + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
>>EITHER
>>>>EXPRESS OR IMPLIED.
>>>>> +
>>>>> +**/
>>>>> +
>>>>> +#include <Library/BaseLib.h>
>>>>> +#include <Library/DebugLib.h>
>>>>> +#include <Library/IoLib.h>
>>>>> +#include <Library/PcdLib.h>
>>>>> +#include <Library/UefiBootServicesTableLib.h>
>>>>> +#include <Pcie.h>
>>>>> +#include <Protocol/CpuIo2.h>
>>>>> +
>>>>> +#define MAX_IO_PORT_ADDRESS PCI_SEG2_PORTIO_MAX
>>>>> +
>>>>> +//
>>>>> +// Handle for the CPU I/O 2 Protocol // STATIC EFI_HANDLE mHandle;
>>>>> +
>>>>> +//
>>>>> +// Lookup table for increment values based on transfer widths //
>>>>> +STATIC CONST UINT8 mInStride[] = {
>>>>> + 1, // EfiCpuIoWidthUint8
>>>>> + 2, // EfiCpuIoWidthUint16
>>>>> + 4, // EfiCpuIoWidthUint32
>>>>> + 8, // EfiCpuIoWidthUint64
>>>>> + 0, // EfiCpuIoWidthFifoUint8
>>>>> + 0, // EfiCpuIoWidthFifoUint16
>>>>> + 0, // EfiCpuIoWidthFifoUint32
>>>>> + 0, // EfiCpuIoWidthFifoUint64
>>>>> + 1, // EfiCpuIoWidthFillUint8
>>>>> + 2, // EfiCpuIoWidthFillUint16
>>>>> + 4, // EfiCpuIoWidthFillUint32
>>>>> + 8 // EfiCpuIoWidthFillUint64
>>>>> +};
>>>>> +
>>>>> +//
>>>>> +// Lookup table for increment values based on transfer widths //
>>>>> +STATIC CONST UINT8 mOutStride[] = {
>>>>> + 1, // EfiCpuIoWidthUint8
>>>>> + 2, // EfiCpuIoWidthUint16
>>>>> + 4, // EfiCpuIoWidthUint32
>>>>> + 8, // EfiCpuIoWidthUint64
>>>>> + 1, // EfiCpuIoWidthFifoUint8
>>>>> + 2, // EfiCpuIoWidthFifoUint16
>>>>> + 4, // EfiCpuIoWidthFifoUint32
>>>>> + 8, // EfiCpuIoWidthFifoUint64
>>>>> + 0, // EfiCpuIoWidthFillUint8
>>>>> + 0, // EfiCpuIoWidthFillUint16
>>>>> + 0, // EfiCpuIoWidthFillUint32
>>>>> + 0 // EfiCpuIoWidthFillUint64
>>>>> +};
>>>>> +
>>>>> +/**
>>>>> + Check parameters to a CPU I/O 2 Protocol service request.
>>>>> +
>>>>> + The I/O operations are carried out exactly as requested. The
>>>>> + caller is responsible for satisfying any alignment and I/O width
>>>>> + restrictions that a PI System on a platform might require. For
>>>>> + example on some platforms, width requests of
>>>>> + EfiCpuIoWidthUint64 do not work.
>>>>> +
>>>>> + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for
>>>>> + I/O
>>>>Port operation.
>>>>> + @param[in] Width Signifies the width of the I/O or Memory
>>operation.
>>>>> + @param[in] Address The base address of the I/O operation.
>>>>> + @param[in] Count The number of I/O operations to perform. The
>>>>number of
>>>>> + bytes moved is Width size * Count, starting at Address.
>>>>> + @param[in] Buffer For read operations, the destination buffer to store
>>>>the results.
>>>>> + For write operations, the source buffer
>>>>> + from which to write
>>>>data.
>>>>> +
>>>>> + @retval EFI_SUCCESS The parameters for this request pass the
>>checks.
>>>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given
>>Width.
>>>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>>>Width,
>>>>> + and Count is not valid for this PI system.
>>>>> +
>>>>> +**/
>>>>> +STATIC
>>>>> +EFI_STATUS
>>>>> +CpuIoCheckParameter (
>>>>> + IN BOOLEAN MmioOperation,
>>>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>>>> + IN UINT64 Address,
>>>>> + IN UINTN Count,
>>>>> + IN VOID *Buffer
>>>>> + )
>>>>> +{
>>>>> + UINT64 MaxCount;
>>>>> + UINT64 Limit;
>>>>> +
>>>>> + //
>>>>> + // Check to see if Buffer is NULL // if (Buffer == NULL) {
>>>>> + ASSERT (FALSE);
>>>>> + return EFI_INVALID_PARAMETER;
>>>>> + }
>>>>> +
>>>>> + //
>>>>> + // Check to see if Width is in the valid range // if
>>>>> + ((UINT32)Width >= EfiCpuIoWidthMaximum) {
>>>>> + ASSERT (FALSE);
>>>>> + return EFI_INVALID_PARAMETER;
>>>>> + }
>>>>> +
>>>>> + //
>>>>> + // For FIFO type, the target address won't increase during the
>>>>> + access, // so treat Count as 1 // if (Width >=
>>>>> + EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
>>>>> + Count = 1;
>>>>> + }
>>>>> +
>>>>> + //
>>>>> + // Check to see if Width is in the valid range for I/O Port
>>>>> + operations // Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
>>>>> + if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
>>>>> + ASSERT (FALSE);
>>>>> + return EFI_INVALID_PARAMETER;
>>>>> + }
>>>>> +
>>>>> + //
>>>>> + // Check to see if Address is aligned // if ((Address &
>>>>> + (UINT64)(mInStride[Width] - 1)) != 0) {
>>>>> + ASSERT (FALSE);
>>>>> + return EFI_UNSUPPORTED;
>>>>> + }
>>>>> +
>>>>> + //
>>>>> + // Check to see if any address associated with this transfer
>>>>> + exceeds the maximum // allowed address. The maximum address
>>>>> + implied by the parameters passed in is // Address + Size * Count.
>>>>> + If the following condition is met, then the transfer // is not supported.
>>>>> + //
>>>>> + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS :
>>>>MAX_IO_PORT_ADDRESS) + 1
>>>>> + //
>>>>> + // Since MAX_ADDRESS can be the maximum integer value supported
>>>>> + by the CPU and Count // can also be the maximum integer value
>>>>> + supported by the CPU, this range // check must be adjusted to
>>>>> + avoid all
>>>>oveflow conditions.
>>>>> + //
>>>>> + Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); if
>>>>> + (Count == 0) {
>>>>> + if (Address > Limit) {
>>>>> + ASSERT (FALSE);
>>>>> + return EFI_UNSUPPORTED;
>>>>> + }
>>>>> + } else {
>>>>> + MaxCount = RShiftU64 (Limit, Width);
>>>>> + if (MaxCount < (Count - 1)) {
>>>>> + ASSERT (FALSE);
>>>>> + return EFI_UNSUPPORTED;
>>>>> + }
>>>>> + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
>>>>> + ASSERT (FALSE);
>>>>> + return EFI_UNSUPPORTED;
>>>>> + }
>>>>> + }
>>>>> +
>>>>> + //
>>>>> + // Check to see if Buffer is aligned // if (((UINTN)Buffer &
>>>>> + ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
>>>>> + ASSERT (FALSE);
>>>>> + return EFI_UNSUPPORTED;
>>>>> + }
>>>>> +
>>>>> + return EFI_SUCCESS;
>>>>> +}
>>>>> +
>>>>> +/**
>>>>> + Reads memory-mapped registers.
>>>>> +
>>>>> + The I/O operations are carried out exactly as requested. The
>>>>> + caller is responsible for satisfying any alignment and I/O width
>>>>> + restrictions that a PI System on a platform might require. For
>>>>> + example on some platforms, width requests of
>>>>> + EfiCpuIoWidthUint64 do not work.
>>>>> +
>>>>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>>>>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address
>>>>> + and Buffer are incremented for each of the Count operations that is
>>performed.
>>>>> +
>>>>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>>>>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>>>>> + Buffer is incremented for each of the Count operations that is
>>>>> + performed. The read or write operation is performed Count times
>>>>> + on the
>>>>same Address.
>>>>> +
>>>>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>>>>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>>>>> + Address is incremented for each of the Count operations that is
>>>>> + performed. The read or write operation is performed Count times
>>>>> + from the
>>>>first element of Buffer.
>>>>> +
>>>>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>>>>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>>>>> + @param[in] Address The base address of the I/O operation.
>>>>> + @param[in] Count The number of I/O operations to perform. The
>>number
>>>>of
>>>>> + bytes moved is Width size * Count, starting at Address.
>>>>> + @param[out] Buffer For read operations, the destination buffer to store
>>the
>>>>results.
>>>>> + For write operations, the source buffer from which to write
>>data.
>>>>> +
>>>>> + @retval EFI_SUCCESS The data was read from or written to the PI
>>>>system.
>>>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given
>>Width.
>>>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>>>Width,
>>>>> + and Count is not valid for this PI system.
>>>>> +
>>>>> +**/
>>>>> +STATIC
>>>>> +EFI_STATUS
>>>>> +EFIAPI
>>>>> +CpuMemoryServiceRead (
>>>>> + IN EFI_CPU_IO2_PROTOCOL *This,
>>>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>>>> + IN UINT64 Address,
>>>>> + IN UINTN Count,
>>>>> + OUT VOID *Buffer
>>>>> + )
>>>>> +{
>>>>> + EFI_STATUS Status;
>>>>> + UINT8 InStride;
>>>>> + UINT8 OutStride;
>>>>> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
>>>>> + UINT8 *Uint8Buffer;
>>>>> +
>>>>> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count,
>>>>> + Buffer); if (EFI_ERROR (Status)) {
>>>>> + return Status;
>>>>> + }
>>>>> +
>>>>> + if ((Address >= PCI_SEG0_MMIO32_MIN) &&
>>>>> + (Address <= PCI_SEG0_MMIO32_MAX)) {
>>>>> + Address += PCI_SEG0_MMIO_MEMBASE; } else if ((Address >=
>>>>> + PCI_SEG1_MMIO32_MIN) &&
>>>>> + (Address <= PCI_SEG1_MMIO32_MAX)) {
>>>>> + Address += PCI_SEG1_MMIO_MEMBASE; } else if ((Address >=
>>>>> + PCI_SEG2_MMIO32_MIN) &&
>>>>> + (Address <= PCI_SEG2_MMIO32_MAX)) {
>>>>> + Address += PCI_SEG2_MMIO_MEMBASE; } else if ((Address >=
>>>>> + PCI_SEG3_MMIO32_MIN) &&
>>>>> + (Address <= PCI_SEG3_MMIO32_MAX)) {
>>>>> + Address += PCI_SEG3_MMIO_MEMBASE; } else {
>>>>> + ASSERT (FALSE);
>>>>> + return EFI_INVALID_PARAMETER;
>>>>> + }
>>>>> +
>>>>> + //
>>>>> + // Select loop based on the width of the transfer // InStride =
>>>>> + mInStride[Width]; OutStride = mOutStride[Width]; OperationWidth
>>>>> + = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); for (Uint8Buffer =
>>>>> + Buffer; Count > 0; Address += InStride, Uint8Buffer +=
>>>>OutStride, Count--) {
>>>>> + if (OperationWidth == EfiCpuIoWidthUint8) {
>>>>> + *Uint8Buffer = MmioRead8 ((UINTN)Address);
>>>>> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
>>>>> + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
>>>>> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
>>>>> + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
>>>>> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
>>>>> + *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
>>>>> + }
>>>>> + }
>>>>> + return EFI_SUCCESS;
>>>>> +}
>>>>> +
>>>>> +/**
>>>>> + Writes memory-mapped registers.
>>>>> +
>>>>> + The I/O operations are carried out exactly as requested. The
>>>>> + caller is responsible for satisfying any alignment and I/O width
>>>>> + restrictions that a PI System on a platform might require. For
>>>>> + example on some platforms, width requests of
>>>>> + EfiCpuIoWidthUint64 do not work.
>>>>> +
>>>>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>>>>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address
>>>>> + and Buffer are incremented for each of the Count operations that is
>>performed.
>>>>> +
>>>>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>>>>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>>>>> + Buffer is incremented for each of the Count operations that is
>>>>> + performed. The read or write operation is performed Count times
>>>>> + on the
>>>>same Address.
>>>>> +
>>>>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>>>>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>>>>> + Address is incremented for each of the Count operations that is
>>>>> + performed. The read or write operation is performed Count times
>>>>> + from the
>>>>first element of Buffer.
>>>>> +
>>>>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>>>>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>>>>> + @param[in] Address The base address of the I/O operation.
>>>>> + @param[in] Count The number of I/O operations to perform. The
>>number
>>>>of
>>>>> + bytes moved is Width size * Count, starting at Address.
>>>>> + @param[in] Buffer For read operations, the destination buffer to store
>>the
>>>>results.
>>>>> + For write operations, the source buffer from which to write
>>data.
>>>>> +
>>>>> + @retval EFI_SUCCESS The data was read from or written to the PI
>>>>system.
>>>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given
>>Width.
>>>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>>>Width,
>>>>> + and Count is not valid for this PI system.
>>>>> +
>>>>> +**/
>>>>> +STATIC
>>>>> +EFI_STATUS
>>>>> +EFIAPI
>>>>> +CpuMemoryServiceWrite (
>>>>> + IN EFI_CPU_IO2_PROTOCOL *This,
>>>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>>>> + IN UINT64 Address,
>>>>> + IN UINTN Count,
>>>>> + IN VOID *Buffer
>>>>> + )
>>>>> +{
>>>>> + EFI_STATUS Status;
>>>>> + UINT8 InStride;
>>>>> + UINT8 OutStride;
>>>>> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
>>>>> + UINT8 *Uint8Buffer;
>>>>> +
>>>>> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count,
>>>>> + Buffer); if (EFI_ERROR (Status)) {
>>>>> + return Status;
>>>>> + }
>>>>> +
>>>>> + if ((Address >= PCI_SEG0_MMIO32_MIN) &&
>>>>> + (Address <= PCI_SEG0_MMIO32_MAX)) {
>>>>> + Address += PCI_SEG0_MMIO_MEMBASE; } else if ((Address >=
>>>>> + PCI_SEG1_MMIO32_MIN) &&
>>>>> + (Address <= PCI_SEG1_MMIO32_MAX)) {
>>>>> + Address += PCI_SEG1_MMIO_MEMBASE; } else if ((Address >=
>>>>> + PCI_SEG2_MMIO32_MIN) &&
>>>>> + (Address <= PCI_SEG2_MMIO32_MAX)) {
>>>>> + Address += PCI_SEG2_MMIO_MEMBASE; } else if ((Address >=
>>>>> + PCI_SEG3_MMIO32_MIN) &&
>>>>> + (Address <= PCI_SEG3_MMIO32_MAX)) {
>>>>> + Address += PCI_SEG3_MMIO_MEMBASE; } else {
>>>>> + ASSERT (FALSE);
>>>>> + return EFI_INVALID_PARAMETER;
>>>>> + }
>>>>> +
>>>>> + //
>>>>> + // Select loop based on the width of the transfer // InStride =
>>>>> + mInStride[Width]; OutStride = mOutStride[Width]; OperationWidth
>>>>> + = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); for (Uint8Buffer =
>>>>> + Buffer; Count > 0; Address += InStride, Uint8Buffer +=
>>>>OutStride, Count--) {
>>>>> + if (OperationWidth == EfiCpuIoWidthUint8) {
>>>>> + MmioWrite8 ((UINTN)Address, *Uint8Buffer);
>>>>> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
>>>>> + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
>>>>> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
>>>>> + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
>>>>> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
>>>>> + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
>>>>> + }
>>>>> + }
>>>>> + return EFI_SUCCESS;
>>>>> +}
>>>>> +
>>>>> +/**
>>>>> + Reads I/O registers.
>>>>> +
>>>>> + The I/O operations are carried out exactly as requested. The
>>>>> + caller is responsible for satisfying any alignment and I/O width
>>>>> + restrictions that a PI System on a platform might require. For
>>>>> + example on some platforms, width requests of
>>>>> + EfiCpuIoWidthUint64 do not work.
>>>>> +
>>>>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>>>>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address
>>>>> + and Buffer are incremented for each of the Count operations that is
>>performed.
>>>>> +
>>>>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>>>>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>>>>> + Buffer is incremented for each of the Count operations that is
>>>>> + performed. The read or write operation is performed Count times
>>>>> + on the
>>>>same Address.
>>>>> +
>>>>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>>>>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>>>>> + Address is incremented for each of the Count operations that is
>>>>> + performed. The read or write operation is performed Count times
>>>>> + from the
>>>>first element of Buffer.
>>>>> +
>>>>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>>>>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>>>>> + @param[in] Address The base address of the I/O operation.
>>>>> + @param[in] Count The number of I/O operations to perform. The
>>number
>>>>of
>>>>> + bytes moved is Width size * Count, starting at Address.
>>>>> + @param[out] Buffer For read operations, the destination buffer to store
>>the
>>>>results.
>>>>> + For write operations, the source buffer from which to write
>>data.
>>>>> +
>>>>> + @retval EFI_SUCCESS The data was read from or written to the PI
>>>>system.
>>>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given
>>Width.
>>>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>>>Width,
>>>>> + and Count is not valid for this PI system.
>>>>> +
>>>>> +**/
>>>>> +STATIC
>>>>> +EFI_STATUS
>>>>> +EFIAPI
>>>>> +CpuIoServiceRead (
>>>>> + IN EFI_CPU_IO2_PROTOCOL *This,
>>>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>>>> + IN UINT64 Address,
>>>>> + IN UINTN Count,
>>>>> + OUT VOID *Buffer
>>>>> + )
>>>>> +{
>>>>> + return EFI_SUCCESS;
>>>>> +}
>>>>> +
>>>>> +/**
>>>>> + Write I/O registers.
>>>>> +
>>>>> + The I/O operations are carried out exactly as requested. The
>>>>> + caller is responsible for satisfying any alignment and I/O width
>>>>> + restrictions that a PI System on a platform might require. For
>>>>> + example on some platforms, width requests of
>>>>> + EfiCpuIoWidthUint64 do not work.
>>>>> +
>>>>> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16,
>>>>> + EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address
>>>>> + and Buffer are incremented for each of the Count operations that is
>>performed.
>>>>> +
>>>>> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
>>>>> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only
>>>>> + Buffer is incremented for each of the Count operations that is
>>>>> + performed. The read or write operation is performed Count times
>>>>> + on the
>>>>same Address.
>>>>> +
>>>>> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
>>>>> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only
>>>>> + Address is incremented for each of the Count operations that is
>>>>> + performed. The read or write operation is performed Count times
>>>>> + from the
>>>>first element of Buffer.
>>>>> +
>>>>> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
>>>>> + @param[in] Width Signifies the width of the I/O or Memory operation.
>>>>> + @param[in] Address The base address of the I/O operation.
>>>>> + @param[in] Count The number of I/O operations to perform. The
>>number
>>>>of
>>>>> + bytes moved is Width size * Count, starting at Address.
>>>>> + @param[in] Buffer For read operations, the destination buffer to store
>>the
>>>>results.
>>>>> + For write operations, the source buffer from which to write
>>data.
>>>>> +
>>>>> + @retval EFI_SUCCESS The data was read from or written to the PI
>>>>system.
>>>>> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
>>>>> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
>>>>> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given
>>Width.
>>>>> + @retval EFI_UNSUPPORTED The address range specified by Address,
>>>>Width,
>>>>> + and Count is not valid for this PI system.
>>>>> +
>>>>> +**/
>>>>> +STATIC
>>>>> +EFI_STATUS
>>>>> +EFIAPI
>>>>> +CpuIoServiceWrite (
>>>>> + IN EFI_CPU_IO2_PROTOCOL *This,
>>>>> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>>>>> + IN UINT64 Address,
>>>>> + IN UINTN Count,
>>>>> + IN VOID *Buffer
>>>>> + )
>>>>> +{
>>>>> + return EFI_SUCCESS;
>>>>> +}
>>>>> +
>>>>> +//
>>>>> +// CPU I/O 2 Protocol instance
>>>>> +//
>>>>> +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
>>>>> + {
>>>>> + CpuMemoryServiceRead,
>>>>> + CpuMemoryServiceWrite
>>>>> + },
>>>>> + {
>>>>> + CpuIoServiceRead,
>>>>> + CpuIoServiceWrite
>>>>> + }
>>>>> +};
>>>>> +
>>>>> +
>>>>> +/**
>>>>> + The user Entry Point for module CpuIo2Dxe. The user code starts
>>>>> +with this
>>>>function.
>>>>> +
>>>>> + @param[in] ImageHandle The firmware allocated handle for the EFI
>>image.
>>>>> + @param[in] SystemTable A pointer to the EFI System Table.
>>>>> +
>>>>> + @retval EFI_SUCCESS The entry point is executed successfully.
>>>>> + @retval other Some error occurs when executing this entry point.
>>>>> +
>>>>> +**/
>>>>> +EFI_STATUS
>>>>> +EFIAPI
>>>>> +PciCpuIo2Initialize (
>>>>> + IN EFI_HANDLE ImageHandle,
>>>>> + IN EFI_SYSTEM_TABLE *SystemTable
>>>>> + )
>>>>> +{
>>>>> + EFI_STATUS Status;
>>>>> +
>>>>> + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL,
>>>>> + &gEfiCpuIo2ProtocolGuid); Status = gBS->InstallMultipleProtocolInterfaces
>>(
>>>>> + &mHandle,
>>>>> + &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
>>>>> + NULL
>>>>> + );
>>>>> + ASSERT_EFI_ERROR (Status);
>>>>> +
>>>>> + return Status;
>>>>> +}
>>>>> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>>>>> b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>>>>> new file mode 100644
>>>>> index 0000000..25a1db1
>>>>> --- /dev/null
>>>>> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>>>>> @@ -0,0 +1,48 @@
>>>>> +## @file
>>>>> +# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
>>>>> +#
>>>>> +# Copyright 2018 NXP
>>>>> +#
>>>>> +# This program and the accompanying materials # are licensed and
>>>>> +made available under the terms and conditions of the BSD License #
>>>>> +which accompanies this distribution. The full text of the license
>>>>> +may be found at #
>>>>> +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fo
>>>>> +pe
>>>>> +nsource.org%2Flicenses%2Fbsd-
>>>>license.php&data=02%7C01%7Cvabhav.sharma
>>>>>
>>>>+%40nxp.com%7C4507c0726b244ad6476d08d5a69a64ee%7C686ea1d3bc2b4c
>>6f
>>>>a92cd
>>>>>
>>>>+99c5c301635%7C0%7C0%7C636598104414046440&sdata=IFSU0%2FeTdWrw
>>gg
>>>>0f0Lq2
>>>>> +qSVGgogG68tYZevrRmC%2BkV8%3D&reserved=0
>>>>> +#
>>>>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>>>> +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
>>EITHER
>>>>EXPRESS OR IMPLIED.
>>>>> +#
>>>>> +##
>>>>> +
>>>>> +[Defines]
>>>>> + INF_VERSION = 0x0001001A
>>>>> + BASE_NAME = PciCpuIo2Dxe
>>>>> + FILE_GUID = 7bff18d7-9aae-434b-9c06-f10a7e157eac
>>>>> + MODULE_TYPE = DXE_DRIVER
>>>>> + VERSION_STRING = 1.0
>>>>> + ENTRY_POINT = PciCpuIo2Initialize
>>>>> +
>>>>> +[Sources]
>>>>> + PciCpuIo2Dxe.c
>>>>> +
>>>>> +[Packages]
>>>>> + MdePkg/MdePkg.dec
>>>>> + Silicon/NXP/NxpQoriqLs.dec
>>>>> +
>>>>> +[LibraryClasses]
>>>>> + BaseLib
>>>>> + DebugLib
>>>>> + IoLib
>>>>> + UefiBootServicesTableLib
>>>>> + UefiDriverEntryPoint
>>>>> +
>>>>> +[Pcd]
>>>>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
>>>>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
>>>>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
>>>>> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
>>>>> +
>>>>> +[Protocols]
>>>>> + gEfiCpuIo2ProtocolGuid ## PRODUCES
>>>>> +
>>>>> +[Depex]
>>>>> + TRUE
>>>>> --
>>>>> 1.9.1
>>>>>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 22/39] Platform/NXP: LS1046 RDB Board FPGA library
2018-04-19 14:44 ` Leif Lindholm
@ 2018-06-04 4:10 ` Meenakshi Aggarwal
2018-06-04 9:25 ` Leif Lindholm
0 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-06-04 4:10 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi, Vabhav Sharma
Hi Leif,
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Thursday, April 19, 2018 8:14 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
> <vabhav.sharma@nxp.com>
> Subject: Re: [PATCH edk2-platforms 22/39] Platform/NXP: LS1046 RDB Board
> FPGA library
>
> On Fri, Feb 16, 2018 at 02:20:18PM +0530, Meenakshi wrote:
> > From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> >
> > Library to provide functions for accessing FPGA on LS1046ARDB board.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
>
> I compare this one to LS1043aRdbPkg/Library/FpgaLib, and the differences in
> the .c file are
> --- Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c 2018-04-18
> 15:13:08.507949763 +0100
> +++ Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c 2018-04-18
> +++ 15:13:08.531949605 +0100
> @@ -1,5 +1,5 @@
> /** @FpgaLib.c
> - Fpga Library for LS1043A-RDB board, containing functions to
> + Fpga Library for LS1046A-RDB board, containing functions to
> program and read the Fpga registers.
>
> FPGA is connected to IFC Controller and so MMIO APIs are used @@ -137,6
> +137,8 @@
> Sd1RefClkSel = FPGA_READ(Sd1RefClkSel);
> DEBUG((DEBUG_INFO, "SD1_CLK1 = %a, SD1_CLK2 = %a\n",
> Sd1RefClkSel ? SERDES_FREQ2 : SERDES_FREQ1, SERDES_FREQ1));
> + DEBUG((DEBUG_INFO, "SD2_CLK1 = %a, SD2_CLK2 = %a\n",
> + SERDES_FREQ1, SERDES_FREQ1));
>
> return;
> }
>
> Could these two libraries be merged into a single LS104xx variant?
>
> The LS2088a one seems to have substantial differences, so that makes sense to
> keep separate.
>
We were planning to keep this library common for both LS1046 and LS1043,
But as this is board specific library, and in case, same soc be used on any other board,
then there will be changes in common library which might not be significant for other.
Also, FPGA_REG_SET structure is different for both, luckily here the new struct members
are added in the end of structure, but we cannot be sure about same in future boards.
So we decided to keep board specific stuff separate.
> No other comments on this patch.
>
> /
> Leif
>
> > ---
> > .../NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h | 97 ++++++++++++++
> > .../NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c | 144
> +++++++++++++++++++++
> > .../NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf | 32 +++++
> > 3 files changed, 273 insertions(+)
> > create mode 100644
> > Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
> > create mode 100644
> > Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c
> > create mode 100644
> > Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
> >
> > diff --git a/Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
> > b/Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
> > new file mode 100644
> > index 0000000..c8f7411
> > --- /dev/null
> > +++ b/Platform/NXP/LS1046aRdbPkg/Include/Library/FpgaLib.h
> > @@ -0,0 +1,97 @@
> > +/** FpgaLib.h
> > +* Header defining the LS1046a Fpga specific constants (Base
> > +addresses, sizes, flags)
> > +*
> > +* Copyright 2017 NXP
> > +*
> > +* This program and the accompanying materials
> > +* are licensed and made available under the terms and conditions of
> > +the BSD License
> > +* which accompanies this distribution. The full text of the license
> > +may be found at
> > +*
> > +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> > +nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.agg
> >
> +arwal%40nxp.com%7C5d08c304527946a5bf8908d5a6040dc0%7C686ea1d3bc
> 2b4c6f
> >
> +a92cd99c5c301635%7C0%7C0%7C636597458708526882&sdata=%2FFRG6Itp%
> 2B23zi
> > +FZzr8QqfiGX7IImR8L6QjjTL2R%2Fgpw%3D&reserved=0
> > +*
> > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > +BASIS,
> > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +*
> > +**/
> > +
> > +#ifndef __LS1046A_FPGA_H__
> > +#define __LS1046A_FPGA_H__
> > +
> > +/**
> > + FPGA register set of LS1046ARDB board-specific.
> > + **/
> > +typedef struct {
> > + UINT8 FpgaVersionMajor; // 0x0 - FPGA Major Revision Register
> > + UINT8 FpgaVersionMinor; // 0x1 - FPGA Minor Revision Register
> > + UINT8 PcbaVersion; // 0x2 - PCBA Revision Register
> > + UINT8 SystemReset; // 0x3 - system reset register
> > + UINT8 SoftMuxOn; // 0x4 - Switch Control Enable Register
> > + UINT8 RcwSource1; // 0x5 - Reset config word 1
> > + UINT8 RcwSource2; // 0x6 - Reset config word 1
> > + UINT8 Vbank; // 0x7 - Flash bank selection Control
> > + UINT8 SysclkSelect; // 0x8 - System clock selection Control
> > + UINT8 UartSel; // 0x9 - Uart selection Control
> > + UINT8 Sd1RefClkSel; // 0xA - Serdes1 reference clock selection Control
> > + UINT8 TdmClkMuxSel; // 0xB - TDM Clock Mux selection Control
> > + UINT8 SdhcSpiCsSel; // 0xC - SDHC/SPI Chip select selection Control
> > + UINT8 StatusLed; // 0xD - Status Led
> > + UINT8 GlobalReset; // 0xE - Global reset
> > + UINT8 SdEmmc; // 0xF - SD or EMMC Interface Control Regsiter
> > + UINT8 VddEn; // 0x10 - VDD Voltage Control Enable Register
> > + UINT8 VddSel; // 0x11 - VDD Voltage Control Register
> > +} FPGA_REG_SET;
> > +
> > +/**
> > + Function to read FPGA register.
> > +**/
> > +UINT8
> > +FpgaRead (
> > + UINTN Reg
> > + );
> > +
> > +/**
> > + Function to write FPGA register.
> > +**/
> > +VOID
> > +FpgaWrite (
> > + UINTN Reg,
> > + UINT8 Value
> > + );
> > +
> > +/**
> > + Function to read FPGA revision.
> > +**/
> > +VOID
> > +FpgaRevBit (
> > + UINT8 *Value
> > + );
> > +
> > +/**
> > + Function to initialize FPGA timings.
> > +**/
> > +VOID
> > +FpgaInit (
> > + VOID
> > + );
> > +
> > +/**
> > + Function to print board personality.
> > +**/
> > +VOID
> > +PrintBoardPersonality (
> > + VOID
> > + );
> > +
> > +#define FPGA_BASE_PHYS 0x7fb00000
> > +
> > +#define SRC_VBANK 0x25
> > +#define SRC_NAND 0x106
> > +#define SRC_QSPI 0x44
> > +#define SRC_SD 0x40
> > +
> > +#define SERDES_FREQ1 "100.00 MHz"
> > +#define SERDES_FREQ2 "156.25 MHz"
> > +
> > +#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg))
> > +#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET,
> > +Reg), Value)
> > +
> > +#endif
> > diff --git a/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c
> > b/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c
> > new file mode 100644
> > index 0000000..90cc1ea
> > --- /dev/null
> > +++ b/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c
> > @@ -0,0 +1,144 @@
> > +/** @FpgaLib.c
> > + Fpga Library for LS1046A-RDB board, containing functions to
> > + program and read the Fpga registers.
> > +
> > + FPGA is connected to IFC Controller and so MMIO APIs are used to
> > + read/write FPGA registers
> > +
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials are licensed and made
> > + available under the terms and conditions of the BSD License which
> > + accompanies this distribution. The full text of the license may be
> > + found at
> > +
> > + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop
> > + ensource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.a
> > +
> ggarwal%40nxp.com%7C5d08c304527946a5bf8908d5a6040dc0%7C686ea1d3b
> c2b4
> > +
> c6fa92cd99c5c301635%7C0%7C0%7C636597458708526882&sdata=%2FFRG6It
> p%2B
> > + 23ziFZzr8QqfiGX7IImR8L6QjjTL2R%2Fgpw%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#include <Base.h>
> > +#include <Library/BaseLib.h>
> > +#include <Library/DebugLib.h>
> > +#include <Library/FpgaLib.h>
> > +#include <Library/IoLib.h>
> > +
> > +/**
> > + Function to read FPGA register.
> > +
> > + @param Reg Register offset of FPGA to read.
> > +
> > +**/
> > +UINT8
> > +FpgaRead (
> > + IN UINTN Reg
> > + )
> > +{
> > + VOID *Base;
> > +
> > + Base = (VOID *)FPGA_BASE_PHYS;
> > +
> > + return MmioRead8 ((UINTN)(Base + Reg)); }
> > +
> > +/**
> > + Function to write FPGA register.
> > +
> > + @param Reg Register offset of FPGA to write.
> > + @param Value Value to be written.
> > +
> > +**/
> > +VOID
> > +FpgaWrite (
> > + IN UINTN Reg,
> > + IN UINT8 Value
> > + )
> > +{
> > + VOID *Base;
> > +
> > + Base = (VOID *)FPGA_BASE_PHYS;
> > +
> > + MmioWrite8 ((UINTN)(Base + Reg), Value); }
> > +
> > +/**
> > + Function to reverse the number.
> > +
> > + @param *Value pointer to number to reverse.
> > +
> > + @retval *Value reversed value.
> > +
> > +**/
> > +VOID
> > +FpgaRevBit (
> > + OUT UINT8 *Value
> > + )
> > +{
> > + UINT8 Rev;
> > + UINT8 Val;
> > + UINTN Index;
> > +
> > + Val = *Value;
> > + Rev = Val & 1;
> > + for (Index = 1; Index <= 7; Index++) {
> > + Val >>= 1;
> > + Rev <<= 1;
> > + Rev |= Val & 1;
> > + }
> > +
> > + *Value = Rev;
> > +}
> > +
> > +/**
> > + Function to print board personality.
> > +
> > +**/
> > +VOID
> > +PrintBoardPersonality (
> > + VOID
> > + )
> > +{
> > + UINT8 RcwSrc1;
> > + UINT8 RcwSrc2;
> > + UINT32 RcwSrc;
> > + UINT32 Sd1RefClkSel;
> > +
> > + RcwSrc1 = FPGA_READ(RcwSource1);
> > + RcwSrc2 = FPGA_READ(RcwSource2);
> > + FpgaRevBit (&RcwSrc1);
> > + RcwSrc = RcwSrc1;
> > + RcwSrc = (RcwSrc << 1) | RcwSrc2;
> > +
> > + switch (RcwSrc) {
> > + case SRC_VBANK:
> > + DEBUG ((DEBUG_INFO, "vBank: %d\n", FPGA_READ(Vbank)));
> > + break;
> > + case SRC_NAND:
> > + DEBUG ((DEBUG_INFO, "NAND\n"));
> > + break;
> > + case SRC_QSPI:
> > + DEBUG ((DEBUG_INFO, "QSPI vBank %d\n", FPGA_READ(Vbank)));
> > + break;
> > + case SRC_SD:
> > + DEBUG ((DEBUG_INFO, "SD\n"));
> > + break;
> > + default:
> > + DEBUG ((DEBUG_INFO, "Invalid setting of SW5\n"));
> > + break;
> > + }
> > +
> > + DEBUG ((DEBUG_INFO, "FPGA: V%x.%x\nPCBA: V%x.0\n",
> > + FPGA_READ(FpgaVersionMajor),
> > + FPGA_READ(FpgaVersionMinor),
> > + FPGA_READ(PcbaVersion)));
> > +
> > + DEBUG ((DEBUG_INFO, "SERDES Reference Clocks:\n"));
> > +
> > + Sd1RefClkSel = FPGA_READ(Sd1RefClkSel); DEBUG((DEBUG_INFO,
> > + "SD1_CLK1 = %a, SD1_CLK2 = %a\n",
> > + Sd1RefClkSel ? SERDES_FREQ2 : SERDES_FREQ1,
> > + SERDES_FREQ1)); DEBUG((DEBUG_INFO, "SD2_CLK1 = %a, SD2_CLK2 =
> %a\n",
> > + SERDES_FREQ1, SERDES_FREQ1));
> > +
> > + return;
> > +}
> > diff --git a/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
> > b/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
> > new file mode 100644
> > index 0000000..afc41e3
> > --- /dev/null
> > +++ b/Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.inf
> > @@ -0,0 +1,32 @@
> > +# @FpgaLib.inf
> > +#
> > +# Copyright 2017 NXP
> > +#
> > +# This program and the accompanying materials # are licensed and
> > +made available under the terms and conditions of the BSD License #
> > +which accompanies this distribution. The full text of the license
> > +may be found at #
> > +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> > +nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.agg
> >
> +arwal%40nxp.com%7C5d08c304527946a5bf8908d5a6040dc0%7C686ea1d3bc
> 2b4c6f
> >
> +a92cd99c5c301635%7C0%7C0%7C636597458708526882&sdata=%2FFRG6Itp%
> 2B23zi
> > +FZzr8QqfiGX7IImR8L6QjjTL2R%2Fgpw%3D&reserved=0
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> > +#
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001000A
> > + BASE_NAME = FpgaLib
> > + FILE_GUID = 6e06ebbf-3a1d-47be-b4f6-1d82f2a9ac73
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = FpgaLib
> > +
> > +[Sources.common]
> > + FpgaLib.c
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > + Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
> > + Silicon/NXP/NxpQoriqLs.dec
> > +
> > +[LibraryClasses]
> > + BaseLib
> > + IoLib
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 22/39] Platform/NXP: LS1046 RDB Board FPGA library
2018-06-04 4:10 ` Meenakshi Aggarwal
@ 2018-06-04 9:25 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-06-04 9:25 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, Udit Kumar,
Varun Sethi, Vabhav Sharma
On Mon, Jun 04, 2018 at 04:10:16AM +0000, Meenakshi Aggarwal wrote:
> Hi Leif,
>
> > -----Original Message-----
> > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > Sent: Thursday, April 19, 2018 8:14 PM
> > To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> > Cc: ard.biesheuvel@linaro.org; edk2-devel@lists.01.org; Udit Kumar
> > <udit.kumar@nxp.com>; Varun Sethi <V.Sethi@nxp.com>; Vabhav Sharma
> > <vabhav.sharma@nxp.com>
> > Subject: Re: [PATCH edk2-platforms 22/39] Platform/NXP: LS1046 RDB Board
> > FPGA library
> >
> > On Fri, Feb 16, 2018 at 02:20:18PM +0530, Meenakshi wrote:
> > > From: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> > >
> > > Library to provide functions for accessing FPGA on LS1046ARDB board.
> > >
> > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> > > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> >
> > I compare this one to LS1043aRdbPkg/Library/FpgaLib, and the differences in
> > the .c file are
> > --- Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.c 2018-04-18
> > 15:13:08.507949763 +0100
> > +++ Platform/NXP/LS1046aRdbPkg/Library/FpgaLib/FpgaLib.c 2018-04-18
> > +++ 15:13:08.531949605 +0100
> > @@ -1,5 +1,5 @@
> > /** @FpgaLib.c
> > - Fpga Library for LS1043A-RDB board, containing functions to
> > + Fpga Library for LS1046A-RDB board, containing functions to
> > program and read the Fpga registers.
> >
> > FPGA is connected to IFC Controller and so MMIO APIs are used @@ -137,6
> > +137,8 @@
> > Sd1RefClkSel = FPGA_READ(Sd1RefClkSel);
> > DEBUG((DEBUG_INFO, "SD1_CLK1 = %a, SD1_CLK2 = %a\n",
> > Sd1RefClkSel ? SERDES_FREQ2 : SERDES_FREQ1, SERDES_FREQ1));
> > + DEBUG((DEBUG_INFO, "SD2_CLK1 = %a, SD2_CLK2 = %a\n",
> > + SERDES_FREQ1, SERDES_FREQ1));
> >
> > return;
> > }
> >
> > Could these two libraries be merged into a single LS104xx variant?
> >
> > The LS2088a one seems to have substantial differences, so that makes sense to
> > keep separate.
>
> We were planning to keep this library common for both LS1046 and
> LS1043,
Excellent. thanks.
> But as this is board specific library, and in case, same soc be used on any other board,
> then there will be changes in common library which might not be significant for other.
>
> Also, FPGA_REG_SET structure is different for both, luckily here the new struct members
> are added in the end of structure, but we cannot be sure about same in future boards.
>
> So we decided to keep board specific stuff separate.
Mainly what I'm after is reducing duplication of code and definitions.
If that can be resolved by board-specific include files including
common headers or a "common bits" library pulled in by board-specific
libraries, that sounds good to me.
Thanks,
Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 00/41] NXP : Add support of LS1043, LS1046 and LS2088 SoCs
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
` (40 preceding siblings ...)
2018-04-20 16:15 ` Leif Lindholm
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 01/41] Silicon/NXP: Add Library to return Mmio APIs pointer Meenakshi Aggarwal
` (42 more replies)
41 siblings, 43 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
We have combined all review comments recieved till now.
Following patches will add support of NXP SoCs[LS1043, LS1046 and LS2088] in edk2-platforms.
Our directory structure will be:
edk2-platforms
|-- Platform
| |-- NXP
| | |-- FVRules.fdf.inc
| | |-- LS1043aRdbPkg
| | | |-- Drivers
| | | | `-- PlatformDxe
| | | | |-- PlatformDxe.c
| | | | `-- PlatformDxe.inf
| | | |-- Include
| | | | `-- IfcBoardSpecific.h
| | | |-- Library
| | | | |-- BoardLib
| | | | | |-- BoardLib.c
| | | | | `-- BoardLib.inf
| | | | `-- PlatformLib
| | | | |-- ArmPlatformLib.c
| | | | |-- ArmPlatformLib.inf
| | | | |-- NxpQoriqLsHelper.S
| | | | `-- NxpQoriqLsMem.c
| | | |-- LS1043aRdbPkg.dec
| | | |-- LS1043aRdbPkg.dsc
| | | |-- LS1043aRdbPkg.fdf
| | | `-- VarStore.fdf.inc
| | |-- LS1046aRdbPkg
| | | |-- Drivers
| | | | `-- PlatformDxe
| | | | |-- PlatformDxe.c
| | | | `-- PlatformDxe.inf
| | | |-- Include
| | | | `-- IfcBoardSpecific.h
| | | |-- Library
| | | | |-- BoardLib
| | | | | |-- BoardLib.c
| | | | | `-- BoardLib.inf
| | | | `-- PlatformLib
| | | | |-- ArmPlatformLib.c
| | | | |-- ArmPlatformLib.inf
| | | | |-- NxpQoriqLsHelper.S
| | | | `-- NxpQoriqLsMem.c
| | | |-- LS1046aRdbPkg.dec
| | | |-- LS1046aRdbPkg.dsc
| | | `-- LS1046aRdbPkg.fdf
| | |-- LS2088aRdbPkg
| | | |-- Drivers
| | | | `-- PlatformDxe
| | | | |-- PlatformDxe.c
| | | | `-- PlatformDxe.inf
| | | |-- Include
| | | | |-- IfcBoardSpecific.h
| | | | `-- Library
| | | | `-- FpgaLib.h
| | | |-- Library
| | | | |-- BoardLib
| | | | | |-- BoardLib.c
| | | | | `-- BoardLib.inf
| | | | |-- FpgaLib
| | | | | |-- FpgaLib.c
| | | | | `-- FpgaLib.inf
| | | | `-- PlatformLib
| | | | |-- ArmPlatformLib.c
| | | | |-- ArmPlatformLib.inf
| | | | |-- NxpQoriqLsHelper.S
| | | | `-- NxpQoriqLsMem.c
| | | |-- LS2088aRdbPkg.dec
| | | |-- LS2088aRdbPkg.dsc
| | | |-- LS2088aRdbPkg.fdf
| | | `-- VarStore.fdf.inc
| | |-- NxpQoriqLs.dsc.inc
| | `-- Readme.md
|-- Silicon
| |-- Maxim
| | `-- Library
| | |-- Ds1307RtcLib
| | | |-- Ds1307Rtc.h
| | | |-- Ds1307RtcLib.c
| | | |-- Ds1307RtcLib.dec
| | | `-- Ds1307RtcLib.inf
| | `-- Ds3232RtcLib
| | |-- Ds3232Rtc.h
| | |-- Ds3232RtcLib.c
| | |-- Ds3232RtcLib.dec
| | `-- Ds3232RtcLib.inf
| |-- NXP
| | |-- Drivers
| | | |-- I2cDxe
| | | | |-- ComponentName.c
| | | | |-- DriverBinding.c
| | | | |-- I2cDxe.c
| | | | |-- I2cDxe.h
| | | | `-- I2cDxe.inf
| | | |-- NorFlashDxe
| | | | |-- NorFlashBlockIoDxe.c
| | | | |-- NorFlashDxe.c
| | | | |-- NorFlashDxe.h
| | | | |-- NorFlashDxe.inf
| | | | `-- NorFlashFvbDxe.c
| | | |-- PciCpuIo2Dxe
| | | | |-- PciCpuIo2Dxe.c
| | | | `-- PciCpuIo2Dxe.inf
| | | |-- UsbHcdInitDxe
| | | | |-- UsbHcd.c
| | | | |-- UsbHcd.h
| | | | `-- UsbHcd.inf
| | | `-- WatchDog
| | | |-- WatchDog.c
| | | |-- WatchDogDxe.inf
| | | `-- WatchDog.h
| | |-- Include
| | | |-- Chassis2
| | | | |-- SerDes.h
| | | | `-- Soc.h
| | | |-- Chassis3
| | | | |-- SerDes.h
| | | | `-- Soc.h
| | | |-- Ifc.h
| | | |-- Library
| | | | |-- FpgaLib.h
| | | | |-- IfcLib.h
| | | | |-- IoAccessLib.h
| | | | `-- NorFlashLib.h
| | | |-- NorFlash.h
| | | `-- NxpPcie.h
| | |-- Library
| | | |-- DUartPortLib
| | | | |-- DUart.h
| | | | |-- DUartPortLib.c
| | | | `-- DUartPortLib.inf
| | | |-- FpgaLib
| | | | |-- FpgaLib.c
| | | | `-- FpgaLib.inf
| | | |-- IfcLib
| | | | |-- IfcLib.c
| | | | |-- IfcLib.h
| | | | `-- IfcLib.inf
| | | |-- IoAccessLib
| | | | |-- IoAccessLib.c
| | | | `-- IoAccessLib.inf
| | | |-- NorFlashLib
| | | | |-- CfiCommand.h
| | | | |-- CfiNorFlashLib.c
| | | | |-- CfiNorFlashLib.h
| | | | |-- NorFlashLib.c
| | | | `-- NorFlashLib.inf
| | | |-- Pcf2129RtcLib
| | | | |-- Pcf2129Rtc.h
| | | | |-- Pcf2129RtcLib.c
| | | | |-- Pcf2129RtcLib.dec
| | | | `-- Pcf2129RtcLib.inf
| | | |-- Pcf8563RealTimeClockLib
| | | | |-- Pcf8563RealTimeClockLib.c
| | | | |-- Pcf8563RealTimeClockLib.dec
| | | | `-- Pcf8563RealTimeClockLib.inf
| | | |-- PciHostBridgeLib
| | | | |-- PciHostBridgeLib.c
| | | | `-- PciHostBridgeLib.inf
| | | |-- PciSegmentLib
| | | | |-- PciSegmentLib.c
| | | | `-- PciSegmentLib.inf
| | | `-- SocLib
| | | |-- Chassis2
| | | | `-- Soc.c
| | | |-- Chassis3
| | | | `-- Soc.c
| | | |-- Chassis.c
| | | |-- Chassis.h
| | | |-- LS1043aSocLib.inf
| | | |-- LS1046aSocLib.inf
| | | |-- LS2088aSocLib.inf
| | | `-- SerDes.c
| | |-- LS1043A
| | | |-- Include
| | | | `-- SocSerDes.h
| | | |-- LS1043A.dec
| | | `-- LS1043A.dsc.inc
| | |-- LS1046A
| | | |-- Include
| | | | `-- SocSerDes.h
| | | |-- LS1046A.dec
| | | `-- LS1046A.dsc.inc
| | |-- LS2088A
| | | |-- Include
| | | | `-- SocSerDes.h
| | | |-- LS2088A.dec
| | | `-- LS2088A.dsc.inc
| | `-- NxpQoriqLs.dec
In Silicon/NXP, we are keeping our SoC specific information and all Drivers and Library which are used by SoCs.
Platform/NXP/ will host our board packages and build script.
Board specific libraries and header files will reside inside board package.
Looking forward for your kind support in upstreaming our boards in edk2-platforms.
Meenakshi Aggarwal (28):
Silicon/NXP: Add Library to return Mmio APIs pointer
Silicon/NXP : Add support for Watchdog driver
SocLib : Add support for initialization of peripherals
Silicon/NXP : Add support for DUART library
Silicon/NXP: Add support for I2c driver
Silicon/Maxim : Add support for DS1307 RTC library
Platform/NXP: Add support for ArmPlatformLib
Platform/NXP: Add Platform driver for LS1043 RDB board
Compilation : Add the fdf, dsc and dec files.
Readme : Add Readme.md file.
IFC : Add Header file for IFC controller
LS1043/BoardLib : Add support for LS1043 BoardLib.
Silicon/NXP : Add support of IfcLib
Silicon/NXP : Add support for FpgaLib.
LS1043 : Enable support of FpgaLib.
Silicon/NXP : Add support of NorFlashLib
Silicon/NXP : Add NOR driver.
LS1043 : Enable NOR driver for LS1043aRDB package.
Silicon/NXP:Add LS1046ARDB SoCLib Support
Platform/NXP: LS1046A RDB Board Library
Platform/NXP: Add Platform driver for LS1046 RDB board
Platform/NXP: Add Platform driver for LS2088 RDB board
Compilation : Add the fdf, dsc and dec files
LS2088 : Enable support of FpgaLib
LS2088ARDB: Enable NOR driver and Runtime Services
Compilation: Update the fdf, dsc and dec files.
DWC3 : Add DWC3 USB controller initialization driver.
LS2088 : Enable support of USB controller
Vabhav (8):
Silicon/NXP:Add support for PCF2129 Real Time Clock Library
Platform/NXP: Add ArmPlatformLib for LS1046A
Platform/NXP: Compilation for LS1046A RDB Board
Silicon/NXP: Implement PciSegmentLib to support multiple RCs
Silicon/NXP: Implement PciHostBridgeLib support
Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
Platform/NXP:PCIe enablement for LS1046A RDB
Platform/NXP:PCIe enablement for LS2088A RDB
Wasim Khan (5):
Silicon/NXP:SocLib support for initialization of peripherals
Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB
Silicon/Maxim: DS3232 RTC Library Support
Platform/NXP: LS2088A RDB Board Library
Platform/NXP: LS2088 RDB Board FPGA library
Platform/NXP/FVRules.fdf.inc | 99 +++
.../Drivers/PlatformDxe/PlatformDxe.c | 119 +++
.../Drivers/PlatformDxe/PlatformDxe.inf | 58 ++
.../NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h | 109 +++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 29 +
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 113 +++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 212 ++++++
.../NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c | 69 ++
.../LS1043aRdbPkg/Library/BoardLib/BoardLib.inf | 31 +
.../Library/PlatformLib/ArmPlatformLib.c | 105 +++
.../Library/PlatformLib/ArmPlatformLib.inf | 69 ++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 38 +
.../Library/PlatformLib/NxpQoriqLsMem.c | 158 ++++
Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 98 +++
.../Drivers/PlatformDxe/PlatformDxe.c | 119 +++
.../Drivers/PlatformDxe/PlatformDxe.inf | 58 ++
.../NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h | 83 +++
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec | 29 +
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 105 +++
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 205 ++++++
.../NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c | 61 ++
.../LS1046aRdbPkg/Library/BoardLib/BoardLib.inf | 31 +
.../Library/PlatformLib/ArmPlatformLib.c | 105 +++
.../Library/PlatformLib/ArmPlatformLib.inf | 68 ++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 35 +
.../Library/PlatformLib/NxpQoriqLsMem.c | 158 ++++
.../Drivers/PlatformDxe/PlatformDxe.c | 119 +++
.../Drivers/PlatformDxe/PlatformDxe.inf | 58 ++
.../NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h | 114 +++
.../NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h | 166 +++++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec | 29 +
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 130 ++++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 224 ++++++
.../NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c | 69 ++
.../LS2088aRdbPkg/Library/BoardLib/BoardLib.inf | 28 +
.../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c | 115 +++
.../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 +
.../Library/PlatformLib/ArmPlatformLib.c | 106 +++
.../Library/PlatformLib/ArmPlatformLib.inf | 79 ++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 35 +
.../Library/PlatformLib/NxpQoriqLsMem.c | 195 +++++
Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc | 99 +++
Platform/NXP/NxpQoriqLs.dsc.inc | 427 +++++++++++
Platform/NXP/Readme.md | 24 +
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h | 54 ++
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 378 ++++++++++
.../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec | 29 +
.../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf | 45 ++
Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h | 49 ++
Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c | 420 +++++++++++
.../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec | 34 +
.../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf | 50 ++
Silicon/NXP/Drivers/I2cDxe/ComponentName.c | 185 +++++
Silicon/NXP/Drivers/I2cDxe/DriverBinding.c | 241 ++++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 693 +++++++++++++++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 96 +++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 64 ++
.../NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c | 252 +++++++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c | 503 +++++++++++++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h | 146 ++++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf | 65 ++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c | 816 +++++++++++++++++++++
Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 633 ++++++++++++++++
Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 49 ++
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c | 218 ++++++
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h | 144 ++++
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf | 48 ++
Silicon/NXP/Drivers/WatchDog/WatchDog.c | 402 ++++++++++
Silicon/NXP/Drivers/WatchDog/WatchDog.h | 39 +
Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf | 47 ++
Silicon/NXP/Include/Chassis2/SerDes.h | 68 ++
Silicon/NXP/Include/Chassis2/Soc.h | 367 +++++++++
Silicon/NXP/Include/Chassis3/SerDes.h | 91 +++
Silicon/NXP/Include/Chassis3/Soc.h | 143 ++++
Silicon/NXP/Include/Ifc.h | 423 +++++++++++
Silicon/NXP/Include/Library/FpgaLib.h | 97 +++
Silicon/NXP/Include/Library/IfcLib.h | 26 +
Silicon/NXP/Include/Library/IoAccessLib.h | 332 +++++++++
Silicon/NXP/Include/Library/NorFlashLib.h | 77 ++
Silicon/NXP/Include/NorFlash.h | 44 ++
Silicon/NXP/Include/NxpPcie.h | 146 ++++
Silicon/NXP/LS1043A/Include/SocSerDes.h | 57 ++
Silicon/NXP/LS1043A/LS1043A.dec | 22 +
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 79 ++
Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 ++
Silicon/NXP/LS1046A/LS1046A.dec | 22 +
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 71 ++
Silicon/NXP/LS2088A/Include/SocSerDes.h | 67 ++
Silicon/NXP/LS2088A/LS2088A.dec | 22 +
Silicon/NXP/LS2088A/LS2088A.dsc.inc | 76 ++
Silicon/NXP/Library/DUartPortLib/DUart.h | 128 ++++
Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 370 ++++++++++
Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 41 ++
Silicon/NXP/Library/FpgaLib/FpgaLib.c | 145 ++++
Silicon/NXP/Library/FpgaLib/FpgaLib.inf | 34 +
Silicon/NXP/Library/IfcLib/IfcLib.c | 150 ++++
Silicon/NXP/Library/IfcLib/IfcLib.h | 190 +++++
Silicon/NXP/Library/IfcLib/IfcLib.inf | 38 +
Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 410 +++++++++++
Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf | 32 +
Silicon/NXP/Library/NorFlashLib/CfiCommand.h | 99 +++
Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c | 210 ++++++
Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h | 53 ++
Silicon/NXP/Library/NorFlashLib/NorFlashLib.c | 696 ++++++++++++++++++
Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf | 43 ++
Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h | 52 ++
Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c | 389 ++++++++++
.../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec | 29 +
.../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf | 47 ++
.../Library/PciHostBridgeLib/PciHostBridgeLib.c | 639 ++++++++++++++++
.../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 51 ++
Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 611 +++++++++++++++
.../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 41 ++
Silicon/NXP/Library/SocLib/Chassis.c | 411 +++++++++++
Silicon/NXP/Library/SocLib/Chassis.h | 162 ++++
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 220 ++++++
Silicon/NXP/Library/SocLib/Chassis3/Soc.c | 191 +++++
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 53 ++
Silicon/NXP/Library/SocLib/LS1046aSocLib.inf | 53 ++
Silicon/NXP/Library/SocLib/LS2088aSocLib.inf | 52 ++
Silicon/NXP/Library/SocLib/SerDes.c | 274 +++++++
Silicon/NXP/NxpQoriqLs.dec | 147 ++++
122 files changed, 18458 insertions(+)
create mode 100644 Platform/NXP/FVRules.fdf.inc
create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
create mode 100644 Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
create mode 100644 Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
create mode 100755 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
create mode 100644 Platform/NXP/NxpQoriqLs.dsc.inc
create mode 100644 Platform/NXP/Readme.md
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
create mode 100644 Silicon/NXP/Drivers/I2cDxe/ComponentName.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c
create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c
create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h
create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
create mode 100644 Silicon/NXP/Include/Chassis2/SerDes.h
create mode 100644 Silicon/NXP/Include/Chassis2/Soc.h
create mode 100644 Silicon/NXP/Include/Chassis3/SerDes.h
create mode 100644 Silicon/NXP/Include/Chassis3/Soc.h
create mode 100644 Silicon/NXP/Include/Ifc.h
create mode 100644 Silicon/NXP/Include/Library/FpgaLib.h
create mode 100644 Silicon/NXP/Include/Library/IfcLib.h
create mode 100644 Silicon/NXP/Include/Library/IoAccessLib.h
create mode 100644 Silicon/NXP/Include/Library/NorFlashLib.h
create mode 100644 Silicon/NXP/Include/NorFlash.h
create mode 100644 Silicon/NXP/Include/NxpPcie.h
create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc.inc
create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc.inc
create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h
create mode 100644 Silicon/NXP/LS2088A/LS2088A.dec
create mode 100644 Silicon/NXP/LS2088A/LS2088A.dsc.inc
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
create mode 100644 Silicon/NXP/Library/FpgaLib/FpgaLib.c
create mode 100644 Silicon/NXP/Library/FpgaLib/FpgaLib.inf
create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.c
create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.h
create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.inf
create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiCommand.h
create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
create mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
create mode 100644 Silicon/NXP/Library/SocLib/Chassis.h
create mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
create mode 100644 Silicon/NXP/Library/SocLib/Chassis3/Soc.c
create mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
create mode 100644 Silicon/NXP/Library/SocLib/LS1046aSocLib.inf
create mode 100644 Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
create mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
create mode 100644 Silicon/NXP/NxpQoriqLs.dec
--
1.9.1
^ permalink raw reply [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 01/41] Silicon/NXP: Add Library to return Mmio APIs pointer
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 19:17 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 02/41] Silicon/NXP : Add support for Watchdog driver Meenakshi Aggarwal
` (41 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
This library add supports to return pointer to
MMIO APIs on basis of Swap flag.
If Flag is True then MMION APIs returened in which data
swapped after reading from MMIO and before write using MMIO.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Include/Library/IoAccessLib.h | 332 +++++++++++++++++++
Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 410 ++++++++++++++++++++++++
Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf | 32 ++
3 files changed, 774 insertions(+)
create mode 100644 Silicon/NXP/Include/Library/IoAccessLib.h
create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
diff --git a/Silicon/NXP/Include/Library/IoAccessLib.h b/Silicon/NXP/Include/Library/IoAccessLib.h
new file mode 100644
index 0000000..f7372a5
--- /dev/null
+++ b/Silicon/NXP/Include/Library/IoAccessLib.h
@@ -0,0 +1,332 @@
+/** @file
+ *
+ * Copyright 2017 NXP
+ *
+ * This program and the accompanying materials
+ * are licensed and made available under the terms and conditions of the BSD License
+ * which accompanies this distribution. The full text of the license may be found at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ *
+ **/
+
+#ifndef __IO_ACCESS_LIB_H__
+#define __IO_ACCESS_LIB_H__
+
+#include <Base.h>
+
+///
+/// Structure to have pointer to R/W
+/// Mmio operations for 16 bits.
+///
+typedef struct _MMIO_OPERATIONS_16 {
+ UINT16 (*Read) (UINTN Address);
+ UINT16 (*Write) (UINTN Address, UINT16 Value);
+ UINT16 (*Or) (UINTN Address, UINT16 Or);
+ UINT16 (*And) (UINTN Address, UINT16 AND);
+ UINT16 (*AndThenOr) (UINTN Address, UINT16 And, UINT16 Or);
+} MMIO_OPERATIONS_16;
+
+///
+/// Structure to have pointer to R/W
+/// Mmio operations for 32 bits.
+///
+typedef struct _MMIO_OPERATIONS_32 {
+ UINT32 (*Read) (UINTN Address);
+ UINT32 (*Write) (UINTN Address, UINT32 Value);
+ UINT32 (*Or) (UINTN Address, UINT32 Or);
+ UINT32 (*And) (UINTN Address, UINT32 AND);
+ UINT32 (*AndThenOr) (UINTN Address, UINT32 And, UINT32 Or);
+} MMIO_OPERATIONS_32;
+
+///
+/// Structure to have pointer to R/W
+/// Mmio operations for 64 bits.
+///
+typedef struct _MMIO_OPERATIONS_64 {
+ UINT64 (*Read) (UINTN Address);
+ UINT64 (*Write) (UINTN Address, UINT64 Value);
+ UINT64 (*Or) (UINTN Address, UINT64 Or);
+ UINT64 (*And) (UINTN Address, UINT64 AND);
+ UINT64 (*AndThenOr) (UINTN Address, UINT64 And, UINT64 Or);
+} MMIO_OPERATIONS_64;
+
+/**
+ Function to return pointer to 16 bit Mmio operations.
+
+ @param Swap Flag to tell if Swap is needed or not
+ on Mmio Operations.
+
+ @return Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_16 *
+GetMmioOperations16 (
+ IN BOOLEAN Swap
+ );
+
+/**
+ Function to return pointer to 32 bit Mmio operations.
+
+ @param Swap Flag to tell if Swap is needed or not
+ on Mmio Operations.
+
+ @return Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_32 *
+GetMmioOperations32 (
+ IN BOOLEAN Swap
+ );
+
+/**
+ Function to return pointer to 64 bit Mmio operations.
+
+ @param Swap Flag to tell if Swap is needed or not
+ on Mmio Operations.
+
+ @return Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_64 *
+GetMmioOperations64 (
+ IN BOOLEAN Swap
+ );
+
+/**
+ MmioRead16 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+SwapMmioRead16 (
+ IN UINTN Address
+ );
+
+/**
+ MmioRead32 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+SwapMmioRead32 (
+ IN UINTN Address
+ );
+
+/**
+ MmioRead64 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+SwapMmioRead64 (
+ IN UINTN Address
+ );
+
+/**
+ MmioWrite16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ );
+
+/**
+ MmioWrite32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ MmioWrite64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ );
+
+/**
+ MmioAndThenOr16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ MmioAndThenOr32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ MmioAndThenOr64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioAndThenOr64 (
+ IN UINTN Address,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ );
+
+/**
+ MmioOr16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ );
+
+/**
+ MmioOr32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ );
+
+/**
+ MmioOr64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioOr64 (
+ IN UINTN Address,
+ IN UINT64 OrData
+ );
+
+/**
+ MmioAnd16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ );
+
+/**
+ MmioAnd32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ );
+
+/**
+ MmioAnd64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioAnd64 (
+ IN UINTN Address,
+ IN UINT64 AndData
+ );
+
+#endif /* __IO_ACCESS_LIB_H__ */
diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
new file mode 100644
index 0000000..0260777
--- /dev/null
+++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
@@ -0,0 +1,410 @@
+/** IoAccessLib.c
+
+ Provide MMIO APIs for BE modules.
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/IoLib.h>
+
+/**
+ MmioRead16 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+SwapMmioRead16 (
+ IN UINTN Address
+ )
+{
+ return SwapBytes16 (MmioRead16 (Address));
+}
+
+/**
+ MmioRead32 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+SwapMmioRead32 (
+ IN UINTN Address
+ )
+{
+ return SwapBytes32 (MmioRead32 (Address));
+}
+
+/**
+ MmioRead64 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+SwapMmioRead64 (
+ IN UINTN Address
+ )
+{
+ return SwapBytes64 (MmioRead64 (Address));
+}
+
+/**
+ MmioWrite16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ )
+{
+ return MmioWrite16 (Address, SwapBytes16 (Value));
+}
+
+/**
+ MmioWrite32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ return MmioWrite32 (Address, SwapBytes32 (Value));
+}
+
+/**
+ MmioWrite64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ )
+{
+ return MmioWrite64 (Address, SwapBytes64 (Value));
+}
+
+/**
+ MmioAndThenOr16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ AndData = SwapBytes16 (AndData);
+ OrData = SwapBytes16 (OrData);
+
+ return MmioAndThenOr16 (Address, AndData, OrData);
+}
+
+/**
+ MmioAndThenOr32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ AndData = SwapBytes32 (AndData);
+ OrData = SwapBytes32 (OrData);
+
+ return MmioAndThenOr32 (Address, AndData, OrData);
+}
+
+/**
+ MmioAndThenOr64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioAndThenOr64 (
+ IN UINTN Address,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ )
+{
+ AndData = SwapBytes64 (AndData);
+ OrData = SwapBytes64 (OrData);
+
+ return MmioAndThenOr64 (Address, AndData, OrData);
+}
+
+/**
+ MmioOr16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ )
+{
+ return MmioOr16 (Address, SwapBytes16 (OrData));
+}
+
+/**
+ MmioOr32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ )
+{
+ return MmioOr32 (Address, SwapBytes32 (OrData));
+}
+
+/**
+ MmioOr64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioOr64 (
+ IN UINTN Address,
+ IN UINT64 OrData
+ )
+{
+ return MmioOr64 (Address, SwapBytes64 (OrData));
+}
+
+/**
+ MmioAnd16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ )
+{
+ return MmioAnd16 (Address, SwapBytes16 (AndData));
+}
+
+/**
+ MmioAnd32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ )
+{
+ return MmioAnd32 (Address, SwapBytes32 (AndData));
+}
+
+/**
+ MmioAnd64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioAnd64 (
+ IN UINTN Address,
+ IN UINT64 AndData
+ )
+{
+ return MmioAnd64 (Address, SwapBytes64 (AndData));
+}
+
+STATIC MMIO_OPERATIONS_16 SwappingFunctions16 = {
+ SwapMmioRead16,
+ SwapMmioWrite16,
+ SwapMmioOr16,
+ SwapMmioAnd16,
+ SwapMmioAndThenOr16,
+};
+
+STATIC MMIO_OPERATIONS_16 NonSwappingFunctions16 = {
+ MmioRead16,
+ MmioWrite16,
+ MmioOr16,
+ MmioAnd16,
+ MmioAndThenOr16,
+};
+
+STATIC MMIO_OPERATIONS_32 SwappingFunctions32 = {
+ SwapMmioRead32,
+ SwapMmioWrite32,
+ SwapMmioOr32,
+ SwapMmioAnd32,
+ SwapMmioAndThenOr32,
+};
+
+STATIC MMIO_OPERATIONS_32 NonSwappingFunctions32 = {
+ MmioRead32,
+ MmioWrite32,
+ MmioOr32,
+ MmioAnd32,
+ MmioAndThenOr32,
+};
+
+STATIC MMIO_OPERATIONS_64 SwappingFunctions64 = {
+ SwapMmioRead64,
+ SwapMmioWrite64,
+ SwapMmioOr64,
+ SwapMmioAnd64,
+ SwapMmioAndThenOr64,
+};
+
+STATIC MMIO_OPERATIONS_64 NonSwappingFunctions64 = {
+ MmioRead64,
+ MmioWrite64,
+ MmioOr64,
+ MmioAnd64,
+ MmioAndThenOr64,
+};
+
+/**
+ Function to return pointer to 16 bit Mmio operations.
+
+ @param Swap Flag to tell if Swap is needed or not
+ on Mmio Operations.
+
+ @return Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_16 *
+GetMmioOperations16 (BOOLEAN Swap) {
+ if (Swap) {
+ return &SwappingFunctions16;
+ } else {
+ return &NonSwappingFunctions16;
+ }
+}
+
+/**
+ Function to return pointer to 32 bit Mmio operations.
+
+ @param Swap Flag to tell if Swap is needed or not
+ on Mmio Operations.
+
+ @return Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_32 *
+GetMmioOperations32 (BOOLEAN Swap) {
+ if (Swap) {
+ return &SwappingFunctions32;
+ } else {
+ return &NonSwappingFunctions32;
+ }
+}
+
+/**
+ Function to return pointer to 64 bit Mmio operations.
+
+ @param Swap Flag to tell if Swap is needed or not
+ on Mmio Operations.
+
+ @return Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_64 *
+GetMmioOperations64 (BOOLEAN Swap) {
+ if (Swap) {
+ return &SwappingFunctions64;
+ } else {
+ return &NonSwappingFunctions64;
+ }
+}
diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
new file mode 100644
index 0000000..e2e7606
--- /dev/null
+++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
@@ -0,0 +1,32 @@
+## @IoAccessLib.inf
+
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = IoAccessLib
+ FILE_GUID = 28d77333-77eb-4faf-8735-130e5eb3e343
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = IoAccessLib
+
+[Sources.common]
+ IoAccessLib.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ IoLib
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 02/41] Silicon/NXP : Add support for Watchdog driver
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 01/41] Silicon/NXP: Add Library to return Mmio APIs pointer Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-17 17:36 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 03/41] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
` (40 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Installs watchdog timer arch protocol
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Drivers/WatchDog/WatchDog.c | 402 +++++++++++++++++++++++++++
Silicon/NXP/Drivers/WatchDog/WatchDog.h | 39 +++
Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf | 47 ++++
3 files changed, 488 insertions(+)
create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c
create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h
create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.c b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
new file mode 100644
index 0000000..1b1a3b5
--- /dev/null
+++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
@@ -0,0 +1,402 @@
+/** WatchDog.c
+*
+* Based on Watchdog driver implemenation available in
+* ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/WatchdogTimer.h>
+
+#include "WatchDog.h"
+
+STATIC EFI_EVENT EfiExitBootServicesEvent;
+STATIC EFI_EVENT WdogFeedEvent;
+STATIC MMIO_OPERATIONS_16 *mMmioOps;
+
+
+STATIC
+VOID
+WdogPing (
+ VOID
+ )
+{
+ //
+ // To reload a timeout value to the counter the proper service sequence begins by
+ // writing 0x_5555 followed by 0x_AAAA to the Watchdog Service Register (WDOG_WSR).
+ // This service sequence will reload the counter with the timeout value WT[7:0] of
+ // Watchdog Control Register (WDOG_WCR).
+ //
+
+ mMmioOps->Write (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WSR_OFFSET,
+ WDOG_SERVICE_SEQ1);
+ mMmioOps->Write (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WSR_OFFSET,
+ WDOG_SERVICE_SEQ2);
+}
+
+/**
+ Stop the Wdog watchdog timer from counting down.
+**/
+STATIC
+VOID
+WdogStop (
+ VOID
+ )
+{
+ // Watchdog cannot be disabled by software once started.
+ // At best, we can keep reload counter with maximum value
+
+ mMmioOps->AndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
+ (UINT16)(~WDOG_WCR_WT),
+ (WD_COUNT (WT_MAX_TIME) & WD_COUNT_MASK));
+ WdogPing ();
+}
+
+/**
+ Starts the Wdog counting down by feeding Service register with
+ desired pattern.
+ The count down will start from the value stored in the Load register,
+ not from the value where it was previously stopped.
+**/
+STATIC
+VOID
+WdogStart (
+ VOID
+ )
+{
+ //Reload the timeout value
+ WdogPing ();
+}
+
+/**
+ On exiting boot services we must make sure the Wdog Watchdog Timer
+ is stopped.
+**/
+STATIC
+VOID
+EFIAPI
+ExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ WdogStop ();
+}
+
+/**
+ This function registers the handler NotifyFunction so it is called every time
+ the watchdog timer expires. It also passes the amount of time since the last
+ handler call to the NotifyFunction.
+ If NotifyFunction is not NULL and a handler is not already registered,
+ then the new handler is registered and EFI_SUCCESS is returned.
+ If NotifyFunction is NULL, and a handler is already registered,
+ then that handler is unregistered.
+ If an attempt is made to register a handler when a handler is already registered,
+ then EFI_ALREADY_STARTED is returned.
+ If an attempt is made to unregister a handler when a handler is not registered,
+ then EFI_INVALID_PARAMETER is returned.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The function to call when a timer interrupt fires. This
+ function executes at TPL_HIGH_LEVEL. The DXE Core will
+ register a handler for the timer interrupt, so it can know
+ how much time has passed. This information is used to
+ signal timer based events. NULL will unregister the handler.
+
+ @retval EFI_SUCCESS The watchdog timer handler was registered.
+ @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
+ registered.
+ @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
+ previously registered.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+WdogRegisterHandler (
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
+ )
+{
+ // ERROR: This function is not supported.
+ // The hardware watchdog will reset the board
+ return EFI_INVALID_PARAMETER;
+}
+
+/**
+
+ This function adjusts the period of timer interrupts to the value specified
+ by TimerPeriod. If the timer period is updated, then the selected timer
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+ If an error occurs while attempting to update the timer period, then the
+ timer hardware will be put back in its state prior to this call, and
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+ is disabled. This is not the same as disabling the CPU's interrupts.
+ Instead, it must either turn off the timer hardware, or it must adjust the
+ interrupt controller so that a CPU interrupt is not generated when the timer
+ interrupt fires.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is
+ returned. If the timer is programmable, then the timer period
+ will be rounded up to the nearest timer period that is supported
+ by the timer hardware. If TimerPeriod is set to 0, then the
+ timer interrupts will be disabled.
+
+
+ @retval EFI_SUCCESS The timer period was changed.
+ @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
+ @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+WdogSetTimerPeriod (
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ IN UINT64 TimerPeriod // In 100ns units
+ )
+{
+ EFI_STATUS Status;
+ UINT64 TimerPeriodInSec;
+ UINT16 Val;
+
+ Status = EFI_SUCCESS;
+
+ if (TimerPeriod == 0) {
+ // This is a watchdog stop request
+ WdogStop ();
+ return Status;
+ } else {
+ // Convert the TimerPeriod (in 100 ns unit) to an equivalent second value
+
+ TimerPeriodInSec = DivU64x32 (TimerPeriod, NANO_SECOND_BASE);
+
+ // The registers in the Wdog are only 32 bits
+ if (TimerPeriodInSec > WT_MAX_TIME) {
+ // We could load the watchdog with the maximum supported value but
+ // if a smaller value was requested, this could have the watchdog
+ // triggering before it was intended.
+ // Better generate an error to let the caller know.
+ Status = EFI_DEVICE_ERROR;
+ return Status;
+ }
+
+ // set the new timeout value in the WCR
+ // Convert the timeout value from Seconds to timer count
+ Val = ((WD_COUNT(TimerPeriodInSec) & WD_COUNT_MASK) << 8);
+
+ mMmioOps->AndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
+ (UINT16)(~WDOG_WCR_WT),
+ Val);
+ // Start the watchdog
+ WdogStart ();
+ }
+
+ return Status;
+}
+
+/**
+ This function retrieves the period of timer interrupts in 100 ns units,
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+ returned, then the timer is currently disabled.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
+ 0 is returned, then the timer is currently disabled.
+
+
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+WdogGetTimerPeriod (
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ OUT UINT64 *TimerPeriod
+ )
+{
+ EFI_STATUS Status;
+ UINT64 ReturnValue;
+ UINT16 Val;
+
+ Status = EFI_SUCCESS;
+
+ if (TimerPeriod == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Check if the watchdog is stopped
+ if ((mMmioOps->Read (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET)
+ & WDOG_WCR_WDE) == 0 ) {
+ // It is stopped, so return zero.
+ ReturnValue = 0;
+ } else {
+ // Convert the Watchdog ticks into equivalent TimerPeriod second value.
+ Val = (mMmioOps->Read (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET)
+ & WDOG_WCR_WT ) >> 8;
+ ReturnValue = WD_SEC(Val);
+ }
+
+ *TimerPeriod = ReturnValue;
+ return Status;
+}
+
+/**
+ Interface structure for the Watchdog Architectural Protocol.
+
+ @par Protocol Description:
+ This protocol provides a service to set the amount of time to wait
+ before firing the watchdog timer, and it also provides a service to
+ register a handler that is invoked when the watchdog timer fires.
+
+ @par When the watchdog timer fires, control will be passed to a handler
+ if one has been registered. If no handler has been registered,
+ or the registered handler returns, then the system will be
+ reset by calling the Runtime Service ResetSystem().
+
+ @param RegisterHandler
+ Registers a handler that will be called each time the
+ watchdogtimer interrupt fires. TimerPeriod defines the minimum
+ time between timer interrupts, so TimerPeriod will also
+ be the minimum time between calls to the registered
+ handler.
+ NOTE: If the watchdog resets the system in hardware, then
+ this function will not have any chance of executing.
+
+ @param SetTimerPeriod
+ Sets the period of the timer interrupt in 100 nS units.
+ This function is optional, and may return EFI_UNSUPPORTED.
+ If this function is supported, then the timer period will
+ be rounded up to the nearest supported timer period.
+
+ @param GetTimerPeriod
+ Retrieves the period of the timer interrupt in 100 nS units.
+
+**/
+STATIC
+EFI_WATCHDOG_TIMER_ARCH_PROTOCOL gWatchdogTimer = {
+ WdogRegisterHandler,
+ WdogSetTimerPeriod,
+ WdogGetTimerPeriod
+};
+
+/**
+ Call back function when the timer event is signaled.
+ This function will feed the watchdog with maximum value
+ so that system wont reset in idle case e.g. stopped on UEFI shell.
+
+ @param[in] Event The Event this notify function registered to.
+ @param[in] Context Pointer to the context data registered to the
+ Event.
+
+**/
+VOID
+EFIAPI
+WdogFeed (
+ IN EFI_EVENT Event,
+ IN VOID* Context
+ )
+{
+ WdogPing();
+}
+/**
+ Initialize state information for the Watchdog Timer Architectural Protocol.
+
+ @param ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Protocol registered
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Hardware problems
+
+**/
+EFI_STATUS
+EFIAPI
+WdogInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ mMmioOps = GetMmioOperations16 (FixedPcdGetBool (PcdWdogBigEndian));
+
+ mMmioOps->AndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
+ (UINT16)(~WDOG_WCR_WT),
+ (WD_COUNT (WT_MAX_TIME) & WD_COUNT_MASK));
+
+ mMmioOps->Or (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET, WDOG_WCR_WDE);
+
+ //
+ // Make sure the Watchdog Timer Architectural Protocol
+ // has not been installed in the system yet.
+ // This will avoid conflicts with the universal watchdog
+ //
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid);
+
+ // Register for an ExitBootServicesEvent
+ Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,
+ ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
+ if (EFI_ERROR (Status)) {
+ Status = EFI_OUT_OF_RESOURCES;
+ return Status;
+ }
+
+ //
+ // Start the timer to feed Watchdog with maximum timeout value.
+ //
+ Status = gBS->CreateEvent (
+ EVT_TIMER | EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ WdogFeed,
+ NULL,
+ &WdogFeedEvent
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = gBS->SetTimer (WdogFeedEvent, TimerPeriodic, WT_FEED_INTERVAL);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Install the Timer Architectural Protocol onto a new handle
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ gBS->CloseEvent (EfiExitBootServicesEvent);
+ Status = EFI_OUT_OF_RESOURCES;
+ return Status;
+ }
+
+ WdogPing ();
+
+ return Status;
+}
diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.h b/Silicon/NXP/Drivers/WatchDog/WatchDog.h
new file mode 100644
index 0000000..9542608
--- /dev/null
+++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.h
@@ -0,0 +1,39 @@
+/** WatchDog.h
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __WATCHDOG_H__
+#define __WATCHDOG_H__
+
+#define WDOG_SIZE 0x1000
+#define WDOG_WCR_OFFSET 0
+#define WDOG_WSR_OFFSET 2
+#define WDOG_WRSR_OFFSET 4
+#define WDOG_WICR_OFFSET 6
+#define WDOG_WCR_WT (0xFF << 8)
+#define WDOG_WCR_WDE (1 << 2)
+#define WDOG_SERVICE_SEQ1 0x5555
+#define WDOG_SERVICE_SEQ2 0xAAAA
+#define WDOG_WCR_WDZST 0x1
+#define WDOG_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
+
+#define WT_MAX_TIME 128
+#define WD_COUNT(Sec) (((Sec) * 2 - 1) << 8)
+#define WD_COUNT_MASK 0xff00
+#define WD_SEC(Cnt) (((Cnt) + 1) / 2)
+
+#define NANO_SECOND_BASE 10000000
+
+#define WT_FEED_INTERVAL (WT_MAX_TIME * NANO_SECOND_BASE)
+
+#endif //__WATCHDOG_H__
diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf b/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
new file mode 100644
index 0000000..a311bdc
--- /dev/null
+++ b/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
@@ -0,0 +1,47 @@
+# WatchDog.inf
+#
+# Component description file for WatchDog module
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = WatchDogDxe
+ FILE_GUID = 0358b544-ec65-4339-89cd-cad60a3dd787
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = WdogInitialize
+
+[Sources.common]
+ WatchDog.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ IoAccessLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian
+
+[Protocols]
+ gEfiWatchdogTimerArchProtocolGuid
+
+[Depex]
+ TRUE
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 03/41] SocLib : Add support for initialization of peripherals
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 01/41] Silicon/NXP: Add Library to return Mmio APIs pointer Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 02/41] Silicon/NXP : Add support for Watchdog driver Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-18 12:31 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 04/41] Silicon/NXP : Add support for DUART library Meenakshi Aggarwal
` (39 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Add SocInit function that initializes peripherals
and print board and soc information.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Include/Chassis2/SerDes.h | 68 +++++
Silicon/NXP/Include/Chassis2/Soc.h | 367 ++++++++++++++++++++++++++
Silicon/NXP/LS1043A/Include/SocSerDes.h | 57 ++++
Silicon/NXP/Library/SocLib/Chassis.c | 372 +++++++++++++++++++++++++++
Silicon/NXP/Library/SocLib/Chassis.h | 144 +++++++++++
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 167 ++++++++++++
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 49 ++++
Silicon/NXP/Library/SocLib/SerDes.c | 271 +++++++++++++++++++
8 files changed, 1495 insertions(+)
create mode 100644 Silicon/NXP/Include/Chassis2/SerDes.h
create mode 100644 Silicon/NXP/Include/Chassis2/Soc.h
create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
create mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
create mode 100644 Silicon/NXP/Library/SocLib/Chassis.h
create mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
create mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
create mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
diff --git a/Silicon/NXP/Include/Chassis2/SerDes.h b/Silicon/NXP/Include/Chassis2/SerDes.h
new file mode 100644
index 0000000..4c874aa
--- /dev/null
+++ b/Silicon/NXP/Include/Chassis2/SerDes.h
@@ -0,0 +1,68 @@
+/** SerDes.h
+ The Header file of SerDes Module for Chassis 2
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SERDES_H__
+#define __SERDES_H__
+
+#include <Uefi/UefiBaseType.h>
+
+#define SRDS_MAX_LANES 4
+
+typedef enum {
+ NONE = 0,
+ PCIE1,
+ PCIE2,
+ PCIE3,
+ SATA,
+ SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC10,
+ QSGMII_FM1_A,
+ XFI_FM1_MAC9,
+ XFI_FM1_MAC10,
+ SGMII_2500_FM1_DTSEC2,
+ SGMII_2500_FM1_DTSEC5,
+ SGMII_2500_FM1_DTSEC9,
+ SGMII_2500_FM1_DTSEC10,
+ SERDES_PRTCL_COUNT
+} SERDES_PROTOCOL;
+
+typedef enum {
+ SRDS_1 = 0,
+ SRDS_2,
+ SRDS_MAX_NUM
+} SERDES_NUMBER;
+
+typedef struct {
+ UINT16 Protocol;
+ UINT8 SrdsLane[SRDS_MAX_LANES];
+} SERDES_CONFIG;
+
+typedef VOID
+(*SERDES_PROBE_LANES_CALLBACK) (
+ IN SERDES_PROTOCOL LaneProtocol,
+ IN VOID *Arg
+ );
+
+VOID
+SerDesProbeLanes(
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ );
+
+#endif /* __SERDES_H */
diff --git a/Silicon/NXP/Include/Chassis2/Soc.h b/Silicon/NXP/Include/Chassis2/Soc.h
new file mode 100644
index 0000000..10e99ab
--- /dev/null
+++ b/Silicon/NXP/Include/Chassis2/Soc.h
@@ -0,0 +1,367 @@
+/** Soc.h
+* Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#define HWA_CGA_M1_CLK_SEL 0xe0000000
+#define HWA_CGA_M1_CLK_SHIFT 29
+
+#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
+#define NUM_CC_PLLS 2
+#define CLK_FREQ 100000000
+#define MAX_CPUS 4
+#define NUM_FMAN 1
+#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
+
+/* RCW SERDES MACRO */
+#define RCWSR_INDEX 4
+#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
+#define RCWSR_SRDS1_PRTCL_SHIFT 16
+#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
+#define RCWSR_SRDS2_PRTCL_SHIFT 0
+
+/* SMMU Defintions */
+#define SMMU_BASE_ADDR 0x09000000
+#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
+#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
+#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
+
+#define SCR0_USFCFG_MASK 0x00000400
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SACR_PAGESIZE_MASK 0x00010000
+#define IDR1_PAGESIZE_MASK 0x80000000
+
+typedef struct {
+ UINTN FreqProcessor[MAX_CPUS];
+ UINTN FreqSystemBus;
+ UINTN FreqDdrBus;
+ UINTN FreqLocalBus;
+ UINTN FreqSdhc;
+ UINTN FreqFman[NUM_FMAN];
+ UINTN FreqQman;
+} SYS_INFO;
+
+/* Device Configuration and Pin Control */
+typedef struct {
+ UINT32 PorSr1; /* POR status 1 */
+#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
+ UINT32 PorSr2; /* POR status 2 */
+ UINT8 Res008[0x20-0x8];
+ UINT32 GppOrCr1; /* General-purpose POR configuration */
+ UINT32 GppOrCr2;
+ UINT32 DcfgFuseSr; /* Fuse status register */
+ UINT8 Res02c[0x70-0x2c];
+ UINT32 DevDisr; /* Device disable control */
+ UINT32 DevDisr2; /* Device disable control 2 */
+ UINT32 DevDisr3; /* Device disable control 3 */
+ UINT32 DevDisr4; /* Device disable control 4 */
+ UINT32 DevDisr5; /* Device disable control 5 */
+ UINT32 DevDisr6; /* Device disable control 6 */
+ UINT32 DevDisr7; /* Device disable control 7 */
+ UINT8 Res08c[0x94-0x8c];
+ UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
+ UINT32 CoreDisrL; /* lower portion for support of 64 cores */
+ UINT8 Res09c[0xa0-0x9c];
+ UINT32 Pvr; /* Processor version */
+ UINT32 Svr; /* System version */
+ UINT32 Mvr; /* Manufacturing version */
+ UINT8 Res0ac[0xb0-0xac];
+ UINT32 RstCr; /* Reset control */
+ UINT32 RstRqPblSr; /* Reset request preboot loader status */
+ UINT8 Res0b8[0xc0-0xb8];
+ UINT32 RstRqMr1; /* Reset request mask */
+ UINT8 Res0c4[0xc8-0xc4];
+ UINT32 RstRqSr1; /* Reset request status */
+ UINT8 Res0cc[0xd4-0xcc];
+ UINT32 RstRqWdTmrL; /* Reset request WDT mask */
+ UINT8 Res0d8[0xdc-0xd8];
+ UINT32 RstRqWdtSrL; /* Reset request WDT status */
+ UINT8 Res0e0[0xe4-0xe0];
+ UINT32 BrrL; /* Boot release */
+ UINT8 Res0e8[0x100-0xe8];
+ UINT32 RcwSr[16]; /* Reset control word status */
+#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
+#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
+#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
+#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
+ UINT8 Res140[0x200-0x140];
+ UINT32 ScratchRw[4]; /* Scratch Read/Write */
+ UINT8 Res210[0x300-0x210];
+ UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
+ UINT8 Res310[0x400-0x310];
+ UINT32 CrstSr[12];
+ UINT8 Res430[0x500-0x430];
+ /* PCI Express n Logical I/O Device Number register */
+ UINT32 DcfgCcsrPex1LiodNr;
+ UINT32 DcfgCcsrPex2LiodNr;
+ UINT32 DcfgCcsrPex3LiodNr;
+ UINT32 DcfgCcsrPex4LiodNr;
+ /* RIO n Logical I/O Device Number register */
+ UINT32 DcfgCcsrRio1LiodNr;
+ UINT32 DcfgCcsrRio2LiodNr;
+ UINT32 DcfgCcsrRio3LiodNr;
+ UINT32 DcfgCcsrRio4LiodNr;
+ /* USB Logical I/O Device Number register */
+ UINT32 DcfgCcsrUsb1LiodNr;
+ UINT32 DcfgCcsrUsb2LiodNr;
+ UINT32 DcfgCcsrUsb3LiodNr;
+ UINT32 DcfgCcsrUsb4LiodNr;
+ /* SD/MMC Logical I/O Device Number register */
+ UINT32 DcfgCcsrSdMmc1LiodNr;
+ UINT32 DcfgCcsrSdMmc2LiodNr;
+ UINT32 DcfgCcsrSdMmc3LiodNr;
+ UINT32 DcfgCcsrSdMmc4LiodNr;
+ /* RIO Message Unit Logical I/O Device Number register */
+ UINT32 DcfgCcsrRiomaintLiodNr;
+ UINT8 Res544[0x550-0x544];
+ UINT32 SataLiodNr[4];
+ UINT8 Res560[0x570-0x560];
+ UINT32 DcfgCcsrMisc1LiodNr;
+ UINT32 DcfgCcsrMisc2LiodNr;
+ UINT32 DcfgCcsrMisc3LiodNr;
+ UINT32 DcfgCcsrMisc4LiodNr;
+ UINT32 DcfgCcsrDma1LiodNr;
+ UINT32 DcfgCcsrDma2LiodNr;
+ UINT32 DcfgCcsrDma3LiodNr;
+ UINT32 DcfgCcsrDma4LiodNr;
+ UINT32 DcfgCcsrSpare1LiodNr;
+ UINT32 DcfgCcsrSpare2LiodNr;
+ UINT32 DcfgCcsrSpare3LiodNr;
+ UINT32 DcfgCcsrSpare4LiodNr;
+ UINT8 Res5a0[0x600-0x5a0];
+ UINT32 DcfgCcsrPblSr;
+ UINT32 PamuBypENr;
+ UINT32 DmaCr1;
+ UINT8 Res60c[0x610-0x60c];
+ UINT32 DcfgCcsrGenSr1;
+ UINT32 DcfgCcsrGenSr2;
+ UINT32 DcfgCcsrGenSr3;
+ UINT32 DcfgCcsrGenSr4;
+ UINT32 DcfgCcsrGenCr1;
+ UINT32 DcfgCcsrGenCr2;
+ UINT32 DcfgCcsrGenCr3;
+ UINT32 DcfgCcsrGenCr4;
+ UINT32 DcfgCcsrGenCr5;
+ UINT32 DcfgCcsrGenCr6;
+ UINT32 DcfgCcsrGenCr7;
+ UINT8 Res63c[0x658-0x63c];
+ UINT32 DcfgCcsrcGenSr1;
+ UINT32 DcfgCcsrcGenSr0;
+ UINT8 Res660[0x678-0x660];
+ UINT32 DcfgCcsrcGenCr1;
+ UINT32 DcfgCcsrcGenCr0;
+ UINT8 Res680[0x700-0x680];
+ UINT32 DcfgCcsrSrIoPstecr;
+ UINT32 DcfgCcsrDcsrCr;
+ UINT8 Res708[0x740-0x708]; /* add more registers when needed */
+ UINT32 TpItyp[64]; /* Topology Initiator Type Register */
+ struct {
+ UINT32 Upper;
+ UINT32 Lower;
+ } TpCluster[16];
+ UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
+ UINT32 DcfgCcsrQmBmWarmRst;
+ UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
+ UINT32 DcfgCcsrReserved0;
+ UINT32 DcfgCcsrReserved1;
+} CCSR_GUR;
+
+/* Supplemental Configuration Unit */
+typedef struct {
+ UINT8 Res000[0x070-0x000];
+ UINT32 Usb1Prm1Cr;
+ UINT32 Usb1Prm2Cr;
+ UINT32 Usb1Prm3Cr;
+ UINT32 Usb2Prm1Cr;
+ UINT32 Usb2Prm2Cr;
+ UINT32 Usb2Prm3Cr;
+ UINT32 Usb3Prm1Cr;
+ UINT32 Usb3Prm2Cr;
+ UINT32 Usb3Prm3Cr;
+ UINT8 Res094[0x100-0x094];
+ UINT32 Usb2Icid;
+ UINT32 Usb3Icid;
+ UINT8 Res108[0x114-0x108];
+ UINT32 DmaIcid;
+ UINT32 SataIcid;
+ UINT32 Usb1Icid;
+ UINT32 QeIcid;
+ UINT32 SdhcIcid;
+ UINT32 EdmaIcid;
+ UINT32 EtrIcid;
+ UINT32 Core0SftRst;
+ UINT32 Core1SftRst;
+ UINT32 Core2SftRst;
+ UINT32 Core3SftRst;
+ UINT8 Res140[0x158-0x140];
+ UINT32 AltCBar;
+ UINT32 QspiCfg;
+ UINT8 Res160[0x180-0x160];
+ UINT32 DmaMcr;
+ UINT8 Res184[0x188-0x184];
+ UINT32 GicAlign;
+ UINT32 DebugIcid;
+ UINT8 Res190[0x1a4-0x190];
+ UINT32 SnpCnfGcr;
+#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
+#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
+#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
+#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
+#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
+#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
+#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
+#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
+#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
+#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
+ UINT8 Res1a8[0x1ac-0x1a8];
+ UINT32 IntpCr;
+ UINT8 Res1b0[0x204-0x1b0];
+ UINT32 CoreSrEnCr;
+ UINT8 Res208[0x220-0x208];
+ UINT32 RvBar00;
+ UINT32 RvBar01;
+ UINT32 RvBar10;
+ UINT32 RvBar11;
+ UINT32 RvBar20;
+ UINT32 RvBar21;
+ UINT32 RvBar30;
+ UINT32 RvBar31;
+ UINT32 LpmCsr;
+ UINT8 Res244[0x400-0x244];
+ UINT32 QspIdQScr;
+ UINT32 EcgTxcMcr;
+ UINT32 SdhcIoVSelCr;
+ UINT32 RcwPMuxCr0;
+ /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+ *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+ *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
+ Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
+#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
+ /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+ *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+ *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
+ Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
+#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
+ UINT32 UsbDrvVBusSelCr;
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
+ UINT32 UsbPwrFaultSelCr;
+#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
+#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
+#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
+#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
+#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
+#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
+ UINT32 UsbRefclkSelcr1;
+ UINT32 UsbRefclkSelcr2;
+ UINT32 UsbRefclkSelcr3;
+ UINT8 Res424[0x600-0x424];
+ UINT32 ScratchRw[4];
+ UINT8 Res610[0x680-0x610];
+ UINT32 CoreBCr;
+ UINT8 Res684[0x1000-0x684];
+ UINT32 Pex1MsiIr;
+ UINT32 Pex1MsiR;
+ UINT8 Res1008[0x2000-0x1008];
+ UINT32 Pex2;
+ UINT32 Pex2MsiR;
+ UINT8 Res2008[0x3000-0x2008];
+ UINT32 Pex3MsiIr;
+ UINT32 Pex3MsiR;
+} CCSR_SCFG;
+
+#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8003
+#define USB_PHY_RX_EQ_VAL_4 0x800b
+
+/*USB_PHY_SS memory map*/
+typedef struct {
+ UINT16 IpIdcodeLo;
+ UINT16 SupIdcodeHi;
+ UINT8 Res4[0x0006-0x0004];
+ UINT16 RtuneDebug;
+ UINT16 RtuneStat;
+ UINT16 SupSsPhase;
+ UINT16 SsFreq;
+ UINT8 ResE[0x0020-0x000e];
+ UINT16 Ateovrd;
+ UINT16 MpllOvrdInLo;
+ UINT8 Res24[0x0026-0x0024];
+ UINT16 SscOvrdIn;
+ UINT8 Res28[0x002A-0x0028];
+ UINT16 LevelOvrdIn;
+ UINT8 Res2C[0x0044-0x002C];
+ UINT16 ScopeCount;
+ UINT8 Res46[0x0060-0x0046];
+ UINT16 MpllLoopCtl;
+ UINT8 Res62[0x006C-0x0062];
+ UINT16 SscClkCntrl;
+ UINT8 Res6E[0x2002-0x006E];
+ UINT16 Lane0TxOvrdInHi;
+ UINT16 Lane0TxOvrdDrvLo;
+ UINT8 Res2006[0x200C-0x2006];
+ UINT16 Lane0RxOvrdInHi;
+ UINT8 Res200E[0x2022-0x200E];
+ UINT16 Lane0TxCmWaitTimeOvrd;
+ UINT8 Res2024[0x202A-0x2024];
+ UINT16 Lane0TxLbertCtl;
+ UINT16 Lane0RxLbertCtl;
+ UINT16 Lane0RxLbertErr;
+ UINT8 Res2030[0x205A-0x2030];
+ UINT16 Lane0TxAltBlock;
+} CCSR_USB_PHY;
+
+/* Clocking */
+typedef struct {
+ struct {
+ UINT32 ClkCnCSr; /* core cluster n clock control status */
+ UINT8 Res004[0x0c];
+ UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
+ UINT8 Res014[0x0c];
+ } ClkcSr[4];
+ UINT8 Res040[0x780]; /* 0x100 */
+ struct {
+ UINT32 PllCnGSr;
+ UINT8 Res804[0x1c];
+ } PllCgSr[NUM_CC_PLLS];
+ UINT8 Res840[0x1c0];
+ UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
+ UINT8 Resa04[0x1fc];
+ UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
+ UINT8 Resc04[0x1c];
+ UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
+ UINT8 Resc24[0x3dc];
+} CCSR_CLOCK;
+
+VOID
+GetSysInfo (
+ OUT SYS_INFO *
+ );
+
+UINT32
+EFIAPI
+GurRead (
+ IN UINTN Address
+ );
+
+#endif /* __SOC_H__ */
diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
new file mode 100644
index 0000000..7707e2a
--- /dev/null
+++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h
@@ -0,0 +1,57 @@
+/** @file
+ The Header file of SerDes Module for LS1043A
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SOC_SERDES_H__
+#define __SOC_SERDES_H__
+
+#ifdef CHASSIS2
+#include <Chassis2/SerDes.h>
+#endif
+
+SERDES_CONFIG SerDes1ConfigTbl[] = {
+ /* SerDes 1 */
+ {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } },
+ {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
+ {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } },
+ {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } },
+ {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } },
+ {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } },
+ {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
+ {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } },
+ {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+ {0x9998, {PCIE1, PCIE2, PCIE3, SATA } },
+ {0x6058, {PCIE1, PCIE1, PCIE2, SATA } },
+ {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+ {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+ {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } },
+ {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+ {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+ {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
+ {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
+ {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } },
+ {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {}
+};
+
+SERDES_CONFIG *SerDesConfigTbl[] = {
+ SerDes1ConfigTbl
+};
+
+#endif /* __SOC_SERDES_H */
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
new file mode 100644
index 0000000..851174c
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -0,0 +1,372 @@
+/** @file
+ SoC specific Library containg functions to initialize various SoC components
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#ifdef CHASSIS2
+#include <Chassis2/Soc.h>
+#endif
+#include <Library/BaseLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include "Chassis.h"
+
+UINT32
+EFIAPI
+GurRead (
+ IN UINTN Address
+ )
+{
+ if (FixedPcdGetBool (PcdGurBigEndian)) {
+ return SwapMmioRead32 (Address);
+ } else {
+ return MmioRead32 (Address);
+ }
+}
+
+/*
+ * Structure to list available SOCs.
+ */
+STATIC CPU_TYPE CpuTypeList[] = {
+ CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
+};
+
+/*
+ * Return the type of initiator (core or hardware accelerator)
+ */
+UINT32
+InitiatorType (
+ IN UINT32 Cluster,
+ IN UINTN InitId
+ )
+{
+ CCSR_GUR *GurBase;
+ UINT32 Idx;
+ UINT32 Type;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
+ Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
+
+ if (Type & TP_ITYP_AV_MASK) {
+ return Type;
+ }
+
+ return 0;
+}
+
+/*
+ * Return the mask for number of cores on this SOC.
+ */
+UINT32
+CpuMask (
+ VOID
+ )
+{
+ CCSR_GUR *GurBase;
+ UINTN ClusterIndex;
+ UINTN Count;
+ UINT32 Cluster;
+ UINT32 Type;
+ UINT32 Mask;
+ UINTN InitiatorIndex;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClusterIndex = 0;
+ Count = 0;
+ Mask = 0;
+
+ do {
+ Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+ for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+ Type = InitiatorType (Cluster, InitiatorIndex);
+ if (Type) {
+ if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) {
+ Mask |= 1 << Count;
+ }
+ Count++;
+ }
+ }
+ ClusterIndex++;
+ } while (CHECK_CLUSTER (Cluster));
+
+ return Mask;
+}
+
+/*
+ * Return the number of cores on this SOC.
+ */
+UINTN
+CpuNumCores (
+ VOID
+ )
+{
+ UINTN Count;
+ UINTN Num;
+
+ Count = 0;
+ Num = CpuMask ();
+
+ while (Num) {
+ Count += Num & 1;
+ Num >>= 1;
+ }
+
+ return Count;
+}
+
+/*
+ * Return the type of core i.e. A53, A57 etc of inputted
+ * core number.
+ */
+UINTN
+QoriqCoreToType (
+ IN UINTN Core
+ )
+{
+ CCSR_GUR *GurBase;
+ UINTN ClusterIndex;
+ UINTN Count;
+ UINT32 Cluster;
+ UINT32 Type;
+ UINTN InitiatorIndex;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClusterIndex = 0;
+ Count = 0;
+
+ do {
+ Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+ for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+ Type = InitiatorType (Cluster, InitiatorIndex);
+ if (Type) {
+ if (Count == Core) {
+ return Type;
+ }
+ Count++;
+ }
+ }
+ ClusterIndex++;
+ } while (CHECK_CLUSTER (Cluster));
+
+ return EFI_NOT_FOUND; /* cannot identify the cluster */
+}
+
+/*
+ * Print CPU information
+ */
+VOID
+PrintCpuInfo (
+ VOID
+ )
+{
+ SYS_INFO SysInfo;
+ UINTN CoreIndex;
+ UINTN Core;
+ UINT32 Type;
+ CHAR8 Buffer[50];
+
+ GetSysInfo (&SysInfo);
+ DEBUG ((DEBUG_INIT, "Clock Configuration:"));
+
+ ForEachCpu (CoreIndex, Core, CpuNumCores (), CpuMask ()) {
+ if (!(CoreIndex % 3)) {
+ DEBUG ((DEBUG_INIT, "\n "));
+ }
+
+ Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
+ switch (Type) {
+ case TY_ITYP_VERSION_A7:
+ AsciiStrCpy (Buffer, "A7");
+ break;
+ case TY_ITYP_VERSION_A53:
+ AsciiStrCpy (Buffer, "A53");
+ break;
+ case TY_ITYP_VERSION_A57:
+ AsciiStrCpy (Buffer, "A57");
+ break;
+ case TY_ITYP_VERSION_A72:
+ AsciiStrCpy (Buffer, "A72");
+ break;
+ default:
+ AsciiStrCpy (Buffer, " Unknown Core ");
+ }
+ DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ", Core, Buffer, SysInfo.FreqProcessor[Core] / MHZ));
+ }
+
+ DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ));
+ DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ));
+
+ if (SysInfo.FreqFman[0] != 0) {
+ DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ));
+ }
+
+ DEBUG ((DEBUG_INIT, "\n"));
+}
+
+/*
+ * Return system bus frequency
+ */
+UINT64
+GetBusFrequency (
+ VOID
+ )
+{
+ SYS_INFO SocSysInfo;
+
+ GetSysInfo (&SocSysInfo);
+
+ return SocSysInfo.FreqSystemBus;
+}
+
+/*
+ * Return SDXC bus frequency
+ */
+UINT64
+GetSdxcFrequency (
+ VOID
+ )
+{
+ SYS_INFO SocSysInfo;
+
+ GetSysInfo (&SocSysInfo);
+
+ return SocSysInfo.FreqSdhc;
+}
+
+/*
+ * Print Soc information
+ */
+VOID
+PrintSoc (
+ VOID
+ )
+{
+ CHAR8 Buf[16];
+ CCSR_GUR *GurBase;
+ UINTN Count;
+ UINTN Svr;
+ UINTN Ver;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+ Buf[0] = L'\0';
+ Svr = GurRead ((UINTN)&GurBase->Svr);
+ Ver = SVR_SOC_VER (Svr);
+
+ for (Count = 0; Count < ARRAY_SIZE (CpuTypeList); Count++)
+ if ((CpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
+ AsciiStrCpy (Buf, (CONST CHAR8 *)CpuTypeList[Count].Name);
+
+ if (IS_E_PROCESSOR (Svr)) {
+ AsciiStrCat (Buf, (CONST CHAR8 *)"E");
+ }
+ break;
+ }
+
+ if (Count == ARRAY_SIZE (CpuTypeList)) {
+ AsciiStrCpy (Buf, (CONST CHAR8 *)"unknown");
+ }
+
+ DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
+ Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
+
+ return;
+}
+
+/*
+ * Dump RCW (Reset Control Word) on console
+ */
+VOID
+PrintRCW (
+ VOID
+ )
+{
+ CCSR_GUR *Base;
+ UINTN Count;
+
+ Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+ /*
+ * Display the RCW, so that no one gets confused as to what RCW
+ * we're actually using for this boot.
+ */
+
+ DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):"));
+ for (Count = 0; Count < ARRAY_SIZE(Base->RcwSr); Count++) {
+ UINT32 Rcw = SwapMmioRead32((UINTN)&Base->RcwSr[Count]);
+
+ if ((Count % 4) == 0) {
+ DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4));
+ }
+
+ DEBUG ((DEBUG_INIT, " %08x", Rcw));
+ }
+
+ DEBUG ((DEBUG_INIT, "\n"));
+}
+
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+VOID
+SmmuInit (
+ VOID
+ )
+{
+ UINT32 Value;
+
+ /* set pagesize as 64K and ssmu-500 in bypass mode */
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
+ MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
+}
+
+/*
+ * Return current Soc Name form CpuTypeList
+ */
+CHAR8 *
+GetSocName (
+ VOID
+ )
+{
+ UINT8 Count;
+ UINTN Svr;
+ UINTN Ver;
+ CCSR_GUR *GurBase;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+ Svr = GurRead ((UINTN)&GurBase->Svr);
+ Ver = SVR_SOC_VER (Svr);
+
+ for (Count = 0; Count < ARRAY_SIZE (CpuTypeList); Count++) {
+ if ((CpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
+ return (CHAR8 *)CpuTypeList[Count].Name;
+ }
+ }
+
+ return NULL;
+}
diff --git a/Silicon/NXP/Library/SocLib/Chassis.h b/Silicon/NXP/Library/SocLib/Chassis.h
new file mode 100644
index 0000000..5aa1209
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/Chassis.h
@@ -0,0 +1,144 @@
+/** @file
+* Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __CHASSIS_H__
+#define __CHASSIS_H__
+
+#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
+#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
+#define TP_ITYP_TYPE_ARM 0x0
+#define TP_ITYP_TYPE_PPC 0x1
+#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
+#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
+#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
+#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
+#define TP_INIT_PER_CLUSTER 4
+
+#define TY_ITYP_VERSION_A7 0x1
+#define TY_ITYP_VERSION_A53 0x2
+#define TY_ITYP_VERSION_A57 0x3
+#define TY_ITYP_VERSION_A72 0x4
+
+STATIC
+inline
+UINTN
+CpuMaskNext (
+ IN UINTN Cpu,
+ IN UINTN Mask
+ )
+{
+ for (Cpu++; !((1 << Cpu) & Mask); Cpu++)
+ ;
+
+ return Cpu;
+}
+
+#define ForEachCpu(Iter, Cpu, NumCpus, Mask) \
+ for (Iter = 0, Cpu = CpuMaskNext(-1, Mask); \
+ Iter < NumCpus; \
+ Iter++, Cpu = CpuMaskNext(Cpu, Mask)) \
+
+#define CPU_TYPE_ENTRY(N, V, NC) \
+ { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
+
+#define SVR_WO_E 0xFFFFFE
+#define SVR_LS1043A 0x879200
+
+#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
+#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
+#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
+#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
+
+#define MHZ 1000000
+
+typedef struct {
+ CHAR8 Name[16];
+ UINT32 SocVer;
+ UINT32 NumCores;
+} CPU_TYPE;
+
+typedef struct {
+ UINTN CpuClk; /* CPU clock in Hz! */
+ UINTN BusClk;
+ UINTN MemClk;
+ UINTN PciClk;
+ UINTN SdhcClk;
+} SOC_CLOCK_INFO;
+
+/*
+ * Print Soc information
+ */
+VOID
+PrintSoc (
+ VOID
+ );
+
+/*
+ * Initialize Clock structure
+ */
+VOID
+ClockInit (
+ VOID
+ );
+
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+VOID
+SmmuInit (
+ VOID
+ );
+
+/*
+ * Print CPU information
+ */
+VOID
+PrintCpuInfo (
+ VOID
+ );
+
+/*
+ * Dump RCW (Reset Control Word) on console
+ */
+VOID
+PrintRCW (
+ VOID
+ );
+
+UINT32
+InitiatorType (
+ IN UINT32 Cluster,
+ IN UINTN InitId
+ );
+
+/*
+ * Return the mask for number of cores on this SOC.
+ */
+UINT32
+CpuMask (
+ VOID
+ );
+
+/*
+ * Return the number of cores on this SOC.
+ */
+UINTN
+CpuNumCores (
+ VOID
+ );
+
+#endif /* __CHASSIS_H__ */
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
new file mode 100644
index 0000000..1875c3b
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -0,0 +1,167 @@
+/** @Soc.c
+ SoC specific Library containg functions to initialize various SoC components
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Chassis.h>
+#include <Chassis2/Soc.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+/**
+ Calculate the frequency of various controllers and
+ populate the passed structure with frequuencies.
+
+ @param PtrSysInfo Input structure to populate with
+ frequencies.
+**/
+VOID
+GetSysInfo (
+ OUT SYS_INFO *PtrSysInfo
+ )
+{
+ CCSR_GUR *GurBase;
+ CCSR_CLOCK *ClkBase;
+ UINTN CpuIndex;
+ UINT32 TempRcw;
+ UINT32 CPllSel;
+ UINT32 CplxPll;
+ CONST UINT8 CoreCplxPll[8] = {
+ [0] = 0, /* CC1 PPL / 1 */
+ [1] = 0, /* CC1 PPL / 2 */
+ [4] = 1, /* CC2 PPL / 1 */
+ [5] = 1, /* CC2 PPL / 2 */
+ };
+
+ CONST UINT8 CoreCplxPllDivisor[8] = {
+ [0] = 1, /* CC1 PPL / 1 */
+ [1] = 2, /* CC1 PPL / 2 */
+ [4] = 1, /* CC2 PPL / 1 */
+ [5] = 2, /* CC2 PPL / 2 */
+ };
+
+ UINTN PllCount;
+ UINTN FreqCPll[NUM_CC_PLLS];
+ UINTN PllRatio[NUM_CC_PLLS];
+ UINTN SysClk;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
+ SysClk = CLK_FREQ;
+
+ SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
+
+ PtrSysInfo->FreqSystemBus = SysClk;
+ PtrSysInfo->FreqDdrBus = SysClk;
+
+ //
+ // selects the platform clock:SYSCLK ratio and calculate
+ // system frequency
+ //
+ PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+ CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+ CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+ //
+ // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
+ //
+ PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+ CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
+ CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+
+ for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
+ PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
+ if (PllRatio[PllCount] > 4) {
+ FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
+ } else {
+ FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
+ }
+ }
+
+ //
+ // Calculate Core frequency
+ //
+ for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
+ CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) & 0xf;
+ CplxPll = CoreCplxPll[CPllSel];
+
+ PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
+ }
+
+ //
+ // Calculate FMAN frequency
+ //
+ TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
+ switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
+ case 2:
+ PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
+ break;
+ case 3:
+ PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
+ break;
+ case 4:
+ PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
+ break;
+ case 5:
+ PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
+ break;
+ case 6:
+ PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
+ break;
+ case 7:
+ PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
+ break;
+ default:
+ DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
+ break;
+ }
+ PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
+ PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
+}
+
+/**
+ Function to initialize SoC specific constructs
+ CPU Info
+ SoC Personality
+ Board Personality
+ RCW prints
+ **/
+VOID
+SocInit (
+ VOID
+ )
+{
+ SmmuInit ();
+
+ //
+ // Early init serial Port to get board information.
+ //
+ SerialPortInitialize ();
+ DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
+ (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
+
+ PrintCpuInfo ();
+
+ //
+ // Print Reset control Word
+ //
+ PrintRCW ();
+ PrintSoc ();
+
+ return;
+}
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
new file mode 100644
index 0000000..d16288a
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -0,0 +1,49 @@
+# @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SocLib
+ FILE_GUID = e868c5ca-9729-43ae-bff4-438c67de8c68
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/LS1043A/LS1043A.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoAccessLib
+ SerialPortLib
+
+[Sources.common]
+ Chassis.c
+ Chassis2/Soc.c
+ SerDes.c
+
+[BuildOptions]
+ GCC:*_*_*_CC_FLAGS = -DCHASSIS2
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocLib/SerDes.c
new file mode 100644
index 0000000..e31e4f3
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/SerDes.c
@@ -0,0 +1,271 @@
+/** SerDes.c
+ Provides the basic interfaces for SerDes Module
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifdef CHASSIS2
+#include <Chassis2/SerDes.h>
+#include <Chassis2/Soc.h>
+#endif
+#include <Library/DebugLib.h>
+#include <SocSerDes.h>
+#include <Uefi.h>
+
+/**
+ Function to get serdes Lane protocol corresponding to
+ serdes protocol.
+
+ @param SerDes Serdes number.
+ @param Cfg Serdes Protocol.
+ @param Lane Serdes Lane number.
+
+ @return Serdes Lane protocol.
+
+**/
+STATIC
+SERDES_PROTOCOL
+GetSerDesPrtcl (
+ IN INTN SerDes,
+ IN INTN Cfg,
+ IN INTN Lane
+ )
+{
+ SERDES_CONFIG *Config;
+
+ if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
+ return 0;
+ }
+
+ Config = SerDesConfigTbl[SerDes];
+ while (Config->Protocol) {
+ if (Config->Protocol == Cfg) {
+ return Config->SrdsLane[Lane];
+ }
+ Config++;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to check if inputted protocol is a valid serdes protocol.
+
+ @param SerDes Serdes number.
+ @param Prtcl Serdes Protocol to be verified.
+
+ @return EFI_INVALID_PARAMETER Input parameter in invalid.
+ @return EFI_NOT_FOUND Serdes Protocol not a valid protocol.
+ @return EFI_SUCCESS Serdes Protocol is a valid protocol.
+
+**/
+STATIC
+EFI_STATUS
+CheckSerDesPrtclValid (
+ IN INTN SerDes,
+ IN UINT32 Prtcl
+ )
+{
+ SERDES_CONFIG *Config;
+ INTN Cnt;
+
+ if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Config = SerDesConfigTbl[SerDes];
+ while (Config->Protocol) {
+ if (Config->Protocol == Prtcl) {
+ DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl));
+ break;
+ }
+ Config++;
+ }
+
+ if (!Config->Protocol) {
+ return EFI_NOT_FOUND;
+ }
+
+ for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
+ if (Config->SrdsLane[Cnt] != NONE) {
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+ Function to fill serdes map information.
+
+ @param Srds Serdes number.
+ @param SerdesProtocolMask Serdes Protocol Mask.
+ @param SerdesProtocolShift Serdes Protocol shift value.
+ @param SerDesPrtclMap Pointer to Serdes Protocol map.
+
+**/
+STATIC
+VOID
+LSSerDesMap (
+ IN UINT32 Srds,
+ IN UINT32 SerdesProtocolMask,
+ IN UINT32 SerdesProtocolShift,
+ OUT UINT64 *SerDesPrtclMap
+ )
+{
+ CCSR_GUR *Gur;
+ UINT32 SrdsProt;
+ INTN Lane;
+ UINT32 Flag;
+
+ Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ *SerDesPrtclMap = 0x0;
+ Flag = 0;
+
+ SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
+ SrdsProt >>= SerdesProtocolShift;
+
+ DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
+ Srds + 1, SrdsProt, SrdsProt));
+
+ if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
+ DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
+ Srds + 1, SrdsProt));
+ Flag++;
+ }
+
+ for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
+ SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
+ if (LanePrtcl >= SERDES_PRTCL_COUNT) {
+ DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
+ Flag++;
+ } else {
+ *SerDesPrtclMap |= (1u << LanePrtcl);
+ }
+ }
+
+ if (Flag) {
+ DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
+ }
+}
+
+/**
+ Get lane protocol on provided serdes lane and execute callback function.
+
+ @param Srds Serdes number.
+ @param SerdesProtocolMask Mask to get Serdes Protocol for Srds
+ @param SerdesProtocolShift Shift value to get Serdes Protocol for Srds.
+ @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
+ @param Arg Pointer to Arguments to be passed to callback function.
+
+**/
+STATIC
+VOID
+SerDesInstanceProbeLanes (
+ IN UINT32 Srds,
+ IN UINT32 SerdesProtocolMask,
+ IN UINT32 SerdesProtocolShift,
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ )
+{
+
+ CCSR_GUR *Gur;
+ UINT32 SrdsProt;
+ INTN Lane;
+
+ Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
+
+ SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
+ SrdsProt >>= SerdesProtocolShift;
+
+ /*
+ * Invoke callback for all lanes in the SerDes instance:
+ */
+ for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
+ SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
+ if ((LanePrtcl >= SERDES_PRTCL_COUNT) || (LanePrtcl < NONE)) {
+ DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
+ } else if (LanePrtcl != NONE) {
+ SerDesLaneProbeCallback (LanePrtcl, Arg);
+ }
+ }
+}
+
+/**
+ Probe all serdes lanes for lane protocol and execute provided callback function.
+
+ @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
+ @param Arg Pointer to Arguments to be passed to callback function.
+
+**/
+VOID
+SerDesProbeLanes (
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ )
+{
+ SerDesInstanceProbeLanes (SRDS_1,
+ RCWSR_SRDS1_PRTCL_MASK,
+ RCWSR_SRDS1_PRTCL_SHIFT,
+ SerDesLaneProbeCallback,
+ Arg);
+
+ if (PcdGetBool (PcdSerdes2Enabled)) {
+ SerDesInstanceProbeLanes (SRDS_2,
+ RCWSR_SRDS2_PRTCL_MASK,
+ RCWSR_SRDS2_PRTCL_SHIFT,
+ SerDesLaneProbeCallback,
+ Arg);
+ }
+}
+
+/**
+ Function to return Serdes protocol map for all serdes available on board.
+
+ @param SerDesPrtclMap Pointer to Serdes protocl map.
+
+**/
+VOID
+GetSerdesProtocolMaps (
+ OUT UINT64 *SerDesPrtclMap
+ )
+{
+ LSSerDesMap (SRDS_1,
+ RCWSR_SRDS1_PRTCL_MASK,
+ RCWSR_SRDS1_PRTCL_SHIFT,
+ SerDesPrtclMap);
+
+ if (PcdGetBool (PcdSerdes2Enabled)) {
+ LSSerDesMap (SRDS_2,
+ RCWSR_SRDS2_PRTCL_MASK,
+ RCWSR_SRDS2_PRTCL_SHIFT,
+ SerDesPrtclMap);
+ }
+
+}
+
+BOOLEAN
+IsSerDesLaneProtocolConfigured (
+ IN UINT64 SerDesPrtclMap,
+ IN SERDES_PROTOCOL Device
+ )
+{
+ if ((Device >= SERDES_PRTCL_COUNT) || (Device < NONE)) {
+ ASSERT ((Device > NONE) && (Device < SERDES_PRTCL_COUNT));
+ DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device));
+ }
+
+ return (SerDesPrtclMap & (1u << Device)) != 0 ;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 04/41] Silicon/NXP : Add support for DUART library
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (2 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 03/41] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 05/41] Silicon/NXP: Add support for I2c driver Meenakshi Aggarwal
` (38 subsequent siblings)
42 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/NXP/Library/DUartPortLib/DUart.h | 128 ++++++++
Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 370 ++++++++++++++++++++++
Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 41 +++
3 files changed, 539 insertions(+)
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h b/Silicon/NXP/Library/DUartPortLib/DUart.h
new file mode 100644
index 0000000..3fa0a68
--- /dev/null
+++ b/Silicon/NXP/Library/DUartPortLib/DUart.h
@@ -0,0 +1,128 @@
+/** DUart.h
+* Header defining the DUART constants (Base addresses, sizes, flags)
+*
+* Based on Serial I/O Port library headers available in PL011Uart.h
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __DUART_H__
+#define __DUART_H__
+
+// FIFO Control Register
+#define DUART_FCR_FIFO_EN 0x01 /* Fifo enable */
+#define DUART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
+#define DUART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
+#define DUART_FCR_DMA_SELECT 0x08 /* For DMA applications */
+#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
+#define DUART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
+#define DUART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
+#define DUART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
+#define DUART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
+#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */
+#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */
+
+// Modem Control Register
+#define DUART_MCR_DTR 0x01 /* Reserved */
+#define DUART_MCR_RTS 0x02 /* RTS */
+#define DUART_MCR_OUT1 0x04 /* Reserved */
+#define DUART_MCR_OUT2 0x08 /* Reserved */
+#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define DUART_MCR_AFE 0x20 /* AFE (Auto Flow Control) */
+#define DUART_MCR_DMA_EN 0x04
+#define DUART_MCR_TX_DFR 0x08
+
+// Line Control Register
+/*
+* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting
+* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+*/
+#define DUART_LCR_WLS_MSK 0x03 /* character length select mask */
+#define DUART_LCR_WLS_5 0x00 /* 5 bit character length */
+#define DUART_LCR_WLS_6 0x01 /* 6 bit character length */
+#define DUART_LCR_WLS_7 0x02 /* 7 bit character length */
+#define DUART_LCR_WLS_8 0x03 /* 8 bit character length */
+#define DUART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
+#define DUART_LCR_PEN 0x08 /* Parity eneble */
+#define DUART_LCR_EPS 0x10 /* Even Parity Select */
+#define DUART_LCR_STKP 0x20 /* Stick Parity */
+#define DUART_LCR_SBRK 0x40 /* Set Break */
+#define DUART_LCR_BKSE 0x80 /* Bank select enable */
+#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */
+
+// Line Status Register
+#define DUART_LSR_DR 0x01 /* Data ready */
+#define DUART_LSR_OE 0x02 /* Overrun */
+#define DUART_LSR_PE 0x04 /* Parity error */
+#define DUART_LSR_FE 0x08 /* Framing error */
+#define DUART_LSR_BI 0x10 /* Break */
+#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */
+#define DUART_LSR_TEMT 0x40 /* Xmitter empty */
+#define DUART_LSR_ERR 0x80 /* Error */
+
+// Modem Status Register
+#define DUART_MSR_DCTS 0x01 /* Delta CTS */
+#define DUART_MSR_DDSR 0x02 /* Reserved */
+#define DUART_MSR_TERI 0x04 /* Reserved */
+#define DUART_MSR_DDCD 0x08 /* Reserved */
+#define DUART_MSR_CTS 0x10 /* Clear to Send */
+#define DUART_MSR_DSR 0x20 /* Reserved */
+#define DUART_MSR_RI 0x40 /* Reserved */
+#define DUART_MSR_DCD 0x80 /* Reserved */
+
+// Interrupt Identification Register
+#define DUART_IIR_NO_INT 0x01 /* No interrupts pending */
+#define DUART_IIR_ID 0x06 /* Mask for the interrupt ID */
+#define DUART_IIR_MSI 0x00 /* Modem status interrupt */
+#define DUART_IIR_THRI 0x02 /* Transmitter holding register empty */
+#define DUART_IIR_RDI 0x04 /* Receiver data interrupt */
+#define DUART_IIR_RLSI 0x06 /* Receiver line status interrupt */
+
+// Interrupt Enable Register
+#define DUART_IER_MSI 0x08 /* Enable Modem status interrupt */
+#define DUART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
+#define DUART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
+#define DUART_IER_RDI 0x01 /* Enable receiver data interrupt */
+
+// LCR defaults
+#define DUART_LCR_8N1 0x03
+#define DUART_LCRVAL DUART_LCR_8N1 /* 8 data, 1 stop, no parity */
+#define DUART_MCRVAL (DUART_MCR_DTR | \
+ DUART_MCR_RTS) /* RTS/DTR */
+#define DUART_FCRVAL (DUART_FCR_FIFO_EN | \
+ DUART_FCR_RXSR | \
+ DUART_FCR_TXSR) /* Clear & enable FIFOs */
+
+#define URBR 0x0
+#define UTHR 0x0
+#define UDLB 0x0
+#define UDMB 0x1
+#define UIER 0x1
+#define UIIR 0x2
+#define UFCR 0x2
+#define UAFR 0x2
+#define ULCR 0x3
+#define UMCR 0x4
+#define ULSR 0x5
+#define UMSR 0x6
+#define USCR 0x7
+#define UDSR 0x10
+
+extern
+UINT64
+GetBusFrequency (
+ VOID
+ );
+
+#endif /* __DUART_H__ */
diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
new file mode 100644
index 0000000..5fcfa9a
--- /dev/null
+++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
@@ -0,0 +1,370 @@
+/** DuartPortLib.c
+ DUART (NS16550) library functions
+
+ Based on Serial I/O Port library functions available in PL011SerialPortLib.c
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+
+#include "DUart.h"
+
+STATIC CONST UINT32 mInvalidControlBits = (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE | \
+ EFI_SERIAL_DATA_TERMINAL_READY);
+
+/**
+ Assert or deassert the control signals on a serial port.
+ The following control signals are set according their bit settings :
+ . Request to Send
+ . Data Terminal Ready
+
+ @param[in] Control The following bits are taken into account :
+ . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
+ "Request To Send" control signal if this bit is
+ equal to one/zero.
+ . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
+ the "Data Terminal Ready" control signal if this
+ bit is equal to one/zero.
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
+ the hardware loopback if this bit is equal to
+ one/zero.
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
+ disable the hardware flow control based on CTS (Clear
+ To Send) and RTS (Ready To Send) control signals.
+
+ @retval EFI_SUCCESS The new control bits were set on the device.
+ @retval EFI_UNSUPPORTED The device does not support this operation.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortSetControl (
+ IN UINT32 Control
+ )
+{
+ UINT32 McrBits;
+ UINTN UartBase;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ if (Control & (mInvalidControlBits)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ McrBits = MmioRead8 (UartBase + UMCR);
+
+ if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
+ McrBits |= DUART_MCR_RTS;
+ } else {
+ McrBits &= ~DUART_MCR_RTS;
+ }
+
+ if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {
+ McrBits |= DUART_MCR_LOOP;
+ } else {
+ McrBits &= ~DUART_MCR_LOOP;
+ }
+
+ if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
+ McrBits |= DUART_MCR_AFE;
+ } else {
+ McrBits &= ~DUART_MCR_AFE;
+ }
+
+ MmioWrite32 (UartBase + UMCR, McrBits);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Retrieve the status of the control bits on a serial device.
+
+ @param[out] Control Status of the control bits on a serial device :
+
+ . EFI_SERIAL_DATA_CLEAR_TO_SEND,
+ EFI_SERIAL_DATA_SET_READY,
+ EFI_SERIAL_RING_INDICATE,
+ EFI_SERIAL_CARRIER_DETECT,
+ EFI_SERIAL_REQUEST_TO_SEND,
+ EFI_SERIAL_DATA_TERMINAL_READY
+ are all related to the DTE (Data Terminal Equipment)
+ and DCE (Data Communication Equipment) modes of
+ operation of the serial device.
+ . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
+ receive buffer is empty, 0 otherwise.
+ . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
+ transmit buffer is empty, 0 otherwise.
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
+ the hardware loopback is enabled (the ouput feeds the
+ receive buffer), 0 otherwise.
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if
+ a loopback is accomplished by software, 0 otherwise.
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
+ one if the hardware flow control based on CTS (Clear
+ To Send) and RTS (Ready To Send) control signals is
+ enabled, 0 otherwise.
+
+ @retval EFI_SUCCESS The control bits were read from the serial device.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortGetControl (
+ OUT UINT32 *Control
+ )
+{
+ UINT32 MsrRegister;
+ UINT32 McrRegister;
+ UINT32 LsrRegister;
+ UINTN UartBase;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ MsrRegister = MmioRead8 (UartBase + UMSR);
+ McrRegister = MmioRead8 (UartBase + UMCR);
+ LsrRegister = MmioRead8 (UartBase + ULSR);
+
+ *Control = 0;
+
+ if ((MsrRegister & DUART_MSR_CTS) == DUART_MSR_CTS) {
+ *Control |= EFI_SERIAL_CLEAR_TO_SEND;
+ }
+
+ if ((McrRegister & DUART_MCR_RTS) == DUART_MCR_RTS) {
+ *Control |= EFI_SERIAL_REQUEST_TO_SEND;
+ }
+
+ if ((LsrRegister & DUART_LSR_TEMT) == DUART_LSR_TEMT) {
+ *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+ }
+
+ if ((McrRegister & DUART_MCR_AFE) == DUART_MCR_AFE) {
+ *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
+ }
+
+ if ((McrRegister & DUART_MCR_LOOP) == DUART_MCR_LOOP) {
+ *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/*
+ * Return Baud divisor on basis of Baudrate
+ */
+UINT32
+CalculateBaudDivisor (
+ IN UINT64 BaudRate
+ )
+{
+ UINTN DUartClk;
+ UINTN FreqSystemBus;
+
+ FreqSystemBus = GetBusFrequency ();
+ DUartClk = FreqSystemBus/PcdGet32(PcdPlatformFreqDiv);
+
+ return ((DUartClk)/(BaudRate * 16));
+}
+
+/*
+ Initialise the serial port to the specified settings.
+ All unspecified settings will be set to the default values.
+
+ @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER.
+
+ **/
+VOID
+EFIAPI
+DuartInitializePort (
+ IN UINT64 BaudRate
+ )
+{
+ UINTN UartBase;
+ UINT32 BaudDivisor;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+ BaudDivisor = CalculateBaudDivisor (BaudRate);
+
+
+ while (!(MmioRead8 (UartBase + ULSR) & DUART_LSR_TEMT));
+
+ //
+ // Enable and assert interrupt when new data is available on
+ // external device,
+ // setup data format, setup baud divisor
+ //
+ MmioWrite8 (UartBase + UIER, 0x1);
+ MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
+ MmioWrite8 (UartBase + UDLB, 0);
+ MmioWrite8 (UartBase + UDMB, 0);
+ MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
+ MmioWrite8 (UartBase + UMCR, DUART_MCRVAL);
+ MmioWrite8 (UartBase + UFCR, DUART_FCRVAL);
+ MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
+ MmioWrite8 (UartBase + UDLB, BaudDivisor & 0xff);
+ MmioWrite8 (UartBase + UDMB, (BaudDivisor >> 8) & 0xff);
+ MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
+
+ return;
+}
+
+/**
+ Programmed hardware of Serial port.
+
+ @return Always return EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ UINT64 BaudRate;
+ BaudRate = (UINTN)PcdGet64 (PcdUartDefaultBaudRate);
+
+
+ DuartInitializePort (BaudRate);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write data to serial device.
+
+ @param Buffer Point of data buffer which need to be written.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Write data failed.
+ @retval !0 Actual number of bytes written to serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
+{
+ UINT8 *Final;
+ UINTN UartBase;
+
+ Final = &Buffer[NumberOfBytes];
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ while (Buffer < Final) {
+ while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_THRE) == 0);
+ MmioWrite8 (UartBase + UTHR, *Buffer++);
+ }
+
+ return NumberOfBytes;
+}
+
+/**
+ Read data from serial device and save the data in buffer.
+
+ @param Buffer Point of data buffer which need to be written.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Read data failed.
+ @retval !0 Actual number of bytes read from serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
+{
+ UINTN Count;
+ UINTN UartBase;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
+ // Loop while waiting for a new char(s) to arrive in the
+ // RxFIFO
+ while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) == 0);
+
+ *Buffer = MmioRead8 (UartBase + URBR);
+ }
+
+ return NumberOfBytes;
+}
+
+/**
+ Check to see if any data is available to be read from the debug device.
+
+ @retval EFI_SUCCESS At least one byte of data is available to be read
+ @retval EFI_NOT_READY No data is available to be read
+ @retval EFI_DEVICE_ERROR The serial device is not functioning properly
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+ UINTN UartBase;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ return ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) != 0);
+}
+
+/**
+ Set new attributes to LS1043a.
+
+ @param BaudRate The baud rate of the serial device. If the baud rate is not supported,
+ the speed will be reduced down to the nearest supported one and the
+ variable's value will be updated accordingly.
+ @param ReceiveFifoDepth The number of characters the device will buffer on input. If the specified
+ value is not supported, the variable's value will be reduced down to the
+ nearest supported one.
+ @param Timeout If applicable, the number of microseconds the device will wait
+ before timing out a Read or a Write operation.
+ @param Parity If applicable, this is the EFI_PARITY_TYPE that is computed or checked
+ as each character is transmitted or received. If the device does not
+ support parity, the value is the default parity value.
+ @param DataBits The number of data bits in each character
+ @param StopBits If applicable, the EFI_STOP_BITS_TYPE number of stop bits per character.
+ If the device does not support stop bits, the value is the default stop
+ bit value.
+
+ @retval EFI_SUCCESS All attributes were set correctly on the serial device.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortSetAttributes (
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+ )
+{
+ DuartInitializePort (*BaudRate);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
new file mode 100644
index 0000000..6940de9
--- /dev/null
+++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
@@ -0,0 +1,41 @@
+# DUartPortLib.inf
+#
+# Component description file for DUartPortLib module
+#
+# Copyright (c) 2013, Freescale Ltd. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = DUartPortLib
+ FILE_GUID = c42dfe79-8de5-429e-a055-2d0a58591498
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialPortLib
+
+[Sources.common]
+ DUartPortLib.c
+
+[LibraryClasses]
+ PcdLib
+ SocLib
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 05/41] Silicon/NXP: Add support for I2c driver
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (3 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 04/41] Silicon/NXP : Add support for DUART library Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-18 17:25 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 06/41] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi Aggarwal
` (37 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
I2C driver produces gEfiI2cMasterProtocolGuid which can be
used by other modules.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Drivers/I2cDxe/ComponentName.c | 185 ++++++++
Silicon/NXP/Drivers/I2cDxe/DriverBinding.c | 241 ++++++++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 693 +++++++++++++++++++++++++++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 96 ++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 64 +++
5 files changed, 1279 insertions(+)
create mode 100644 Silicon/NXP/Drivers/I2cDxe/ComponentName.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
diff --git a/Silicon/NXP/Drivers/I2cDxe/ComponentName.c b/Silicon/NXP/Drivers/I2cDxe/ComponentName.c
new file mode 100644
index 0000000..efed6b9
--- /dev/null
+++ b/Silicon/NXP/Drivers/I2cDxe/ComponentName.c
@@ -0,0 +1,185 @@
+/** @file
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "I2cDxe.h"
+
+STATIC EFI_UNICODE_STRING_TABLE mNxpI2cDriverNameTable[] = {
+ {
+ "en",
+ (CHAR16 *)L"Nxp I2C Driver"
+ },
+ { }
+};
+
+STATIC EFI_UNICODE_STRING_TABLE mNxpI2cControllerNameTable[] = {
+ {
+ "en",
+ (CHAR16 *)L"Nxp I2C Controller"
+ },
+ { }
+};
+
+/**
+ Retrieves a Unicode string that is the user readable name of the driver.
+
+ This function retrieves the user readable name of a driver in the form of a
+ Unicode string. If the driver specified by This has a user readable name in
+ the language specified by Language, then a pointer to the driver name is
+ returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+ by This does not support the language specified by Language,
+ then EFI_UNSUPPORTED is returned.
+
+ @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+ EFI_COMPONENT_NAME_PROTOCOL instance.
+
+ @param Language[in] A pointer to a Null-terminated ASCII string
+ array indicating the language. This is the
+ language of the driver name that the caller is
+ requesting, and it must match one of the
+ languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up
+ to the driver writer. Language is specified
+ in RFC 4646 or ISO 639-2 language code format.
+
+ @param DriverName[out] A pointer to the Unicode string to return.
+ This Unicode string is the name of the
+ driver specified by This in the language
+ specified by Language.
+
+ @retval EFI_SUCCESS The Unicode string for the Driver specified by
+ This and the language specified by Language was
+ returned in DriverName.
+
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+
+ @retval EFI_INVALID_PARAMETER DriverName is NULL.
+
+ @retval EFI_UNSUPPORTED The driver specified by This does not support
+ the language specified by Language.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+NxpI2cGetDriverName (
+ IN EFI_COMPONENT_NAME2_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
+ )
+{
+ return LookupUnicodeString2 (Language,
+ This->SupportedLanguages,
+ mNxpI2cDriverNameTable,
+ DriverName,
+ FALSE);
+}
+
+/**
+ Retrieves a Unicode string that is the user readable name of the controller
+ that is being managed by a driver.
+
+ This function retrieves the user readable name of the controller specified by
+ ControllerHandle and ChildHandle in the form of a Unicode string. If the
+ driver specified by This has a user readable name in the language specified by
+ Language, then a pointer to the controller name is returned in ControllerName,
+ and EFI_SUCCESS is returned. If the driver specified by This is not currently
+ managing the controller specified by ControllerHandle and ChildHandle,
+ then EFI_UNSUPPORTED is returned. If the driver specified by This does not
+ support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+ @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+ EFI_COMPONENT_NAME_PROTOCOL instance.
+
+ @param ControllerHandle[in] The handle of a controller that the driver
+ specified by This is managing. This handle
+ specifies the controller whose name is to be
+ returned.
+
+ @param ChildHandle[in] The handle of the child controller to retrieve
+ the name of. This is an optional parameter that
+ may be NULL. It will be NULL for device
+ drivers. It will also be NULL for a bus drivers
+ that wish to retrieve the name of the bus
+ controller. It will not be NULL for a bus
+ driver that wishes to retrieve the name of a
+ child controller.
+
+ @param Language[in] A pointer to a Null-terminated ASCII string
+ array indicating the language. This is the
+ language of the driver name that the caller is
+ requesting, and it must match one of the
+ languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up
+ to the driver writer. Language is specified in
+ RFC 4646 or ISO 639-2 language code format.
+
+ @param ControllerName[out] A pointer to the Unicode string to return.
+ This Unicode string is the name of the
+ controller specified by ControllerHandle and
+ ChildHandle in the language specified by
+ Language from the point of view of the driver
+ specified by This.
+
+ @retval EFI_SUCCESS The Unicode string for the user readable name in
+ the language specified by Language for the
+ driver specified by This was returned in
+ DriverName.
+
+ @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
+
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+ EFI_HANDLE.
+
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+
+ @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+
+ @retval EFI_UNSUPPORTED The driver specified by This is not currently
+ managing the controller specified by
+ ControllerHandle and ChildHandle.
+
+ @retval EFI_UNSUPPORTED The driver specified by This does not support
+ the language specified by Language.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+NxpI2cGetControllerName (
+ IN EFI_COMPONENT_NAME2_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
+ )
+{
+ if (ChildHandle != NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ return LookupUnicodeString2 (Language,
+ This->SupportedLanguages,
+ mNxpI2cControllerNameTable,
+ ControllerName,
+ FALSE);
+}
+
+//
+// EFI Component Name 2 Protocol
+//
+EFI_COMPONENT_NAME2_PROTOCOL gNxpI2cDriverComponentName2 = {
+ NxpI2cGetDriverName,
+ NxpI2cGetControllerName,
+ "en"
+};
diff --git a/Silicon/NXP/Drivers/I2cDxe/DriverBinding.c b/Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
new file mode 100644
index 0000000..ad7a9f3
--- /dev/null
+++ b/Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
@@ -0,0 +1,241 @@
+/** @file
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD
+ License which accompanies this distribution. The full text of the license may
+ be found at http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/DriverBinding.h>
+
+#include "I2cDxe.h"
+
+/**
+ Tests to see if this driver supports a given controller.
+
+ @param This[in] A pointer to the EFI_DRIVER_BINDING_PROTOCOL
+ instance.
+ @param ControllerHandle[in] The handle of the controller to test.
+ @param RemainingDevicePath[in] The remaining device path.
+ (Ignored - this is not a bus driver.)
+
+ @retval EFI_SUCCESS The driver supports this controller.
+ @retval EFI_ALREADY_STARTED The device specified by ControllerHandle is
+ already being managed by the driver specified
+ by This.
+ @retval EFI_UNSUPPORTED The device specified by ControllerHandle is
+ not supported by the driver specified by This.
+
+**/
+EFI_STATUS
+EFIAPI
+NxpI2cDriverBindingSupported (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ )
+{
+ NON_DISCOVERABLE_DEVICE *Dev;
+ EFI_STATUS Status;
+
+ //
+ // Connect to the non-discoverable device
+ //
+ Status = gBS->OpenProtocol (ControllerHandle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ (VOID **) &Dev,
+ This->DriverBindingHandle,
+ ControllerHandle,
+ EFI_OPEN_PROTOCOL_BY_DRIVER);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (CompareGuid (Dev->Type, &gNxpNonDiscoverableI2cMasterGuid)) {
+ Status = EFI_SUCCESS;
+ } else {
+ Status = EFI_UNSUPPORTED;
+ }
+
+ //
+ // Clean up.
+ //
+ gBS->CloseProtocol (ControllerHandle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ This->DriverBindingHandle,
+ ControllerHandle);
+
+ return Status;
+}
+
+
+/**
+ Starts a device controller or a bus controller.
+
+ @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL
+ instance.
+ @param[in] ControllerHandle The handle of the device to start. This
+ handle must support a protocol interface that
+ supplies an I/O abstraction to the driver.
+ @param[in] RemainingDevicePath The remaining portion of the device path.
+ (Ignored - this is not a bus driver.)
+
+ @retval EFI_SUCCESS The device was started.
+ @retval EFI_DEVICE_ERROR The device could not be started due to a
+ device error.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
+ lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+NxpI2cDriverBindingStart (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL
+ )
+{
+ return NxpI2cInit (This->DriverBindingHandle, ControllerHandle);
+}
+
+
+/**
+ Stops a device controller or a bus controller.
+
+ @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL
+ instance.
+ @param[in] ControllerHandle A handle to the device being stopped. The handle
+ must support a bus specific I/O protocol for the
+ driver to use to stop the device.
+ @param[in] NumberOfChildren The number of child device handles in
+ ChildHandleBuffer.
+ @param[in] ChildHandleBuffer An array of child handles to be freed. May be
+ NULL if NumberOfChildren is 0.
+
+ @retval EFI_SUCCESS The device was stopped.
+ @retval EFI_DEVICE_ERROR The device could not be stopped due to a device
+ error.
+
+**/
+EFI_STATUS
+EFIAPI
+NxpI2cDriverBindingStop (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer OPTIONAL
+ )
+{
+ return NxpI2cRelease (This->DriverBindingHandle, ControllerHandle);
+}
+
+
+STATIC EFI_DRIVER_BINDING_PROTOCOL gNxpI2cDriverBinding = {
+ NxpI2cDriverBindingSupported,
+ NxpI2cDriverBindingStart,
+ NxpI2cDriverBindingStop,
+ 0xa,
+ NULL,
+ NULL
+};
+
+
+/**
+ The entry point of I2c UEFI Driver.
+
+ @param ImageHandle The image handle of the UEFI Driver.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The Driver or UEFI Driver exited normally.
+ @retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than
+ SystemTable->Hdr.Revision.
+
+**/
+EFI_STATUS
+EFIAPI
+I2cDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Add the driver to the list of drivers
+ //
+ Status = EfiLibInstallDriverBindingComponentName2 (
+ ImageHandle, SystemTable, &gNxpI2cDriverBinding, ImageHandle,
+ NULL, &gNxpI2cDriverComponentName2);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Unload function for the I2c UEFI Driver.
+
+ @param ImageHandle[in] The allocated handle for the EFI image
+
+ @retval EFI_SUCCESS The driver was unloaded successfully
+ @retval EFI_INVALID_PARAMETER ImageHandle is not a valid image handle.
+
+**/
+EFI_STATUS
+EFIAPI
+I2cDxeUnload (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ UINTN Index;
+
+ //
+ // Retrieve all USB I/O handles in the handle database
+ //
+ Status = gBS->LocateHandleBuffer (ByProtocol,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Disconnect the driver from the handles in the handle database
+ //
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->DisconnectController (HandleBuffer[Index],
+ gImageHandle,
+ NULL);
+ }
+
+ //
+ // Free the handle array
+ //
+ gBS->FreePool (HandleBuffer);
+
+ //
+ // Uninstall protocols installed by the driver in its entrypoint
+ //
+ Status = gBS->UninstallMultipleProtocolInterfaces (ImageHandle,
+ &gEfiDriverBindingProtocolGuid,
+ &gNxpI2cDriverBinding,
+ NULL
+ );
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
new file mode 100644
index 0000000..08aae72
--- /dev/null
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
@@ -0,0 +1,693 @@
+/** I2cDxe.c
+ I2c driver APIs for read, write, initialize, set speed and reset
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include "I2cDxe.h"
+
+STATIC CONST UINT16 ClkDiv[60][2] = {
+ { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
+ { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
+ { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
+ { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
+ { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
+ { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
+ { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
+ { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
+ { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
+ { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
+ { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
+ { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 },{ 1280, 0x35 },
+ { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
+ { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
+ { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
+};
+
+/**
+ Calculate and return proper clock divider
+
+ @param Rate clock rate
+
+ @retval ClkDiv Value used to get frequency divider value
+
+**/
+STATIC
+UINT8
+GetClkDiv (
+ IN UINT32 Rate
+ )
+{
+ UINTN ClkRate;
+ UINT32 Div;
+ UINT8 ClkDivx;
+
+ ClkRate = GetBusFrequency ();
+
+ Div = (ClkRate + Rate - 1) / Rate;
+
+ if (Div < ClkDiv[0][0]) {
+ ClkDivx = 0;
+ } else if (Div > ClkDiv[ARRAY_SIZE (ClkDiv) - 1][0]){
+ ClkDivx = ARRAY_SIZE (ClkDiv) - 1;
+ } else {
+ for (ClkDivx = 0; ClkDiv[ClkDivx][0] < Div; ClkDivx++);
+ }
+
+ return ClkDivx;
+}
+
+/**
+ Function used to check if i2c is in mentioned state or not
+
+ @param I2cRegs Pointer to I2C registers
+ @param State i2c state need to be checked
+
+ @retval EFI_NOT_READY Arbitration was lost
+ @retval EFI_TIMEOUT Timeout occured
+ @retval CurrState Value of state register
+
+**/
+STATIC
+EFI_STATUS
+WaitForI2cState (
+ IN I2C_REGS *I2cRegs,
+ IN UINT32 State
+ )
+{
+ UINT8 CurrState;
+ UINT64 Cnt;
+
+ for (Cnt = 0; Cnt < 50000; Cnt++) {
+ MemoryFence ();
+ CurrState = MmioRead8 ((UINTN)&I2cRegs->I2cSr);
+ if (CurrState & I2C_SR_IAL) {
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, CurrState | I2C_SR_IAL);
+ return EFI_NOT_READY;
+ }
+
+ if ((CurrState & (State >> 8)) == (UINT8)State) {
+ return CurrState;
+ }
+ }
+
+ return EFI_TIMEOUT;
+}
+
+/**
+ Function to transfer byte on i2c
+
+ @param I2cRegs Pointer to i2c registers
+ @param Byte Byte to be transferred on i2c bus
+
+ @retval EFI_NOT_READY Arbitration was lost
+ @retval EFI_TIMEOUT Timeout occured
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Data transfer was succesful
+
+**/
+STATIC
+EFI_STATUS
+TransferByte (
+ IN I2C_REGS *I2cRegs,
+ IN UINT8 Byte
+ )
+{
+ EFI_STATUS Ret;
+
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+ MmioWrite8 ((UINTN)&I2cRegs->I2cDr, Byte);
+
+ Ret = WaitForI2cState (I2cRegs, IIF);
+ if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
+ return Ret;
+ }
+
+ if (Ret & I2C_SR_RX_NO_AK) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to stop transaction on i2c bus
+
+ @param I2cRegs Pointer to i2c registers
+
+ @retval EFI_NOT_READY Arbitration was lost
+ @retval EFI_TIMEOUT Timeout occured
+ @retval EFI_SUCCESS Stop operation was successful
+
+**/
+STATIC
+EFI_STATUS
+I2cStop (
+ IN I2C_REGS *I2cRegs
+ )
+{
+ INT32 Ret;
+ UINT32 Temp;
+
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+
+ Temp &= ~(I2C_CR_MSTA | I2C_CR_MTX);
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+ Ret = WaitForI2cState (I2cRegs, BUS_IDLE);
+
+ if (Ret < 0) {
+ return Ret;
+ } else {
+ return EFI_SUCCESS;
+ }
+}
+
+/**
+ Function to send start signal, Chip Address and
+ memory offset
+
+ @param I2cRegs Pointer to i2c base registers
+ @param Chip Chip Address
+ @param Offset Slave memory's offset
+ @param Alen length of chip address
+
+ @retval EFI_NOT_READY Arbitration lost
+ @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Read was successful
+
+**/
+STATIC
+EFI_STATUS
+InitTransfer (
+ IN I2C_REGS *I2cRegs,
+ IN UINT8 Chip,
+ IN UINT32 Offset,
+ IN INT32 Alen
+ )
+{
+ UINT32 Temp;
+ EFI_STATUS Ret;
+
+ // Enable I2C controller
+ if (MmioRead8 ((UINTN)&I2cRegs->I2cCr) & I2C_CR_IDIS) {
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IEN);
+ }
+
+ if (MmioRead8 ((UINTN)&I2cRegs->I2cAdr) == (Chip << 1)) {
+ MmioWrite8 ((UINTN)&I2cRegs->I2cAdr, (Chip << 1) ^ 2);
+ }
+
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+ Ret = WaitForI2cState (I2cRegs, BUS_IDLE);
+ if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
+ return Ret;
+ }
+
+ // Start I2C transaction
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+ // set to master mode
+ Temp |= I2C_CR_MSTA;
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+ Ret = WaitForI2cState (I2cRegs, BUS_BUSY);
+ if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
+ return Ret;
+ }
+
+ Temp |= I2C_CR_MTX | I2C_CR_TX_NO_AK;
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+ // write slave Address
+ Ret = TransferByte (I2cRegs, Chip << 1);
+ if (Ret != EFI_SUCCESS) {
+ return Ret;
+ }
+
+ if (Alen >= 0) {
+ while (Alen--) {
+ Ret = TransferByte (I2cRegs, (Offset >> (Alen * 8)) & 0xff);
+ if (Ret != EFI_SUCCESS)
+ return Ret;
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to check if i2c bus is idle
+
+ @param Base Pointer to base address of I2c controller
+
+ @retval EFI_SUCCESS
+
+**/
+STATIC
+INT32
+I2cBusIdle (
+ IN VOID *Base
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to initiate data transfer on i2c bus
+
+ @param I2cRegs Pointer to i2c base registers
+ @param Chip Chip Address
+ @param Offset Slave memory's offset
+ @param Alen length of chip address
+
+ @retval EFI_NOT_READY Arbitration lost
+ @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Read was successful
+
+**/
+STATIC
+EFI_STATUS
+InitDataTransfer (
+ IN I2C_REGS *I2cRegs,
+ IN UINT8 Chip,
+ IN UINT32 Offset,
+ IN INT32 Alen
+ )
+{
+ EFI_STATUS Status;
+ INT32 Retry;
+
+ for (Retry = 0; Retry < 3; Retry++) {
+ Status = InitTransfer (I2cRegs, Chip, Offset, Alen);
+ if (Status == EFI_SUCCESS) {
+ return EFI_SUCCESS;
+ }
+
+ I2cStop (I2cRegs);
+
+ if (EFI_NOT_FOUND == Status) {
+ return Status;
+ }
+
+ // Disable controller
+ if (Status != EFI_NOT_READY) {
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
+ }
+
+ if (I2cBusIdle (I2cRegs) < 0) {
+ break;
+ }
+ }
+ return Status;
+}
+
+/**
+ Function to read data using i2c bus
+
+ @param BaseAddr I2c Controller Base Address
+ @param Chip Address of slave device from where data to be read
+ @param Offset Offset of slave memory
+ @param Alen Address length of slave
+ @param Buffer A pointer to the destination buffer for the data
+ @param Len Length of data to be read
+
+ @retval EFI_NOT_READY Arbitration lost
+ @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Read was successful
+
+**/
+STATIC
+EFI_STATUS
+I2cDataRead (
+ IN UINTN BaseAddr,
+ IN UINT8 Chip,
+ IN UINT32 Offset,
+ IN UINT32 Alen,
+ IN UINT8 *Buffer,
+ IN UINT32 Len
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Temp;
+ INT32 I;
+ I2C_REGS *I2cRegs;
+
+ I2cRegs = (I2C_REGS *)(BaseAddr);
+
+ Status = InitDataTransfer (I2cRegs, Chip, Offset, Alen);
+ if (Status != EFI_SUCCESS) {
+ return Status;
+ }
+
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+ Temp |= I2C_CR_RSTA;
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+ Status = TransferByte (I2cRegs, (Chip << 1) | 1);
+ if (Status != EFI_SUCCESS) {
+ I2cStop (I2cRegs);
+ return Status;
+ }
+
+ // setup bus to read data
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+ Temp &= ~(I2C_CR_MTX | I2C_CR_TX_NO_AK);
+ if (Len == 1) {
+ Temp |= I2C_CR_TX_NO_AK;
+ }
+
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+
+ // Dummy Read to initiate recieve operation
+ MmioRead8 ((UINTN)&I2cRegs->I2cDr);
+
+ for (I = 0; I < Len; I++) {
+ Status = WaitForI2cState (I2cRegs, IIF);
+ if ((Status == EFI_TIMEOUT) || (Status == EFI_NOT_READY)) {
+ I2cStop (I2cRegs);
+ return Status;
+ }
+ //
+ // It must generate STOP before read I2DR to prevent
+ // controller from generating another clock cycle
+ //
+ if (I == (Len - 1)) {
+ I2cStop (I2cRegs);
+ } else if (I == (Len - 2)) {
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+ Temp |= I2C_CR_TX_NO_AK;
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+ }
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+ Buffer[I] = MmioRead8 ((UINTN)&I2cRegs->I2cDr);
+ }
+
+ I2cStop (I2cRegs);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to write data using i2c bus
+
+ @param BaseAddr I2c Controller Base Address
+ @param Chip Address of slave device where data to be written
+ @param Offset Offset of slave memory
+ @param Alen Address length of slave
+ @param Buffer A pointer to the source buffer for the data
+ @param Len Length of data to be write
+
+ @retval EFI_NOT_READY Arbitration lost
+ @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Read was successful
+
+**/
+STATIC
+EFI_STATUS
+I2cDataWrite (
+ IN UINTN BaseAddr,
+ IN UINT8 Chip,
+ IN UINT32 Offset,
+ IN INT32 Alen,
+ OUT UINT8 *Buffer,
+ IN INT32 Len
+ )
+{
+ EFI_STATUS Status;
+ I2C_REGS *I2cRegs;
+ INT32 I;
+
+ I2cRegs = (I2C_REGS *)BaseAddr;
+
+ Status = InitDataTransfer (I2cRegs, Chip, Offset, Alen);
+ if (Status != EFI_SUCCESS) {
+ return Status;
+ }
+
+ // Write operation
+ for (I = 0; I < Len; I++) {
+ Status = TransferByte (I2cRegs, Buffer[I]);
+ if (Status != EFI_SUCCESS) {
+ break;
+ }
+ }
+
+ I2cStop (I2cRegs);
+ return Status;
+}
+
+/**
+ Function to set i2c bus frequency
+
+ @param This Pointer to I2c master protocol
+ @param BusClockHertz value to be set
+
+ @retval EFI_SUCCESS Operation successfull
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+SetBusFrequency (
+ IN CONST EFI_I2C_MASTER_PROTOCOL *This,
+ IN OUT UINTN *BusClockHertz
+ )
+{
+ I2C_REGS *I2cRegs;
+ UINT8 ClkId;
+ UINT8 SpeedId;
+ NXP_I2C_MASTER *I2c;
+
+ I2c = NXP_I2C_FROM_THIS (This);
+
+ I2cRegs = (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin);
+
+ ClkId = GetClkDiv (*BusClockHertz);
+ SpeedId = ClkDiv[ClkId][1];
+
+ // Store divider value
+ MmioWrite8 ((UINTN)&I2cRegs->I2cFdr, SpeedId);
+
+ MemoryFence ();
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to reset I2c Controller
+
+ @param This Pointer to I2c master protocol
+
+ @return EFI_SUCCESS Operation successfull
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+Reset (
+ IN CONST EFI_I2C_MASTER_PROTOCOL *This
+ )
+{
+ I2C_REGS *I2cRegs;
+ NXP_I2C_MASTER *I2c;
+
+ I2c = NXP_I2C_FROM_THIS (This);
+
+ I2cRegs = (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin);
+
+ // Reset module
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, 0);
+
+ MemoryFence ();
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+StartRequest (
+ IN CONST EFI_I2C_MASTER_PROTOCOL *This,
+ IN UINTN SlaveAddress,
+ IN EFI_I2C_REQUEST_PACKET *RequestPacket,
+ IN EFI_EVENT Event OPTIONAL,
+ OUT EFI_STATUS *I2cStatus OPTIONAL
+ )
+{
+ NXP_I2C_MASTER *I2c;
+ UINT32 Count;
+ INT32 Ret;
+ UINT32 Length;
+ UINT8 *Buffer;
+ UINT32 Flag;
+ UINT32 RegAddress;
+ UINT32 OffsetLength;
+
+ RegAddress = 0;
+
+ I2c = NXP_I2C_FROM_THIS (This);
+
+ if (RequestPacket->OperationCount <= 0) {
+ DEBUG ((DEBUG_ERROR,"%a: Operation count is not valid %d\n",
+ __FUNCTION__, RequestPacket->OperationCount));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ OffsetLength = RequestPacket->Operation[0].LengthInBytes;
+ RegAddress = *RequestPacket->Operation[0].Buffer;
+
+ for (Count = 1; Count < RequestPacket->OperationCount; Count++) {
+ Flag = RequestPacket->Operation[Count].Flags;
+ Length = RequestPacket->Operation[Count].LengthInBytes;
+ Buffer = RequestPacket->Operation[Count].Buffer;
+
+ if (Length <= 0) {
+ DEBUG ((DEBUG_ERROR,"%a: Invalid length of buffer %d\n",
+ __FUNCTION__, Length));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (Flag == I2C_FLAG_READ) {
+ Ret = I2cDataRead (I2c->Dev->Resources[0].AddrRangeMin, SlaveAddress,
+ RegAddress, OffsetLength, Buffer, Length);
+ if (Ret != EFI_SUCCESS) {
+ DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n",
+ __FUNCTION__, Ret));
+ return Ret;
+ }
+ } else if (Flag == I2C_FLAG_WRITE) {
+ Ret = I2cDataWrite (I2c->Dev->Resources[0].AddrRangeMin, SlaveAddress,
+ RegAddress, OffsetLength, Buffer, Length);
+ if (Ret != EFI_SUCCESS) {
+ DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n",
+ __FUNCTION__, Ret));
+ return Ret;
+ }
+ } else {
+ DEBUG ((DEBUG_ERROR,"%a: Invalid Flag %d\n",
+ __FUNCTION__, Flag));
+ return EFI_INVALID_PARAMETER;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+STATIC CONST EFI_I2C_CONTROLLER_CAPABILITIES I2cControllerCapabilities = {
+ 0,
+ 0,
+ 0,
+ 0
+};
+
+EFI_STATUS
+NxpI2cInit (
+ IN EFI_HANDLE DriverBindingHandle,
+ IN EFI_HANDLE ControllerHandle
+ )
+{
+ EFI_STATUS Status;
+ NON_DISCOVERABLE_DEVICE *Dev;
+ NXP_I2C_MASTER *I2c;
+
+ Status = gBS->OpenProtocol (ControllerHandle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ (VOID **)&Dev, DriverBindingHandle,
+ ControllerHandle, EFI_OPEN_PROTOCOL_BY_DRIVER);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ I2c = AllocateZeroPool (sizeof (NXP_I2C_MASTER));
+
+ I2c->Signature = NXP_I2C_SIGNATURE;
+ I2c->I2cMaster.SetBusFrequency = SetBusFrequency;
+ I2c->I2cMaster.Reset = Reset;
+ I2c->I2cMaster.StartRequest = StartRequest;
+ I2c->I2cMaster.I2cControllerCapabilities = &I2cControllerCapabilities;
+ I2c->Dev = Dev;
+
+ CopyGuid (&I2c->DevicePath.Vendor.Guid, &gEfiCallerIdGuid);
+ I2c->DevicePath.MmioBase = I2c->Dev->Resources[0].AddrRangeMin;
+ SetDevicePathNodeLength (&I2c->DevicePath.Vendor,
+ sizeof (I2c->DevicePath) - sizeof (I2c->DevicePath.End));
+ SetDevicePathEndNode (&I2c->DevicePath.End);
+
+ Status = gBS->InstallMultipleProtocolInterfaces (&ControllerHandle,
+ &gEfiI2cMasterProtocolGuid, (VOID**)&I2c->I2cMaster,
+ &gEfiDevicePathProtocolGuid, &I2c->DevicePath,
+ NULL);
+
+ if (EFI_ERROR (Status)) {
+ FreePool (I2c);
+ gBS->CloseProtocol (ControllerHandle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ DriverBindingHandle,
+ ControllerHandle);
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+NxpI2cRelease (
+ IN EFI_HANDLE DriverBindingHandle,
+ IN EFI_HANDLE ControllerHandle
+ )
+{
+ EFI_I2C_MASTER_PROTOCOL *I2cMaster;
+ EFI_STATUS Status;
+ NXP_I2C_MASTER *I2c;
+
+ Status = gBS->HandleProtocol (ControllerHandle,
+ &gEfiI2cMasterProtocolGuid,
+ (VOID **)&I2cMaster);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ I2c = NXP_I2C_FROM_THIS (I2cMaster);
+
+ Status = gBS->UninstallMultipleProtocolInterfaces (ControllerHandle,
+ &gEfiI2cMasterProtocolGuid, I2cMaster,
+ &gEfiDevicePathProtocolGuid, &I2c->DevicePath,
+ NULL);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = gBS->CloseProtocol (ControllerHandle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ DriverBindingHandle,
+ ControllerHandle);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ gBS->FreePool (I2c);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
new file mode 100644
index 0000000..01eeca4
--- /dev/null
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
@@ -0,0 +1,96 @@
+/** I2cDxe.h
+ Header defining the constant, base address amd function for I2C controller
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __I2C_DXE_H__
+#define __I2C_DXE_H__
+
+#include <Library/UefiLib.h>
+#include <Uefi.h>
+
+#include <Protocol/I2cMaster.h>
+#include <Protocol/NonDiscoverableDevice.h>
+
+#define I2C_CR_IIEN (1 << 6)
+#define I2C_CR_MSTA (1 << 5)
+#define I2C_CR_MTX (1 << 4)
+#define I2C_CR_TX_NO_AK (1 << 3)
+#define I2C_CR_RSTA (1 << 2)
+
+#define I2C_SR_ICF (1 << 7)
+#define I2C_SR_IBB (1 << 5)
+#define I2C_SR_IAL (1 << 4)
+#define I2C_SR_IIF (1 << 1)
+#define I2C_SR_RX_NO_AK (1 << 0)
+
+#define I2C_CR_IEN (0 << 7)
+#define I2C_CR_IDIS (1 << 7)
+#define I2C_SR_IIF_CLEAR (1 << 1)
+
+#define BUS_IDLE (0 | (I2C_SR_IBB << 8))
+#define BUS_BUSY (I2C_SR_IBB | (I2C_SR_IBB << 8))
+#define IIF (I2C_SR_IIF | (I2C_SR_IIF << 8))
+
+#define I2C_FLAG_WRITE 0x0
+
+#define NXP_I2C_SIGNATURE SIGNATURE_32 ('N', 'I', '2', 'C')
+#define NXP_I2C_FROM_THIS(a) CR ((a), NXP_I2C_MASTER, \
+ I2cMaster, NXP_I2C_SIGNATURE)
+extern EFI_COMPONENT_NAME2_PROTOCOL gNxpI2cDriverComponentName2;
+
+#pragma pack(1)
+typedef struct {
+ VENDOR_DEVICE_PATH Vendor;
+ UINT64 MmioBase;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} NXP_I2C_DEVICE_PATH;
+#pragma pack()
+
+typedef struct {
+ UINT32 Signature;
+ EFI_I2C_MASTER_PROTOCOL I2cMaster;
+ NXP_I2C_DEVICE_PATH DevicePath;
+ NON_DISCOVERABLE_DEVICE *Dev;
+} NXP_I2C_MASTER;
+
+/**
+ Record defining i2c registers
+**/
+typedef struct {
+ UINT8 I2cAdr;
+ UINT8 I2cFdr;
+ UINT8 I2cCr;
+ UINT8 I2cSr;
+ UINT8 I2cDr;
+} I2C_REGS ;
+
+extern
+UINT64
+GetBusFrequency (
+ VOID
+ );
+
+EFI_STATUS
+NxpI2cInit (
+ IN EFI_HANDLE DriverBindingHandle,
+ IN EFI_HANDLE ControllerHandle
+ );
+
+EFI_STATUS
+NxpI2cRelease (
+ IN EFI_HANDLE DriverBindingHandle,
+ IN EFI_HANDLE ControllerHandle
+ );
+
+#endif
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
new file mode 100644
index 0000000..0691362
--- /dev/null
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -0,0 +1,64 @@
+# @file
+#
+# Component description file for I2c driver
+#
+# Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = I2cDxe
+ FILE_GUID = 5f2927ba-1b04-4d5f-8bef-2b50c635d1e7
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = I2cDxeEntryPoint
+ UNLOAD = I2cDxeUnload
+
+[Sources.common]
+ ComponentName.c
+ DriverBinding.c
+ I2cDxe.c
+
+[LibraryClasses]
+ ArmLib
+ BaseMemoryLib
+ DevicePathLib
+ IoLib
+ MemoryAllocationLib
+ PcdLib
+ SocLib
+ TimerLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Guids]
+ gNxpNonDiscoverableI2cMasterGuid
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[Protocols]
+ gEdkiiNonDiscoverableDeviceProtocolGuid ## TO_START
+ gEfiI2cMasterProtocolGuid ## BY_START
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
+
+[Depex]
+ TRUE
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 06/41] Silicon/Maxim : Add support for DS1307 RTC library
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (4 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 05/41] Silicon/NXP: Add support for I2c driver Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 07/41] Platform/NXP: Add support for ArmPlatformLib Meenakshi Aggarwal
` (36 subsequent siblings)
42 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Real time clock Apis on top of I2C Apis
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h | 54 +++
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 378 +++++++++++++++++++++
.../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec | 29 ++
.../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf | 45 +++
4 files changed, 506 insertions(+)
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
new file mode 100644
index 0000000..3fad7fa
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
@@ -0,0 +1,54 @@
+/** Ds1307Rtc.h
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __DS1307RTC_H__
+#define __DS1307RTC_H__
+
+/*
+ * RTC time register
+ */
+#define DS1307_SEC_REG_ADDR 0x00
+#define DS1307_MIN_REG_ADDR 0x01
+#define DS1307_HR_REG_ADDR 0x02
+#define DS1307_DAY_REG_ADDR 0x03
+#define DS1307_DATE_REG_ADDR 0x04
+#define DS1307_MON_REG_ADDR 0x05
+#define DS1307_YR_REG_ADDR 0x06
+
+#define DS1307_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
+
+/*
+ * RTC control register
+ */
+#define DS1307_CTL_REG_ADDR 0x07
+
+#define START_YEAR 1970
+#define END_YEAR 2070
+
+/*
+ * TIME MASKS
+ */
+#define MASK_SEC 0x7F
+#define MASK_MIN 0x7F
+#define MASK_HOUR 0x3F
+#define MASK_DAY 0x3F
+#define MASK_MONTH 0x1F
+
+typedef struct {
+ UINTN OperationCount;
+ EFI_I2C_OPERATION SetAddressOp;
+ EFI_I2C_OPERATION GetSetDateTimeOp;
+} RTC_I2C_REQUEST;
+
+#endif // __DS1307RTC_H__
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
new file mode 100644
index 0000000..53878ba
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
@@ -0,0 +1,378 @@
+/** Ds1307RtcLib.c
+ Implement EFI RealTimeClock via RTC Lib for DS1307 RTC.
+
+ Based on RTC implementation available in
+ EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/I2cMaster.h>
+
+#include "Ds1307Rtc.h"
+
+STATIC VOID *mDriverEventRegistration;
+STATIC EFI_HANDLE mI2cMasterHandle;
+STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
+
+/**
+ Read RTC register.
+
+ @param RtcRegAddr Register offset of RTC to be read.
+
+ @retval Register Value read
+
+**/
+
+STATIC
+UINT8
+RtcRead (
+ IN UINT8 RtcRegAddr
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+ UINT8 Val;
+
+ Val = 0;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
+ }
+
+ return Val;
+}
+
+/**
+ Write RTC register.
+
+ @param RtcRegAddr Register offset of RTC to write.
+ @param Val Value to be written
+
+**/
+
+STATIC
+VOID
+RtcWrite (
+ IN UINT8 RtcRegAddr,
+ IN UINT8 Val
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = 0;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
+ }
+}
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+
+**/
+
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Second;
+ UINT8 Minute;
+ UINT8 Hour;
+ UINT8 Day;
+ UINT8 Month;
+ UINT8 Year;
+
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ Status = EFI_SUCCESS;
+
+ Second = RtcRead (DS1307_SEC_REG_ADDR);
+ Minute = RtcRead (DS1307_MIN_REG_ADDR);
+ Hour = RtcRead (DS1307_HR_REG_ADDR);
+ Day = RtcRead (DS1307_DATE_REG_ADDR);
+ Month = RtcRead (DS1307_MON_REG_ADDR);
+ Year = RtcRead (DS1307_YR_REG_ADDR);
+
+ if (Second & DS1307_SEC_BIT_CH) {
+ DEBUG ((DEBUG_ERROR, "### Warning: RTC oscillator has stopped\n"));
+ /* clear the CH flag */
+ RtcWrite (DS1307_SEC_REG_ADDR,
+ RtcRead (DS1307_SEC_REG_ADDR) & ~DS1307_SEC_BIT_CH);
+ Status = EFI_DEVICE_ERROR;
+ }
+
+ Time->Second = BcdToDecimal8 (Second & MASK_SEC);
+ Time->Minute = BcdToDecimal8 (Minute & MASK_MIN);
+ Time->Hour = BcdToDecimal8 (Hour & MASK_HOUR);
+ Time->Day = BcdToDecimal8 (Day & MASK_DAY);
+ Time->Month = BcdToDecimal8 (Month & MASK_MONTH);
+
+ //
+ // RTC can save year 1970 to 2069
+ // On writing Year, save year % 100
+ // On Reading reversing the operation e.g. 2012
+ // write = 12 (2012 % 100)
+ // read = 2012 (12 + 2000)
+ //
+ Time->Year = BcdToDecimal8 (Year) +
+ (BcdToDecimal8 (Year) >= 70 ? START_YEAR - 70 : END_YEAR -70);
+
+ return Status;
+}
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ if (Time->Year < START_YEAR || Time->Year >= END_YEAR){
+ DEBUG ((DEBUG_ERROR, "WARNING: Year should be between 1970 and 2069!\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ RtcWrite (DS1307_YR_REG_ADDR, DecimalToBcd8 (Time->Year % 100));
+ RtcWrite (DS1307_MON_REG_ADDR, DecimalToBcd8 (Time->Month));
+ RtcWrite (DS1307_DATE_REG_ADDR, DecimalToBcd8 (Time->Day));
+ RtcWrite (DS1307_HR_REG_ADDR, DecimalToBcd8 (Time->Hour));
+ RtcWrite (DS1307_MIN_REG_ADDR, DecimalToBcd8 (Time->Minute));
+ RtcWrite (DS1307_SEC_REG_ADDR, DecimalToBcd8 (Time->Second));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this
+ platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // The DS1307 does not support setting the alarm
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // The DS1307 does not support setting the alarm
+ return EFI_UNSUPPORTED;
+}
+
+STATIC
+VOID
+I2cDriverRegistrationEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_I2C_MASTER_PROTOCOL *I2cMaster;
+ UINTN BusFrequency;
+ EFI_HANDLE Handle;
+ UINTN BufferSize;
+
+ //
+ // Try to connect the newly registered driver to our handle.
+ //
+ do {
+ BufferSize = sizeof (EFI_HANDLE);
+ Status = gBS->LocateHandle (ByRegisterNotify,
+ &gEfiI2cMasterProtocolGuid,
+ mDriverEventRegistration,
+ &BufferSize,
+ &Handle);
+ if (EFI_ERROR (Status)) {
+ if (Status != EFI_NOT_FOUND) {
+ DEBUG ((DEBUG_WARN, "%a: gBS->LocateHandle () returned %r\n",
+ __FUNCTION__, Status));
+ }
+ break;
+ }
+
+ if (Handle != mI2cMasterHandle) {
+ continue;
+ }
+
+ DEBUG ((DEBUG_INFO, "%a: found I2C master!\n", __FUNCTION__));
+
+ gBS->CloseEvent (Event);
+
+ Status = gBS->OpenProtocol (mI2cMasterHandle, &gEfiI2cMasterProtocolGuid,
+ (VOID **)&I2cMaster, gImageHandle, NULL,
+ EFI_OPEN_PROTOCOL_EXCLUSIVE);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = I2cMaster->Reset (I2cMaster);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
+ __FUNCTION__, Status));
+ break;
+ }
+
+ BusFrequency = FixedPcdGet16 (PcdI2cBusFrequency);
+ Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
+ __FUNCTION__, Status));
+ break;
+ }
+
+ mI2cMaster = I2cMaster;
+ break;
+ } while (TRUE);
+
+ return;
+}
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+
+ //
+ // Find the handle that marks the controller
+ // that will provide the I2C master protocol.
+ //
+ BufferSize = sizeof (EFI_HANDLE);
+ Status = gBS->LocateHandle (
+ ByProtocol,
+ &gDs1307RealTimeClockLibI2cMasterProtocolGuid,
+ NULL,
+ &BufferSize,
+ &mI2cMasterHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register a protocol registration notification callback on the driver
+ // binding protocol so we can attempt to connect our I2C master to it
+ // as soon as it appears.
+ //
+ EfiCreateProtocolNotifyEvent (
+ &gEfiI2cMasterProtocolGuid,
+ TPL_CALLBACK,
+ I2cDriverRegistrationEvent,
+ NULL,
+ &mDriverEventRegistration);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
new file mode 100644
index 0000000..c8935f6
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
@@ -0,0 +1,29 @@
+#/** @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+ PACKAGE_NAME = Ds1307RtcLib
+ PACKAGE_GUID = 0c095cf6-834d-4fa2-a5a0-31ac35591ad2
+ PACKAGE_VERSION = 0.1
+
+[Guids]
+ gDs1307RtcLibTokenSpaceGuid = { 0xd939eb84, 0xa95a, 0x46a0, { 0xa8, 0x2b, 0xb9, 0x64, 0x30, 0xcf, 0xf5, 0x99 }}
+
+[Protocols]
+ gDs1307RealTimeClockLibI2cMasterProtocolGuid = { 0xd37c4d54, 0x1bca, 0x49e0, { 0xa0, 0x4a, 0x5c, 0x37, 0x59, 0x38, 0xc7, 0xec}}
+
+[PcdsFixedAtBuild]
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
new file mode 100644
index 0000000..71dc8c5
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
@@ -0,0 +1,45 @@
+# @Ds1307RtcLib.inf
+#
+# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Ds1307RtcLib
+ FILE_GUID = 7112fb46-8dda-4a41-ac40-bf212fedfc08
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+[Sources.common]
+ Ds1307RtcLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
+
+[LibraryClasses]
+ DebugLib
+ UefiBootServicesTableLib
+ UefiLib
+
+[Protocols]
+ gEfiI2cMasterProtocolGuid ## CONSUMES
+ gDs1307RealTimeClockLibI2cMasterProtocolGuid ## CONSUMES
+
+[FixedPcd]
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency
+
+[Depex]
+ gDs1307RealTimeClockLibI2cMasterProtocolGuid
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 07/41] Platform/NXP: Add support for ArmPlatformLib
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (5 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 06/41] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 08/41] Platform/NXP: Add Platform driver for LS1043 RDB board Meenakshi Aggarwal
` (35 subsequent siblings)
42 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
.../Library/PlatformLib/ArmPlatformLib.c | 105 ++++++++++++++
.../Library/PlatformLib/ArmPlatformLib.inf | 67 +++++++++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 38 ++++++
.../Library/PlatformLib/NxpQoriqLsMem.c | 152 +++++++++++++++++++++
4 files changed, 362 insertions(+)
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 0000000..ab4815d
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,105 @@
+/** ArmPlatformLib.c
+*
+* Contains board initialization functions.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+extern VOID SocInit (VOID);
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Placeholder for Platform Initialization
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = sizeof (LS1043aMpCoreInfoCTA53x4) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = LS1043aMpCoreInfoCTA53x4;
+
+ return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+ IN UINTN MpId
+ )
+{
+ return 1;
+}
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 0000000..7feac56
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,67 @@
+# @file
+#
+# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformLib
+ FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ArmLib
+ SocLib
+
+[Sources.common]
+ NxpQoriqLsHelper.S | GCC
+ NxpQoriqLsMem.c
+ ArmPlatformLib.c
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
new file mode 100644
index 0000000..205c0d8
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
@@ -0,0 +1,38 @@
+# @file
+#
+# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_IMPORT(ArmReadMpidr)
+
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ tst x0, #3
+ cset x0, eq
+ ret
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+EL1_OR_EL2(x0)
+1:
+2:
+ ret
+
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
+ ldrh w0, [x0]
+ ret
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
new file mode 100644
index 0000000..64c5612
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -0,0 +1,152 @@
+/** NxpQoriqLsMem.c
+*
+* Board memory specific Library.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
+ )
+{
+ UINTN Index;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ Index = 0;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
+ EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ // DRAM1 (Must be 1st entry)
+ VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // CCSR Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IFC region 1
+ //
+ // A-009241 : Unaligned write transactions to IFC may result in corruption of data
+ // Affects : IFC
+ // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
+ // writes on external IFC interface that can corrupt data on external flash.
+ // Impact : Data corruption on external flash may happen in case of unaligned writes to
+ // IFC memory space.
+ // Workaround: Following are the workarounds:
+ // For write transactions from core, IFC interface memories (including IFC SRAM)
+ // should be configured as device type memory in MMU.
+ // For write transactions from non-core masters (like system DMA), the address
+ // should be 16 byte aligned and the data size should be multiple of 16 bytes.
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // QMAN SWP
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // BMAN SWP
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // IFC region 2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DRAM2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // PCIe1
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe3
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DRAM3
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram3BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram3BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram3Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // QSPI region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 08/41] Platform/NXP: Add Platform driver for LS1043 RDB board
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (6 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 07/41] Platform/NXP: Add support for ArmPlatformLib Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-18 17:47 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 09/41] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
` (34 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../Drivers/PlatformDxe/PlatformDxe.c | 119 +++++++++++++++++++++
.../Drivers/PlatformDxe/PlatformDxe.inf | 58 ++++++++++
2 files changed, 177 insertions(+)
create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
new file mode 100644
index 0000000..7ce7318
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -0,0 +1,119 @@
+/** @file
+ LS1043 DXE platform driver.
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/NonDiscoverableDevice.h>
+
+typedef struct {
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR StartDesc;
+ UINT8 EndDesc;
+} ADDRESS_SPACE_DESCRIPTOR;
+
+STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
+
+STATIC
+EFI_STATUS
+RegisterDevice (
+ IN EFI_GUID *TypeGuid,
+ IN ADDRESS_SPACE_DESCRIPTOR *Desc,
+ OUT EFI_HANDLE *Handle
+ )
+{
+ NON_DISCOVERABLE_DEVICE *Device;
+ EFI_STATUS Status;
+
+ Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device));
+ if (Device == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Device->Type = TypeGuid;
+ Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent;
+ Device->Resources = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Desc;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (Handle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid, Device,
+ NULL);
+ if (EFI_ERROR (Status)) {
+ goto FreeDevice;
+ }
+ return EFI_SUCCESS;
+
+FreeDevice:
+ FreePool (Device);
+
+ return Status;
+}
+
+VOID
+PopulateI2cInformation (
+ IN VOID
+ )
+{
+ UINT32 Index;
+
+ for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
+ mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+ mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
+ mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ mI2cDesc[Index].StartDesc.GenFlag = 0;
+ mI2cDesc[Index].StartDesc.SpecificFlag = 0;
+ mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
+ mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
+ (Index * FixedPcdGet32 (PcdI2cSize));
+ mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
+ FixedPcdGet32 (PcdI2cSize) - 1;
+ mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
+ mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
+
+ mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
+ }
+}
+
+EFI_STATUS
+EFIAPI
+PlatformDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ Handle = NULL;
+
+ PopulateI2cInformation ();
+
+ Status = RegisterDevice (&gNxpNonDiscoverableI2cMasterGuid,
+ &mI2cDesc[0], &Handle);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install the DS1307 I2C Master protocol on this handle so the RTC driver
+ // can identify it as the I2C master it can invoke directly.
+ //
+ Status = gBS->InstallProtocolInterface (&Handle,
+ &gDs1307RealTimeClockLibI2cMasterProtocolGuid,
+ EFI_NATIVE_INTERFACE, NULL);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
new file mode 100644
index 0000000..91d6ad3
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -0,0 +1,58 @@
+## @file
+#
+# Component description file for LS1043 DXE platform driver.
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformDxe
+ FILE_GUID = 21108101-adcd-4123-930e-a2354a554db7
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PlatformDxeEntryPoint
+
+[Sources]
+ PlatformDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ MemoryAllocationLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Guids]
+ gNxpNonDiscoverableI2cMasterGuid
+
+[Protocols]
+ gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
+ gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES
+
+[FixedPcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
+
+[Depex]
+ TRUE
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 09/41] Compilation : Add the fdf, dsc and dec files.
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (7 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 08/41] Platform/NXP: Add Platform driver for LS1043 RDB board Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-18 18:35 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 10/41] Readme : Add Readme.md file Meenakshi Aggarwal
` (33 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
The firmware device, description and declaration files.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/FVRules.fdf.inc | 99 +++++++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 29 ++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 80 ++++++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 198 +++++++++++++
Platform/NXP/NxpQoriqLs.dsc.inc | 412 +++++++++++++++++++++++++++
Silicon/NXP/LS1043A/LS1043A.dec | 22 ++
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 73 +++++
Silicon/NXP/NxpQoriqLs.dec | 117 ++++++++
8 files changed, 1030 insertions(+)
create mode 100644 Platform/NXP/FVRules.fdf.inc
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
create mode 100644 Platform/NXP/NxpQoriqLs.dsc.inc
create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc.inc
create mode 100644 Silicon/NXP/NxpQoriqLs.dec
diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc
new file mode 100644
index 0000000..d0e17cb
--- /dev/null
+++ b/Platform/NXP/FVRules.fdf.inc
@@ -0,0 +1,99 @@
+# FvRules.fdf.inc
+#
+# Rules for creating FD.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
new file mode 100644
index 0000000..1b639e2
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
@@ -0,0 +1,29 @@
+# LS1043aRdbPkg.dec
+# LS1043a board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ PACKAGE_NAME = LS1043aRdbPkg
+ PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
new file mode 100644
index 0000000..c2701fe
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -0,0 +1,80 @@
+# LS1043aRdbPkg.dsc
+#
+# LS1043ARDB Board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_NAME = LS1043aRdbPkg
+ PLATFORM_GUID = 60169ec4-d2b4-44f8-825e-f8684fd42e4f
+ OUTPUT_DIRECTORY = Build/LS1043aRdbPkg
+ FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+
+!include Platform/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
+
+[LibraryClasses.common]
+ SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+ ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+ IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
+ RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
+
+[PcdsFixedAtBuild.common]
+
+ #
+ # LS1043a board Specific PCDs
+ # XX (DRAM - Region 1 2GB)
+ # (NOR - IFC Region 1 512MB)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
+ #
+ # Board Specific Pcds
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
+
+ #
+ # RTC Pcds
+ #
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # Architectural Protocols
+ #
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+
+ Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
+ Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+ Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+
+ ##
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
new file mode 100644
index 0000000..417303d
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -0,0 +1,198 @@
+# LS1043aRdbPkg.fdf
+#
+# FLASH layout file for LS1043a board.
+#
+# Copyright (c) 2016, Freescale Ltd. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LS1043ARDB_EFI]
+BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
+Size = 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xED000
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x000ED000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+!include Platform/NXP/FVRules.fdf.inc
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize = 0x1
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+ INF Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+
+ INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ #
+ # Network modules
+ #
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+ INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+ INF NetworkPkg/TcpDxe/TcpDxe.inf
+ INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+ INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+ INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+ INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+!endif
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/FatPei/FatPei.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
new file mode 100644
index 0000000..972dadc
--- /dev/null
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -0,0 +1,412 @@
+# @file
+#
+# Copyright 2017 NXP.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001000A
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+
+[LibraryClasses.common]
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+ ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+ BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+ PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+ # Networking Requirements
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+ # ARM GIC400 General Interrupt Driver
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+ SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.common.SEC]
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+ LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+ MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+
+ # 1/123 faster than Stm or Vstm version
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+ # Uncomment to turn on GDB stub in SEC.
+ #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+
+[LibraryClasses.common.PEIM]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.AARCH64]
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[BuildOptions]
+ XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7
+ GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a
+ RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu cortex-a9
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
+ GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+ # It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+ gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+[PcdsDynamicDefault.common]
+ #
+ # Set video resolution for boot options and for text setup.
+ # PlatformDxe can set the former at runtime.
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
+
+[PcdsDynamicHii.common.DEFAULT]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
+
+[PcdsFixedAtBuild.common]
+ gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|1 # Only one core
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|2000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000001
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000045
+!endif
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ #
+ # Optional feature to help prevent EFI memory map fragments
+ # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+ # Values are in EFI Pages (4K). DXE Core will make sure that
+ # at least this much of each type of memory can be allocated
+ # from a single memory range. This way you only end up with
+ # maximum of two fragements for each type in the memory map
+ # (the memory used, and the free memory that was prereserved
+ # but not used).
+ #
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ # Serial Terminal
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+ # Size of the region reserved for fixed address allocations (Reserved 32MB)
+ gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x08000000
+ gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x0
+ gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x94A00000
+ gArmTokenSpaceGuid.PcdCpuResetAddress|0x94A00000
+
+ # Timer
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
+
+ # We want to use the Shell Libraries but don't want it to initialise
+ # automatically. We initialise the libraries when the command is called by the
+ # Shell.
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+
+ # Use the serial console for both ConIn & ConOut
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000
+!ifdef $(NO_SHELL_PROFILES)
+ gEfiShellPkgTokenSpaceGuid.PcdShellProfileMask|0x00
+!endif #$(NO_SHELL_PROFILES)
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # SEC
+ #
+ ArmPlatformPkg/PrePi/PeiUniCore.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+ # FDT installation
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ #
+ # Networking stack
+ #
+ MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+ NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+ NetworkPkg/TcpDxe/TcpDxe.inf
+ NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+ NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+ NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+ NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+!endif
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ FatPkg/FatPei/FatPei.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Example Application
+ #
+ MdeModulePkg/Application/HelloWorld/HelloWorld.inf
+ ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+!ifndef $(NO_SHELL_PROFILES)
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+!endif #$(NO_SHELL_PROFILES)
+ }
+
+ ##
diff --git a/Silicon/NXP/LS1043A/LS1043A.dec b/Silicon/NXP/LS1043A/LS1043A.dec
new file mode 100644
index 0000000..7581424
--- /dev/null
+++ b/Silicon/NXP/LS1043A/LS1043A.dec
@@ -0,0 +1,22 @@
+# LS1043A.dec
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001000A
+
+[Guids.common]
+ gNxpLs1043ATokenSpaceGuid = {0x6834fe45, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
+
+[Includes]
+ Include
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
new file mode 100644
index 0000000..8395dfd
--- /dev/null
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -0,0 +1,73 @@
+# LS1043A.dsc
+# LS1043A Soc package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsDynamicDefault.common]
+
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
+
+[PcdsFixedAtBuild.common]
+
+ #
+ # CCSR Address Space and other attached Memories
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
+ gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000
+ gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
+
+ #
+ # Big Endian IPs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
+
+##
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
new file mode 100644
index 0000000..df64ad6
--- /dev/null
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -0,0 +1,117 @@
+# @file.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001000A
+ PACKAGE_VERSION = 0.1
+
+[Includes]
+ .
+ Include
+
+[Guids.common]
+ gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
+ gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
+
+[PcdsFixedAtBuild.common]
+ #
+ # Pcds for I2C Controller
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002
+
+ #
+ # Pcds for base address and size
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
+ gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
+ gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
+ gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x0|UINT64|0x00000104
+ gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
+ gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
+ gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
+ gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
+ gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
+ gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0|UINT64|0x0000011A
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0|UINT64|0x0000011B
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0|UINT64|0x0000011C
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0|UINT64|0x0000011D
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x0|UINT64|0x0000011E
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x0|UINT64|0x0000011F
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x00000120
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x00000121
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x00000122
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x00000123
+ gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x00000124
+ gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x00000125
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000126
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000127
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000128
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129
+ gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A
+
+ #
+ # IFC PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
+
+ #
+ # NV Pcd
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
+ gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211
+
+ #
+ # Platform PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
+
+ #
+ # Clock PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
+ gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1
+
+ #
+ # Pcds to support Big Endian IPs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
+ gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
+ gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|FALSE|BOOLEAN|0x00000313
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 10/41] Readme : Add Readme.md file.
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (8 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 09/41] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-18 18:41 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC controller Meenakshi Aggarwal
` (32 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Readme.md to explain how to build NXP board packages.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/Readme.md | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Platform/NXP/Readme.md
diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md
new file mode 100644
index 0000000..902bafe
--- /dev/null
+++ b/Platform/NXP/Readme.md
@@ -0,0 +1,24 @@
+Support for all NXP boards is available in this directory.
+
+# How to build
+
+1. Set toolchain path.
+
+ export PATH=<TOOLCHAIN_PATH>/gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-gnu/bin/:$PATH
+
+2. Export following variables needed for compilation.
+
+ export CROSS_COMPILE=aarch64-linux-gnu-
+ export GCC_ARCH_PREFIX=GCC49_AARCH64_PREFIX
+ export GCC49_AARCH64_PREFIX=aarch64-linux-gnu-
+ export PACKAGES_PATH=<EDK2_PATH>/edk2/edk2-platforms
+
+3. Build desired board package
+
+ source edksetup.sh
+ build -p "path to package's description (.dsc) file" -a AARCH64 -t GCC49 -b DEBUG/RELEASE clean
+
+ e.g.
+ build -p "$PACKAGES_PATH/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc" -a AARCH64 -t GCC49 -b DEBUG clean
+ build -p "$PACKAGES_PATH/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc" -a AARCH64 -t GCC49 -b DEBUG
+
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC controller
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (9 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 10/41] Readme : Add Readme.md file Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-18 18:45 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 12/41] LS1043/BoardLib : Add support for LS1043 BoardLib Meenakshi Aggarwal
` (31 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
This header file contain IFC controller timing structure,
chip select enum and other IFC macros.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Include/Ifc.h | 423 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 423 insertions(+)
create mode 100644 Silicon/NXP/Include/Ifc.h
diff --git a/Silicon/NXP/Include/Ifc.h b/Silicon/NXP/Include/Ifc.h
new file mode 100644
index 0000000..6babb22
--- /dev/null
+++ b/Silicon/NXP/Include/Ifc.h
@@ -0,0 +1,423 @@
+/** @Ifc.h
+
+ The integrated flash controller (IFC) is used to interface with external asynchronous
+ NAND flash, asynchronous NOR flash, SRAM, generic ASIC memories and EPROM.
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __IFC_H__
+#define __IFC_H__
+
+#include <Library/BaseLib.h>
+#include <Uefi.h>
+
+#define IFC_BANK_COUNT 4
+
+#define IFC_CSPR_REG_LEN 148
+#define IFC_AMASK_REG_LEN 144
+#define IFC_CSOR_REG_LEN 144
+#define IFC_FTIM_REG_LEN 576
+
+#define IFC_CSPR_USED_LEN sizeof (IFC_CSPR) * \
+ IFC_BANK_COUNT
+
+#define IFC_AMASK_USED_LEN sizeof (IFC_AMASK) * \
+ IFC_BANK_COUNT
+
+#define IFC_CSOR_USED_LEN sizeof (IFC_CSOR) * \
+ IFC_BANK_COUNT
+
+#define IFC_FTIM_USED_LEN sizeof (IFC_FTIM) * \
+ IFC_BANK_COUNT
+
+/* List of commands */
+#define IFC_NAND_CMD_RESET 0xFF
+#define IFC_NAND_CMD_READID 0x90
+#define IFC_NAND_CMD_STATUS 0x70
+#define IFC_NAND_CMD_READ0 0x00
+#define IFC_NAND_CMD_READSTART 0x30
+#define IFC_NAND_CMD_ERASE1 0x60
+#define IFC_NAND_CMD_ERASE2 0xD0
+#define IFC_NAND_CMD_SEQIN 0x80
+#define IFC_NAND_CMD_PAGEPROG 0x10
+#define MAX_RETRY_COUNT 150000
+
+
+#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
+
+/*
+ * NAND Event and Error Status Register (NAND_EVTER_STAT)
+ */
+
+/* Operation Complete */
+#define IFC_NAND_EVTER_STAT_OPC 0x80000000
+
+/* Flash Timeout Error */
+#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
+
+/* Write Protect Error */
+#define IFC_NAND_EVTER_STAT_WPER 0x04000000
+
+/* ECC Error */
+#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
+
+/*
+ * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
+ */
+
+/* NAND Machine specific opcodes OP0-OP14*/
+#define IFC_NAND_FIR0_OP0 0xFC000000
+#define IFC_NAND_FIR0_OP0_SHIFT 26
+#define IFC_NAND_FIR0_OP1 0x03F00000
+#define IFC_NAND_FIR0_OP1_SHIFT 20
+#define IFC_NAND_FIR0_OP2 0x000FC000
+#define IFC_NAND_FIR0_OP2_SHIFT 14
+#define IFC_NAND_FIR0_OP3 0x00003F00
+#define IFC_NAND_FIR0_OP3_SHIFT 8
+#define IFC_NAND_FIR0_OP4 0x000000FC
+#define IFC_NAND_FIR0_OP4_SHIFT 2
+#define IFC_NAND_FIR1_OP5 0xFC000000
+#define IFC_NAND_FIR1_OP5_SHIFT 26
+#define IFC_NAND_FIR1_OP6 0x03F00000
+#define IFC_NAND_FIR1_OP6_SHIFT 20
+#define IFC_NAND_FIR1_OP7 0x000FC000
+#define IFC_NAND_FIR1_OP7_SHIFT 14
+#define IFC_NAND_FIR1_OP8 0x00003F00
+#define IFC_NAND_FIR1_OP8_SHIFT 8
+#define IFC_NAND_FIR1_OP9 0x000000FC
+#define IFC_NAND_FIR1_OP9_SHIFT 2
+#define IFC_NAND_FIR2_OP10 0xFC000000
+#define IFC_NAND_FIR2_OP10_SHIFT 26
+#define IFC_NAND_FIR2_OP11 0x03F00000
+#define IFC_NAND_FIR2_OP11_SHIFT 20
+#define IFC_NAND_FIR2_OP12 0x000FC000
+#define IFC_NAND_FIR2_OP12_SHIFT 14
+#define IFC_NAND_FIR2_OP13 0x00003F00
+#define IFC_NAND_FIR2_OP13_SHIFT 8
+#define IFC_NAND_FIR2_OP14 0x000000FC
+#define IFC_NAND_FIR2_OP14_SHIFT 2
+
+/*
+ * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
+ */
+
+/* General purpose FCM flash command bytes CMD0-CMD7 */
+#define IFC_NAND_FCR0_CMD0 0xFF000000
+#define IFC_NAND_FCR0_CMD0_SHIFT 24
+#define IFC_NAND_FCR0_CMD1 0x00FF0000
+#define IFC_NAND_FCR0_CMD1_SHIFT 16
+#define IFC_NAND_FCR0_CMD2 0x0000FF00
+#define IFC_NAND_FCR0_CMD2_SHIFT 8
+#define IFC_NAND_FCR0_CMD3 0x000000FF
+#define IFC_NAND_FCR0_CMD3_SHIFT 0
+#define IFC_NAND_FCR1_CMD4 0xFF000000
+#define IFC_NAND_FCR1_CMD4_SHIFT 24
+#define IFC_NAND_FCR1_CMD5 0x00FF0000
+#define IFC_NAND_FCR1_CMD5_SHIFT 16
+#define IFC_NAND_FCR1_CMD6 0x0000FF00
+#define IFC_NAND_FCR1_CMD6_SHIFT 8
+#define IFC_NAND_FCR1_CMD7 0x000000FF
+#define IFC_NAND_FCR1_CMD7_SHIFT 0
+
+/* Timing registers for NAND Flash */
+
+#define IFC_FTIM0_NAND_TCCST_SHIFT 25
+#define IFC_FTIM0_NAND_TCCST(n) ((n) << IFC_FTIM0_NAND_TCCST_SHIFT)
+#define IFC_FTIM0_NAND_TWP_SHIFT 16
+#define IFC_FTIM0_NAND_TWP(n) ((n) << IFC_FTIM0_NAND_TWP_SHIFT)
+#define IFC_FTIM0_NAND_TWCHT_SHIFT 8
+#define IFC_FTIM0_NAND_TWCHT(n) ((n) << IFC_FTIM0_NAND_TWCHT_SHIFT)
+#define IFC_FTIM0_NAND_TWH_SHIFT 0
+#define IFC_FTIM0_NAND_TWH(n) ((n) << IFC_FTIM0_NAND_TWH_SHIFT)
+#define IFC_FTIM1_NAND_TADLE_SHIFT 24
+#define IFC_FTIM1_NAND_TADLE(n) ((n) << IFC_FTIM1_NAND_TADLE_SHIFT)
+#define IFC_FTIM1_NAND_TWBE_SHIFT 16
+#define IFC_FTIM1_NAND_TWBE(n) ((n) << IFC_FTIM1_NAND_TWBE_SHIFT)
+#define IFC_FTIM1_NAND_TRR_SHIFT 8
+#define IFC_FTIM1_NAND_TRR(n) ((n) << IFC_FTIM1_NAND_TRR_SHIFT)
+#define IFC_FTIM1_NAND_TRP_SHIFT 0
+#define IFC_FTIM1_NAND_TRP(n) ((n) << IFC_FTIM1_NAND_TRP_SHIFT)
+#define IFC_FTIM2_NAND_TRAD_SHIFT 21
+#define IFC_FTIM2_NAND_TRAD(n) ((n) << IFC_FTIM2_NAND_TRAD_SHIFT)
+#define IFC_FTIM2_NAND_TREH_SHIFT 11
+#define IFC_FTIM2_NAND_TREH(n) ((n) << IFC_FTIM2_NAND_TREH_SHIFT)
+#define IFC_FTIM2_NAND_TWHRE_SHIFT 0
+#define IFC_FTIM2_NAND_TWHRE(n) ((n) << IFC_FTIM2_NAND_TWHRE_SHIFT)
+#define IFC_FTIM3_NAND_TWW_SHIFT 24
+#define IFC_FTIM3_NAND_TWW(n) ((n) << IFC_FTIM3_NAND_TWW_SHIFT)
+
+/*
+ * Flash ROW and COL Address Register (ROWn, COLn)
+ */
+
+/* Main/spare region locator */
+#define IFC_NAND_COL_MS 0x80000000
+
+/* Column Address */
+#define IFC_NAND_COL_CA_MASK 0x00000FFF
+
+#define NAND_STATUS_WP 0x80
+
+/*
+ * NAND Event and Error Enable Register (NAND_EVTER_EN)
+ */
+
+/* Operation complete event enable */
+#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
+
+/* Page read complete event enable */
+#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
+
+/* Flash Timeout error enable */
+#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
+
+/* Write Protect error enable */
+#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
+
+/* ECC error logging enable */
+#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
+
+/*
+ * CSPR - Chip Select Property Register
+ */
+
+#define IFC_CSPR_BA 0xFFFF0000
+#define IFC_CSPR_BA_SHIFT 16
+#define IFC_CSPR_PORT_SIZE 0x00000180
+#define IFC_CSPR_PORT_SIZE_SHIFT 7
+
+// Port Size 8 bit
+#define IFC_CSPR_PORT_SIZE_8 0x00000080
+
+// Port Size 16 bit
+#define IFC_CSPR_PORT_SIZE_16 0x00000100
+
+// Port Size 32 bit
+#define IFC_CSPR_PORT_SIZE_32 0x00000180
+
+// Write Protect
+#define IFC_CSPR_WP 0x00000040
+#define IFC_CSPR_WP_SHIFT 6
+
+// Machine Select
+#define IFC_CSPR_MSEL 0x00000006
+#define IFC_CSPR_MSEL_SHIFT 1
+
+// NOR
+#define IFC_CSPR_MSEL_NOR 0x00000000
+
+/* NAND */
+#define IFC_CSPR_MSEL_NAND 0x00000002
+
+/* GPCM */
+#define IFC_CSPR_MSEL_GPCM 0x00000004
+
+// Bank Valid
+#define IFC_CSPR_V 0x00000001
+#define IFC_CSPR_V_SHIFT 0
+
+/*
+ * Chip Select Option Register - NOR Flash Mode
+ */
+
+// Enable Address shift Mode
+#define IFC_CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
+
+// Page Read Enable from NOR device
+#define IFC_CSOR_NOR_PGRD_EN 0x10000000
+
+// AVD Toggle Enable during Burst Program
+#define IFC_CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
+
+// Address Data Multiplexing Shift
+#define IFC_CSOR_NOR_ADM_MASK 0x0003E000
+#define IFC_CSOR_NOR_ADM_SHIFT_SHIFT 13
+#define IFC_CSOR_NOR_ADM_SHIFT(n) ((n) << IFC_CSOR_NOR_ADM_SHIFT_SHIFT)
+
+// Type of the NOR device hooked
+#define IFC_CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
+#define IFC_CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
+
+// Time for Read Enable High to Output High Impedance
+#define IFC_CSOR_NOR_TRHZ_MASK 0x0000001C
+#define IFC_CSOR_NOR_TRHZ_SHIFT 2
+#define IFC_CSOR_NOR_TRHZ_20 0x00000000
+#define IFC_CSOR_NOR_TRHZ_40 0x00000004
+#define IFC_CSOR_NOR_TRHZ_60 0x00000008
+#define IFC_CSOR_NOR_TRHZ_80 0x0000000C
+#define IFC_CSOR_NOR_TRHZ_100 0x00000010
+
+// Buffer control disable
+#define IFC_CSOR_NOR_BCTLD 0x00000001
+
+/*
+ * Chip Select Option Register IFC_NAND Machine
+ */
+
+/* Enable ECC Encoder */
+#define IFC_CSOR_NAND_ECC_ENC_EN 0x80000000
+#define IFC_CSOR_NAND_ECC_MODE_MASK 0x30000000
+
+/* 4 bit correction per 520 Byte sector */
+#define IFC_CSOR_NAND_ECC_MODE_4 0x00000000
+
+/* 8 bit correction per 528 Byte sector */
+#define IFC_CSOR_NAND_ECC_MODE_8 0x10000000
+
+/* Enable ECC Decoder */
+#define IFC_CSOR_NAND_ECC_DEC_EN 0x04000000
+
+/* Row Address Length */
+#define IFC_CSOR_NAND_RAL_MASK 0x01800000
+#define IFC_CSOR_NAND_RAL_SHIFT 20
+#define IFC_CSOR_NAND_RAL_1 0x00000000
+#define IFC_CSOR_NAND_RAL_2 0x00800000
+#define IFC_CSOR_NAND_RAL_3 0x01000000
+#define IFC_CSOR_NAND_RAL_4 0x01800000
+
+/* Page Size 512b, 2k, 4k */
+#define IFC_CSOR_NAND_PGS_MASK 0x00180000
+#define IFC_CSOR_NAND_PGS_SHIFT 16
+#define IFC_CSOR_NAND_PGS_512 0x00000000
+#define IFC_CSOR_NAND_PGS_2K 0x00080000
+#define IFC_CSOR_NAND_PGS_4K 0x00100000
+#define IFC_CSOR_NAND_PGS_8K 0x00180000
+
+/* Spare region Size */
+#define IFC_CSOR_NAND_SPRZ_MASK 0x0000E000
+#define IFC_CSOR_NAND_SPRZ_SHIFT 13
+#define IFC_CSOR_NAND_SPRZ_16 0x00000000
+#define IFC_CSOR_NAND_SPRZ_64 0x00002000
+#define IFC_CSOR_NAND_SPRZ_128 0x00004000
+#define IFC_CSOR_NAND_SPRZ_210 0x00006000
+#define IFC_CSOR_NAND_SPRZ_218 0x00008000
+#define IFC_CSOR_NAND_SPRZ_224 0x0000A000
+#define IFC_CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
+
+/* Pages Per Block */
+#define IFC_CSOR_NAND_PB_MASK 0x00000700
+#define IFC_CSOR_NAND_PB_SHIFT 8
+#define IFC_CSOR_NAND_PB(n) (n-5) << IFC_CSOR_NAND_PB_SHIFT
+
+/* Time for Read Enable High to Output High Impedance */
+#define IFC_CSOR_NAND_TRHZ_MASK 0x0000001C
+#define IFC_CSOR_NAND_TRHZ_SHIFT 2
+#define IFC_CSOR_NAND_TRHZ_20 0x00000000
+#define IFC_CSOR_NAND_TRHZ_40 0x00000004
+#define IFC_CSOR_NAND_TRHZ_60 0x00000008
+#define IFC_CSOR_NAND_TRHZ_80 0x0000000C
+#define IFC_CSOR_NAND_TRHZ_100 0x00000010
+
+/*
+ * FTIM0 - NOR Flash Mode
+ */
+#define IFC_FTIM0_NOR 0xF03F3F3F
+#define IFC_FTIM0_NOR_TACSE_SHIFT 28
+#define IFC_FTIM0_NOR_TACSE(n) ((n) << IFC_FTIM0_NOR_TACSE_SHIFT)
+#define IFC_FTIM0_NOR_TEADC_SHIFT 16
+#define IFC_FTIM0_NOR_TEADC(n) ((n) << IFC_FTIM0_NOR_TEADC_SHIFT)
+#define IFC_FTIM0_NOR_TAVDS_SHIFT 8
+#define IFC_FTIM0_NOR_TAVDS(n) ((n) << IFC_FTIM0_NOR_TAVDS_SHIFT)
+#define IFC_FTIM0_NOR_TEAHC_SHIFT 0
+#define IFC_FTIM0_NOR_TEAHC(n) ((n) << IFC_FTIM0_NOR_TEAHC_SHIFT)
+
+/*
+ * FTIM1 - NOR Flash Mode
+ */
+#define IFC_FTIM1_NOR 0xFF003F3F
+#define IFC_FTIM1_NOR_TACO_SHIFT 24
+#define IFC_FTIM1_NOR_TACO(n) ((n) << IFC_FTIM1_NOR_TACO_SHIFT)
+#define IFC_FTIM1_NOR_TRAD_NOR_SHIFT 8
+#define IFC_FTIM1_NOR_TRAD_NOR(n) ((n) << IFC_FTIM1_NOR_TRAD_NOR_SHIFT)
+#define IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
+#define IFC_FTIM1_NOR_TSEQRAD_NOR(n) ((n) << IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT)
+
+/*
+ * FTIM2 - NOR Flash Mode
+ */
+#define IFC_FTIM2_NOR 0x0F3CFCFF
+#define IFC_FTIM2_NOR_TCS_SHIFT 24
+#define IFC_FTIM2_NOR_TCS(n) ((n) << IFC_FTIM2_NOR_TCS_SHIFT)
+#define IFC_FTIM2_NOR_TCH_SHIFT 18
+#define IFC_FTIM2_NOR_TCH(n) ((n) << IFC_FTIM2_NOR_TCH_SHIFT)
+#define IFC_FTIM2_NOR_TWPH_SHIFT 10
+#define IFC_FTIM2_NOR_TWPH(n) ((n) << IFC_FTIM2_NOR_TWPH_SHIFT)
+#define IFC_FTIM2_NOR_TWP_SHIFT 0
+#define IFC_FTIM2_NOR_TWP(n) ((n) << IFC_FTIM2_NOR_TWP_SHIFT)
+
+/*
+ * FTIM0 - Normal GPCM Mode
+ */
+#define IFC_FTIM0_GPCM 0xF03F3F3F
+#define IFC_FTIM0_GPCM_TACSE_SHIFT 28
+#define IFC_FTIM0_GPCM_TACSE(n) ((n) << IFC_FTIM0_GPCM_TACSE_SHIFT)
+#define IFC_FTIM0_GPCM_TEADC_SHIFT 16
+#define IFC_FTIM0_GPCM_TEADC(n) ((n) << IFC_FTIM0_GPCM_TEADC_SHIFT)
+#define IFC_FTIM0_GPCM_TAVDS_SHIFT 8
+#define IFC_FTIM0_GPCM_TAVDS(n) ((n) << IFC_FTIM0_GPCM_TAVDS_SHIFT)
+#define IFC_FTIM0_GPCM_TEAHC_SHIFT 0
+#define IFC_FTIM0_GPCM_TEAHC(n) ((n) << IFC_FTIM0_GPCM_TEAHC_SHIFT)
+
+/*
+ * FTIM1 - Normal GPCM Mode
+ */
+#define IFC_FTIM1_GPCM 0xFF003F00
+#define IFC_FTIM1_GPCM_TACO_SHIFT 24
+#define IFC_FTIM1_GPCM_TACO(n) ((n) << IFC_FTIM1_GPCM_TACO_SHIFT)
+#define IFC_FTIM1_GPCM_TRAD_SHIFT 8
+#define IFC_FTIM1_GPCM_TRAD(n) ((n) << IFC_FTIM1_GPCM_TRAD_SHIFT)
+
+/*
+ * FTIM2 - Normal GPCM Mode
+ */
+#define IFC_FTIM2_GPCM 0x0F3C00FF
+#define IFC_FTIM2_GPCM_TCS_SHIFT 24
+#define IFC_FTIM2_GPCM_TCS(n) ((n) << IFC_FTIM2_GPCM_TCS_SHIFT)
+#define IFC_FTIM2_GPCM_TCH_SHIFT 18
+#define IFC_FTIM2_GPCM_TCH(n) ((n) << IFC_FTIM2_GPCM_TCH_SHIFT)
+#define IFC_FTIM2_GPCM_TWP_SHIFT 0
+#define IFC_FTIM2_GPCM_TWP(n) ((n) << IFC_FTIM2_GPCM_TWP_SHIFT)
+
+/* Convert an address into the right format for the CSPR Registers */
+#define IFC_CSPR_PHYS_ADDR(x) (((UINTN)x) & 0xffff0000)
+
+/*
+ * Address Mask Register
+ */
+#define IFC_AMASK_MASK 0xFFFF0000
+#define IFC_AMASK_SHIFT 16
+#define IFC_AMASK(n) (IFC_AMASK_MASK << \
+ (HighBitSet32(n) - IFC_AMASK_SHIFT))
+
+typedef enum {
+ IFC_CS0 = 0,
+ IFC_CS1,
+ IFC_CS2,
+ IFC_CS3,
+ IFC_CS4,
+ IFC_CS5,
+ IFC_CS6,
+ IFC_CS7,
+ IFC_CS_MAX,
+} IFC_CHIP_SEL;
+
+typedef struct {
+ UINT32 Ftim[IFC_BANK_COUNT];
+ UINT32 CsprExt;
+ UINT32 Cspr;
+ UINT32 Csor;
+ UINT32 Amask;
+ UINT8 CS;
+} IFC_TIMINGS;
+
+#endif //__IFC_H__
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 12/41] LS1043/BoardLib : Add support for LS1043 BoardLib.
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (10 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC controller Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-18 18:50 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 13/41] Silicon/NXP : Add support of IfcLib Meenakshi Aggarwal
` (30 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
BoardLib will contain functions specific for LS1043aRdb board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
.../NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h | 109 +++++++++++++++++++++
.../NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c | 69 +++++++++++++
.../LS1043aRdbPkg/Library/BoardLib/BoardLib.inf | 31 ++++++
3 files changed, 209 insertions(+)
create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h b/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
new file mode 100644
index 0000000..261867a
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
@@ -0,0 +1,109 @@
+/** IfcBoardSpecificLib.h
+
+ IFC Flash Board Specific Macros and structure
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __IFC__BOARD_SPECIFIC_H__
+#define __IFC__BOARD_SPECIFIC_H__
+
+#include <Ifc.h>
+
+// On board flash support
+#define IFC_NAND_BUF_BASE 0x7E800000
+
+// On board Inegrated flash Controller chip select configuration
+#define IFC_NOR_CS IFC_CS0
+#define IFC_NAND_CS IFC_CS1
+#define IFC_FPGA_CS IFC_CS2
+
+// board-specific NAND timing
+#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x7) | \
+ IFC_FTIM0_NAND_TWP(0x18) | \
+ IFC_FTIM0_NAND_TWCHT(0x7) | \
+ IFC_FTIM0_NAND_TWH(0xa))
+
+#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x32) | \
+ IFC_FTIM1_NAND_TWBE(0x39) | \
+ IFC_FTIM1_NAND_TRR(0xe) | \
+ IFC_FTIM1_NAND_TRP(0x18))
+
+#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0xf) | \
+ IFC_FTIM2_NAND_TREH(0xa) | \
+ IFC_FTIM2_NAND_TWHRE(0x1e))
+
+#define NAND_FTIM3 0x0
+
+#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BUF_BASE) \
+ | IFC_CSPR_PORT_SIZE_8 \
+ | IFC_CSPR_MSEL_NAND \
+ | IFC_CSPR_V)
+
+#define NAND_CSPR_EXT 0x0
+#define NAND_AMASK 0xFFFF0000
+
+#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | IFC_CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | IFC_CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | IFC_CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | IFC_CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
+ | IFC_CSOR_NAND_PB(6)) /* 2^6 Pages Per Block */
+
+// board-specific NOR timing
+#define NOR_FTIM0 (IFC_FTIM0_NOR_TACSE(0x1) | \
+ IFC_FTIM0_NOR_TEADC(0x1) | \
+ IFC_FTIM0_NOR_TAVDS(0x0) | \
+ IFC_FTIM0_NOR_TEAHC(0xc))
+#define NOR_FTIM1 (IFC_FTIM1_NOR_TACO(0x1c) | \
+ IFC_FTIM1_NOR_TRAD_NOR(0xb) |\
+ IFC_FTIM1_NOR_TSEQRAD_NOR(0x9))
+#define NOR_FTIM2 (IFC_FTIM2_NOR_TCS(0x1) | \
+ IFC_FTIM2_NOR_TCH(0x4) | \
+ IFC_FTIM2_NOR_TWPH(0x8) | \
+ IFC_FTIM2_NOR_TWP(0x10))
+#define NOR_FTIM3 0x0
+
+#define NOR_CSPR (IFC_CSPR_PHYS_ADDR(FixedPcdGet64 (PcdIfcRegion1BaseAddr)) \
+ | IFC_CSPR_PORT_SIZE_16 \
+ | IFC_CSPR_MSEL_NOR \
+ | IFC_CSPR_V)
+
+#define NOR_CSPR_EXT 0x0
+#define NOR_AMASK IFC_AMASK(128*1024*1024)
+#define NOR_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) | \
+ IFC_CSOR_NOR_TRHZ_80)
+
+// board-specific fpga timing
+#define FPGA_BASE_PHYS 0x7fb00000
+#define FPGA_CSPR_EXT 0x0
+#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
+ IFC_CSPR_PORT_SIZE_8 | \
+ IFC_CSPR_MSEL_GPCM | \
+ IFC_CSPR_V)
+
+#define FPGA_AMASK IFC_AMASK(64 * 1024)
+#define FPGA_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) | \
+ IFC_CSOR_NOR_NOR_MODE_AVD_NOR | \
+ IFC_CSOR_NOR_TRHZ_80)
+
+#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0xf) | \
+ IFC_FTIM0_GPCM_TEADC(0xf) | \
+ IFC_FTIM0_GPCM_TEAHC(0xf))
+#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \
+ IFC_FTIM1_GPCM_TRAD(0x3f))
+#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \
+ IFC_FTIM2_GPCM_TCH(0xf) | \
+ IFC_FTIM2_GPCM_TWP(0xff))
+#define FPGA_FTIM3 0x0
+
+#endif //__IFC__BOARD_SPECIFIC_H__
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
new file mode 100644
index 0000000..a101a8d
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
@@ -0,0 +1,69 @@
+/** @file
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IfcBoardSpecific.h>
+
+VOID
+GetIfcNorFlashTimings (
+ IN IFC_TIMINGS * NorIfcTimings
+ )
+{
+ NorIfcTimings->Ftim[0] = NOR_FTIM0;
+ NorIfcTimings->Ftim[1] = NOR_FTIM1;
+ NorIfcTimings->Ftim[2] = NOR_FTIM2;
+ NorIfcTimings->Ftim[3] = NOR_FTIM3;
+ NorIfcTimings->Cspr = NOR_CSPR;
+ NorIfcTimings->CsprExt = NOR_CSPR_EXT;
+ NorIfcTimings->Amask = NOR_AMASK;
+ NorIfcTimings->Csor = NOR_CSOR;
+ NorIfcTimings->CS = IFC_NOR_CS;
+
+ return ;
+}
+
+VOID
+GetIfcFpgaTimings (
+ IN IFC_TIMINGS *FpgaIfcTimings
+ )
+{
+ FpgaIfcTimings->Ftim[0] = FPGA_FTIM0;
+ FpgaIfcTimings->Ftim[1] = FPGA_FTIM1;
+ FpgaIfcTimings->Ftim[2] = FPGA_FTIM2;
+ FpgaIfcTimings->Ftim[3] = FPGA_FTIM3;
+ FpgaIfcTimings->Cspr = FPGA_CSPR;
+ FpgaIfcTimings->CsprExt = FPGA_CSPR_EXT;
+ FpgaIfcTimings->Amask = FPGA_AMASK;
+ FpgaIfcTimings->Csor = FPGA_CSOR;
+ FpgaIfcTimings->CS = IFC_FPGA_CS;
+
+ return;
+}
+
+VOID
+GetIfcNandFlashTimings (
+ IN IFC_TIMINGS * NandIfcTimings
+ )
+{
+ NandIfcTimings->Ftim[0] = NAND_FTIM0;
+ NandIfcTimings->Ftim[1] = NAND_FTIM1;
+ NandIfcTimings->Ftim[2] = NAND_FTIM2;
+ NandIfcTimings->Ftim[3] = NAND_FTIM3;
+ NandIfcTimings->Cspr = NAND_CSPR;
+ NandIfcTimings->CsprExt = NAND_CSPR_EXT;
+ NandIfcTimings->Amask = NAND_AMASK;
+ NandIfcTimings->Csor = NAND_CSOR;
+ NandIfcTimings->CS = IFC_NAND_CS;
+
+ return;
+}
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
new file mode 100644
index 0000000..7d2702b
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
@@ -0,0 +1,31 @@
+# @file
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = BoardLib
+ FILE_GUID = 8ecefc8f-a2c4-4091-b80f-92da7c4ab37f
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardLib
+
+[Sources.common]
+ BoardLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[FixedPcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 13/41] Silicon/NXP : Add support of IfcLib
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (11 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 12/41] LS1043/BoardLib : Add support for LS1043 BoardLib Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-19 13:25 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 14/41] Silicon/NXP : Add support for FpgaLib Meenakshi Aggarwal
` (29 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Add support of IfcLib, it will be used to perform
any operation on IFC controller.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Include/Library/IfcLib.h | 26 +++++
Silicon/NXP/Library/IfcLib/IfcLib.c | 150 +++++++++++++++++++++++++++
Silicon/NXP/Library/IfcLib/IfcLib.h | 190 ++++++++++++++++++++++++++++++++++
Silicon/NXP/Library/IfcLib/IfcLib.inf | 38 +++++++
Silicon/NXP/NxpQoriqLs.dec | 1 +
5 files changed, 405 insertions(+)
create mode 100644 Silicon/NXP/Include/Library/IfcLib.h
create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.c
create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.h
create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.inf
diff --git a/Silicon/NXP/Include/Library/IfcLib.h b/Silicon/NXP/Include/Library/IfcLib.h
new file mode 100644
index 0000000..8d2c151
--- /dev/null
+++ b/Silicon/NXP/Include/Library/IfcLib.h
@@ -0,0 +1,26 @@
+/** @IfcLib.h
+
+ The integrated flash controller (IFC) is used to interface with external asynchronous
+ NAND flash, asynchronous NOR flash, SRAM, generic ASIC memories and EPROM.
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __IFC_LIB_H__
+#define __IFC_LIB_H__
+
+VOID
+IfcInit (
+ VOID
+ );
+
+#endif //__IFC_LIB_H__
diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.c b/Silicon/NXP/Library/IfcLib/IfcLib.c
new file mode 100644
index 0000000..8cf02ae
--- /dev/null
+++ b/Silicon/NXP/Library/IfcLib/IfcLib.c
@@ -0,0 +1,150 @@
+/** @IfcLib.c
+
+ The integrated flash controller (IFC) is used to interface with external asynchronous/
+ synchronous NAND flash, asynchronous NOR flash, SRAM, generic ASIC memory and
+ EPROM.
+ It has eight chip-selects, to which a maximum of eight flash devices can be attached,
+ although only one of these can be accessed at any given time.
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/IoAccessLib.h>
+#include "IfcLib.h"
+
+STATIC MMIO_OPERATIONS_32 *mMmioOps;
+
+STATIC UINT8 mNandCS;
+STATIC UINT8 mNorCS;
+STATIC UINT8 mFpgaCS;
+
+VOID
+SetTimings (
+ IN UINT8 CS,
+ IN IFC_TIMINGS IfcTimings
+ )
+{
+ IFC_REGS* IfcRegs;
+
+ IfcRegs = (IFC_REGS*)PcdGet64 (PcdIfcBaseAddr);
+
+ // Configure Extended chip select property registers
+ mMmioOps->Write ((UINTN)&IfcRegs->CsprCs[CS].CsprExt, IfcTimings.CsprExt);
+
+ // Configure Fpga timing registers
+ mMmioOps->Write ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM0], IfcTimings.Ftim[0]);
+ mMmioOps->Write ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM1], IfcTimings.Ftim[1]);
+ mMmioOps->Write ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM2], IfcTimings.Ftim[2]);
+ mMmioOps->Write ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM3], IfcTimings.Ftim[3]);
+
+ // Configure chip select option registers
+ mMmioOps->Write ((UINTN)&IfcRegs->CsprCs[CS].Cspr, IfcTimings.Cspr);
+
+ // Configure address mask registers
+ mMmioOps->Write ((UINTN)&IfcRegs->AmaskCs[CS].Amask, IfcTimings.Amask);
+
+ // Configure chip select property registers
+ mMmioOps->Write ((UINTN)&IfcRegs->CsorCs[CS].Csor, IfcTimings.Csor);
+
+ return;
+}
+
+VOID
+NandInit(
+ VOID
+ )
+{
+ IFC_REGS* IfcRegs;
+ IFC_TIMINGS NandIfcTimings;
+
+ IfcRegs = (IFC_REGS*)PcdGet64 (PcdIfcBaseAddr);
+
+ // Get Nand Flash Timings
+ GetIfcNandFlashTimings (&NandIfcTimings);
+
+ // Validate chip select
+ if (NandIfcTimings.CS < IFC_CS_MAX) {
+ mNandCS = NandIfcTimings.CS;
+
+ // clear event registers
+ mMmioOps->Write ((UINTN)&IfcRegs->IfcNand.PgrdcmplEvtStat, ~0U);
+
+ mMmioOps->Write ((UINTN)&IfcRegs->IfcNand.NandEvterStat, ~0U);
+
+ // Enable error and event for any detected errors
+ mMmioOps->Write ((UINTN)&IfcRegs->IfcNand.NandEvterEn,
+ IFC_NAND_EVTER_EN_OPC_EN |
+ IFC_NAND_EVTER_EN_PGRDCMPL_EN |
+ IFC_NAND_EVTER_EN_FTOER_EN |
+ IFC_NAND_EVTER_EN_WPER_EN);
+ mMmioOps->Write ((UINTN)&IfcRegs->IfcNand.Ncfgr, 0x0);
+
+ SetTimings (mNandCS, NandIfcTimings);
+ }
+
+ return;
+}
+
+VOID
+FpgaInit (
+ VOID
+ )
+{
+ IFC_TIMINGS FpgaIfcTimings;
+
+ // Get Fpga Flash Timings
+ GetIfcFpgaTimings (&FpgaIfcTimings);
+
+ // Validate chip select
+ if (FpgaIfcTimings.CS < IFC_CS_MAX) {
+ mFpgaCS = FpgaIfcTimings.CS;
+ SetTimings (mFpgaCS, FpgaIfcTimings);
+ }
+
+ return;
+}
+
+VOID
+NorInit (
+ VOID
+ )
+{
+ IFC_TIMINGS NorIfcTimings;
+
+ // Get NOR Flash Timings
+ GetIfcNorFlashTimings (&NorIfcTimings);
+
+ // Validate chip select
+ if (NorIfcTimings.CS < IFC_CS_MAX) {
+ mNorCS = NorIfcTimings.CS;
+ SetTimings (mNorCS, NorIfcTimings);
+ }
+
+ return;
+}
+
+//
+// IFC has NOR , NAND and FPGA
+//
+VOID
+IfcInit (
+ VOID
+ )
+{
+ mMmioOps = GetMmioOperations32 (FixedPcdGetBool (PcdIfcBigEndian));
+
+ NorInit();
+ NandInit();
+ FpgaInit();
+
+ return;
+}
diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.h b/Silicon/NXP/Library/IfcLib/IfcLib.h
new file mode 100644
index 0000000..38ce247
--- /dev/null
+++ b/Silicon/NXP/Library/IfcLib/IfcLib.h
@@ -0,0 +1,190 @@
+/** @IfcLib.h
+
+ The integrated flash controller (IFC) is used to interface with external asynchronous/
+ synchronous NAND flash, asynchronous NOR flash, SRAM, generic ASIC memory and
+ EPROM.
+ It has eight chip-selects, to which a maximum of eight flash devices can be attached,
+ although only one of these can be accessed at any given time.
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __IFC_LIB_H__
+#define __IFC_LIB_H__
+
+#include <Ifc.h>
+#include <Uefi.h>
+
+#define IFC_NAND_RESERVED_SIZE FixedPcdGet32 (PcdIfcNandReservedSize)
+
+typedef enum {
+ IFC_FTIM0 = 0,
+ IFC_FTIM1,
+ IFC_FTIM2,
+ IFC_FTIM3,
+} IFC_FTIMS;
+
+typedef struct {
+ UINT32 CsprExt;
+ UINT32 Cspr;
+ UINT32 Res;
+} IFC_CSPR;
+
+typedef struct {
+ UINT32 Amask;
+ UINT32 Res[0x2];
+} IFC_AMASK;
+
+typedef struct {
+ UINT32 Csor;
+ UINT32 CsorExt;
+ UINT32 Res;
+} IFC_CSOR;
+
+typedef struct {
+ UINT32 Ftim[4];
+ UINT32 Res[0x8];
+}IFC_FTIM ;
+
+typedef struct {
+ UINT32 Ncfgr;
+ UINT32 Res1[0x4];
+ UINT32 NandFcr0;
+ UINT32 NandFcr1;
+ UINT32 Res2[0x8];
+ UINT32 Row0;
+ UINT32 Res3;
+ UINT32 Col0;
+ UINT32 Res4;
+ UINT32 Row1;
+ UINT32 Res5;
+ UINT32 Col1;
+ UINT32 Res6;
+ UINT32 Row2;
+ UINT32 Res7;
+ UINT32 Col2;
+ UINT32 Res8;
+ UINT32 Row3;
+ UINT32 Res9;
+ UINT32 Col3;
+ UINT32 Res10[0x24];
+ UINT32 NandFbcr;
+ UINT32 Res11;
+ UINT32 NandFir0;
+ UINT32 NandFir1;
+ UINT32 nandFir2;
+ UINT32 Res12[0x10];
+ UINT32 NandCsel;
+ UINT32 Res13;
+ UINT32 NandSeqStrt;
+ UINT32 Res14;
+ UINT32 NandEvterStat;
+ UINT32 Res15;
+ UINT32 PgrdcmplEvtStat;
+ UINT32 Res16[0x2];
+ UINT32 NandEvterEn;
+ UINT32 Res17[0x2];
+ UINT32 NandEvterIntrEn;
+ UINT32 Res18[0x2];
+ UINT32 NandErattr0;
+ UINT32 NandErattr1;
+ UINT32 Res19[0x10];
+ UINT32 NandFsr;
+ UINT32 Res20;
+ UINT32 NandEccstat[4];
+ UINT32 Res21[0x20];
+ UINT32 NanNdcr;
+ UINT32 Res22[0x2];
+ UINT32 NandAutobootTrgr;
+ UINT32 Res23;
+ UINT32 NandMdr;
+ UINT32 Res24[0x5C];
+} IFC_NAND;
+
+/*
+ * IFC controller NOR Machine registers
+ */
+typedef struct {
+ UINT32 NorEvterStat;
+ UINT32 Res1[0x2];
+ UINT32 NorEvterEn;
+ UINT32 Res2[0x2];
+ UINT32 NorEvterIntrEn;
+ UINT32 Res3[0x2];
+ UINT32 NorErattr0;
+ UINT32 NorErattr1;
+ UINT32 NorErattr2;
+ UINT32 Res4[0x4];
+ UINT32 NorCr;
+ UINT32 Res5[0xEF];
+} IFC_NOR;
+
+/*
+ * IFC controller GPCM Machine registers
+ */
+typedef struct {
+ UINT32 GpcmEvterStat;
+ UINT32 Res1[0x2];
+ UINT32 GpcmEvterEn;
+ UINT32 Res2[0x2];
+ UINT32 gpcmEvterIntrEn;
+ UINT32 Res3[0x2];
+ UINT32 GpcmErattr0;
+ UINT32 GpcmErattr1;
+ UINT32 GcmErattr2;
+ UINT32 GpcmStat;
+} IFC_GPCM;
+
+/*
+ * IFC Controller Registers
+ */
+typedef struct {
+ UINT32 IfcRev;
+ UINT32 Res1[0x2];
+ IFC_CSPR CsprCs[IFC_BANK_COUNT];
+ UINT8 Res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
+ IFC_AMASK AmaskCs[IFC_BANK_COUNT];
+ UINT8 Res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
+ IFC_CSOR CsorCs[IFC_BANK_COUNT];
+ UINT8 Res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
+ IFC_FTIM FtimCs[IFC_BANK_COUNT];
+ UINT8 Res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
+ UINT32 RbStat;
+ UINT32 RbMap;
+ UINT32 WpMap;
+ UINT32 IfcGcr;
+ UINT32 Res7[0x2];
+ UINT32 CmEvter_stat;
+ UINT32 Res8[0x2];
+ UINT32 CmEvterEn;
+ UINT32 Res9[0x2];
+ UINT32 CmEvterIntrEn;
+ UINT32 Res10[0x2];
+ UINT32 CmErattr0;
+ UINT32 CmErattr1;
+ UINT32 Res11[0x2];
+ UINT32 IfcCcr;
+ UINT32 IfcCsr;
+ UINT32 DdrCcrLow;
+ UINT32 Res12[IFC_NAND_RESERVED_SIZE];
+ IFC_NAND IfcNand;
+ IFC_NOR IfcNor;
+ IFC_GPCM IfcGpcm;
+} IFC_REGS;
+
+extern VOID GetIfcNorFlashTimings (IFC_TIMINGS * NorIfcTimings);
+
+extern VOID GetIfcFpgaTimings (IFC_TIMINGS *FpgaIfcTimings);
+
+extern VOID GetIfcNandFlashTimings (IFC_TIMINGS * NandIfcTimings);
+
+#endif //__IFC_LIB_H__
diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.inf b/Silicon/NXP/Library/IfcLib/IfcLib.inf
new file mode 100644
index 0000000..989eb44
--- /dev/null
+++ b/Silicon/NXP/Library/IfcLib/IfcLib.inf
@@ -0,0 +1,38 @@
+# IfcLib.inf
+#
+# Component description file for IFC Library
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = IfcLib
+ FILE_GUID = a465d76c-0785-4ee7-bd72-767983d575a2
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = IfcLib
+
+[Sources.common]
+ IfcLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BoardLib
+ IoAccessLib
+
+[FixedPcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index df64ad6..bd89da4 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -77,6 +77,7 @@
gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000128
gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129
gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0|UINT64|0x0000012B
#
# IFC PCDs
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 14/41] Silicon/NXP : Add support for FpgaLib.
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (12 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 13/41] Silicon/NXP : Add support of IfcLib Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-19 17:37 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 15/41] LS1043 : Enable support of FpgaLib Meenakshi Aggarwal
` (28 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
FpgaLib export FPGA_READ and FPGA_WRITE function and
provide a function to print Board personality.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Include/Library/FpgaLib.h | 97 +++++++++++++++++++++
Silicon/NXP/Library/FpgaLib/FpgaLib.c | 145 ++++++++++++++++++++++++++++++++
Silicon/NXP/Library/FpgaLib/FpgaLib.inf | 34 ++++++++
3 files changed, 276 insertions(+)
create mode 100644 Silicon/NXP/Include/Library/FpgaLib.h
create mode 100644 Silicon/NXP/Library/FpgaLib/FpgaLib.c
create mode 100644 Silicon/NXP/Library/FpgaLib/FpgaLib.inf
diff --git a/Silicon/NXP/Include/Library/FpgaLib.h b/Silicon/NXP/Include/Library/FpgaLib.h
new file mode 100644
index 0000000..847689c
--- /dev/null
+++ b/Silicon/NXP/Include/Library/FpgaLib.h
@@ -0,0 +1,97 @@
+/** FpgaLib.h
+* Header defining the Fpga specific constants (Base addresses, sizes, flags)
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __LS1_FPGA_H__
+#define __LS1_FPGA_H__
+
+/*
+ * FPGA register set of board.
+ */
+typedef struct {
+ UINT8 FpgaVersionMajor; /* 0x0 - FPGA Major Revision Register */
+ UINT8 FpgaVersionMinor; /* 0x1 - FPGA Minor Revision Register */
+ UINT8 PcbaVersion; /* 0x2 - PCBA Revision Register */
+ UINT8 SystemReset; /* 0x3 - system reset register */
+ UINT8 SoftMuxOn; /* 0x4 - Switch Control Enable Register */
+ UINT8 RcwSource1; /* 0x5 - Reset config word 1 */
+ UINT8 RcwSource2; /* 0x6 - Reset config word 2 */
+ UINT8 Vbank; /* 0x7 - Flash bank selection Control */
+ UINT8 SysclkSelect; /* 0x8 - System clock selection Control */
+ UINT8 UartSel; /* 0x9 - Uart selection Control */
+ UINT8 Sd1RefClkSel; /* 0xA - Serdes1 reference clock selection Control */
+ UINT8 TdmClkMuxSel; /* 0xB - TDM Clock Mux selection Control */
+ UINT8 SdhcSpiCsSel; /* 0xC - SDHC/SPI Chip select selection Control */
+ UINT8 StatusLed; /* 0xD - Status Led */
+ UINT8 GlobalReset; /* 0xE - Global reset */
+ UINT8 SdEmmc; /* 0xF - SD or EMMC Interface Control Regsiter */
+ UINT8 VddEn; /* 0x10 - VDD Voltage Control Enable Register */
+ UINT8 VddSel; /* 0x11 - VDD Voltage Control Register */
+} FPGA_REG_SET;
+
+/**
+ Function to read FPGA register.
+**/
+UINT8
+FpgaRead (
+ UINTN Reg
+ );
+
+/**
+ Function to write FPGA register.
+**/
+VOID
+FpgaWrite (
+ UINTN Reg,
+ UINT8 Value
+ );
+
+/**
+ Function to read FPGA revision.
+**/
+VOID
+FpgaRevBit (
+ UINT8 *Value
+ );
+
+/**
+ Function to initialize FPGA timings.
+**/
+VOID
+FpgaInit (
+ VOID
+ );
+
+/**
+ Function to print board personality.
+**/
+VOID
+PrintBoardPersonality (
+ VOID
+ );
+
+#define FPGA_BASE_PHYS 0x7fb00000
+
+#define SRC_VBANK 0x25
+#define SRC_NAND 0x106
+#define SRC_QSPI 0x44
+#define SRC_SD 0x40
+
+#define SERDES_FREQ1 "100.00 MHz"
+#define SERDES_FREQ2 "156.25 MHz"
+
+#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg))
+#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), Value)
+
+#endif
diff --git a/Silicon/NXP/Library/FpgaLib/FpgaLib.c b/Silicon/NXP/Library/FpgaLib/FpgaLib.c
new file mode 100644
index 0000000..93e9a90
--- /dev/null
+++ b/Silicon/NXP/Library/FpgaLib/FpgaLib.c
@@ -0,0 +1,145 @@
+/** @FpgaLib.c
+ Fpga Library containing functions to program and read the Fpga registers.
+
+ FPGA is connected to IFC Controller and so MMIO APIs are used
+ to read/write FPGA registers
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/FpgaLib.h>
+#include <Library/IoLib.h>
+
+/**
+ Function to read FPGA register.
+
+ @param Reg Register offset of FPGA to read.
+
+**/
+UINT8
+FpgaRead (
+ IN UINTN Reg
+ )
+{
+ VOID *Base;
+
+ Base = (VOID *)FPGA_BASE_PHYS;
+
+ return MmioRead8 ((UINTN)(Base + Reg));
+}
+
+/**
+ Function to write FPGA register.
+
+ @param Reg Register offset of FPGA to write.
+ @param Value Value to be written.
+
+**/
+VOID
+FpgaWrite (
+ IN UINTN Reg,
+ IN UINT8 Value
+ )
+{
+ VOID *Base;
+
+ Base = (VOID *)FPGA_BASE_PHYS;
+
+ MmioWrite8 ((UINTN)(Base + Reg), Value);
+}
+
+/**
+ Function to reverse the number.
+
+ @param *Value pointer to number to reverse.
+
+ @retval *Value reversed value.
+
+**/
+VOID
+FpgaRevBit (
+ OUT UINT8 *Value
+ )
+{
+ UINT8 Rev;
+ UINT8 Val;
+ UINTN Index;
+
+ Val = *Value;
+ Rev = Val & 1;
+ for (Index = 1; Index <= 7; Index++) {
+ Val >>= 1;
+ Rev <<= 1;
+ Rev |= Val & 1;
+ }
+
+ *Value = Rev;
+}
+
+/**
+ Function to print board personality.
+
+**/
+VOID
+PrintBoardPersonality (
+ VOID
+ )
+{
+ UINT8 RcwSrc1;
+ UINT8 RcwSrc2;
+ UINT32 RcwSrc;
+ UINT32 Sd1RefClkSel;
+
+ RcwSrc1 = FPGA_READ(RcwSource1);
+ RcwSrc2 = FPGA_READ(RcwSource2);
+ FpgaRevBit (&RcwSrc1);
+ RcwSrc = RcwSrc1;
+ RcwSrc = (RcwSrc << 1) | RcwSrc2;
+
+ switch (RcwSrc) {
+ case SRC_VBANK:
+ DEBUG ((DEBUG_INFO, "vBank: %d\n", FPGA_READ(Vbank)));
+ break;
+ case SRC_NAND:
+ DEBUG ((DEBUG_INFO, "NAND\n"));
+ break;
+ case SRC_QSPI:
+ DEBUG ((DEBUG_INFO, "QSPI vBank %d\n", FPGA_READ(Vbank)));
+ break;
+ case SRC_SD:
+ DEBUG ((DEBUG_INFO, "SD\n"));
+ break;
+ default:
+ DEBUG ((DEBUG_INFO, "Invalid setting of SW5\n"));
+ break;
+ }
+
+ DEBUG ((DEBUG_INFO, "FPGA: V%x.%x\nPCBA: V%x.0\n",
+ FPGA_READ(FpgaVersionMajor),
+ FPGA_READ(FpgaVersionMinor),
+ FPGA_READ(PcbaVersion)));
+
+ DEBUG ((DEBUG_INFO, "SERDES Reference Clocks:\n"));
+
+ Sd1RefClkSel = FPGA_READ(Sd1RefClkSel);
+ DEBUG ((DEBUG_INFO, "SD1_CLK1 = %a, SD1_CLK2 = %a\n",
+ Sd1RefClkSel ? SERDES_FREQ2 : SERDES_FREQ1, SERDES_FREQ1));
+ if (PcdGetBool (PcdSerdes2Enabled)) {
+ DEBUG ((DEBUG_INFO, "SD2_CLK1 = %a, SD2_CLK2 = %a\n",
+ SERDES_FREQ1, SERDES_FREQ1));
+ }
+
+ return;
+}
diff --git a/Silicon/NXP/Library/FpgaLib/FpgaLib.inf b/Silicon/NXP/Library/FpgaLib/FpgaLib.inf
new file mode 100644
index 0000000..c6c23ad
--- /dev/null
+++ b/Silicon/NXP/Library/FpgaLib/FpgaLib.inf
@@ -0,0 +1,34 @@
+# @FpgaLib.inf
+#
+# Copyright 2017 NXP
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001000A
+ BASE_NAME = FpgaLib
+ FILE_GUID = 5962d040-8b8a-11df-9a71-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = FpgaLib
+
+[Sources.common]
+ FpgaLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 15/41] LS1043 : Enable support of FpgaLib.
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (13 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 14/41] Silicon/NXP : Add support for FpgaLib Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 16/41] Silicon/NXP : Add support of NorFlashLib Meenakshi Aggarwal
` (27 subsequent siblings)
42 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 3 +++
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 2 ++
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 5 +++++
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 2 ++
4 files changed, 12 insertions(+)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index c2701fe..48a7b5a 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -38,6 +38,9 @@
SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
+ IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
+ BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
+ FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf
[PcdsFixedAtBuild.common]
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index 8395dfd..a4eb117 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -63,11 +63,13 @@
gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
#
# Big Endian IPs
#
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
##
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index 1875c3b..e79728e 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -19,11 +19,14 @@
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
+#include <Library/IfcLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
+extern VOID PrintBoardPersonality (VOID);
+
/**
Calculate the frequency of various controllers and
populate the passed structure with frequuencies.
@@ -162,6 +165,8 @@ SocInit (
//
PrintRCW ();
PrintSoc ();
+ IfcInit ();
+ PrintBoardPersonality ();
return;
}
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index d16288a..af0790f 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -29,6 +29,8 @@
[LibraryClasses]
BaseLib
DebugLib
+ FpgaLib
+ IfcLib
IoAccessLib
SerialPortLib
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 16/41] Silicon/NXP : Add support of NorFlashLib
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (14 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 15/41] LS1043 : Enable support of FpgaLib Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-19 18:13 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 17/41] Silicon/NXP : Add NOR driver Meenakshi Aggarwal
` (26 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
NorFlashLib interacts with the underlying IFC NOR controller.
This will be used by NOR driver for any information
exchange with NOR controller.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Include/Library/NorFlashLib.h | 77 +++
Silicon/NXP/Include/NorFlash.h | 44 ++
Silicon/NXP/Library/NorFlashLib/CfiCommand.h | 99 ++++
Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c | 210 +++++++
Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h | 53 ++
Silicon/NXP/Library/NorFlashLib/NorFlashLib.c | 696 +++++++++++++++++++++++
Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf | 43 ++
7 files changed, 1222 insertions(+)
create mode 100644 Silicon/NXP/Include/Library/NorFlashLib.h
create mode 100644 Silicon/NXP/Include/NorFlash.h
create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiCommand.h
create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
diff --git a/Silicon/NXP/Include/Library/NorFlashLib.h b/Silicon/NXP/Include/Library/NorFlashLib.h
new file mode 100644
index 0000000..defdc61
--- /dev/null
+++ b/Silicon/NXP/Include/Library/NorFlashLib.h
@@ -0,0 +1,77 @@
+/** @file
+
+ Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+ Copyright 2017 NXP
+
+This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ **/
+
+#ifndef _NOR_FLASH_LIB_H_
+#define _NOR_FLASH_LIB_H_
+
+#include <NorFlash.h>
+
+#define NOR_FLASH_DEVICE_COUNT 1
+
+typedef struct {
+ UINTN DeviceBaseAddress; // Start address of the Device Base Address (DBA)
+ UINTN RegionBaseAddress; // Start address of one single region
+ UINTN Size;
+ UINTN BlockSize;
+ UINTN MultiByteWordCount; // Maximum Word count that can be written to Nor Flash in multi byte write
+ UINTN WordWriteTimeOut; // single byte/word timeout usec
+ UINTN BufferWriteTimeOut; // buffer write timeout usec
+ UINTN BlockEraseTimeOut; // block erase timeout usec
+ UINTN ChipEraseTimeOut; // chip erase timeout usec
+} NorFlashDescription;
+
+EFI_STATUS
+NorFlashPlatformGetDevices (
+ OUT NorFlashDescription **NorFlashDevices,
+ OUT UINT32 *Count
+ );
+
+EFI_STATUS
+NorFlashPlatformFlashGetAttributes (
+ OUT NorFlashDescription *NorFlashDevices,
+ IN UINT32 Count
+ );
+
+EFI_STATUS
+NorFlashPlatformWriteBuffer (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+EFI_STATUS
+NorFlashPlatformEraseSector (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN SectorAddress
+ );
+
+EFI_STATUS
+NorFlashPlatformRead (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN UINTN BufferSizeInBytes,
+ OUT UINT8 *Buffer
+ );
+
+EFI_STATUS
+NorFlashPlatformReset (
+ IN UINTN Instance
+ );
+
+#endif /* _NOR_FLASH_LIB_H_ */
diff --git a/Silicon/NXP/Include/NorFlash.h b/Silicon/NXP/Include/NorFlash.h
new file mode 100644
index 0000000..8fa41d8
--- /dev/null
+++ b/Silicon/NXP/Include/NorFlash.h
@@ -0,0 +1,44 @@
+/** @NorFlash.h
+
+ Contains data structure shared by both NOR Library and Driver.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __NOR_FLASH_H__
+#define __NOR_FLASH_H__
+
+#include <Protocol/BlockIo.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+
+typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
+
+typedef struct {
+ VENDOR_DEVICE_PATH Vendor;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} NOR_FLASH_DEVICE_PATH;
+
+struct _NOR_FLASH_INSTANCE {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ UINTN DeviceBaseAddress;
+ UINTN RegionBaseAddress;
+ UINTN Size;
+ EFI_LBA StartLba;
+ EFI_BLOCK_IO_PROTOCOL BlockIoProtocol;
+ EFI_BLOCK_IO_MEDIA Media;
+ EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
+ VOID* ShadowBuffer;
+ NOR_FLASH_DEVICE_PATH DevicePath;
+};
+
+
+#endif /* __NOR_FLASH_H__ */
diff --git a/Silicon/NXP/Library/NorFlashLib/CfiCommand.h b/Silicon/NXP/Library/NorFlashLib/CfiCommand.h
new file mode 100644
index 0000000..8543227
--- /dev/null
+++ b/Silicon/NXP/Library/NorFlashLib/CfiCommand.h
@@ -0,0 +1,99 @@
+/** @CfiCommand.h
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __CFI_COMMAND_H__
+#define __CFI_COMMAND_H__
+
+// CFI Data "QRY"
+#define CFI_QRY_Q 0x51
+#define CFI_QRY_R 0x52
+#define CFI_QRY_Y 0x59
+#define CFI_QRY 0x515259
+
+#define ENTER_CFI_QUERY_MODE_ADDR 0x0055
+#define ENTER_CFI_QUERY_MODE_CMD 0x0098
+
+#define CFI_QUERY_UNIQUE_QRY_STRING 0x10
+
+// Offsets for CFI queries
+#define CFI_QUERY_TYP_TIMEOUT_WORD_WRITE 0x1F
+#define CFI_QUERY_TYP_TIMEOUT_MAX_BUFFER_WRITE 0x20
+#define CFI_QUERY_TYP_TIMEOUT_BLOCK_ERASE 0x21
+#define CFI_QUERY_TYP_TIMEOUT_CHIP_ERASE 0x22
+#define CFI_QUERY_MAX_TIMEOUT_WORD_WRITE 0x23
+#define CFI_QUERY_MAX_TIMEOUT_MAX_BUFFER_WRITE 0x24
+#define CFI_QUERY_MAX_TIMEOUT_BLOCK_ERASE 0x25
+#define CFI_QUERY_MAX_TIMEOUT_CHIP_ERASE 0x26
+#define CFI_QUERY_DEVICE_SIZE 0x27
+#define CFI_QUERY_MAX_NUM_BYTES_WRITE 0x2A
+#define CFI_QUERY_BLOCK_SIZE 0x2F
+
+// Unlock Address
+#define CMD_UNLOCK_1_ADDR 0x555
+#define CMD_UNLOCK_2_ADDR 0x2AA
+
+// RESET Command
+#define CMD_RESET_FIRST 0xAA
+#define CMD_RESET_SECOND 0x55
+#define CMD_RESET 0xF0
+
+// READ Command
+
+// Manufacturer ID
+#define CMD_READ_M_ID_FIRST 0xAA
+#define CMD_READ_M_ID_SECOND 0x55
+#define CMD_READ_M_ID_THIRD 0x90
+#define CMD_READ_M_ID_FOURTH 0x01
+
+// Device ID
+#define CMD_READ_D_ID_FIRST 0xAA
+#define CMD_READ_D_ID_SECOND 0x55
+#define CMD_READ_D_ID_THIRD 0x90
+#define CMD_READ_D_ID_FOURTH 0x7E
+#define CMD_READ_D_ID_FIFTH 0x13
+#define CMD_READ_D_ID_SIXTH 0x00
+
+// WRITE Command
+
+// PROGRAM Command
+#define CMD_PROGRAM_FIRST 0xAA
+#define CMD_PROGRAM_SECOND 0x55
+#define CMD_PROGRAM_THIRD 0xA0
+
+// Write Buffer Command
+#define CMD_WRITE_TO_BUFFER_FIRST 0xAA
+#define CMD_WRITE_TO_BUFFER_SECOND 0x55
+#define CMD_WRITE_TO_BUFFER_THIRD 0x25
+#define CMD_WRITE_TO_BUFFER_CONFIRM 0x29
+
+// ERASE Command
+
+// UNLOCK COMMANDS FOR ERASE
+#define CMD_ERASE_FIRST 0xAA
+#define CMD_ERASE_SECOND 0x55
+#define CMD_ERASE_THIRD 0x80
+#define CMD_ERASE_FOURTH 0xAA
+#define CMD_ERASE_FIFTH 0x55
+
+// Chip Erase Command
+#define CMD_CHIP_ERASE_SIXTH 0x10
+
+// Sector Erase Command
+#define CMD_SECTOR_ERASE_SIXTH 0x30
+
+// SUSPEND Command
+#define CMD_PROGRAM_OR_ERASE_SUSPEND 0xB0
+#define CMD_PROGRAM_OR_ERASE_RESUME 0x30
+
+#endif // __CFI_COMMAND_H__
diff --git a/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
new file mode 100644
index 0000000..941d5d4
--- /dev/null
+++ b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
@@ -0,0 +1,210 @@
+/** @CfiNorFlashLib.c
+
+ Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ **/
+
+#include <PiDxe.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+
+#include "CfiCommand.h"
+#include "CfiNorFlashLib.h"
+
+STATIC
+VOID
+NorFlashReadCfiData (
+ IN UINTN DeviceBaseAddress,
+ IN UINTN CfiOffset,
+ IN UINT32 Count,
+ OUT VOID *Data
+ )
+{
+ UINT32 Loop;
+ FLASH_DATA *TmpData = (FLASH_DATA *)Data;
+
+ for (Loop = 0; Loop < Count; Loop++, TmpData++) {
+ *TmpData = mMmioOps->Read ((UINTN)((FLASH_DATA*)DeviceBaseAddress + CfiOffset));
+ CfiOffset++;
+ }
+}
+
+/*
+ Currently we support only CFI flash devices; Bail-out otherwise
+*/
+EFI_STATUS
+CfiNorFlashFlashGetAttributes (
+ OUT NorFlashDescription *NorFlashDevices,
+ IN UINT32 Index
+ )
+{
+ UINT32 Count;
+ FLASH_DATA QryData[QRY_STRING_COUNT];
+ FLASH_DATA BlockSize[BLOCK_SIZE_COUNT];
+ UINTN DeviceBaseAddress;
+ FLASH_DATA MaxNumBytes[BLOCK_SIZE_COUNT];
+ FLASH_DATA Size;
+ FLASH_DATA HighByteMask; // Masks High byte in a UIN16 word
+ FLASH_DATA HighByteShift; // Bitshifts needed to make a byte High Byte in a UIN16 word
+ FLASH_DATA Temp1;
+ FLASH_DATA Temp2;
+ FLASH_DATA Z;
+
+ HighByteMask = 0xFF;
+ HighByteShift = 8;
+
+ for (Count = 0; Count < Index; Count++) {
+
+ NorFlashDevices[Count].DeviceBaseAddress = DeviceBaseAddress = PcdGet64 (PcdFlashDeviceBase64);
+
+ // Reset flash first
+ NorFlashPlatformReset (DeviceBaseAddress);
+
+ // Enter the CFI Query Mode
+ SEND_NOR_COMMAND (
+ DeviceBaseAddress,
+ ENTER_CFI_QUERY_MODE_ADDR,
+ ENTER_CFI_QUERY_MODE_CMD
+ );
+
+ MemoryFence();
+
+ // Query the unique QRY
+ NorFlashReadCfiData (
+ DeviceBaseAddress,
+ CFI_QUERY_UNIQUE_QRY_STRING,
+ QRY_STRING_COUNT,
+ &QryData
+ );
+
+ if ((QryData[0] != (FLASH_DATA)CFI_QRY_Q) ||
+ (QryData[1] != (FLASH_DATA)CFI_QRY_R) ||
+ (QryData[2] != (FLASH_DATA)CFI_QRY_Y)) {
+ DEBUG ((DEBUG_ERROR, "Not a CFI flash (QRY not recvd): "
+ "Got = 0x%04x, 0x%04x, 0x%04x\n",
+ QryData[0], QryData[1], QryData[2]));
+ return EFI_DEVICE_ERROR;
+ }
+
+ NorFlashReadCfiData (
+ DeviceBaseAddress,
+ CFI_QUERY_DEVICE_SIZE,
+ DEVICE_SIZE_COUNT,
+ &Size
+ );
+
+ // Refer CFI Specification [2^n in number of bytes.]
+ NorFlashDevices[Count].Size = 1 << Size;
+
+ NorFlashReadCfiData (
+ DeviceBaseAddress,
+ CFI_QUERY_BLOCK_SIZE,
+ BLOCK_SIZE_COUNT,
+ &BlockSize
+ );
+
+ // Refer CFI Specification [Erase block(s) within this region are (z) times 256 bytes in size.
+ // The value z = 0 is used for 128-byte block size.
+ Z = (FLASH_DATA)((BlockSize[1] << HighByteShift) | (BlockSize[0] & HighByteMask));
+ if (Z == 0) {
+ NorFlashDevices[Count].BlockSize = 128;
+ } else {
+ NorFlashDevices[Count].BlockSize = 256 * Z;
+ }
+
+ NorFlashReadCfiData (
+ DeviceBaseAddress,
+ CFI_QUERY_MAX_NUM_BYTES_WRITE,
+ BLOCK_SIZE_COUNT,
+ &MaxNumBytes
+ );
+
+ // Refer CFI Specification
+ /* from CFI query we get the Max. number of BYTE in multi-byte write = 2^N.
+ But our Flash Library is able to read/write in WORD size (2 bytes) which
+ is why we need to CONVERT MAX BYTES TO MAX WORDS by diving it by
+ width of word size */
+ NorFlashDevices[Count].MultiByteWordCount =\
+ (1 << ((FLASH_DATA)((MaxNumBytes[1] << HighByteShift) |
+ (MaxNumBytes[0] & HighByteMask))))/sizeof(FLASH_DATA);
+
+ NorFlashReadCfiData (
+ DeviceBaseAddress,
+ CFI_QUERY_TYP_TIMEOUT_WORD_WRITE,
+ WORD_WRITE_COUNT,
+ &Temp1
+ );
+
+ NorFlashReadCfiData (
+ DeviceBaseAddress,
+ CFI_QUERY_MAX_TIMEOUT_WORD_WRITE,
+ WORD_WRITE_COUNT,
+ &Temp2
+ );
+
+ NorFlashDevices[Count].WordWriteTimeOut = (1U << Temp1) * (1U << Temp2);
+
+ NorFlashReadCfiData (
+ DeviceBaseAddress,
+ CFI_QUERY_TYP_TIMEOUT_MAX_BUFFER_WRITE,
+ BUFFER_WRITE_COUNT,
+ &Temp1
+ );
+
+ NorFlashReadCfiData (
+ DeviceBaseAddress,
+ CFI_QUERY_MAX_TIMEOUT_MAX_BUFFER_WRITE,
+ BUFFER_WRITE_COUNT,
+ &Temp2
+ );
+
+ NorFlashDevices[Count].BufferWriteTimeOut = (1U << Temp1) * (1U << Temp2);
+
+ NorFlashReadCfiData (
+ DeviceBaseAddress,
+ CFI_QUERY_TYP_TIMEOUT_BLOCK_ERASE,
+ BLOCK_ERASE_COUNT,
+ &Temp1
+ );
+
+ NorFlashReadCfiData (
+ DeviceBaseAddress,
+ CFI_QUERY_MAX_TIMEOUT_BLOCK_ERASE,
+ BLOCK_ERASE_COUNT,
+ &Temp2
+ );
+
+ // Converting from millisecond to microseconds
+ NorFlashDevices[Count].BlockEraseTimeOut = (1U << Temp1) * (1U << Temp2) * 1000;
+
+ NorFlashReadCfiData (
+ DeviceBaseAddress,
+ CFI_QUERY_TYP_TIMEOUT_CHIP_ERASE,
+ CHIP_ERASE_COUNT,
+ &Temp1
+ );
+
+ NorFlashReadCfiData (
+ DeviceBaseAddress,
+ CFI_QUERY_MAX_TIMEOUT_CHIP_ERASE,
+ CHIP_ERASE_COUNT,
+ &Temp2
+ );
+
+ NorFlashDevices[Count].ChipEraseTimeOut = (1U << Temp1) * (1U << Temp2) * 1000;
+
+ // Put device back into Read Array mode (via Reset)
+ NorFlashPlatformReset (DeviceBaseAddress);
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
new file mode 100644
index 0000000..710f706
--- /dev/null
+++ b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
@@ -0,0 +1,53 @@
+/** @CfiNorFlashLib.h
+
+ Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __CFI_NOR_FLASH_LIB_H__
+#define __CFI_NOR_FLASH_LIB_H__
+
+#include <Library/DebugLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/NorFlashLib.h>
+
+extern MMIO_OPERATIONS_16 *mMmioOps;
+
+/*
+ * Values for the width of the port
+ */
+#define FLASH_CFI_8BIT 0x01
+#define FLASH_CFI_16BIT 0x02
+#define FLASH_CFI_32BIT 0x04
+#define FLASH_CFI_64BIT 0x08
+
+#define QRY_STRING_COUNT 3
+#define DEVICE_SIZE_COUNT 1
+#define BLOCK_SIZE_COUNT 2
+#define WORD_WRITE_COUNT 1
+#define BUFFER_WRITE_COUNT 1
+#define BLOCK_ERASE_COUNT 1
+#define CHIP_ERASE_COUNT 1
+
+#define CREATE_BYTE_OFFSET(OffsetAddr) ((sizeof (FLASH_DATA)) * (OffsetAddr))
+#define CREATE_NOR_ADDRESS(BaseAddr, OffsetAddr) ((BaseAddr) + (OffsetAddr))
+#define SEND_NOR_COMMAND(BaseAddr, Offset, Cmd) mMmioOps->Write (CREATE_NOR_ADDRESS (BaseAddr, CREATE_BYTE_OFFSET (Offset)), (Cmd))
+
+typedef UINT16 FLASH_DATA;
+
+EFI_STATUS
+CfiNorFlashFlashGetAttributes (
+ OUT NorFlashDescription *NorFlashDevices,
+ IN UINT32 Index
+ );
+
+#endif //__CFI_NOR_FLASH_LIB_H__
diff --git a/Silicon/NXP/Library/NorFlashLib/NorFlashLib.c b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
new file mode 100644
index 0000000..c89ddc3
--- /dev/null
+++ b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
@@ -0,0 +1,696 @@
+/** @NorFlashLib.c
+
+ Based on NorFlash implementation available in NorFlashDxe.c
+
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <Library/BaseMemoryLib/MemLibInternals.h>
+#include <Library/IoAccessLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+
+#include "CfiCommand.h"
+#include "CfiNorFlashLib.h"
+
+#define GET_BLOCK_OFFSET(Lba) ((Instance->RegionBaseAddress) -\
+ (Instance->DeviceBaseAddress) + ((UINTN)((Lba) * Instance->Media.BlockSize)))
+
+MMIO_OPERATIONS_16 *mMmioOps;
+
+NorFlashDescription mNorFlashDevices[NOR_FLASH_DEVICE_COUNT];
+
+STATIC VOID
+UnlockEraseAddress (
+ IN UINTN DeviceBaseAddress
+ )
+{ // Issue the Unlock cmds
+ SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, CMD_ERASE_FIRST);
+
+ SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR, CMD_ERASE_SECOND);
+
+ // Issue a setup command
+ SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, CMD_ERASE_THIRD);
+
+ // Issue the Unlock cmds
+ SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, CMD_ERASE_FOURTH);
+
+ SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR, CMD_ERASE_FIFTH);
+
+ return;
+}
+
+STATIC
+UINT64
+ConvertMicroSecondsToTicks (
+ IN UINTN MicroSeconds
+ )
+{
+ UINT64 TimerTicks64;
+
+ TimerTicks64 = 0;
+
+ // Calculate counter ticks that represent requested delay:
+ // = MicroSeconds x TICKS_PER_MICRO_SEC
+ // = MicroSeconds x Timer Frequency(in Hz) x 10^-6
+ // GetPerformanceCounterProperties = Get Arm Timer Frequency in Hz
+ TimerTicks64 = DivU64x32 (
+ MultU64x64 (
+ MicroSeconds,
+ GetPerformanceCounterProperties (NULL, NULL)
+ ),
+ 1000000U
+ );
+ return TimerTicks64;
+}
+
+/**
+ * The following function erases a NOR flash sector.
+ **/
+EFI_STATUS
+NorFlashPlatformEraseSector (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN SectorAddress
+ )
+{
+ FLASH_DATA EraseStatus1;
+ FLASH_DATA EraseStatus2;
+ UINT64 Timeout;
+ UINT64 SystemCounterVal;
+
+ EraseStatus1 = 0;
+ EraseStatus2 = 0;
+ Timeout = 0;
+
+ Timeout = ConvertMicroSecondsToTicks (mNorFlashDevices[Instance->Media.MediaId].BlockEraseTimeOut);
+
+ // Request a sector erase by writing two unlock cycles, followed by a
+ // setup command and two additional unlock cycles
+
+ UnlockEraseAddress (Instance->DeviceBaseAddress);
+
+ // Now send the address of the sector to be erased
+ SEND_NOR_COMMAND (SectorAddress, 0, CMD_SECTOR_ERASE_SIXTH);
+
+ // Wait for erase to complete
+ // Read Sector start address twice to detect bit toggle and to
+ // determine ERASE DONE (all bits are 1)
+ // Get the maximum timer ticks needed to complete the operation
+ // Check if operation is complete or not in continous loop?
+ // if complete, exit from loop
+ // if not check the ticks that have been passed from the begining of loop
+ // if Maximum Ticks allocated for operation has passed exit from loop
+
+ SystemCounterVal = GetPerformanceCounter ();
+ Timeout += SystemCounterVal;
+ while (SystemCounterVal < Timeout) {
+ if ((EraseStatus1 = mMmioOps->Read (SectorAddress))
+ == (EraseStatus2 = mMmioOps->Read (SectorAddress)))
+ {
+ if (mMmioOps->Read (SectorAddress) == 0xFFFF) {
+ break;
+ }
+ }
+ SystemCounterVal = GetPerformanceCounter ();
+ }
+
+ if (SystemCounterVal >= Timeout) {
+ DEBUG ((DEBUG_ERROR, "%a :Failed to Erase @ SectorAddress 0x%p, Timeout\n",
+ __FUNCTION__, SectorAddress));
+ return EFI_DEVICE_ERROR;
+ } else {
+ return EFI_SUCCESS;
+ }
+}
+
+EFI_STATUS
+NorFlashPlatformWriteWord (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN WordOffset,
+ IN FLASH_DATA Word
+ )
+{
+ UINT64 Timeout;
+ UINTN TargetAddress;
+ UINT64 SystemCounterVal;
+ FLASH_DATA Read1;
+ FLASH_DATA Read2;
+
+ Timeout = 0;
+
+ Timeout = ConvertMicroSecondsToTicks (mNorFlashDevices[Instance->Media.MediaId].WordWriteTimeOut);
+
+ TargetAddress = CREATE_NOR_ADDRESS (
+ Instance->DeviceBaseAddress,
+ CREATE_BYTE_OFFSET (WordOffset)
+ );
+
+ // Issue the Unlock cmds
+ SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR, CMD_PROGRAM_FIRST);
+
+ SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_2_ADDR, CMD_PROGRAM_SECOND);
+
+ SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR, CMD_PROGRAM_THIRD);
+
+ MmioWrite16 (TargetAddress, Word);
+
+ // Wait for Write to Complete
+ // Read the last written address twice to detect bit toggle and
+ // to determine if date is wriiten successfully or not ?
+ // Get the maximum timer ticks needed to complete the operation
+ // Check if operation is complete or not in continous loop?
+ // if complete, exit from loop
+ // if not check the ticks that have been passed from the begining of loop
+ // if Maximum Ticks allocated for operation has passed, then exit from loop
+
+ SystemCounterVal = GetPerformanceCounter ();
+ Timeout += SystemCounterVal;
+ while (SystemCounterVal < Timeout) {
+ if ((Read1 = MmioRead16 (TargetAddress))
+ == (Read2 = MmioRead16 (TargetAddress)))
+ {
+ if (Word == MmioRead16 (TargetAddress)) {
+ break;
+ }
+ }
+ SystemCounterVal = GetPerformanceCounter ();
+ }
+
+ if (SystemCounterVal >= Timeout) {
+ DEBUG ((DEBUG_ERROR, "%a: Failed to Write @ TargetAddress 0x%p, Timeout\n",
+ __FUNCTION__, TargetAddress));
+ return EFI_DEVICE_ERROR;
+ } else {
+ return EFI_SUCCESS;
+ }
+}
+
+EFI_STATUS
+NorFlashPlatformWritePageBuffer (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN PageBufferOffset,
+ IN UINTN NumWords,
+ IN FLASH_DATA *Buffer
+ )
+{
+ UINT64 Timeout;
+ UINTN LastWrittenAddress;
+ FLASH_DATA LastWritenData;
+ UINTN CurrentOffset;
+ UINTN EndOffset;
+ UINTN TargetAddress;
+ UINT64 SystemCounterVal;
+ FLASH_DATA Read1;
+ FLASH_DATA Read2;
+
+ // Initialize variables
+ Timeout = 0;
+ LastWrittenAddress = 0;
+ LastWritenData = 0;
+ CurrentOffset = PageBufferOffset;
+ EndOffset = PageBufferOffset + NumWords - 1;
+ Timeout = ConvertMicroSecondsToTicks (mNorFlashDevices[Instance->Media.MediaId].BufferWriteTimeOut);
+ TargetAddress = CREATE_NOR_ADDRESS (
+ Instance->DeviceBaseAddress,
+ CREATE_BYTE_OFFSET (CurrentOffset)
+ );
+
+ // don't try with a count of zero
+ if (!NumWords) {
+ return EFI_SUCCESS;
+ } else if (NumWords == 1) {
+ return NorFlashPlatformWriteWord (Instance, PageBufferOffset, *Buffer);
+ }
+
+ // Issue the Unlock cmds
+ SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR, CMD_WRITE_TO_BUFFER_FIRST);
+
+ SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_2_ADDR, CMD_WRITE_TO_BUFFER_SECOND);
+
+ // Write the buffer load
+ SEND_NOR_COMMAND (TargetAddress, 0, CMD_WRITE_TO_BUFFER_THIRD);
+
+ // Write # of locations to program
+ SEND_NOR_COMMAND (TargetAddress, 0, (NumWords - 1));
+
+ // Load Data into Buffer
+ while (CurrentOffset <= EndOffset) {
+ LastWrittenAddress = CREATE_NOR_ADDRESS (
+ Instance->DeviceBaseAddress,
+ CREATE_BYTE_OFFSET (CurrentOffset++)
+ );
+ LastWritenData = *Buffer++;
+
+ // Write Data
+ MmioWrite16 (LastWrittenAddress, LastWritenData);
+ }
+
+ // Issue the Buffered Program Confirm command
+ SEND_NOR_COMMAND (TargetAddress, 0, CMD_WRITE_TO_BUFFER_CONFIRM);
+
+ /* Wait for Write to Complete
+ Read the last written address twice to detect bit toggle and
+ to determine if date is wriiten successfully or not ?
+ Get the maximum timer ticks needed to complete the operation
+ Check if operation is complete or not in continous loop?
+ if complete, exit from loop
+ if not check the ticks that have been passed from the begining of loop
+ if Maximum Ticks allocated for operation has passed, then exit from loop **/
+ SystemCounterVal = GetPerformanceCounter();
+ Timeout += SystemCounterVal;
+ while (SystemCounterVal < Timeout) {
+ if ((Read1 = MmioRead16 (LastWrittenAddress))
+ == (Read2 = MmioRead16 (LastWrittenAddress)))
+ {
+ if (LastWritenData == MmioRead16 (LastWrittenAddress)) {
+ break;
+ }
+ }
+ SystemCounterVal = GetPerformanceCounter ();
+ }
+
+ if (SystemCounterVal >= Timeout) {
+ DEBUG ((DEBUG_ERROR, "%a: Failed to Write @LastWrittenAddress 0x%p, Timeout\n",
+ __FUNCTION__, LastWrittenAddress));
+ return EFI_DEVICE_ERROR;
+ } else {
+ return EFI_SUCCESS;
+ }
+}
+
+EFI_STATUS
+NorFlashPlatformWriteWordAlignedAddressBuffer (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN UINTN Offset,
+ IN UINTN NumWords,
+ IN FLASH_DATA *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINTN MultiByteWordCount;
+ UINTN Mask;
+ UINTN IntWords;
+
+ MultiByteWordCount = mNorFlashDevices[Instance->Media.MediaId].MultiByteWordCount;
+ Mask = MultiByteWordCount - 1;
+ IntWords = NumWords;
+ Status = EFI_SUCCESS;
+
+ if (Offset & Mask) {
+ // program only as much as necessary, so pick the lower of the two numbers
+ if (NumWords < (MultiByteWordCount - (Offset & Mask))) {
+ IntWords = NumWords;
+ } else {
+ IntWords = MultiByteWordCount - (Offset & Mask);
+ }
+
+ // program the first few to get write buffer aligned
+ Status = NorFlashPlatformWritePageBuffer (Instance, Offset, IntWords, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Offset += IntWords; // adjust pointers and counter
+ NumWords -= IntWords;
+ Buffer += IntWords;
+
+ if (NumWords == 0) {
+ return Status;
+ }
+ }
+
+ while (NumWords >= MultiByteWordCount) {// while big chunks to do
+ Status = NorFlashPlatformWritePageBuffer (
+ Instance,
+ Offset,
+ MultiByteWordCount,
+ Buffer
+ );
+ if (EFI_ERROR (Status)) {
+ return (Status);
+ }
+
+ Offset += MultiByteWordCount; // adjust pointers and counter
+ NumWords -= MultiByteWordCount;
+ Buffer += MultiByteWordCount;
+ }
+ if (NumWords == 0) {
+ return (Status);
+ }
+
+ Status = NorFlashPlatformWritePageBuffer (
+ Instance,
+ Offset,
+ NumWords,
+ Buffer
+ );
+ return (Status);
+}
+
+/**
+ Writes data to the NOR Flash using the Buffered Programming method.
+
+ Write Buffer Programming allows the system to write a maximum of 32 bytes
+ in one programming operation. Therefore this function will only handle
+ buffers up to 32 bytes.
+ To deal with larger buffers, call this function again.
+**/
+EFI_STATUS
+NorFlashPlatformWriteBuffer (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ FLASH_DATA *SrcBuffer;
+ UINTN TargetOffsetinBytes;
+ UINTN WordsToWrite;
+ UINTN Mask;
+ UINTN BufferSizeInBytes;
+ UINTN IntBytes;
+ VOID *CopyFrom;
+ VOID *CopyTo;
+ FLASH_DATA TempWrite;
+
+ SrcBuffer = (FLASH_DATA *)Buffer;
+ TargetOffsetinBytes = 0;
+ WordsToWrite = 0;
+ Mask = sizeof (FLASH_DATA) - 1;
+ BufferSizeInBytes = *NumBytes;
+ IntBytes = BufferSizeInBytes; // Intermediate Bytes needed to copy for alignment
+ TempWrite = 0;
+
+ DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=%ld, Offset=0x%x, "
+ "*NumBytes=0x%x, Buffer @ 0x%08x)\n",
+ __FUNCTION__, Lba, Offset, *NumBytes, Buffer));
+
+ TargetOffsetinBytes = GET_BLOCK_OFFSET (Lba) + (UINTN)(Offset);
+
+ if (TargetOffsetinBytes & Mask) {
+ // Write only as much as necessary, so pick the lower of the two numbers
+ // and call it Intermediate bytes to write to make alignment proper
+ if (BufferSizeInBytes < (sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask))) {
+ IntBytes = BufferSizeInBytes;
+ } else {
+ IntBytes = sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask);
+ }
+
+ // Read the first few to get Read buffer aligned
+ NorFlashPlatformRead (
+ Instance,
+ Lba,
+ (TargetOffsetinBytes & ~Mask) - GET_BLOCK_OFFSET (Lba),
+ sizeof (TempWrite),
+ (UINT8*)&TempWrite
+ );
+
+ CopyTo = (UINT8*)&TempWrite;
+ CopyTo += (TargetOffsetinBytes & Mask);
+ CopyFrom = Buffer;
+
+ CopyMem (CopyTo, CopyFrom, IntBytes);
+
+ Status = NorFlashPlatformWriteWordAlignedAddressBuffer (
+ Instance,
+ (UINTN)((TargetOffsetinBytes & ~Mask) / sizeof (FLASH_DATA)),
+ 1,
+ &TempWrite);
+ if (EFI_ERROR (Status)) {
+ DEBUG((DEBUG_ERROR, "%a : Failed to Write @TargetOffset 0x%x (0x%x)\n",
+ __FUNCTION__, TargetOffsetinBytes, Status));
+ goto EXIT;
+ }
+
+ TargetOffsetinBytes += IntBytes; /* adjust pointers and counter */
+ BufferSizeInBytes -= IntBytes;
+ Buffer += IntBytes;
+
+ if (BufferSizeInBytes == 0) {
+ goto EXIT;
+ }
+ }
+
+ // Write the bytes to CFI width aligned address.
+ // Note we can Write number of bytes=CFI width in one operation
+ WordsToWrite = BufferSizeInBytes / sizeof (FLASH_DATA);
+ SrcBuffer = (FLASH_DATA*)Buffer;
+
+ Status = NorFlashPlatformWriteWordAlignedAddressBuffer (
+ Instance,
+ (UINTN)(TargetOffsetinBytes/sizeof (FLASH_DATA)),
+ WordsToWrite,
+ SrcBuffer);
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "%a : Failed to Write @ TargetOffset 0x%x (0x%x)\n",
+ __FUNCTION__, TargetOffsetinBytes, Status));
+ goto EXIT;
+ }
+
+ BufferSizeInBytes -= (WordsToWrite * sizeof (FLASH_DATA));
+ Buffer += (WordsToWrite*sizeof (FLASH_DATA));
+ TargetOffsetinBytes += (WordsToWrite * sizeof (FLASH_DATA));
+
+ if (BufferSizeInBytes == 0) {
+ goto EXIT;
+ }
+
+ // Now Write bytes that are remaining and are less than CFI width.
+ // Read the first few to get Read buffer aligned
+ NorFlashPlatformRead (
+ Instance,
+ Lba,
+ TargetOffsetinBytes - GET_BLOCK_OFFSET (Lba),
+ sizeof (TempWrite),
+ (UINT8*)&TempWrite);
+
+ CopyFrom = Buffer;
+ CopyTo = &TempWrite;
+
+ CopyMem (CopyTo, CopyFrom, BufferSizeInBytes);
+
+ Status = NorFlashPlatformWriteWordAlignedAddressBuffer (
+ Instance,
+ (UINTN)(TargetOffsetinBytes/sizeof (FLASH_DATA)),
+ 1,
+ &TempWrite
+ );
+
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "%a: Failed to Write @TargetOffset 0x%x Status=%d\n",
+ __FUNCTION__, TargetOffsetinBytes, Status));
+ goto EXIT;
+ }
+
+EXIT:
+ // Put device back into Read Array mode (via Reset)
+ NorFlashPlatformReset (Instance->DeviceBaseAddress);
+ return (Status);
+}
+
+EFI_STATUS
+NorFlashPlatformRead (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN UINTN BufferSizeInBytes,
+ OUT UINT8 *Buffer
+ )
+{
+ UINTN IntBytes;
+ UINTN Mask;
+ FLASH_DATA TempRead;
+ VOID *CopyFrom;
+ VOID *CopyTo;
+ UINTN TargetOffsetinBytes;
+ FLASH_DATA *ReadData;
+ UINTN BlockSize;
+
+ IntBytes = BufferSizeInBytes; //Intermediate Bytes needed to copy for alignment
+ Mask = sizeof (FLASH_DATA) - 1;
+ TempRead = 0;
+ TargetOffsetinBytes = (UINTN)(GET_BLOCK_OFFSET (Lba) + Offset);
+ BlockSize = Instance->Media.BlockSize;
+
+ DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=%ld, Offset=0x%x,"
+ " BufferSizeInBytes=0x%x, Buffer @ 0x%p)\n",
+ __FUNCTION__, Lba, Offset, BufferSizeInBytes, Buffer));
+
+ // The buffer must be valid
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Return if we have not any byte to read
+ if (BufferSizeInBytes == 0) {
+ return EFI_SUCCESS;
+ }
+
+ if (((Lba * BlockSize) + BufferSizeInBytes) > Instance->Size) {
+ DEBUG ((DEBUG_ERROR, "%a : Read will exceed device size.\n", __FUNCTION__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Put device back into Read Array mode (via Reset)
+ NorFlashPlatformReset (Instance->DeviceBaseAddress);
+
+ // First Read bytes to make buffer aligned to CFI width
+ if (TargetOffsetinBytes & Mask) {
+ // Read only as much as necessary, so pick the lower of the two numbers
+ if (BufferSizeInBytes < (sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask))) {
+ IntBytes = BufferSizeInBytes;
+ } else {
+ IntBytes = sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask);
+ }
+
+ // Read the first few to get Read buffer aligned
+ TempRead = MmioRead16 (
+ CREATE_NOR_ADDRESS (
+ Instance->DeviceBaseAddress,
+ CREATE_BYTE_OFFSET ((TargetOffsetinBytes & ~Mask) / sizeof (FLASH_DATA))
+ )
+ );
+
+ CopyFrom = (UINT8*)&TempRead;
+ CopyFrom += (TargetOffsetinBytes & Mask);
+ CopyTo = Buffer;
+
+ CopyMem (CopyTo, CopyFrom, IntBytes);
+
+ TargetOffsetinBytes += IntBytes; // adjust pointers and counter
+ BufferSizeInBytes -= IntBytes;
+ Buffer += IntBytes;
+ if (BufferSizeInBytes == 0) {
+ return EFI_SUCCESS;
+ }
+ }
+
+ ReadData = (FLASH_DATA*)Buffer;
+
+ // Readout the bytes from CFI width aligned address.
+ // Note we can read number of bytes=CFI width in one operation
+ while (BufferSizeInBytes >= sizeof (FLASH_DATA)) {
+ *ReadData = MmioRead16 (
+ CREATE_NOR_ADDRESS (
+ Instance->DeviceBaseAddress,
+ CREATE_BYTE_OFFSET (TargetOffsetinBytes / sizeof (FLASH_DATA))
+ )
+ );
+ ReadData += 1;
+ BufferSizeInBytes -= sizeof (FLASH_DATA);
+ TargetOffsetinBytes += sizeof (FLASH_DATA);
+ }
+
+ if (BufferSizeInBytes == 0) {
+ return EFI_SUCCESS;
+ }
+
+ // Now read bytes that are remaining and are less than CFI width.
+ CopyTo = ReadData;
+ // Read the first few to get Read buffer aligned
+ TempRead = MmioRead16 (
+ CREATE_NOR_ADDRESS (
+ Instance->DeviceBaseAddress,
+ CREATE_BYTE_OFFSET (TargetOffsetinBytes/sizeof (FLASH_DATA))
+ )
+ );
+ CopyFrom = &TempRead;
+
+ CopyMem (CopyTo, CopyFrom, BufferSizeInBytes);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NorFlashPlatformReset (
+ IN UINTN DeviceBaseAddress
+ )
+{
+ SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, CMD_RESET_FIRST);
+
+ SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR, CMD_RESET_SECOND);
+
+ SEND_NOR_COMMAND (DeviceBaseAddress, 0, CMD_RESET);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+NorFlashInitMmioOps (
+ VOID
+ )
+{
+ mMmioOps = GetMmioOperations16 (FixedPcdGetBool (PcdIfcBigEndian));
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NorFlashPlatformGetDevices (
+ OUT NorFlashDescription **NorFlashDevices,
+ OUT UINT32 *Count
+ )
+{
+ // This is the function to be called, before using
+ if ((NorFlashDevices == NULL) || (Count == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Get the number of NOR flash devices supported
+ *NorFlashDevices = mNorFlashDevices;
+ *Count = NOR_FLASH_DEVICE_COUNT;
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NorFlashPlatformFlashGetAttributes (
+ OUT NorFlashDescription *NorFlashDevices,
+ IN UINT32 Count
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Index;
+
+ if ((NorFlashDevices == NULL) || (Count == 0)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Check the attributes of the NOR flash slave we are connected to.
+ // Currently we support only CFI flash devices. Bail-out otherwise.
+ Status = CfiNorFlashFlashGetAttributes (NorFlashDevices, Count);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Limit the Size of Nor Flash that can be programmed
+ for (Index = 0; Index < Count; Index++) {
+ NorFlashDevices[Index].RegionBaseAddress = PcdGet64 (PcdFlashReservedRegionBase64);
+ NorFlashDevices[Index].Size -= (NorFlashDevices[Index].RegionBaseAddress -
+ NorFlashDevices[Index].DeviceBaseAddress);
+ if ((NorFlashDevices[Index].RegionBaseAddress - NorFlashDevices[Index].DeviceBaseAddress)
+ % NorFlashDevices[Index].BlockSize)
+ {
+ DEBUG ((DEBUG_ERROR, "%a : Reserved Region(0x%p) doesn't start "
+ "from block boundry(0x%08x)\n", __FUNCTION__,
+ (UINTN)NorFlashDevices[Index].RegionBaseAddress,
+ (UINT32)NorFlashDevices[Index].BlockSize));
+ return EFI_DEVICE_ERROR;
+ }
+ }
+ return Status;
+}
diff --git a/Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
new file mode 100644
index 0000000..e0370b9
--- /dev/null
+++ b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
@@ -0,0 +1,43 @@
+# @NorFlashLib.inf
+#
+# Component description file for NorFlashLib module
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = NorFlashLib
+ FILE_GUID = f3176a49-dde1-450d-a909-8580c03b9ba8
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NorFlashLib
+ CONSTRUCTOR = NorFlashInitMmioOps
+
+[Sources.common]
+ CfiNorFlashLib.c
+ NorFlashLib.c
+
+[LibraryClasses]
+ ArmLib
+ IoAccessLib
+ TimerLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[Pcd.common]
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 17/41] Silicon/NXP : Add NOR driver.
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (15 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 16/41] Silicon/NXP : Add support of NorFlashLib Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-19 18:32 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 18/41] LS1043 : Enable NOR driver for LS1043aRDB package Meenakshi Aggarwal
` (25 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Add NOR DXE phase driver, it installs BlockIO and Fvp
protocol.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 98 +++
.../NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c | 252 +++++++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c | 503 +++++++++++++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h | 146 ++++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf | 65 ++
Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c | 816 +++++++++++++++++++++
6 files changed, 1880 insertions(+)
create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c
diff --git a/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
new file mode 100644
index 0000000..e254337
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,98 @@
+## @file
+# FDF include file with FD definition that defines an empty variable store.
+#
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+##
+
+[FD.LS1043aRdbNv_EFI]
+BaseAddress = 0x60300000 #The base address of the FLASH device
+Size = 0x000C0000 #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xC0000
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
+DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
+DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE = 0x00040000
+DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE = 0x00040000
+
+#############################################################################
+# LS1043ARDB NVRAM Area
+# LS1043ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#############################################################################
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0xC0000
+ 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0xC2, 0xF9, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
+ 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiAuthenticatedVariableGuid =
+ # { 0xaaf32c78, 0x947b, 0x439a,
+ # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+ # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xFF, 0x03, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
new file mode 100644
index 0000000..bc49fdc
--- /dev/null
+++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
@@ -0,0 +1,252 @@
+/** @NorFlashBlockIoDxe.c
+
+ Based on NorFlash implementation available in
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
+
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/NorFlashLib.h>
+
+#include <NorFlash.h>
+#include "NorFlashDxe.h"
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReset (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_BLKIO_THIS (This);
+
+ DEBUG ((DEBUG_INFO, "NorFlashBlockIoReset (MediaId=0x%x)\n",
+ This->Media->MediaId));
+
+ return NorFlashPlatformReset (Instance->DeviceBaseAddress);
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReadBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+ EFI_STATUS Status;
+ EFI_BLOCK_IO_MEDIA *Media;
+ UINTN NumBlocks;
+ UINT8 *ReadBuffer;
+ UINTN BlockCount;
+ UINTN BlockSizeInBytes;
+ EFI_LBA CurrentBlock;
+
+ Status = EFI_SUCCESS;
+
+ if ((This == NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Instance = INSTANCE_FROM_BLKIO_THIS (This);
+ Media = This->Media;
+
+ if (Media == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a : Media is NULL\n", __FUNCTION__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ NumBlocks = BufferSizeInBytes / Instance->Media.BlockSize ;
+
+ DEBUG ((DEBUG_BLKIO,
+ "%a : (MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%p)\n",
+ __FUNCTION__, MediaId, Lba, BufferSizeInBytes, Buffer));
+
+ if (!Media->MediaPresent) {
+ return EFI_NO_MEDIA;
+ }
+ if (Media->MediaId != MediaId) {
+ return EFI_MEDIA_CHANGED;
+ }
+ if ((Media->IoAlign >= 2) && (((UINTN)Buffer & (Media->IoAlign - 1)) != 0)) {
+ return EFI_INVALID_PARAMETER;
+ }
+ if (BufferSizeInBytes == 0) {
+ // Return if we have not any byte to read
+ return EFI_SUCCESS;
+ }
+ if ((BufferSizeInBytes % Media->BlockSize) != 0) {
+ // The size of the buffer must be a multiple of the block size
+ DEBUG ((DEBUG_ERROR, "%a : BlockSize in bytes = 0x%x\n", __FUNCTION__, BufferSizeInBytes));
+ return EFI_INVALID_PARAMETER;
+ }
+ if ((Lba + NumBlocks - 1) > Media->LastBlock) {
+ // All blocks must be within the device
+ DEBUG ((DEBUG_ERROR, "%a : Read will exceed last block %d, %d, %d \n",
+ __FUNCTION__, Lba, NumBlocks, Media->LastBlock));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ BlockSizeInBytes = Instance->Media.BlockSize;
+
+ /* Because the target *Buffer is a pointer to VOID,
+ * we must put all the data into a pointer
+ * to a proper data type, so use *ReadBuffer */
+ ReadBuffer = (UINT8 *)Buffer;
+
+ CurrentBlock = Lba;
+ // Read data block by Block
+ for (BlockCount = 0; BlockCount < NumBlocks; BlockCount++) {
+ DEBUG ((DEBUG_BLKIO, "%a: Reading block #%d\n", __FUNCTION__, (UINTN)CurrentBlock));
+
+ Status = NorFlashPlatformRead (Instance, CurrentBlock, (UINTN)0 ,
+ BlockSizeInBytes, ReadBuffer);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+
+ CurrentBlock++;
+ ReadBuffer = ReadBuffer + BlockSizeInBytes;
+ }
+
+ return Status;
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoWriteBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID *Buffer
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+ EFI_STATUS Status;
+ EFI_BLOCK_IO_MEDIA *Media;
+ UINTN NumBlocks;
+ EFI_LBA CurrentBlock;
+ UINTN BlockSizeInBytes;
+ UINT32 BlockCount;
+ UINTN SectorAddress;
+ UINT8 *WriteBuffer;
+
+ Status = EFI_SUCCESS;
+
+ if ((This == NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Instance = INSTANCE_FROM_BLKIO_THIS (This);
+ Media = This->Media;
+
+ if (Media == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a : Media is NULL\n", __FUNCTION__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ NumBlocks = BufferSizeInBytes / Instance->Media.BlockSize ;
+
+ DEBUG ((DEBUG_BLKIO,
+ "%a : (MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB) BufferPtr @ 0x%08x)\n",
+ __FUNCTION__, MediaId, Lba, BufferSizeInBytes, Buffer));
+
+ if (!Media->MediaPresent) {
+ return EFI_NO_MEDIA;
+ }
+ if (Media->MediaId != MediaId) {
+ return EFI_MEDIA_CHANGED;
+ }
+ if (Media->ReadOnly) {
+ return EFI_WRITE_PROTECTED;
+ }
+ if (BufferSizeInBytes == 0) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+ if ((BufferSizeInBytes % Media->BlockSize) != 0) {
+ // The size of the buffer must be a multiple of the block size
+ DEBUG ((DEBUG_ERROR, "%a : BlockSize in bytes = 0x%x\n",__FUNCTION__, BufferSizeInBytes));
+ return EFI_INVALID_PARAMETER;
+ }
+ if ((Lba + NumBlocks - 1) > Media->LastBlock) {
+ // All blocks must be within the device
+ DEBUG ((DEBUG_ERROR, "%a: Write will exceed last block %d, %d, %d \n",
+ __FUNCTION__,Lba, NumBlocks, Media->LastBlock));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ BlockSizeInBytes = Instance->Media.BlockSize;
+
+ WriteBuffer = (UINT8 *)Buffer;
+
+ CurrentBlock = Lba;
+ // Program data block by Block
+ for (BlockCount = 0; BlockCount < NumBlocks; BlockCount++) {
+ DEBUG ((DEBUG_BLKIO, "%a: Writing block #%d\n", __FUNCTION__, (UINTN)CurrentBlock));
+ // Erase the Block(Sector) to be written to
+ SectorAddress = GET_NOR_BLOCK_ADDRESS (
+ Instance->RegionBaseAddress,
+ CurrentBlock,
+ Instance->Media.BlockSize
+ );
+
+ Status = NorFlashPlatformEraseSector (Instance, (UINTN)SectorAddress);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Failed to erase Target 0x%x (0x%x) \n",
+ __FUNCTION__,SectorAddress, Status));
+ break;
+ }
+
+ // Program Block(Sector) to be written to
+ Status = NorFlashWrite (Instance, CurrentBlock, (UINTN)0, &BlockSizeInBytes, WriteBuffer);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+
+ CurrentBlock++;
+ WriteBuffer = WriteBuffer + BlockSizeInBytes;
+ }
+
+ return Status;
+}
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoFlushBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This
+ )
+{
+ DEBUG ((DEBUG_BLKIO, "%a NOT IMPLEMENTED (not required)\n", __FUNCTION__));
+
+ // Nothing to do so just return without error
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
new file mode 100644
index 0000000..ab94662
--- /dev/null
+++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
@@ -0,0 +1,503 @@
+/** @file
+
+ Based on NorFlash implementation available in
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c
+
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NorFlashLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+
+#include "NorFlashDxe.h"
+
+STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent;
+
+//
+// Global variable declarations
+//
+NOR_FLASH_INSTANCE **mNorFlashInstances;
+UINT32 mNorFlashDeviceCount;
+
+NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
+ .Signature = NOR_FLASH_SIGNATURE,
+ .StartLba = 0,
+ .BlockIoProtocol = {
+ .Revision = EFI_BLOCK_IO_PROTOCOL_REVISION2,
+ .Reset = NorFlashBlockIoReset,
+ .ReadBlocks = NorFlashBlockIoReadBlocks,
+ .WriteBlocks = NorFlashBlockIoWriteBlocks,
+ .FlushBlocks = NorFlashBlockIoFlushBlocks,
+ },
+
+ .Media = {
+ .RemovableMedia = FALSE,
+ .MediaPresent = TRUE,
+ .LogicalPartition = FALSE,
+ .ReadOnly = FALSE,
+ .WriteCaching = FALSE,
+ .IoAlign = 4,
+ .LowestAlignedLba = 0,
+ .LogicalBlocksPerPhysicalBlock = 1,
+ },
+
+ .FvbProtocol = {
+ .GetAttributes = FvbGetAttributes,
+ .SetAttributes = FvbSetAttributes,
+ .GetPhysicalAddress = FvbGetPhysicalAddress,
+ .GetBlockSize = FvbGetBlockSize,
+ .Read = FvbRead,
+ .Write = FvbWrite,
+ .EraseBlocks = FvbEraseBlocks,
+ .ParentHandle = NULL,
+ },
+ .ShadowBuffer = NULL,
+ .DevicePath = {
+ .Vendor = {
+ .Header = {
+ .Type = HARDWARE_DEVICE_PATH,
+ .SubType = HW_VENDOR_DP,
+ .Length = {(UINT8)sizeof (VENDOR_DEVICE_PATH),
+ (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) }
+ },
+ .Guid = EFI_CALLER_ID_GUID, // GUID ... NEED TO BE FILLED
+ },
+ .End = {
+ .Type = END_DEVICE_PATH_TYPE,
+ .SubType = END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ .Length = { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
+ }
+ }
+};
+
+/**
+
+ Test If the Destination buffer sets (0->1) or clears (1->0) any bit in Source buffer ?
+
+ @param[in] Source Source Buffer Pointer
+ @param[in] Destination Destination Buffer Pointer
+ @param[in] NumBytes Bytes to Compare
+ @param[in] Set True : Test Weather Destination buffer sets any bit in Source buffer ?
+ False : Test Weather Destination buffer clears any bit in Source buffer ?
+
+ @retval TRUE Destination buffer sets/clear a bit in source buffer.
+ @retval FALSE Destination buffer doesn't sets/clear bit in source buffer.
+
+**/
+STATIC
+BOOLEAN
+TestBitSetClear (
+ IN VOID *Source,
+ IN VOID *Destination,
+ IN UINTN NumBytes,
+ IN BOOLEAN Set
+ )
+{
+ UINTN Index = 0;
+ VOID* Buffer;
+
+ if (Set) {
+ Buffer = Destination;
+ } else {
+ Buffer = Source;
+ }
+
+ while (Index < NumBytes) {
+ if ((NumBytes - Index) >= 8) {
+ if ((*((UINT64*)(Source+Index)) ^ *((UINT64*)(Destination+Index))) & *((UINT64*)(Buffer+Index))) {
+ return TRUE;
+ }
+ Index += 8;
+ } else if ((NumBytes - Index) >= 4) {
+ if ((*((UINT32*)(Source+Index)) ^ *((UINT32*)(Destination+Index))) & *((UINT32*)(Buffer+Index))) {
+ return TRUE;
+ }
+ Index += 4;
+ } else if ((NumBytes - Index) >= 2) {
+ if ((*((UINT16*)(Source+Index)) ^ *((UINT16*)(Destination+Index))) & *((UINT16*)(Buffer+Index))) {
+ return TRUE;
+ }
+ Index += 2;
+ } else if ((NumBytes - Index) >= 1) {
+ if ((*((UINT8*)(Source+Index)) ^ *((UINT8*)(Destination+Index))) & *((UINT8*)(Buffer+Index))) {
+ return TRUE;
+ }
+ Index += 1;
+ }
+ }
+ return FALSE;
+}
+
+EFI_STATUS
+NorFlashCreateInstance (
+ IN UINTN NorFlashDeviceBase,
+ IN UINTN NorFlashRegionBase,
+ IN UINTN NorFlashSize,
+ IN UINT32 MediaId,
+ IN UINT32 BlockSize,
+ IN BOOLEAN SupportFvb,
+ OUT NOR_FLASH_INSTANCE** NorFlashInstance
+ )
+{
+ EFI_STATUS Status;
+ NOR_FLASH_INSTANCE* Instance;
+
+ ASSERT (NorFlashInstance != NULL);
+
+ Instance = AllocateRuntimeCopyPool (sizeof (NOR_FLASH_INSTANCE),
+ &mNorFlashInstanceTemplate);
+ if (Instance == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Instance->DeviceBaseAddress = NorFlashDeviceBase;
+ Instance->RegionBaseAddress = NorFlashRegionBase;
+ Instance->Size = NorFlashSize;
+
+ Instance->BlockIoProtocol.Media = &Instance->Media;
+ Instance->Media.MediaId = MediaId;
+ Instance->Media.BlockSize = BlockSize;
+ Instance->Media.LastBlock = (NorFlashSize / BlockSize) - 1;
+
+ Instance->ShadowBuffer = AllocateRuntimePool (BlockSize);
+ if (Instance->ShadowBuffer == NULL) {
+ FreePool (Instance);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ if (SupportFvb) {
+ NorFlashFvbInitialize (Instance);
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Instance->Handle,
+ &gEfiDevicePathProtocolGuid,
+ &Instance->DevicePath,
+ &gEfiBlockIoProtocolGuid,
+ &Instance->BlockIoProtocol,
+ &gEfiFirmwareVolumeBlockProtocolGuid,
+ &Instance->FvbProtocol,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ FreePool (Instance->ShadowBuffer);
+ FreePool (Instance);
+ return Status;
+ }
+ } else {
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Instance->Handle,
+ &gEfiDevicePathProtocolGuid,
+ &Instance->DevicePath,
+ &gEfiBlockIoProtocolGuid,
+ &Instance->BlockIoProtocol,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ FreePool (Instance->ShadowBuffer);
+ FreePool (Instance);
+ return Status;
+ }
+ }
+
+ *NorFlashInstance = Instance;
+
+ return Status;
+}
+
+/*
+ Write a full or portion of a block.
+ It must not span block boundaries; that is,
+ Offset + NumBytes <= Instance->Media.BlockSize.
+ */
+EFI_STATUS
+NorFlashWrite (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+)
+{
+ EFI_STATUS Status;
+ UINTN BlockSize;
+ BOOLEAN DoErase;
+ VOID *Source;
+ UINTN SectorAddress;
+
+ Status = EFI_SUCCESS;
+ Source = NULL;
+
+ DEBUG ((DEBUG_BLKIO,
+ "%a(Parameters: Lba=%ld, Offset=0x%x, NumBytes=0x%x, Buffer @ 0x%08x)\n",
+ __FUNCTION__, Lba, Offset, *NumBytes, Buffer));
+
+ // The buffer must be valid
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Detect WriteDisabled state
+ if (Instance->Media.ReadOnly == TRUE) {
+ DEBUG ((DEBUG_ERROR,
+ "NorFlashWrite: ERROR - Can not write: Device is in WriteDisabled state.\n"));
+ // It is in WriteDisabled state, return an error right away
+ return EFI_ACCESS_DENIED;
+ }
+
+ // Cache the block size to avoid de-referencing pointers all the time
+ BlockSize = Instance->Media.BlockSize;
+
+ // We must have some bytes to write
+ if ((*NumBytes == 0) || (*NumBytes > BlockSize)) {
+ DEBUG ((DEBUG_ERROR,
+ "NorFlashWrite: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n",
+ Offset, *NumBytes, BlockSize ));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ if (((Lba * BlockSize) + Offset + *NumBytes) > Instance->Size) {
+ DEBUG ((DEBUG_ERROR, "%a: ERROR - Write will exceed device size\n", __FUNCTION__));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Check we did get some memory. Buffer is BlockSize.
+ if (Instance->ShadowBuffer == NULL) {
+ DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - Buffer not ready\n"));
+ return EFI_DEVICE_ERROR;
+ }
+
+ SectorAddress = GET_NOR_BLOCK_ADDRESS (
+ Instance->RegionBaseAddress,
+ Lba,
+ Instance->Media.BlockSize
+ );
+
+ // Pick 128bytes as a good start for word operations as opposed to erasing the
+ // block and writing the data regardless if an erase is really needed.
+ // It looks like most individual NV variable writes are smaller than 128bytes.
+ if (*NumBytes <= 128) {
+ Source = Instance->ShadowBuffer;
+ //First Read the data into shadow buffer from location where data is to be written
+ Status = NorFlashPlatformRead (
+ Instance,
+ Lba,
+ Offset,
+ *NumBytes,
+ Source
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: ERROR - Failed to Read @ %p Status=%d\n",
+ __FUNCTION__, Offset + SectorAddress, Status));
+ return Status;
+ }
+ // Check to see if we need to erase before programming the data into NorFlash.
+ // If the destination bits are only changing from 1s to 0s we can
+ // just write. After a block is erased all bits in the block is set to 1.
+ // If any byte requires us to erase we just give up and rewrite all of it.
+ DoErase = TestBitSetClear (Source, Buffer, *NumBytes, TRUE);
+
+ // if we got here then write all the data. Otherwise do the
+ // Erase-Write cycle.
+ if (!DoErase) {
+ Status = NorFlashPlatformWriteBuffer (
+ Instance,
+ Lba,
+ Offset,
+ NumBytes,
+ Buffer
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: ERROR - Failed to Write @ %p Status=%d\n",
+ __FUNCTION__, Offset + SectorAddress, Status));
+ return Status;
+ }
+ return EFI_SUCCESS;
+ }
+ }
+
+ // If we are not going to write full block, read block and then update bytes in it
+ if (*NumBytes != BlockSize) {
+ // Read NorFlash Flash data into shadow buffer
+ Status = NorFlashBlockIoReadBlocks (
+ &(Instance->BlockIoProtocol),
+ Instance->Media.MediaId,
+ Lba,
+ BlockSize,
+ Instance->ShadowBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ // Return one of the pre-approved error statuses
+ return EFI_DEVICE_ERROR;
+ }
+ // Put the data at the appropriate location inside the buffer area
+ CopyMem ((VOID *)((UINTN)Instance->ShadowBuffer + Offset), Buffer, *NumBytes);
+ }
+ //Erase Block
+ Status = NorFlashPlatformEraseSector (Instance, SectorAddress);
+ if (EFI_ERROR (Status)) {
+ // Return one of the pre-approved error statuses
+ return EFI_DEVICE_ERROR;
+ }
+ if (*NumBytes != BlockSize) {
+ // Write the modified shadow buffer back to the NorFlash
+ Status = NorFlashPlatformWriteBuffer (
+ Instance,
+ Lba,
+ 0,
+ &BlockSize,
+ Instance->ShadowBuffer
+ );
+ } else {
+ // Write the Buffer to an entire block in NorFlash
+ Status = NorFlashPlatformWriteBuffer (
+ Instance,
+ Lba,
+ 0,
+ &BlockSize,
+ Buffer
+ );
+ }
+ if (EFI_ERROR (Status)) {
+ // Return one of the pre-approved error statuses
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+NorFlashVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINTN Index;
+
+ for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->DeviceBaseAddress);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->RegionBaseAddress);
+
+ // Convert BlockIo protocol
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.FlushBlocks);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.ReadBlocks);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.Reset);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoProtocol.WriteBlocks);
+
+ // Convert Fvb
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.EraseBlocks);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetAttributes);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetBlockSize);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetPhysicalAddress);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Read);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.SetAttributes);
+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Write);
+ if (mNorFlashInstances[Index]->ShadowBuffer != NULL) {
+ EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->ShadowBuffer);
+ }
+ }
+
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+NorFlashInitialise (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINT32 Index;
+ NorFlashDescription* NorFlashDevices;
+ BOOLEAN ContainVariableStorage;
+
+ ContainVariableStorage = 0;
+
+ Status = NorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashDeviceCount);
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "%a : Failed to get Nor devices (0x%x)\n",
+ __FUNCTION__, Status));
+ return Status;
+ }
+
+ Status = NorFlashPlatformFlashGetAttributes (NorFlashDevices, mNorFlashDeviceCount);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a : Failed to get NOR device attributes (0x%x)\n",
+ __FUNCTION__, Status));
+ ASSERT_EFI_ERROR (Status); // System becomes unusable if NOR flash is not detected
+ return Status;
+ }
+
+ mNorFlashInstances = AllocateRuntimePool (
+ sizeof (NOR_FLASH_INSTANCE*) * mNorFlashDeviceCount);
+ if (mNorFlashInstances == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a : Failed to allocate runtime memory \n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
+ // Check if this NOR Flash device contain the variable storage region
+ ContainVariableStorage =
+ (NorFlashDevices[Index].RegionBaseAddress <= PcdGet64 (PcdFlashNvStorageVariableBase64)) &&
+ ((PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvStorageVariableSize)) <=
+ (NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size));
+
+ Status = NorFlashCreateInstance (
+ NorFlashDevices[Index].DeviceBaseAddress,
+ NorFlashDevices[Index].RegionBaseAddress,
+ NorFlashDevices[Index].Size,
+ Index,
+ NorFlashDevices[Index].BlockSize,
+ ContainVariableStorage,
+ &mNorFlashInstances[Index]
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR,
+ "%a : Failed to create instance for NorFlash[%d] (0x%x)\n",
+ Index, Status));
+ }
+ }
+
+ //
+ // Register for the virtual address change event
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ NorFlashVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mNorFlashVirtualAddrChangeEvent
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to create VirtualAddressChange event 0x%x\n", Status));
+ }
+
+ return Status;
+}
diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
new file mode 100644
index 0000000..3b1826c
--- /dev/null
+++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
@@ -0,0 +1,146 @@
+/** @NorFlashDxe.h
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __NOR_FLASH_DXE_H__
+#define __NOR_FLASH_DXE_H__
+
+#include <Protocol/BlockIo.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+
+#define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize) ( BaseAddr + (UINTN)((Lba) * LbaSize) )
+
+#define NOR_FLASH_SIGNATURE SIGNATURE_32 ('n', 'o', 'r', '0')
+
+#define INSTANCE_FROM_FVB_THIS(a) CR (a, NOR_FLASH_INSTANCE, FvbProtocol, NOR_FLASH_SIGNATURE)
+
+#define INSTANCE_FROM_BLKIO_THIS(a) CR (a, NOR_FLASH_INSTANCE, BlockIoProtocol, NOR_FLASH_SIGNATURE)
+
+EFI_STATUS
+EFIAPI
+NorFlashFvbInitialize (
+ IN NOR_FLASH_INSTANCE* Instance
+ );
+
+EFI_STATUS
+EFIAPI
+FvbGetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+FvbSetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+FvbGetPhysicalAddress(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
+ );
+
+EFI_STATUS
+EFIAPI
+FvbGetBlockSize(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumberOfBlocks
+ );
+
+EFI_STATUS
+EFIAPI
+FvbRead(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN OUT UINT8 *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+FvbWrite(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+FvbEraseBlocks(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ ...
+ );
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReset (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN BOOLEAN ExtendedVerification
+ );
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoReadBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+);
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoWriteBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA Lba,
+ IN UINTN BufferSizeInBytes,
+ IN VOID *Buffer
+);
+
+//
+// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
+//
+EFI_STATUS
+EFIAPI
+NorFlashBlockIoFlushBlocks (
+ IN EFI_BLOCK_IO_PROTOCOL *This
+);
+
+EFI_STATUS
+NorFlashWrite (
+ IN NOR_FLASH_INSTANCE *Instance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+);
+
+#endif /* __NOR_FLASH_DXE_H__ */
diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
new file mode 100644
index 0000000..e83e813
--- /dev/null
+++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
@@ -0,0 +1,65 @@
+# @file
+#
+# Component description file for NorFlashDxe module
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = NorFlashDxe
+ FILE_GUID = 616fe8d8-f4aa-42e0-a393-b332bdb2d3c1
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = NorFlashInitialise
+
+[Sources.common]
+ NorFlashBlockIoDxe.c
+ NorFlashDxe.c
+ NorFlashFvbDxe.c
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ DxeServicesTableLib
+ HobLib
+ NorFlashLib
+ UefiDriverEntryPoint
+ UefiRuntimeLib
+
+[Guids]
+ gEfiSystemNvDataFvGuid
+ gEfiVariableGuid
+ gEfiAuthenticatedVariableGuid
+ gEfiEventVirtualAddressChangeGuid
+ gEdkiiNvVarStoreFormattedGuid ## PRODUCES ## PROTOCOL
+
+[Protocols]
+ gEfiBlockIoProtocolGuid
+ gEfiFirmwareVolumeBlockProtocolGuid
+
+[Pcd.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize
+
+[Depex]
+ gEfiCpuArchProtocolGuid
diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c
new file mode 100644
index 0000000..425fbce
--- /dev/null
+++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c
@@ -0,0 +1,816 @@
+/** @NorFlashFvbDxe.c
+
+ Based on NorFlash implementation available in
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashFvbDxe.c
+
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Guid/VariableFormat.h>
+#include <Guid/NvVarStoreFormatted.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/NorFlashLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeLib.h>
+
+#include <NorFlash.h>
+#include "NorFlashDxe.h"
+
+STATIC EFI_EVENT mFvbVirtualAddrChangeEvent;
+STATIC UINTN mFlashNvStorageVariableBase;
+
+///
+/// The Firmware Volume Block Protocol is the low-level interface
+/// to a firmware volume. File-level access to a firmware volume
+/// should not be done using the Firmware Volume Block Protocol.
+/// Normal access to a firmware volume must use the Firmware
+/// Volume Protocol. Typically, only the file system driver that
+/// produces the Firmware Volume Protocol will bind to the
+/// Firmware Volume Block Protocol.
+///
+
+/**
+ Initialises the FV Header and Variable Store Header
+ to support variable operations.
+
+ @param[in] Ptr - Location to initialise the headers
+
+**/
+EFI_STATUS
+InitializeFvAndVariableStoreHeaders (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ EFI_STATUS Status;
+ VOID* Headers;
+ UINTN HeadersLength;
+ EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader;
+ VARIABLE_STORE_HEADER *VariableStoreHeader;
+
+ HeadersLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY) + sizeof (VARIABLE_STORE_HEADER);
+ Headers = AllocateZeroPool (HeadersLength);
+ if (Headers == NULL) {
+ DEBUG ((DEBUG_ERROR, "Memory allocation failed for Headers \n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ // FirmwareVolumeHeader->FvLength is declared to have the Variable area AND the FTW working area AND the FTW Spare contiguous.
+ ASSERT ((PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvStorageVariableSize)) == PcdGet64 (PcdFlashNvStorageFtwWorkingBase64));
+ ASSERT ((PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) + PcdGet32 (PcdFlashNvStorageFtwWorkingSize)) == PcdGet64 (PcdFlashNvStorageFtwSpareBase64));
+
+ // Check if the size of the area is at least one block size
+ ASSERT ((PcdGet32 (PcdFlashNvStorageVariableSize) > 0) && (PcdGet32 (PcdFlashNvStorageVariableSize) / Instance->Media.BlockSize > 0));
+ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingSize) > 0) && (PcdGet32 (PcdFlashNvStorageFtwWorkingSize) / Instance->Media.BlockSize > 0));
+ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareSize) > 0) && (PcdGet32 (PcdFlashNvStorageFtwSpareSize) / Instance->Media.BlockSize > 0));
+
+ // Ensure the Variable area Base Addresses are aligned on a block size boundaries
+ ASSERT ((PcdGet64 (PcdFlashNvStorageVariableBase64) % Instance->Media.BlockSize) == 0);
+ ASSERT ((PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) % Instance->Media.BlockSize) == 0);
+ ASSERT ((PcdGet64 (PcdFlashNvStorageFtwSpareBase64) % Instance->Media.BlockSize) == 0);
+
+ //
+ // EFI_FIRMWARE_VOLUME_HEADER
+ //
+ FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers;
+ CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid);
+ FirmwareVolumeHeader->FvLength =
+ PcdGet32 (PcdFlashNvStorageVariableSize) +
+ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ PcdGet32 (PcdFlashNvStorageFtwSpareSize);
+ FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE;
+ FirmwareVolumeHeader->Attributes = (EFI_FVB_ATTRIBUTES_2) (
+ EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
+ EFI_FVB2_READ_STATUS | // Reads are currently enabled
+ EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
+ EFI_FVB2_ERASE_POLARITY | // After erasure all bits take this value (i.e. '1')
+ EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
+ EFI_FVB2_WRITE_ENABLED_CAP // Writes may be enabled
+ );
+ FirmwareVolumeHeader->HeaderLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY);
+ FirmwareVolumeHeader->Revision = EFI_FVH_REVISION;
+ //i.e. if blocks are 0-5 then last block = 5, total blocks = 6
+ FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->Media.LastBlock + 1;
+ FirmwareVolumeHeader->BlockMap[0].Length = Instance->Media.BlockSize;
+ FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0;
+ FirmwareVolumeHeader->BlockMap[1].Length = 0;
+ FirmwareVolumeHeader->Checksum = CalculateCheckSum16 ((UINT16*)FirmwareVolumeHeader,FirmwareVolumeHeader->HeaderLength);
+
+ //
+ // VARIABLE_STORE_HEADER
+ //
+ VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)Headers + FirmwareVolumeHeader->HeaderLength);
+ CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid);
+ VariableStoreHeader->Size = PcdGet32(PcdFlashNvStorageVariableSize) - FirmwareVolumeHeader->HeaderLength;
+ VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED;
+ VariableStoreHeader->State = VARIABLE_STORE_HEALTHY;
+
+ // Install the combined super-header in the NorFlash
+ Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers);
+
+ FreePool (Headers);
+ return Status;
+}
+
+/**
+ Check the integrity of firmware volume header.
+
+ @param[in] FwVolHeader - A pointer to a firmware volume header
+
+ @retval EFI_SUCCESS - The firmware volume is consistent
+ @retval EFI_NOT_FOUND - The firmware volume has been corrupted.
+
+**/
+EFI_STATUS
+ValidateFvHeader (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ UINT16 Checksum;
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
+ VARIABLE_STORE_HEADER *VariableStoreHeader;
+ UINTN VariableStoreLength;
+ UINTN FvLength;
+
+ FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER*)mFlashNvStorageVariableBase;
+
+ FvLength = PcdGet32 (PcdFlashNvStorageVariableSize) +
+ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ PcdGet32 (PcdFlashNvStorageFtwSpareSize);
+
+ //
+ // Verify the header revision, header signature, length
+ // Length of FvBlock cannot be 2**64-1
+ // HeaderLength cannot be an odd number
+ //
+ if ((FwVolHeader->Revision != EFI_FVH_REVISION) ||
+ (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||
+ (FwVolHeader->FvLength != FvLength)) {
+ DEBUG ((DEBUG_ERROR, "%a: No Firmware Volume header present\n", __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ // Check the Firmware Volume Guid
+ if (CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid) == FALSE ) {
+ DEBUG ((DEBUG_ERROR, "%a: Firmware Volume Guid non-compatible\n", __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ // Verify the header checksum
+ Checksum = CalculateSum16 ((UINT16*)FwVolHeader, FwVolHeader->HeaderLength);
+ if (Checksum != 0) {
+ DEBUG ((DEBUG_ERROR, "%a: FV checksum is invalid (Checksum:0x%X)\n", __FUNCTION__, Checksum));
+ return EFI_NOT_FOUND;
+ }
+
+ VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)FwVolHeader + FwVolHeader->HeaderLength);
+
+ // Check the Variable Store Guid
+ if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) &&
+ !CompareGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid)) {
+ DEBUG ((DEBUG_ERROR, "%a: Variable Store Guid non-compatible\n", __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) - FwVolHeader->HeaderLength;
+ if (VariableStoreHeader->Size != VariableStoreLength) {
+ DEBUG ((DEBUG_ERROR, "%a: Variable Store Length does not match\n", __FUNCTION__));
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ The GetAttributes() function retrieves the attributes and
+ current settings of the block.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and
+ current settings are returned.
+ Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+**/
+EFI_STATUS
+EFIAPI
+FvbGetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes;
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS (This);
+
+ FlashFvbAttributes = (EFI_FVB_ATTRIBUTES_2) (
+ EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
+ EFI_FVB2_READ_STATUS | // Reads are currently enabled
+ EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
+ EFI_FVB2_ERASE_POLARITY // After erasure all bits take this value (i.e. '1')
+ );
+
+ // Check if it is write protected
+ if (Instance->Media.ReadOnly != TRUE) {
+ FlashFvbAttributes = FlashFvbAttributes |
+ EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
+ EFI_FVB2_WRITE_ENABLED_CAP; // Writes may be enabled
+ }
+
+ *Attributes = FlashFvbAttributes;
+
+ DEBUG ((DEBUG_BLKIO, "FvbGetAttributes(0x%X)\n", *Attributes));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ The SetAttributes() function sets configurable firmware volume attributes
+ and returns the new settings of the firmware volume.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes On input, Attributes is a pointer to EFI_FVB_ATTRIBUTES_2
+ that contains the desired firmware volume settings.
+ On successful return, it contains the new settings of
+ the firmware volume.
+ Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+ @retval EFI_INVALID_PARAMETER The attributes requested are in conflict with the capabilities
+ as declared in the firmware volume header.
+
+**/
+EFI_STATUS
+EFIAPI
+FvbSetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ DEBUG ((DEBUG_BLKIO, "FvbSetAttributes(0x%X) is not supported\n",*Attributes));
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ The GetPhysicalAddress() function retrieves the base address of
+ a memory-mapped firmware volume. This function should be called
+ only for memory-mapped firmware volumes.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Address Pointer to a caller-allocated
+ EFI_PHYSICAL_ADDRESS that, on successful
+ return from GetPhysicalAddress(), contains the
+ base address of the firmware volume.
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped.
+
+**/
+EFI_STATUS
+EFIAPI
+FvbGetPhysicalAddress (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
+ )
+{
+ *Address = mFlashNvStorageVariableBase;
+ return EFI_SUCCESS;
+}
+
+/**
+ The GetBlockSize() function retrieves the size of the requested
+ block. It also returns the number of additional blocks with
+ the identical size. The GetBlockSize() function is used to
+ retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba Indicates the block for which to return the size.
+
+ @param BlockSize Pointer to a caller-allocated UINTN in which
+ the size of the block is returned.
+
+ @param NumberOfBlocks Pointer to a caller-allocated UINTN in
+ which the number of consecutive blocks,
+ starting with Lba, is returned. All
+ blocks in this range have a size of
+ BlockSize.
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range.
+
+**/
+EFI_STATUS
+EFIAPI
+FvbGetBlockSize (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumberOfBlocks
+ )
+{
+ EFI_STATUS Status;
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS (This);
+
+ DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize(Lba=%ld, BlockSize=0x%x, LastBlock=%ld)\n",
+ Lba, Instance->Media.BlockSize, Instance->Media.LastBlock));
+
+ if (Lba > Instance->Media.LastBlock) {
+ DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%ld)\n",
+ __FUNCTION__, Lba, Instance->Media.LastBlock));
+ Status = EFI_INVALID_PARAMETER;
+ } else {
+ // In this platform each NorFlash device has equal sized blocks.
+ *BlockSize = (UINTN) Instance->Media.BlockSize;
+ *NumberOfBlocks = (UINTN) (Instance->Media.LastBlock - Lba + 1);
+
+ DEBUG ((DEBUG_BLKIO, "%a : *BlockSize=0x%x, *NumberOfBlocks=0x%x.\n",
+ __FUNCTION__, *BlockSize, *NumberOfBlocks));
+
+ Status = EFI_SUCCESS;
+ }
+
+ return Status;
+}
+
+/**
+ Reads the specified number of bytes into a buffer from the specified block.
+
+ The Read() function reads the requested number of bytes from the
+ requested block and stores them in the provided buffer.
+ Implementations should be mindful that the firmware volume
+ might be in the ReadDisabled state. If it is in this state,
+ the Read() function must return the status code
+ EFI_ACCESS_DENIED without modifying the contents of the
+ buffer. The Read() function must also prevent spanning block
+ boundaries. If a read is requested that would span a block
+ boundary, the read must read up to the boundary but not
+ beyond. The output parameter NumBytes must be set to correctly
+ indicate the number of bytes actually read. The caller must be
+ aware that a read may be partially completed.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index from which to read.
+
+ @param Offset Offset into the block at which to begin reading.
+
+ @param NumBytes Pointer to a UINTN.
+ At entry, *NumBytes contains the total size of the buffer.
+ At exit, *NumBytes contains the total number of bytes read.
+
+ @param Buffer Pointer to a caller-allocated buffer that will be used
+ to hold the data that is read.
+
+ @retval EFI_SUCCESS The firmware volume was read successfully, and contents are
+ in Buffer.
+
+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary.
+ On output, NumBytes contains the total number of bytes
+ returned in Buffer.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be read.
+
+**/
+EFI_STATUS
+EFIAPI
+FvbRead (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN OUT UINT8 *Buffer
+ )
+{
+ UINTN BlockSize;
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS (This);
+
+ DEBUG ((DEBUG_BLKIO, "FvbRead(Parameters: Lba=%ld, Offset=0x%x, "
+ "*NumBytes=0x%x, Buffer @ 0x%08x)\n",
+ Instance->StartLba + Lba, Offset, *NumBytes, Buffer));
+
+ // Cache the block size to avoid de-referencing pointers all the time
+ BlockSize = Instance->Media.BlockSize;
+
+ DEBUG ((DEBUG_BLKIO, "FvbRead: Check if (Offset=0x%x + NumBytes=0x%x) <= "
+ "BlockSize=0x%x\n", Offset, *NumBytes, BlockSize ));
+
+ // The read must not span block boundaries.
+ while (Offset >= BlockSize) {
+ Offset -= BlockSize;
+ Lba++;
+ }
+
+ if ((Instance->StartLba + Lba) > Instance->Media.LastBlock) {
+ DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%ld)\n",
+ __FUNCTION__, Lba, Instance->Media.LastBlock));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((Offset + *NumBytes) > BlockSize) {
+ *NumBytes = BlockSize-Offset;
+ }
+
+ return NorFlashPlatformRead (
+ Instance,
+ Instance->StartLba + Lba,
+ Offset,
+ *NumBytes,
+ Buffer
+ );
+}
+
+/**
+ Writes the specified number of bytes from the input buffer to the block.
+
+ The Write() function writes the specified number of bytes from
+ the provided buffer to the specified block and offset. If the
+ firmware volume is sticky write, the caller must ensure that
+ all the bits of the specified range to write are in the
+ EFI_FVB_ERASE_POLARITY state before calling the Write()
+ function, or else the result will be unpredictable. This
+ unpredictability arises because, for a sticky-write firmware
+ volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
+ state but cannot flip it back again. Before calling the
+ Write() function, it is recommended for the caller to first call
+ the EraseBlocks() function to erase the specified block to
+ write. A block erase cycle will transition bits from the
+ (NOT)EFI_FVB_ERASE_POLARITY state back to the
+ EFI_FVB_ERASE_POLARITY state. Implementations should be
+ mindful that the firmware volume might be in the WriteDisabled
+ state. If it is in this state, the Write() function must
+ return the status code EFI_ACCESS_DENIED without modifying the
+ contents of the firmware volume. The Write() function must
+ also prevent spanning block boundaries. If a write is
+ requested that spans a block boundary, the write must store up
+ to the boundary but not beyond. The output parameter NumBytes
+ must be set to correctly indicate the number of bytes actually
+ written. The caller must be aware that a write may be
+ partially completed. All writes, partial or otherwise, must be
+ fully flushed to the hardware before the Write() service
+ returns.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index to write to.
+
+ @param Offset Offset into the block at which to begin writing.
+
+ @param NumBytes The pointer to a UINTN.
+ At entry, *NumBytes contains the total size of the buffer.
+ At exit, *NumBytes contains the total number of bytes actually written.
+
+ @param Buffer The pointer to a caller-allocated buffer that contains the source for the write.
+
+ @retval EFI_SUCCESS The firmware volume was written successfully.
+
+ @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA boundary.
+ On output, NumBytes contains the total number of bytes
+ actually written.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is malfunctioning and could not be written.
+
+**/
+EFI_STATUS
+EFIAPI
+FvbWrite (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ NOR_FLASH_INSTANCE *Instance;
+ UINTN BlockSize;
+
+ Instance = INSTANCE_FROM_FVB_THIS (This);
+ // Cache the block size to avoid de-referencing pointers all the time
+ BlockSize = Instance->Media.BlockSize;
+
+ // The write must not span block boundaries.
+ while(Offset >= BlockSize) {
+ Offset -= BlockSize;
+ Lba++;
+ }
+
+ if ((Instance->StartLba + Lba) > Instance->Media.LastBlock) {
+ DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%ld)\n",
+ __FUNCTION__, Lba, Instance->Media.LastBlock));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((Offset + *NumBytes) > BlockSize) {
+ *NumBytes = BlockSize-Offset;
+ }
+
+ return NorFlashWrite (
+ Instance,
+ Instance->StartLba + Lba,
+ Offset,
+ NumBytes,
+ Buffer
+ );
+}
+
+/**
+ Erases and initialises a firmware volume block.
+
+ The EraseBlocks() function erases one or more blocks as denoted
+ by the variable argument list. The entire parameter list of
+ blocks must be verified before erasing any blocks. If a block is
+ requested that does not exist within the associated firmware
+ volume (it has a larger index than the last block of the
+ firmware volume), the EraseBlocks() function must return the
+ status code EFI_INVALID_PARAMETER without modifying the contents
+ of the firmware volume. Implementations should be mindful that
+ the firmware volume might be in the WriteDisabled state. If it
+ is in this state, the EraseBlocks() function must return the
+ status code EFI_ACCESS_DENIED without modifying the contents of
+ the firmware volume. All calls to EraseBlocks() must be fully
+ flushed to the hardware before the EraseBlocks() service
+ returns.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
+ instance.
+
+ @param ... The variable argument list is a list of tuples.
+ Each tuple describes a range of LBAs to erase
+ and consists of the following:
+ - An EFI_LBA that indicates the starting LBA
+ - A UINTN that indicates the number of blocks to erase.
+
+ The list is terminated with an EFI_LBA_LIST_TERMINATOR.
+ For example, the following indicates that two ranges of blocks
+ (5-7 and 10-11) are to be erased:
+ EraseBlocks (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR);
+
+ @retval EFI_SUCCESS The erase request successfully completed.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and could not be written.
+ The firmware device may have been partially erased.
+
+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable argument list do
+ not exist in the firmware volume.
+
+**/
+EFI_STATUS
+EFIAPI
+FvbEraseBlocks (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ ...
+ )
+{
+ EFI_STATUS Status;
+ VA_LIST Args;
+ UINTN BlockAddress; // Physical address of Lba to erase
+ EFI_LBA StartingLba; // Lba from which we start erasing
+ UINTN NumOfLba; // Number of Lba blocks to erase
+ NOR_FLASH_INSTANCE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS (This);
+
+ DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks()\n"));
+
+ Status = EFI_SUCCESS;
+
+ // Detect WriteDisabled state
+ if (Instance->Media.ReadOnly == TRUE) {
+ // Firmware volume is in WriteDisabled state
+ DEBUG ((DEBUG_ERROR, "%a : Device is in WriteDisabled state\n"));
+ return EFI_ACCESS_DENIED;
+ }
+
+ // Before erasing, check the entire list of parameters to
+ // ensure all specified blocks are valid
+
+ VA_START (Args, This);
+ do {
+ // Get the Lba from which we start erasing
+ StartingLba = VA_ARG (Args, EFI_LBA);
+
+ // Have we reached the end of the list?
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
+ //Exit the while loop
+ break;
+ }
+
+ // How many Lba blocks are we requested to erase?
+ NumOfLba = VA_ARG (Args, UINT32);
+
+ // All blocks must be within range
+ DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Check if: ( StartingLba=%ld + NumOfLba=%d - 1 ) > LastBlock=%ld.\n",
+ Instance->StartLba + StartingLba, NumOfLba, Instance->Media.LastBlock));
+ if ((NumOfLba == 0) ||
+ ((Instance->StartLba + StartingLba + NumOfLba - 1) > Instance->Media.LastBlock)) {
+ VA_END (Args);
+ DEBUG ((DEBUG_ERROR, "%a : Lba range goes past the last Lba\n"));
+ Status = EFI_INVALID_PARAMETER;
+ goto EXIT;
+ }
+ } while (TRUE);
+ VA_END (Args);
+
+ //
+ // To get here, all must be ok, so start erasing
+ //
+ VA_START (Args, This);
+ do {
+ // Get the Lba from which we start erasing
+ StartingLba = VA_ARG (Args, EFI_LBA);
+
+ // Have we reached the end of the list?
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
+ // Exit the while loop
+ break;
+ }
+
+ // How many Lba blocks are we requested to erase?
+ NumOfLba = VA_ARG (Args, UINT32);
+
+ // Go through each one and erase it
+ while (NumOfLba > 0) {
+ // Get the physical address of Lba to erase
+ BlockAddress = GET_NOR_BLOCK_ADDRESS (
+ Instance->RegionBaseAddress,
+ Instance->StartLba + StartingLba,
+ Instance->Media.BlockSize
+ );
+
+ // Erase it
+ DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Erasing Lba=%ld @ 0x%08x.\n",
+ Instance->StartLba + StartingLba, BlockAddress));
+ Status = NorFlashPlatformEraseSector (Instance, BlockAddress);
+ if (EFI_ERROR (Status)) {
+ VA_END (Args);
+ Status = EFI_DEVICE_ERROR;
+ goto EXIT;
+ }
+
+ // Move to the next Lba
+ StartingLba++;
+ NumOfLba--;
+ }
+ } while (TRUE);
+ VA_END (Args);
+
+EXIT:
+ return Status;
+}
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+FvbVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase);
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+NorFlashFvbInitialize (
+ IN NOR_FLASH_INSTANCE *Instance
+ )
+{
+ EFI_STATUS Status;
+ UINT32 FvbNumLba;
+ EFI_BOOT_MODE BootMode;
+ UINTN RuntimeMmioRegionSize;
+
+ DEBUG ((DEBUG_BLKIO, "NorFlashFvbInitialize\n"));
+
+ mFlashNvStorageVariableBase = FixedPcdGet64 (PcdFlashNvStorageVariableBase64);
+
+ // Set the index of the first LBA for the FVB
+ Instance->StartLba = (PcdGet64 (PcdFlashNvStorageVariableBase64) - Instance->RegionBaseAddress) /
+ Instance->Media.BlockSize;
+
+ BootMode = GetBootModeHob ();
+ if (BootMode == BOOT_WITH_DEFAULT_SETTINGS) {
+ Status = EFI_INVALID_PARAMETER;
+ } else {
+ // Determine if there is a valid header at the beginning of the NorFlash
+ Status = ValidateFvHeader (Instance);
+ }
+
+ // Install the Default FVB header if required
+ if (EFI_ERROR (Status)) {
+ // There is no valid header, so time to install one.
+ DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __FUNCTION__));
+ DEBUG ((DEBUG_INFO, "%a: Installing a correct one for this volume.\n", __FUNCTION__));
+
+ // Erase all the NorFlash that is reserved for variable storage
+ FvbNumLba = (PcdGet32 (PcdFlashNvStorageVariableSize) +
+ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ PcdGet32 (PcdFlashNvStorageFtwSpareSize)) /
+ Instance->Media.BlockSize;
+
+ Status = FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumLba, EFI_LBA_LIST_TERMINATOR);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Install all appropriate headers
+ Status = InitializeFvAndVariableStoreHeaders (Instance);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ //
+ // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME
+ //
+
+ // Note: all the NOR Flash region needs to be reserved into the UEFI Runtime memory;
+ // even if we only use the small block region at the top of the NOR Flash.
+ // The reason is when the NOR Flash memory is set into program mode, the command
+ // is written as the base of the flash region (ie: Instance->DeviceBaseAddress)
+ RuntimeMmioRegionSize = (Instance->RegionBaseAddress - Instance->DeviceBaseAddress) + Instance->Size;
+
+ Status = gDS->AddMemorySpace (
+ EfiGcdMemoryTypeMemoryMappedIo,
+ Instance->DeviceBaseAddress,
+ RuntimeMmioRegionSize,
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gDS->SetMemorySpaceAttributes (
+ Instance->DeviceBaseAddress,
+ RuntimeMmioRegionSize,
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // The driver implementing the variable read service can now be dispatched;
+ // the varstore headers are in place.
+ //
+ Status = gBS->InstallProtocolInterface (
+ &gImageHandle,
+ &gEdkiiNvVarStoreFormattedGuid,
+ EFI_NATIVE_INTERFACE,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register for the virtual address change event
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ FvbVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mFvbVirtualAddrChangeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 18/41] LS1043 : Enable NOR driver for LS1043aRDB package.
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (16 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 17/41] Silicon/NXP : Add NOR driver Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-19 18:33 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 19/41] Silicon/NXP:Add LS1046ARDB SoCLib Support Meenakshi Aggarwal
` (24 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 15 ++++++++++++++-
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 9 ++++++++-
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 48a7b5a..9a68cfd 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -41,6 +41,7 @@
IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf
+ NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
[PcdsFixedAtBuild.common]
@@ -65,6 +66,13 @@
gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
+ #
+ # NV Storage PCDs
+ #
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
@@ -74,10 +82,15 @@
#
# Architectural Protocols
#
- MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ }
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+ Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
##
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 417303d..6b27aed 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -55,6 +55,7 @@ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
!include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
################################################################################
#
# FV Section
@@ -104,7 +105,8 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -124,6 +126,11 @@ READ_LOCK_STATUS = TRUE
INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
#
+ # NOR Driver
+ #
+ INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+ #
# Network modules
#
INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 19/41] Silicon/NXP:Add LS1046ARDB SoCLib Support
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (17 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 18/41] LS1043 : Enable NOR driver for LS1043aRDB package Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-19 18:41 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 20/41] Silicon/NXP:Add support for PCF2129 Real Time Clock Library Meenakshi Aggarwal
` (23 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Provide Functions to initialize peripherals,
print board and soc information.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 +
Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 ++++++++++++++++++++++
Silicon/NXP/LS1046A/LS1046A.dec | 22 +++++++++
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 68 ++++++++++++++++++++++++++++
Silicon/NXP/Library/SocLib/Chassis.c | 1 +
Silicon/NXP/Library/SocLib/Chassis.h | 1 +
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 48 ++++++++++++++++++++
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 2 +
Silicon/NXP/Library/SocLib/LS1046aSocLib.inf | 53 ++++++++++++++++++++++
Silicon/NXP/NxpQoriqLs.dec | 1 +
10 files changed, 252 insertions(+)
create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc.inc
create mode 100644 Silicon/NXP/Library/SocLib/LS1046aSocLib.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index 9a68cfd..b69ffa2 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -59,6 +59,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
+ gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|TRUE
#
# RTC Pcds
diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h b/Silicon/NXP/LS1046A/Include/SocSerDes.h
new file mode 100644
index 0000000..957db0f
--- /dev/null
+++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h
@@ -0,0 +1,55 @@
+/** @file
+ The Header file of SerDes Module
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __LS1046A_SERDES_H__
+#define __LS1046A_SERDES_H__
+
+#include <Chassis2/SerDes.h>
+
+SERDES_CONFIG SerDes1ConfigTbl[] = {
+ /* SerDes 1 */
+ {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE } },
+ {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE } },
+ {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6 } },
+ {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6 } },
+ {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, SGMII_FM1_DTSEC6 } },
+ {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
+ {}
+};
+
+SERDES_CONFIG SerDes2ConfigTbl[] = {
+ /* SerDes 2 */
+ {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+ {0x5559, {PCIE1, PCIE2, PCIE3, SATA } },
+ {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3 } },
+ {0x5506, {PCIE1, PCIE2, NONE, PCIE3 } },
+ {0x0506, {NONE, PCIE2, NONE, PCIE3 } },
+ {0x0559, {NONE, PCIE2, PCIE3, SATA } },
+ {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA } },
+ {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3 } },
+ {}
+};
+
+SERDES_CONFIG *SerDesConfigTbl[] = {
+ SerDes1ConfigTbl,
+ SerDes2ConfigTbl
+};
+
+#endif /* __LS1046A_SERDES_H */
diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec
new file mode 100644
index 0000000..93fc80d
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dec
@@ -0,0 +1,22 @@
+# LS1046A.dec
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001000A
+
+[Guids.common]
+ gNxpLs1046ATokenSpaceGuid = {0x8d7ffac8, 0xb4d5, 0x43c3, {0xaa, 0x27, 0x84, 0xbc, 0x12, 0x01, 0x28, 0x10}}
+
+[Includes]
+ Include
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
new file mode 100644
index 0000000..9f87028
--- /dev/null
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -0,0 +1,68 @@
+# LS1046A.dsc
+# LS1046A Soc package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsDynamicDefault.common]
+
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x01410000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01420000
+
+[PcdsFixedAtBuild.common]
+
+ #
+ # CCSR Address Space and other attached Memories
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
+ gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000
+ gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
+
+##
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index 851174c..e8e69a6 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -45,6 +45,7 @@ GurRead (
*/
STATIC CPU_TYPE CpuTypeList[] = {
CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
+ CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
};
/*
diff --git a/Silicon/NXP/Library/SocLib/Chassis.h b/Silicon/NXP/Library/SocLib/Chassis.h
index 5aa1209..5b7e5c4 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.h
+++ b/Silicon/NXP/Library/SocLib/Chassis.h
@@ -56,6 +56,7 @@ CpuMaskNext (
#define SVR_WO_E 0xFFFFFE
#define SVR_LS1043A 0x879200
+#define SVR_LS1046A 0x870700
#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
index e79728e..62d761e 100644
--- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -20,6 +20,7 @@
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/IfcLib.h>
+#include <Library/IoAccessLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
@@ -138,6 +139,43 @@ GetSysInfo (
}
/**
+ Function to select pins depending upon pcd using supplemental
+ configuration unit(SCFG) extended RCW controlled pinmux control
+ register which contains the bits to provide pin multiplexing control.
+ This register is reset on HRESET.
+ **/
+VOID
+ConfigScfgMux (VOID)
+{
+ CCSR_SCFG *Scfg;
+ UINT32 UsbPwrFault;
+
+ Scfg = (VOID *)PcdGet64 (PcdScfgBaseAddr);
+ // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
+ // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
+
+ // LS1043A
+ // Configures functionality of the IIC4_SCL to USB3_DRVVBUS
+ // Configures functionality of the IIC4_SDA to USB3_PWRFAULT
+
+ // LS1046A
+ // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
+ if (PcdGetBool (PcdMuxToUsb3)) {
+ SwapMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_SELCR_USB);
+ } else {
+ SwapMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB);
+ }
+
+ SwapMmioWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, CCSR_SCFG_USBDRVVBUS_SELCR_USB1);
+ UsbPwrFault =
+ (CCSR_SCFG_USBPWRFAULT_DEDICATED << CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) |
+ (CCSR_SCFG_USBPWRFAULT_DEDICATED << CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) |
+ (CCSR_SCFG_USBPWRFAULT_SHARED << CCSR_SCFG_USBPWRFAULT_USB1_SHIFT);
+
+ SwapMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
+}
+
+/**
Function to initialize SoC specific constructs
CPU Info
SoC Personality
@@ -167,6 +205,16 @@ SocInit (
PrintSoc ();
IfcInit ();
PrintBoardPersonality ();
+ //
+ // Due to the extensive functionality present on the chip and the limited number of external
+ // signals available, several functional blocks share signal resources through multiplexing.
+ // In this case when there is alternate functionality between multiple functional blocks,
+ // the signal's function is determined at the chip level (rather than at the block level)
+ // typically by a reset configuration word (RCW) option. Some of the signals' function are
+ // determined externel to RCW at Power-on Reset Sequence.
+ //
+ ConfigScfgMux ();
+
return;
}
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
index af0790f..d93d66a 100644
--- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -47,5 +47,7 @@
gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
diff --git a/Silicon/NXP/Library/SocLib/LS1046aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1046aSocLib.inf
new file mode 100644
index 0000000..7eb0180
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/LS1046aSocLib.inf
@@ -0,0 +1,53 @@
+# @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SocLib
+ FILE_GUID = ddd5f950-8816-4d38-8f98-f42b07333f78
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/LS1046A/LS1046A.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ FpgaLib
+ IfcLib
+ IoAccessLib
+ SerialPortLib
+
+[Sources.common]
+ Chassis.c
+ Chassis2/Soc.c
+ SerDes.c
+
+[BuildOptions]
+ GCC:*_*_*_CC_FLAGS = -DCHASSIS2
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index bd89da4..159ea65 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -101,6 +101,7 @@
#
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
+ gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE|BOOLEAN|0x00000252
#
# Clock PCDs
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 20/41] Silicon/NXP:Add support for PCF2129 Real Time Clock Library
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (18 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 19/41] Silicon/NXP:Add LS1046ARDB SoCLib Support Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-19 18:52 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 21/41] Platform/NXP: LS1046A RDB Board Library Meenakshi Aggarwal
` (22 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
Library to provide functions for NXP pcf2129 real time clock library
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/NxpQoriqLs.dsc.inc | 1 +
Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h | 52 +++
Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c | 389 +++++++++++++++++++++
.../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec | 29 ++
.../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf | 47 +++
5 files changed, 518 insertions(+)
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec
create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
index 972dadc..5529a04 100644
--- a/Platform/NXP/NxpQoriqLs.dsc.inc
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -34,6 +34,7 @@
ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
new file mode 100644
index 0000000..c862954
--- /dev/null
+++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
@@ -0,0 +1,52 @@
+/** Pcf2129Rtc.h
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __PCF2129RTC_H__
+#define __PCF2129RTC_H__
+
+/*
+ * RTC register addresses
+ */
+#define PCF2129_CTRL1_REG_ADDR 0x00 // Control Register 1
+#define PCF2129_CTRL2_REG_ADDR 0x01 // Control Register 2
+#define PCF2129_CTRL3_REG_ADDR 0x02 // Control Register 3
+#define PCF2129_SEC_REG_ADDR 0x03
+#define PCF2129_MIN_REG_ADDR 0x04
+#define PCF2129_HR_REG_ADDR 0x05
+#define PCF2129_DAY_REG_ADDR 0x06
+#define PCF2129_WEEKDAY_REG_ADDR 0x07
+#define PCF2129_MON_REG_ADDR 0x08
+#define PCF2129_YR_REG_ADDR 0x09
+
+#define PCF2129_CTRL3_BIT_BLF BIT2 /* Battery Low Flag*/
+
+/*
+ * Masks for RTC registers
+ */
+#define PCF2129_SECONDS_MASK 0x7F
+#define PCF2129_MINUTES_MASK 0x7F
+#define PCF2129_HOURS_MASK 0x3F
+#define PCF2129_DAYS_MASK 0x3F
+#define PCF2129_MONTHS_MASK 0x1F
+
+#define EPOCH_BASE_1990 1990
+#define EPOCH_BASE_2000 2000
+
+typedef struct {
+ UINTN OperationCount;
+ EFI_I2C_OPERATION SetAddressOp;
+ EFI_I2C_OPERATION GetSetDateTimeOp;
+} RTC_I2C_REQUEST;
+
+#endif // __PCF2129RTC_H__
diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
new file mode 100644
index 0000000..90bad66
--- /dev/null
+++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
@@ -0,0 +1,389 @@
+/** @PCF2129RtcLib.c
+ Implement EFI RealTimeClock with runtime services via RTC Lib for PCF2129 RTC.
+
+ Based on RTC implementation available in
+ EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/TimeBaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/I2cMaster.h>
+
+#include "Pcf2129Rtc.h"
+
+STATIC VOID *mDriverEventRegistration;
+STATIC EFI_HANDLE mI2cMasterHandle;
+STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
+
+/**
+ Write RTC register.
+
+ @param RtcRegAddr Register offset of RTC to write.
+ @param Val Value to be written
+
+**/
+
+STATIC
+VOID
+RtcWrite (
+ IN UINT8 RtcRegAddr,
+ IN UINT8 Val
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = 0;
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = 0;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (
+ mI2cMaster,
+ FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL,
+ NULL
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
+ }
+
+}
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+
+**/
+
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Buffer[10];
+ RTC_I2C_REQUEST Req;
+ UINT8 RtcRegAddr;
+ UINT16 EpochBase;
+
+ Status = EFI_SUCCESS;
+ RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
+ Buffer[0] = 0;
+
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ RtcWrite (PCF2129_CTRL1_REG_ADDR, Buffer[0]);
+
+ if (Time == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = 0;
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Buffer);
+ Req.GetSetDateTimeOp.Buffer = Buffer;
+
+ Status = mI2cMaster->StartRequest (
+ mI2cMaster,
+ FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
+ }
+
+ if (Buffer[PCF2129_CTRL3_REG_ADDR] & PCF2129_CTRL3_BIT_BLF) {
+ DEBUG((DEBUG_INFO, "### Warning: RTC battery status low, check/replace RTC battery.\n"));
+ }
+
+ EpochBase = BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]) >= 98 ? EPOCH_BASE_1990 : EPOCH_BASE_2000;
+
+ Time->Nanosecond = 0;
+ Time->Second = BcdToDecimal8 (Buffer[PCF2129_SEC_REG_ADDR] & PCF2129_SECONDS_MASK);
+ Time->Minute = BcdToDecimal8 (Buffer[PCF2129_MIN_REG_ADDR] & PCF2129_MINUTES_MASK);
+ Time->Hour = BcdToDecimal8 (Buffer[PCF2129_HR_REG_ADDR] & PCF2129_HOURS_MASK);
+ Time->Day = BcdToDecimal8 (Buffer[PCF2129_DAY_REG_ADDR] & PCF2129_DAYS_MASK);
+ Time->Month = BcdToDecimal8 (Buffer[PCF2129_MON_REG_ADDR] & PCF2129_MONTHS_MASK);
+ Time->Year = BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]) + EpochBase;
+
+ return Status;
+}
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
+
+**/
+
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ UINT8 Buffer[8];
+ UINT8 Index;
+ EFI_STATUS Status;
+ RTC_I2C_REQUEST Req;
+ UINT8 RtcRegAddr;
+
+ Index = 0;
+ Status = EFI_SUCCESS;
+ RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
+
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ // start register address
+ Buffer[Index++] = PCF2129_SEC_REG_ADDR;
+
+ // hours, minutes and seconds
+ Buffer[Index++] = DecimalToBcd8 (Time->Second);
+ Buffer[Index++] = DecimalToBcd8 (Time->Minute);
+ Buffer[Index++] = DecimalToBcd8 (Time->Hour);
+ Buffer[Index++] = DecimalToBcd8 (Time->Day);
+ Buffer[Index++] = EfiTimeToWday (Time);
+ Buffer[Index++] = DecimalToBcd8 (Time->Month);
+ Buffer[Index++] = DecimalToBcd8 (Time->Year % 100);
+
+ Req.OperationCount = 2;
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = 0;
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = 0;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Buffer);
+ Req.GetSetDateTimeOp.Buffer = Buffer;
+
+ Status = mI2cMaster->StartRequest (
+ mI2cMaster,
+ FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL,
+ NULL
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
+ return Status;
+ }
+
+ return Status;
+}
+
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+STATIC
+VOID
+I2cDriverRegistrationEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_I2C_MASTER_PROTOCOL *I2cMaster;
+ UINTN BusFrequency;
+ EFI_HANDLE Handle;
+ UINTN BufferSize;
+
+ //
+ // Try to connect the newly registered driver to our handle.
+ //
+ do {
+ BufferSize = sizeof (EFI_HANDLE);
+ Status = gBS->LocateHandle (ByRegisterNotify,
+ &gEfiI2cMasterProtocolGuid,
+ mDriverEventRegistration,
+ &BufferSize,
+ &Handle);
+ if (EFI_ERROR (Status)) {
+ if (Status != EFI_NOT_FOUND) {
+ DEBUG ((DEBUG_WARN, "%a: gBS->LocateHandle () returned %r\n",
+ __FUNCTION__, Status));
+ }
+ break;
+ }
+
+ if (Handle != mI2cMasterHandle) {
+ continue;
+ }
+
+ DEBUG ((DEBUG_INFO, "%a: found I2C master!\n", __FUNCTION__));
+
+ gBS->CloseEvent (Event);
+
+ Status = gBS->OpenProtocol (mI2cMasterHandle, &gEfiI2cMasterProtocolGuid,
+ (VOID **)&I2cMaster, gImageHandle, NULL,
+ EFI_OPEN_PROTOCOL_EXCLUSIVE);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = I2cMaster->Reset (I2cMaster);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
+ __FUNCTION__, Status));
+ break;
+ }
+
+ BusFrequency = FixedPcdGet16 (PcdI2cBusFrequency);
+ Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
+ __FUNCTION__, Status));
+ break;
+ }
+
+ mI2cMaster = I2cMaster;
+ break;
+ } while (TRUE);
+}
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_DEVICE_ERROR The operation could not be started.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+
+ EFI_STATUS Status;
+ UINTN BufferSize;
+
+ //
+ // Find the handle that marks the controller
+ // that will provide the I2C master protocol.
+ //
+ BufferSize = sizeof (EFI_HANDLE);
+ Status = gBS->LocateHandle (
+ ByProtocol,
+ &gPcf2129RealTimeClockLibI2cMasterProtocolGuid,
+ NULL,
+ &BufferSize,
+ &mI2cMasterHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register a protocol registration notification callback on the driver
+ // binding protocol so we can attempt to connect our I2C master to it
+ // as soon as it appears.
+ //
+ EfiCreateProtocolNotifyEvent (
+ &gEfiI2cMasterProtocolGuid,
+ TPL_CALLBACK,
+ I2cDriverRegistrationEvent,
+ NULL,
+ &mDriverEventRegistration);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec
new file mode 100644
index 0000000..ea3fad6
--- /dev/null
+++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec
@@ -0,0 +1,29 @@
+#/** @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+ PACKAGE_NAME = Pcf2129RtcLib
+ PACKAGE_GUID = d6c2b7cf-4d3b-4173-8d99-fdcf9ba8403d
+ PACKAGE_VERSION = 0.1
+
+[Guids]
+ gPcf2129RtcLibTokenSpaceGuid = { 0xb67741d5, 0x0b12, 0x42e1, {0x85, 0xcd, 0x37, 0x1c, 0x5d, 0x59, 0xb7, 0xb0 }}
+
+[Protocols]
+ gPcf2129RealTimeClockLibI2cMasterProtocolGuid = { 0x8a1aac5e, 0xdffa, 0x4722, {0xba, 0x75, 0x55, 0x80, 0xda, 0x6a, 0x1b, 0x00 }}
+
+[PcdsFixedAtBuild]
+ gPcf2129RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001
+ gPcf2129RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002
diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
new file mode 100644
index 0000000..fd19b63
--- /dev/null
+++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
@@ -0,0 +1,47 @@
+#/** @Pcf2129RtcLib.inf
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Pcf2129RtcLib
+ FILE_GUID = B661E02D-A90B-42AB-A5F9-CF841AAA43D9
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+
+[Sources.common]
+ Pcf2129RtcLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec
+
+[LibraryClasses]
+ DebugLib
+ TimeBaseLib
+ UefiBootServicesTableLib
+ UefiLib
+
+[Protocols]
+ gEfiI2cMasterProtocolGuid ## CONSUMES
+ gPcf2129RealTimeClockLibI2cMasterProtocolGuid ## CONSUMES
+
+[Pcd]
+ gPcf2129RtcLibTokenSpaceGuid.PcdI2cSlaveAddress
+ gPcf2129RtcLibTokenSpaceGuid.PcdI2cBusFrequency
+
+[Depex]
+ gPcf2129RealTimeClockLibI2cMasterProtocolGuid ## CONSUMES
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 21/41] Platform/NXP: LS1046A RDB Board Library
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (19 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 20/41] Silicon/NXP:Add support for PCF2129 Real Time Clock Library Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-19 18:54 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 22/41] Platform/NXP: Add ArmPlatformLib for LS1046A Meenakshi Aggarwal
` (21 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Library to provide board specific timings for LS1046ARDB
board with interfacing to IFC controller for accessing
FPGA and NAND.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
.../NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h | 83 ++++++++++++++++++++++
.../NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c | 61 ++++++++++++++++
.../LS1046aRdbPkg/Library/BoardLib/BoardLib.inf | 31 ++++++++
3 files changed, 175 insertions(+)
create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
diff --git a/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h b/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
new file mode 100644
index 0000000..e15100d
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
@@ -0,0 +1,83 @@
+/** IfcBoardSpecificLib.h
+
+ IFC Flash Board Specific Macros and structure
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __IFC__BOARD_SPECIFIC_H__
+#define __IFC__BOARD_SPECIFIC_H__
+
+#include <Ifc.h>
+
+// On board flash support
+#define IFC_NAND_BUF_BASE 0x7E800000
+
+// On board Inegrated flash Controller chip select configuration
+#define IFC_NOR_CS IFC_CS_MAX
+#define IFC_NAND_CS IFC_CS0
+#define IFC_FPGA_CS IFC_CS2
+
+// board-specific NAND timing
+#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x7) | \
+ IFC_FTIM0_NAND_TWP(0x18) | \
+ IFC_FTIM0_NAND_TWCHT(0x7) | \
+ IFC_FTIM0_NAND_TWH(0xa))
+
+#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x32) | \
+ IFC_FTIM1_NAND_TWBE(0x39) | \
+ IFC_FTIM1_NAND_TRR(0xe) | \
+ IFC_FTIM1_NAND_TRP(0x18))
+
+#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0xf) | \
+ IFC_FTIM2_NAND_TREH(0xa) | \
+ IFC_FTIM2_NAND_TWHRE(0x1e))
+
+#define NAND_FTIM3 0x0
+
+#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BUF_BASE) \
+ | IFC_CSPR_PORT_SIZE_8 \
+ | IFC_CSPR_MSEL_NAND \
+ | IFC_CSPR_V)
+
+#define NAND_CSPR_EXT 0x0
+#define NAND_AMASK 0xFFFF0000
+
+#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | IFC_CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
+ | IFC_CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | IFC_CSOR_NAND_PGS_4K /* Page Size = 4K */ \
+ | IFC_CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
+ | IFC_CSOR_NAND_PB(6)) /* 2^6 Pages Per Block */
+
+// board-specific fpga timing
+#define FPGA_BASE_PHYS 0x7fb00000
+#define FPGA_CSPR_EXT 0x0
+#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
+ IFC_CSPR_PORT_SIZE_8 | \
+ IFC_CSPR_MSEL_GPCM | \
+ IFC_CSPR_V)
+
+#define FPGA_AMASK IFC_AMASK(64 * 1024)
+#define FPGA_CSOR IFC_CSOR_NOR_ADM_SHIFT(16)
+
+#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0x0e) | \
+ IFC_FTIM0_GPCM_TEADC(0x0e) | \
+ IFC_FTIM0_GPCM_TEAHC(0x0e))
+#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \
+ IFC_FTIM1_GPCM_TRAD(0x3f))
+#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \
+ IFC_FTIM2_GPCM_TCH(0xf) | \
+ IFC_FTIM2_GPCM_TWP(0x3E))
+#define FPGA_FTIM3 0x0
+
+#endif //__IFC__BOARD_SPECIFIC_H__
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
new file mode 100644
index 0000000..0971935
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
@@ -0,0 +1,61 @@
+/** @file
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IfcBoardSpecific.h>
+
+VOID
+GetIfcNorFlashTimings (
+ IN IFC_TIMINGS * NorIfcTimings
+ )
+{
+ NorIfcTimings->CS = IFC_NOR_CS;
+
+ return ;
+}
+
+VOID
+GetIfcFpgaTimings (
+ IN IFC_TIMINGS *FpgaIfcTimings
+ )
+{
+ FpgaIfcTimings->Ftim[0] = FPGA_FTIM0;
+ FpgaIfcTimings->Ftim[1] = FPGA_FTIM1;
+ FpgaIfcTimings->Ftim[2] = FPGA_FTIM2;
+ FpgaIfcTimings->Ftim[3] = FPGA_FTIM3;
+ FpgaIfcTimings->Cspr = FPGA_CSPR;
+ FpgaIfcTimings->CsprExt = FPGA_CSPR_EXT;
+ FpgaIfcTimings->Amask = FPGA_AMASK;
+ FpgaIfcTimings->Csor = FPGA_CSOR;
+ FpgaIfcTimings->CS = IFC_FPGA_CS;
+
+ return;
+}
+
+VOID
+GetIfcNandFlashTimings (
+ IN IFC_TIMINGS * NandIfcTimings
+ )
+{
+ NandIfcTimings->Ftim[0] = NAND_FTIM0;
+ NandIfcTimings->Ftim[1] = NAND_FTIM1;
+ NandIfcTimings->Ftim[2] = NAND_FTIM2;
+ NandIfcTimings->Ftim[3] = NAND_FTIM3;
+ NandIfcTimings->Cspr = NAND_CSPR;
+ NandIfcTimings->CsprExt = NAND_CSPR_EXT;
+ NandIfcTimings->Amask = NAND_AMASK;
+ NandIfcTimings->Csor = NAND_CSOR;
+ NandIfcTimings->CS = IFC_NAND_CS;
+
+ return;
+}
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
new file mode 100644
index 0000000..151c383
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
@@ -0,0 +1,31 @@
+# @file
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = BoardLib
+ FILE_GUID = 66041dab-97b4-4b45-b9b4-1209a2d55d7a
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardLib
+
+[Sources.common]
+ BoardLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[FixedPcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 22/41] Platform/NXP: Add ArmPlatformLib for LS1046A
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (20 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 21/41] Platform/NXP: LS1046A RDB Board Library Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-19 19:08 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 23/41] Platform/NXP: Add Platform driver for LS1046 RDB board Meenakshi Aggarwal
` (20 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
Adding support of ArmPlatformLib for NXP LS1046ARDB board
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
.../Library/PlatformLib/ArmPlatformLib.c | 105 ++++++++++++++
.../Library/PlatformLib/ArmPlatformLib.inf | 66 +++++++++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 35 +++++
.../Library/PlatformLib/NxpQoriqLsMem.c | 152 +++++++++++++++++++++
4 files changed, 358 insertions(+)
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 0000000..c59a06a
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,105 @@
+/** ArmPlatformLib.c
+*
+* Contains board initialization functions.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+extern VOID SocInit (VOID);
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Placeholder for Platform Initialization
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+ARM_CORE_INFO LS1046aMpCoreInfoCTA72x4[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = sizeof (LS1046aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = LS1046aMpCoreInfoCTA72x4;
+
+ return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+ IN UINTN MpId
+ )
+{
+ return 1;
+}
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 0000000..49b57fc
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,66 @@
+# @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformLib
+ FILE_GUID = 05a9029b-266f-421d-bb46-0e8385c64aa0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ArmLib
+ SocLib
+
+[Sources.common]
+ NxpQoriqLsHelper.S | GCC
+ NxpQoriqLsMem.c
+ ArmPlatformLib.c
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
new file mode 100644
index 0000000..6d54091
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
@@ -0,0 +1,35 @@
+# @file
+#
+# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_IMPORT(ArmReadMpidr)
+
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ tst x0, #3
+ cset x0, eq
+ ret
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ ret
+
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
+ ldrh w0, [x0]
+ ret
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
new file mode 100644
index 0000000..64c5612
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -0,0 +1,152 @@
+/** NxpQoriqLsMem.c
+*
+* Board memory specific Library.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
+ )
+{
+ UINTN Index;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ Index = 0;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
+ EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ // DRAM1 (Must be 1st entry)
+ VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // CCSR Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IFC region 1
+ //
+ // A-009241 : Unaligned write transactions to IFC may result in corruption of data
+ // Affects : IFC
+ // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
+ // writes on external IFC interface that can corrupt data on external flash.
+ // Impact : Data corruption on external flash may happen in case of unaligned writes to
+ // IFC memory space.
+ // Workaround: Following are the workarounds:
+ // For write transactions from core, IFC interface memories (including IFC SRAM)
+ // should be configured as device type memory in MMU.
+ // For write transactions from non-core masters (like system DMA), the address
+ // should be 16 byte aligned and the data size should be multiple of 16 bytes.
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // QMAN SWP
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // BMAN SWP
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // IFC region 2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DRAM2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // PCIe1
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe3
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DRAM3
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram3BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram3BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram3Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // QSPI region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 23/41] Platform/NXP: Add Platform driver for LS1046 RDB board
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (21 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 22/41] Platform/NXP: Add ArmPlatformLib for LS1046A Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-19 22:05 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 24/41] Platform/NXP: Compilation for LS1046A RDB Board Meenakshi Aggarwal
` (19 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../Drivers/PlatformDxe/PlatformDxe.c | 119 +++++++++++++++++++++
.../Drivers/PlatformDxe/PlatformDxe.inf | 58 ++++++++++
2 files changed, 177 insertions(+)
create mode 100644 Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
create mode 100644 Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
diff --git a/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
new file mode 100644
index 0000000..b74818e
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -0,0 +1,119 @@
+/** @file
+ LS1046 RDB board DXE platform driver.
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/NonDiscoverableDevice.h>
+
+typedef struct {
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR StartDesc;
+ UINT8 EndDesc;
+} ADDRESS_SPACE_DESCRIPTOR;
+
+STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
+
+STATIC
+EFI_STATUS
+RegisterDevice (
+ IN EFI_GUID *TypeGuid,
+ IN ADDRESS_SPACE_DESCRIPTOR *Desc,
+ OUT EFI_HANDLE *Handle
+ )
+{
+ NON_DISCOVERABLE_DEVICE *Device;
+ EFI_STATUS Status;
+
+ Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device));
+ if (Device == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Device->Type = TypeGuid;
+ Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent;
+ Device->Resources = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Desc;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (Handle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid, Device,
+ NULL);
+ if (EFI_ERROR (Status)) {
+ goto FreeDevice;
+ }
+ return EFI_SUCCESS;
+
+FreeDevice:
+ FreePool (Device);
+
+ return Status;
+}
+
+VOID
+PopulateI2cInformation (
+ IN VOID
+ )
+{
+ UINT32 Index;
+
+ for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
+ mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+ mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
+ mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ mI2cDesc[Index].StartDesc.GenFlag = 0;
+ mI2cDesc[Index].StartDesc.SpecificFlag = 0;
+ mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
+ mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
+ (Index * FixedPcdGet32 (PcdI2cSize));
+ mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
+ FixedPcdGet32 (PcdI2cSize) - 1;
+ mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
+ mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
+
+ mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
+ }
+}
+
+EFI_STATUS
+EFIAPI
+PlatformDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ Handle = NULL;
+
+ PopulateI2cInformation ();
+
+ Status = RegisterDevice (&gNxpNonDiscoverableI2cMasterGuid,
+ &mI2cDesc[3], &Handle);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install the DS1307 I2C Master protocol on this handle so the RTC driver
+ // can identify it as the I2C master it can invoke directly.
+ //
+ Status = gBS->InstallProtocolInterface (&Handle,
+ &gPcf2129RealTimeClockLibI2cMasterProtocolGuid,
+ EFI_NATIVE_INTERFACE, NULL);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
new file mode 100644
index 0000000..2556af2
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -0,0 +1,58 @@
+## @file
+#
+# Component description file for LS1046 DXE platform driver.
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformDxe
+ FILE_GUID = 5bf02256-a7d2-4bfd-9934-2055358c6a6c
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PlatformDxeEntryPoint
+
+[Sources]
+ PlatformDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ MemoryAllocationLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Guids]
+ gNxpNonDiscoverableI2cMasterGuid
+
+[Protocols]
+ gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
+ gPcf2129RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES
+
+[FixedPcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
+
+[Depex]
+ TRUE
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 24/41] Platform/NXP: Compilation for LS1046A RDB Board
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (22 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 23/41] Platform/NXP: Add Platform driver for LS1046 RDB board Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-20 17:39 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 25/41] Silicon/NXP:SocLib support for initialization of peripherals Meenakshi Aggarwal
` (18 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
Adding firmware device,description and declaration files to enable
compilation for NXP LS1046ARDB board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec | 29 ++++
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 90 ++++++++++++
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 198 +++++++++++++++++++++++++++
3 files changed, 317 insertions(+)
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
new file mode 100644
index 0000000..a872ade
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
@@ -0,0 +1,29 @@
+# LS1046aRdbPkg.dec
+# LS1046a board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ PACKAGE_NAME = LS1046aRdbPkg
+ PACKAGE_GUID = c0c8d5e4-f63b-4470-89bc-73c13c13b247
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
new file mode 100644
index 0000000..7eb08a9
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
@@ -0,0 +1,90 @@
+# LS1046aRdbPkg.dsc
+#
+# LS1046ARDB Board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_NAME = LS1046aRdbPkg
+ PLATFORM_GUID = 43920156-3f3b-4199-9b29-c6db1fb792b0
+ OUTPUT_DIRECTORY = Build/LS1046aRdbPkg
+ FLASH_DEFINITION = Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
+
+!include Platform/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS1046A/LS1046A.dsc.inc
+
+[LibraryClasses.common]
+ SocLib|Silicon/NXP/Library/SocLib/LS1046aSocLib.inf
+ ArmPlatformLib|Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+ IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
+ RealTimeClockLib|Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
+ IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
+ BoardLib|Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
+ FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf
+
+[PcdsFixedAtBuild.common]
+
+ #
+ # LS1046a board Specific PCDs
+ # XX (DRAM - Region 1 2GB)
+ # (NOR - IFC Region 1 512MB)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
+ #
+ # Board Specific Pcds
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x2
+
+ #
+ # Big Endian IPs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
+
+ #
+ # RTC Pcds
+ #
+ gPcf2129RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
+ gPcf2129RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # Architectural Protocols
+ #
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+
+ Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
+ Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+
+ Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+ ##
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
new file mode 100644
index 0000000..443b561
--- /dev/null
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
@@ -0,0 +1,198 @@
+# LS1046aRdbPkg.fdf
+#
+# FLASH layout file for LS1046a board.
+#
+# Copyright (c) 2016, Freescale Ltd. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LS1046ARDB_EFI]
+BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
+Size = 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xED000
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x000ED000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+!include Platform/NXP/FVRules.fdf.inc
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize = 0x1
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+ INF Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+
+ INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ #
+ # Network modules
+ #
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+ INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+ INF NetworkPkg/TcpDxe/TcpDxe.inf
+ INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+ INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+ INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+ INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+!endif
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/FatPei/FatPei.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+ FILE FV_IMAGE = c1c1e1a2-3879-4b5e-9dd1-3df2ce60d8ec {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 25/41] Silicon/NXP:SocLib support for initialization of peripherals
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (23 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 24/41] Platform/NXP: Compilation for LS1046A RDB Board Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 9:22 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 26/41] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB Meenakshi Aggarwal
` (17 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Wasim Khan <wasim.khan@nxp.com>
Added SocInit function that initializes peripherals
and print board and soc information for LS2088ARDB Board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Include/Chassis3/SerDes.h | 91 ++++++++++++++
Silicon/NXP/Include/Chassis3/Soc.h | 144 +++++++++++++++++++++
Silicon/NXP/LS2088A/Include/SocSerDes.h | 67 ++++++++++
Silicon/NXP/Library/SocLib/Chassis.c | 38 ++++++
Silicon/NXP/Library/SocLib/Chassis.h | 17 +++
Silicon/NXP/Library/SocLib/Chassis3/Soc.c | 180 +++++++++++++++++++++++++++
Silicon/NXP/Library/SocLib/LS2088aSocLib.inf | 50 ++++++++
Silicon/NXP/Library/SocLib/SerDes.c | 3 +
8 files changed, 590 insertions(+)
create mode 100644 Silicon/NXP/Include/Chassis3/SerDes.h
create mode 100644 Silicon/NXP/Include/Chassis3/Soc.h
create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h
create mode 100644 Silicon/NXP/Library/SocLib/Chassis3/Soc.c
create mode 100644 Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
diff --git a/Silicon/NXP/Include/Chassis3/SerDes.h b/Silicon/NXP/Include/Chassis3/SerDes.h
new file mode 100644
index 0000000..a77ddd5
--- /dev/null
+++ b/Silicon/NXP/Include/Chassis3/SerDes.h
@@ -0,0 +1,91 @@
+/** SerDes.h
+ The Header file of SerDes Module for Chassis 3
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SERDES_H__
+#define __SERDES_H__
+
+#include <Uefi/UefiBaseType.h>
+
+#define SRDS_MAX_LANES 8
+
+//
+// SerDes lane protocols/devices
+//
+typedef enum {
+ NONE = 0,
+ PCIE1,
+ PCIE2,
+ PCIE3,
+ PCIE4,
+ SATA1,
+ SATA2,
+ XAUI1,
+ XAUI2,
+ XFI1,
+ XFI2,
+ XFI3,
+ XFI4,
+ XFI5,
+ XFI6,
+ XFI7,
+ XFI8,
+ SGMII1,
+ SGMII2,
+ SGMII3,
+ SGMII4,
+ SGMII5,
+ SGMII6,
+ SGMII7,
+ SGMII8,
+ SGMII9,
+ SGMII10,
+ SGMII11,
+ SGMII12,
+ SGMII13,
+ SGMII14,
+ SGMII15,
+ SGMII16,
+ QSGMII_A,
+ QSGMII_B,
+ QSGMII_C,
+ QSGMII_D,
+ // Number of entries in this enum
+ SERDES_PRTCL_COUNT
+} SERDES_PROTOCOL;
+
+typedef enum {
+ SRDS_1 = 0,
+ SRDS_2,
+ SRDS_MAX_NUM
+} SERDES_NUMBER;
+
+typedef struct {
+ UINT16 Protocol;
+ UINT8 SrdsLane[SRDS_MAX_LANES];
+} SERDES_CONFIG;
+
+typedef VOID
+(*SERDES_PROBE_LANES_CALLBACK) (
+ IN SERDES_PROTOCOL LaneProtocol,
+ IN VOID *Arg
+ );
+
+VOID
+SerDesProbeLanes(
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ );
+
+#endif /* __SERDES_H */
diff --git a/Silicon/NXP/Include/Chassis3/Soc.h b/Silicon/NXP/Include/Chassis3/Soc.h
new file mode 100644
index 0000000..8d967e7
--- /dev/null
+++ b/Silicon/NXP/Include/Chassis3/Soc.h
@@ -0,0 +1,144 @@
+/** Soc.h
+* Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#define FSL_CLK_GRPA_ADDR 0x01300000
+#define FSL_CLK_GRPB_ADDR 0x01310000
+
+#define FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } /* LS208x */
+#define TP_CLUSTER_EOC_MASK 0x80000000 /* Mask for End of clusters */
+#define NUM_CC_PLLS 6
+#define CLK_FREQ 100000000
+#define MAX_CPUS 16
+#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) != TP_CLUSTER_EOC_MASK)
+
+/* RCW SERDES MACRO */
+#define RCWSR_INDEX 28
+#define RCWSR_SRDS1_PRTCL_MASK 0x00ff0000
+#define RCWSR_SRDS1_PRTCL_SHIFT 16
+#define RCWSR_SRDS2_PRTCL_MASK 0xff000000
+#define RCWSR_SRDS2_PRTCL_SHIFT 24
+
+/* SMMU Defintions */
+#define SMMU_BASE_ADDR 0x05000000
+#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
+#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
+#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
+
+#define SCR0_USFCFG_MASK 0x00000400
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SACR_PAGESIZE_MASK 0x00010000
+
+typedef struct {
+ UINTN FreqProcessor[MAX_CPUS];
+ UINTN FreqSystemBus;
+ UINTN FreqDdrBus;
+ UINTN FreqDdrBus2;
+ UINTN FreqLocalBus;
+ UINTN FreqSdhc;
+ UINTN FreqFman[1];
+ UINTN FreqQman;
+ UINTN FreqPme;
+} SYS_INFO;
+
+/* Device Configuration and Pin Control */
+typedef struct {
+ UINT32 PorSr1; /* POR status 1 */
+ UINT32 PorSr2; /* POR status 2 */
+ UINT8 Res008[0x18];
+ UINT32 GppOrCr1; /* General-purpose POR configuration */
+ UINT32 GppOrCr2; /* General-purpose POR configuration 2 */
+ UINT32 DcfgFuseSr; /* Fuse status register */
+ UINT32 GppOrCr3;
+ UINT32 GppOrCr4;
+ UINT8 Res034[0x3C];
+ UINT32 DevDisr; /* Device disable control */
+ UINT32 DevDisr2; /* Device disable control 2 */
+ UINT32 DevDisr3; /* Device disable control 3 */
+ UINT32 DevDisr4; /* Device disable control 4 */
+ UINT32 DevDisr5; /* Device disable control 5 */
+ UINT32 DevDisr6; /* Device disable control 6 */
+ UINT32 DevDisr7; /* Device disable control 7 */
+ UINT8 Res08c[0x4];
+ UINT32 CoreDisrUpper; /* uppper portion for support of 64 cores */
+ UINT32 CoreDisrLower; /* lower portion for support of 64 cores */
+ UINT8 Res098[0x8];
+ UINT32 Pvr; /* Processor version */
+ UINT32 Svr; /* System version */
+ UINT32 Mvr; /* Manufacturing version */
+ UINT8 Res0ac[0x54];
+ UINT32 RcwSr[32]; /* Reset control word status */
+#define CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT 2
+#define CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK 0x1f
+#define CHASSIS3_RCWSR_0_MEM_PLL_RAT_SHIFT 10
+#define CHASSIS3_RCWSR_0_MEM_PLL_RAT_MASK 0x3f
+#define CHASSIS3_RCWSR_0_MEM2_PLL_RAT_SHIFT 18
+#define CHASSIS3_RCWSR_0_MEM2_PLL_RAT_MASK 0x3f
+ UINT8 Res180[0x80];
+ UINT32 ScratchRw[32]; /* Scratch Read/Write */
+ UINT8 Res280[0x80];
+ UINT32 ScratchW1R[4]; /* Scratch Read (Write once) */
+ UINT8 Res310[0xF0];
+ UINT32 BootLocPtrL; /* Low addr : Boot location pointer */
+ UINT32 BootLocPtrH; /* High addr : Boot location pointer */
+ UINT8 Res408[0xF8];
+ UINT8 Res500[0x240];
+ UINT32 TpItyp[64];
+ struct {
+ UINT32 Upper;
+ UINT32 Lower;
+ } TpCluster[3];
+ UINT8 Res858[0x7A8];
+} CCSR_GUR;
+
+/* Clocking */
+typedef struct {
+ struct {
+ UINT32 Csr; /* core cluster n clock control status */
+ UINT8 Res04[0x1C];
+ } ClkCnCsr[8];
+} CCSR_CLT_CTRL;
+
+/* Clock Cluster */
+typedef struct {
+ struct {
+ UINT8 Res00[0x10];
+ UINT32 Csr; /* core cluster n clock control status */
+ UINT8 Res14[0xC];
+ } HwnCsr[3];
+ UINT8 Res60[0x20];
+ struct {
+ UINT32 Gsr; /* core cluster n clock general status */
+ UINT8 Res84[0x1C];
+ } PllnGsr[3];
+ UINT8 Rese0[0x20];
+} CCSR_CLK_CLUSTER;
+
+VOID
+GetSysInfo (
+ OUT SYS_INFO *
+ );
+
+UINT32
+EFIAPI
+GurRead (
+ IN UINTN Address
+ );
+
+#endif /* __SOC_H__ */
diff --git a/Silicon/NXP/LS2088A/Include/SocSerDes.h b/Silicon/NXP/LS2088A/Include/SocSerDes.h
new file mode 100644
index 0000000..9135423
--- /dev/null
+++ b/Silicon/NXP/LS2088A/Include/SocSerDes.h
@@ -0,0 +1,67 @@
+/** @file
+ The Header file of SerDes Module for LS2088A
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SOC_SERDES_H__
+#define __SOC_SERDES_H__
+
+#include <Chassis3/SerDes.h>
+
+SERDES_CONFIG SerDes1ConfigTbl[] = {
+ // SerDes 1
+ { 0x03, { PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
+ { 0x05, { PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x07, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x09, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x0A, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x0C, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x0E, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
+ { 0x26, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
+ { 0x28, { SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
+ { 0x2A, { XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
+ { 0x2B, { SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
+ { 0x32, { XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
+ { 0x33, { PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B, QSGMII_A } },
+ { 0x35, { QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+ {}
+};
+
+SERDES_CONFIG SerDes2ConfigTbl[] = {
+ // SerDes 2
+ { 0x07, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x09, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x0A, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x0C, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x0E, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
+ { 0x3D, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
+ { 0x3E, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
+ { 0x3F, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
+ { 0x40, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
+ { 0x41, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
+ { 0x42, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
+ { 0x43, { PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
+ { 0x44, { PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
+ { 0x45, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, PCIE4 } },
+ { 0x47, { PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, SGMII16 } },
+ { 0x49, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } },
+ { 0x4A, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } },
+ {}
+};
+
+SERDES_CONFIG *SerDesConfigTbl[] = {
+ SerDes1ConfigTbl,
+ SerDes2ConfigTbl
+};
+
+#endif /* __SOC_SERDES_H */
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
index e8e69a6..58f1ba7 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.c
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -16,6 +16,8 @@
#include <Base.h>
#ifdef CHASSIS2
#include <Chassis2/Soc.h>
+#elif CHASSIS3
+#include <Chassis3/Soc.h>
#endif
#include <Library/BaseLib.h>
#include <Library/IoAccessLib.h>
@@ -46,6 +48,7 @@ GurRead (
STATIC CPU_TYPE CpuTypeList[] = {
CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
+ CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
};
/*
@@ -133,6 +136,41 @@ CpuNumCores (
}
/*
+ * Return core's cluster
+ */
+INT32
+QoriqCoreToCluster (
+ IN UINTN Core
+ )
+{
+ CCSR_GUR *GurBase;
+ UINTN ClusterIndex;
+ UINTN Count;
+ UINT32 Cluster;
+ UINT32 Type;
+ UINTN InitiatorIndex;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClusterIndex = 0;
+ Count = 0;
+ do {
+ Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+ for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+ Type = InitiatorType (Cluster, InitiatorIndex);
+ if (Type) {
+ if (Count == Core) {
+ return ClusterIndex;
+ }
+ Count++;
+ }
+ }
+ ClusterIndex++;
+ } while (CHECK_CLUSTER (Cluster));
+
+ return -1; // cannot identify the cluster
+}
+
+/*
* Return the type of core i.e. A53, A57 etc of inputted
* core number.
*/
diff --git a/Silicon/NXP/Library/SocLib/Chassis.h b/Silicon/NXP/Library/SocLib/Chassis.h
index 5b7e5c4..3ac18bf 100644
--- a/Silicon/NXP/Library/SocLib/Chassis.h
+++ b/Silicon/NXP/Library/SocLib/Chassis.h
@@ -57,6 +57,7 @@ CpuMaskNext (
#define SVR_WO_E 0xFFFFFE
#define SVR_LS1043A 0x879200
#define SVR_LS1046A 0x870700
+#define SVR_LS2088A 0x870901
#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
@@ -142,4 +143,20 @@ CpuNumCores (
VOID
);
+/*
+ * Return the type of initiator for core/hardware accelerator for given core index.
+ */
+UINTN
+QoriqCoreToType (
+ IN UINTN Core
+ );
+
+/*
+ * Return the cluster of initiator for core/hardware accelerator for given core index.
+ */
+INT32
+QoriqCoreToCluster (
+ IN UINTN Core
+ );
+
#endif /* __CHASSIS_H__ */
diff --git a/Silicon/NXP/Library/SocLib/Chassis3/Soc.c b/Silicon/NXP/Library/SocLib/Chassis3/Soc.c
new file mode 100644
index 0000000..0fc92f4
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/Chassis3/Soc.c
@@ -0,0 +1,180 @@
+/** @Soc.c
+ SoC specific Library containg functions to initialize various SoC components
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Chassis.h>
+#include <Chassis3/Soc.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+VOID
+GetSysInfo (
+ OUT SYS_INFO *PtrSysInfo
+ )
+{
+ UINT32 Index;
+ CCSR_GUR *GurBase;
+ CCSR_CLT_CTRL *ClkBase;
+ CCSR_CLK_CLUSTER *ClkGrp[2] = {
+ (VOID *) (FSL_CLK_GRPA_ADDR),
+ (VOID *) (FSL_CLK_GRPB_ADDR)
+ };
+
+ CONST UINT8 CoreCplxPll[16] = {
+ [0] = 0, // CC1 PPL / 1
+ [1] = 0, // CC1 PPL / 2
+ [2] = 0, // CC1 PPL / 4
+ [4] = 1, // CC2 PPL / 1
+ [5] = 1, // CC2 PPL / 2
+ [6] = 1, // CC2 PPL / 4
+ [8] = 2, // CC3 PPL / 1
+ [9] = 2, // CC3 PPL / 2
+ [10] = 2, // CC3 PPL / 4
+ [12] = 3, // CC4 PPL / 1
+ [13] = 3, // CC4 PPL / 2
+ [14] = 3, // CC4 PPL / 4
+ };
+
+ CONST UINT8 CoreCplxPllDivisor[16] = {
+ [0] = 1, // CC1 PPL / 1
+ [1] = 2, // CC1 PPL / 2
+ [2] = 4, // CC1 PPL / 4
+ [4] = 1, // CC2 PPL / 1
+ [5] = 2, // CC2 PPL / 2
+ [6] = 4, // CC2 PPL / 4
+ [8] = 1, // CC3 PPL / 1
+ [9] = 2, // CC3 PPL / 2
+ [10] = 4, // CC3 PPL / 4
+ [12] = 1, // CC4 PPL / 1
+ [13] = 2, // CC4 PPL / 2
+ [14] = 4, // CC4 PPL / 4
+ };
+
+ INT32 CcGroup[12] = FSL_CLUSTER_CLOCKS;
+ UINTN PllCount;
+ UINTN Cluster;
+ UINTN FreqCPll[NUM_CC_PLLS];
+ UINTN PllRatio[NUM_CC_PLLS];
+ UINTN SysClk;
+ UINT32 Cpu;
+ UINT32 CPllSel;
+ UINT32 CplxPll;
+ VOID *Offset;
+
+ SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
+ SysClk = CLK_FREQ;
+
+ PtrSysInfo->FreqSystemBus = SysClk;
+ PtrSysInfo->FreqDdrBus = PcdGet64 (PcdDdrClk);
+ PtrSysInfo->FreqDdrBus2 = PcdGet64 (PcdDdrClk);
+
+ //
+ // selects the platform clock:SYSCLK ratio and calculate
+ // system frequency
+ //
+ PtrSysInfo->FreqSystemBus *=
+ (GurRead ((UINTN)&GurBase->RcwSr[0]) >> CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT) &
+ CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK;
+
+ //
+ // Platform clock is half of platform PLL
+ //
+ PtrSysInfo->FreqSystemBus /= PcdGet32 (PcdPlatformFreqDiv);
+
+ //
+ // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
+ //
+ PtrSysInfo->FreqDdrBus *=
+ (GurRead ((UINTN)&GurBase->RcwSr[0]) >> CHASSIS3_RCWSR_0_MEM_PLL_RAT_SHIFT) &
+ CHASSIS3_RCWSR_0_MEM_PLL_RAT_MASK;
+
+ PtrSysInfo->FreqDdrBus2 *=
+ (GurRead ((UINTN)&GurBase->RcwSr[0]) >> CHASSIS3_RCWSR_0_MEM2_PLL_RAT_SHIFT) &
+ CHASSIS3_RCWSR_0_MEM2_PLL_RAT_MASK;
+
+ for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
+ Offset = (VOID *)((UINTN)ClkGrp[PllCount/3] +
+ __builtin_offsetof (CCSR_CLK_CLUSTER, PllnGsr[PllCount%3].Gsr));
+ PllRatio[PllCount] = (GurRead ((UINTN)Offset) >> 1) & 0x3f;
+ FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
+ }
+
+ //
+ // Calculate Core frequency
+ //
+ ForEachCpu (Index, Cpu, CpuNumCores (), CpuMask ()) {
+ Cluster = QoriqCoreToCluster (Cpu);
+ ASSERT_EFI_ERROR (Cluster);
+ CPllSel = (GurRead ((UINTN)&ClkBase->ClkCnCsr[Cluster].Csr) >> 27) & 0xf;
+ CplxPll = CoreCplxPll[CPllSel];
+ CplxPll += CcGroup[Cluster] - 1;
+ PtrSysInfo->FreqProcessor[Cpu] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
+ }
+ PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
+}
+
+/**
+ Perform the early initialization.
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+
+**/
+VOID
+SocInit (
+ VOID
+ )
+{
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+
+ //
+ // Initialize SMMU
+ //
+ SmmuInit ();
+
+ //
+ // Initialize the Serial Port.
+ // Early serial port initialization is required to print RCW,
+ // Soc and CPU infomation at the begining of UEFI boot.
+ //
+ SerialPortInitialize ();
+
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer),
+ "\nUEFI firmware (version %s built at %a on %a)\n\r",
+ (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__);
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+ //
+ // Print CPU information
+ //
+ PrintCpuInfo ();
+
+ //
+ // Print Reset Controll Word
+ //
+ PrintRCW ();
+
+ //
+ // Print Soc Personality information
+ //
+ PrintSoc ();
+}
diff --git a/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf b/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
new file mode 100644
index 0000000..3d9237d
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
@@ -0,0 +1,50 @@
+# @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SocLib
+ FILE_GUID = 3b233a6a-0ee1-42a3-a7f7-c285b5ba80dc
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/LS2088A/LS2088A.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoAccessLib
+ SerialPortLib
+
+[Sources.common]
+ Chassis.c
+ Chassis3/Soc.c
+ SerDes.c
+
+[BuildOptions]
+ GCC:*_*_*_CC_FLAGS = -DCHASSIS3
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDdrClk
diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocLib/SerDes.c
index e31e4f3..9eba8ae 100644
--- a/Silicon/NXP/Library/SocLib/SerDes.c
+++ b/Silicon/NXP/Library/SocLib/SerDes.c
@@ -16,6 +16,9 @@
#ifdef CHASSIS2
#include <Chassis2/SerDes.h>
#include <Chassis2/Soc.h>
+#elif CHASSIS3
+#include <Chassis3/SerDes.h>
+#include <Chassis3/Soc.h>
#endif
#include <Library/DebugLib.h>
#include <SocSerDes.h>
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 26/41] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (24 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 25/41] Silicon/NXP:SocLib support for initialization of peripherals Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 9:30 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 27/41] Platform/NXP: Add Platform driver for LS2088 RDB board Meenakshi Aggarwal
` (16 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Wasim Khan <wasim.khan@nxp.com>
Add support of ArmPlatformLib for NXP LS2088ARDB board
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
.../Library/PlatformLib/ArmPlatformLib.c | 106 ++++++++++++
.../Library/PlatformLib/ArmPlatformLib.inf | 77 +++++++++
.../Library/PlatformLib/NxpQoriqLsHelper.S | 35 ++++
.../Library/PlatformLib/NxpQoriqLsMem.c | 189 +++++++++++++++++++++
4 files changed, 407 insertions(+)
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 0000000..90f14ba
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,106 @@
+/** ArmPlatformLib.c
+*
+* Contains board initialization functions.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+extern VOID SocInit (VOID);
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Placeholder for Platform Initialization
+
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+ARM_CORE_INFO LS2088aMpCoreInfoCTA72x4[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = sizeof (LS2088aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = LS2088aMpCoreInfoCTA72x4;
+
+ return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+ IN UINTN MpId
+ )
+{
+ return 1;
+}
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 0000000..f5e5abd
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,77 @@
+#/** @file
+#
+# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformLib
+ FILE_GUID = d1361285-8a47-421c-9efd-6b262c9093fc
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ArmLib
+ SocLib
+
+[Sources.common]
+ ArmPlatformLib.c
+ NxpQoriqLsHelper.S | GCC
+ NxpQoriqLsMem.c
+
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalSize
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsCacheSize
+
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
new file mode 100644
index 0000000..1917b02
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
@@ -0,0 +1,35 @@
+#/** @file
+#
+# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#include <AsmMacroIoLibV8.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_IMPORT(ArmReadMpidr)
+
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ tst x0, #3
+ cset x0, eq
+ ret
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ ret
+
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
+ ldrh w0, [x0]
+ ret
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
new file mode 100644
index 0000000..ccb49f6
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -0,0 +1,189 @@
+/** NxpQoriqLsMem.c
+*
+* Board memory specific Library.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
+
+//
+// Calculate the MC (Management Complex) base address and DDR size based on
+// if the MC is loaded in DDR low memory region or in DDR high memory region.
+//
+#if FixedPcdGetBool (PcdMcHighMemSupport)
+#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemSize) - FixedPcdGet64 (PcdDpaa2McRamSize)
+#define MC_BASE_ADDR FixedPcdGet64 (PcdDram2BaseAddr) + DDR_MEM_SIZE
+#else
+#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemSize)
+#define MC_BASE_ADDR FixedPcdGet64 (PcdDram1BaseAddr) - FixedPcdGet64 (PcdDpaa2McRamSize)
+#endif
+
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR ** VirtualMemoryMap
+ )
+{
+ UINTN Index;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ Index = 0;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
+ EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ // DRAM1 (Must be 1st entry)
+ VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
+
+ // CCSR Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IFC region 1
+ //
+ // A-009241 : Unaligned write transactions to IFC may result in corruption of data
+ // Affects : IFC
+ // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
+ // writes on external IFC interface that can corrupt data on external flash.
+ // Impact : Data corruption on external flash may happen in case of unaligned writes to
+ // IFC memory space.
+ // Workaround: Following are the workarounds:
+ // For write transactions from core, IFC interface memories (including IFC SRAM)
+ // should be configured as device type memory in MMU.
+ // For write transactions from non-core masters (like system DMA), the address
+ // should be 16 byte aligned and the data size should be multiple of 16 bytes.
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IFC region 2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // QSPI region 1
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // QSPI region 2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegion2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegion2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegion2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // DRAM2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr);
+ VirtualMemoryTable[Index].Length = DDR_MEM_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
+
+ // MC private DRAM
+ VirtualMemoryTable[++Index].PhysicalBase = MC_BASE_ADDR;
+ VirtualMemoryTable[Index].VirtualBase = MC_BASE_ADDR;
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2McRamSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe1
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe3
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe4
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp4BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp4BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp4BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DPAA2 MC Portals region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2McPortalBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2McPortalBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2McPortalSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DPAA2 NI Portals region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2NiPortalsBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2NiPortalsBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2NiPortalsSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DPAA2 QBMAN Portals - cache enabled region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
+
+ // DPAA2 QBMAN Portals - cache inhibited region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2QBmanPortalSize) - FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 27/41] Platform/NXP: Add Platform driver for LS2088 RDB board
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (25 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 26/41] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 9:35 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 28/41] Silicon/Maxim: DS3232 RTC Library Support Meenakshi Aggarwal
` (15 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
.../Drivers/PlatformDxe/PlatformDxe.c | 119 +++++++++++++++++++++
.../Drivers/PlatformDxe/PlatformDxe.inf | 58 ++++++++++
2 files changed, 177 insertions(+)
create mode 100644 Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
new file mode 100644
index 0000000..667e750
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -0,0 +1,119 @@
+/** @file
+ LS2088 RDB board DXE platform driver.
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/NonDiscoverableDevice.h>
+
+typedef struct {
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR StartDesc;
+ UINT8 EndDesc;
+} ADDRESS_SPACE_DESCRIPTOR;
+
+STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
+
+STATIC
+EFI_STATUS
+RegisterDevice (
+ IN EFI_GUID *TypeGuid,
+ IN ADDRESS_SPACE_DESCRIPTOR *Desc,
+ OUT EFI_HANDLE *Handle
+ )
+{
+ NON_DISCOVERABLE_DEVICE *Device;
+ EFI_STATUS Status;
+
+ Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device));
+ if (Device == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Device->Type = TypeGuid;
+ Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent;
+ Device->Resources = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Desc;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (Handle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid, Device,
+ NULL);
+ if (EFI_ERROR (Status)) {
+ goto FreeDevice;
+ }
+ return EFI_SUCCESS;
+
+FreeDevice:
+ FreePool (Device);
+
+ return Status;
+}
+
+VOID
+PopulateI2cInformation (
+ IN VOID
+ )
+{
+ UINT32 Index;
+
+ for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
+ mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+ mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
+ mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ mI2cDesc[Index].StartDesc.GenFlag = 0;
+ mI2cDesc[Index].StartDesc.SpecificFlag = 0;
+ mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
+ mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
+ (Index * FixedPcdGet32 (PcdI2cSize));
+ mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
+ FixedPcdGet32 (PcdI2cSize) - 1;
+ mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
+ mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
+
+ mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
+ }
+}
+
+EFI_STATUS
+EFIAPI
+PlatformDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ Handle = NULL;
+
+ PopulateI2cInformation ();
+
+ Status = RegisterDevice (&gNxpNonDiscoverableI2cMasterGuid,
+ &mI2cDesc[0], &Handle);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install the DS3232 I2C Master protocol on this handle so the RTC driver
+ // can identify it as the I2C master it can invoke directly.
+ //
+ Status = gBS->InstallProtocolInterface (&Handle,
+ &gDs3232RealTimeClockLibI2cMasterProtocolGuid,
+ EFI_NATIVE_INTERFACE, NULL);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
new file mode 100644
index 0000000..1972022
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -0,0 +1,58 @@
+## @file
+#
+# Component description file for LS2088 DXE platform driver.
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformDxe
+ FILE_GUID = 71dbcbc8-8cde-41ff-b51c-02fe338a60c3
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PlatformDxeEntryPoint
+
+[Sources]
+ PlatformDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ MemoryAllocationLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Guids]
+ gNxpNonDiscoverableI2cMasterGuid
+
+[Protocols]
+ gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
+ gDs3232RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES
+
+[FixedPcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
+
+[Depex]
+ TRUE
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 28/41] Silicon/Maxim: DS3232 RTC Library Support
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (26 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 27/41] Platform/NXP: Add Platform driver for LS2088 RDB board Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 9:56 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 29/41] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
` (14 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Wasim Khan <wasim.khan@nxp.com>
Add Maxim DS3232 RTC Library support
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h | 49 +++
Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c | 420 +++++++++++++++++++++
.../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec | 34 ++
.../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf | 50 +++
4 files changed, 553 insertions(+)
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
new file mode 100644
index 0000000..cd1a321
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
@@ -0,0 +1,49 @@
+/** Ds3232Rtc.h
+*
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __DS3232RTC_H__
+#define __DS3232RTC_H__
+
+//RTC time register
+#define DS3232_SEC_REG_ADDR 0x00
+#define DS3232_MIN_REG_ADDR 0x01
+#define DS3232_HR_REG_ADDR 0x02
+#define DS3232_DAY_REG_ADDR 0x03
+#define DS3232_DATE_REG_ADDR 0x04
+#define DS3232_MON_REG_ADDR 0x05
+#define DS3232_YR_REG_ADDR 0x06
+
+#define DS3232_SEC_BIT_CH 0x80 // Clock Halt (in Register 0)
+
+//RTC control register
+#define DS3232_CTL_REG_ADDR 0x0e
+#define DS3232_STAT_REG_ADDR 0x0f
+
+#define START_YEAR 1970
+#define END_YEAR 2070
+
+//TIME MASKS
+#define MASK_SEC 0x7F
+#define MASK_MIN 0x7F
+#define MASK_HOUR 0x3F
+#define MASK_DAY 0x3F
+#define MASK_MONTH 0x1F
+
+typedef struct {
+ UINTN OperationCount;
+ EFI_I2C_OPERATION SetAddressOp;
+ EFI_I2C_OPERATION GetSetDateTimeOp;
+} RTC_I2C_REQUEST;
+
+#endif // __DS3232RTC_H__
diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
new file mode 100644
index 0000000..3ab94a8
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
@@ -0,0 +1,420 @@
+/** Ds3232RtcLib.c
+* Implement EFI RealTimeClock via RTC Lib for DS3232 RTC.
+*
+* Based on RTC implementation available in
+* EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
+*
+* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+* Copyright 2017 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/I2cMaster.h>
+
+#include "Ds3232Rtc.h"
+
+STATIC VOID *mDriverEventRegistration;
+STATIC EFI_HANDLE mI2cMasterHandle;
+STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
+
+/**
+ Read RTC register.
+
+ @param SlaveDeviceAddress Slave device address offset of RTC to be read.
+ @param RtcRegAddr Register offset of RTC to be read.
+
+ @retval Register Value read
+
+**/
+STATIC
+UINT8
+RtcRead (
+ IN UINT8 SlaveDeviceAddress,
+ IN UINT8 RtcRegAddr
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+ UINT8 Val;
+
+ Val = 0;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress,
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
+ }
+
+ return Val;
+}
+
+/**
+ Write RTC register.
+
+ @param SlaveDeviceAddress Slave device address offset of RTC to be read.
+ @param RtcRegAddr Register offset of RTC to write.
+ @param Val Value to be written
+
+**/
+STATIC
+VOID
+RtcWrite (
+ IN UINT8 SlaveDeviceAddress,
+ IN UINT8 RtcRegAddr,
+ IN UINT8 Val
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = 0;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress,
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
+ }
+}
+
+/**
+ Configure the MUX device connected to I2C.
+
+ @param RegValue Value to write on mux device register address
+
+**/
+VOID
+ConfigureMuxDevice (
+ IN UINT8 RegValue
+ )
+{
+ RtcWrite (FixedPcdGet8 (PcdMuxDeviceAddress), FixedPcdGet8 (PcdMuxControlRegOffset), RegValue);
+}
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Second;
+ UINT8 Minute;
+ UINT8 Hour;
+ UINT8 Day;
+ UINT8 Month;
+ UINT8 Year;
+
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ Status = EFI_SUCCESS;
+
+ //
+ // Check if the I2C device is connected though a MUX device.
+ //
+ if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
+ // Switch to the channel connected to Ds3232 RTC
+ ConfigureMuxDevice (FixedPcdGet8 (PcdMuxRtcChannelValue));
+ }
+
+ Second = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR);
+ Minute = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MIN_REG_ADDR);
+ Hour = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_HR_REG_ADDR);
+ Day = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_DATE_REG_ADDR);
+ Month = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MON_REG_ADDR);
+ Year = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_YR_REG_ADDR);
+
+ if (Second & DS3232_SEC_BIT_CH) {
+ DEBUG ((DEBUG_ERROR, "### Warning: RTC oscillator has stopped\n"));
+ /* clear the CH flag */
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR,
+ RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR) & ~DS3232_SEC_BIT_CH);
+ Status = EFI_DEVICE_ERROR;
+ goto EXIT;
+ }
+
+ Time->Second = BcdToDecimal8 (Second & MASK_SEC);
+ Time->Minute = BcdToDecimal8 (Minute & MASK_MIN);
+ Time->Hour = BcdToDecimal8 (Hour & MASK_HOUR);
+ Time->Day = BcdToDecimal8 (Day & MASK_DAY);
+ Time->Month = BcdToDecimal8 (Month & MASK_MONTH);
+
+ //
+ // RTC can save year 1970 to 2069
+ // On writing Year, save year % 100
+ // On Reading reversing the operation e.g. 2012
+ // write = 12 (2012 % 100)
+ // read = 2012 (12 + 2000)
+ //
+ Time->Year = BcdToDecimal8 (Year) +
+ (BcdToDecimal8 (Year) >= 70 ? START_YEAR - 70 : END_YEAR -70);
+
+EXIT:
+ if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
+ // Switch to the default channel
+ ConfigureMuxDevice (FixedPcdGet8 (PcdMuxDefaultChannelValue));
+ }
+
+ return Status;
+}
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ if (Time->Year < START_YEAR || Time->Year >= END_YEAR){
+ DEBUG ((DEBUG_ERROR, "WARNING: Year should be between 1970 and 2069!\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check if the I2C device is connected though a MUX device.
+ //
+ if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
+ // Switch to the channel connected to Ds3232 RTC
+ ConfigureMuxDevice (FixedPcdGet8 (PcdMuxRtcChannelValue));
+ }
+
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_YR_REG_ADDR, DecimalToBcd8 (Time->Year % 100));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MON_REG_ADDR, DecimalToBcd8 (Time->Month));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_DATE_REG_ADDR, DecimalToBcd8 (Time->Day));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_HR_REG_ADDR, DecimalToBcd8 (Time->Hour));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MIN_REG_ADDR, DecimalToBcd8 (Time->Minute));
+ RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR, DecimalToBcd8 (Time->Second));
+
+ if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
+ // Switch to the default channel
+ ConfigureMuxDevice (FixedPcdGet8 (PcdMuxDefaultChannelValue));
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // Currently not supporting this feature.
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // Currently not supporting this feature.
+ return EFI_UNSUPPORTED;
+}
+
+STATIC
+VOID
+I2cDriverRegistrationEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_I2C_MASTER_PROTOCOL *I2cMaster;
+ UINTN BusFrequency;
+ EFI_HANDLE Handle;
+ UINTN BufferSize;
+
+ //
+ // Try to connect the newly registered driver to our handle.
+ //
+ do {
+ BufferSize = sizeof (EFI_HANDLE);
+ Status = gBS->LocateHandle (ByRegisterNotify,
+ &gEfiI2cMasterProtocolGuid,
+ mDriverEventRegistration,
+ &BufferSize,
+ &Handle);
+ if (EFI_ERROR (Status)) {
+ if (Status != EFI_NOT_FOUND) {
+ DEBUG ((DEBUG_WARN, "%a: gBS->LocateHandle () returned %r\n",
+ __FUNCTION__, Status));
+ }
+ break;
+ }
+
+ if (Handle != mI2cMasterHandle) {
+ continue;
+ }
+
+ DEBUG ((DEBUG_INFO, "%a: found I2C master!\n", __FUNCTION__));
+
+ gBS->CloseEvent (Event);
+
+ Status = gBS->OpenProtocol (mI2cMasterHandle, &gEfiI2cMasterProtocolGuid,
+ (VOID **)&I2cMaster, gImageHandle, NULL,
+ EFI_OPEN_PROTOCOL_EXCLUSIVE);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = I2cMaster->Reset (I2cMaster);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
+ __FUNCTION__, Status));
+ break;
+ }
+
+ BusFrequency = FixedPcdGet16 (PcdI2cBusFrequency);
+ Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
+ __FUNCTION__, Status));
+ break;
+ }
+
+ mI2cMaster = I2cMaster;
+ break;
+ } while (TRUE);
+
+ return;
+
+}
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+
+ //
+ // Find the handle that marks the controller
+ // that will provide the I2C master protocol.
+ //
+ BufferSize = sizeof (EFI_HANDLE);
+ Status = gBS->LocateHandle (
+ ByProtocol,
+ &gDs3232RealTimeClockLibI2cMasterProtocolGuid,
+ NULL,
+ &BufferSize,
+ &mI2cMasterHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register a protocol registration notification callback on the driver
+ // binding protocol so we can attempt to connect our I2C master to it
+ // as soon as it appears.
+ //
+ EfiCreateProtocolNotifyEvent (
+ &gEfiI2cMasterProtocolGuid,
+ TPL_CALLBACK,
+ I2cDriverRegistrationEvent,
+ NULL,
+ &mDriverEventRegistration);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
new file mode 100644
index 0000000..a0033a2
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
@@ -0,0 +1,34 @@
+#/** @file
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+ PACKAGE_NAME = Ds3232RtcLib
+ PACKAGE_GUID = 0b4192f7-e404-4019-b2e5-1e6004da3313
+ PACKAGE_VERSION = 0.1
+
+[Guids]
+ gDs3232RtcLibTokenSpaceGuid = { 0x7960fc51, 0x0832, 0x4f0b, { 0xb4, 0x22, 0x53, 0x87, 0x03, 0xaa, 0x85, 0xda }}
+
+[Protocols]
+ gDs3232RealTimeClockLibI2cMasterProtocolGuid = { 0xa17eb2ee, 0xcadc, 0x40f1, { 0x8a, 0x45, 0x4d, 0x5a, 0xf3, 0xd6, 0xce, 0x53 }}
+
+[PcdsFixedAtBuild]
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002
+ gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed|FALSE|BOOLEAN|0x00000003
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress|0|UINT8|0x00000004
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset|0|UINT8|0x00000005
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0|UINT8|0x00000006
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0|UINT8|0x00000007
diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
new file mode 100644
index 0000000..95664c1
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
@@ -0,0 +1,50 @@
+# @Ds3232RtcLib.inf
+#
+# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Ds3232RtcLib
+ FILE_GUID = 97f1f2c2-51e1-47ad-9660-70b33da1fe71
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+[Sources.common]
+ Ds3232RtcLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
+
+[LibraryClasses]
+ DebugLib
+ UefiBootServicesTableLib
+ UefiLib
+
+[Protocols]
+ gEfiI2cMasterProtocolGuid ## CONSUMES
+ gDs3232RealTimeClockLibI2cMasterProtocolGuid ## CONSUMES
+
+[FixedPcd]
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency
+ gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue
+
+[Depex]
+ gDs3232RealTimeClockLibI2cMasterProtocolGuid
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 29/41] Compilation : Add the fdf, dsc and dec files
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (27 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 28/41] Silicon/Maxim: DS3232 RTC Library Support Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 10:17 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 30/41] Platform/NXP: LS2088A RDB Board Library Meenakshi Aggarwal
` (13 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
The firmware device, description and declaration files for LS2088 board
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec | 29 ++++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 96 +++++++++++++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 200 +++++++++++++++++++++++++++
Silicon/NXP/LS2088A/LS2088A.dec | 22 +++
Silicon/NXP/LS2088A/LS2088A.dsc.inc | 71 ++++++++++
Silicon/NXP/NxpQoriqLs.dec | 13 ++
6 files changed, 431 insertions(+)
create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
create mode 100755 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
create mode 100644 Silicon/NXP/LS2088A/LS2088A.dec
create mode 100644 Silicon/NXP/LS2088A/LS2088A.dsc.inc
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
new file mode 100644
index 0000000..93d2e5a
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
@@ -0,0 +1,29 @@
+# LS2088aRdbPkg.dec
+# LS2088a board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ PACKAGE_NAME = LS2088aRdbPkg
+ PACKAGE_GUID = 474e0c59-5f77-4060-82dd-9025ee4f4939
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
new file mode 100755
index 0000000..465c59e
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -0,0 +1,96 @@
+# LS2088aRdbPkg.dsc
+#
+# LS2088ARDB Board package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_NAME = LS2088aRdbPkg
+ PLATFORM_GUID = be06d8bc-05eb-44d6-b39f-191e93617ebd
+ OUTPUT_DIRECTORY = Build/LS2088aRdbPkg
+ FLASH_DEFINITION = Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+ DEFINE MC_HIGH_MEM = TRUE
+
+!include Platform/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS2088A/LS2088A.dsc.inc
+
+[LibraryClasses.common]
+ SocLib|Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
+ ArmPlatformLib|Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+ IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
+ RealTimeClockLib|Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
+
+[PcdsFixedAtBuild.common]
+
+!if $(MC_HIGH_MEM) == TRUE # Management Complex loaded at the end of DDR2
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000 # Actual base address (0x0080000000)
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000 # 2 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x80000000 # 2GB (PcdDpaa2McRamSize must be 512MB aligned)
+ gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|1
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0080000000 # Actual base
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x0080000000 # 2G
+!else
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x00A0000000 # Actual base address (0x0080000000) + 512MB
+ gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0060000000 # 2GB - 512MB
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x20000000 # 512MB (Fixed)
+ gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|0
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00A0000000 # Actual base + 512MB
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x0060000000 # 2G - 512MB
+!endif
+ gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x380000000 # 14 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x8080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x8800000000 # 512 GB
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
+ #
+ # Board Specific Pcds
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0600
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x2
+ gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|133333333
+
+ #
+ # RTC Pcds
+ #
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
+ gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
+ gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed|TRUE
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress|0x75
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset|0x09
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0x09
+ gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0x08
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # Architectural Protocols
+ #
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+ Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+ Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
new file mode 100644
index 0000000..b526be1
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
@@ -0,0 +1,200 @@
+# LS2088aRdbPkg.fdf
+#
+# FLASH layout file for LS2088a board.
+#
+# Copyright (c) 2016, Freescale Ltd. All rights reserved.
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LS2088aRdb_EFI]
+BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
+Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0x00100000
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x00100000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+!include Platform/NXP/FVRules.fdf.inc
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize = 0x1
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+
+ INF Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+
+ INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ #
+ # Network modules
+ #
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+ INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+ INF NetworkPkg/TcpDxe/TcpDxe.inf
+ INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+ INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+ INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+ INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+!else
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+!endif
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/FatPei/FatPei.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
diff --git a/Silicon/NXP/LS2088A/LS2088A.dec b/Silicon/NXP/LS2088A/LS2088A.dec
new file mode 100644
index 0000000..8539c63
--- /dev/null
+++ b/Silicon/NXP/LS2088A/LS2088A.dec
@@ -0,0 +1,22 @@
+# LS2088A.dec
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+
+[Guids.common]
+ gNxpLs2088ATokenSpaceGuid = {0xaf770da7, 0x264c, 0x4857, {0x9d, 0xed, 0x56, 0x5e, 0x2c, 0x08, 0x7e, 0x26}}
+
+[Includes]
+ Include
diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc.inc b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
new file mode 100644
index 0000000..8f7dbb5
--- /dev/null
+++ b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
@@ -0,0 +1,71 @@
+# LS2088A.dsc
+# LS2088A Soc package.
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsDynamicDefault.common]
+
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x6000000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x6100000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x00
+
+[PcdsFixedAtBuild.common]
+
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0C000000
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|266666666 #266MHz
+
+ #
+ # ARM L2x0 PCDs
+ gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x10900000
+
+ #
+ # CCSR Address Space and other attached Memories
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x1370000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x30000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x10000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x510000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0xF0000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x3EEA
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x10000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x400000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x10000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x2000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000 # 32 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x2800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 # 32 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x3000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 # 32 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x3800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x800000000 # 32 GB
+ gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x8080000000 # Extended System Memory Base
+ gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0380000000 # 14GB Extended System Memory Size
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x3100000
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x10000
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x1E00000
+ gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x02140000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02000000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
+
+##
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index 159ea65..da148b7 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -91,6 +91,18 @@
gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
#
+ # DPAA2 PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x0|UINT64|0x000001E0
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalBaseAddr|0x0|UINT64|0x000001E1
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalSize|0x0|UINT64|0x000001E2
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsBaseAddr|0x0|UINT64|0x000001E3
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsSize|0x0|UINT64|0x000001E4
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsBaseAddr|0x0|UINT64|0x000001E5
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalSize|0x0|UINT64|0x000001E6
+ gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsCacheSize|0x0|UINT64|0x000001E7
+
+ #
# NV Pcd
#
gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
@@ -102,6 +114,7 @@
gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE|BOOLEAN|0x00000252
+ gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|FALSE|BOOLEAN|0x00000253
#
# Clock PCDs
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 30/41] Platform/NXP: LS2088A RDB Board Library
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (28 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 29/41] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 10:20 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 31/41] Platform/NXP: LS2088 RDB Board FPGA library Meenakshi Aggarwal
` (12 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Wasim Khan <wasim.khan@nxp.com>
Library to provide board specific timings for LS2088ARDB
board with interfacing to IFC controller for accessing
NOR, NAND and FPGA.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
.../NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h | 114 +++++++++++++++++++++
.../NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c | 69 +++++++++++++
.../LS2088aRdbPkg/Library/BoardLib/BoardLib.inf | 28 +++++
3 files changed, 211 insertions(+)
create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h b/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
new file mode 100644
index 0000000..174a242
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
@@ -0,0 +1,114 @@
+/** IfcBoardSpecificLib.h
+
+ IFC Flash Board Specific Macros and structure
+
+ Copyright 2017-2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __IFC__BOARD_SPECIFIC_H__
+#define __IFC__BOARD_SPECIFIC_H__
+
+#include <Ifc.h>
+
+// On board flash support
+#define IFC_NAND_BUF_BASE 0x530000000ULL
+
+// On board Inegrated flash Controller chip select configuration
+#define IFC_NOR_CS IFC_CS0
+#define IFC_NAND_CS IFC_CS2
+#define IFC_FPGA_CS IFC_CS3
+
+
+/* board-specific NAND timing */
+#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x0e) | \
+ IFC_FTIM0_NAND_TWP(0x30) | \
+ IFC_FTIM0_NAND_TWCHT(0x0e) | \
+ IFC_FTIM0_NAND_TWH(0x14))
+
+#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x64) | \
+ IFC_FTIM1_NAND_TWBE(0xab) | \
+ IFC_FTIM1_NAND_TRR(0x1c) | \
+ IFC_FTIM1_NAND_TRP(0x30))
+
+#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0x1e) | \
+ IFC_FTIM2_NAND_TREH(0x14) | \
+ IFC_FTIM2_NAND_TWHRE(0x3c))
+
+#define NAND_FTIM3 0x0
+
+#define IFC_NAND_BASE_PHYS 0x30000000
+#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BASE_PHYS) \
+ | IFC_CSPR_PORT_SIZE_8 \
+ | IFC_CSPR_MSEL_NAND \
+ | IFC_CSPR_V)
+
+#define NAND_CSPR_EXT 0x0
+#define NAND_AMASK 0xFFFF0000
+
+#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | IFC_CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | IFC_CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
+ | IFC_CSOR_NAND_PGS_4K /* Page Size = 4K */ \
+ | IFC_CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
+ | IFC_CSOR_NAND_PB(7)) /* 2^7 Pages Per Block */
+
+// board-specific NOR timing
+#define NOR_FTIM0 (IFC_FTIM0_NOR_TACSE(0x4) | \
+ IFC_FTIM0_NOR_TEADC(0x5) | \
+ IFC_FTIM0_NOR_TEAHC(0x5))
+
+#define NOR_FTIM1 (IFC_FTIM1_NOR_TACO(0x35) | \
+ IFC_FTIM1_NOR_TRAD_NOR(0x1a) | \
+ IFC_FTIM1_NOR_TSEQRAD_NOR(0x13))
+
+#define NOR_FTIM2 (IFC_FTIM2_NOR_TCS(0x4) | \
+ IFC_FTIM2_NOR_TCH(0x4) | \
+ IFC_FTIM2_NOR_TWPH(0xe) | \
+ IFC_FTIM2_NOR_TWP(0x1c))
+
+#define NOR_FTIM3 0x04000000
+
+#define IFC_FLASH_BASE_PHYS 0x80000000
+#define NOR_CSPR (IFC_CSPR_PHYS_ADDR(IFC_FLASH_BASE_PHYS) \
+ | IFC_CSPR_PORT_SIZE_16 \
+ | IFC_CSPR_MSEL_NOR \
+ | IFC_CSPR_V)
+
+#define NOR_CSPR_EXT 0x0
+#define NOR_AMASK IFC_AMASK(128*1024*1024)
+#define NOR_CSOR IFC_CSOR_NOR_ADM_SHIFT(12)
+
+// board-specific fpga timing
+#define FPGA_BASE_PHYS 0x20000000
+#define FPGA_CSPR_EXT 0x0
+#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
+ IFC_CSPR_PORT_SIZE_8 | \
+ IFC_CSPR_MSEL_GPCM | \
+ IFC_CSPR_V)
+
+#define FPGA_AMASK IFC_AMASK(64 * 1024)
+#define FPGA_CSOR IFC_CSOR_NOR_ADM_SHIFT(12)
+
+#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0xe) | \
+ IFC_FTIM0_GPCM_TEADC(0xe) | \
+ IFC_FTIM0_GPCM_TEAHC(0xe))
+
+#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \
+ IFC_FTIM1_GPCM_TRAD(0x3f))
+
+#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \
+ IFC_FTIM2_GPCM_TCH(0xf) | \
+ IFC_FTIM2_GPCM_TWP(0x3e))
+
+#define FPGA_FTIM3 0x0
+
+#endif //__IFC__BOARD_SPECIFIC_H__
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
new file mode 100644
index 0000000..936b789
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
@@ -0,0 +1,69 @@
+/** @file
+
+ Copyright 2017-2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <IfcBoardSpecific.h>
+
+VOID
+GetIfcNorFlashTimings (
+ IN IFC_TIMINGS * NorIfcTimings
+ )
+{
+ NorIfcTimings->Ftim[0] = NOR_FTIM0;
+ NorIfcTimings->Ftim[1] = NOR_FTIM1;
+ NorIfcTimings->Ftim[2] = NOR_FTIM2;
+ NorIfcTimings->Ftim[3] = NOR_FTIM3;
+ NorIfcTimings->Cspr = NOR_CSPR;
+ NorIfcTimings->CsprExt = NOR_CSPR_EXT;
+ NorIfcTimings->Amask = NOR_AMASK;
+ NorIfcTimings->Csor = NOR_CSOR;
+ NorIfcTimings->CS = IFC_NOR_CS;
+
+ return ;
+}
+
+VOID
+GetIfcFpgaTimings (
+ IN IFC_TIMINGS *FpgaIfcTimings
+ )
+{
+ FpgaIfcTimings->Ftim[0] = FPGA_FTIM0;
+ FpgaIfcTimings->Ftim[1] = FPGA_FTIM1;
+ FpgaIfcTimings->Ftim[2] = FPGA_FTIM2;
+ FpgaIfcTimings->Ftim[3] = FPGA_FTIM3;
+ FpgaIfcTimings->Cspr = FPGA_CSPR;
+ FpgaIfcTimings->CsprExt = FPGA_CSPR_EXT;
+ FpgaIfcTimings->Amask = FPGA_AMASK;
+ FpgaIfcTimings->Csor = FPGA_CSOR;
+ FpgaIfcTimings->CS = IFC_FPGA_CS;
+
+ return;
+}
+
+VOID
+GetIfcNandFlashTimings (
+ IN IFC_TIMINGS * NandIfcTimings
+ )
+{
+ NandIfcTimings->Ftim[0] = NAND_FTIM0;
+ NandIfcTimings->Ftim[1] = NAND_FTIM1;
+ NandIfcTimings->Ftim[2] = NAND_FTIM2;
+ NandIfcTimings->Ftim[3] = NAND_FTIM3;
+ NandIfcTimings->Cspr = NAND_CSPR;
+ NandIfcTimings->CsprExt = NAND_CSPR_EXT;
+ NandIfcTimings->Amask = NAND_AMASK;
+ NandIfcTimings->Csor = NAND_CSOR;
+ NandIfcTimings->CS = IFC_NAND_CS;
+
+ return;
+}
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
new file mode 100644
index 0000000..5df84b1
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
@@ -0,0 +1,28 @@
+# @file
+#
+# Copyright 2017-2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = BoardLib
+ FILE_GUID = 13eacf2a-4338-48f4-88de-6ce4618e1a53
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardLib
+
+[Sources.common]
+ BoardLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 31/41] Platform/NXP: LS2088 RDB Board FPGA library
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (29 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 30/41] Platform/NXP: LS2088A RDB Board Library Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 10:22 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 32/41] LS2088 : Enable support of FpgaLib Meenakshi Aggarwal
` (11 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Wasim Khan <wasim.khan@nxp.com>
Library to provide functions for accessing FPGA
on LS2088ARDB board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
---
.../NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h | 166 +++++++++++++++++++++
.../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c | 115 ++++++++++++++
.../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 ++++
3 files changed, 312 insertions(+)
create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h b/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
new file mode 100644
index 0000000..84d1f02
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
@@ -0,0 +1,166 @@
+/** FpgaLib.h
+* Header defining the LS2088a Fpga specific constants (Base addresses, sizes, flags)
+*
+* Copyright 2017-2018 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __LS2088A_FPGA_H__
+#define __LS2088A_FPGA_H__
+
+typedef enum {
+ CLK_66,
+ CLK_83,
+ CLK_100,
+ CLK_125,
+ CLK_133
+} SYSTEM_CLOCK;
+
+/*
+ * FPGA register set of LS2088ARDB board-specific.
+ */
+typedef struct {
+ UINT8 Id; // ID value uniquely identifying each QorIQ board type
+ UINT8 Arch; // Board Version
+ UINT8 Ver; // FPGA Version
+ UINT8 Model; // Programming Model
+ UINT8 Minor; // Minor Revision Number
+ UINT8 CtlSys;
+ UINT8 Aux;
+ UINT8 ClkSpd;
+ UINT8 StatDut;
+ UINT8 StatSys;
+ UINT8 StatAlrm;
+ UINT8 Present;
+ UINT8 Present2;
+ UINT8 RcwCtl;
+ UINT8 CtlLed;
+ UINT8 I2cBlk;
+ UINT8 RcfgCtl;
+ UINT8 RcfgSt;
+ UINT8 DcmAd;
+ UINT8 DcmDa;
+ UINT8 Dcmd;
+ UINT8 Dmsg;
+ UINT8 Gdc;
+ UINT8 Gdd;
+ UINT8 Dmack;
+ UINT8 Res1[6];
+ UINT8 Watch;
+ UINT8 PwrCtl[2];
+ UINT8 Res2[2];
+ UINT8 PwrStat[4];
+ UINT8 Res3[8];
+ UINT8 ClkSpd2[2];
+ UINT8 Res4[2];
+ UINT8 Sclk[3];
+ UINT8 Res5;
+ UINT8 Dclk[3];
+ UINT8 Res6;
+ UINT8 ClkDspd[3];
+ UINT8 Res7;
+ UINT8 RstCtl;
+ UINT8 RstStat;
+ UINT8 RstRsn;
+ UINT8 RstFrc[2];
+ UINT8 Res8[11];
+ UINT8 BrdCfg[16];
+ UINT8 DutCfg[16];
+ UINT8 RcwAd[2];
+ UINT8 RcwData;
+ UINT8 Res9[5];
+ UINT8 PostCtl;
+ UINT8 PostStat;
+ UINT8 PostDat[2];
+ UINT8 Pid[4];
+ UINT8 GpioIo[4];
+ UINT8 GpioDir[4];
+ UINT8 Res10[20];
+ UINT8 RjtagCtl;
+ UINT8 RjtagDat;
+ UINT8 Res11[2];
+ UINT8 TrigSrc[4];
+ UINT8 TrigDst[4];
+ UINT8 TrigStat;
+ UINT8 Res12[3];
+ UINT8 TrigCtr[4];
+ UINT8 Res13[16];
+ UINT8 ClkFreq[6];
+ UINT8 ResC6[8];
+ UINT8 ClkBase[2];
+ UINT8 ResD0[8];
+ UINT8 Cms[2];
+ UINT8 ResC0[6];
+ UINT8 Aux2[4];
+ UINT8 Res14[10];
+ UINT8 AuxAd;
+ UINT8 AuxDa;
+ UINT8 Res15[16];
+} FPGA_REG_SET;
+
+/**
+ Function to read FPGA register.
+**/
+UINT8
+FpgaRead (
+ UINTN Reg
+ );
+
+/**
+ Function to write FPGA register.
+**/
+VOID
+FpgaWrite (
+ UINTN Reg,
+ UINT8 Value
+ );
+
+/**
+ Function to initialize FPGA timings.
+**/
+VOID
+FpgaInit (
+ VOID
+ );
+
+/**
+ Function to get system clock frequency.
+**/
+UINTN
+GetBoardSysClk (
+ VOID
+ );
+
+/**
+ Function to print board personality.
+**/
+VOID
+PrintBoardPersonality (
+ VOID
+ );
+
+#define FPGA_BASE_PHYS 0x520000000
+
+//SYSCLK
+#define FPGA_CLK_MASK 0x0F // FPGA Clock Mask
+#define SYSCLK_66_MHZ 66000000
+#define SYSCLK_83_MHZ 83000000
+#define SYSCLK_100_MHZ 100000000
+#define SYSCLK_125_MHZ 125000000
+#define SYSCLK_133_MHZ 133000000
+
+#define FPGA_VBANK_MASK 0x07
+#define FPGA_CS_MASK 0x08
+
+#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg))
+#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), Value)
+
+#endif // __LS2088A_FPGA_H__
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
new file mode 100644
index 0000000..8948c21
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
@@ -0,0 +1,115 @@
+/** @FpgaLib.c
+ Fpga Library for LS2088A-RDB board, containing functions to
+ program and read the Fpga registers.
+
+ FPGA is connected to IFC Controller and so MMIO APIs are used
+ to read/write FPGA registers
+
+ Copyright 2017-2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/FpgaLib.h>
+#include <Library/IoLib.h>
+
+/**
+ Function to read FPGA register.
+
+ @param Reg Register offset of FPGA to read.
+
+**/
+UINT8
+FpgaRead (
+ IN UINTN Reg
+ )
+{
+ VOID *Base;
+
+ Base = (VOID *)FPGA_BASE_PHYS;
+
+ return MmioRead8 ((UINTN)(Base + Reg));
+}
+
+/**
+ Function to write FPGA register.
+
+ @param Reg Register offset of FPGA to write.
+ @param Value Value to be written.
+
+**/
+VOID
+FpgaWrite (
+ IN UINTN Reg,
+ IN UINT8 Value
+ )
+{
+ VOID *Base;
+
+ Base = (VOID *)FPGA_BASE_PHYS;
+
+ MmioWrite8 ((UINTN)(Base + Reg), Value);
+}
+
+/**
+ Function to get board system clock frequency.
+
+**/
+UINTN
+GetBoardSysClk (
+ VOID
+ )
+{
+ UINT8 SysclkConf;
+ SysclkConf = FPGA_READ (BrdCfg[1]);
+ switch (SysclkConf & FPGA_CLK_MASK) {
+ case CLK_66:
+ return SYSCLK_66_MHZ;
+ case CLK_83:
+ return SYSCLK_83_MHZ;
+ case CLK_100:
+ return SYSCLK_100_MHZ;
+ case CLK_125:
+ return SYSCLK_125_MHZ;
+ case CLK_133:
+ return SYSCLK_133_MHZ;
+ }
+ return SYSCLK_100_MHZ;
+}
+
+/**
+ Function to print board personality.
+
+**/
+VOID
+PrintBoardPersonality (
+ VOID
+ )
+{
+ UINT8 SwitchConf;
+ SwitchConf = FPGA_READ (Arch);
+
+ DEBUG ((DEBUG_INFO, "Board Arch: V%d, ", SwitchConf >> 4));
+ DEBUG ((DEBUG_INFO, "Board version: %c, boot from ",
+ (SwitchConf & 0xf) + 'A'));
+
+ SwitchConf = FPGA_READ (BrdCfg[0]);
+
+ if (SwitchConf & FPGA_CS_MASK)
+ DEBUG ((DEBUG_INFO, "NAND\n"));
+ else
+ DEBUG ((DEBUG_INFO, "vBank: %d\n", (SwitchConf & FPGA_VBANK_MASK)));
+
+ DEBUG ((DEBUG_INFO, "FPGA: v%d.%d\n", FPGA_READ (Ver),
+ FPGA_READ (Minor)));
+}
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
new file mode 100644
index 0000000..e70723a
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
@@ -0,0 +1,31 @@
+# @FpgaLib.inf
+#
+# Copyright 2017-2018 NXP
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x0001000A
+ BASE_NAME = FpgaLib
+ FILE_GUID = dd2ce2f3-f219-4b57-82fd-f1ff8ae8bf5a
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = FpgaLib
+
+[Sources.common]
+ FpgaLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ IoLib
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 32/41] LS2088 : Enable support of FpgaLib
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (30 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 31/41] Platform/NXP: LS2088 RDB Board FPGA library Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 10:23 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 33/41] LS2088ARDB: Enable NOR driver and Runtime Services Meenakshi Aggarwal
` (10 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 3 +++
Silicon/NXP/Include/Chassis3/Soc.h | 1 -
Silicon/NXP/LS2088A/LS2088A.dsc.inc | 1 +
Silicon/NXP/Library/SocLib/Chassis3/Soc.c | 13 ++++++++++++-
Silicon/NXP/Library/SocLib/LS2088aSocLib.inf | 2 ++
5 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
index 465c59e..76d51a2 100755
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -39,6 +39,9 @@
SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
RealTimeClockLib|Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
+ IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
+ BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
+ FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
[PcdsFixedAtBuild.common]
diff --git a/Silicon/NXP/Include/Chassis3/Soc.h b/Silicon/NXP/Include/Chassis3/Soc.h
index 8d967e7..0dd9eee 100644
--- a/Silicon/NXP/Include/Chassis3/Soc.h
+++ b/Silicon/NXP/Include/Chassis3/Soc.h
@@ -22,7 +22,6 @@
#define FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } /* LS208x */
#define TP_CLUSTER_EOC_MASK 0x80000000 /* Mask for End of clusters */
#define NUM_CC_PLLS 6
-#define CLK_FREQ 100000000
#define MAX_CPUS 16
#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) != TP_CLUSTER_EOC_MASK)
diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc.inc b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
index 8f7dbb5..2cff40f 100644
--- a/Silicon/NXP/LS2088A/LS2088A.dsc.inc
+++ b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
@@ -67,5 +67,6 @@
gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02000000
gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000
##
diff --git a/Silicon/NXP/Library/SocLib/Chassis3/Soc.c b/Silicon/NXP/Library/SocLib/Chassis3/Soc.c
index 0fc92f4..d334bb7 100644
--- a/Silicon/NXP/Library/SocLib/Chassis3/Soc.c
+++ b/Silicon/NXP/Library/SocLib/Chassis3/Soc.c
@@ -19,11 +19,15 @@
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
+#include <Library/IfcLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
+extern VOID PrintBoardPersonality (VOID);
+extern UINTN GetBoardSysClk (VOID);
+
VOID
GetSysInfo (
OUT SYS_INFO *PtrSysInfo
@@ -82,7 +86,7 @@ GetSysInfo (
GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
- SysClk = CLK_FREQ;
+ SysClk = GetBoardSysClk ();
PtrSysInfo->FreqSystemBus = SysClk;
PtrSysInfo->FreqDdrBus = PcdGet64 (PcdDdrClk);
@@ -151,6 +155,8 @@ SocInit (
//
SmmuInit ();
+ IfcInit ();
+
//
// Initialize the Serial Port.
// Early serial port initialization is required to print RCW,
@@ -177,4 +183,9 @@ SocInit (
// Print Soc Personality information
//
PrintSoc ();
+
+ //
+ // Print Board Personality information
+ //
+ PrintBoardPersonality ();
}
diff --git a/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf b/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
index 3d9237d..9547f5a 100644
--- a/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
+++ b/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
@@ -29,6 +29,8 @@
[LibraryClasses]
BaseLib
DebugLib
+ FpgaLib
+ IfcLib
IoAccessLib
SerialPortLib
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 33/41] LS2088ARDB: Enable NOR driver and Runtime Services
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (31 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 32/41] LS2088 : Enable support of FpgaLib Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 10:24 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 34/41] Silicon/NXP: Implement PciSegmentLib to support multiple RCs Meenakshi Aggarwal
` (9 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Enable NOR driver and Runtime Services for LS2088ARDB Platform
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 15 ++++-
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 6 +-
Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc | 99 ++++++++++++++++++++++++++++
3 files changed, 118 insertions(+), 2 deletions(-)
create mode 100644 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
index 76d51a2..e788581 100755
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -42,6 +42,7 @@
IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
+ NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
[PcdsFixedAtBuild.common]
@@ -84,6 +85,13 @@
gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0x09
gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0x08
+ #
+ # NV Storage PCDs
+ #
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x580000000
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x580300000
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
@@ -93,7 +101,12 @@
#
# Architectural Protocols
#
- MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf{
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ }
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+ Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
index b526be1..61bb160 100644
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
@@ -55,6 +55,7 @@ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
!include Platform/NXP/FVRules.fdf.inc
+!include VarStore.fdf.inc
################################################################################
#
# FV Section
@@ -103,7 +104,8 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
- INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
INF Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -124,6 +126,8 @@ READ_LOCK_STATUS = TRUE
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+ INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
+
#
# Network modules
#
diff --git a/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
new file mode 100644
index 0000000..7d35042
--- /dev/null
+++ b/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
@@ -0,0 +1,99 @@
+## @file
+# FDF include file with FD definition that defines an empty variable store.
+#
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
+# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
+# Copyright 2017-2018 NXP.
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+##
+
+[FD.LS2088aRdbNv_EFI]
+
+BaseAddress = 0x580300000|gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase #The base address of the FLASH device
+Size = 0x000C0000|gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize #The size in bytes of the FLASH device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xC0000
+
+#
+# Place NV Storage just above Platform Data Base
+#
+DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
+DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
+DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
+DEFINE FTW_WORKING_SIZE = 0x00040000
+DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
+DEFINE FTW_SPARE_SIZE = 0x00040000
+
+#############################################################################
+# LS2088ARDB NVRAM Area
+# LS2088ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
+#############################################################################
+
+
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER
+ # ZeroVector []
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =
+ # { 0xFFF12B8D, 0x7696, 0x4C8B,
+ # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+ # FvLength: 0xC0000
+ 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
+ # Signature "_FVH" # Attributes
+ 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
+ # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
+ 0x48, 0x00, 0xFA, 0xF5, 0x00, 0x00, 0x00, 0x02,
+ # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
+ 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+ # Blockmap[1]: End
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ ## This is the VARIABLE_STORE_HEADER
+ # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
+ # Signature: gEfiAuthenticatedVariableGuid =
+ # { 0xaaf32c78, 0x947b, 0x439a,
+ # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+ # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
+ # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
+ # This can speed up the Variable Dispatch a bit.
+ 0xB8, 0xFF, 0x03, 0x00,
+ # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+ 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
+ # WriteQueueSize: UINT64
+ 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+#NV_FTW_SPARE
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 34/41] Silicon/NXP: Implement PciSegmentLib to support multiple RCs
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (32 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 33/41] LS2088ARDB: Enable NOR driver and Runtime Services Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 10:44 ` Ard Biesheuvel
2018-12-21 14:01 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 35/41] Silicon/NXP: Implement PciHostBridgeLib support Meenakshi Aggarwal
` (8 subsequent siblings)
42 siblings, 2 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
Multiple root complex support is not provided by standard library
PciLib/PciExpressLib/PciSegmentLib, Reimplementing it and provide
function for reading/writing into PCIe configuration Space.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Include/NxpPcie.h | 146 +++++
Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 611 +++++++++++++++++++++
.../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 41 ++
3 files changed, 798 insertions(+)
create mode 100644 Silicon/NXP/Include/NxpPcie.h
create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
diff --git a/Silicon/NXP/Include/NxpPcie.h b/Silicon/NXP/Include/NxpPcie.h
new file mode 100644
index 0000000..a0beefe
--- /dev/null
+++ b/Silicon/NXP/Include/NxpPcie.h
@@ -0,0 +1,146 @@
+/** @file
+ PCI memory configuration for NXP
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __NXP_PCIE_H__
+#define __NXP_PCIE_H__
+
+// Segment 0
+#define PCI_SEG0_NUM 0
+#define PCI_SEG0_MMIO32_MIN 0x40000000
+#define PCI_SEG0_MMIO32_MAX 0x4fffffff
+#define PCI_SEG0_MMIO64_MIN PCI_SEG0_MMIO_MEMBASE + \
+ SEG_MEM_SIZE + \
+ MEM64_BASE
+#define PCI_SEG0_MMIO64_MAX PCI_SEG0_MMIO64_MIN + MEM64_LIMIT
+#define PCI_SEG0_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp1BaseAddr)
+#define PCI_SEG0_DBI_BASE 0x03400000
+#define PCI_SEG0_MMIO_OFFSET 0x0
+#define PCI_SEG0_PORTIO_MEMBASE PCI_SEG0_MMIO_MEMBASE + SEG_IO_SIZE
+#define PCI_SEG0_PORTIO_OFFSET 0x0
+
+// Segment 1
+#define PCI_SEG1_NUM 1
+#define PCI_SEG1_MMIO32_MIN 0x40000000
+#define PCI_SEG1_MMIO32_MAX 0x4fffffff
+#define PCI_SEG1_MMIO64_MIN PCI_SEG1_MMIO_MEMBASE + \
+ SEG_MEM_SIZE + \
+ MEM64_BASE
+#define PCI_SEG1_MMIO64_MAX PCI_SEG1_MMIO64_MIN + MEM64_LIMIT
+#define PCI_SEG1_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp2BaseAddr)
+#define PCI_SEG1_DBI_BASE 0x03500000
+#define PCI_SEG1_MMIO_OFFSET 0x10000000
+#define PCI_SEG1_PORTIO_MEMBASE PCI_SEG1_MMIO_MEMBASE + SEG_IO_SIZE
+#define PCI_SEG1_PORTIO_OFFSET 0x10000
+
+// Segment 2
+#define PCI_SEG2_NUM 2
+#define PCI_SEG2_MMIO32_MIN 0x40000000
+#define PCI_SEG2_MMIO32_MAX 0x4fffffff
+#define PCI_SEG2_MMIO64_MIN PCI_SEG2_MMIO_MEMBASE + \
+ SEG_MEM_SIZE + \
+ MEM64_BASE
+#define PCI_SEG2_MMIO64_MAX PCI_SEG2_MMIO64_MIN + MEM64_LIMIT
+#define PCI_SEG2_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp3BaseAddr)
+#define PCI_SEG2_DBI_BASE 0x03600000
+#define PCI_SEG2_MMIO_OFFSET 0x20000000
+#define PCI_SEG2_PORTIO_MEMBASE PCI_SEG2_MMIO_MEMBASE + SEG_IO_SIZE
+#define PCI_SEG2_PORTIO_OFFSET 0x20000
+
+// Segment 3
+#define PCI_SEG3_NUM 3
+#define PCI_SEG3_MMIO32_MIN 0x40000000
+#define PCI_SEG3_MMIO32_MAX 0x4fffffff
+#define PCI_SEG3_MMIO64_MIN PCI_SEG3_MMIO_MEMBASE + \
+ SEG_MEM_SIZE + \
+ MEM64_BASE
+#define PCI_SEG3_MMIO64_MAX PCI_SEG3_MMIO64_MIN + MEM64_LIMIT
+#define PCI_SEG3_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp4BaseAddr)
+#define PCI_SEG3_DBI_BASE 0x03700000
+#define PCI_SEG3_MMIO_OFFSET 0x30000000
+#define PCI_SEG3_PORTIO_MEMBASE PCI_SEG3_MMIO_MEMBASE + SEG_IO_SIZE
+#define PCI_SEG3_PORTIO_OFFSET 0x30000
+
+// Segment configuration
+#define PCI_SEG_BUSNUM_MIN 0x0
+#define PCI_SEG_BUSNUM_MAX 0xff
+#define PCI_SEG_PORTIO_MIN 0x0
+#define PCI_SEG_PORTIO_MAX 0xffff
+#define PCI_SEG_MMIO32_MIN 0x40000000
+#define PCI_SEG_MMIO32_MAX 0x4fffffff
+#define PCI_SEG_MMIO32_DIFF 0x10000000
+#define PCI_SEG_MMIO64_MAX_DIFF 0x3fffffff
+#define SEG_CFG_SIZE 0x00001000
+#define SEG_CFG_BUS 0x00000000
+#define SEG_MEM_SIZE 0x40000000
+#define SEG_MEM_LIMIT 0x7fffffff
+#define SEG_MEM_BUS 0x40000000
+#define SEG_IO_SIZE 0x00010000
+#define SEG_IO_BUS 0x00000000
+#define PCI_SEG_PORTIO_LIMIT (NUM_PCIE_CONTROLLER * SEG_IO_SIZE) + \
+ PCI_SEG_PORTIO_MAX
+#define PCI_BASE_DIFF 0x800000000
+#define PCI_DBI_SIZE_DIFF 0x100000
+#define PCI_SEG0_PHY_CFG0_BASE PCI_SEG0_MMIO_MEMBASE
+#define PCI_SEG0_PHY_CFG1_BASE PCI_SEG0_PHY_CFG0_BASE + SEG_CFG_SIZE
+#define PCI_SEG0_PHY_MEM_BASE PCI_SEG0_MMIO64_MIN - MEM64_BASE
+#define PCI_SEG0_PHY_MEM64_BASE PCI_SEG0_MMIO64_MIN
+#define PCI_SEG0_PHY_IO_BASE PCI_SEG0_MMIO_MEMBASE + SEG_IO_SIZE
+#define MEM64_BASE 0xC0000000 // MMIO64 starts at 4GB offset
+#define MEM64_LIMIT 0x1FFFFFFFF
+#define SEG_MEM64_BASE 0x100000000
+
+// iATU configuration
+#define IATU_VIEWPORT_OFF 0x900
+#define IATU_VIEWPORT_OUTBOUND 0
+
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4
+#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
+
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
+#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31
+
+#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
+#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
+#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914
+#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918
+#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C
+
+#define IATU_REGION_INDEX0 0x0
+#define IATU_REGION_INDEX1 0x1
+#define IATU_REGION_INDEX2 0x2
+#define IATU_REGION_INDEX3 0x3
+#define IATU_REGION_INDEX4 0x4
+
+// PCIe Controller configuration
+#define NUM_PCIE_CONTROLLER FixedPcdGet32 (PcdNumPciController)
+#define PCI_LUT_DBG FixedPcdGet32 (PcdPcieLutDbg)
+#define PCI_LUT_BASE FixedPcdGet32 (PcdPcieLutBase)
+#define LTSSM_STATE_MASK 0x3f
+#define LTSSM_PCIE_L0 0x11
+#define PCI_LINK_CAP 0x7c
+#define PCI_LINK_SPEED_MASK 0xf
+#define PCI_CLASS_BRIDGE_PCI 0x6040010
+#define PCI_CLASS_DEVICE 0x8
+#define PCI_DBI_RO_WR_EN 0x8bc
+#define PCI_BASE_ADDRESS_0 0x10
+
+VOID GetSerdesProtocolMaps (UINT64 *);
+
+BOOLEAN IsSerDesLaneProtocolConfigured (UINT64, UINT16);
+
+#endif
diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
new file mode 100644
index 0000000..3a3e24a
--- /dev/null
+++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
@@ -0,0 +1,611 @@
+/** @file
+ PCI Segment Library for NXP SoCs with multiple RCs
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials are
+ licensed and made available under the terms and conditions of
+ the BSD License which accompanies this distribution. The full
+ text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <NxpPcie.h>
+
+typedef enum {
+ PciCfgWidthUint8 = 0,
+ PciCfgWidthUint16,
+ PciCfgWidthUint32,
+ PciCfgWidthMax
+} PCI_CFG_WIDTH;
+
+/**
+ Assert the validity of a PCI Segment address.
+ A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
+
+ @param A The address to validate.
+ @param M Additional bits to assert to be zero.
+
+**/
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
+ ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
+
+/**
+ Function to return PCIe Physical Address(PCIe view) or Controller
+ Address(CPU view) for different RCs
+
+ @param Address Address passed from bus layer.
+
+ @return Return PCIe CPU or Controller address.
+
+**/
+STATIC
+UINT64
+PciSegmentLibGetConfigBase (
+ IN UINT64 Address
+ )
+{
+
+ UINT16 Segment;
+
+ //
+ // Reading Segment number(47-32 bits) in Address
+ //
+ Segment = (Address >> 32);
+
+ switch (Segment) {
+ // Root Complex 1
+ case PCI_SEG0_NUM:
+ // Reading bus number(bits 20-27)
+ if ((Address >> 20) & 1) {
+ return PCI_SEG0_MMIO_MEMBASE;
+ } else {
+ // On Bus 0 RCs are connected
+ return PCI_SEG0_DBI_BASE;
+ }
+ // Root Complex 2
+ case PCI_SEG1_NUM:
+ // Reading bus number(bits 20-27)
+ if ((Address >> 20) & 1) {
+ return PCI_SEG1_MMIO_MEMBASE;
+ } else {
+ // On Bus 0 RCs are connected
+ return PCI_SEG1_DBI_BASE;
+ }
+ // Root Complex 3
+ case PCI_SEG2_NUM:
+ // Reading bus number(bits 20-27)
+ if ((Address >> 20) & 1) {
+ return PCI_SEG2_MMIO_MEMBASE;
+ } else {
+ // On Bus 0 RCs are connected
+ return PCI_SEG2_DBI_BASE;
+ }
+ // Root Complex 4
+ case PCI_SEG3_NUM:
+ // Reading bus number(bits 20-27)
+ if ((Address >> 20) & 1) {
+ return PCI_SEG3_MMIO_MEMBASE;
+ } else {
+ // On Bus 0 RCs are connected
+ return PCI_SEG3_DBI_BASE;
+ }
+ default:
+ return 0;
+ }
+
+}
+
+/**
+ Internal worker function to ignore device
+
+ @param Address The address that encodes BDF
+
+ @return TRUE to ignore the devices
+
+**/
+STATIC
+BOOLEAN
+IgnoreDevices (
+ IN UINT64 Address
+ )
+{
+ //
+ // ignore devices > 0 on bus 0
+ //
+ if ((Address & 0xff00000) == 0 && (Address & 0xf8000) != 0) {
+ return TRUE;
+ }
+
+ //
+ // ignore device > 0 on bus 1
+ //
+ if ((Address & 0xfe00000) == 0 && (Address & 0xf8000) != 0) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ Internal worker function to read a PCI configuration register.
+
+ @param Address The address that encodes the Segment, PCI Bus, Device,
+ Function and Register.
+ @param Width The width of data to read
+
+ @return The value read from the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibReadWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width
+ )
+{
+ UINT64 Base;
+ UINT16 Offset;
+
+ //
+ // Reading Function(12-0) bits in Address
+ //
+ Offset = (Address & (SIZE_4KB - 1));
+
+ Base = PciSegmentLibGetConfigBase (Address);
+
+ if (IgnoreDevices (Address)) {
+ return MAX_UINT32;
+ }
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ return MmioRead8 (Base + Offset);
+ case PciCfgWidthUint16:
+ return MmioRead16 (Base + Offset);
+ case PciCfgWidthUint32:
+ return MmioRead32 (Base + Offset);
+ default:
+ ASSERT (FALSE);
+ }
+
+ return CHAR_NULL;
+}
+
+/**
+ Internal worker function to writes a PCI configuration register.
+
+ @param Address The address that encodes the Segment, PCI Bus, Device,
+ Function and Register.
+ @param Width The width of data to write
+ @param Data The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibWriteWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width,
+ IN UINT32 Data
+ )
+{
+ UINT64 Base;
+ UINT32 Offset;
+
+ //
+ // Reading Function(12-0 bits) in Address
+ //
+ Offset = (Address & (SIZE_4KB - 1));
+
+ Base = PciSegmentLibGetConfigBase (Address);
+
+ if (IgnoreDevices (Address)) {
+ return MAX_UINT32;
+ }
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ MmioWrite8 (Base + Offset, Data);
+ break;
+ case PciCfgWidthUint16:
+ MmioWrite16 (Base + Offset, Data);
+ break;
+ case PciCfgWidthUint32:
+ MmioWrite32 (Base + Offset, Data);
+ break;
+ default:
+ ASSERT (FALSE);
+ }
+
+ return Data;
+}
+
+/**
+ Register a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Bus, Device,
+ Function and Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciSegmentRegisterForRuntimeAccess (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+ return RETURN_UNSUPPORTED;
+}
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+
+ @return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+PciSegmentRead8 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
+}
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
+}
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+PciSegmentRead16 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
+}
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the
+ value specified by Value.
+
+ Value is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+PciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
+}
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+PciSegmentRead32 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
+}
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the
+ value specified by Value.
+
+ Value is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+PciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
+}
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param Size The size in bytes of the transfer.
+ @param Buffer The pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+PciSegmentReadBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ // 0xFFF is used as limit for 4KB config space
+ ASSERT (((StartAddress & (SIZE_4KB - 1)) + Size) <= SIZE_4KB);
+
+ if (Size == 0) {
+ return Size;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ //
+ // Read a byte if StartAddress is byte aligned
+ //
+ *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer += sizeof (UINT8);
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ //
+ // Read a word if StartAddress is word aligned
+ //
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer += sizeof (UINT16);
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Read as many double words as possible
+ //
+ WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer += sizeof (UINT32);
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Read the last remaining word if exist
+ //
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer += sizeof (UINT16);
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Read the last remaining byte if exist
+ //
+ *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ }
+
+ return ReturnValue;
+}
+
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param Size The size in bytes of the transfer.
+ @param Buffer The pointer to a buffer containing the data to write.
+
+ @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+PciSegmentWriteBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ // 0xFFF is used as limit for 4KB config space
+ ASSERT (((StartAddress & (SIZE_4KB - 1)) + Size) <= SIZE_4KB);
+
+ if (Size == 0) {
+ return Size;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ //
+ // Write a byte if StartAddress is byte aligned
+ //
+ PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer += sizeof (UINT8);
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ //
+ // Write a word if StartAddress is word aligned
+ //
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer += sizeof (UINT16);
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Write as many double words as possible
+ //
+ PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer += sizeof (UINT32);
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Write the last remaining word if exist
+ //
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer += sizeof (UINT16);
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Write the last remaining byte if exist
+ //
+ PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
+ }
+
+ return ReturnValue;
+}
diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
new file mode 100644
index 0000000..1ac83d4
--- /dev/null
+++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
@@ -0,0 +1,41 @@
+## @file
+# PCI Segment Library for NXP SoCs with multiple RCs
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PciSegmentLib
+ FILE_GUID = c9f59261-5a60-4a4c-82f6-1f520442e100
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciSegmentLib
+
+[Sources]
+ PciSegmentLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 35/41] Silicon/NXP: Implement PciHostBridgeLib support
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (33 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 34/41] Silicon/NXP: Implement PciSegmentLib to support multiple RCs Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 10:51 ` Ard Biesheuvel
2018-12-21 18:30 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 36/41] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL Meenakshi Aggarwal
` (7 subsequent siblings)
42 siblings, 2 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
Implement the library that exposes the PCIe root complexes to the
generic PCI host bridge driver,Putting SoC Specific low level init
code for the RCs.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
---
.../Library/PciHostBridgeLib/PciHostBridgeLib.c | 639 +++++++++++++++++++++
.../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 51 ++
2 files changed, 690 insertions(+)
create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
new file mode 100644
index 0000000..a543d7d
--- /dev/null
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -0,0 +1,639 @@
+/** @file
+ PCI Host Bridge Library instance for NXP SoCs
+
+ Copyright 2018 NXP
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciHostBridgeLib.h>
+#include <NxpPcie.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+#pragma pack(1)
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }
+ },
+ EISA_PNP_ID (0x0A08), // PCI Express
+ PCI_SEG0_NUM
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }
+ },
+ EISA_PNP_ID (0x0A08), // PCI Express
+ PCI_SEG1_NUM
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }
+ },
+ EISA_PNP_ID (0x0A08), // PCI Express
+ PCI_SEG2_NUM
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ },
+ {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
+ }
+ },
+ EISA_PNP_ID (0x0A08), // PCI Express
+ PCI_SEG3_NUM
+ },
+
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+ }
+};
+
+STATIC
+GLOBAL_REMOVE_IF_UNREFERENCED
+CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+ L"Mem", L"I/O", L"Bus"
+};
+
+#define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | \
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE
+
+#define PCI_SUPPORT_ATTRIBUTES EFI_PCI_ATTRIBUTE_ISA_IO_16 | \
+ EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
+ EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
+ EFI_PCI_ATTRIBUTE_VGA_IO_16 | \
+ EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
+
+PCI_ROOT_BRIDGE mPciRootBridges[NUM_PCIE_CONTROLLER];
+
+/**
+ Function to set-up iATU outbound window for PCIe controller
+
+ @param Dbi Address of PCIe host controller.
+ @param Idx Index of iATU outbound window.
+ @param Type Type(Cfg0/Cfg1/Mem/IO) of iATU outbound window.
+ @param Phys PCIe controller phy address for outbound window.
+ @param BusAdr PCIe controller bus address for outbound window.
+ @param Pcie Size of PCIe controller space(Cfg0/Cfg1/Mem/IO).
+
+**/
+STATIC
+VOID
+PcieIatuOutboundSet (
+ IN EFI_PHYSICAL_ADDRESS Dbi,
+ IN UINT32 Idx,
+ IN UINT32 Type,
+ IN UINT64 Phys,
+ IN UINT64 BusAddr,
+ IN UINT64 Size
+ )
+{
+ MmioWrite32 (Dbi + IATU_VIEWPORT_OFF,
+ (UINT32)(IATU_VIEWPORT_OUTBOUND | Idx));
+ MmioWrite32 (Dbi + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
+ (UINT32)Phys);
+ MmioWrite32 (Dbi + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
+ (UINT32)(Phys >> 32));
+ MmioWrite32 (Dbi + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
+ (UINT32)(Phys + Size - BIT0));
+ MmioWrite32 (Dbi + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
+ (UINT32)BusAddr);
+ MmioWrite32 (Dbi + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
+ (UINT32)(BusAddr >> 32));
+ MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
+ (UINT32)Type);
+ MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
+ IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN);
+}
+
+/**
+ Function to check PCIe controller LTSSM state
+
+ @param Pcie Address of PCIe host controller.
+
+**/
+STATIC
+INTN
+PcieLinkState (
+ IN EFI_PHYSICAL_ADDRESS Pcie
+ )
+{
+ UINT32 State;
+
+ //
+ // Reading PCIe controller LTSSM state
+ //
+ if (FeaturePcdGet (PcdPciLutBigEndian)) {
+ State = SwapMmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
+ LTSSM_STATE_MASK;
+ } else {
+ State = MmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
+ LTSSM_STATE_MASK;
+ }
+
+ if (State < LTSSM_PCIE_L0) {
+ DEBUG ((DEBUG_INFO," Pcie Link error. LTSSM=0x%2x\n", State));
+ return EFI_SUCCESS;
+ }
+
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Helper function to check PCIe link state
+
+ @param Pcie Address of PCIe host controller.
+
+**/
+STATIC
+INTN
+PcieLinkUp (
+ IN EFI_PHYSICAL_ADDRESS Pcie
+ )
+{
+ INTN State;
+ UINT32 Cap;
+
+ State = PcieLinkState (Pcie);
+ if (State) {
+ return State;
+ }
+
+ //
+ // Try to download speed to gen1
+ //
+ Cap = MmioRead32 ((UINTN)Pcie + PCI_LINK_CAP);
+ MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, (UINT32)(Cap & (~PCI_LINK_SPEED_MASK)) | BIT0);
+ State = PcieLinkState (Pcie);
+ if (State) {
+ return State;
+ }
+
+ MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, Cap);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function checks whether PCIe is enabled or not
+ depending upon SoC serdes protocol map
+
+ @param PcieNum PCIe number.
+
+ @return The PCIe number enabled in map.
+ @return FALSE PCIe number is disabled in map.
+
+**/
+STATIC
+BOOLEAN
+IsPcieNumEnabled(
+ IN UINTN PcieNum
+ )
+{
+ UINT64 SerDes1ProtocolMap;
+
+ SerDes1ProtocolMap = 0x0;
+
+ //
+ // Reading serdes map
+ //
+ GetSerdesProtocolMaps (&SerDes1ProtocolMap);
+
+ //
+ // Verify serdes line is configured in the map
+ //
+ if (PcieNum < NUM_PCIE_CONTROLLER) {
+ return IsSerDesLaneProtocolConfigured (SerDes1ProtocolMap, (PcieNum + BIT0));
+ } else {
+ DEBUG ((DEBUG_ERROR, "Device not supported\n"));
+ }
+
+ return FALSE;
+}
+
+/**
+ Function to set-up iATU outbound window for PCIe controller
+
+ @param Pcie Address of PCIe host controller
+ @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
+ @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
+ @param MemBase PCIe controller phy address in MMIO32 Memory Space.
+ @param Mem64Base PCIe controller phy address in MMIO64 Memory Space.
+ @param IoBase PCIe controller phy address IO Space.
+**/
+STATIC
+VOID
+PcieSetupAtu (
+ IN EFI_PHYSICAL_ADDRESS Pcie,
+ IN EFI_PHYSICAL_ADDRESS Cfg0Base,
+ IN EFI_PHYSICAL_ADDRESS Cfg1Base,
+ IN EFI_PHYSICAL_ADDRESS MemBase,
+ IN EFI_PHYSICAL_ADDRESS Mem64Base,
+ IN EFI_PHYSICAL_ADDRESS IoBase
+ )
+{
+
+ //
+ // iATU : OUTBOUND WINDOW 0 : CFG0
+ //
+ PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX0,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
+ Cfg0Base,
+ SEG_CFG_BUS,
+ SEG_CFG_SIZE);
+
+ //
+ // iATU : OUTBOUND WINDOW 1 : CFG1
+ PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX1,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
+ Cfg1Base,
+ SEG_CFG_BUS,
+ SEG_CFG_SIZE);
+ //
+ // iATU 2 : OUTBOUND WINDOW 2 : MMIO32
+ //
+ PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX2,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | BIT12,
+ MemBase,
+ SEG_MEM_BUS,
+ SEG_MEM_SIZE);
+
+ //
+ // iATU 3 : OUTBOUND WINDOW 3: IO
+ //
+ PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX3,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
+ IoBase,
+ SEG_IO_BUS,
+ SEG_IO_SIZE);
+ //
+ // iATU 4 : OUTBOUND WINDOW 4 : MMIO64
+ //
+ PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX4,
+ IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
+ Mem64Base,
+ SEG_MEM64_BASE,
+ MEM64_LIMIT);
+
+ if (FeaturePcdGet (PcdPciDebug) == TRUE) {
+ INTN Cnt;
+ UINTN AddrTemp;
+
+ for (Cnt = 0; Cnt <= IATU_REGION_INDEX4; Cnt++) {
+ MmioWrite32 ((UINTN)Pcie + IATU_VIEWPORT_OFF,
+ (UINT32)(IATU_VIEWPORT_OUTBOUND | Cnt));
+ DEBUG ((DEBUG_INFO,"iATU%d:\n", Cnt));
+ AddrTemp = (UINTN)((UINTN)Pcie + IATU_VIEWPORT_OFF);
+ DEBUG ((DEBUG_INFO,"iATU%d VIEWPORT REG Addr:%08lx Val:%08lx\n",
+ Cnt, AddrTemp, MmioRead32 (AddrTemp)));
+ DEBUG ((DEBUG_INFO,"iATU%d VIEWPORT REG:%08lx\n",
+ Cnt, MmioRead32 ((UINTN)Pcie + IATU_VIEWPORT_OFF)));
+ DEBUG ((DEBUG_INFO,"\tLOWER PHYS 0x%08x\n",
+ MmioRead32 ((UINTN)Pcie + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0)));
+ DEBUG ((DEBUG_INFO,"\tUPPER PHYS 0x%08x\n",
+ MmioRead32 ((UINTN)Pcie + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0)));
+ DEBUG ((DEBUG_INFO,"\tLOWER BUS 0x%08x\n",
+ MmioRead32 ((UINTN)Pcie + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0)));
+ DEBUG ((DEBUG_INFO,"\tUPPER BUS 0x%08x\n",
+ MmioRead32 ((UINTN)Pcie + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0)));
+ DEBUG ((DEBUG_INFO,"\tLIMIT 0x%08x\n",
+ MmioRead32 ((UINTN)Pcie + IATU_LIMIT_ADDR_OFF_OUTBOUND_0)));
+ DEBUG ((DEBUG_INFO,"\tCR1 0x%08x\n",
+ MmioRead32 ((UINTN)Pcie + IATU_REGION_CTRL_1_OFF_OUTBOUND_0)));
+ DEBUG ((DEBUG_INFO,"\tCR2 0x%08x\n",
+ MmioRead32 ((UINTN)Pcie + IATU_REGION_CTRL_2_OFF_OUTBOUND_0)));
+ }
+ }
+}
+
+/**
+ Helper function to set-up PCIe controller
+
+ @param Pcie Address of PCIe host controller
+ @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
+ @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
+ @param MemBase PCIe controller phy address MMIO32 Memory Space.
+ @param Mem64Base PCIe controller phy address MMIO64 Memory Space.
+ @param IoBase PCIe controller phy address IO Space.
+
+**/
+STATIC
+VOID
+PcieSetupCntrl (
+ IN EFI_PHYSICAL_ADDRESS Pcie,
+ IN EFI_PHYSICAL_ADDRESS Cfg0Base,
+ IN EFI_PHYSICAL_ADDRESS Cfg1Base,
+ IN EFI_PHYSICAL_ADDRESS MemBase,
+ IN EFI_PHYSICAL_ADDRESS Mem64Base,
+ IN EFI_PHYSICAL_ADDRESS IoBase
+ )
+{
+ //
+ // iATU outbound set-up
+ //
+ PcieSetupAtu (Pcie, Cfg0Base, Cfg1Base, MemBase, Mem64Base, IoBase);
+
+ //
+ // program correct class for RC
+ //
+ MmioWrite32 ((UINTN)Pcie + PCI_BASE_ADDRESS_0, (BIT0 - BIT0));
+ MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)BIT0);
+ MmioWrite32 ((UINTN)Pcie + PCI_CLASS_DEVICE, (UINT32)PCI_CLASS_BRIDGE_PCI);
+ MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)(BIT0 - BIT0));
+}
+
+/**
+ Return all the root bridge instances in an array.
+
+ @param Count Return the count of root bridge instances.
+
+ @return All the root bridge instances in an array.
+
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+ OUT UINTN *Count
+ )
+{
+ UINTN Idx;
+ UINTN Loop;
+ INTN LinkUp;
+ UINT64 PciPhyMemAddr[NUM_PCIE_CONTROLLER];
+ UINT64 PciPhyMem64Addr[NUM_PCIE_CONTROLLER];
+ UINT64 PciPhyCfg0Addr[NUM_PCIE_CONTROLLER];
+ UINT64 PciPhyCfg1Addr[NUM_PCIE_CONTROLLER];
+ UINT64 PciPhyIoAddr[NUM_PCIE_CONTROLLER];
+ UINT64 Regs[NUM_PCIE_CONTROLLER];
+ UINT8 PciEnabled[NUM_PCIE_CONTROLLER];
+
+ *Count = 0;
+
+ //
+ // Filling local array for
+ // PCIe controller Physical address space for Cfg0,Cfg1,Mem,IO
+ // Host Contoller address
+ //
+ for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
+ PciPhyMemAddr[Idx] = PCI_SEG0_PHY_MEM_BASE + (PCI_BASE_DIFF * Idx);
+ PciPhyCfg0Addr[Idx] = PCI_SEG0_PHY_CFG0_BASE + (PCI_BASE_DIFF * Idx);
+ PciPhyCfg1Addr[Idx] = PCI_SEG0_PHY_CFG1_BASE + (PCI_BASE_DIFF * Idx);
+ PciPhyIoAddr [Idx] = PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx);
+ PciPhyMem64Addr[Idx] = PCI_SEG0_PHY_MEM64_BASE + (PCI_BASE_DIFF * Idx);
+ Regs[Idx] = PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx);
+ }
+
+ if (FeaturePcdGet (PcdPciDebug) == TRUE) {
+ DEBUG ((DEBUG_INFO, "In PCIE_INFO: %d\n", Idx));
+ DEBUG ((DEBUG_INFO, "PciNum:%d Info PCIe Controller Address: %016llx\n",
+ Idx,
+ Regs[Idx]));
+ DEBUG ((DEBUG_INFO, "Info CFG Values: %016llx:%016llx\n",
+ (UINT64)PciPhyCfg0Addr[Idx],
+ (UINT64)PciPhyCfg1Addr[Idx]));
+ DEBUG ((DEBUG_INFO, "Info Mem Values: %016llx\n",
+ (UINT64)PciPhyMemAddr[Idx]));
+ DEBUG ((DEBUG_INFO, "Info IO Values: %016llx\n",
+ (UINT64)PciPhyIoAddr[Idx]));
+ DEBUG ((DEBUG_INFO, "Info Mem64 Values: %016llx\n",
+ (UINT64)PciPhyMem64Addr[Idx]));
+ }
+
+ for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
+ //
+ // Verify PCIe controller is enabled in Soc Serdes Map
+ //
+ if (!IsPcieNumEnabled (Idx)) {
+ DEBUG ((DEBUG_ERROR, "PCIE%d is disabled\n", (Idx + BIT0)));
+ //
+ // Continue with other PCIe controller
+ //
+ continue;
+ }
+ DEBUG ((DEBUG_INFO, "PCIE%d is Enabled\n", Idx + BIT0));
+
+ //
+ // Verify PCIe controller LTSSM state
+ //
+ LinkUp = PcieLinkUp(Regs[Idx]);
+ if (!LinkUp) {
+ //
+ // Let the user know there's no PCIe link
+ //
+ DEBUG ((DEBUG_INFO,"no link, regs @ 0x%lx\n", Regs[Idx]));
+ //
+ // Continue with other PCIe controller
+ //
+ continue;
+ }
+ DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + BIT0));
+
+ //
+ // Function to set up address translation unit outbound window for
+ // PCIe Controller
+ //
+ PcieSetupCntrl (Regs[Idx],
+ PciPhyCfg0Addr[Idx],
+ PciPhyCfg1Addr[Idx],
+ PciPhyMemAddr[Idx],
+ PciPhyMem64Addr[Idx],
+ PciPhyIoAddr[Idx]);
+ //
+ // Local array to index all enable PCIe controllers
+ //
+ PciEnabled[*Count] = Idx;
+
+ *Count += BIT0;
+ }
+
+ if (*Count == 0) {
+ return NULL;
+ } else {
+ for (Loop = 0; Loop < *Count; Loop++) {
+ mPciRootBridges[Loop].Segment = PciEnabled[Loop];
+ mPciRootBridges[Loop].Supports = PCI_SUPPORT_ATTRIBUTES;
+ mPciRootBridges[Loop].Attributes = PCI_SUPPORT_ATTRIBUTES;
+ mPciRootBridges[Loop].DmaAbove4G = TRUE;
+ mPciRootBridges[Loop].NoExtendedConfigSpace = FALSE;
+ mPciRootBridges[Loop].ResourceAssigned = FALSE;
+ mPciRootBridges[Loop].AllocationAttributes = PCI_ALLOCATION_ATTRIBUTES;
+ mPciRootBridges[Loop].Bus.Base = PCI_SEG_BUSNUM_MIN;
+ mPciRootBridges[Loop].Bus.Limit = PCI_SEG_BUSNUM_MAX;
+ mPciRootBridges[Loop].Io.Base = PCI_SEG_PORTIO_MIN;
+ mPciRootBridges[Loop].Io.Limit = PCI_SEG_PORTIO_MAX;
+ mPciRootBridges[Loop].Io.Translation = MAX_UINT64 -
+ (PciEnabled[Loop] *
+ SEG_IO_SIZE) + 1;
+ mPciRootBridges[Loop].Mem.Base = PCI_SEG_MMIO32_MIN;
+ mPciRootBridges[Loop].Mem.Limit = PCI_SEG_MMIO32_MAX;
+ mPciRootBridges[Loop].Mem.Translation = MAX_UINT64 -
+ (PciEnabled[Loop] *
+ PCI_SEG_MMIO32_DIFF) + 1;
+ mPciRootBridges[Loop].MemAbove4G.Base = PciPhyMemAddr[PciEnabled[Loop]];
+ mPciRootBridges[Loop].MemAbove4G.Limit = PciPhyMemAddr[PciEnabled[Loop]] +
+ PCI_SEG_MMIO64_MAX_DIFF;
+ //
+ // No separate ranges for prefetchable and non-prefetchable BARs
+ //
+ mPciRootBridges[Loop].PMem.Base = MAX_UINT64;
+ mPciRootBridges[Loop].PMem.Limit = 0;
+ mPciRootBridges[Loop].PMemAbove4G.Base = MAX_UINT64;
+ mPciRootBridges[Loop].PMemAbove4G.Limit = 0;
+ mPciRootBridges[Loop].DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PciEnabled[Loop]];
+ }
+
+ return mPciRootBridges;
+ }
+}
+
+/**
+ Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
+
+ @param Bridges The root bridge instances array.
+ @param Count The count of the array.
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+ PCI_ROOT_BRIDGE *Bridges,
+ UINTN Count
+ )
+{
+}
+
+/**
+ Inform the platform that the resource conflict happens.
+
+ @param HostBridgeHandle Handle of the Host Bridge.
+ @param Configuration Pointer to PCI I/O and PCI memory resource
+ descriptors. The Configuration contains the resources
+ for all the root bridges. The resource for each root
+ bridge is terminated with END descriptor and an
+ additional END is appended indicating the end of the
+ entire resources. The resource descriptor field
+ values follow the description in
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ .SubmitResources().
+
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+ EFI_HANDLE HostBridgeHandle,
+ VOID *Configuration
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ UINTN RootBridgeIndex;
+ DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
+
+ RootBridgeIndex = 0;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+ while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+ DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
+ for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ ASSERT (Descriptor->ResType <
+ ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));
+ DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrLen, Descriptor->AddrRangeMax
+ ));
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+ DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
+ Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
+ ((Descriptor->SpecificFlag &
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+ ) != 0) ? L" (Prefetchable)" : L""
+ ));
+ }
+ }
+ //
+ // Skip the END descriptor for root bridge
+ //
+ ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+ );
+ }
+
+ return;
+}
diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
new file mode 100644
index 0000000..4f1c4d2
--- /dev/null
+++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -0,0 +1,51 @@
+## @file
+# PCI Host Bridge Library instance for NXP ARM SOC
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PciHostBridgeLib
+ FILE_GUID = f4c99bcc-5c95-49ad-b0f3-fc5b611dc9c1
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciHostBridgeLib
+
+[Sources]
+ PciHostBridgeLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ DebugLib
+ DevicePathLib
+ IoAccessLib
+ MemoryAllocationLib
+ PcdLib
+ SocLib
+ UefiBootServicesTableLib
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdNumPciController
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciDebug
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 36/41] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (34 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 35/41] Silicon/NXP: Implement PciHostBridgeLib support Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 11:09 ` Ard Biesheuvel
2018-12-21 18:49 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 37/41] Compilation: Update the fdf, dsc and dec files Meenakshi Aggarwal
` (6 subsequent siblings)
42 siblings, 2 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
NXP SOC has mutiple PCIe RCs,Adding respective implementation of
EFI_CPU_IO2_PROTOCOL to provide Memory Space Read/Write functions
used by generic Host Bridge Driver including correct value for
the translation offset during MMIO accesses
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 633 ++++++++++++++++++++++
Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 49 ++
2 files changed, 682 insertions(+)
create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
new file mode 100644
index 0000000..b5c175b
--- /dev/null
+++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
@@ -0,0 +1,633 @@
+/** @file
+ Produces the CPU I/O 2 Protocol.
+
+ Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+ Copyright 2018 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <NxpPcie.h>
+#include <Protocol/CpuIo2.h>
+
+#define MAX_IO_PORT_ADDRESS PCI_SEG_PORTIO_LIMIT
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE mHandle;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mInStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 0, // EfiCpuIoWidthFifoUint8
+ 0, // EfiCpuIoWidthFifoUint16
+ 0, // EfiCpuIoWidthFifoUint32
+ 0, // EfiCpuIoWidthFifoUint64
+ 1, // EfiCpuIoWidthFillUint8
+ 2, // EfiCpuIoWidthFillUint16
+ 4, // EfiCpuIoWidthFillUint32
+ 8 // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mOutStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 1, // EfiCpuIoWidthFifoUint8
+ 2, // EfiCpuIoWidthFifoUint16
+ 4, // EfiCpuIoWidthFifoUint32
+ 8, // EfiCpuIoWidthFifoUint64
+ 0, // EfiCpuIoWidthFillUint8
+ 0, // EfiCpuIoWidthFillUint16
+ 0, // EfiCpuIoWidthFillUint32
+ 0 // EfiCpuIoWidthFillUint64
+};
+
+/**
+ Check parameters to a CPU I/O 2 Protocol service request.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work.
+
+ @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The parameters for this request pass the checks.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+CpuIoCheckParameter (
+ IN BOOLEAN MmioOperation,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ UINT64 MaxCount;
+ UINT64 Limit;
+
+ //
+ // Check to see if Buffer is NULL
+ //
+ if (Buffer == NULL) {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Width is in the valid range
+ //
+ if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // For FIFO type, the target address won't increase during the access,
+ // so treat Count as 1
+ //
+ if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
+ Count = 1;
+ }
+
+ //
+ // Check to see if Width is in the valid range for I/O Port operations
+ //
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
+ if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Address is aligned
+ //
+ if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Check to see if any address associated with this transfer exceeds the maximum
+ // allowed address. The maximum address implied by the parameters passed in is
+ // Address + Size * Count. If the following condition is met, then the transfer
+ // is not supported.
+ //
+ // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
+ //
+ // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
+ // can also be the maximum integer value supported by the CPU, this range
+ // check must be adjusted to avoid all oveflow conditions.
+ //
+ Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
+ if (Count == 0) {
+ if (Address > Limit) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ } else {
+ MaxCount = RShiftU64 (Limit, Width);
+ if (MaxCount < (Count - 1)) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ }
+
+ //
+ // Check to see if Buffer is aligned
+ //
+ if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads memory-mapped registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceRead (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ //
+ // Make sure the parameters are valid
+ //
+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((Address >= (PCI_SEG0_MMIO32_MIN + PCI_SEG0_MMIO_OFFSET)) &&
+ (Address <= (PCI_SEG0_MMIO32_MAX + PCI_SEG0_MMIO_OFFSET))) {
+ Address += PCI_SEG0_MMIO_MEMBASE - PCI_SEG0_MMIO_OFFSET;
+ } else if ((Address >= (PCI_SEG1_MMIO32_MIN + PCI_SEG1_MMIO_OFFSET)) &&
+ (Address <= (PCI_SEG1_MMIO32_MAX + PCI_SEG1_MMIO_OFFSET))) {
+ Address += PCI_SEG1_MMIO_MEMBASE - PCI_SEG1_MMIO_OFFSET;
+ } else if ((Address >= (PCI_SEG2_MMIO32_MIN + PCI_SEG2_MMIO_OFFSET)) &&
+ (Address <= (PCI_SEG2_MMIO32_MAX + PCI_SEG2_MMIO_OFFSET))) {
+ Address += PCI_SEG2_MMIO_MEMBASE - PCI_SEG2_MMIO_OFFSET;
+ } else if ((Address >= (PCI_SEG3_MMIO32_MIN + PCI_SEG3_MMIO_OFFSET)) &&
+ (Address <= (PCI_SEG3_MMIO32_MAX + PCI_SEG3_MMIO_OFFSET))) {
+ Address += PCI_SEG3_MMIO_MEMBASE - PCI_SEG3_MMIO_OFFSET;
+ } else {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Writes memory-mapped registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceWrite (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ //
+ // Make sure the parameters are valid
+ //
+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((Address >= (PCI_SEG0_MMIO32_MIN + PCI_SEG0_MMIO_OFFSET)) &&
+ (Address <= (PCI_SEG0_MMIO32_MAX + PCI_SEG0_MMIO_OFFSET))) {
+ Address += PCI_SEG0_MMIO_MEMBASE - PCI_SEG0_MMIO_OFFSET;
+ } else if ((Address >= (PCI_SEG1_MMIO32_MIN + PCI_SEG1_MMIO_OFFSET)) &&
+ (Address <= (PCI_SEG1_MMIO32_MAX + PCI_SEG1_MMIO_OFFSET))) {
+ Address += PCI_SEG1_MMIO_MEMBASE - PCI_SEG1_MMIO_OFFSET;
+ } else if ((Address >= (PCI_SEG2_MMIO32_MIN + PCI_SEG2_MMIO_OFFSET)) &&
+ (Address <= (PCI_SEG2_MMIO32_MAX + PCI_SEG2_MMIO_OFFSET))) {
+ Address += PCI_SEG2_MMIO_MEMBASE - PCI_SEG2_MMIO_OFFSET;
+ } else if ((Address >= (PCI_SEG3_MMIO32_MIN + PCI_SEG3_MMIO_OFFSET)) &&
+ (Address <= (PCI_SEG3_MMIO32_MAX + PCI_SEG3_MMIO_OFFSET))) {
+ Address += PCI_SEG3_MMIO_MEMBASE - PCI_SEG3_MMIO_OFFSET;
+ } else {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads I/O registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceRead (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ //
+ // Make sure the parameters are valid
+ //
+ Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG0_PORTIO_OFFSET)) &&
+ (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG0_PORTIO_OFFSET))) {
+ Address += PCI_SEG0_PORTIO_MEMBASE - PCI_SEG0_PORTIO_OFFSET;
+ } else if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG1_PORTIO_OFFSET)) &&
+ (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG1_PORTIO_OFFSET))) {
+ Address += PCI_SEG1_PORTIO_MEMBASE - PCI_SEG1_PORTIO_OFFSET;
+ } else if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG2_PORTIO_OFFSET)) &&
+ (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG2_PORTIO_OFFSET))) {
+ Address += PCI_SEG2_PORTIO_MEMBASE - PCI_SEG2_PORTIO_OFFSET;
+ } else if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG3_PORTIO_OFFSET)) &&
+ (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG3_PORTIO_OFFSET))) {
+ Address += PCI_SEG3_PORTIO_MEMBASE - PCI_SEG3_PORTIO_OFFSET;
+ } else {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
+
+ for (Uint8Buffer = Buffer; Count > 0;
+ Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write I/O registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceWrite (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ //
+ // Make sure the parameters are valid
+ //
+ Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG0_PORTIO_OFFSET)) &&
+ (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG0_PORTIO_OFFSET))) {
+ Address += PCI_SEG0_PORTIO_MEMBASE - PCI_SEG0_PORTIO_OFFSET;
+ } else if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG1_PORTIO_OFFSET)) &&
+ (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG1_PORTIO_OFFSET))) {
+ Address += PCI_SEG1_PORTIO_MEMBASE - PCI_SEG1_PORTIO_OFFSET;
+ } else if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG2_PORTIO_OFFSET)) &&
+ (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG2_PORTIO_OFFSET))) {
+ Address += PCI_SEG2_PORTIO_MEMBASE - PCI_SEG2_PORTIO_OFFSET;
+ } else if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG3_PORTIO_OFFSET)) &&
+ (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG3_PORTIO_OFFSET))) {
+ Address += PCI_SEG3_PORTIO_MEMBASE - PCI_SEG3_PORTIO_OFFSET;
+ } else {
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
+
+ for (Uint8Buffer = (UINT8 *)Buffer; Count > 0;
+ Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+//
+// CPU I/O 2 Protocol instance
+//
+STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
+ {
+ CpuMemoryServiceRead,
+ CpuMemoryServiceWrite
+ },
+ {
+ CpuIoServiceRead,
+ CpuIoServiceWrite
+ }
+};
+
+
+/**
+ The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+PciCpuIo2Initialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mHandle,
+ &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
new file mode 100644
index 0000000..7e958b1
--- /dev/null
+++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
@@ -0,0 +1,49 @@
+## @file
+# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
+#
+# Copyright 2018 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PciCpuIo2Dxe
+ FILE_GUID = 7bff18d7-9aae-434b-9c06-f10a7e157eac
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PciCpuIo2Initialize
+
+[Sources]
+ PciCpuIo2Dxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdNumPciController
+
+[Protocols]
+ gEfiCpuIo2ProtocolGuid ## PRODUCES
+
+[Depex]
+ TRUE
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 37/41] Compilation: Update the fdf, dsc and dec files.
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (35 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 36/41] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 18:51 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 38/41] DWC3 : Add DWC3 USB controller initialization driver Meenakshi Aggarwal
` (5 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
LS1043A PCIe compilation and update firmware device,
description and declaration files.Defining Embedded Package
PCD which should be at least 20 for 64K PCIe IO size required
for CPU hob during PEI phase to Add IO space post PEI phase.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 16 ++++++++++++++++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 7 +++++++
.../LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++
.../LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
Platform/NXP/NxpQoriqLs.dsc.inc | 2 ++
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 4 ++++
Silicon/NXP/NxpQoriqLs.dec | 10 ++++++++++
7 files changed, 47 insertions(+)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
index b69ffa2..b43c81a 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -42,6 +42,8 @@
BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf
NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
+ PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
+ PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
[PcdsFixedAtBuild.common]
@@ -74,6 +76,13 @@
gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000
gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000
+ #
+ # PCI PCDs.
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x10000
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x7FC
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
@@ -94,4 +103,11 @@
Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
+ Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+ }
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
##
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
index 6b27aed..d02b3cc 100644
--- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -131,6 +131,13 @@ READ_LOCK_STATUS = TRUE
INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
#
+ # PCI
+ #
+ INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
# Network modules
#
INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
index 7feac56..f2c8b66 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -65,3 +65,5 @@
gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
+ gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdRomSize
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
index 64c5612..1ef3292 100644
--- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ // ROM Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdRomBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
// IFC region 1
//
// A-009241 : Unaligned write transactions to IFC may result in corruption of data
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
index 5529a04..063d0b8 100644
--- a/Platform/NXP/NxpQoriqLs.dsc.inc
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -245,6 +245,8 @@
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|20
+
#
# Optional feature to help prevent EFI memory map fragments
# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
index a4eb117..f3220fa 100644
--- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -64,6 +64,9 @@
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3
+ gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
+ gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
#
# Big Endian IPs
@@ -71,5 +74,6 @@
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE
##
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index da148b7..aae0a34 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -78,6 +78,16 @@
gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129
gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A
gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0|UINT64|0x0000012B
+ gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x0|UINT64|0x0000012C
+ gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x0|UINT64|0x0000012D
+
+ #
+ # PCI PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x000001D0
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x000001D1
+ gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE|BOOLEAN|0x000001D2
+ gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|0|UINT32|0x000001D3
#
# IFC PCDs
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 38/41] DWC3 : Add DWC3 USB controller initialization driver.
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (36 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 37/41] Compilation: Update the fdf, dsc and dec files Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 19:03 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 39/41] LS2088 : Enable support of USB controller Meenakshi Aggarwal
` (4 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Add support of DWC3 controller driver which
Performs DWC3 controller initialization and
Register itself as NonDiscoverableMmioDevice
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c | 218 +++++++++++++++++++++++++++
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h | 144 ++++++++++++++++++
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf | 48 ++++++
Silicon/NXP/NxpQoriqLs.dec | 5 +
4 files changed, 415 insertions(+)
create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
new file mode 100644
index 0000000..0a9c821
--- /dev/null
+++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
@@ -0,0 +1,218 @@
+/** @file
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/NonDiscoverableDeviceRegistrationLib.h>
+
+#include "UsbHcd.h"
+
+STATIC
+VOID
+XhciSetBeatBurstLength (
+ IN UINTN UsbReg
+ )
+{
+ DWC3 *Dwc3Reg;
+
+ Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET);
+
+ MmioAndThenOr32 ((UINTN)&Dwc3Reg->GSBusCfg0, ~USB3_ENABLE_BEAT_BURST_MASK,
+ USB3_ENABLE_BEAT_BURST);
+ MmioOr32 ((UINTN)&Dwc3Reg->GSBusCfg1, USB3_SET_BEAT_BURST_LIMIT);
+
+ return;
+}
+
+STATIC
+VOID
+Dwc3SetFladj (
+ IN DWC3 *Dwc3Reg,
+ IN UINT32 Val
+ )
+{
+ MmioOr32 ((UINTN)&Dwc3Reg->GFLAdj, GFLADJ_30MHZ_REG_SEL |
+ GFLADJ_30MHZ(Val));
+}
+
+VOID
+Dwc3SetMode (
+ IN DWC3 *Dwc3Reg,
+ IN UINT32 Mode
+ )
+{
+ MmioAndThenOr32 ((UINTN)&Dwc3Reg->GCtl,
+ ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
+ DWC3_GCTL_PRTCAPDIR(Mode));
+}
+
+STATIC
+VOID
+Dwc3CoreSoftReset (
+ IN DWC3 *Dwc3Reg
+ )
+{
+ MmioOr32 ((UINTN)&Dwc3Reg->GCtl, DWC3_GCTL_CORESOFTRESET);
+ MmioOr32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
+ MmioOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
+ MmioAnd32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], ~DWC3_GUSB3PIPECTL_PHYSOFTRST);
+ MmioAnd32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg, ~DWC3_GUSB2PHYCFG_PHYSOFTRST);
+ MmioAnd32 ((UINTN)&Dwc3Reg->GCtl, ~DWC3_GCTL_CORESOFTRESET);
+
+ return;
+}
+
+STATIC
+EFI_STATUS
+Dwc3CoreInit (
+ IN DWC3 *Dwc3Reg
+ )
+{
+ UINT32 Revision;
+ UINT32 Reg;
+ UINTN Dwc3Hwparams1;
+
+ Revision = MmioRead32 ((UINTN)&Dwc3Reg->GSnpsId);
+ //
+ // This should read as 0x5533, ascii of U3(DWC_usb3) followed by revision number
+ //
+ if ((Revision & DWC3_GSNPSID_MASK) != DWC3_SYNOPSYS_ID) {
+ DEBUG ((DEBUG_ERROR,"This is not a DesignWare USB3 DRD Core.\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ Dwc3CoreSoftReset (Dwc3Reg);
+
+ Reg = MmioRead32 ((UINTN)&Dwc3Reg->GCtl);
+ Reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
+ Reg &= ~DWC3_GCTL_DISSCRAMBLE;
+
+ Dwc3Hwparams1 = MmioRead32 ((UINTN)&Dwc3Reg->GHwParams1);
+
+ if (DWC3_GHWPARAMS1_EN_PWROPT(Dwc3Hwparams1) == DWC3_GHWPARAMS1_EN_PWROPT_CLK) {
+ Reg &= ~DWC3_GCTL_DSBLCLKGTNG;
+ } else {
+ DEBUG ((DEBUG_ERROR,"No power optimization available.\n"));
+ }
+
+ if ((Revision & DWC3_RELEASE_MASK) < DWC3_RELEASE_190a) {
+ Reg |= DWC3_GCTL_U2RSTECN;
+ }
+
+ MmioWrite32 ((UINTN)&Dwc3Reg->GCtl, Reg);
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+XhciCoreInit (
+ IN UINTN UsbReg
+ )
+{
+ EFI_STATUS Status;
+ DWC3 *Dwc3Reg;
+
+ Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET);
+
+ Status = Dwc3CoreInit (Dwc3Reg);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Dwc3CoreInit Failed for controller 0x%x (0x%x) \n",
+ UsbReg, Status));
+ return Status;
+ }
+
+ Dwc3SetMode (Dwc3Reg, DWC3_GCTL_PRTCAP_HOST);
+
+ Dwc3SetFladj (Dwc3Reg, GFLADJ_30MHZ_DEFAULT);
+
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+InitializeUsbController (
+ IN UINTN UsbReg
+ )
+{
+ EFI_STATUS Status;
+
+ Status = XhciCoreInit (UsbReg);
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Change beat burst and outstanding pipelined transfers requests
+ //
+ XhciSetBeatBurstLength (UsbReg);
+
+ return Status;
+}
+
+/**
+ The Entry Point of module. It follows the standard UEFI driver model.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeUsbHcd (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINT32 NumUsbController;
+ UINT32 ControllerAddr;
+
+ Status = EFI_SUCCESS;
+ NumUsbController = PcdGet32 (PcdNumUsbController);
+
+ while (NumUsbController) {
+ NumUsbController--;
+ ControllerAddr = PcdGet32 (PcdUsbBaseAddr) +
+ (NumUsbController * PcdGet32 (PcdUsbSize));
+
+ Status = InitializeUsbController (ControllerAddr);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "USB Controller initialization Failed for %d (0x%x)\n",
+ ControllerAddr, Status));
+ continue;
+ }
+
+ Status = RegisterNonDiscoverableMmioDevice (
+ NonDiscoverableDeviceTypeXhci,
+ NonDiscoverableDeviceDmaTypeNonCoherent,
+ NULL,
+ NULL,
+ 1,
+ ControllerAddr, PcdGet32 (PcdUsbSize)
+ );
+
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Failed to register USB device (0x%x) with error 0x%x \n",
+ ControllerAddr, Status));
+ }
+ }
+
+ return Status;
+}
diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
new file mode 100644
index 0000000..99d86dc
--- /dev/null
+++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
@@ -0,0 +1,144 @@
+/** @file
+
+ Copyright 2017 NXP
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __USB_HCD__
+#define __USB_HCD__
+
+#include <Base.h>
+
+/* Global constants */
+#define DWC3_GSNPSID_MASK 0xffff0000
+#define DWC3_SYNOPSYS_ID 0x55330000
+#define DWC3_RELEASE_MASK 0xffff
+#define DWC3_REG_OFFSET 0xC100
+#define DWC3_RELEASE_190a 0x190a
+
+/* Global Configuration Register */
+#define DWC3_GCTL_U2RSTECN BIT16
+#define DWC3_GCTL_PRTCAPDIR(N) ((N) << 12)
+#define DWC3_GCTL_PRTCAP_HOST 1
+#define DWC3_GCTL_PRTCAP_OTG 3
+#define DWC3_GCTL_CORESOFTRESET BIT11
+#define DWC3_GCTL_SCALEDOWN(N) ((N) << 4)
+#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
+#define DWC3_GCTL_DISSCRAMBLE BIT3
+#define DWC3_GCTL_DSBLCLKGTNG BIT0
+
+/* Global HWPARAMS1 Register */
+#define DWC3_GHWPARAMS1_EN_PWROPT(N) (((N) & (3 << 24)) >> 24)
+#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
+
+/* Global USB2 PHY Configuration Register */
+#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT31
+
+/* Global USB3 PIPE Control Register */
+#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT31
+
+/* Global Frame Length Adjustment Register */
+#define GFLADJ_30MHZ_REG_SEL BIT7
+#define GFLADJ_30MHZ(N) ((N) & 0x3f)
+#define GFLADJ_30MHZ_DEFAULT 0x20
+
+/* Default to the FSL XHCI defines */
+#define USB3_ENABLE_BEAT_BURST 0xF
+#define USB3_ENABLE_BEAT_BURST_MASK 0xFF
+#define USB3_SET_BEAT_BURST_LIMIT 0xF00
+
+typedef struct {
+ UINT32 GEvntAdrLo;
+ UINT32 GEvntAdrHi;
+ UINT32 GEvntSiz;
+ UINT32 GEvntCount;
+} G_EVENT_BUFFER;
+
+typedef struct {
+ UINT32 DDepCmdPar2;
+ UINT32 DDepCmdPar1;
+ UINT32 DDepCmdPar0;
+ UINT32 DDepCmd;
+} D_PHYSICAL_EP;
+
+typedef struct {
+ UINT32 GSBusCfg0;
+ UINT32 GSBusCfg1;
+ UINT32 GTxThrCfg;
+ UINT32 GRxThrCfg;
+ UINT32 GCtl;
+ UINT32 Res1;
+ UINT32 GSts;
+ UINT32 Res2;
+ UINT32 GSnpsId;
+ UINT32 GGpio;
+ UINT32 GUid;
+ UINT32 GUctl;
+ UINT64 GBusErrAddr;
+ UINT64 GPrtbImap;
+ UINT32 GHwParams0;
+ UINT32 GHwParams1;
+ UINT32 GHwParams2;
+ UINT32 GHwParams3;
+ UINT32 GHwParams4;
+ UINT32 GHwParams5;
+ UINT32 GHwParams6;
+ UINT32 GHwParams7;
+ UINT32 GDbgFifoSpace;
+ UINT32 GDbgLtssm;
+ UINT32 GDbgLnmcc;
+ UINT32 GDbgBmu;
+ UINT32 GDbgLspMux;
+ UINT32 GDbgLsp;
+ UINT32 GDbgEpInfo0;
+ UINT32 GDbgEpInfo1;
+ UINT64 GPrtbImapHs;
+ UINT64 GPrtbImapFs;
+ UINT32 Res3[28];
+ UINT32 GUsb2PhyCfg[16];
+ UINT32 GUsb2I2cCtl[16];
+ UINT32 GUsb2PhyAcc[16];
+ UINT32 GUsb3PipeCtl[16];
+ UINT32 GTxFifoSiz[32];
+ UINT32 GRxFifoSiz[32];
+ G_EVENT_BUFFER GEvntBuf[32];
+ UINT32 GHwParams8;
+ UINT32 Res4[11];
+ UINT32 GFLAdj;
+ UINT32 Res5[51];
+ UINT32 DCfg;
+ UINT32 DCtl;
+ UINT32 DEvten;
+ UINT32 DSts;
+ UINT32 DGCmdPar;
+ UINT32 DGCmd;
+ UINT32 Res6[2];
+ UINT32 DAlepena;
+ UINT32 Res7[55];
+ D_PHYSICAL_EP DPhyEpCmd[32];
+ UINT32 Res8[128];
+ UINT32 OCfg;
+ UINT32 OCtl;
+ UINT32 OEvt;
+ UINT32 OEvtEn;
+ UINT32 OSts;
+ UINT32 Res9[3];
+ UINT32 AdpCfg;
+ UINT32 AdpCtl;
+ UINT32 AdpEvt;
+ UINT32 AdpEvten;
+ UINT32 BcCfg;
+ UINT32 Res10;
+ UINT32 BcEvt;
+ UINT32 BcEvten;
+} DWC3;
+
+#endif
diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
new file mode 100644
index 0000000..ac74bc6
--- /dev/null
+++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
@@ -0,0 +1,48 @@
+# UsbHcd.inf
+#
+# Copyright 2017 NXP
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001a
+ BASE_NAME = UsbHcdDxe
+ FILE_GUID = 196e7c2a-37b2-4b85-8683-718588952449
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InitializeUsbHcd
+
+[Sources.common]
+ UsbHcd.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ IoLib
+ MemoryAllocationLib
+ NonDiscoverableDeviceRegistrationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[FixedPcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbSize
+
+[Depex]
+ TRUE
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
index aae0a34..dd2c314 100644
--- a/Silicon/NXP/NxpQoriqLs.dec
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -82,6 +82,11 @@
gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x0|UINT64|0x0000012D
#
+ # USB PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|0|UINT32|0x00000170
+
+ #
# PCI PCDs
#
gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x000001D0
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 39/41] LS2088 : Enable support of USB controller
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (37 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 38/41] DWC3 : Add DWC3 USB controller initialization driver Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 40/41] Platform/NXP:PCIe enablement for LS1046A RDB Meenakshi Aggarwal
` (3 subsequent siblings)
42 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
Enable support of USB drives on ls2088 board.
LS2088 has DWC3 controller
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 1 +
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 13 +++++++++++++
Platform/NXP/NxpQoriqLs.dsc.inc | 12 ++++++++++++
Silicon/NXP/LS2088A/LS2088A.dsc.inc | 1 +
4 files changed, 27 insertions(+)
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
index e788581..e074991 100755
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -110,3 +110,4 @@
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
+ Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
index 61bb160..62f084d 100644
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
@@ -153,6 +153,19 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
!endif
+ INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+ #
+ # USB Support
+ #
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ INF Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+
#
# FAT filesystem + GPT/MBR partitioning
#
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
index 063d0b8..3236b02 100644
--- a/Platform/NXP/NxpQoriqLs.dsc.inc
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -100,6 +100,7 @@
VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
[LibraryClasses.common.SEC]
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
@@ -368,6 +369,17 @@
!endif
#
+ # USB Support
+ #
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+ #
# FAT filesystem + GPT/MBR partitioning
#
MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc.inc b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
index 2cff40f..0d8fd82 100644
--- a/Silicon/NXP/LS2088A/LS2088A.dsc.inc
+++ b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
@@ -68,5 +68,6 @@
gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|2
##
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 40/41] Platform/NXP:PCIe enablement for LS1046A RDB
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (38 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 39/41] LS2088 : Enable support of USB controller Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 19:05 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 41/41] Platform/NXP:PCIe enablement for LS2088A RDB Meenakshi Aggarwal
` (2 subsequent siblings)
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
Compilation: Update the fdf, dsc and dec files.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 15 +++++++++++++++
Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 7 +++++++
.../LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++
.../NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 3 +++
5 files changed, 33 insertions(+)
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
index 7eb08a9..57f2043 100644
--- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
@@ -41,6 +41,8 @@
IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
BoardLib|Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf
+ PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
+ PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
[PcdsFixedAtBuild.common]
@@ -65,6 +67,7 @@
gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE
#
# RTC Pcds
@@ -72,6 +75,12 @@
gPcf2129RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
gPcf2129RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
+ #
+ # PCI PCDs.
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x80000
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
@@ -85,6 +94,12 @@
Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+ Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+ }
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
##
diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
index 443b561..887f386 100644
--- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
+++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
@@ -124,6 +124,13 @@ READ_LOCK_STATUS = TRUE
INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
#
+ # PCI
+ #
+ INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
# Network modules
#
INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
index 49b57fc..5e09757 100644
--- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -42,6 +42,8 @@
gArmTokenSpaceGuid.PcdArmPrimaryCore
gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+ gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdRomSize
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
index 64c5612..1ef3292 100644
--- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
+++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ // ROM Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdRomBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
// IFC region 1
//
// A-009241 : Unaligned write transactions to IFC may result in corruption of data
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
index 9f87028..59a6150 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -64,5 +64,8 @@
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3
+ gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
+ gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
##
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [PATCH edk2-platforms 41/41] Platform/NXP:PCIe enablement for LS2088A RDB
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (39 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 40/41] Platform/NXP:PCIe enablement for LS1046A RDB Meenakshi Aggarwal
@ 2018-11-28 15:01 ` Meenakshi Aggarwal
2018-12-21 19:05 ` Leif Lindholm
2018-12-17 9:50 ` [PATCH edk2-platforms 00/41] NXP : Add support of LS1043, LS1046 and LS2088 SoCs Leif Lindholm
[not found] ` <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com>
42 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-11-28 15:01 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, edk2-devel
From: Vabhav <vabhav.sharma@nxp.com>
Compilation: Update the fdf, dsc and dec files.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 17 +++++++++++++++++
Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 7 +++++++
.../Library/PlatformLib/ArmPlatformLib.inf | 2 ++
.../LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
Silicon/NXP/LS2088A/LS2088A.dsc.inc | 3 +++
5 files changed, 35 insertions(+)
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
index e074991..aefc214 100755
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
@@ -43,6 +43,8 @@
BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
+ PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
+ PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
[PcdsFixedAtBuild.common]
@@ -92,6 +94,13 @@
gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x580000000
gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x580300000
+ #
+ # PCI PCDs.
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x80000
+ gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
@@ -111,3 +120,11 @@
Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
+ Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
+ }
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ ##
diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
index 62f084d..d32c5a0 100644
--- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
+++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
@@ -129,6 +129,13 @@ READ_LOCK_STATUS = TRUE
INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
#
+ # PCI
+ #
+ INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ #
# Network modules
#
INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
index f5e5abd..0b836a8 100644
--- a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -44,6 +44,8 @@
gArmTokenSpaceGuid.PcdArmPrimaryCore
gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+ gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdRomSize
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
index ccb49f6..8b2145b 100644
--- a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
+++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -80,6 +80,12 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ // ROM Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdRomBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
// IFC region 1
//
// A-009241 : Unaligned write transactions to IFC may result in corruption of data
diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc.inc b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
index 0d8fd82..831edea 100644
--- a/Silicon/NXP/LS2088A/LS2088A.dsc.inc
+++ b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
@@ -69,5 +69,8 @@
gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000
gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|2
+ gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|4
+ gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
+ gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
##
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 00/41] NXP : Add support of LS1043, LS1046 and LS2088 SoCs
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
` (40 preceding siblings ...)
2018-11-28 15:01 ` [PATCH edk2-platforms 41/41] Platform/NXP:PCIe enablement for LS2088A RDB Meenakshi Aggarwal
@ 2018-12-17 9:50 ` Leif Lindholm
[not found] ` <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com>
42 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-17 9:50 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
Hi Meenakshi,
I will start going through this set today.
It would be most helpful if you could also provide this set on a
public git branch I can get at.
Best Regards,
Leif
On Wed, Nov 28, 2018 at 08:31:14PM +0530, Meenakshi Aggarwal wrote:
> We have combined all review comments recieved till now.
>
> Following patches will add support of NXP SoCs[LS1043, LS1046 and LS2088] in edk2-platforms.
>
> Our directory structure will be:
>
> edk2-platforms
> |-- Platform
> | |-- NXP
> | | |-- FVRules.fdf.inc
> | | |-- LS1043aRdbPkg
> | | | |-- Drivers
> | | | | `-- PlatformDxe
> | | | | |-- PlatformDxe.c
> | | | | `-- PlatformDxe.inf
> | | | |-- Include
> | | | | `-- IfcBoardSpecific.h
> | | | |-- Library
> | | | | |-- BoardLib
> | | | | | |-- BoardLib.c
> | | | | | `-- BoardLib.inf
> | | | | `-- PlatformLib
> | | | | |-- ArmPlatformLib.c
> | | | | |-- ArmPlatformLib.inf
> | | | | |-- NxpQoriqLsHelper.S
> | | | | `-- NxpQoriqLsMem.c
> | | | |-- LS1043aRdbPkg.dec
> | | | |-- LS1043aRdbPkg.dsc
> | | | |-- LS1043aRdbPkg.fdf
> | | | `-- VarStore.fdf.inc
> | | |-- LS1046aRdbPkg
> | | | |-- Drivers
> | | | | `-- PlatformDxe
> | | | | |-- PlatformDxe.c
> | | | | `-- PlatformDxe.inf
> | | | |-- Include
> | | | | `-- IfcBoardSpecific.h
> | | | |-- Library
> | | | | |-- BoardLib
> | | | | | |-- BoardLib.c
> | | | | | `-- BoardLib.inf
> | | | | `-- PlatformLib
> | | | | |-- ArmPlatformLib.c
> | | | | |-- ArmPlatformLib.inf
> | | | | |-- NxpQoriqLsHelper.S
> | | | | `-- NxpQoriqLsMem.c
> | | | |-- LS1046aRdbPkg.dec
> | | | |-- LS1046aRdbPkg.dsc
> | | | `-- LS1046aRdbPkg.fdf
> | | |-- LS2088aRdbPkg
> | | | |-- Drivers
> | | | | `-- PlatformDxe
> | | | | |-- PlatformDxe.c
> | | | | `-- PlatformDxe.inf
> | | | |-- Include
> | | | | |-- IfcBoardSpecific.h
> | | | | `-- Library
> | | | | `-- FpgaLib.h
> | | | |-- Library
> | | | | |-- BoardLib
> | | | | | |-- BoardLib.c
> | | | | | `-- BoardLib.inf
> | | | | |-- FpgaLib
> | | | | | |-- FpgaLib.c
> | | | | | `-- FpgaLib.inf
> | | | | `-- PlatformLib
> | | | | |-- ArmPlatformLib.c
> | | | | |-- ArmPlatformLib.inf
> | | | | |-- NxpQoriqLsHelper.S
> | | | | `-- NxpQoriqLsMem.c
> | | | |-- LS2088aRdbPkg.dec
> | | | |-- LS2088aRdbPkg.dsc
> | | | |-- LS2088aRdbPkg.fdf
> | | | `-- VarStore.fdf.inc
> | | |-- NxpQoriqLs.dsc.inc
> | | `-- Readme.md
> |-- Silicon
> | |-- Maxim
> | | `-- Library
> | | |-- Ds1307RtcLib
> | | | |-- Ds1307Rtc.h
> | | | |-- Ds1307RtcLib.c
> | | | |-- Ds1307RtcLib.dec
> | | | `-- Ds1307RtcLib.inf
> | | `-- Ds3232RtcLib
> | | |-- Ds3232Rtc.h
> | | |-- Ds3232RtcLib.c
> | | |-- Ds3232RtcLib.dec
> | | `-- Ds3232RtcLib.inf
> | |-- NXP
> | | |-- Drivers
> | | | |-- I2cDxe
> | | | | |-- ComponentName.c
> | | | | |-- DriverBinding.c
> | | | | |-- I2cDxe.c
> | | | | |-- I2cDxe.h
> | | | | `-- I2cDxe.inf
> | | | |-- NorFlashDxe
> | | | | |-- NorFlashBlockIoDxe.c
> | | | | |-- NorFlashDxe.c
> | | | | |-- NorFlashDxe.h
> | | | | |-- NorFlashDxe.inf
> | | | | `-- NorFlashFvbDxe.c
> | | | |-- PciCpuIo2Dxe
> | | | | |-- PciCpuIo2Dxe.c
> | | | | `-- PciCpuIo2Dxe.inf
> | | | |-- UsbHcdInitDxe
> | | | | |-- UsbHcd.c
> | | | | |-- UsbHcd.h
> | | | | `-- UsbHcd.inf
> | | | `-- WatchDog
> | | | |-- WatchDog.c
> | | | |-- WatchDogDxe.inf
> | | | `-- WatchDog.h
> | | |-- Include
> | | | |-- Chassis2
> | | | | |-- SerDes.h
> | | | | `-- Soc.h
> | | | |-- Chassis3
> | | | | |-- SerDes.h
> | | | | `-- Soc.h
> | | | |-- Ifc.h
> | | | |-- Library
> | | | | |-- FpgaLib.h
> | | | | |-- IfcLib.h
> | | | | |-- IoAccessLib.h
> | | | | `-- NorFlashLib.h
> | | | |-- NorFlash.h
> | | | `-- NxpPcie.h
> | | |-- Library
> | | | |-- DUartPortLib
> | | | | |-- DUart.h
> | | | | |-- DUartPortLib.c
> | | | | `-- DUartPortLib.inf
> | | | |-- FpgaLib
> | | | | |-- FpgaLib.c
> | | | | `-- FpgaLib.inf
> | | | |-- IfcLib
> | | | | |-- IfcLib.c
> | | | | |-- IfcLib.h
> | | | | `-- IfcLib.inf
> | | | |-- IoAccessLib
> | | | | |-- IoAccessLib.c
> | | | | `-- IoAccessLib.inf
> | | | |-- NorFlashLib
> | | | | |-- CfiCommand.h
> | | | | |-- CfiNorFlashLib.c
> | | | | |-- CfiNorFlashLib.h
> | | | | |-- NorFlashLib.c
> | | | | `-- NorFlashLib.inf
> | | | |-- Pcf2129RtcLib
> | | | | |-- Pcf2129Rtc.h
> | | | | |-- Pcf2129RtcLib.c
> | | | | |-- Pcf2129RtcLib.dec
> | | | | `-- Pcf2129RtcLib.inf
> | | | |-- Pcf8563RealTimeClockLib
> | | | | |-- Pcf8563RealTimeClockLib.c
> | | | | |-- Pcf8563RealTimeClockLib.dec
> | | | | `-- Pcf8563RealTimeClockLib.inf
> | | | |-- PciHostBridgeLib
> | | | | |-- PciHostBridgeLib.c
> | | | | `-- PciHostBridgeLib.inf
> | | | |-- PciSegmentLib
> | | | | |-- PciSegmentLib.c
> | | | | `-- PciSegmentLib.inf
> | | | `-- SocLib
> | | | |-- Chassis2
> | | | | `-- Soc.c
> | | | |-- Chassis3
> | | | | `-- Soc.c
> | | | |-- Chassis.c
> | | | |-- Chassis.h
> | | | |-- LS1043aSocLib.inf
> | | | |-- LS1046aSocLib.inf
> | | | |-- LS2088aSocLib.inf
> | | | `-- SerDes.c
> | | |-- LS1043A
> | | | |-- Include
> | | | | `-- SocSerDes.h
> | | | |-- LS1043A.dec
> | | | `-- LS1043A.dsc.inc
> | | |-- LS1046A
> | | | |-- Include
> | | | | `-- SocSerDes.h
> | | | |-- LS1046A.dec
> | | | `-- LS1046A.dsc.inc
> | | |-- LS2088A
> | | | |-- Include
> | | | | `-- SocSerDes.h
> | | | |-- LS2088A.dec
> | | | `-- LS2088A.dsc.inc
> | | `-- NxpQoriqLs.dec
>
>
> In Silicon/NXP, we are keeping our SoC specific information and all Drivers and Library which are used by SoCs.
>
> Platform/NXP/ will host our board packages and build script.
>
> Board specific libraries and header files will reside inside board package.
>
>
> Looking forward for your kind support in upstreaming our boards in edk2-platforms.
>
>
> Meenakshi Aggarwal (28):
> Silicon/NXP: Add Library to return Mmio APIs pointer
> Silicon/NXP : Add support for Watchdog driver
> SocLib : Add support for initialization of peripherals
> Silicon/NXP : Add support for DUART library
> Silicon/NXP: Add support for I2c driver
> Silicon/Maxim : Add support for DS1307 RTC library
> Platform/NXP: Add support for ArmPlatformLib
> Platform/NXP: Add Platform driver for LS1043 RDB board
> Compilation : Add the fdf, dsc and dec files.
> Readme : Add Readme.md file.
> IFC : Add Header file for IFC controller
> LS1043/BoardLib : Add support for LS1043 BoardLib.
> Silicon/NXP : Add support of IfcLib
> Silicon/NXP : Add support for FpgaLib.
> LS1043 : Enable support of FpgaLib.
> Silicon/NXP : Add support of NorFlashLib
> Silicon/NXP : Add NOR driver.
> LS1043 : Enable NOR driver for LS1043aRDB package.
> Silicon/NXP:Add LS1046ARDB SoCLib Support
> Platform/NXP: LS1046A RDB Board Library
> Platform/NXP: Add Platform driver for LS1046 RDB board
> Platform/NXP: Add Platform driver for LS2088 RDB board
> Compilation : Add the fdf, dsc and dec files
> LS2088 : Enable support of FpgaLib
> LS2088ARDB: Enable NOR driver and Runtime Services
> Compilation: Update the fdf, dsc and dec files.
> DWC3 : Add DWC3 USB controller initialization driver.
> LS2088 : Enable support of USB controller
>
> Vabhav (8):
> Silicon/NXP:Add support for PCF2129 Real Time Clock Library
> Platform/NXP: Add ArmPlatformLib for LS1046A
> Platform/NXP: Compilation for LS1046A RDB Board
> Silicon/NXP: Implement PciSegmentLib to support multiple RCs
> Silicon/NXP: Implement PciHostBridgeLib support
> Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
> Platform/NXP:PCIe enablement for LS1046A RDB
> Platform/NXP:PCIe enablement for LS2088A RDB
>
> Wasim Khan (5):
> Silicon/NXP:SocLib support for initialization of peripherals
> Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB
> Silicon/Maxim: DS3232 RTC Library Support
> Platform/NXP: LS2088A RDB Board Library
> Platform/NXP: LS2088 RDB Board FPGA library
>
> Platform/NXP/FVRules.fdf.inc | 99 +++
> .../Drivers/PlatformDxe/PlatformDxe.c | 119 +++
> .../Drivers/PlatformDxe/PlatformDxe.inf | 58 ++
> .../NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h | 109 +++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 29 +
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 113 +++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 212 ++++++
> .../NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c | 69 ++
> .../LS1043aRdbPkg/Library/BoardLib/BoardLib.inf | 31 +
> .../Library/PlatformLib/ArmPlatformLib.c | 105 +++
> .../Library/PlatformLib/ArmPlatformLib.inf | 69 ++
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 38 +
> .../Library/PlatformLib/NxpQoriqLsMem.c | 158 ++++
> Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 98 +++
> .../Drivers/PlatformDxe/PlatformDxe.c | 119 +++
> .../Drivers/PlatformDxe/PlatformDxe.inf | 58 ++
> .../NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h | 83 +++
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec | 29 +
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 105 +++
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 205 ++++++
> .../NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c | 61 ++
> .../LS1046aRdbPkg/Library/BoardLib/BoardLib.inf | 31 +
> .../Library/PlatformLib/ArmPlatformLib.c | 105 +++
> .../Library/PlatformLib/ArmPlatformLib.inf | 68 ++
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 35 +
> .../Library/PlatformLib/NxpQoriqLsMem.c | 158 ++++
> .../Drivers/PlatformDxe/PlatformDxe.c | 119 +++
> .../Drivers/PlatformDxe/PlatformDxe.inf | 58 ++
> .../NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h | 114 +++
> .../NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h | 166 +++++
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec | 29 +
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 130 ++++
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 224 ++++++
> .../NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c | 69 ++
> .../LS2088aRdbPkg/Library/BoardLib/BoardLib.inf | 28 +
> .../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c | 115 +++
> .../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 +
> .../Library/PlatformLib/ArmPlatformLib.c | 106 +++
> .../Library/PlatformLib/ArmPlatformLib.inf | 79 ++
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 35 +
> .../Library/PlatformLib/NxpQoriqLsMem.c | 195 +++++
> Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc | 99 +++
> Platform/NXP/NxpQoriqLs.dsc.inc | 427 +++++++++++
> Platform/NXP/Readme.md | 24 +
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h | 54 ++
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 378 ++++++++++
> .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec | 29 +
> .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf | 45 ++
> Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h | 49 ++
> Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c | 420 +++++++++++
> .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec | 34 +
> .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf | 50 ++
> Silicon/NXP/Drivers/I2cDxe/ComponentName.c | 185 +++++
> Silicon/NXP/Drivers/I2cDxe/DriverBinding.c | 241 ++++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 693 +++++++++++++++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 96 +++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 64 ++
> .../NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c | 252 +++++++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c | 503 +++++++++++++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h | 146 ++++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf | 65 ++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c | 816 +++++++++++++++++++++
> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 633 ++++++++++++++++
> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 49 ++
> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c | 218 ++++++
> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h | 144 ++++
> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf | 48 ++
> Silicon/NXP/Drivers/WatchDog/WatchDog.c | 402 ++++++++++
> Silicon/NXP/Drivers/WatchDog/WatchDog.h | 39 +
> Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf | 47 ++
> Silicon/NXP/Include/Chassis2/SerDes.h | 68 ++
> Silicon/NXP/Include/Chassis2/Soc.h | 367 +++++++++
> Silicon/NXP/Include/Chassis3/SerDes.h | 91 +++
> Silicon/NXP/Include/Chassis3/Soc.h | 143 ++++
> Silicon/NXP/Include/Ifc.h | 423 +++++++++++
> Silicon/NXP/Include/Library/FpgaLib.h | 97 +++
> Silicon/NXP/Include/Library/IfcLib.h | 26 +
> Silicon/NXP/Include/Library/IoAccessLib.h | 332 +++++++++
> Silicon/NXP/Include/Library/NorFlashLib.h | 77 ++
> Silicon/NXP/Include/NorFlash.h | 44 ++
> Silicon/NXP/Include/NxpPcie.h | 146 ++++
> Silicon/NXP/LS1043A/Include/SocSerDes.h | 57 ++
> Silicon/NXP/LS1043A/LS1043A.dec | 22 +
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 79 ++
> Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 ++
> Silicon/NXP/LS1046A/LS1046A.dec | 22 +
> Silicon/NXP/LS1046A/LS1046A.dsc.inc | 71 ++
> Silicon/NXP/LS2088A/Include/SocSerDes.h | 67 ++
> Silicon/NXP/LS2088A/LS2088A.dec | 22 +
> Silicon/NXP/LS2088A/LS2088A.dsc.inc | 76 ++
> Silicon/NXP/Library/DUartPortLib/DUart.h | 128 ++++
> Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 370 ++++++++++
> Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 41 ++
> Silicon/NXP/Library/FpgaLib/FpgaLib.c | 145 ++++
> Silicon/NXP/Library/FpgaLib/FpgaLib.inf | 34 +
> Silicon/NXP/Library/IfcLib/IfcLib.c | 150 ++++
> Silicon/NXP/Library/IfcLib/IfcLib.h | 190 +++++
> Silicon/NXP/Library/IfcLib/IfcLib.inf | 38 +
> Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 410 +++++++++++
> Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf | 32 +
> Silicon/NXP/Library/NorFlashLib/CfiCommand.h | 99 +++
> Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c | 210 ++++++
> Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h | 53 ++
> Silicon/NXP/Library/NorFlashLib/NorFlashLib.c | 696 ++++++++++++++++++
> Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf | 43 ++
> Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h | 52 ++
> Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c | 389 ++++++++++
> .../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec | 29 +
> .../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf | 47 ++
> .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 639 ++++++++++++++++
> .../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 51 ++
> Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 611 +++++++++++++++
> .../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 41 ++
> Silicon/NXP/Library/SocLib/Chassis.c | 411 +++++++++++
> Silicon/NXP/Library/SocLib/Chassis.h | 162 ++++
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 220 ++++++
> Silicon/NXP/Library/SocLib/Chassis3/Soc.c | 191 +++++
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 53 ++
> Silicon/NXP/Library/SocLib/LS1046aSocLib.inf | 53 ++
> Silicon/NXP/Library/SocLib/LS2088aSocLib.inf | 52 ++
> Silicon/NXP/Library/SocLib/SerDes.c | 274 +++++++
> Silicon/NXP/NxpQoriqLs.dec | 147 ++++
> 122 files changed, 18458 insertions(+)
> create mode 100644 Platform/NXP/FVRules.fdf.inc
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
> create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
> create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
> create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
> create mode 100755 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
> create mode 100644 Platform/NXP/NxpQoriqLs.dsc.inc
> create mode 100644 Platform/NXP/Readme.md
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/ComponentName.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c
> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
> create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
> create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> create mode 100644 Silicon/NXP/Include/Chassis2/SerDes.h
> create mode 100644 Silicon/NXP/Include/Chassis2/Soc.h
> create mode 100644 Silicon/NXP/Include/Chassis3/SerDes.h
> create mode 100644 Silicon/NXP/Include/Chassis3/Soc.h
> create mode 100644 Silicon/NXP/Include/Ifc.h
> create mode 100644 Silicon/NXP/Include/Library/FpgaLib.h
> create mode 100644 Silicon/NXP/Include/Library/IfcLib.h
> create mode 100644 Silicon/NXP/Include/Library/IoAccessLib.h
> create mode 100644 Silicon/NXP/Include/Library/NorFlashLib.h
> create mode 100644 Silicon/NXP/Include/NorFlash.h
> create mode 100644 Silicon/NXP/Include/NxpPcie.h
> create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
> create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc.inc
> create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
> create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc.inc
> create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/LS2088A/LS2088A.dec
> create mode 100644 Silicon/NXP/LS2088A/LS2088A.dsc.inc
> create mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
> create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> create mode 100644 Silicon/NXP/Library/FpgaLib/FpgaLib.c
> create mode 100644 Silicon/NXP/Library/FpgaLib/FpgaLib.inf
> create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.c
> create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.h
> create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.inf
> create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiCommand.h
> create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
> create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
> create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
> create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
> create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec
> create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
> create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> create mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
> create mode 100644 Silicon/NXP/Library/SocLib/Chassis.h
> create mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> create mode 100644 Silicon/NXP/Library/SocLib/Chassis3/Soc.c
> create mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> create mode 100644 Silicon/NXP/Library/SocLib/LS1046aSocLib.inf
> create mode 100644 Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
> create mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
> create mode 100644 Silicon/NXP/NxpQoriqLs.dec
>
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 02/41] Silicon/NXP : Add support for Watchdog driver
2018-11-28 15:01 ` [PATCH edk2-platforms 02/41] Silicon/NXP : Add support for Watchdog driver Meenakshi Aggarwal
@ 2018-12-17 17:36 ` Leif Lindholm
2019-01-29 5:32 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-12-17 17:36 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
Starting with this one, since that was the biggest pain point last
time around.
On Wed, Nov 28, 2018 at 08:31:16PM +0530, Meenakshi Aggarwal wrote:
> Installs watchdog timer arch protocol
As per the email I just cc:d you on: unless the hardware supports
configuration in a mode where it could be used for a compliant
EFI_WATCHDOG_TIMER_ARCH_PROTOCOL (i.e., trigger a software event
rather than a hardware reset), please rewrite this driver such
that it does not register as that protocol.
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Drivers/WatchDog/WatchDog.c | 402 +++++++++++++++++++++++++++
> Silicon/NXP/Drivers/WatchDog/WatchDog.h | 39 +++
> Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf | 47 ++++
> 3 files changed, 488 insertions(+)
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
I would appreciate if you could follow
https://github.com/tianocore/tianocore.github.io/wiki/Laszlo's-unkempt-git-guide-for-edk2-contributors-and-maintainers#contrib-23
when submitting the next revision. It greatly assists with reviewing.
> diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.c b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
> new file mode 100644
> index 0000000..1b1a3b5
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
> @@ -0,0 +1,402 @@
> +/** WatchDog.c
> +*
> +* Based on Watchdog driver implemenation available in
> +* ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c
> +*
> +* Copyright 2017 NXP
May want to change this to 2017-2018
Also, format should be
Copyright (c) ... NXP. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <PiDxe.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Protocol/WatchdogTimer.h>
> +
> +#include "WatchDog.h"
> +
> +STATIC EFI_EVENT EfiExitBootServicesEvent;
> +STATIC EFI_EVENT WdogFeedEvent;
m-prefix for both above please.
Can you do a search-and-replace Wdog -> Watchdog and WDOG -> WATCHDOG
please?
> +STATIC MMIO_OPERATIONS_16 *mMmioOps;
> +
> +
> +STATIC
> +VOID
> +WdogPing (
> + VOID
> + )
> +{
> + //
> + // To reload a timeout value to the counter the proper service sequence begins by
> + // writing 0x_5555 followed by 0x_AAAA to the Watchdog Service Register (WDOG_WSR).
> + // This service sequence will reload the counter with the timeout value WT[7:0] of
> + // Watchdog Control Register (WDOG_WCR).
> + //
> +
> + mMmioOps->Write (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WSR_OFFSET,
> + WDOG_SERVICE_SEQ1);
The memory access operations really need to encode size.
I would strongly prefer mMmioOps->Write16.
You could also tidy the call sites up with something like
#define WATCHDOG_ADDRESS(register) (PcdGet64 (PcdWdog1BaseAddr), WATCHDOG_ ## register ## _OFFSET)
So the invocation becomes
mMmioOps->Write16 (WATCHDOG_ADDRESS (WSR), WATCHDOG_SERVICE_SEQ1);
> + mMmioOps->Write (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WSR_OFFSET,
> + WDOG_SERVICE_SEQ2);
> +}
> +
> +/**
> + Stop the Wdog watchdog timer from counting down.
> +**/
> +STATIC
> +VOID
> +WdogStop (
> + VOID
> + )
> +{
> + // Watchdog cannot be disabled by software once started.
> + // At best, we can keep reload counter with maximum value
> +
> + mMmioOps->AndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
> + (UINT16)(~WDOG_WCR_WT),
> + (WD_COUNT (WT_MAX_TIME) & WD_COUNT_MASK));
> + WdogPing ();
> +}
> +
> +/**
> + Starts the Wdog counting down by feeding Service register with
> + desired pattern.
> + The count down will start from the value stored in the Load register,
> + not from the value where it was previously stopped.
> +**/
> +STATIC
> +VOID
> +WdogStart (
> + VOID
> + )
> +{
> + //Reload the timeout value
> + WdogPing ();
> +}
> +
> +/**
> + On exiting boot services we must make sure the Wdog Watchdog Timer
> + is stopped.
> +**/
> +STATIC
> +VOID
> +EFIAPI
> +ExitBootServicesEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + WdogStop ();
> +}
> +
> +/**
> + This function registers the handler NotifyFunction so it is called every time
> + the watchdog timer expires. It also passes the amount of time since the last
> + handler call to the NotifyFunction.
> + If NotifyFunction is not NULL and a handler is not already registered,
> + then the new handler is registered and EFI_SUCCESS is returned.
> + If NotifyFunction is NULL, and a handler is already registered,
> + then that handler is unregistered.
> + If an attempt is made to register a handler when a handler is already registered,
> + then EFI_ALREADY_STARTED is returned.
> + If an attempt is made to unregister a handler when a handler is not registered,
> + then EFI_INVALID_PARAMETER is returned.
> +
> + @param This The EFI_TIMER_ARCH_PROTOCOL instance.
> + @param NotifyFunction The function to call when a timer interrupt fires. This
> + function executes at TPL_HIGH_LEVEL. The DXE Core will
> + register a handler for the timer interrupt, so it can know
> + how much time has passed. This information is used to
> + signal timer based events. NULL will unregister the handler.
> +
> + @retval EFI_SUCCESS The watchdog timer handler was registered.
> + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
> + registered.
> + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
> + previously registered.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +WdogRegisterHandler (
> + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
> + IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
> + )
> +{
> + // ERROR: This function is not supported.
> + // The hardware watchdog will reset the board
> + return EFI_INVALID_PARAMETER;
> +}
> +
> +/**
> +
> + This function adjusts the period of timer interrupts to the value specified
> + by TimerPeriod. If the timer period is updated, then the selected timer
> + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
> + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
> + If an error occurs while attempting to update the timer period, then the
> + timer hardware will be put back in its state prior to this call, and
> + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
> + is disabled. This is not the same as disabling the CPU's interrupts.
> + Instead, it must either turn off the timer hardware, or it must adjust the
> + interrupt controller so that a CPU interrupt is not generated when the timer
> + interrupt fires.
> +
> + @param This The EFI_TIMER_ARCH_PROTOCOL instance.
> + @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
> + the timer hardware is not programmable, then EFI_UNSUPPORTED is
> + returned. If the timer is programmable, then the timer period
> + will be rounded up to the nearest timer period that is supported
> + by the timer hardware. If TimerPeriod is set to 0, then the
> + timer interrupts will be disabled.
> +
> +
> + @retval EFI_SUCCESS The timer period was changed.
> + @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
> + @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +WdogSetTimerPeriod (
> + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
> + IN UINT64 TimerPeriod // In 100ns units
> + )
> +{
> + EFI_STATUS Status;
> + UINT64 TimerPeriodInSec;
> + UINT16 Val;
> +
> + Status = EFI_SUCCESS;
> +
> + if (TimerPeriod == 0) {
> + // This is a watchdog stop request
> + WdogStop ();
> + return Status;
> + } else {
> + // Convert the TimerPeriod (in 100 ns unit) to an equivalent second value
> +
> + TimerPeriodInSec = DivU64x32 (TimerPeriod, NANO_SECOND_BASE);
> +
> + // The registers in the Wdog are only 32 bits
> + if (TimerPeriodInSec > WT_MAX_TIME) {
> + // We could load the watchdog with the maximum supported value but
> + // if a smaller value was requested, this could have the watchdog
> + // triggering before it was intended.
> + // Better generate an error to let the caller know.
> + Status = EFI_DEVICE_ERROR;
> + return Status;
> + }
> +
> + // set the new timeout value in the WCR
> + // Convert the timeout value from Seconds to timer count
> + Val = ((WD_COUNT(TimerPeriodInSec) & WD_COUNT_MASK) << 8);
> +
> + mMmioOps->AndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
> + (UINT16)(~WDOG_WCR_WT),
> + Val);
> + // Start the watchdog
> + WdogStart ();
> + }
> +
> + return Status;
> +}
> +
> +/**
> + This function retrieves the period of timer interrupts in 100 ns units,
> + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
> + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
> + returned, then the timer is currently disabled.
> +
> + @param This The EFI_TIMER_ARCH_PROTOCOL instance.
> + @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
> + 0 is returned, then the timer is currently disabled.
> +
> +
> + @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
> + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +WdogGetTimerPeriod (
> + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
> + OUT UINT64 *TimerPeriod
> + )
> +{
> + EFI_STATUS Status;
> + UINT64 ReturnValue;
> + UINT16 Val;
> +
> + Status = EFI_SUCCESS;
> +
> + if (TimerPeriod == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Check if the watchdog is stopped
> + if ((mMmioOps->Read (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET)
> + & WDOG_WCR_WDE) == 0 ) {
> + // It is stopped, so return zero.
> + ReturnValue = 0;
> + } else {
> + // Convert the Watchdog ticks into equivalent TimerPeriod second value.
> + Val = (mMmioOps->Read (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET)
> + & WDOG_WCR_WT ) >> 8;
> + ReturnValue = WD_SEC(Val);
> + }
> +
> + *TimerPeriod = ReturnValue;
> + return Status;
> +}
> +
> +/**
> + Interface structure for the Watchdog Architectural Protocol.
> +
> + @par Protocol Description:
> + This protocol provides a service to set the amount of time to wait
> + before firing the watchdog timer, and it also provides a service to
> + register a handler that is invoked when the watchdog timer fires.
> +
> + @par When the watchdog timer fires, control will be passed to a handler
> + if one has been registered. If no handler has been registered,
> + or the registered handler returns, then the system will be
> + reset by calling the Runtime Service ResetSystem().
> +
> + @param RegisterHandler
> + Registers a handler that will be called each time the
> + watchdogtimer interrupt fires. TimerPeriod defines the minimum
> + time between timer interrupts, so TimerPeriod will also
> + be the minimum time between calls to the registered
> + handler.
> + NOTE: If the watchdog resets the system in hardware, then
> + this function will not have any chance of executing.
> +
> + @param SetTimerPeriod
> + Sets the period of the timer interrupt in 100 nS units.
> + This function is optional, and may return EFI_UNSUPPORTED.
> + If this function is supported, then the timer period will
> + be rounded up to the nearest supported timer period.
> +
> + @param GetTimerPeriod
> + Retrieves the period of the timer interrupt in 100 nS units.
> +
> +**/
> +STATIC
> +EFI_WATCHDOG_TIMER_ARCH_PROTOCOL gWatchdogTimer = {
g implies global (as in visible to all modules). Please use 'm' for
module-local globals.
> + WdogRegisterHandler,
> + WdogSetTimerPeriod,
> + WdogGetTimerPeriod
> +};
> +
> +/**
> + Call back function when the timer event is signaled.
> + This function will feed the watchdog with maximum value
> + so that system wont reset in idle case e.g. stopped on UEFI shell.
> +
> + @param[in] Event The Event this notify function registered to.
> + @param[in] Context Pointer to the context data registered to the
> + Event.
> +
> +**/
> +VOID
> +EFIAPI
> +WdogFeed (
> + IN EFI_EVENT Event,
> + IN VOID* Context
> + )
> +{
> + WdogPing();
> +}
> +/**
> + Initialize state information for the Watchdog Timer Architectural Protocol.
> +
> + @param ImageHandle of the loaded driver
> + @param SystemTable Pointer to the System Table
> +
> + @retval EFI_SUCCESS Protocol registered
> + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
> + @retval EFI_DEVICE_ERROR Hardware problems
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +WdogInitialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE Handle;
> +
> + mMmioOps = GetMmioOperations16 (FixedPcdGetBool (PcdWdogBigEndian));
> +
> + mMmioOps->AndThenOr (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
> + (UINT16)(~WDOG_WCR_WT),
> + (WD_COUNT (WT_MAX_TIME) & WD_COUNT_MASK));
> +
> + mMmioOps->Or (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET, WDOG_WCR_WDE);
> +
> + //
> + // Make sure the Watchdog Timer Architectural Protocol
> + // has not been installed in the system yet.
> + // This will avoid conflicts with the universal watchdog
> + //
> + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid);
> +
> + // Register for an ExitBootServicesEvent
> + Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,
> + ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
> + if (EFI_ERROR (Status)) {
> + Status = EFI_OUT_OF_RESOURCES;
> + return Status;
> + }
> +
> + //
> + // Start the timer to feed Watchdog with maximum timeout value.
> + //
> + Status = gBS->CreateEvent (
> + EVT_TIMER | EVT_NOTIFY_SIGNAL,
> + TPL_NOTIFY,
> + WdogFeed,
> + NULL,
> + &WdogFeedEvent
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + Status = gBS->SetTimer (WdogFeedEvent, TimerPeriodic, WT_FEED_INTERVAL);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + // Install the Timer Architectural Protocol onto a new handle
> + Handle = NULL;
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &Handle,
> + &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer,
> + NULL
> + );
> + if (EFI_ERROR (Status)) {
> + gBS->CloseEvent (EfiExitBootServicesEvent);
> + Status = EFI_OUT_OF_RESOURCES;
> + return Status;
> + }
> +
> + WdogPing ();
> +
> + return Status;
> +}
> diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.h b/Silicon/NXP/Drivers/WatchDog/WatchDog.h
> new file mode 100644
> index 0000000..9542608
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.h
> @@ -0,0 +1,39 @@
> +/** WatchDog.h
> +*
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __WATCHDOG_H__
> +#define __WATCHDOG_H__
> +
> +#define WDOG_SIZE 0x1000
> +#define WDOG_WCR_OFFSET 0
> +#define WDOG_WSR_OFFSET 2
> +#define WDOG_WRSR_OFFSET 4
> +#define WDOG_WICR_OFFSET 6
> +#define WDOG_WCR_WT (0xFF << 8)
> +#define WDOG_WCR_WDE (1 << 2)
> +#define WDOG_SERVICE_SEQ1 0x5555
> +#define WDOG_SERVICE_SEQ2 0xAAAA
> +#define WDOG_WCR_WDZST 0x1
> +#define WDOG_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
> +
> +#define WT_MAX_TIME 128
WT?
> +#define WD_COUNT(Sec) (((Sec) * 2 - 1) << 8)
> +#define WD_COUNT_MASK 0xff00
> +#define WD_SEC(Cnt) (((Cnt) + 1) / 2)
WD?
/
Leif
> +
> +#define NANO_SECOND_BASE 10000000
> +
> +#define WT_FEED_INTERVAL (WT_MAX_TIME * NANO_SECOND_BASE)
> +
> +#endif //__WATCHDOG_H__
> diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf b/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> new file mode 100644
> index 0000000..a311bdc
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> @@ -0,0 +1,47 @@
> +# WatchDog.inf
> +#
> +# Component description file for WatchDog module
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = WatchDogDxe
> + FILE_GUID = 0358b544-ec65-4339-89cd-cad60a3dd787
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = WdogInitialize
> +
> +[Sources.common]
> + WatchDog.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + IoAccessLib
> + PcdLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian
> +
> +[Protocols]
> + gEfiWatchdogTimerArchProtocolGuid
> +
> +[Depex]
> + TRUE
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 03/41] SocLib : Add support for initialization of peripherals
2018-11-28 15:01 ` [PATCH edk2-platforms 03/41] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
@ 2018-12-18 12:31 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-18 12:31 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Wed, Nov 28, 2018 at 08:31:17PM +0530, Meenakshi Aggarwal wrote:
> Add SocInit function that initializes peripherals
> and print board and soc information.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/Chassis2/SerDes.h | 68 +++++
> Silicon/NXP/Include/Chassis2/Soc.h | 367 ++++++++++++++++++++++++++
> Silicon/NXP/LS1043A/Include/SocSerDes.h | 57 ++++
> Silicon/NXP/Library/SocLib/Chassis.c | 372 +++++++++++++++++++++++++++
> Silicon/NXP/Library/SocLib/Chassis.h | 144 +++++++++++
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 167 ++++++++++++
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 49 ++++
> Silicon/NXP/Library/SocLib/SerDes.c | 271 +++++++++++++++++++
> 8 files changed, 1495 insertions(+)
> create mode 100644 Silicon/NXP/Include/Chassis2/SerDes.h
> create mode 100644 Silicon/NXP/Include/Chassis2/Soc.h
> create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
> create mode 100644 Silicon/NXP/Library/SocLib/Chassis.h
> create mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> create mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> create mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
>
> diff --git a/Silicon/NXP/Include/Chassis2/SerDes.h b/Silicon/NXP/Include/Chassis2/SerDes.h
> new file mode 100644
> index 0000000..4c874aa
> --- /dev/null
> +++ b/Silicon/NXP/Include/Chassis2/SerDes.h
> @@ -0,0 +1,68 @@
> +/** SerDes.h
> + The Header file of SerDes Module for Chassis 2
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __SERDES_H__
> +#define __SERDES_H__
SERDES is a bit too generic. Please add an NXP_ prefix, or more if you
can come up with something that pins it down to the group of users of
this header (QORIQ?).
> +
> +#include <Uefi/UefiBaseType.h>
> +
> +#define SRDS_MAX_LANES 4
> +
> +typedef enum {
> + NONE = 0,
> + PCIE1,
> + PCIE2,
> + PCIE3,
> + SATA,
> + SGMII_FM1_DTSEC1,
> + SGMII_FM1_DTSEC2,
> + SGMII_FM1_DTSEC5,
> + SGMII_FM1_DTSEC6,
> + SGMII_FM1_DTSEC9,
> + SGMII_FM1_DTSEC10,
> + QSGMII_FM1_A,
> + XFI_FM1_MAC9,
> + XFI_FM1_MAC10,
> + SGMII_2500_FM1_DTSEC2,
> + SGMII_2500_FM1_DTSEC5,
> + SGMII_2500_FM1_DTSEC9,
> + SGMII_2500_FM1_DTSEC10,
> + SERDES_PRTCL_COUNT
As per
https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/5_source_files/56_declarations_and_types.html#5622-enumerated-types
please rename enum members to CamelCase. (Please apply throughout set.)
Yes, I missed this in my previous review - apologies for that.
> +} SERDES_PROTOCOL;
> +
> +typedef enum {
> + SRDS_1 = 0,
> + SRDS_2,
> + SRDS_MAX_NUM
> +} SERDES_NUMBER;
> +
> +typedef struct {
> + UINT16 Protocol;
> + UINT8 SrdsLane[SRDS_MAX_LANES];
> +} SERDES_CONFIG;
> +
> +typedef VOID
> +(*SERDES_PROBE_LANES_CALLBACK) (
> + IN SERDES_PROTOCOL LaneProtocol,
> + IN VOID *Arg
> + );
> +
> +VOID
> +SerDesProbeLanes(
> + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> + IN VOID *Arg
> + );
> +
> +#endif /* __SERDES_H */
> diff --git a/Silicon/NXP/Include/Chassis2/Soc.h b/Silicon/NXP/Include/Chassis2/Soc.h
> new file mode 100644
> index 0000000..10e99ab
> --- /dev/null
> +++ b/Silicon/NXP/Include/Chassis2/Soc.h
> @@ -0,0 +1,367 @@
> +/** Soc.h
> +* Header defining the Base addresses, sizes, flags etc for chassis 1
> +*
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __SOC_H__
> +#define __SOC_H__
NXP_PREFIX please.
> +
> +#define HWA_CGA_M1_CLK_SEL 0xe0000000
> +#define HWA_CGA_M1_CLK_SHIFT 29
> +
> +#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
> +#define NUM_CC_PLLS 2
> +#define CLK_FREQ 100000000
> +#define MAX_CPUS 4
> +#define NUM_FMAN 1
> +#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
> +
> +/* RCW SERDES MACRO */
> +#define RCWSR_INDEX 4
> +#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
> +#define RCWSR_SRDS1_PRTCL_SHIFT 16
> +#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
> +#define RCWSR_SRDS2_PRTCL_SHIFT 0
> +
> +/* SMMU Defintions */
> +#define SMMU_BASE_ADDR 0x09000000
> +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> +
> +#define SCR0_USFCFG_MASK 0x00000400
> +#define SCR0_CLIENTPD_MASK 0x00000001
> +#define SACR_PAGESIZE_MASK 0x00010000
> +#define IDR1_PAGESIZE_MASK 0x80000000
> +
> +typedef struct {
> + UINTN FreqProcessor[MAX_CPUS];
> + UINTN FreqSystemBus;
> + UINTN FreqDdrBus;
> + UINTN FreqLocalBus;
> + UINTN FreqSdhc;
> + UINTN FreqFman[NUM_FMAN];
> + UINTN FreqQman;
> +} SYS_INFO;
> +
> +/* Device Configuration and Pin Control */
> +typedef struct {
> + UINT32 PorSr1; /* POR status 1 */
> +#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
> + UINT32 PorSr2; /* POR status 2 */
> + UINT8 Res008[0x20-0x8];
> + UINT32 GppOrCr1; /* General-purpose POR configuration */
> + UINT32 GppOrCr2;
> + UINT32 DcfgFuseSr; /* Fuse status register */
> + UINT8 Res02c[0x70-0x2c];
> + UINT32 DevDisr; /* Device disable control */
> + UINT32 DevDisr2; /* Device disable control 2 */
> + UINT32 DevDisr3; /* Device disable control 3 */
> + UINT32 DevDisr4; /* Device disable control 4 */
> + UINT32 DevDisr5; /* Device disable control 5 */
> + UINT32 DevDisr6; /* Device disable control 6 */
> + UINT32 DevDisr7; /* Device disable control 7 */
> + UINT8 Res08c[0x94-0x8c];
> + UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
> + UINT32 CoreDisrL; /* lower portion for support of 64 cores */
> + UINT8 Res09c[0xa0-0x9c];
> + UINT32 Pvr; /* Processor version */
> + UINT32 Svr; /* System version */
> + UINT32 Mvr; /* Manufacturing version */
> + UINT8 Res0ac[0xb0-0xac];
> + UINT32 RstCr; /* Reset control */
> + UINT32 RstRqPblSr; /* Reset request preboot loader status */
> + UINT8 Res0b8[0xc0-0xb8];
> + UINT32 RstRqMr1; /* Reset request mask */
> + UINT8 Res0c4[0xc8-0xc4];
> + UINT32 RstRqSr1; /* Reset request status */
> + UINT8 Res0cc[0xd4-0xcc];
> + UINT32 RstRqWdTmrL; /* Reset request WDT mask */
> + UINT8 Res0d8[0xdc-0xd8];
> + UINT32 RstRqWdtSrL; /* Reset request WDT status */
> + UINT8 Res0e0[0xe4-0xe0];
> + UINT32 BrrL; /* Boot release */
> + UINT8 Res0e8[0x100-0xe8];
> + UINT32 RcwSr[16]; /* Reset control word status */
> +#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
> +#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
> +#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
> +#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
> + UINT8 Res140[0x200-0x140];
> + UINT32 ScratchRw[4]; /* Scratch Read/Write */
> + UINT8 Res210[0x300-0x210];
> + UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
> + UINT8 Res310[0x400-0x310];
> + UINT32 CrstSr[12];
> + UINT8 Res430[0x500-0x430];
> + /* PCI Express n Logical I/O Device Number register */
> + UINT32 DcfgCcsrPex1LiodNr;
> + UINT32 DcfgCcsrPex2LiodNr;
> + UINT32 DcfgCcsrPex3LiodNr;
> + UINT32 DcfgCcsrPex4LiodNr;
> + /* RIO n Logical I/O Device Number register */
> + UINT32 DcfgCcsrRio1LiodNr;
> + UINT32 DcfgCcsrRio2LiodNr;
> + UINT32 DcfgCcsrRio3LiodNr;
> + UINT32 DcfgCcsrRio4LiodNr;
> + /* USB Logical I/O Device Number register */
> + UINT32 DcfgCcsrUsb1LiodNr;
> + UINT32 DcfgCcsrUsb2LiodNr;
> + UINT32 DcfgCcsrUsb3LiodNr;
> + UINT32 DcfgCcsrUsb4LiodNr;
> + /* SD/MMC Logical I/O Device Number register */
> + UINT32 DcfgCcsrSdMmc1LiodNr;
> + UINT32 DcfgCcsrSdMmc2LiodNr;
> + UINT32 DcfgCcsrSdMmc3LiodNr;
> + UINT32 DcfgCcsrSdMmc4LiodNr;
> + /* RIO Message Unit Logical I/O Device Number register */
> + UINT32 DcfgCcsrRiomaintLiodNr;
> + UINT8 Res544[0x550-0x544];
> + UINT32 SataLiodNr[4];
> + UINT8 Res560[0x570-0x560];
> + UINT32 DcfgCcsrMisc1LiodNr;
> + UINT32 DcfgCcsrMisc2LiodNr;
> + UINT32 DcfgCcsrMisc3LiodNr;
> + UINT32 DcfgCcsrMisc4LiodNr;
> + UINT32 DcfgCcsrDma1LiodNr;
> + UINT32 DcfgCcsrDma2LiodNr;
> + UINT32 DcfgCcsrDma3LiodNr;
> + UINT32 DcfgCcsrDma4LiodNr;
> + UINT32 DcfgCcsrSpare1LiodNr;
> + UINT32 DcfgCcsrSpare2LiodNr;
> + UINT32 DcfgCcsrSpare3LiodNr;
> + UINT32 DcfgCcsrSpare4LiodNr;
> + UINT8 Res5a0[0x600-0x5a0];
> + UINT32 DcfgCcsrPblSr;
> + UINT32 PamuBypENr;
> + UINT32 DmaCr1;
> + UINT8 Res60c[0x610-0x60c];
> + UINT32 DcfgCcsrGenSr1;
> + UINT32 DcfgCcsrGenSr2;
> + UINT32 DcfgCcsrGenSr3;
> + UINT32 DcfgCcsrGenSr4;
> + UINT32 DcfgCcsrGenCr1;
> + UINT32 DcfgCcsrGenCr2;
> + UINT32 DcfgCcsrGenCr3;
> + UINT32 DcfgCcsrGenCr4;
> + UINT32 DcfgCcsrGenCr5;
> + UINT32 DcfgCcsrGenCr6;
> + UINT32 DcfgCcsrGenCr7;
> + UINT8 Res63c[0x658-0x63c];
> + UINT32 DcfgCcsrcGenSr1;
> + UINT32 DcfgCcsrcGenSr0;
> + UINT8 Res660[0x678-0x660];
> + UINT32 DcfgCcsrcGenCr1;
> + UINT32 DcfgCcsrcGenCr0;
> + UINT8 Res680[0x700-0x680];
> + UINT32 DcfgCcsrSrIoPstecr;
> + UINT32 DcfgCcsrDcsrCr;
> + UINT8 Res708[0x740-0x708]; /* add more registers when needed */
> + UINT32 TpItyp[64]; /* Topology Initiator Type Register */
> + struct {
> + UINT32 Upper;
> + UINT32 Lower;
> + } TpCluster[16];
> + UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
> + UINT32 DcfgCcsrQmBmWarmRst;
> + UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
> + UINT32 DcfgCcsrReserved0;
> + UINT32 DcfgCcsrReserved1;
> +} CCSR_GUR;
> +
> +/* Supplemental Configuration Unit */
> +typedef struct {
> + UINT8 Res000[0x070-0x000];
> + UINT32 Usb1Prm1Cr;
> + UINT32 Usb1Prm2Cr;
> + UINT32 Usb1Prm3Cr;
> + UINT32 Usb2Prm1Cr;
> + UINT32 Usb2Prm2Cr;
> + UINT32 Usb2Prm3Cr;
> + UINT32 Usb3Prm1Cr;
> + UINT32 Usb3Prm2Cr;
> + UINT32 Usb3Prm3Cr;
> + UINT8 Res094[0x100-0x094];
> + UINT32 Usb2Icid;
> + UINT32 Usb3Icid;
> + UINT8 Res108[0x114-0x108];
> + UINT32 DmaIcid;
> + UINT32 SataIcid;
> + UINT32 Usb1Icid;
> + UINT32 QeIcid;
> + UINT32 SdhcIcid;
> + UINT32 EdmaIcid;
> + UINT32 EtrIcid;
> + UINT32 Core0SftRst;
> + UINT32 Core1SftRst;
> + UINT32 Core2SftRst;
> + UINT32 Core3SftRst;
> + UINT8 Res140[0x158-0x140];
> + UINT32 AltCBar;
> + UINT32 QspiCfg;
> + UINT8 Res160[0x180-0x160];
> + UINT32 DmaMcr;
> + UINT8 Res184[0x188-0x184];
> + UINT32 GicAlign;
> + UINT32 DebugIcid;
> + UINT8 Res190[0x1a4-0x190];
> + UINT32 SnpCnfGcr;
> +#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
> +#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
> +#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
> +#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
> +#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
> +#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
> +#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
> +#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
> +#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
> +#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
> + UINT8 Res1a8[0x1ac-0x1a8];
> + UINT32 IntpCr;
> + UINT8 Res1b0[0x204-0x1b0];
> + UINT32 CoreSrEnCr;
> + UINT8 Res208[0x220-0x208];
> + UINT32 RvBar00;
> + UINT32 RvBar01;
> + UINT32 RvBar10;
> + UINT32 RvBar11;
> + UINT32 RvBar20;
> + UINT32 RvBar21;
> + UINT32 RvBar30;
> + UINT32 RvBar31;
> + UINT32 LpmCsr;
> + UINT8 Res244[0x400-0x244];
> + UINT32 QspIdQScr;
> + UINT32 EcgTxcMcr;
> + UINT32 SdhcIoVSelCr;
> + UINT32 RcwPMuxCr0;
> + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> + *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> + *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
> + Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
> +#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
> + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> + *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> + *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
> + Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
> +#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
> + UINT32 UsbDrvVBusSelCr;
> +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
> +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
> +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
> + UINT32 UsbPwrFaultSelCr;
> +#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
> +#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
> +#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
> +#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
> +#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
> +#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
> + UINT32 UsbRefclkSelcr1;
> + UINT32 UsbRefclkSelcr2;
> + UINT32 UsbRefclkSelcr3;
> + UINT8 Res424[0x600-0x424];
> + UINT32 ScratchRw[4];
> + UINT8 Res610[0x680-0x610];
> + UINT32 CoreBCr;
> + UINT8 Res684[0x1000-0x684];
> + UINT32 Pex1MsiIr;
> + UINT32 Pex1MsiR;
> + UINT8 Res1008[0x2000-0x1008];
> + UINT32 Pex2;
> + UINT32 Pex2MsiR;
> + UINT8 Res2008[0x3000-0x2008];
> + UINT32 Pex3MsiIr;
> + UINT32 Pex3MsiR;
> +} CCSR_SCFG;
> +
> +#define USB_TXVREFTUNE 0x9
> +#define USB_SQRXTUNE 0xFC7FFFFF
> +#define USB_PCSTXSWINGFULL 0x47
> +#define USB_PHY_RX_EQ_VAL_1 0x0000
> +#define USB_PHY_RX_EQ_VAL_2 0x8000
> +#define USB_PHY_RX_EQ_VAL_3 0x8003
> +#define USB_PHY_RX_EQ_VAL_4 0x800b
> +
> +/*USB_PHY_SS memory map*/
> +typedef struct {
> + UINT16 IpIdcodeLo;
> + UINT16 SupIdcodeHi;
> + UINT8 Res4[0x0006-0x0004];
> + UINT16 RtuneDebug;
> + UINT16 RtuneStat;
> + UINT16 SupSsPhase;
> + UINT16 SsFreq;
> + UINT8 ResE[0x0020-0x000e];
> + UINT16 Ateovrd;
> + UINT16 MpllOvrdInLo;
> + UINT8 Res24[0x0026-0x0024];
> + UINT16 SscOvrdIn;
> + UINT8 Res28[0x002A-0x0028];
> + UINT16 LevelOvrdIn;
> + UINT8 Res2C[0x0044-0x002C];
> + UINT16 ScopeCount;
> + UINT8 Res46[0x0060-0x0046];
> + UINT16 MpllLoopCtl;
> + UINT8 Res62[0x006C-0x0062];
> + UINT16 SscClkCntrl;
> + UINT8 Res6E[0x2002-0x006E];
> + UINT16 Lane0TxOvrdInHi;
> + UINT16 Lane0TxOvrdDrvLo;
> + UINT8 Res2006[0x200C-0x2006];
> + UINT16 Lane0RxOvrdInHi;
> + UINT8 Res200E[0x2022-0x200E];
> + UINT16 Lane0TxCmWaitTimeOvrd;
> + UINT8 Res2024[0x202A-0x2024];
> + UINT16 Lane0TxLbertCtl;
> + UINT16 Lane0RxLbertCtl;
> + UINT16 Lane0RxLbertErr;
> + UINT8 Res2030[0x205A-0x2030];
> + UINT16 Lane0TxAltBlock;
> +} CCSR_USB_PHY;
> +
> +/* Clocking */
> +typedef struct {
> + struct {
> + UINT32 ClkCnCSr; /* core cluster n clock control status */
> + UINT8 Res004[0x0c];
> + UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
> + UINT8 Res014[0x0c];
> + } ClkcSr[4];
> + UINT8 Res040[0x780]; /* 0x100 */
> + struct {
> + UINT32 PllCnGSr;
> + UINT8 Res804[0x1c];
> + } PllCgSr[NUM_CC_PLLS];
> + UINT8 Res840[0x1c0];
> + UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
> + UINT8 Resa04[0x1fc];
> + UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
> + UINT8 Resc04[0x1c];
> + UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
> + UINT8 Resc24[0x3dc];
> +} CCSR_CLOCK;
> +
> +VOID
> +GetSysInfo (
> + OUT SYS_INFO *
> + );
> +
> +UINT32
> +EFIAPI
> +GurRead (
> + IN UINTN Address
> + );
> +
> +#endif /* __SOC_H__ */
> diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
> new file mode 100644
> index 0000000..7707e2a
> --- /dev/null
> +++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h
> @@ -0,0 +1,57 @@
> +/** @file
> + The Header file of SerDes Module for LS1043A
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __SOC_SERDES_H__
> +#define __SOC_SERDES_H__
> +
> +#ifdef CHASSIS2
> +#include <Chassis2/SerDes.h>
> +#endif
> +
> +SERDES_CONFIG SerDes1ConfigTbl[] = {
> + /* SerDes 1 */
> + {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3 } },
> + {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
> + {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3 } },
> + {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA } },
> + {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
> + {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
> + {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, PCIE3 } },
> + {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3 } },
> + {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA } },
> + {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3 } },
> + {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA } },
> + {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1 } },
> + {0x9998, {PCIE1, PCIE2, PCIE3, SATA } },
> + {0x6058, {PCIE1, PCIE1, PCIE2, SATA } },
> + {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
> + {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
> + {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3 } },
> + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {0x1460, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
> + {0x2460, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
> + {0x3460, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE3, PCIE3 } },
> + {0x3455, {SGMII_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3 } },
> + {0x9960, {PCIE1, PCIE2, PCIE3, PCIE3 } },
> + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {0x2533, {SGMII_2500_FM1_DTSEC9, PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {}
> +};
> +
> +SERDES_CONFIG *SerDesConfigTbl[] = {
> + SerDes1ConfigTbl
> +};
> +
> +#endif /* __SOC_SERDES_H */
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> new file mode 100644
> index 0000000..851174c
> --- /dev/null
> +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> @@ -0,0 +1,372 @@
> +/** @file
> + SoC specific Library containg functions to initialize various SoC components
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#ifdef CHASSIS2
> +#include <Chassis2/Soc.h>
> +#endif
> +#include <Library/BaseLib.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +#include "Chassis.h"
> +
> +UINT32
> +EFIAPI
> +GurRead (
> + IN UINTN Address
> + )
> +{
> + if (FixedPcdGetBool (PcdGurBigEndian)) {
> + return SwapMmioRead32 (Address);
> + } else {
> + return MmioRead32 (Address);
> + }
> +}
> +
> +/*
> + * Structure to list available SOCs.
> + */
> +STATIC CPU_TYPE CpuTypeList[] = {
STATIC global variables need an m-prefix:
https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/4_naming_conventions/43_identifiers.html#4332-any-variable-with-file-scope-or-better-shall-be-prefixed-by-an-m-or-g
> + CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
Please put a comment near here explaining at least the 4.
> +};
> +
> +/*
> + * Return the type of initiator (core or hardware accelerator)
> + */
> +UINT32
> +InitiatorType (
> + IN UINT32 Cluster,
> + IN UINTN InitId
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINT32 Idx;
> + UINT32 Type;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
> + Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
> +
> + if (Type & TP_ITYP_AV_MASK) {
> + return Type;
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * Return the mask for number of cores on this SOC.
> + */
> +UINT32
> +CpuMask (
> + VOID
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINTN ClusterIndex;
> + UINTN Count;
> + UINT32 Cluster;
> + UINT32 Type;
> + UINT32 Mask;
> + UINTN InitiatorIndex;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClusterIndex = 0;
> + Count = 0;
> + Mask = 0;
> +
> + do {
> + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> + Type = InitiatorType (Cluster, InitiatorIndex);
> + if (Type) {
> + if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) {
> + Mask |= 1 << Count;
> + }
> + Count++;
> + }
> + }
> + ClusterIndex++;
> + } while (CHECK_CLUSTER (Cluster));
> +
> + return Mask;
> +}
> +
> +/*
> + * Return the number of cores on this SOC.
> + */
> +UINTN
> +CpuNumCores (
> + VOID
> + )
> +{
> + UINTN Count;
> + UINTN Num;
> +
> + Count = 0;
> + Num = CpuMask ();
> +
> + while (Num) {
> + Count += Num & 1;
> + Num >>= 1;
> + }
> +
> + return Count;
> +}
> +
> +/*
> + * Return the type of core i.e. A53, A57 etc of inputted
> + * core number.
> + */
> +UINTN
> +QoriqCoreToType (
> + IN UINTN Core
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINTN ClusterIndex;
> + UINTN Count;
> + UINT32 Cluster;
> + UINT32 Type;
> + UINTN InitiatorIndex;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClusterIndex = 0;
> + Count = 0;
> +
> + do {
> + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> + Type = InitiatorType (Cluster, InitiatorIndex);
> + if (Type) {
> + if (Count == Core) {
> + return Type;
> + }
> + Count++;
> + }
> + }
> + ClusterIndex++;
> + } while (CHECK_CLUSTER (Cluster));
> +
> + return EFI_NOT_FOUND; /* cannot identify the cluster */
> +}
> +
> +/*
> + * Print CPU information
> + */
> +VOID
> +PrintCpuInfo (
> + VOID
> + )
> +{
> + SYS_INFO SysInfo;
> + UINTN CoreIndex;
> + UINTN Core;
> + UINT32 Type;
> + CHAR8 Buffer[50];
Unless something non-obvious is going on here, you shouldn't need a
buffer here (which helps get around the bit where I'm ask you to get
rid of the statically sized array).
If you do:
CHAR8 *CoreName;
> +
> + GetSysInfo (&SysInfo);
> + DEBUG ((DEBUG_INIT, "Clock Configuration:"));
> +
> + ForEachCpu (CoreIndex, Core, CpuNumCores (), CpuMask ()) {
> + if (!(CoreIndex % 3)) {
> + DEBUG ((DEBUG_INIT, "\n "));
> + }
> +
> + Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
> + switch (Type) {
> + case TY_ITYP_VERSION_A7:
> + AsciiStrCpy (Buffer, "A7");
Then you can replace this copy with
CoreName = "A7";
and so on
(And if something non-obvious is going on, please add a comment
describing it.)
> + break;
> + case TY_ITYP_VERSION_A53:
> + AsciiStrCpy (Buffer, "A53");
> + break;
> + case TY_ITYP_VERSION_A57:
> + AsciiStrCpy (Buffer, "A57");
> + break;
> + case TY_ITYP_VERSION_A72:
> + AsciiStrCpy (Buffer, "A72");
> + break;
> + default:
> + AsciiStrCpy (Buffer, " Unknown Core ");
> + }
> + DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ", Core, Buffer, SysInfo.FreqProcessor[Core] / MHZ));
> + }
> +
> + DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ));
> + DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ));
> +
> + if (SysInfo.FreqFman[0] != 0) {
> + DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ));
> + }
> +
> + DEBUG ((DEBUG_INIT, "\n"));
> +}
> +
> +/*
> + * Return system bus frequency
> + */
> +UINT64
> +GetBusFrequency (
> + VOID
> + )
> +{
> + SYS_INFO SocSysInfo;
> +
> + GetSysInfo (&SocSysInfo);
> +
> + return SocSysInfo.FreqSystemBus;
> +}
> +
> +/*
> + * Return SDXC bus frequency
> + */
> +UINT64
> +GetSdxcFrequency (
> + VOID
> + )
> +{
> + SYS_INFO SocSysInfo;
> +
> + GetSysInfo (&SocSysInfo);
> +
> + return SocSysInfo.FreqSdhc;
> +}
> +
> +/*
> + * Print Soc information
> + */
> +VOID
> +PrintSoc (
> + VOID
> + )
> +{
> + CHAR8 Buf[16];
> + CCSR_GUR *GurBase;
> + UINTN Count;
> + UINTN Svr;
Can you expand this name to make it clear what it refers to?
> + UINTN Ver;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> +
> + Buf[0] = L'\0';
This seems unneeded. StrCat is only ever called after
> + Svr = GurRead ((UINTN)&GurBase->Svr);
> + Ver = SVR_SOC_VER (Svr);
> +
> + for (Count = 0; Count < ARRAY_SIZE (CpuTypeList); Count++)
Missing {
> + if ((CpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
> + AsciiStrCpy (Buf, (CONST CHAR8 *)CpuTypeList[Count].Name);
I may be willing to overlook the statically sized buffer above, but if
so, all of the String manipulation calls must use the sized versions:
AsciiStrCpyS
> +
> + if (IS_E_PROCESSOR (Svr)) {
> + AsciiStrCat (Buf, (CONST CHAR8 *)"E");
AsciiStrCatS
> + }
> + break;
> + }
Missing }
> +
> + if (Count == ARRAY_SIZE (CpuTypeList)) {
> + AsciiStrCpy (Buf, (CONST CHAR8 *)"unknown");
AsciiStrCpyS
> + }
> +
> + DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
> + Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
> +
> + return;
> +}
> +
> +/*
> + * Dump RCW (Reset Control Word) on console
> + */
> +VOID
> +PrintRCW (
> + VOID
> + )
> +{
> + CCSR_GUR *Base;
> + UINTN Count;
> +
> + Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> +
> + /*
> + * Display the RCW, so that no one gets confused as to what RCW
> + * we're actually using for this boot.
> + */
> +
> + DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):"));
> + for (Count = 0; Count < ARRAY_SIZE(Base->RcwSr); Count++) {
> + UINT32 Rcw = SwapMmioRead32((UINTN)&Base->RcwSr[Count]);
> +
> + if ((Count % 4) == 0) {
> + DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4));
> + }
> +
> + DEBUG ((DEBUG_INIT, " %08x", Rcw));
> + }
> +
> + DEBUG ((DEBUG_INIT, "\n"));
> +}
> +
> +/*
> + * Setup SMMU in bypass mode
> + * and also set its pagesize
> + */
> +VOID
> +SmmuInit (
> + VOID
> + )
> +{
> + UINT32 Value;
> +
> + /* set pagesize as 64K and ssmu-500 in bypass mode */
> + Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> +
> + Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> +
> + Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> +}
> +
> +/*
> + * Return current Soc Name form CpuTypeList
> + */
> +CHAR8 *
> +GetSocName (
> + VOID
> + )
> +{
> + UINT8 Count;
> + UINTN Svr;
> + UINTN Ver;
> + CCSR_GUR *GurBase;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> +
> + Svr = GurRead ((UINTN)&GurBase->Svr);
> + Ver = SVR_SOC_VER (Svr);
> +
> + for (Count = 0; Count < ARRAY_SIZE (CpuTypeList); Count++) {
> + if ((CpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
> + return (CHAR8 *)CpuTypeList[Count].Name;
> + }
> + }
> +
> + return NULL;
> +}
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.h b/Silicon/NXP/Library/SocLib/Chassis.h
> new file mode 100644
> index 0000000..5aa1209
> --- /dev/null
> +++ b/Silicon/NXP/Library/SocLib/Chassis.h
> @@ -0,0 +1,144 @@
> +/** @file
> +* Header defining the Base addresses, sizes, flags etc for chassis 1
> +*
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __CHASSIS_H__
> +#define __CHASSIS_H__
NXP_ and/or QUORIQ_ prefix?
Oh, and please drop leading _ from include guards:
https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/5_source_files/53_include_files.html#535-all-include-file-contents-must-be-protected-by-a-include-guard
> +
> +#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
> +#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
> +#define TP_ITYP_TYPE_ARM 0x0
> +#define TP_ITYP_TYPE_PPC 0x1
> +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
> +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
> +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
> +#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
> +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
> +#define TP_INIT_PER_CLUSTER 4
> +
> +#define TY_ITYP_VERSION_A7 0x1
> +#define TY_ITYP_VERSION_A53 0x2
> +#define TY_ITYP_VERSION_A57 0x3
> +#define TY_ITYP_VERSION_A72 0x4
> +
> +STATIC
> +inline
> +UINTN
> +CpuMaskNext (
https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/5_source_files/53_include_files.html#537-include-files-shall-not-generate-code-or-define-data-variables
> + IN UINTN Cpu,
> + IN UINTN Mask
> + )
> +{
> + for (Cpu++; !((1 << Cpu) & Mask); Cpu++)
> + ;
> +
> + return Cpu;
> +}
> +
> +#define ForEachCpu(Iter, Cpu, NumCpus, Mask) \
> + for (Iter = 0, Cpu = CpuMaskNext(-1, Mask); \
> + Iter < NumCpus; \
> + Iter++, Cpu = CpuMaskNext(Cpu, Mask)) \
Macros are fine, but please drop that trailing \
> +
> +#define CPU_TYPE_ENTRY(N, V, NC) \
> + { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
> +
> +#define SVR_WO_E 0xFFFFFE
> +#define SVR_LS1043A 0x879200
> +
> +#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> +#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
> +#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
> +
> +#define MHZ 1000000
> +
> +typedef struct {
> + CHAR8 Name[16];
Shouldn't need a static size, just make it a pointer.
> + UINT32 SocVer;
> + UINT32 NumCores;
> +} CPU_TYPE;
No further comments beyond this point.
Regards,
Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 05/41] Silicon/NXP: Add support for I2c driver
2018-11-28 15:01 ` [PATCH edk2-platforms 05/41] Silicon/NXP: Add support for I2c driver Meenakshi Aggarwal
@ 2018-12-18 17:25 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-18 17:25 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Wed, Nov 28, 2018 at 08:31:19PM +0530, Meenakshi Aggarwal wrote:
> I2C driver produces gEfiI2cMasterProtocolGuid which can be
> used by other modules.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Many thanks for the non-trivial rework.
A few style comments below.
> ---
> Silicon/NXP/Drivers/I2cDxe/ComponentName.c | 185 ++++++++
> Silicon/NXP/Drivers/I2cDxe/DriverBinding.c | 241 ++++++++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 693 +++++++++++++++++++++++++++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 96 ++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 64 +++
> 5 files changed, 1279 insertions(+)
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/ComponentName.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
>
> diff --git a/Silicon/NXP/Drivers/I2cDxe/ComponentName.c b/Silicon/NXP/Drivers/I2cDxe/ComponentName.c
> new file mode 100644
> index 0000000..efed6b9
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/I2cDxe/ComponentName.c
> @@ -0,0 +1,185 @@
> +/** @file
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include "I2cDxe.h"
> +
> +STATIC EFI_UNICODE_STRING_TABLE mNxpI2cDriverNameTable[] = {
> + {
> + "en",
> + (CHAR16 *)L"Nxp I2C Driver"
> + },
> + { }
> +};
> +
> +STATIC EFI_UNICODE_STRING_TABLE mNxpI2cControllerNameTable[] = {
> + {
> + "en",
> + (CHAR16 *)L"Nxp I2C Controller"
> + },
> + { }
> +};
> +
> +/**
> + Retrieves a Unicode string that is the user readable name of the driver.
> +
> + This function retrieves the user readable name of a driver in the form of a
> + Unicode string. If the driver specified by This has a user readable name in
> + the language specified by Language, then a pointer to the driver name is
> + returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
> + by This does not support the language specified by Language,
> + then EFI_UNSUPPORTED is returned.
> +
> + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
> + EFI_COMPONENT_NAME_PROTOCOL instance.
> +
> + @param Language[in] A pointer to a Null-terminated ASCII string
> + array indicating the language. This is the
> + language of the driver name that the caller is
> + requesting, and it must match one of the
> + languages specified in SupportedLanguages. The
> + number of languages supported by a driver is up
> + to the driver writer. Language is specified
> + in RFC 4646 or ISO 639-2 language code format.
> +
> + @param DriverName[out] A pointer to the Unicode string to return.
> + This Unicode string is the name of the
> + driver specified by This in the language
> + specified by Language.
> +
> + @retval EFI_SUCCESS The Unicode string for the Driver specified by
> + This and the language specified by Language was
> + returned in DriverName.
> +
> + @retval EFI_INVALID_PARAMETER Language is NULL.
> +
> + @retval EFI_INVALID_PARAMETER DriverName is NULL.
> +
> + @retval EFI_UNSUPPORTED The driver specified by This does not support
> + the language specified by Language.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +NxpI2cGetDriverName (
> + IN EFI_COMPONENT_NAME2_PROTOCOL *This,
> + IN CHAR8 *Language,
> + OUT CHAR16 **DriverName
> + )
> +{
> + return LookupUnicodeString2 (Language,
> + This->SupportedLanguages,
> + mNxpI2cDriverNameTable,
> + DriverName,
> + FALSE);
> +}
> +
> +/**
> + Retrieves a Unicode string that is the user readable name of the controller
> + that is being managed by a driver.
> +
> + This function retrieves the user readable name of the controller specified by
> + ControllerHandle and ChildHandle in the form of a Unicode string. If the
> + driver specified by This has a user readable name in the language specified by
> + Language, then a pointer to the controller name is returned in ControllerName,
> + and EFI_SUCCESS is returned. If the driver specified by This is not currently
> + managing the controller specified by ControllerHandle and ChildHandle,
> + then EFI_UNSUPPORTED is returned. If the driver specified by This does not
> + support the language specified by Language, then EFI_UNSUPPORTED is returned.
> +
> + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
> + EFI_COMPONENT_NAME_PROTOCOL instance.
> +
> + @param ControllerHandle[in] The handle of a controller that the driver
> + specified by This is managing. This handle
> + specifies the controller whose name is to be
> + returned.
> +
> + @param ChildHandle[in] The handle of the child controller to retrieve
> + the name of. This is an optional parameter that
> + may be NULL. It will be NULL for device
> + drivers. It will also be NULL for a bus drivers
> + that wish to retrieve the name of the bus
> + controller. It will not be NULL for a bus
> + driver that wishes to retrieve the name of a
> + child controller.
> +
> + @param Language[in] A pointer to a Null-terminated ASCII string
> + array indicating the language. This is the
> + language of the driver name that the caller is
> + requesting, and it must match one of the
> + languages specified in SupportedLanguages. The
> + number of languages supported by a driver is up
> + to the driver writer. Language is specified in
> + RFC 4646 or ISO 639-2 language code format.
> +
> + @param ControllerName[out] A pointer to the Unicode string to return.
> + This Unicode string is the name of the
> + controller specified by ControllerHandle and
> + ChildHandle in the language specified by
> + Language from the point of view of the driver
> + specified by This.
> +
> + @retval EFI_SUCCESS The Unicode string for the user readable name in
> + the language specified by Language for the
> + driver specified by This was returned in
> + DriverName.
> +
> + @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
> +
> + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
> + EFI_HANDLE.
> +
> + @retval EFI_INVALID_PARAMETER Language is NULL.
> +
> + @retval EFI_INVALID_PARAMETER ControllerName is NULL.
> +
> + @retval EFI_UNSUPPORTED The driver specified by This is not currently
> + managing the controller specified by
> + ControllerHandle and ChildHandle.
> +
> + @retval EFI_UNSUPPORTED The driver specified by This does not support
> + the language specified by Language.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +NxpI2cGetControllerName (
> + IN EFI_COMPONENT_NAME2_PROTOCOL *This,
> + IN EFI_HANDLE ControllerHandle,
> + IN EFI_HANDLE ChildHandle OPTIONAL,
> + IN CHAR8 *Language,
> + OUT CHAR16 **ControllerName
> + )
> +{
> + if (ChildHandle != NULL) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + return LookupUnicodeString2 (Language,
> + This->SupportedLanguages,
> + mNxpI2cControllerNameTable,
> + ControllerName,
> + FALSE);
> +}
> +
> +//
> +// EFI Component Name 2 Protocol
> +//
> +EFI_COMPONENT_NAME2_PROTOCOL gNxpI2cDriverComponentName2 = {
> + NxpI2cGetDriverName,
> + NxpI2cGetControllerName,
> + "en"
> +};
> diff --git a/Silicon/NXP/Drivers/I2cDxe/DriverBinding.c b/Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
> new file mode 100644
> index 0000000..ad7a9f3
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
> @@ -0,0 +1,241 @@
> +/** @file
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD
> + License which accompanies this distribution. The full text of the license may
> + be found at http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +
> +#include <Protocol/DriverBinding.h>
> +
> +#include "I2cDxe.h"
> +
> +/**
> + Tests to see if this driver supports a given controller.
> +
> + @param This[in] A pointer to the EFI_DRIVER_BINDING_PROTOCOL
> + instance.
> + @param ControllerHandle[in] The handle of the controller to test.
> + @param RemainingDevicePath[in] The remaining device path.
> + (Ignored - this is not a bus driver.)
> +
> + @retval EFI_SUCCESS The driver supports this controller.
> + @retval EFI_ALREADY_STARTED The device specified by ControllerHandle is
> + already being managed by the driver specified
> + by This.
> + @retval EFI_UNSUPPORTED The device specified by ControllerHandle is
> + not supported by the driver specified by This.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +NxpI2cDriverBindingSupported (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE ControllerHandle,
> + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
> + )
> +{
> + NON_DISCOVERABLE_DEVICE *Dev;
> + EFI_STATUS Status;
> +
> + //
> + // Connect to the non-discoverable device
> + //
> + Status = gBS->OpenProtocol (ControllerHandle,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid,
> + (VOID **) &Dev,
> + This->DriverBindingHandle,
> + ControllerHandle,
> + EFI_OPEN_PROTOCOL_BY_DRIVER);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if (CompareGuid (Dev->Type, &gNxpNonDiscoverableI2cMasterGuid)) {
> + Status = EFI_SUCCESS;
> + } else {
> + Status = EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Clean up.
> + //
> + gBS->CloseProtocol (ControllerHandle,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid,
> + This->DriverBindingHandle,
> + ControllerHandle);
> +
> + return Status;
> +}
> +
> +
> +/**
> + Starts a device controller or a bus controller.
> +
> + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL
> + instance.
> + @param[in] ControllerHandle The handle of the device to start. This
> + handle must support a protocol interface that
> + supplies an I/O abstraction to the driver.
> + @param[in] RemainingDevicePath The remaining portion of the device path.
> + (Ignored - this is not a bus driver.)
> +
> + @retval EFI_SUCCESS The device was started.
> + @retval EFI_DEVICE_ERROR The device could not be started due to a
> + device error.
> + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
> + lack of resources.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +NxpI2cDriverBindingStart (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE ControllerHandle,
> + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL
> + )
> +{
> + return NxpI2cInit (This->DriverBindingHandle, ControllerHandle);
> +}
> +
> +
> +/**
> + Stops a device controller or a bus controller.
> +
> + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL
> + instance.
> + @param[in] ControllerHandle A handle to the device being stopped. The handle
> + must support a bus specific I/O protocol for the
> + driver to use to stop the device.
> + @param[in] NumberOfChildren The number of child device handles in
> + ChildHandleBuffer.
> + @param[in] ChildHandleBuffer An array of child handles to be freed. May be
> + NULL if NumberOfChildren is 0.
> +
> + @retval EFI_SUCCESS The device was stopped.
> + @retval EFI_DEVICE_ERROR The device could not be stopped due to a device
> + error.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +NxpI2cDriverBindingStop (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE ControllerHandle,
> + IN UINTN NumberOfChildren,
> + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL
> + )
> +{
> + return NxpI2cRelease (This->DriverBindingHandle, ControllerHandle);
> +}
> +
> +
> +STATIC EFI_DRIVER_BINDING_PROTOCOL gNxpI2cDriverBinding = {
> + NxpI2cDriverBindingSupported,
> + NxpI2cDriverBindingStart,
> + NxpI2cDriverBindingStop,
> + 0xa,
> + NULL,
> + NULL
> +};
> +
> +
> +/**
> + The entry point of I2c UEFI Driver.
> +
> + @param ImageHandle The image handle of the UEFI Driver.
> + @param SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The Driver or UEFI Driver exited normally.
> + @retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than
> + SystemTable->Hdr.Revision.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +I2cDxeEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> +
> + //
> + // Add the driver to the list of drivers
> + //
> + Status = EfiLibInstallDriverBindingComponentName2 (
> + ImageHandle, SystemTable, &gNxpI2cDriverBinding, ImageHandle,
> + NULL, &gNxpI2cDriverComponentName2);
> + ASSERT_EFI_ERROR (Status);
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Unload function for the I2c UEFI Driver.
> +
> + @param ImageHandle[in] The allocated handle for the EFI image
> +
> + @retval EFI_SUCCESS The driver was unloaded successfully
> + @retval EFI_INVALID_PARAMETER ImageHandle is not a valid image handle.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +I2cDxeUnload (
> + IN EFI_HANDLE ImageHandle
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE *HandleBuffer;
> + UINTN HandleCount;
> + UINTN Index;
> +
> + //
> + // Retrieve all USB I/O handles in the handle database
> + //
> + Status = gBS->LocateHandleBuffer (ByProtocol,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid,
> + NULL,
> + &HandleCount,
> + &HandleBuffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Disconnect the driver from the handles in the handle database
> + //
> + for (Index = 0; Index < HandleCount; Index++) {
> + Status = gBS->DisconnectController (HandleBuffer[Index],
> + gImageHandle,
> + NULL);
> + }
> +
> + //
> + // Free the handle array
> + //
> + gBS->FreePool (HandleBuffer);
> +
> + //
> + // Uninstall protocols installed by the driver in its entrypoint
> + //
> + Status = gBS->UninstallMultipleProtocolInterfaces (ImageHandle,
> + &gEfiDriverBindingProtocolGuid,
> + &gNxpI2cDriverBinding,
> + NULL
> + );
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> new file mode 100644
> index 0000000..08aae72
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> @@ -0,0 +1,693 @@
> +/** I2cDxe.c
> + I2c driver APIs for read, write, initialize, set speed and reset
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +
> +#include "I2cDxe.h"
> +
> +STATIC CONST UINT16 ClkDiv[60][2] = {
m-prefix please.
Also, could you rework this slightly as a
STATIC CONST STRUCT {
UINT16 <something>;
UINT16 <something else>;
} mClkDiv = { {..., ...},
......
};
?
> + { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
> + { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
> + { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
> + { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
> + { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
> + { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
> + { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
> + { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
> + { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
> + { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
> + { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
> + { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 },{ 1280, 0x35 },
> + { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
> + { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
> + { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
> +};
> +
> +/**
> + Calculate and return proper clock divider
> +
> + @param Rate clock rate
Desired clock rate or current clock rate?
> +
> + @retval ClkDiv Value used to get frequency divider value
Does this mean the register configuration value?
(I think the rework I propose above would help clarify this.)
> +
> +**/
> +STATIC
> +UINT8
> +GetClkDiv (
GetClkDivIndex?
> + IN UINT32 Rate
> + )
> +{
> + UINTN ClkRate;
> + UINT32 Div;
> + UINT8 ClkDivx;
I don't understand what ClkDivx is - index?
> +
> + ClkRate = GetBusFrequency ();
> +
> + Div = (ClkRate + Rate - 1) / Rate;
> +
> + if (Div < ClkDiv[0][0]) {
> + ClkDivx = 0;
> + } else if (Div > ClkDiv[ARRAY_SIZE (ClkDiv) - 1][0]){
> + ClkDivx = ARRAY_SIZE (ClkDiv) - 1;
> + } else {
> + for (ClkDivx = 0; ClkDiv[ClkDivx][0] < Div; ClkDivx++);
> + }
> +
> + return ClkDivx;
With that restructuring, this code could be changed to something like
UINT8 Index;
Index = 0;
if (Div < *mClkDiv.<something>) {
return 0;
}
do {
if (mClkDiv[Index].<something> >= Div) {
return Index;
}
Index++;
} while (Index < ARRAY_SIZE (mClkDiv));
return ARRAY_SIZE (mClkDiv) - 1;
which is easier for at least me to read.
(I've not tested the above, and I might have got a comparison wrong
somewhere, but you get the idea.)
> +}
> +
> +/**
> + Function used to check if i2c is in mentioned state or not
> +
> + @param I2cRegs Pointer to I2C registers
> + @param State i2c state need to be checked
> +
> + @retval EFI_NOT_READY Arbitration was lost
> + @retval EFI_TIMEOUT Timeout occured
> + @retval CurrState Value of state register
> +
> +**/
> +STATIC
> +EFI_STATUS
> +WaitForI2cState (
> + IN I2C_REGS *I2cRegs,
> + IN UINT32 State
> + )
> +{
> + UINT8 CurrState;
> + UINT64 Cnt;
Cnt -> Count
> +
> + for (Cnt = 0; Cnt < 50000; Cnt++) {
Could you add a #define for that 50000?
Presumably <something>_RETRIES?
> + MemoryFence ();
> + CurrState = MmioRead8 ((UINTN)&I2cRegs->I2cSr);
> + if (CurrState & I2C_SR_IAL) {
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, CurrState | I2C_SR_IAL);
> + return EFI_NOT_READY;
> + }
> +
> + if ((CurrState & (State >> 8)) == (UINT8)State) {
> + return CurrState;
> + }
> + }
> +
> + return EFI_TIMEOUT;
> +}
> +
> +/**
> + Function to transfer byte on i2c
> +
> + @param I2cRegs Pointer to i2c registers
> + @param Byte Byte to be transferred on i2c bus
> +
> + @retval EFI_NOT_READY Arbitration was lost
> + @retval EFI_TIMEOUT Timeout occured
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Data transfer was succesful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +TransferByte (
> + IN I2C_REGS *I2cRegs,
> + IN UINT8 Byte
> + )
> +{
> + EFI_STATUS Ret;
Ret -> RetVal
> +
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> + MmioWrite8 ((UINTN)&I2cRegs->I2cDr, Byte);
> +
> + Ret = WaitForI2cState (I2cRegs, IIF);
> + if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
> + return Ret;
> + }
> +
> + if (Ret & I2C_SR_RX_NO_AK) {
> + return EFI_NOT_FOUND;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to stop transaction on i2c bus
> +
> + @param I2cRegs Pointer to i2c registers
> +
> + @retval EFI_NOT_READY Arbitration was lost
> + @retval EFI_TIMEOUT Timeout occured
> + @retval EFI_SUCCESS Stop operation was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +I2cStop (
> + IN I2C_REGS *I2cRegs
> + )
> +{
> + INT32 Ret;
Ret -> RetVal.
EFI_STATUS.
(Can you please change these throughout - it's more edk2 idiomatic.)
> + UINT32 Temp;
> +
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> +
> + Temp &= ~(I2C_CR_MSTA | I2C_CR_MTX);
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> +
> + Ret = WaitForI2cState (I2cRegs, BUS_IDLE);
> +
> + if (Ret < 0) {
> + return Ret;
> + } else {
> + return EFI_SUCCESS;
> + }
> +}
> +
> +/**
> + Function to send start signal, Chip Address and
> + memory offset
> +
> + @param I2cRegs Pointer to i2c base registers
> + @param Chip Chip Address
> + @param Offset Slave memory's offset
> + @param Alen length of chip address
> +
> + @retval EFI_NOT_READY Arbitration lost
> + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Read was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +InitTransfer (
> + IN I2C_REGS *I2cRegs,
> + IN UINT8 Chip,
> + IN UINT32 Offset,
> + IN INT32 Alen
AddressLength?
> + )
> +{
> + UINT32 Temp;
> + EFI_STATUS Ret;
> +
> + // Enable I2C controller
> + if (MmioRead8 ((UINTN)&I2cRegs->I2cCr) & I2C_CR_IDIS) {
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IEN);
> + }
> +
> + if (MmioRead8 ((UINTN)&I2cRegs->I2cAdr) == (Chip << 1)) {
> + MmioWrite8 ((UINTN)&I2cRegs->I2cAdr, (Chip << 1) ^ 2);
> + }
> +
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> + Ret = WaitForI2cState (I2cRegs, BUS_IDLE);
> + if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
> + return Ret;
> + }
> +
> + // Start I2C transaction
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> + // set to master mode
> + Temp |= I2C_CR_MSTA;
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> +
> + Ret = WaitForI2cState (I2cRegs, BUS_BUSY);
> + if ((Ret == EFI_TIMEOUT) || (Ret == EFI_NOT_READY)) {
> + return Ret;
> + }
> +
> + Temp |= I2C_CR_MTX | I2C_CR_TX_NO_AK;
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> +
> + // write slave Address
> + Ret = TransferByte (I2cRegs, Chip << 1);
> + if (Ret != EFI_SUCCESS) {
> + return Ret;
> + }
> +
> + if (Alen >= 0) {
> + while (Alen--) {
> + Ret = TransferByte (I2cRegs, (Offset >> (Alen * 8)) & 0xff);
> + if (Ret != EFI_SUCCESS)
> + return Ret;
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to check if i2c bus is idle
> +
> + @param Base Pointer to base address of I2c controller
> +
> + @retval EFI_SUCCESS
> +
> +**/
> +STATIC
> +INT32
> +I2cBusIdle (
> + IN VOID *Base
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to initiate data transfer on i2c bus
> +
> + @param I2cRegs Pointer to i2c base registers
> + @param Chip Chip Address
> + @param Offset Slave memory's offset
> + @param Alen length of chip address
> +
> + @retval EFI_NOT_READY Arbitration lost
> + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Read was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +InitDataTransfer (
> + IN I2C_REGS *I2cRegs,
> + IN UINT8 Chip,
> + IN UINT32 Offset,
> + IN INT32 Alen
AddressLength?
(Please update throughout.)
> + )
> +{
> + EFI_STATUS Status;
Hmm ... actually, could you please align these throughout the patch.
I don't really care whether it's RetVal or Status - but I would like
for it to be consistent within any given module.
> + INT32 Retry;
> +
> + for (Retry = 0; Retry < 3; Retry++) {
A #define for that 3?
No more comments for this patch.
Regards,
Leif
> + Status = InitTransfer (I2cRegs, Chip, Offset, Alen);
> + if (Status == EFI_SUCCESS) {
> + return EFI_SUCCESS;
> + }
> +
> + I2cStop (I2cRegs);
> +
> + if (EFI_NOT_FOUND == Status) {
> + return Status;
> + }
> +
> + // Disable controller
> + if (Status != EFI_NOT_READY) {
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
> + }
> +
> + if (I2cBusIdle (I2cRegs) < 0) {
> + break;
> + }
> + }
> + return Status;
> +}
> +
> +/**
> + Function to read data using i2c bus
> +
> + @param BaseAddr I2c Controller Base Address
> + @param Chip Address of slave device from where data to be read
> + @param Offset Offset of slave memory
> + @param Alen Address length of slave
> + @param Buffer A pointer to the destination buffer for the data
> + @param Len Length of data to be read
> +
> + @retval EFI_NOT_READY Arbitration lost
> + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Read was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +I2cDataRead (
> + IN UINTN BaseAddr,
> + IN UINT8 Chip,
> + IN UINT32 Offset,
> + IN UINT32 Alen,
> + IN UINT8 *Buffer,
> + IN UINT32 Len
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 Temp;
> + INT32 I;
> + I2C_REGS *I2cRegs;
> +
> + I2cRegs = (I2C_REGS *)(BaseAddr);
> +
> + Status = InitDataTransfer (I2cRegs, Chip, Offset, Alen);
> + if (Status != EFI_SUCCESS) {
> + return Status;
> + }
> +
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> + Temp |= I2C_CR_RSTA;
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> +
> + Status = TransferByte (I2cRegs, (Chip << 1) | 1);
> + if (Status != EFI_SUCCESS) {
> + I2cStop (I2cRegs);
> + return Status;
> + }
> +
> + // setup bus to read data
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> + Temp &= ~(I2C_CR_MTX | I2C_CR_TX_NO_AK);
> + if (Len == 1) {
> + Temp |= I2C_CR_TX_NO_AK;
> + }
> +
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> +
> + // Dummy Read to initiate recieve operation
> + MmioRead8 ((UINTN)&I2cRegs->I2cDr);
> +
> + for (I = 0; I < Len; I++) {
> + Status = WaitForI2cState (I2cRegs, IIF);
> + if ((Status == EFI_TIMEOUT) || (Status == EFI_NOT_READY)) {
> + I2cStop (I2cRegs);
> + return Status;
> + }
> + //
> + // It must generate STOP before read I2DR to prevent
> + // controller from generating another clock cycle
> + //
> + if (I == (Len - 1)) {
> + I2cStop (I2cRegs);
> + } else if (I == (Len - 2)) {
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> + Temp |= I2C_CR_TX_NO_AK;
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> + }
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> + Buffer[I] = MmioRead8 ((UINTN)&I2cRegs->I2cDr);
> + }
> +
> + I2cStop (I2cRegs);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to write data using i2c bus
> +
> + @param BaseAddr I2c Controller Base Address
> + @param Chip Address of slave device where data to be written
> + @param Offset Offset of slave memory
> + @param Alen Address length of slave
> + @param Buffer A pointer to the source buffer for the data
> + @param Len Length of data to be write
> +
> + @retval EFI_NOT_READY Arbitration lost
> + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Read was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +I2cDataWrite (
> + IN UINTN BaseAddr,
> + IN UINT8 Chip,
> + IN UINT32 Offset,
> + IN INT32 Alen,
> + OUT UINT8 *Buffer,
> + IN INT32 Len
> + )
> +{
> + EFI_STATUS Status;
> + I2C_REGS *I2cRegs;
> + INT32 I;
> +
> + I2cRegs = (I2C_REGS *)BaseAddr;
> +
> + Status = InitDataTransfer (I2cRegs, Chip, Offset, Alen);
> + if (Status != EFI_SUCCESS) {
> + return Status;
> + }
> +
> + // Write operation
> + for (I = 0; I < Len; I++) {
> + Status = TransferByte (I2cRegs, Buffer[I]);
> + if (Status != EFI_SUCCESS) {
> + break;
> + }
> + }
> +
> + I2cStop (I2cRegs);
> + return Status;
> +}
> +
> +/**
> + Function to set i2c bus frequency
> +
> + @param This Pointer to I2c master protocol
> + @param BusClockHertz value to be set
> +
> + @retval EFI_SUCCESS Operation successfull
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SetBusFrequency (
> + IN CONST EFI_I2C_MASTER_PROTOCOL *This,
> + IN OUT UINTN *BusClockHertz
> + )
> +{
> + I2C_REGS *I2cRegs;
> + UINT8 ClkId;
> + UINT8 SpeedId;
> + NXP_I2C_MASTER *I2c;
> +
> + I2c = NXP_I2C_FROM_THIS (This);
> +
> + I2cRegs = (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin);
> +
> + ClkId = GetClkDiv (*BusClockHertz);
> + SpeedId = ClkDiv[ClkId][1];
> +
> + // Store divider value
> + MmioWrite8 ((UINTN)&I2cRegs->I2cFdr, SpeedId);
> +
> + MemoryFence ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to reset I2c Controller
> +
> + @param This Pointer to I2c master protocol
> +
> + @return EFI_SUCCESS Operation successfull
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +Reset (
> + IN CONST EFI_I2C_MASTER_PROTOCOL *This
> + )
> +{
> + I2C_REGS *I2cRegs;
> + NXP_I2C_MASTER *I2c;
> +
> + I2c = NXP_I2C_FROM_THIS (This);
> +
> + I2cRegs = (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin);
> +
> + // Reset module
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, 0);
> +
> + MemoryFence ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +StartRequest (
> + IN CONST EFI_I2C_MASTER_PROTOCOL *This,
> + IN UINTN SlaveAddress,
> + IN EFI_I2C_REQUEST_PACKET *RequestPacket,
> + IN EFI_EVENT Event OPTIONAL,
> + OUT EFI_STATUS *I2cStatus OPTIONAL
> + )
> +{
> + NXP_I2C_MASTER *I2c;
> + UINT32 Count;
> + INT32 Ret;
> + UINT32 Length;
> + UINT8 *Buffer;
> + UINT32 Flag;
> + UINT32 RegAddress;
> + UINT32 OffsetLength;
> +
> + RegAddress = 0;
> +
> + I2c = NXP_I2C_FROM_THIS (This);
> +
> + if (RequestPacket->OperationCount <= 0) {
> + DEBUG ((DEBUG_ERROR,"%a: Operation count is not valid %d\n",
> + __FUNCTION__, RequestPacket->OperationCount));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + OffsetLength = RequestPacket->Operation[0].LengthInBytes;
> + RegAddress = *RequestPacket->Operation[0].Buffer;
> +
> + for (Count = 1; Count < RequestPacket->OperationCount; Count++) {
> + Flag = RequestPacket->Operation[Count].Flags;
> + Length = RequestPacket->Operation[Count].LengthInBytes;
> + Buffer = RequestPacket->Operation[Count].Buffer;
> +
> + if (Length <= 0) {
> + DEBUG ((DEBUG_ERROR,"%a: Invalid length of buffer %d\n",
> + __FUNCTION__, Length));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if (Flag == I2C_FLAG_READ) {
> + Ret = I2cDataRead (I2c->Dev->Resources[0].AddrRangeMin, SlaveAddress,
> + RegAddress, OffsetLength, Buffer, Length);
> + if (Ret != EFI_SUCCESS) {
> + DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n",
> + __FUNCTION__, Ret));
> + return Ret;
> + }
> + } else if (Flag == I2C_FLAG_WRITE) {
> + Ret = I2cDataWrite (I2c->Dev->Resources[0].AddrRangeMin, SlaveAddress,
> + RegAddress, OffsetLength, Buffer, Length);
> + if (Ret != EFI_SUCCESS) {
> + DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n",
> + __FUNCTION__, Ret));
> + return Ret;
> + }
> + } else {
> + DEBUG ((DEBUG_ERROR,"%a: Invalid Flag %d\n",
> + __FUNCTION__, Flag));
> + return EFI_INVALID_PARAMETER;
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC CONST EFI_I2C_CONTROLLER_CAPABILITIES I2cControllerCapabilities = {
> + 0,
> + 0,
> + 0,
> + 0
> +};
> +
> +EFI_STATUS
> +NxpI2cInit (
> + IN EFI_HANDLE DriverBindingHandle,
> + IN EFI_HANDLE ControllerHandle
> + )
> +{
> + EFI_STATUS Status;
> + NON_DISCOVERABLE_DEVICE *Dev;
> + NXP_I2C_MASTER *I2c;
> +
> + Status = gBS->OpenProtocol (ControllerHandle,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid,
> + (VOID **)&Dev, DriverBindingHandle,
> + ControllerHandle, EFI_OPEN_PROTOCOL_BY_DRIVER);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + I2c = AllocateZeroPool (sizeof (NXP_I2C_MASTER));
> +
> + I2c->Signature = NXP_I2C_SIGNATURE;
> + I2c->I2cMaster.SetBusFrequency = SetBusFrequency;
> + I2c->I2cMaster.Reset = Reset;
> + I2c->I2cMaster.StartRequest = StartRequest;
> + I2c->I2cMaster.I2cControllerCapabilities = &I2cControllerCapabilities;
> + I2c->Dev = Dev;
> +
> + CopyGuid (&I2c->DevicePath.Vendor.Guid, &gEfiCallerIdGuid);
> + I2c->DevicePath.MmioBase = I2c->Dev->Resources[0].AddrRangeMin;
> + SetDevicePathNodeLength (&I2c->DevicePath.Vendor,
> + sizeof (I2c->DevicePath) - sizeof (I2c->DevicePath.End));
> + SetDevicePathEndNode (&I2c->DevicePath.End);
> +
> + Status = gBS->InstallMultipleProtocolInterfaces (&ControllerHandle,
> + &gEfiI2cMasterProtocolGuid, (VOID**)&I2c->I2cMaster,
> + &gEfiDevicePathProtocolGuid, &I2c->DevicePath,
> + NULL);
> +
> + if (EFI_ERROR (Status)) {
> + FreePool (I2c);
> + gBS->CloseProtocol (ControllerHandle,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid,
> + DriverBindingHandle,
> + ControllerHandle);
> + }
> +
> + return Status;
> +}
> +
> +EFI_STATUS
> +NxpI2cRelease (
> + IN EFI_HANDLE DriverBindingHandle,
> + IN EFI_HANDLE ControllerHandle
> + )
> +{
> + EFI_I2C_MASTER_PROTOCOL *I2cMaster;
> + EFI_STATUS Status;
> + NXP_I2C_MASTER *I2c;
> +
> + Status = gBS->HandleProtocol (ControllerHandle,
> + &gEfiI2cMasterProtocolGuid,
> + (VOID **)&I2cMaster);
> + ASSERT_EFI_ERROR (Status);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + I2c = NXP_I2C_FROM_THIS (I2cMaster);
> +
> + Status = gBS->UninstallMultipleProtocolInterfaces (ControllerHandle,
> + &gEfiI2cMasterProtocolGuid, I2cMaster,
> + &gEfiDevicePathProtocolGuid, &I2c->DevicePath,
> + NULL);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + Status = gBS->CloseProtocol (ControllerHandle,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid,
> + DriverBindingHandle,
> + ControllerHandle);
> + ASSERT_EFI_ERROR (Status);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + gBS->FreePool (I2c);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> new file mode 100644
> index 0000000..01eeca4
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> @@ -0,0 +1,96 @@
> +/** I2cDxe.h
> + Header defining the constant, base address amd function for I2C controller
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __I2C_DXE_H__
> +#define __I2C_DXE_H__
> +
> +#include <Library/UefiLib.h>
> +#include <Uefi.h>
> +
> +#include <Protocol/I2cMaster.h>
> +#include <Protocol/NonDiscoverableDevice.h>
> +
> +#define I2C_CR_IIEN (1 << 6)
> +#define I2C_CR_MSTA (1 << 5)
> +#define I2C_CR_MTX (1 << 4)
> +#define I2C_CR_TX_NO_AK (1 << 3)
> +#define I2C_CR_RSTA (1 << 2)
> +
> +#define I2C_SR_ICF (1 << 7)
> +#define I2C_SR_IBB (1 << 5)
> +#define I2C_SR_IAL (1 << 4)
> +#define I2C_SR_IIF (1 << 1)
> +#define I2C_SR_RX_NO_AK (1 << 0)
> +
> +#define I2C_CR_IEN (0 << 7)
> +#define I2C_CR_IDIS (1 << 7)
> +#define I2C_SR_IIF_CLEAR (1 << 1)
> +
> +#define BUS_IDLE (0 | (I2C_SR_IBB << 8))
> +#define BUS_BUSY (I2C_SR_IBB | (I2C_SR_IBB << 8))
> +#define IIF (I2C_SR_IIF | (I2C_SR_IIF << 8))
> +
> +#define I2C_FLAG_WRITE 0x0
> +
> +#define NXP_I2C_SIGNATURE SIGNATURE_32 ('N', 'I', '2', 'C')
> +#define NXP_I2C_FROM_THIS(a) CR ((a), NXP_I2C_MASTER, \
> + I2cMaster, NXP_I2C_SIGNATURE)
> +extern EFI_COMPONENT_NAME2_PROTOCOL gNxpI2cDriverComponentName2;
> +
> +#pragma pack(1)
> +typedef struct {
> + VENDOR_DEVICE_PATH Vendor;
> + UINT64 MmioBase;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} NXP_I2C_DEVICE_PATH;
> +#pragma pack()
> +
> +typedef struct {
> + UINT32 Signature;
> + EFI_I2C_MASTER_PROTOCOL I2cMaster;
> + NXP_I2C_DEVICE_PATH DevicePath;
> + NON_DISCOVERABLE_DEVICE *Dev;
> +} NXP_I2C_MASTER;
> +
> +/**
> + Record defining i2c registers
> +**/
> +typedef struct {
> + UINT8 I2cAdr;
> + UINT8 I2cFdr;
> + UINT8 I2cCr;
> + UINT8 I2cSr;
> + UINT8 I2cDr;
> +} I2C_REGS ;
> +
> +extern
> +UINT64
> +GetBusFrequency (
> + VOID
> + );
> +
> +EFI_STATUS
> +NxpI2cInit (
> + IN EFI_HANDLE DriverBindingHandle,
> + IN EFI_HANDLE ControllerHandle
> + );
> +
> +EFI_STATUS
> +NxpI2cRelease (
> + IN EFI_HANDLE DriverBindingHandle,
> + IN EFI_HANDLE ControllerHandle
> + );
> +
> +#endif
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> new file mode 100644
> index 0000000..0691362
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> @@ -0,0 +1,64 @@
> +# @file
> +#
> +# Component description file for I2c driver
> +#
> +# Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = I2cDxe
> + FILE_GUID = 5f2927ba-1b04-4d5f-8bef-2b50c635d1e7
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = I2cDxeEntryPoint
> + UNLOAD = I2cDxeUnload
> +
> +[Sources.common]
> + ComponentName.c
> + DriverBinding.c
> + I2cDxe.c
> +
> +[LibraryClasses]
> + ArmLib
> + BaseMemoryLib
> + DevicePathLib
> + IoLib
> + MemoryAllocationLib
> + PcdLib
> + SocLib
> + TimerLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> + UefiLib
> +
> +[Guids]
> + gNxpNonDiscoverableI2cMasterGuid
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[Protocols]
> + gEdkiiNonDiscoverableDeviceProtocolGuid ## TO_START
> + gEfiI2cMasterProtocolGuid ## BY_START
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
> +
> +[Depex]
> + TRUE
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 08/41] Platform/NXP: Add Platform driver for LS1043 RDB board
2018-11-28 15:01 ` [PATCH edk2-platforms 08/41] Platform/NXP: Add Platform driver for LS1043 RDB board Meenakshi Aggarwal
@ 2018-12-18 17:47 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-18 17:47 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
Please add a commit message.
What does the platform driver _do_?
(No comments on the code.)
/
Leif
On Wed, Nov 28, 2018 at 08:31:22PM +0530, Meenakshi Aggarwal wrote:
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> .../Drivers/PlatformDxe/PlatformDxe.c | 119 +++++++++++++++++++++
> .../Drivers/PlatformDxe/PlatformDxe.inf | 58 ++++++++++
> 2 files changed, 177 insertions(+)
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> new file mode 100644
> index 0000000..7ce7318
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> @@ -0,0 +1,119 @@
> +/** @file
> + LS1043 DXE platform driver.
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +**/
> +
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +
> +#include <Protocol/NonDiscoverableDevice.h>
> +
> +typedef struct {
> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR StartDesc;
> + UINT8 EndDesc;
> +} ADDRESS_SPACE_DESCRIPTOR;
> +
> +STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
> +
> +STATIC
> +EFI_STATUS
> +RegisterDevice (
> + IN EFI_GUID *TypeGuid,
> + IN ADDRESS_SPACE_DESCRIPTOR *Desc,
> + OUT EFI_HANDLE *Handle
> + )
> +{
> + NON_DISCOVERABLE_DEVICE *Device;
> + EFI_STATUS Status;
> +
> + Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device));
> + if (Device == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + Device->Type = TypeGuid;
> + Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent;
> + Device->Resources = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Desc;
> +
> + Status = gBS->InstallMultipleProtocolInterfaces (Handle,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid, Device,
> + NULL);
> + if (EFI_ERROR (Status)) {
> + goto FreeDevice;
> + }
> + return EFI_SUCCESS;
> +
> +FreeDevice:
> + FreePool (Device);
> +
> + return Status;
> +}
> +
> +VOID
> +PopulateI2cInformation (
> + IN VOID
> + )
> +{
> + UINT32 Index;
> +
> + for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
> + mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
> + mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
> + mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
> + mI2cDesc[Index].StartDesc.GenFlag = 0;
> + mI2cDesc[Index].StartDesc.SpecificFlag = 0;
> + mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
> + mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
> + (Index * FixedPcdGet32 (PcdI2cSize));
> + mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
> + FixedPcdGet32 (PcdI2cSize) - 1;
> + mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
> + mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
> +
> + mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
> + }
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +PlatformDxeEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE Handle;
> +
> + Handle = NULL;
> +
> + PopulateI2cInformation ();
> +
> + Status = RegisterDevice (&gNxpNonDiscoverableI2cMasterGuid,
> + &mI2cDesc[0], &Handle);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Install the DS1307 I2C Master protocol on this handle so the RTC driver
> + // can identify it as the I2C master it can invoke directly.
> + //
> + Status = gBS->InstallProtocolInterface (&Handle,
> + &gDs1307RealTimeClockLibI2cMasterProtocolGuid,
> + EFI_NATIVE_INTERFACE, NULL);
> + ASSERT_EFI_ERROR (Status);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> new file mode 100644
> index 0000000..91d6ad3
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> @@ -0,0 +1,58 @@
> +## @file
> +#
> +# Component description file for LS1043 DXE platform driver.
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PlatformDxe
> + FILE_GUID = 21108101-adcd-4123-930e-a2354a554db7
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PlatformDxeEntryPoint
> +
> +[Sources]
> + PlatformDxe.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + DebugLib
> + MemoryAllocationLib
> + PcdLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> + UefiLib
> +
> +[Guids]
> + gNxpNonDiscoverableI2cMasterGuid
> +
> +[Protocols]
> + gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
> + gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES
> +
> +[FixedPcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
> +
> +[Depex]
> + TRUE
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 09/41] Compilation : Add the fdf, dsc and dec files.
2018-11-28 15:01 ` [PATCH edk2-platforms 09/41] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
@ 2018-12-18 18:35 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-18 18:35 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Wed, Nov 28, 2018 at 08:31:23PM +0530, Meenakshi Aggarwal wrote:
> The firmware device, description and declaration files.
>
I won't give a reviewed-by yet since there will be at least some
changes related to watchdog - but I have a couple of comments in
addition to that.
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Platform/NXP/FVRules.fdf.inc | 99 +++++++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 29 ++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 80 ++++++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 198 +++++++++++++
> Platform/NXP/NxpQoriqLs.dsc.inc | 412 +++++++++++++++++++++++++++
> Silicon/NXP/LS1043A/LS1043A.dec | 22 ++
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 73 +++++
> Silicon/NXP/NxpQoriqLs.dec | 117 ++++++++
> 8 files changed, 1030 insertions(+)
> create mode 100644 Platform/NXP/FVRules.fdf.inc
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> create mode 100644 Platform/NXP/NxpQoriqLs.dsc.inc
> create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
> create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc.inc
> create mode 100644 Silicon/NXP/NxpQoriqLs.dec
>
> diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc
> new file mode 100644
> index 0000000..d0e17cb
> --- /dev/null
> +++ b/Platform/NXP/FVRules.fdf.inc
> @@ -0,0 +1,99 @@
> +# FvRules.fdf.inc
> +#
> +# Rules for creating FD.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# Rules are use with the [FV] section's module INF type to define
> +# how an FFS file is created for a given INF file. The following Rule are the default
> +# rules for the different module type. User can add the customized rules to define the
> +# content of the FFS file.
> +#
> +################################################################################
> +
> +[Rule.Common.SEC]
> + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> + TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + }
> +
> +[Rule.Common.PEI_CORE]
> + FILE PEI_CORE = $(NAMED_GUID) {
> + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING ="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.PEIM]
> + FILE PEIM = $(NAMED_GUID) {
> + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.PEIM.TIANOCOMPRESSED]
> + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
> + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> + }
> +
> +[Rule.Common.DXE_CORE]
> + FILE DXE_CORE = $(NAMED_GUID) {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +
> +[Rule.Common.UEFI_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.DXE_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.DXE_RUNTIME_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.UEFI_APPLICATION]
> + FILE APPLICATION = $(NAMED_GUID) {
> + UI STRING ="$(MODULE_NAME)" Optional
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + }
> +
> +[Rule.Common.UEFI_DRIVER.BINARY]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional |.depex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_APPLICATION.BINARY]
> + FILE APPLICATION = $(NAMED_GUID) {
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> + }
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> new file mode 100644
> index 0000000..1b639e2
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> @@ -0,0 +1,29 @@
> +# LS1043aRdbPkg.dec
> +# LS1043a board package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + PACKAGE_NAME = LS1043aRdbPkg
> + PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +# Supported Module Types:
> +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> new file mode 100644
> index 0000000..c2701fe
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -0,0 +1,80 @@
> +# LS1043aRdbPkg.dsc
> +#
> +# LS1043ARDB Board package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + #
> + # Defines for default states. These can be changed on the command line.
> + # -D FLAG=VALUE
> + #
> + PLATFORM_NAME = LS1043aRdbPkg
> + PLATFORM_GUID = 60169ec4-d2b4-44f8-825e-f8684fd42e4f
> + OUTPUT_DIRECTORY = Build/LS1043aRdbPkg
> + FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> +
> +!include Platform/NXP/NxpQoriqLs.dsc.inc
> +!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +
> +[LibraryClasses.common]
> + SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> + ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> + IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> + RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
> +
> +[PcdsFixedAtBuild.common]
> +
> + #
> + # LS1043a board Specific PCDs
> + # XX (DRAM - Region 1 2GB)
> + # (NOR - IFC Region 1 512MB)
> + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
> + gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
> + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
> +
> + #
> + # Board Specific Pcds
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
> +
> + #
> + # RTC Pcds
> + #
> + gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
> + gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> + #
> + # Architectural Protocols
> + #
> + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> +
> + Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> + Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> + Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> +
> + ##
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> new file mode 100644
> index 0000000..417303d
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> @@ -0,0 +1,198 @@
> +# LS1043aRdbPkg.fdf
> +#
> +# FLASH layout file for LS1043a board.
> +#
> +# Copyright (c) 2016, Freescale Ltd. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into the Flash Device Image. Each FD section
> +# defines one flash "device" image. A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash" image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +################################################################################
> +
> +[FD.LS1043ARDB_EFI]
> +BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
> +Size = 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
> +ErasePolarity = 1
> +BlockSize = 0x1
> +NumBlocks = 0xED000
> +
> +################################################################################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +#
> +################################################################################
> +0x00000000|0x000ED000
> +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> +FV = FVMAIN_COMPACT
> +
> +!include Platform/NXP/FVRules.fdf.inc
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed within a flash
> +# device file. This section also defines order the components and modules are positioned
> +# within the image. The [FV] section consists of define statements, set statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
> +BlockSize = 0x1
> +NumBlocks = 0 # This FV gets compressed so make it just big enough
> +FvAlignment = 8 # FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF MdeModulePkg/Core/Dxe/DxeMain.inf
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +
> + #
> + # PI DXE Drivers producing Architectural Protocols (EFI Services)
> + #
> + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> +
> + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + INF Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> + INF Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> +
> + INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> +
> + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> +
> + #
> + # Multiple Console IO support
> + #
> + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
> +
> + #
> + # Network modules
> + #
The IPv4-only networking stack is getting deleted from edk2 in the
near future. Please have a look at edk2-platforms commit
dc37ca75fe525b7a86f3e2852b23c06badf272bd for guidance on which changes
would be required.
> + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
> +!if $(NETWORK_IP6_ENABLE) == TRUE
> + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + INF NetworkPkg/TcpDxe/TcpDxe.inf
> + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> +!else
> + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> +!endif
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + INF FatPkg/FatPei/FatPei.inf
> + INF FatPkg/EnhancedFatDxe/Fat.inf
> +
> + #
> + # UEFI application (Shell Embedded Boot Loader)
> + #
> + INF ShellPkg/Application/Shell/Shell.inf
> +
> + #
> + # Bds
> + #
> + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + INF MdeModulePkg/Application/UiApp/UiApp.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment = 8
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF ArmPlatformPkg/PrePi/PeiUniCore.inf
> +
> + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> + }
> diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
> new file mode 100644
> index 0000000..972dadc
> --- /dev/null
> +++ b/Platform/NXP/NxpQoriqLs.dsc.inc
> @@ -0,0 +1,412 @@
> +# @file
> +#
> +# Copyright 2017 NXP.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + #
> + # Defines for default states. These can be changed on the command line.
> + # -D FLAG=VALUE
> + #
> + PLATFORM_VERSION = 0.1
> + DSC_SPECIFICATION = 0x0001000A
1A?
> + SUPPORTED_ARCHITECTURES = AARCH64
> + BUILD_TARGETS = DEBUG|RELEASE
Could you add NOOPT also?
> + SKUID_IDENTIFIER = DEFAULT
> +
> +[LibraryClasses.common]
> + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
> + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
> + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
> + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
> + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
> + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
> + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
> + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
> + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
> +
> + # Networking Requirements
> + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
> + DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
> + UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
> + IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
> +
> + # ARM GIC400 General Interrupt Driver
> + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
> + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
> + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
> + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
> + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
> + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
> + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
> + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
> + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
> + SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
> + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
> + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
> + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
> + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
> + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
> + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
> + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
> + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
> + DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
> + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
> + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
> + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
> + NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
> + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
> + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
> + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
> + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
> + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> +
> +[LibraryClasses.common.SEC]
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
> + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
> + LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
> + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
> + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
> + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
> + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
> +
> + # 1/123 faster than Stm or Vstm version
> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> +
> + # Uncomment to turn on GDB stub in SEC.
> + #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
> +
> +[LibraryClasses.common.PEIM]
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
> + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
> + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> +
> +[LibraryClasses.common.DXE_CORE]
> + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
> + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
> + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
> + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
> +
> +[LibraryClasses.common.DXE_DRIVER]
> + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
> +
> +[LibraryClasses.common.UEFI_APPLICATION]
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
> + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> +
> +[LibraryClasses.common.UEFI_DRIVER]
> + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
> + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
> + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> +
> +[LibraryClasses.common.DXE_RUNTIME_DRIVER]
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> +
> +[LibraryClasses.AARCH64]
> + #
> + # It is not possible to prevent the ARM compiler for generic intrinsic functions.
> + # This library provides the instrinsic functions generate by a given compiler.
> + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
> + #
> + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
> +
> +[BuildOptions]
> + XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7
Do you actually test build with XCODE?
Very cool if you do, but if not, please drop :)
> + GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a
Should be able to drop this, it is now default.
> + RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu cortex-a9
> +
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
> + GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
> + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +
> +[PcdsFeatureFlag.common]
> + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
> + # It could be set FALSE to save size.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
> + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
> +
> + # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
> + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
> + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
> + gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
> +
> +[PcdsDynamicDefault.common]
> + #
> + # Set video resolution for boot options and for text setup.
> + # PlatformDxe can set the former at runtime.
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
> +
> +[PcdsDynamicHii.common.DEFAULT]
> + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
> +
> +[PcdsFixedAtBuild.common]
> + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
> + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
> + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
> + gArmPlatformTokenSpaceGuid.PcdCoreCount|1 # Only one core
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|2000000
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
> + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
> + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
> + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
> + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
> + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
> +
> +!if $(TARGET) == RELEASE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000001
> +!else
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000045
> +!endif
> +
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +
> + #
> + # Optional feature to help prevent EFI memory map fragments
> + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
> + # Values are in EFI Pages (4K). DXE Core will make sure that
> + # at least this much of each type of memory can be allocated
> + # from a single memory range. This way you only end up with
> + # maximum of two fragements for each type in the memory map
> + # (the memory used, and the free memory that was prereserved
> + # but not used).
> + #
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
> +
> + # Serial Terminal
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
> + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
> +
> + # Size of the region reserved for fixed address allocations (Reserved 32MB)
> + gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x08000000
> + gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x0
The above two are unused (and about to be deleted from ArmPkg.dec, so
please drop above three lines).
> + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x94A00000
> + gArmTokenSpaceGuid.PcdCpuResetAddress|0x94A00000
Do you actually use these? (Most platforms don't these days.)
> +
> + # Timer
> + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
> +
> + # We want to use the Shell Libraries but don't want it to initialise
> + # automatically. We initialise the libraries when the command is called by the
> + # Shell.
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> +
> + # Use the serial console for both ConIn & ConOut
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
You can probably delete one of these identical statements.
> + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000
> +!ifdef $(NO_SHELL_PROFILES)
> + gEfiShellPkgTokenSpaceGuid.PcdShellProfileMask|0x00
> +!endif #$(NO_SHELL_PROFILES)
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> + #
> + # SEC
> + #
> + ArmPlatformPkg/PrePi/PeiUniCore.inf
> + MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + }
> +
> + #
> + # DXE
> + #
> + MdeModulePkg/Core/Dxe/DxeMain.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
> + }
> + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + }
> +
> + #
> + # Architectural Protocols
> + #
> + ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> + EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> +
> + # FDT installation
> + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
> + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> + ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
> +
> + #
> + # Networking stack
> + #
Same as for .fdt.
> + MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> + MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
> +!if $(NETWORK_IP6_ENABLE) == TRUE
> + NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + NetworkPkg/TcpDxe/TcpDxe.inf
> + NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> +!else
> + MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> +!endif
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + FatPkg/FatPei/FatPei.inf
> + FatPkg/EnhancedFatDxe/Fat.inf
> +
> + #
> + # Bds
> + #
> + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + MdeModulePkg/Application/UiApp/UiApp.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
> + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
> + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
> + }
> + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> +
> + #
> + # Example Application
> + #
> + MdeModulePkg/Application/HelloWorld/HelloWorld.inf
> + ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> + ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> + ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> + ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> + ShellPkg/Application/Shell/Shell.inf {
> + <LibraryClasses>
> + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
> +!ifndef $(NO_SHELL_PROFILES)
> + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
> +!endif #$(NO_SHELL_PROFILES)
> + }
> +
> + ##
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dec b/Silicon/NXP/LS1043A/LS1043A.dec
> new file mode 100644
> index 0000000..7581424
> --- /dev/null
> +++ b/Silicon/NXP/LS1043A/LS1043A.dec
> @@ -0,0 +1,22 @@
> +# LS1043A.dec
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x0001000A
1A?
> +
> +[Guids.common]
> + gNxpLs1043ATokenSpaceGuid = {0x6834fe45, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> +
> +[Includes]
> + Include
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> new file mode 100644
> index 0000000..8395dfd
> --- /dev/null
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> @@ -0,0 +1,73 @@
> +# LS1043A.dsc
> +# LS1043A Soc package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +[PcdsDynamicDefault.common]
> +
> + #
> + # ARM General Interrupt Controller
> + gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
> +
> +[PcdsFixedAtBuild.common]
> +
> + #
> + # CCSR Address Space and other attached Memories
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
> + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000
> + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> +
> + #
> + # Big Endian IPs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
> +
> +##
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> new file mode 100644
> index 0000000..df64ad6
> --- /dev/null
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -0,0 +1,117 @@
> +# @file.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x0001000A
1A?
> + PACKAGE_VERSION = 0.1
> +
> +[Includes]
> + .
Err, no. Please don't.
/
Leif
> + Include
> +
> +[Guids.common]
> + gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> + gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
> +
> +[PcdsFixedAtBuild.common]
> + #
> + # Pcds for I2C Controller
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002
> +
> + #
> + # Pcds for base address and size
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
> + gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
> + gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
> + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x0|UINT64|0x00000104
> + gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
> + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
> + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
> + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
> + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
> + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0|UINT64|0x0000011A
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0|UINT64|0x0000011B
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0|UINT64|0x0000011C
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0|UINT64|0x0000011D
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x0|UINT64|0x0000011E
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x0|UINT64|0x0000011F
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x00000120
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x00000121
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x00000122
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x00000123
> + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x00000124
> + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x00000125
> + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000126
> + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000127
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000128
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129
> + gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A
> +
> + #
> + # IFC PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
> +
> + #
> + # NV Pcd
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
> + gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211
> +
> + #
> + # Platform PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
> +
> + #
> + # Clock PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
> + gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1
> +
> + #
> + # Pcds to support Big Endian IPs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
> + gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|FALSE|BOOLEAN|0x00000313
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 10/41] Readme : Add Readme.md file.
2018-11-28 15:01 ` [PATCH edk2-platforms 10/41] Readme : Add Readme.md file Meenakshi Aggarwal
@ 2018-12-18 18:41 ` Leif Lindholm
2019-02-01 5:43 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-12-18 18:41 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Wed, Nov 28, 2018 at 08:31:24PM +0530, Meenakshi Aggarwal wrote:
> Readme.md to explain how to build NXP board packages.
>
Could you add a link to this file from top-level Readme.md (towards
the very end)?
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Platform/NXP/Readme.md | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
> create mode 100644 Platform/NXP/Readme.md
>
> diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md
> new file mode 100644
> index 0000000..902bafe
> --- /dev/null
> +++ b/Platform/NXP/Readme.md
> @@ -0,0 +1,24 @@
> +Support for all NXP boards is available in this directory.
> +
> +# How to build
> +
> +1. Set toolchain path.
> +
> + export PATH=<TOOLCHAIN_PATH>/gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-gnu/bin/:$PATH
> +
> +2. Export following variables needed for compilation.
> +
> + export CROSS_COMPILE=aarch64-linux-gnu-
> + export GCC_ARCH_PREFIX=GCC49_AARCH64_PREFIX
> + export GCC49_AARCH64_PREFIX=aarch64-linux-gnu-
> + export PACKAGES_PATH=<EDK2_PATH>/edk2/edk2-platforms
> +
Can you check whether you are happy with the generic build
instructions in the top-level Readme.md and improve those if not?
Then you could reference those rather than repeating.
/
Leif
> +3. Build desired board package
> +
> + source edksetup.sh
> + build -p "path to package's description (.dsc) file" -a AARCH64 -t GCC49 -b DEBUG/RELEASE clean
> +
> + e.g.
> + build -p "$PACKAGES_PATH/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc" -a AARCH64 -t GCC49 -b DEBUG clean
> + build -p "$PACKAGES_PATH/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc" -a AARCH64 -t GCC49 -b DEBUG
> +
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC controller
2018-11-28 15:01 ` [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC controller Meenakshi Aggarwal
@ 2018-12-18 18:45 ` Leif Lindholm
2019-02-01 5:55 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-12-18 18:45 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Wed, Nov 28, 2018 at 08:31:25PM +0530, Meenakshi Aggarwal wrote:
> This header file contain IFC controller timing structure,
> chip select enum and other IFC macros.
Please expand the IFC acronym here (like is done in file header below).
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/Ifc.h | 423 ++++++++++++++++++++++++++++++++++++++++++++++
Please Update at least filename Ifc.h->NxpIfc.h
> 1 file changed, 423 insertions(+)
> create mode 100644 Silicon/NXP/Include/Ifc.h
>
> diff --git a/Silicon/NXP/Include/Ifc.h b/Silicon/NXP/Include/Ifc.h
> new file mode 100644
> index 0000000..6babb22
> --- /dev/null
> +++ b/Silicon/NXP/Include/Ifc.h
> @@ -0,0 +1,423 @@
> +/** @Ifc.h
> +
> + The integrated flash controller (IFC) is used to interface with external asynchronous
> + NAND flash, asynchronous NOR flash, SRAM, generic ASIC memories and EPROM.
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __IFC_H__
> +#define __IFC_H__
Please add NXP_ prefix.
(I am less concerned about the actual defines below.)
> +
> +#include <Library/BaseLib.h>
Is BaseLib.h really used by this file?
If not, please drop it.
> +#include <Uefi.h>
> +
> +#define IFC_BANK_COUNT 4
> +
> +#define IFC_CSPR_REG_LEN 148
> +#define IFC_AMASK_REG_LEN 144
> +#define IFC_CSOR_REG_LEN 144
> +#define IFC_FTIM_REG_LEN 576
> +
> +#define IFC_CSPR_USED_LEN sizeof (IFC_CSPR) * \
> + IFC_BANK_COUNT
> +
> +#define IFC_AMASK_USED_LEN sizeof (IFC_AMASK) * \
> + IFC_BANK_COUNT
> +
> +#define IFC_CSOR_USED_LEN sizeof (IFC_CSOR) * \
> + IFC_BANK_COUNT
> +
> +#define IFC_FTIM_USED_LEN sizeof (IFC_FTIM) * \
> + IFC_BANK_COUNT
> +
> +/* List of commands */
> +#define IFC_NAND_CMD_RESET 0xFF
> +#define IFC_NAND_CMD_READID 0x90
> +#define IFC_NAND_CMD_STATUS 0x70
> +#define IFC_NAND_CMD_READ0 0x00
> +#define IFC_NAND_CMD_READSTART 0x30
> +#define IFC_NAND_CMD_ERASE1 0x60
> +#define IFC_NAND_CMD_ERASE2 0xD0
> +#define IFC_NAND_CMD_SEQIN 0x80
> +#define IFC_NAND_CMD_PAGEPROG 0x10
> +#define MAX_RETRY_COUNT 150000
> +
> +
> +#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
> +
> +/*
> + * NAND Event and Error Status Register (NAND_EVTER_STAT)
> + */
> +
> +/* Operation Complete */
> +#define IFC_NAND_EVTER_STAT_OPC 0x80000000
> +
> +/* Flash Timeout Error */
> +#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
> +
> +/* Write Protect Error */
> +#define IFC_NAND_EVTER_STAT_WPER 0x04000000
> +
> +/* ECC Error */
> +#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
> +
> +/*
> + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
> + */
> +
> +/* NAND Machine specific opcodes OP0-OP14*/
> +#define IFC_NAND_FIR0_OP0 0xFC000000
> +#define IFC_NAND_FIR0_OP0_SHIFT 26
> +#define IFC_NAND_FIR0_OP1 0x03F00000
> +#define IFC_NAND_FIR0_OP1_SHIFT 20
> +#define IFC_NAND_FIR0_OP2 0x000FC000
> +#define IFC_NAND_FIR0_OP2_SHIFT 14
> +#define IFC_NAND_FIR0_OP3 0x00003F00
> +#define IFC_NAND_FIR0_OP3_SHIFT 8
> +#define IFC_NAND_FIR0_OP4 0x000000FC
> +#define IFC_NAND_FIR0_OP4_SHIFT 2
> +#define IFC_NAND_FIR1_OP5 0xFC000000
> +#define IFC_NAND_FIR1_OP5_SHIFT 26
> +#define IFC_NAND_FIR1_OP6 0x03F00000
> +#define IFC_NAND_FIR1_OP6_SHIFT 20
> +#define IFC_NAND_FIR1_OP7 0x000FC000
> +#define IFC_NAND_FIR1_OP7_SHIFT 14
> +#define IFC_NAND_FIR1_OP8 0x00003F00
> +#define IFC_NAND_FIR1_OP8_SHIFT 8
> +#define IFC_NAND_FIR1_OP9 0x000000FC
> +#define IFC_NAND_FIR1_OP9_SHIFT 2
> +#define IFC_NAND_FIR2_OP10 0xFC000000
> +#define IFC_NAND_FIR2_OP10_SHIFT 26
> +#define IFC_NAND_FIR2_OP11 0x03F00000
> +#define IFC_NAND_FIR2_OP11_SHIFT 20
> +#define IFC_NAND_FIR2_OP12 0x000FC000
> +#define IFC_NAND_FIR2_OP12_SHIFT 14
> +#define IFC_NAND_FIR2_OP13 0x00003F00
> +#define IFC_NAND_FIR2_OP13_SHIFT 8
> +#define IFC_NAND_FIR2_OP14 0x000000FC
> +#define IFC_NAND_FIR2_OP14_SHIFT 2
> +
> +/*
> + * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
> + */
> +
> +/* General purpose FCM flash command bytes CMD0-CMD7 */
> +#define IFC_NAND_FCR0_CMD0 0xFF000000
> +#define IFC_NAND_FCR0_CMD0_SHIFT 24
> +#define IFC_NAND_FCR0_CMD1 0x00FF0000
> +#define IFC_NAND_FCR0_CMD1_SHIFT 16
> +#define IFC_NAND_FCR0_CMD2 0x0000FF00
> +#define IFC_NAND_FCR0_CMD2_SHIFT 8
> +#define IFC_NAND_FCR0_CMD3 0x000000FF
> +#define IFC_NAND_FCR0_CMD3_SHIFT 0
> +#define IFC_NAND_FCR1_CMD4 0xFF000000
> +#define IFC_NAND_FCR1_CMD4_SHIFT 24
> +#define IFC_NAND_FCR1_CMD5 0x00FF0000
> +#define IFC_NAND_FCR1_CMD5_SHIFT 16
> +#define IFC_NAND_FCR1_CMD6 0x0000FF00
> +#define IFC_NAND_FCR1_CMD6_SHIFT 8
> +#define IFC_NAND_FCR1_CMD7 0x000000FF
> +#define IFC_NAND_FCR1_CMD7_SHIFT 0
> +
> +/* Timing registers for NAND Flash */
> +
> +#define IFC_FTIM0_NAND_TCCST_SHIFT 25
> +#define IFC_FTIM0_NAND_TCCST(n) ((n) << IFC_FTIM0_NAND_TCCST_SHIFT)
> +#define IFC_FTIM0_NAND_TWP_SHIFT 16
> +#define IFC_FTIM0_NAND_TWP(n) ((n) << IFC_FTIM0_NAND_TWP_SHIFT)
> +#define IFC_FTIM0_NAND_TWCHT_SHIFT 8
> +#define IFC_FTIM0_NAND_TWCHT(n) ((n) << IFC_FTIM0_NAND_TWCHT_SHIFT)
> +#define IFC_FTIM0_NAND_TWH_SHIFT 0
> +#define IFC_FTIM0_NAND_TWH(n) ((n) << IFC_FTIM0_NAND_TWH_SHIFT)
> +#define IFC_FTIM1_NAND_TADLE_SHIFT 24
> +#define IFC_FTIM1_NAND_TADLE(n) ((n) << IFC_FTIM1_NAND_TADLE_SHIFT)
> +#define IFC_FTIM1_NAND_TWBE_SHIFT 16
> +#define IFC_FTIM1_NAND_TWBE(n) ((n) << IFC_FTIM1_NAND_TWBE_SHIFT)
> +#define IFC_FTIM1_NAND_TRR_SHIFT 8
> +#define IFC_FTIM1_NAND_TRR(n) ((n) << IFC_FTIM1_NAND_TRR_SHIFT)
> +#define IFC_FTIM1_NAND_TRP_SHIFT 0
> +#define IFC_FTIM1_NAND_TRP(n) ((n) << IFC_FTIM1_NAND_TRP_SHIFT)
> +#define IFC_FTIM2_NAND_TRAD_SHIFT 21
> +#define IFC_FTIM2_NAND_TRAD(n) ((n) << IFC_FTIM2_NAND_TRAD_SHIFT)
> +#define IFC_FTIM2_NAND_TREH_SHIFT 11
> +#define IFC_FTIM2_NAND_TREH(n) ((n) << IFC_FTIM2_NAND_TREH_SHIFT)
> +#define IFC_FTIM2_NAND_TWHRE_SHIFT 0
> +#define IFC_FTIM2_NAND_TWHRE(n) ((n) << IFC_FTIM2_NAND_TWHRE_SHIFT)
> +#define IFC_FTIM3_NAND_TWW_SHIFT 24
> +#define IFC_FTIM3_NAND_TWW(n) ((n) << IFC_FTIM3_NAND_TWW_SHIFT)
> +
> +/*
> + * Flash ROW and COL Address Register (ROWn, COLn)
> + */
> +
> +/* Main/spare region locator */
> +#define IFC_NAND_COL_MS 0x80000000
> +
> +/* Column Address */
> +#define IFC_NAND_COL_CA_MASK 0x00000FFF
> +
> +#define NAND_STATUS_WP 0x80
> +
> +/*
> + * NAND Event and Error Enable Register (NAND_EVTER_EN)
> + */
> +
> +/* Operation complete event enable */
> +#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
> +
> +/* Page read complete event enable */
> +#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
> +
> +/* Flash Timeout error enable */
> +#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
> +
> +/* Write Protect error enable */
> +#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
> +
> +/* ECC error logging enable */
> +#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
> +
> +/*
> + * CSPR - Chip Select Property Register
> + */
> +
> +#define IFC_CSPR_BA 0xFFFF0000
> +#define IFC_CSPR_BA_SHIFT 16
> +#define IFC_CSPR_PORT_SIZE 0x00000180
> +#define IFC_CSPR_PORT_SIZE_SHIFT 7
> +
> +// Port Size 8 bit
> +#define IFC_CSPR_PORT_SIZE_8 0x00000080
> +
> +// Port Size 16 bit
> +#define IFC_CSPR_PORT_SIZE_16 0x00000100
> +
> +// Port Size 32 bit
> +#define IFC_CSPR_PORT_SIZE_32 0x00000180
> +
> +// Write Protect
> +#define IFC_CSPR_WP 0x00000040
> +#define IFC_CSPR_WP_SHIFT 6
> +
> +// Machine Select
> +#define IFC_CSPR_MSEL 0x00000006
> +#define IFC_CSPR_MSEL_SHIFT 1
> +
> +// NOR
> +#define IFC_CSPR_MSEL_NOR 0x00000000
> +
> +/* NAND */
> +#define IFC_CSPR_MSEL_NAND 0x00000002
> +
> +/* GPCM */
> +#define IFC_CSPR_MSEL_GPCM 0x00000004
> +
> +// Bank Valid
> +#define IFC_CSPR_V 0x00000001
> +#define IFC_CSPR_V_SHIFT 0
> +
> +/*
> + * Chip Select Option Register - NOR Flash Mode
> + */
> +
> +// Enable Address shift Mode
> +#define IFC_CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
> +
> +// Page Read Enable from NOR device
> +#define IFC_CSOR_NOR_PGRD_EN 0x10000000
> +
> +// AVD Toggle Enable during Burst Program
> +#define IFC_CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
> +
> +// Address Data Multiplexing Shift
> +#define IFC_CSOR_NOR_ADM_MASK 0x0003E000
> +#define IFC_CSOR_NOR_ADM_SHIFT_SHIFT 13
> +#define IFC_CSOR_NOR_ADM_SHIFT(n) ((n) << IFC_CSOR_NOR_ADM_SHIFT_SHIFT)
> +
> +// Type of the NOR device hooked
> +#define IFC_CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
> +#define IFC_CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
> +
> +// Time for Read Enable High to Output High Impedance
> +#define IFC_CSOR_NOR_TRHZ_MASK 0x0000001C
> +#define IFC_CSOR_NOR_TRHZ_SHIFT 2
> +#define IFC_CSOR_NOR_TRHZ_20 0x00000000
> +#define IFC_CSOR_NOR_TRHZ_40 0x00000004
> +#define IFC_CSOR_NOR_TRHZ_60 0x00000008
> +#define IFC_CSOR_NOR_TRHZ_80 0x0000000C
> +#define IFC_CSOR_NOR_TRHZ_100 0x00000010
> +
> +// Buffer control disable
> +#define IFC_CSOR_NOR_BCTLD 0x00000001
> +
> +/*
> + * Chip Select Option Register IFC_NAND Machine
> + */
> +
> +/* Enable ECC Encoder */
> +#define IFC_CSOR_NAND_ECC_ENC_EN 0x80000000
> +#define IFC_CSOR_NAND_ECC_MODE_MASK 0x30000000
> +
> +/* 4 bit correction per 520 Byte sector */
> +#define IFC_CSOR_NAND_ECC_MODE_4 0x00000000
> +
> +/* 8 bit correction per 528 Byte sector */
> +#define IFC_CSOR_NAND_ECC_MODE_8 0x10000000
> +
> +/* Enable ECC Decoder */
> +#define IFC_CSOR_NAND_ECC_DEC_EN 0x04000000
> +
> +/* Row Address Length */
> +#define IFC_CSOR_NAND_RAL_MASK 0x01800000
> +#define IFC_CSOR_NAND_RAL_SHIFT 20
> +#define IFC_CSOR_NAND_RAL_1 0x00000000
> +#define IFC_CSOR_NAND_RAL_2 0x00800000
> +#define IFC_CSOR_NAND_RAL_3 0x01000000
> +#define IFC_CSOR_NAND_RAL_4 0x01800000
> +
> +/* Page Size 512b, 2k, 4k */
> +#define IFC_CSOR_NAND_PGS_MASK 0x00180000
> +#define IFC_CSOR_NAND_PGS_SHIFT 16
> +#define IFC_CSOR_NAND_PGS_512 0x00000000
> +#define IFC_CSOR_NAND_PGS_2K 0x00080000
> +#define IFC_CSOR_NAND_PGS_4K 0x00100000
> +#define IFC_CSOR_NAND_PGS_8K 0x00180000
> +
> +/* Spare region Size */
> +#define IFC_CSOR_NAND_SPRZ_MASK 0x0000E000
> +#define IFC_CSOR_NAND_SPRZ_SHIFT 13
> +#define IFC_CSOR_NAND_SPRZ_16 0x00000000
> +#define IFC_CSOR_NAND_SPRZ_64 0x00002000
> +#define IFC_CSOR_NAND_SPRZ_128 0x00004000
> +#define IFC_CSOR_NAND_SPRZ_210 0x00006000
> +#define IFC_CSOR_NAND_SPRZ_218 0x00008000
> +#define IFC_CSOR_NAND_SPRZ_224 0x0000A000
> +#define IFC_CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
> +
> +/* Pages Per Block */
> +#define IFC_CSOR_NAND_PB_MASK 0x00000700
> +#define IFC_CSOR_NAND_PB_SHIFT 8
> +#define IFC_CSOR_NAND_PB(n) (n-5) << IFC_CSOR_NAND_PB_SHIFT
> +
> +/* Time for Read Enable High to Output High Impedance */
> +#define IFC_CSOR_NAND_TRHZ_MASK 0x0000001C
> +#define IFC_CSOR_NAND_TRHZ_SHIFT 2
> +#define IFC_CSOR_NAND_TRHZ_20 0x00000000
> +#define IFC_CSOR_NAND_TRHZ_40 0x00000004
> +#define IFC_CSOR_NAND_TRHZ_60 0x00000008
> +#define IFC_CSOR_NAND_TRHZ_80 0x0000000C
> +#define IFC_CSOR_NAND_TRHZ_100 0x00000010
> +
> +/*
> + * FTIM0 - NOR Flash Mode
> + */
> +#define IFC_FTIM0_NOR 0xF03F3F3F
> +#define IFC_FTIM0_NOR_TACSE_SHIFT 28
> +#define IFC_FTIM0_NOR_TACSE(n) ((n) << IFC_FTIM0_NOR_TACSE_SHIFT)
> +#define IFC_FTIM0_NOR_TEADC_SHIFT 16
> +#define IFC_FTIM0_NOR_TEADC(n) ((n) << IFC_FTIM0_NOR_TEADC_SHIFT)
> +#define IFC_FTIM0_NOR_TAVDS_SHIFT 8
> +#define IFC_FTIM0_NOR_TAVDS(n) ((n) << IFC_FTIM0_NOR_TAVDS_SHIFT)
> +#define IFC_FTIM0_NOR_TEAHC_SHIFT 0
> +#define IFC_FTIM0_NOR_TEAHC(n) ((n) << IFC_FTIM0_NOR_TEAHC_SHIFT)
> +
> +/*
> + * FTIM1 - NOR Flash Mode
> + */
> +#define IFC_FTIM1_NOR 0xFF003F3F
> +#define IFC_FTIM1_NOR_TACO_SHIFT 24
> +#define IFC_FTIM1_NOR_TACO(n) ((n) << IFC_FTIM1_NOR_TACO_SHIFT)
> +#define IFC_FTIM1_NOR_TRAD_NOR_SHIFT 8
> +#define IFC_FTIM1_NOR_TRAD_NOR(n) ((n) << IFC_FTIM1_NOR_TRAD_NOR_SHIFT)
> +#define IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
> +#define IFC_FTIM1_NOR_TSEQRAD_NOR(n) ((n) << IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT)
> +
> +/*
> + * FTIM2 - NOR Flash Mode
> + */
> +#define IFC_FTIM2_NOR 0x0F3CFCFF
> +#define IFC_FTIM2_NOR_TCS_SHIFT 24
> +#define IFC_FTIM2_NOR_TCS(n) ((n) << IFC_FTIM2_NOR_TCS_SHIFT)
> +#define IFC_FTIM2_NOR_TCH_SHIFT 18
> +#define IFC_FTIM2_NOR_TCH(n) ((n) << IFC_FTIM2_NOR_TCH_SHIFT)
> +#define IFC_FTIM2_NOR_TWPH_SHIFT 10
> +#define IFC_FTIM2_NOR_TWPH(n) ((n) << IFC_FTIM2_NOR_TWPH_SHIFT)
> +#define IFC_FTIM2_NOR_TWP_SHIFT 0
> +#define IFC_FTIM2_NOR_TWP(n) ((n) << IFC_FTIM2_NOR_TWP_SHIFT)
> +
> +/*
> + * FTIM0 - Normal GPCM Mode
> + */
> +#define IFC_FTIM0_GPCM 0xF03F3F3F
> +#define IFC_FTIM0_GPCM_TACSE_SHIFT 28
> +#define IFC_FTIM0_GPCM_TACSE(n) ((n) << IFC_FTIM0_GPCM_TACSE_SHIFT)
> +#define IFC_FTIM0_GPCM_TEADC_SHIFT 16
> +#define IFC_FTIM0_GPCM_TEADC(n) ((n) << IFC_FTIM0_GPCM_TEADC_SHIFT)
> +#define IFC_FTIM0_GPCM_TAVDS_SHIFT 8
> +#define IFC_FTIM0_GPCM_TAVDS(n) ((n) << IFC_FTIM0_GPCM_TAVDS_SHIFT)
> +#define IFC_FTIM0_GPCM_TEAHC_SHIFT 0
> +#define IFC_FTIM0_GPCM_TEAHC(n) ((n) << IFC_FTIM0_GPCM_TEAHC_SHIFT)
> +
> +/*
> + * FTIM1 - Normal GPCM Mode
> + */
> +#define IFC_FTIM1_GPCM 0xFF003F00
> +#define IFC_FTIM1_GPCM_TACO_SHIFT 24
> +#define IFC_FTIM1_GPCM_TACO(n) ((n) << IFC_FTIM1_GPCM_TACO_SHIFT)
> +#define IFC_FTIM1_GPCM_TRAD_SHIFT 8
> +#define IFC_FTIM1_GPCM_TRAD(n) ((n) << IFC_FTIM1_GPCM_TRAD_SHIFT)
> +
> +/*
> + * FTIM2 - Normal GPCM Mode
> + */
> +#define IFC_FTIM2_GPCM 0x0F3C00FF
> +#define IFC_FTIM2_GPCM_TCS_SHIFT 24
> +#define IFC_FTIM2_GPCM_TCS(n) ((n) << IFC_FTIM2_GPCM_TCS_SHIFT)
> +#define IFC_FTIM2_GPCM_TCH_SHIFT 18
> +#define IFC_FTIM2_GPCM_TCH(n) ((n) << IFC_FTIM2_GPCM_TCH_SHIFT)
> +#define IFC_FTIM2_GPCM_TWP_SHIFT 0
> +#define IFC_FTIM2_GPCM_TWP(n) ((n) << IFC_FTIM2_GPCM_TWP_SHIFT)
> +
> +/* Convert an address into the right format for the CSPR Registers */
> +#define IFC_CSPR_PHYS_ADDR(x) (((UINTN)x) & 0xffff0000)
> +
> +/*
> + * Address Mask Register
> + */
> +#define IFC_AMASK_MASK 0xFFFF0000
> +#define IFC_AMASK_SHIFT 16
> +#define IFC_AMASK(n) (IFC_AMASK_MASK << \
> + (HighBitSet32(n) - IFC_AMASK_SHIFT))
> +
> +typedef enum {
> + IFC_CS0 = 0,
> + IFC_CS1,
> + IFC_CS2,
> + IFC_CS3,
> + IFC_CS4,
> + IFC_CS5,
> + IFC_CS6,
> + IFC_CS7,
> + IFC_CS_MAX,
CamelCase for member names, please.
/
Leif
> +} IFC_CHIP_SEL;
> +
> +typedef struct {
> + UINT32 Ftim[IFC_BANK_COUNT];
> + UINT32 CsprExt;
> + UINT32 Cspr;
> + UINT32 Csor;
> + UINT32 Amask;
> + UINT8 CS;
> +} IFC_TIMINGS;
> +
> +#endif //__IFC_H__
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 12/41] LS1043/BoardLib : Add support for LS1043 BoardLib.
2018-11-28 15:01 ` [PATCH edk2-platforms 12/41] LS1043/BoardLib : Add support for LS1043 BoardLib Meenakshi Aggarwal
@ 2018-12-18 18:50 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-18 18:50 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Wed, Nov 28, 2018 at 08:31:26PM +0530, Meenakshi Aggarwal wrote:
> BoardLib will contain functions specific for LS1043aRdb board.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Sorry, I do have a few more (trivial) comments.
But feel free to keep the reviewed-by if you address them.
> ---
> .../NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h | 109 +++++++++++++++++++++
Ifc->NxpIfc?
> .../NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c | 69 +++++++++++++
> .../LS1043aRdbPkg/Library/BoardLib/BoardLib.inf | 31 ++++++
> 3 files changed, 209 insertions(+)
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h b/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
> new file mode 100644
> index 0000000..261867a
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Include/IfcBoardSpecific.h
> @@ -0,0 +1,109 @@
> +/** IfcBoardSpecificLib.h
> +
> + IFC Flash Board Specific Macros and structure
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +#ifndef __IFC__BOARD_SPECIFIC_H__
> +#define __IFC__BOARD_SPECIFIC_H__
NXP_ prefix?
> +
> +#include <Ifc.h>
> +
> +// On board flash support
> +#define IFC_NAND_BUF_BASE 0x7E800000
> +
> +// On board Inegrated flash Controller chip select configuration
> +#define IFC_NOR_CS IFC_CS0
> +#define IFC_NAND_CS IFC_CS1
> +#define IFC_FPGA_CS IFC_CS2
> +
> +// board-specific NAND timing
> +#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x7) | \
> + IFC_FTIM0_NAND_TWP(0x18) | \
> + IFC_FTIM0_NAND_TWCHT(0x7) | \
> + IFC_FTIM0_NAND_TWH(0xa))
> +
> +#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x32) | \
> + IFC_FTIM1_NAND_TWBE(0x39) | \
> + IFC_FTIM1_NAND_TRR(0xe) | \
> + IFC_FTIM1_NAND_TRP(0x18))
> +
> +#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0xf) | \
> + IFC_FTIM2_NAND_TREH(0xa) | \
> + IFC_FTIM2_NAND_TWHRE(0x1e))
> +
> +#define NAND_FTIM3 0x0
> +
> +#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BUF_BASE) \
> + | IFC_CSPR_PORT_SIZE_8 \
> + | IFC_CSPR_MSEL_NAND \
> + | IFC_CSPR_V)
> +
> +#define NAND_CSPR_EXT 0x0
> +#define NAND_AMASK 0xFFFF0000
> +
> +#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
> + | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
> + | IFC_CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
> + | IFC_CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
> + | IFC_CSOR_NAND_PGS_2K /* Page Size = 2K */ \
> + | IFC_CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
> + | IFC_CSOR_NAND_PB(6)) /* 2^6 Pages Per Block */
> +
> +// board-specific NOR timing
> +#define NOR_FTIM0 (IFC_FTIM0_NOR_TACSE(0x1) | \
> + IFC_FTIM0_NOR_TEADC(0x1) | \
> + IFC_FTIM0_NOR_TAVDS(0x0) | \
> + IFC_FTIM0_NOR_TEAHC(0xc))
> +#define NOR_FTIM1 (IFC_FTIM1_NOR_TACO(0x1c) | \
> + IFC_FTIM1_NOR_TRAD_NOR(0xb) |\
> + IFC_FTIM1_NOR_TSEQRAD_NOR(0x9))
> +#define NOR_FTIM2 (IFC_FTIM2_NOR_TCS(0x1) | \
> + IFC_FTIM2_NOR_TCH(0x4) | \
> + IFC_FTIM2_NOR_TWPH(0x8) | \
> + IFC_FTIM2_NOR_TWP(0x10))
> +#define NOR_FTIM3 0x0
> +
> +#define NOR_CSPR (IFC_CSPR_PHYS_ADDR(FixedPcdGet64 (PcdIfcRegion1BaseAddr)) \
> + | IFC_CSPR_PORT_SIZE_16 \
> + | IFC_CSPR_MSEL_NOR \
> + | IFC_CSPR_V)
> +
> +#define NOR_CSPR_EXT 0x0
> +#define NOR_AMASK IFC_AMASK(128*1024*1024)
> +#define NOR_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) | \
> + IFC_CSOR_NOR_TRHZ_80)
> +
> +// board-specific fpga timing
> +#define FPGA_BASE_PHYS 0x7fb00000
> +#define FPGA_CSPR_EXT 0x0
> +#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
> + IFC_CSPR_PORT_SIZE_8 | \
> + IFC_CSPR_MSEL_GPCM | \
> + IFC_CSPR_V)
> +
> +#define FPGA_AMASK IFC_AMASK(64 * 1024)
> +#define FPGA_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) | \
> + IFC_CSOR_NOR_NOR_MODE_AVD_NOR | \
> + IFC_CSOR_NOR_TRHZ_80)
> +
> +#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0xf) | \
> + IFC_FTIM0_GPCM_TEADC(0xf) | \
> + IFC_FTIM0_GPCM_TEAHC(0xf))
> +#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \
> + IFC_FTIM1_GPCM_TRAD(0x3f))
> +#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \
> + IFC_FTIM2_GPCM_TCH(0xf) | \
> + IFC_FTIM2_GPCM_TWP(0xff))
> +#define FPGA_FTIM3 0x0
> +
> +#endif //__IFC__BOARD_SPECIFIC_H__
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
> new file mode 100644
> index 0000000..a101a8d
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.c
> @@ -0,0 +1,69 @@
> +/** @file
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <IfcBoardSpecific.h>
> +
> +VOID
> +GetIfcNorFlashTimings (
> + IN IFC_TIMINGS * NorIfcTimings
> + )
> +{
> + NorIfcTimings->Ftim[0] = NOR_FTIM0;
> + NorIfcTimings->Ftim[1] = NOR_FTIM1;
> + NorIfcTimings->Ftim[2] = NOR_FTIM2;
> + NorIfcTimings->Ftim[3] = NOR_FTIM3;
> + NorIfcTimings->Cspr = NOR_CSPR;
> + NorIfcTimings->CsprExt = NOR_CSPR_EXT;
> + NorIfcTimings->Amask = NOR_AMASK;
> + NorIfcTimings->Csor = NOR_CSOR;
> + NorIfcTimings->CS = IFC_NOR_CS;
> +
> + return ;
Please drop the space before ;.
/
Leif
> +}
> +
> +VOID
> +GetIfcFpgaTimings (
> + IN IFC_TIMINGS *FpgaIfcTimings
> + )
> +{
> + FpgaIfcTimings->Ftim[0] = FPGA_FTIM0;
> + FpgaIfcTimings->Ftim[1] = FPGA_FTIM1;
> + FpgaIfcTimings->Ftim[2] = FPGA_FTIM2;
> + FpgaIfcTimings->Ftim[3] = FPGA_FTIM3;
> + FpgaIfcTimings->Cspr = FPGA_CSPR;
> + FpgaIfcTimings->CsprExt = FPGA_CSPR_EXT;
> + FpgaIfcTimings->Amask = FPGA_AMASK;
> + FpgaIfcTimings->Csor = FPGA_CSOR;
> + FpgaIfcTimings->CS = IFC_FPGA_CS;
> +
> + return;
> +}
> +
> +VOID
> +GetIfcNandFlashTimings (
> + IN IFC_TIMINGS * NandIfcTimings
> + )
> +{
> + NandIfcTimings->Ftim[0] = NAND_FTIM0;
> + NandIfcTimings->Ftim[1] = NAND_FTIM1;
> + NandIfcTimings->Ftim[2] = NAND_FTIM2;
> + NandIfcTimings->Ftim[3] = NAND_FTIM3;
> + NandIfcTimings->Cspr = NAND_CSPR;
> + NandIfcTimings->CsprExt = NAND_CSPR_EXT;
> + NandIfcTimings->Amask = NAND_AMASK;
> + NandIfcTimings->Csor = NAND_CSOR;
> + NandIfcTimings->CS = IFC_NAND_CS;
> +
> + return;
> +}
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
> new file mode 100644
> index 0000000..7d2702b
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
> @@ -0,0 +1,31 @@
> +# @file
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = BoardLib
> + FILE_GUID = 8ecefc8f-a2c4-4091-b80f-92da7c4ab37f
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = BoardLib
> +
> +[Sources.common]
> + BoardLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[FixedPcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 13/41] Silicon/NXP : Add support of IfcLib
2018-11-28 15:01 ` [PATCH edk2-platforms 13/41] Silicon/NXP : Add support of IfcLib Meenakshi Aggarwal
@ 2018-12-19 13:25 ` Leif Lindholm
2019-02-01 6:53 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-12-19 13:25 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Wed, Nov 28, 2018 at 08:31:27PM +0530, Meenakshi Aggarwal wrote:
> Add support of IfcLib, it will be used to perform
> any operation on IFC controller.
Expand acronym.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/Library/IfcLib.h | 26 +++++
> Silicon/NXP/Library/IfcLib/IfcLib.c | 150 +++++++++++++++++++++++++++
> Silicon/NXP/Library/IfcLib/IfcLib.h | 190 ++++++++++++++++++++++++++++++++++
> Silicon/NXP/Library/IfcLib/IfcLib.inf | 38 +++++++
Names Ifc -> NxpIfc please.
> Silicon/NXP/NxpQoriqLs.dec | 1 +
> 5 files changed, 405 insertions(+)
> create mode 100644 Silicon/NXP/Include/Library/IfcLib.h
> create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.c
> create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.h
> create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.inf
>
> diff --git a/Silicon/NXP/Include/Library/IfcLib.h b/Silicon/NXP/Include/Library/IfcLib.h
> new file mode 100644
> index 0000000..8d2c151
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/IfcLib.h
> @@ -0,0 +1,26 @@
> +/** @IfcLib.h
> +
> + The integrated flash controller (IFC) is used to interface with external asynchronous
> + NAND flash, asynchronous NOR flash, SRAM, generic ASIC memories and EPROM.
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __IFC_LIB_H__
> +#define __IFC_LIB_H__
Header guard NXP_ (and/or QORIQ_) prefix.
> +
> +VOID
> +IfcInit (
> + VOID
> + );
> +
> +#endif //__IFC_LIB_H__
> diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.c b/Silicon/NXP/Library/IfcLib/IfcLib.c
> new file mode 100644
> index 0000000..8cf02ae
> --- /dev/null
> +++ b/Silicon/NXP/Library/IfcLib/IfcLib.c
> @@ -0,0 +1,150 @@
> +/** @IfcLib.c
> +
> + The integrated flash controller (IFC) is used to interface with external asynchronous/
> + synchronous NAND flash, asynchronous NOR flash, SRAM, generic ASIC memory and
> + EPROM.
> + It has eight chip-selects, to which a maximum of eight flash devices can be attached,
> + although only one of these can be accessed at any given time.
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/IoAccessLib.h>
> +#include "IfcLib.h"
> +
> +STATIC MMIO_OPERATIONS_32 *mMmioOps;
> +
> +STATIC UINT8 mNandCS;
> +STATIC UINT8 mNorCS;
> +STATIC UINT8 mFpgaCS;
> +
> +VOID
Local only?
If so, STATIC please.
> +SetTimings (
> + IN UINT8 CS,
> + IN IFC_TIMINGS IfcTimings
> + )
> +{
> + IFC_REGS* IfcRegs;
> +
> + IfcRegs = (IFC_REGS*)PcdGet64 (PcdIfcBaseAddr);
> +
> + // Configure Extended chip select property registers
> + mMmioOps->Write ((UINTN)&IfcRegs->CsprCs[CS].CsprExt, IfcTimings.CsprExt);
> +
> + // Configure Fpga timing registers
> + mMmioOps->Write ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM0], IfcTimings.Ftim[0]);
> + mMmioOps->Write ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM1], IfcTimings.Ftim[1]);
> + mMmioOps->Write ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM2], IfcTimings.Ftim[2]);
> + mMmioOps->Write ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM3], IfcTimings.Ftim[3]);
> +
> + // Configure chip select option registers
> + mMmioOps->Write ((UINTN)&IfcRegs->CsprCs[CS].Cspr, IfcTimings.Cspr);
> +
> + // Configure address mask registers
> + mMmioOps->Write ((UINTN)&IfcRegs->AmaskCs[CS].Amask, IfcTimings.Amask);
> +
> + // Configure chip select property registers
> + mMmioOps->Write ((UINTN)&IfcRegs->CsorCs[CS].Csor, IfcTimings.Csor);
> +
> + return;
> +}
> +
> +VOID
Local only?
If so, STATIC please.
> +NandInit(
> + VOID
> + )
> +{
> + IFC_REGS* IfcRegs;
> + IFC_TIMINGS NandIfcTimings;
> +
> + IfcRegs = (IFC_REGS*)PcdGet64 (PcdIfcBaseAddr);
> +
> + // Get Nand Flash Timings
> + GetIfcNandFlashTimings (&NandIfcTimings);
> +
> + // Validate chip select
> + if (NandIfcTimings.CS < IFC_CS_MAX) {
> + mNandCS = NandIfcTimings.CS;
> +
> + // clear event registers
> + mMmioOps->Write ((UINTN)&IfcRegs->IfcNand.PgrdcmplEvtStat, ~0U);
> +
> + mMmioOps->Write ((UINTN)&IfcRegs->IfcNand.NandEvterStat, ~0U);
> +
> + // Enable error and event for any detected errors
> + mMmioOps->Write ((UINTN)&IfcRegs->IfcNand.NandEvterEn,
> + IFC_NAND_EVTER_EN_OPC_EN |
Indentation should be to function name, not struct name.
(Please address throughout.)
> + IFC_NAND_EVTER_EN_PGRDCMPL_EN |
> + IFC_NAND_EVTER_EN_FTOER_EN |
> + IFC_NAND_EVTER_EN_WPER_EN);
> + mMmioOps->Write ((UINTN)&IfcRegs->IfcNand.Ncfgr, 0x0);
> +
> + SetTimings (mNandCS, NandIfcTimings);
> + }
> +
> + return;
> +}
> +
> +VOID
Local only?
If so, STATIC please.
> +FpgaInit (
> + VOID
> + )
> +{
> + IFC_TIMINGS FpgaIfcTimings;
> +
> + // Get Fpga Flash Timings
> + GetIfcFpgaTimings (&FpgaIfcTimings);
> +
> + // Validate chip select
> + if (FpgaIfcTimings.CS < IFC_CS_MAX) {
> + mFpgaCS = FpgaIfcTimings.CS;
> + SetTimings (mFpgaCS, FpgaIfcTimings);
> + }
> +
> + return;
> +}
> +
> +VOID
> +NorInit (
> + VOID
> + )
> +{
> + IFC_TIMINGS NorIfcTimings;
> +
> + // Get NOR Flash Timings
> + GetIfcNorFlashTimings (&NorIfcTimings);
> +
> + // Validate chip select
> + if (NorIfcTimings.CS < IFC_CS_MAX) {
> + mNorCS = NorIfcTimings.CS;
> + SetTimings (mNorCS, NorIfcTimings);
> + }
> +
> + return;
> +}
> +
> +//
> +// IFC has NOR , NAND and FPGA
> +//
> +VOID
> +IfcInit (
> + VOID
> + )
> +{
> + mMmioOps = GetMmioOperations32 (FixedPcdGetBool (PcdIfcBigEndian));
> +
> + NorInit();
> + NandInit();
> + FpgaInit();
> +
> + return;
> +}
> diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.h b/Silicon/NXP/Library/IfcLib/IfcLib.h
> new file mode 100644
> index 0000000..38ce247
> --- /dev/null
> +++ b/Silicon/NXP/Library/IfcLib/IfcLib.h
> @@ -0,0 +1,190 @@
> +/** @IfcLib.h
> +
> + The integrated flash controller (IFC) is used to interface with external asynchronous/
> + synchronous NAND flash, asynchronous NOR flash, SRAM, generic ASIC memory and
> + EPROM.
> + It has eight chip-selects, to which a maximum of eight flash devices can be attached,
> + although only one of these can be accessed at any given time.
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __IFC_LIB_H__
> +#define __IFC_LIB_H__
NXP_ and/or QORIQ_ prefix?
> +
> +#include <Ifc.h>
> +#include <Uefi.h>
> +
> +#define IFC_NAND_RESERVED_SIZE FixedPcdGet32 (PcdIfcNandReservedSize)
> +
> +typedef enum {
> + IFC_FTIM0 = 0,
> + IFC_FTIM1,
> + IFC_FTIM2,
> + IFC_FTIM3,
CamelCase member names please, throughout.
> +} IFC_FTIMS;
> +
> +typedef struct {
> + UINT32 CsprExt;
> + UINT32 Cspr;
> + UINT32 Res;
> +} IFC_CSPR;
> +
> +typedef struct {
> + UINT32 Amask;
AddressMask?
> + UINT32 Res[0x2];
Is this "Reserved"?
If so, please write out in full.
Also please drop the hex prefix.
Apples throughout.
> +} IFC_AMASK;
> +
> +typedef struct {
> + UINT32 Csor;
> + UINT32 CsorExt;
> + UINT32 Res;
> +} IFC_CSOR;
> +
> +typedef struct {
> + UINT32 Ftim[4];
> + UINT32 Res[0x8];
> +}IFC_FTIM ;
> +
> +typedef struct {
> + UINT32 Ncfgr;
> + UINT32 Res1[0x4];
> + UINT32 NandFcr0;
> + UINT32 NandFcr1;
> + UINT32 Res2[0x8];
> + UINT32 Row0;
> + UINT32 Res3;
> + UINT32 Col0;
> + UINT32 Res4;
> + UINT32 Row1;
> + UINT32 Res5;
> + UINT32 Col1;
> + UINT32 Res6;
> + UINT32 Row2;
> + UINT32 Res7;
> + UINT32 Col2;
> + UINT32 Res8;
> + UINT32 Row3;
> + UINT32 Res9;
> + UINT32 Col3;
> + UINT32 Res10[0x24];
> + UINT32 NandFbcr;
> + UINT32 Res11;
> + UINT32 NandFir0;
> + UINT32 NandFir1;
> + UINT32 nandFir2;
> + UINT32 Res12[0x10];
> + UINT32 NandCsel;
> + UINT32 Res13;
> + UINT32 NandSeqStrt;
> + UINT32 Res14;
> + UINT32 NandEvterStat;
> + UINT32 Res15;
> + UINT32 PgrdcmplEvtStat;
> + UINT32 Res16[0x2];
> + UINT32 NandEvterEn;
> + UINT32 Res17[0x2];
> + UINT32 NandEvterIntrEn;
> + UINT32 Res18[0x2];
> + UINT32 NandErattr0;
> + UINT32 NandErattr1;
> + UINT32 Res19[0x10];
> + UINT32 NandFsr;
> + UINT32 Res20;
> + UINT32 NandEccstat[4];
> + UINT32 Res21[0x20];
> + UINT32 NanNdcr;
> + UINT32 Res22[0x2];
> + UINT32 NandAutobootTrgr;
> + UINT32 Res23;
> + UINT32 NandMdr;
> + UINT32 Res24[0x5C];
> +} IFC_NAND;
> +
> +/*
> + * IFC controller NOR Machine registers
> + */
> +typedef struct {
> + UINT32 NorEvterStat;
> + UINT32 Res1[0x2];
> + UINT32 NorEvterEn;
> + UINT32 Res2[0x2];
> + UINT32 NorEvterIntrEn;
> + UINT32 Res3[0x2];
> + UINT32 NorErattr0;
> + UINT32 NorErattr1;
> + UINT32 NorErattr2;
> + UINT32 Res4[0x4];
> + UINT32 NorCr;
> + UINT32 Res5[0xEF];
> +} IFC_NOR;
> +
> +/*
> + * IFC controller GPCM Machine registers
> + */
> +typedef struct {
extra space
> + UINT32 GpcmEvterStat;
> + UINT32 Res1[0x2];
> + UINT32 GpcmEvterEn;
> + UINT32 Res2[0x2];
> + UINT32 gpcmEvterIntrEn;
> + UINT32 Res3[0x2];
> + UINT32 GpcmErattr0;
> + UINT32 GpcmErattr1;
> + UINT32 GcmErattr2;
> + UINT32 GpcmStat;
> +} IFC_GPCM;
> +
> +/*
> + * IFC Controller Registers
> + */
> +typedef struct {
> + UINT32 IfcRev;
> + UINT32 Res1[0x2];
> + IFC_CSPR CsprCs[IFC_BANK_COUNT];
> + UINT8 Res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
> + IFC_AMASK AmaskCs[IFC_BANK_COUNT];
> + UINT8 Res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
> + IFC_CSOR CsorCs[IFC_BANK_COUNT];
> + UINT8 Res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
> + IFC_FTIM FtimCs[IFC_BANK_COUNT];
> + UINT8 Res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
> + UINT32 RbStat;
> + UINT32 RbMap;
> + UINT32 WpMap;
> + UINT32 IfcGcr;
> + UINT32 Res7[0x2];
> + UINT32 CmEvter_stat;
> + UINT32 Res8[0x2];
> + UINT32 CmEvterEn;
> + UINT32 Res9[0x2];
> + UINT32 CmEvterIntrEn;
> + UINT32 Res10[0x2];
> + UINT32 CmErattr0;
> + UINT32 CmErattr1;
> + UINT32 Res11[0x2];
> + UINT32 IfcCcr;
> + UINT32 IfcCsr;
> + UINT32 DdrCcrLow;
> + UINT32 Res12[IFC_NAND_RESERVED_SIZE];
> + IFC_NAND IfcNand;
> + IFC_NOR IfcNor;
> + IFC_GPCM IfcGpcm;
> +} IFC_REGS;
> +
> +extern VOID GetIfcNorFlashTimings (IFC_TIMINGS * NorIfcTimings);
> +
> +extern VOID GetIfcFpgaTimings (IFC_TIMINGS *FpgaIfcTimings);
> +
> +extern VOID GetIfcNandFlashTimings (IFC_TIMINGS * NandIfcTimings);
Please move these function declarations to the (first) patch that adds
implementations of these functions.
> +
> +#endif //__IFC_LIB_H__
> diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.inf b/Silicon/NXP/Library/IfcLib/IfcLib.inf
> new file mode 100644
> index 0000000..989eb44
> --- /dev/null
> +++ b/Silicon/NXP/Library/IfcLib/IfcLib.inf
> @@ -0,0 +1,38 @@
> +# IfcLib.inf
> +#
> +# Component description file for IFC Library
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = IfcLib
Nxp
> + FILE_GUID = a465d76c-0785-4ee7-bd72-767983d575a2
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = IfcLib
Nxp
/
Leif
> +
> +[Sources.common]
> + IfcLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BoardLib
> + IoAccessLib
> +
> +[FixedPcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index df64ad6..bd89da4 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -77,6 +77,7 @@
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000128
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129
> gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0|UINT64|0x0000012B
>
> #
> # IFC PCDs
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 14/41] Silicon/NXP : Add support for FpgaLib.
2018-11-28 15:01 ` [PATCH edk2-platforms 14/41] Silicon/NXP : Add support for FpgaLib Meenakshi Aggarwal
@ 2018-12-19 17:37 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-19 17:37 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Wed, Nov 28, 2018 at 08:31:28PM +0530, Meenakshi Aggarwal wrote:
> FpgaLib export FPGA_READ and FPGA_WRITE function and
> provide a function to print Board personality.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/Library/FpgaLib.h | 97 +++++++++++++++++++++
> Silicon/NXP/Library/FpgaLib/FpgaLib.c | 145 ++++++++++++++++++++++++++++++++
> Silicon/NXP/Library/FpgaLib/FpgaLib.inf | 34 ++++++++
Moving this library up to a more "generic" level than in previous
submission (which is a good thing!), could you add Nxp/Qoriq in
file/directory/library names?
> 3 files changed, 276 insertions(+)
> create mode 100644 Silicon/NXP/Include/Library/FpgaLib.h
> create mode 100644 Silicon/NXP/Library/FpgaLib/FpgaLib.c
> create mode 100644 Silicon/NXP/Library/FpgaLib/FpgaLib.inf
>
> diff --git a/Silicon/NXP/Include/Library/FpgaLib.h b/Silicon/NXP/Include/Library/FpgaLib.h
> new file mode 100644
> index 0000000..847689c
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/FpgaLib.h
> @@ -0,0 +1,97 @@
> +/** FpgaLib.h
> +* Header defining the Fpga specific constants (Base addresses, sizes, flags)
> +*
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __LS1_FPGA_H__
> +#define __LS1_FPGA_H__
NXP/QORIQ in include guard?
> +
> +/*
> + * FPGA register set of board.
> + */
> +typedef struct {
> + UINT8 FpgaVersionMajor; /* 0x0 - FPGA Major Revision Register */
> + UINT8 FpgaVersionMinor; /* 0x1 - FPGA Minor Revision Register */
> + UINT8 PcbaVersion; /* 0x2 - PCBA Revision Register */
> + UINT8 SystemReset; /* 0x3 - system reset register */
> + UINT8 SoftMuxOn; /* 0x4 - Switch Control Enable Register */
> + UINT8 RcwSource1; /* 0x5 - Reset config word 1 */
> + UINT8 RcwSource2; /* 0x6 - Reset config word 2 */
> + UINT8 Vbank; /* 0x7 - Flash bank selection Control */
> + UINT8 SysclkSelect; /* 0x8 - System clock selection Control */
> + UINT8 UartSel; /* 0x9 - Uart selection Control */
> + UINT8 Sd1RefClkSel; /* 0xA - Serdes1 reference clock selection Control */
> + UINT8 TdmClkMuxSel; /* 0xB - TDM Clock Mux selection Control */
> + UINT8 SdhcSpiCsSel; /* 0xC - SDHC/SPI Chip select selection Control */
> + UINT8 StatusLed; /* 0xD - Status Led */
> + UINT8 GlobalReset; /* 0xE - Global reset */
> + UINT8 SdEmmc; /* 0xF - SD or EMMC Interface Control Regsiter */
> + UINT8 VddEn; /* 0x10 - VDD Voltage Control Enable Register */
> + UINT8 VddSel; /* 0x11 - VDD Voltage Control Register */
> +} FPGA_REG_SET;
> +
> +/**
> + Function to read FPGA register.
> +**/
> +UINT8
> +FpgaRead (
Nxp/Qoriq in function names?
> + UINTN Reg
> + );
> +
> +/**
> + Function to write FPGA register.
> +**/
> +VOID
> +FpgaWrite (
> + UINTN Reg,
> + UINT8 Value
> + );
> +
> +/**
> + Function to read FPGA revision.
> +**/
> +VOID
> +FpgaRevBit (
> + UINT8 *Value
> + );
> +
> +/**
> + Function to initialize FPGA timings.
> +**/
> +VOID
> +FpgaInit (
> + VOID
> + );
> +
> +/**
> + Function to print board personality.
> +**/
> +VOID
> +PrintBoardPersonality (
> + VOID
> + );
> +
> +#define FPGA_BASE_PHYS 0x7fb00000
> +
> +#define SRC_VBANK 0x25
> +#define SRC_NAND 0x106
> +#define SRC_QSPI 0x44
> +#define SRC_SD 0x40
> +
> +#define SERDES_FREQ1 "100.00 MHz"
> +#define SERDES_FREQ2 "156.25 MHz"
> +
> +#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg))
> +#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), Value)
NXP/QORIQ and Nxp/Qoriq on the above too.
> +
> +#endif
Include guard comment, please.
> diff --git a/Silicon/NXP/Library/FpgaLib/FpgaLib.c b/Silicon/NXP/Library/FpgaLib/FpgaLib.c
> new file mode 100644
> index 0000000..93e9a90
> --- /dev/null
> +++ b/Silicon/NXP/Library/FpgaLib/FpgaLib.c
> @@ -0,0 +1,145 @@
> +/** @FpgaLib.c
> + Fpga Library containing functions to program and read the Fpga registers.
> +
> + FPGA is connected to IFC Controller and so MMIO APIs are used
> + to read/write FPGA registers
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/FpgaLib.h>
> +#include <Library/IoLib.h>
> +
> +/**
> + Function to read FPGA register.
> +
> + @param Reg Register offset of FPGA to read.
> +
> +**/
> +UINT8
> +FpgaRead (
> + IN UINTN Reg
> + )
> +{
> + VOID *Base;
> +
> + Base = (VOID *)FPGA_BASE_PHYS;
> +
> + return MmioRead8 ((UINTN)(Base + Reg));
> +}
> +
> +/**
> + Function to write FPGA register.
> +
> + @param Reg Register offset of FPGA to write.
> + @param Value Value to be written.
> +
> +**/
> +VOID
> +FpgaWrite (
> + IN UINTN Reg,
> + IN UINT8 Value
> + )
> +{
> + VOID *Base;
> +
> + Base = (VOID *)FPGA_BASE_PHYS;
> +
> + MmioWrite8 ((UINTN)(Base + Reg), Value);
> +}
> +
> +/**
> + Function to reverse the number.
> +
> + @param *Value pointer to number to reverse.
> +
> + @retval *Value reversed value.
> +
> +**/
> +VOID
> +FpgaRevBit (
> + OUT UINT8 *Value
> + )
> +{
> + UINT8 Rev;
> + UINT8 Val;
> + UINTN Index;
> +
> + Val = *Value;
> + Rev = Val & 1;
> + for (Index = 1; Index <= 7; Index++) {
> + Val >>= 1;
> + Rev <<= 1;
> + Rev |= Val & 1;
> + }
> +
> + *Value = Rev;
> +}
> +
> +/**
> + Function to print board personality.
> +
> +**/
> +VOID
> +PrintBoardPersonality (
> + VOID
> + )
> +{
> + UINT8 RcwSrc1;
> + UINT8 RcwSrc2;
> + UINT32 RcwSrc;
> + UINT32 Sd1RefClkSel;
> +
> + RcwSrc1 = FPGA_READ(RcwSource1);
> + RcwSrc2 = FPGA_READ(RcwSource2);
> + FpgaRevBit (&RcwSrc1);
> + RcwSrc = RcwSrc1;
> + RcwSrc = (RcwSrc << 1) | RcwSrc2;
> +
> + switch (RcwSrc) {
> + case SRC_VBANK:
> + DEBUG ((DEBUG_INFO, "vBank: %d\n", FPGA_READ(Vbank)));
> + break;
> + case SRC_NAND:
> + DEBUG ((DEBUG_INFO, "NAND\n"));
> + break;
> + case SRC_QSPI:
> + DEBUG ((DEBUG_INFO, "QSPI vBank %d\n", FPGA_READ(Vbank)));
> + break;
> + case SRC_SD:
> + DEBUG ((DEBUG_INFO, "SD\n"));
> + break;
> + default:
> + DEBUG ((DEBUG_INFO, "Invalid setting of SW5\n"));
> + break;
> + }
> +
> + DEBUG ((DEBUG_INFO, "FPGA: V%x.%x\nPCBA: V%x.0\n",
> + FPGA_READ(FpgaVersionMajor),
> + FPGA_READ(FpgaVersionMinor),
> + FPGA_READ(PcbaVersion)));
> +
> + DEBUG ((DEBUG_INFO, "SERDES Reference Clocks:\n"));
> +
> + Sd1RefClkSel = FPGA_READ(Sd1RefClkSel);
> + DEBUG ((DEBUG_INFO, "SD1_CLK1 = %a, SD1_CLK2 = %a\n",
> + Sd1RefClkSel ? SERDES_FREQ2 : SERDES_FREQ1, SERDES_FREQ1));
> + if (PcdGetBool (PcdSerdes2Enabled)) {
> + DEBUG ((DEBUG_INFO, "SD2_CLK1 = %a, SD2_CLK2 = %a\n",
> + SERDES_FREQ1, SERDES_FREQ1));
> + }
> +
> + return;
> +}
> diff --git a/Silicon/NXP/Library/FpgaLib/FpgaLib.inf b/Silicon/NXP/Library/FpgaLib/FpgaLib.inf
> new file mode 100644
> index 0000000..c6c23ad
> --- /dev/null
> +++ b/Silicon/NXP/Library/FpgaLib/FpgaLib.inf
> @@ -0,0 +1,34 @@
> +# @FpgaLib.inf
> +#
> +# Copyright 2017 NXP
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001000A
1A
/
Leif
> + BASE_NAME = FpgaLib
> + FILE_GUID = 5962d040-8b8a-11df-9a71-0002a5d5c51b
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = FpgaLib
> +
> +[Sources.common]
> + FpgaLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + IoLib
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 16/41] Silicon/NXP : Add support of NorFlashLib
2018-11-28 15:01 ` [PATCH edk2-platforms 16/41] Silicon/NXP : Add support of NorFlashLib Meenakshi Aggarwal
@ 2018-12-19 18:13 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-19 18:13 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Wed, Nov 28, 2018 at 08:31:30PM +0530, Meenakshi Aggarwal wrote:
> NorFlashLib interacts with the underlying IFC NOR controller.
Expand IFC in commit message.
> This will be used by NOR driver for any information
> exchange with NOR controller.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
On the whole, a big improvement.
A few minor style comments and one polite request below.
> ---
> Silicon/NXP/Include/Library/NorFlashLib.h | 77 +++
> Silicon/NXP/Include/NorFlash.h | 44 ++
> Silicon/NXP/Library/NorFlashLib/CfiCommand.h | 99 ++++
> Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c | 210 +++++++
> Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h | 53 ++
> Silicon/NXP/Library/NorFlashLib/NorFlashLib.c | 696 +++++++++++++++++++++++
> Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf | 43 ++
> 7 files changed, 1222 insertions(+)
> create mode 100644 Silicon/NXP/Include/Library/NorFlashLib.h
> create mode 100644 Silicon/NXP/Include/NorFlash.h
> create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiCommand.h
> create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
> create mode 100644 Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
> create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
> create mode 100644 Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
>
> diff --git a/Silicon/NXP/Include/Library/NorFlashLib.h b/Silicon/NXP/Include/Library/NorFlashLib.h
> new file mode 100644
> index 0000000..defdc61
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/NorFlashLib.h
> @@ -0,0 +1,77 @@
> +/** @file
> +
> + Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
> + Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
> + Copyright 2017 NXP
> +
> +This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> + **/
> +
> +#ifndef _NOR_FLASH_LIB_H_
> +#define _NOR_FLASH_LIB_H_
> +
> +#include <NorFlash.h>
> +
> +#define NOR_FLASH_DEVICE_COUNT 1
> +
> +typedef struct {
> + UINTN DeviceBaseAddress; // Start address of the Device Base Address (DBA)
> + UINTN RegionBaseAddress; // Start address of one single region
> + UINTN Size;
> + UINTN BlockSize;
> + UINTN MultiByteWordCount; // Maximum Word count that can be written to Nor Flash in multi byte write
> + UINTN WordWriteTimeOut; // single byte/word timeout usec
> + UINTN BufferWriteTimeOut; // buffer write timeout usec
> + UINTN BlockEraseTimeOut; // block erase timeout usec
> + UINTN ChipEraseTimeOut; // chip erase timeout usec
> +} NorFlashDescription;
> +
> +EFI_STATUS
> +NorFlashPlatformGetDevices (
> + OUT NorFlashDescription **NorFlashDevices,
> + OUT UINT32 *Count
> + );
> +
> +EFI_STATUS
> +NorFlashPlatformFlashGetAttributes (
> + OUT NorFlashDescription *NorFlashDevices,
> + IN UINT32 Count
> + );
> +
> +EFI_STATUS
> +NorFlashPlatformWriteBuffer (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + );
> +
> +EFI_STATUS
> +NorFlashPlatformEraseSector (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN SectorAddress
> + );
> +
> +EFI_STATUS
> +NorFlashPlatformRead (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN UINTN BufferSizeInBytes,
> + OUT UINT8 *Buffer
> + );
> +
> +EFI_STATUS
> +NorFlashPlatformReset (
> + IN UINTN Instance
> + );
> +
> +#endif /* _NOR_FLASH_LIB_H_ */
> diff --git a/Silicon/NXP/Include/NorFlash.h b/Silicon/NXP/Include/NorFlash.h
> new file mode 100644
> index 0000000..8fa41d8
> --- /dev/null
> +++ b/Silicon/NXP/Include/NorFlash.h
> @@ -0,0 +1,44 @@
> +/** @NorFlash.h
> +
> + Contains data structure shared by both NOR Library and Driver.
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __NOR_FLASH_H__
> +#define __NOR_FLASH_H__
> +
> +#include <Protocol/BlockIo.h>
> +#include <Protocol/FirmwareVolumeBlock.h>
> +
> +typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
> +
> +typedef struct {
> + VENDOR_DEVICE_PATH Vendor;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} NOR_FLASH_DEVICE_PATH;
> +
> +struct _NOR_FLASH_INSTANCE {
> + UINT32 Signature;
> + EFI_HANDLE Handle;
> + UINTN DeviceBaseAddress;
> + UINTN RegionBaseAddress;
> + UINTN Size;
> + EFI_LBA StartLba;
> + EFI_BLOCK_IO_PROTOCOL BlockIoProtocol;
> + EFI_BLOCK_IO_MEDIA Media;
> + EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
> + VOID* ShadowBuffer;
> + NOR_FLASH_DEVICE_PATH DevicePath;
> +};
> +
> +
> +#endif /* __NOR_FLASH_H__ */
> diff --git a/Silicon/NXP/Library/NorFlashLib/CfiCommand.h b/Silicon/NXP/Library/NorFlashLib/CfiCommand.h
> new file mode 100644
> index 0000000..8543227
> --- /dev/null
> +++ b/Silicon/NXP/Library/NorFlashLib/CfiCommand.h
I did say last time that we didn't need to worry about turning this
library common yet.
I want to go back on that slightly:
I do want everything in this file that relates to the CFI
specification to be submitted as a new
edk2/MdePkg/Include/IndustryStandard/Cfi.h
> @@ -0,0 +1,99 @@
> +/** @CfiCommand.h
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __CFI_COMMAND_H__
> +#define __CFI_COMMAND_H__
This would then only need to be
#ifndef CFI_H_
> +
> +// CFI Data "QRY"
> +#define CFI_QRY_Q 0x51
> +#define CFI_QRY_R 0x52
> +#define CFI_QRY_Y 0x59
> +#define CFI_QRY 0x515259
> +
> +#define ENTER_CFI_QUERY_MODE_ADDR 0x0055
> +#define ENTER_CFI_QUERY_MODE_CMD 0x0098
And I think these would need to be changed to CFI_ENTER_
> +
> +#define CFI_QUERY_UNIQUE_QRY_STRING 0x10
> +
> +// Offsets for CFI queries
> +#define CFI_QUERY_TYP_TIMEOUT_WORD_WRITE 0x1F
> +#define CFI_QUERY_TYP_TIMEOUT_MAX_BUFFER_WRITE 0x20
> +#define CFI_QUERY_TYP_TIMEOUT_BLOCK_ERASE 0x21
> +#define CFI_QUERY_TYP_TIMEOUT_CHIP_ERASE 0x22
> +#define CFI_QUERY_MAX_TIMEOUT_WORD_WRITE 0x23
> +#define CFI_QUERY_MAX_TIMEOUT_MAX_BUFFER_WRITE 0x24
> +#define CFI_QUERY_MAX_TIMEOUT_BLOCK_ERASE 0x25
> +#define CFI_QUERY_MAX_TIMEOUT_CHIP_ERASE 0x26
> +#define CFI_QUERY_DEVICE_SIZE 0x27
> +#define CFI_QUERY_MAX_NUM_BYTES_WRITE 0x2A
> +#define CFI_QUERY_BLOCK_SIZE 0x2F
> +
> +// Unlock Address
> +#define CMD_UNLOCK_1_ADDR 0x555
> +#define CMD_UNLOCK_2_ADDR 0x2AA
And all of these would need to be CFI_CMD_
> +
> +// RESET Command
> +#define CMD_RESET_FIRST 0xAA
> +#define CMD_RESET_SECOND 0x55
> +#define CMD_RESET 0xF0
> +
> +// READ Command
> +
> +// Manufacturer ID
> +#define CMD_READ_M_ID_FIRST 0xAA
> +#define CMD_READ_M_ID_SECOND 0x55
> +#define CMD_READ_M_ID_THIRD 0x90
> +#define CMD_READ_M_ID_FOURTH 0x01
> +
> +// Device ID
> +#define CMD_READ_D_ID_FIRST 0xAA
> +#define CMD_READ_D_ID_SECOND 0x55
> +#define CMD_READ_D_ID_THIRD 0x90
> +#define CMD_READ_D_ID_FOURTH 0x7E
> +#define CMD_READ_D_ID_FIFTH 0x13
> +#define CMD_READ_D_ID_SIXTH 0x00
> +
> +// WRITE Command
> +
> +// PROGRAM Command
> +#define CMD_PROGRAM_FIRST 0xAA
> +#define CMD_PROGRAM_SECOND 0x55
> +#define CMD_PROGRAM_THIRD 0xA0
> +
> +// Write Buffer Command
> +#define CMD_WRITE_TO_BUFFER_FIRST 0xAA
> +#define CMD_WRITE_TO_BUFFER_SECOND 0x55
> +#define CMD_WRITE_TO_BUFFER_THIRD 0x25
> +#define CMD_WRITE_TO_BUFFER_CONFIRM 0x29
> +
> +// ERASE Command
> +
> +// UNLOCK COMMANDS FOR ERASE
> +#define CMD_ERASE_FIRST 0xAA
> +#define CMD_ERASE_SECOND 0x55
> +#define CMD_ERASE_THIRD 0x80
> +#define CMD_ERASE_FOURTH 0xAA
> +#define CMD_ERASE_FIFTH 0x55
> +
> +// Chip Erase Command
> +#define CMD_CHIP_ERASE_SIXTH 0x10
> +
> +// Sector Erase Command
> +#define CMD_SECTOR_ERASE_SIXTH 0x30
> +
> +// SUSPEND Command
> +#define CMD_PROGRAM_OR_ERASE_SUSPEND 0xB0
> +#define CMD_PROGRAM_OR_ERASE_RESUME 0x30
> +
> +#endif // __CFI_COMMAND_H__
(If ther is) Anything in this file which is not covered by the CFI
specification, keep it here, under this name.
> diff --git a/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
> new file mode 100644
> index 0000000..941d5d4
> --- /dev/null
> +++ b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.c
> @@ -0,0 +1,210 @@
> +/** @CfiNorFlashLib.c
> +
> + Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> + **/
> +
> +#include <PiDxe.h>
> +#include <Library/ArmLib.h>
> +#include <Library/BaseLib.h>
> +
> +#include "CfiCommand.h"
> +#include "CfiNorFlashLib.h"
> +
> +STATIC
> +VOID
> +NorFlashReadCfiData (
> + IN UINTN DeviceBaseAddress,
> + IN UINTN CfiOffset,
> + IN UINT32 Count,
> + OUT VOID *Data
> + )
> +{
> + UINT32 Loop;
> + FLASH_DATA *TmpData = (FLASH_DATA *)Data;
> +
> + for (Loop = 0; Loop < Count; Loop++, TmpData++) {
> + *TmpData = mMmioOps->Read ((UINTN)((FLASH_DATA*)DeviceBaseAddress + CfiOffset));
> + CfiOffset++;
> + }
> +}
> +
> +/*
> + Currently we support only CFI flash devices; Bail-out otherwise
> +*/
> +EFI_STATUS
> +CfiNorFlashFlashGetAttributes (
> + OUT NorFlashDescription *NorFlashDevices,
> + IN UINT32 Index
> + )
> +{
> + UINT32 Count;
> + FLASH_DATA QryData[QRY_STRING_COUNT];
> + FLASH_DATA BlockSize[BLOCK_SIZE_COUNT];
> + UINTN DeviceBaseAddress;
> + FLASH_DATA MaxNumBytes[BLOCK_SIZE_COUNT];
> + FLASH_DATA Size;
> + FLASH_DATA HighByteMask; // Masks High byte in a UIN16 word
> + FLASH_DATA HighByteShift; // Bitshifts needed to make a byte High Byte in a UIN16 word
> + FLASH_DATA Temp1;
> + FLASH_DATA Temp2;
> + FLASH_DATA Z;
> +
> + HighByteMask = 0xFF;
> + HighByteShift = 8;
> +
> + for (Count = 0; Count < Index; Count++) {
> +
> + NorFlashDevices[Count].DeviceBaseAddress = DeviceBaseAddress = PcdGet64 (PcdFlashDeviceBase64);
> +
> + // Reset flash first
> + NorFlashPlatformReset (DeviceBaseAddress);
> +
> + // Enter the CFI Query Mode
> + SEND_NOR_COMMAND (
> + DeviceBaseAddress,
> + ENTER_CFI_QUERY_MODE_ADDR,
> + ENTER_CFI_QUERY_MODE_CMD
> + );
> +
> + MemoryFence();
> +
> + // Query the unique QRY
> + NorFlashReadCfiData (
> + DeviceBaseAddress,
> + CFI_QUERY_UNIQUE_QRY_STRING,
> + QRY_STRING_COUNT,
> + &QryData
> + );
> +
> + if ((QryData[0] != (FLASH_DATA)CFI_QRY_Q) ||
> + (QryData[1] != (FLASH_DATA)CFI_QRY_R) ||
> + (QryData[2] != (FLASH_DATA)CFI_QRY_Y)) {
> + DEBUG ((DEBUG_ERROR, "Not a CFI flash (QRY not recvd): "
> + "Got = 0x%04x, 0x%04x, 0x%04x\n",
> + QryData[0], QryData[1], QryData[2]));
> + return EFI_DEVICE_ERROR;
> + }
> +
> + NorFlashReadCfiData (
> + DeviceBaseAddress,
> + CFI_QUERY_DEVICE_SIZE,
> + DEVICE_SIZE_COUNT,
> + &Size
> + );
> +
> + // Refer CFI Specification [2^n in number of bytes.]
> + NorFlashDevices[Count].Size = 1 << Size;
> +
> + NorFlashReadCfiData (
> + DeviceBaseAddress,
> + CFI_QUERY_BLOCK_SIZE,
> + BLOCK_SIZE_COUNT,
> + &BlockSize
> + );
> +
> + // Refer CFI Specification [Erase block(s) within this region are (z) times 256 bytes in size.
> + // The value z = 0 is used for 128-byte block size.
> + Z = (FLASH_DATA)((BlockSize[1] << HighByteShift) | (BlockSize[0] & HighByteMask));
> + if (Z == 0) {
> + NorFlashDevices[Count].BlockSize = 128;
> + } else {
> + NorFlashDevices[Count].BlockSize = 256 * Z;
> + }
> +
> + NorFlashReadCfiData (
> + DeviceBaseAddress,
> + CFI_QUERY_MAX_NUM_BYTES_WRITE,
> + BLOCK_SIZE_COUNT,
> + &MaxNumBytes
> + );
> +
> + // Refer CFI Specification
> + /* from CFI query we get the Max. number of BYTE in multi-byte write = 2^N.
> + But our Flash Library is able to read/write in WORD size (2 bytes) which
> + is why we need to CONVERT MAX BYTES TO MAX WORDS by diving it by
> + width of word size */
> + NorFlashDevices[Count].MultiByteWordCount =\
> + (1 << ((FLASH_DATA)((MaxNumBytes[1] << HighByteShift) |
> + (MaxNumBytes[0] & HighByteMask))))/sizeof(FLASH_DATA);
> +
> + NorFlashReadCfiData (
> + DeviceBaseAddress,
> + CFI_QUERY_TYP_TIMEOUT_WORD_WRITE,
> + WORD_WRITE_COUNT,
> + &Temp1
> + );
> +
> + NorFlashReadCfiData (
> + DeviceBaseAddress,
> + CFI_QUERY_MAX_TIMEOUT_WORD_WRITE,
> + WORD_WRITE_COUNT,
> + &Temp2
> + );
> +
> + NorFlashDevices[Count].WordWriteTimeOut = (1U << Temp1) * (1U << Temp2);
> +
> + NorFlashReadCfiData (
> + DeviceBaseAddress,
> + CFI_QUERY_TYP_TIMEOUT_MAX_BUFFER_WRITE,
> + BUFFER_WRITE_COUNT,
> + &Temp1
> + );
> +
> + NorFlashReadCfiData (
> + DeviceBaseAddress,
> + CFI_QUERY_MAX_TIMEOUT_MAX_BUFFER_WRITE,
> + BUFFER_WRITE_COUNT,
> + &Temp2
> + );
> +
> + NorFlashDevices[Count].BufferWriteTimeOut = (1U << Temp1) * (1U << Temp2);
> +
> + NorFlashReadCfiData (
> + DeviceBaseAddress,
> + CFI_QUERY_TYP_TIMEOUT_BLOCK_ERASE,
> + BLOCK_ERASE_COUNT,
> + &Temp1
> + );
> +
> + NorFlashReadCfiData (
> + DeviceBaseAddress,
> + CFI_QUERY_MAX_TIMEOUT_BLOCK_ERASE,
> + BLOCK_ERASE_COUNT,
> + &Temp2
> + );
> +
> + // Converting from millisecond to microseconds
> + NorFlashDevices[Count].BlockEraseTimeOut = (1U << Temp1) * (1U << Temp2) * 1000;
> +
> + NorFlashReadCfiData (
> + DeviceBaseAddress,
> + CFI_QUERY_TYP_TIMEOUT_CHIP_ERASE,
> + CHIP_ERASE_COUNT,
> + &Temp1
> + );
> +
> + NorFlashReadCfiData (
> + DeviceBaseAddress,
> + CFI_QUERY_MAX_TIMEOUT_CHIP_ERASE,
> + CHIP_ERASE_COUNT,
> + &Temp2
> + );
> +
> + NorFlashDevices[Count].ChipEraseTimeOut = (1U << Temp1) * (1U << Temp2) * 1000;
> +
> + // Put device back into Read Array mode (via Reset)
> + NorFlashPlatformReset (DeviceBaseAddress);
> + }
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
> new file mode 100644
> index 0000000..710f706
> --- /dev/null
> +++ b/Silicon/NXP/Library/NorFlashLib/CfiNorFlashLib.h
> @@ -0,0 +1,53 @@
> +/** @CfiNorFlashLib.h
> +
> + Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __CFI_NOR_FLASH_LIB_H__
> +#define __CFI_NOR_FLASH_LIB_H__
> +
> +#include <Library/DebugLib.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/NorFlashLib.h>
> +
> +extern MMIO_OPERATIONS_16 *mMmioOps;
> +
> +/*
> + * Values for the width of the port
> + */
> +#define FLASH_CFI_8BIT 0x01
> +#define FLASH_CFI_16BIT 0x02
> +#define FLASH_CFI_32BIT 0x04
> +#define FLASH_CFI_64BIT 0x08
> +
> +#define QRY_STRING_COUNT 3
> +#define DEVICE_SIZE_COUNT 1
> +#define BLOCK_SIZE_COUNT 2
> +#define WORD_WRITE_COUNT 1
> +#define BUFFER_WRITE_COUNT 1
> +#define BLOCK_ERASE_COUNT 1
> +#define CHIP_ERASE_COUNT 1
Are any of these part of the CFI specification? If so move them to the
new header proposed above, and ensure CFI_ prefix.
> +
> +#define CREATE_BYTE_OFFSET(OffsetAddr) ((sizeof (FLASH_DATA)) * (OffsetAddr))
> +#define CREATE_NOR_ADDRESS(BaseAddr, OffsetAddr) ((BaseAddr) + (OffsetAddr))
> +#define SEND_NOR_COMMAND(BaseAddr, Offset, Cmd) mMmioOps->Write (CREATE_NOR_ADDRESS (BaseAddr, CREATE_BYTE_OFFSET (Offset)), (Cmd))
> +
> +typedef UINT16 FLASH_DATA;
> +
> +EFI_STATUS
> +CfiNorFlashFlashGetAttributes (
> + OUT NorFlashDescription *NorFlashDevices,
> + IN UINT32 Index
> + );
> +
> +#endif //__CFI_NOR_FLASH_LIB_H__
> diff --git a/Silicon/NXP/Library/NorFlashLib/NorFlashLib.c b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
> new file mode 100644
> index 0000000..c89ddc3
> --- /dev/null
> +++ b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.c
> @@ -0,0 +1,696 @@
> +/** @NorFlashLib.c
> +
> + Based on NorFlash implementation available in NorFlashDxe.c
> +
> + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
> + Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <Library/BaseMemoryLib/MemLibInternals.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/TimerLib.h>
> +
> +#include "CfiCommand.h"
> +#include "CfiNorFlashLib.h"
> +
> +#define GET_BLOCK_OFFSET(Lba) ((Instance->RegionBaseAddress) -\
> + (Instance->DeviceBaseAddress) + ((UINTN)((Lba) * Instance->Media.BlockSize)))
> +
> +MMIO_OPERATIONS_16 *mMmioOps;
> +
> +NorFlashDescription mNorFlashDevices[NOR_FLASH_DEVICE_COUNT];
> +
> +STATIC VOID
> +UnlockEraseAddress (
> + IN UINTN DeviceBaseAddress
> + )
> +{ // Issue the Unlock cmds
> + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, CMD_ERASE_FIRST);
> +
> + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR, CMD_ERASE_SECOND);
> +
> + // Issue a setup command
> + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, CMD_ERASE_THIRD);
> +
> + // Issue the Unlock cmds
> + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, CMD_ERASE_FOURTH);
> +
> + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR, CMD_ERASE_FIFTH);
> +
> + return;
> +}
> +
> +STATIC
> +UINT64
> +ConvertMicroSecondsToTicks (
> + IN UINTN MicroSeconds
> + )
> +{
> + UINT64 TimerTicks64;
> +
> + TimerTicks64 = 0;
> +
> + // Calculate counter ticks that represent requested delay:
> + // = MicroSeconds x TICKS_PER_MICRO_SEC
> + // = MicroSeconds x Timer Frequency(in Hz) x 10^-6
> + // GetPerformanceCounterProperties = Get Arm Timer Frequency in Hz
> + TimerTicks64 = DivU64x32 (
> + MultU64x64 (
> + MicroSeconds,
> + GetPerformanceCounterProperties (NULL, NULL)
> + ),
> + 1000000U
> + );
> + return TimerTicks64;
> +}
> +
> +/**
> + * The following function erases a NOR flash sector.
> + **/
> +EFI_STATUS
> +NorFlashPlatformEraseSector (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN SectorAddress
> + )
> +{
> + FLASH_DATA EraseStatus1;
> + FLASH_DATA EraseStatus2;
> + UINT64 Timeout;
> + UINT64 SystemCounterVal;
> +
> + EraseStatus1 = 0;
> + EraseStatus2 = 0;
> + Timeout = 0;
> +
> + Timeout = ConvertMicroSecondsToTicks (mNorFlashDevices[Instance->Media.MediaId].BlockEraseTimeOut);
> +
> + // Request a sector erase by writing two unlock cycles, followed by a
> + // setup command and two additional unlock cycles
> +
> + UnlockEraseAddress (Instance->DeviceBaseAddress);
> +
> + // Now send the address of the sector to be erased
> + SEND_NOR_COMMAND (SectorAddress, 0, CMD_SECTOR_ERASE_SIXTH);
> +
> + // Wait for erase to complete
> + // Read Sector start address twice to detect bit toggle and to
> + // determine ERASE DONE (all bits are 1)
> + // Get the maximum timer ticks needed to complete the operation
> + // Check if operation is complete or not in continous loop?
> + // if complete, exit from loop
> + // if not check the ticks that have been passed from the begining of loop
> + // if Maximum Ticks allocated for operation has passed exit from loop
> +
> + SystemCounterVal = GetPerformanceCounter ();
> + Timeout += SystemCounterVal;
> + while (SystemCounterVal < Timeout) {
> + if ((EraseStatus1 = mMmioOps->Read (SectorAddress))
> + == (EraseStatus2 = mMmioOps->Read (SectorAddress)))
> + {
> + if (mMmioOps->Read (SectorAddress) == 0xFFFF) {
> + break;
> + }
> + }
> + SystemCounterVal = GetPerformanceCounter ();
> + }
> +
> + if (SystemCounterVal >= Timeout) {
> + DEBUG ((DEBUG_ERROR, "%a :Failed to Erase @ SectorAddress 0x%p, Timeout\n",
> + __FUNCTION__, SectorAddress));
> + return EFI_DEVICE_ERROR;
> + } else {
> + return EFI_SUCCESS;
> + }
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformWriteWord (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN WordOffset,
> + IN FLASH_DATA Word
> + )
> +{
> + UINT64 Timeout;
> + UINTN TargetAddress;
> + UINT64 SystemCounterVal;
> + FLASH_DATA Read1;
> + FLASH_DATA Read2;
> +
> + Timeout = 0;
> +
> + Timeout = ConvertMicroSecondsToTicks (mNorFlashDevices[Instance->Media.MediaId].WordWriteTimeOut);
> +
> + TargetAddress = CREATE_NOR_ADDRESS (
> + Instance->DeviceBaseAddress,
> + CREATE_BYTE_OFFSET (WordOffset)
> + );
> +
> + // Issue the Unlock cmds
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR, CMD_PROGRAM_FIRST);
> +
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_2_ADDR, CMD_PROGRAM_SECOND);
> +
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR, CMD_PROGRAM_THIRD);
> +
> + MmioWrite16 (TargetAddress, Word);
> +
> + // Wait for Write to Complete
> + // Read the last written address twice to detect bit toggle and
> + // to determine if date is wriiten successfully or not ?
> + // Get the maximum timer ticks needed to complete the operation
> + // Check if operation is complete or not in continous loop?
> + // if complete, exit from loop
> + // if not check the ticks that have been passed from the begining of loop
> + // if Maximum Ticks allocated for operation has passed, then exit from loop
> +
> + SystemCounterVal = GetPerformanceCounter ();
> + Timeout += SystemCounterVal;
> + while (SystemCounterVal < Timeout) {
> + if ((Read1 = MmioRead16 (TargetAddress))
> + == (Read2 = MmioRead16 (TargetAddress)))
"if" is not a function - when line wrapping, align to preceding test.
My preference here would be
if ((Read1 = MmioRead16 (TargetAddress)) ==
(Read2 = MmioRead16 (TargetAddress)))
(Please follow this pattern throughout.)
> + {
And that { at the end of the preceding line.
> + if (Word == MmioRead16 (TargetAddress)) {
> + break;
> + }
> + }
> + SystemCounterVal = GetPerformanceCounter ();
> + }
> +
> + if (SystemCounterVal >= Timeout) {
> + DEBUG ((DEBUG_ERROR, "%a: Failed to Write @ TargetAddress 0x%p, Timeout\n",
> + __FUNCTION__, TargetAddress));
> + return EFI_DEVICE_ERROR;
> + } else {
> + return EFI_SUCCESS;
> + }
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformWritePageBuffer (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN PageBufferOffset,
> + IN UINTN NumWords,
> + IN FLASH_DATA *Buffer
> + )
> +{
> + UINT64 Timeout;
> + UINTN LastWrittenAddress;
> + FLASH_DATA LastWritenData;
> + UINTN CurrentOffset;
> + UINTN EndOffset;
> + UINTN TargetAddress;
> + UINT64 SystemCounterVal;
> + FLASH_DATA Read1;
> + FLASH_DATA Read2;
> +
> + // Initialize variables
> + Timeout = 0;
> + LastWrittenAddress = 0;
> + LastWritenData = 0;
> + CurrentOffset = PageBufferOffset;
> + EndOffset = PageBufferOffset + NumWords - 1;
> + Timeout = ConvertMicroSecondsToTicks (mNorFlashDevices[Instance->Media.MediaId].BufferWriteTimeOut);
> + TargetAddress = CREATE_NOR_ADDRESS (
> + Instance->DeviceBaseAddress,
> + CREATE_BYTE_OFFSET (CurrentOffset)
> + );
> +
> + // don't try with a count of zero
> + if (!NumWords) {
> + return EFI_SUCCESS;
> + } else if (NumWords == 1) {
> + return NorFlashPlatformWriteWord (Instance, PageBufferOffset, *Buffer);
> + }
> +
> + // Issue the Unlock cmds
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR, CMD_WRITE_TO_BUFFER_FIRST);
> +
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_2_ADDR, CMD_WRITE_TO_BUFFER_SECOND);
> +
> + // Write the buffer load
> + SEND_NOR_COMMAND (TargetAddress, 0, CMD_WRITE_TO_BUFFER_THIRD);
> +
> + // Write # of locations to program
> + SEND_NOR_COMMAND (TargetAddress, 0, (NumWords - 1));
> +
> + // Load Data into Buffer
> + while (CurrentOffset <= EndOffset) {
> + LastWrittenAddress = CREATE_NOR_ADDRESS (
> + Instance->DeviceBaseAddress,
> + CREATE_BYTE_OFFSET (CurrentOffset++)
> + );
> + LastWritenData = *Buffer++;
> +
> + // Write Data
> + MmioWrite16 (LastWrittenAddress, LastWritenData);
> + }
> +
> + // Issue the Buffered Program Confirm command
> + SEND_NOR_COMMAND (TargetAddress, 0, CMD_WRITE_TO_BUFFER_CONFIRM);
> +
> + /* Wait for Write to Complete
> + Read the last written address twice to detect bit toggle and
> + to determine if date is wriiten successfully or not ?
> + Get the maximum timer ticks needed to complete the operation
> + Check if operation is complete or not in continous loop?
> + if complete, exit from loop
> + if not check the ticks that have been passed from the begining of loop
> + if Maximum Ticks allocated for operation has passed, then exit from loop **/
> + SystemCounterVal = GetPerformanceCounter();
> + Timeout += SystemCounterVal;
> + while (SystemCounterVal < Timeout) {
> + if ((Read1 = MmioRead16 (LastWrittenAddress))
> + == (Read2 = MmioRead16 (LastWrittenAddress)))
OK, it was only this location as well.
/
Leif
> + {
> + if (LastWritenData == MmioRead16 (LastWrittenAddress)) {
> + break;
> + }
> + }
> + SystemCounterVal = GetPerformanceCounter ();
> + }
> +
> + if (SystemCounterVal >= Timeout) {
> + DEBUG ((DEBUG_ERROR, "%a: Failed to Write @LastWrittenAddress 0x%p, Timeout\n",
> + __FUNCTION__, LastWrittenAddress));
> + return EFI_DEVICE_ERROR;
> + } else {
> + return EFI_SUCCESS;
> + }
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformWriteWordAlignedAddressBuffer (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN UINTN Offset,
> + IN UINTN NumWords,
> + IN FLASH_DATA *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINTN MultiByteWordCount;
> + UINTN Mask;
> + UINTN IntWords;
> +
> + MultiByteWordCount = mNorFlashDevices[Instance->Media.MediaId].MultiByteWordCount;
> + Mask = MultiByteWordCount - 1;
> + IntWords = NumWords;
> + Status = EFI_SUCCESS;
> +
> + if (Offset & Mask) {
> + // program only as much as necessary, so pick the lower of the two numbers
> + if (NumWords < (MultiByteWordCount - (Offset & Mask))) {
> + IntWords = NumWords;
> + } else {
> + IntWords = MultiByteWordCount - (Offset & Mask);
> + }
> +
> + // program the first few to get write buffer aligned
> + Status = NorFlashPlatformWritePageBuffer (Instance, Offset, IntWords, Buffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + Offset += IntWords; // adjust pointers and counter
> + NumWords -= IntWords;
> + Buffer += IntWords;
> +
> + if (NumWords == 0) {
> + return Status;
> + }
> + }
> +
> + while (NumWords >= MultiByteWordCount) {// while big chunks to do
> + Status = NorFlashPlatformWritePageBuffer (
> + Instance,
> + Offset,
> + MultiByteWordCount,
> + Buffer
> + );
> + if (EFI_ERROR (Status)) {
> + return (Status);
> + }
> +
> + Offset += MultiByteWordCount; // adjust pointers and counter
> + NumWords -= MultiByteWordCount;
> + Buffer += MultiByteWordCount;
> + }
> + if (NumWords == 0) {
> + return (Status);
> + }
> +
> + Status = NorFlashPlatformWritePageBuffer (
> + Instance,
> + Offset,
> + NumWords,
> + Buffer
> + );
> + return (Status);
> +}
> +
> +/**
> + Writes data to the NOR Flash using the Buffered Programming method.
> +
> + Write Buffer Programming allows the system to write a maximum of 32 bytes
> + in one programming operation. Therefore this function will only handle
> + buffers up to 32 bytes.
> + To deal with larger buffers, call this function again.
> +**/
> +EFI_STATUS
> +NorFlashPlatformWriteBuffer (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN OUT UINTN *NumBytes,
> + IN UINT8 *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + FLASH_DATA *SrcBuffer;
> + UINTN TargetOffsetinBytes;
> + UINTN WordsToWrite;
> + UINTN Mask;
> + UINTN BufferSizeInBytes;
> + UINTN IntBytes;
> + VOID *CopyFrom;
> + VOID *CopyTo;
> + FLASH_DATA TempWrite;
> +
> + SrcBuffer = (FLASH_DATA *)Buffer;
> + TargetOffsetinBytes = 0;
> + WordsToWrite = 0;
> + Mask = sizeof (FLASH_DATA) - 1;
> + BufferSizeInBytes = *NumBytes;
> + IntBytes = BufferSizeInBytes; // Intermediate Bytes needed to copy for alignment
> + TempWrite = 0;
> +
> + DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=%ld, Offset=0x%x, "
> + "*NumBytes=0x%x, Buffer @ 0x%08x)\n",
> + __FUNCTION__, Lba, Offset, *NumBytes, Buffer));
> +
> + TargetOffsetinBytes = GET_BLOCK_OFFSET (Lba) + (UINTN)(Offset);
> +
> + if (TargetOffsetinBytes & Mask) {
> + // Write only as much as necessary, so pick the lower of the two numbers
> + // and call it Intermediate bytes to write to make alignment proper
> + if (BufferSizeInBytes < (sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask))) {
> + IntBytes = BufferSizeInBytes;
> + } else {
> + IntBytes = sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask);
> + }
> +
> + // Read the first few to get Read buffer aligned
> + NorFlashPlatformRead (
> + Instance,
> + Lba,
> + (TargetOffsetinBytes & ~Mask) - GET_BLOCK_OFFSET (Lba),
> + sizeof (TempWrite),
> + (UINT8*)&TempWrite
> + );
> +
> + CopyTo = (UINT8*)&TempWrite;
> + CopyTo += (TargetOffsetinBytes & Mask);
> + CopyFrom = Buffer;
> +
> + CopyMem (CopyTo, CopyFrom, IntBytes);
> +
> + Status = NorFlashPlatformWriteWordAlignedAddressBuffer (
> + Instance,
> + (UINTN)((TargetOffsetinBytes & ~Mask) / sizeof (FLASH_DATA)),
> + 1,
> + &TempWrite);
> + if (EFI_ERROR (Status)) {
> + DEBUG((DEBUG_ERROR, "%a : Failed to Write @TargetOffset 0x%x (0x%x)\n",
> + __FUNCTION__, TargetOffsetinBytes, Status));
> + goto EXIT;
> + }
> +
> + TargetOffsetinBytes += IntBytes; /* adjust pointers and counter */
> + BufferSizeInBytes -= IntBytes;
> + Buffer += IntBytes;
> +
> + if (BufferSizeInBytes == 0) {
> + goto EXIT;
> + }
> + }
> +
> + // Write the bytes to CFI width aligned address.
> + // Note we can Write number of bytes=CFI width in one operation
> + WordsToWrite = BufferSizeInBytes / sizeof (FLASH_DATA);
> + SrcBuffer = (FLASH_DATA*)Buffer;
> +
> + Status = NorFlashPlatformWriteWordAlignedAddressBuffer (
> + Instance,
> + (UINTN)(TargetOffsetinBytes/sizeof (FLASH_DATA)),
> + WordsToWrite,
> + SrcBuffer);
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a : Failed to Write @ TargetOffset 0x%x (0x%x)\n",
> + __FUNCTION__, TargetOffsetinBytes, Status));
> + goto EXIT;
> + }
> +
> + BufferSizeInBytes -= (WordsToWrite * sizeof (FLASH_DATA));
> + Buffer += (WordsToWrite*sizeof (FLASH_DATA));
> + TargetOffsetinBytes += (WordsToWrite * sizeof (FLASH_DATA));
> +
> + if (BufferSizeInBytes == 0) {
> + goto EXIT;
> + }
> +
> + // Now Write bytes that are remaining and are less than CFI width.
> + // Read the first few to get Read buffer aligned
> + NorFlashPlatformRead (
> + Instance,
> + Lba,
> + TargetOffsetinBytes - GET_BLOCK_OFFSET (Lba),
> + sizeof (TempWrite),
> + (UINT8*)&TempWrite);
> +
> + CopyFrom = Buffer;
> + CopyTo = &TempWrite;
> +
> + CopyMem (CopyTo, CopyFrom, BufferSizeInBytes);
> +
> + Status = NorFlashPlatformWriteWordAlignedAddressBuffer (
> + Instance,
> + (UINTN)(TargetOffsetinBytes/sizeof (FLASH_DATA)),
> + 1,
> + &TempWrite
> + );
> +
> + if (EFI_ERROR(Status)) {
> + DEBUG((DEBUG_ERROR, "%a: Failed to Write @TargetOffset 0x%x Status=%d\n",
> + __FUNCTION__, TargetOffsetinBytes, Status));
> + goto EXIT;
> + }
> +
> +EXIT:
> + // Put device back into Read Array mode (via Reset)
> + NorFlashPlatformReset (Instance->DeviceBaseAddress);
> + return (Status);
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformRead (
> + IN NOR_FLASH_INSTANCE *Instance,
> + IN EFI_LBA Lba,
> + IN UINTN Offset,
> + IN UINTN BufferSizeInBytes,
> + OUT UINT8 *Buffer
> + )
> +{
> + UINTN IntBytes;
> + UINTN Mask;
> + FLASH_DATA TempRead;
> + VOID *CopyFrom;
> + VOID *CopyTo;
> + UINTN TargetOffsetinBytes;
> + FLASH_DATA *ReadData;
> + UINTN BlockSize;
> +
> + IntBytes = BufferSizeInBytes; //Intermediate Bytes needed to copy for alignment
> + Mask = sizeof (FLASH_DATA) - 1;
> + TempRead = 0;
> + TargetOffsetinBytes = (UINTN)(GET_BLOCK_OFFSET (Lba) + Offset);
> + BlockSize = Instance->Media.BlockSize;
> +
> + DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=%ld, Offset=0x%x,"
> + " BufferSizeInBytes=0x%x, Buffer @ 0x%p)\n",
> + __FUNCTION__, Lba, Offset, BufferSizeInBytes, Buffer));
> +
> + // The buffer must be valid
> + if (Buffer == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Return if we have not any byte to read
> + if (BufferSizeInBytes == 0) {
> + return EFI_SUCCESS;
> + }
> +
> + if (((Lba * BlockSize) + BufferSizeInBytes) > Instance->Size) {
> + DEBUG ((DEBUG_ERROR, "%a : Read will exceed device size.\n", __FUNCTION__));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Put device back into Read Array mode (via Reset)
> + NorFlashPlatformReset (Instance->DeviceBaseAddress);
> +
> + // First Read bytes to make buffer aligned to CFI width
> + if (TargetOffsetinBytes & Mask) {
> + // Read only as much as necessary, so pick the lower of the two numbers
> + if (BufferSizeInBytes < (sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask))) {
> + IntBytes = BufferSizeInBytes;
> + } else {
> + IntBytes = sizeof (FLASH_DATA) - (TargetOffsetinBytes & Mask);
> + }
> +
> + // Read the first few to get Read buffer aligned
> + TempRead = MmioRead16 (
> + CREATE_NOR_ADDRESS (
> + Instance->DeviceBaseAddress,
> + CREATE_BYTE_OFFSET ((TargetOffsetinBytes & ~Mask) / sizeof (FLASH_DATA))
> + )
> + );
> +
> + CopyFrom = (UINT8*)&TempRead;
> + CopyFrom += (TargetOffsetinBytes & Mask);
> + CopyTo = Buffer;
> +
> + CopyMem (CopyTo, CopyFrom, IntBytes);
> +
> + TargetOffsetinBytes += IntBytes; // adjust pointers and counter
> + BufferSizeInBytes -= IntBytes;
> + Buffer += IntBytes;
> + if (BufferSizeInBytes == 0) {
> + return EFI_SUCCESS;
> + }
> + }
> +
> + ReadData = (FLASH_DATA*)Buffer;
> +
> + // Readout the bytes from CFI width aligned address.
> + // Note we can read number of bytes=CFI width in one operation
> + while (BufferSizeInBytes >= sizeof (FLASH_DATA)) {
> + *ReadData = MmioRead16 (
> + CREATE_NOR_ADDRESS (
> + Instance->DeviceBaseAddress,
> + CREATE_BYTE_OFFSET (TargetOffsetinBytes / sizeof (FLASH_DATA))
> + )
> + );
> + ReadData += 1;
> + BufferSizeInBytes -= sizeof (FLASH_DATA);
> + TargetOffsetinBytes += sizeof (FLASH_DATA);
> + }
> +
> + if (BufferSizeInBytes == 0) {
> + return EFI_SUCCESS;
> + }
> +
> + // Now read bytes that are remaining and are less than CFI width.
> + CopyTo = ReadData;
> + // Read the first few to get Read buffer aligned
> + TempRead = MmioRead16 (
> + CREATE_NOR_ADDRESS (
> + Instance->DeviceBaseAddress,
> + CREATE_BYTE_OFFSET (TargetOffsetinBytes/sizeof (FLASH_DATA))
> + )
> + );
> + CopyFrom = &TempRead;
> +
> + CopyMem (CopyTo, CopyFrom, BufferSizeInBytes);
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformReset (
> + IN UINTN DeviceBaseAddress
> + )
> +{
> + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, CMD_RESET_FIRST);
> +
> + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR, CMD_RESET_SECOND);
> +
> + SEND_NOR_COMMAND (DeviceBaseAddress, 0, CMD_RESET);
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +NorFlashInitMmioOps (
> + VOID
> + )
> +{
> + mMmioOps = GetMmioOperations16 (FixedPcdGetBool (PcdIfcBigEndian));
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformGetDevices (
> + OUT NorFlashDescription **NorFlashDevices,
> + OUT UINT32 *Count
> + )
> +{
> + // This is the function to be called, before using
> + if ((NorFlashDevices == NULL) || (Count == NULL)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Get the number of NOR flash devices supported
> + *NorFlashDevices = mNorFlashDevices;
> + *Count = NOR_FLASH_DEVICE_COUNT;
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +NorFlashPlatformFlashGetAttributes (
> + OUT NorFlashDescription *NorFlashDevices,
> + IN UINT32 Count
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 Index;
> +
> + if ((NorFlashDevices == NULL) || (Count == 0)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Check the attributes of the NOR flash slave we are connected to.
> + // Currently we support only CFI flash devices. Bail-out otherwise.
> + Status = CfiNorFlashFlashGetAttributes (NorFlashDevices, Count);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + // Limit the Size of Nor Flash that can be programmed
> + for (Index = 0; Index < Count; Index++) {
> + NorFlashDevices[Index].RegionBaseAddress = PcdGet64 (PcdFlashReservedRegionBase64);
> + NorFlashDevices[Index].Size -= (NorFlashDevices[Index].RegionBaseAddress -
> + NorFlashDevices[Index].DeviceBaseAddress);
> + if ((NorFlashDevices[Index].RegionBaseAddress - NorFlashDevices[Index].DeviceBaseAddress)
> + % NorFlashDevices[Index].BlockSize)
> + {
> + DEBUG ((DEBUG_ERROR, "%a : Reserved Region(0x%p) doesn't start "
> + "from block boundry(0x%08x)\n", __FUNCTION__,
> + (UINTN)NorFlashDevices[Index].RegionBaseAddress,
> + (UINT32)NorFlashDevices[Index].BlockSize));
> + return EFI_DEVICE_ERROR;
> + }
> + }
> + return Status;
> +}
> diff --git a/Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
> new file mode 100644
> index 0000000..e0370b9
> --- /dev/null
> +++ b/Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
> @@ -0,0 +1,43 @@
> +# @NorFlashLib.inf
> +#
> +# Component description file for NorFlashLib module
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = NorFlashLib
> + FILE_GUID = f3176a49-dde1-450d-a909-8580c03b9ba8
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = NorFlashLib
> + CONSTRUCTOR = NorFlashInitMmioOps
> +
> +[Sources.common]
> + CfiNorFlashLib.c
> + NorFlashLib.c
> +
> +[LibraryClasses]
> + ArmLib
> + IoAccessLib
> + TimerLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[Pcd.common]
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 17/41] Silicon/NXP : Add NOR driver.
2018-11-28 15:01 ` [PATCH edk2-platforms 17/41] Silicon/NXP : Add NOR driver Meenakshi Aggarwal
@ 2018-12-19 18:32 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-19 18:32 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Wed, Nov 28, 2018 at 08:31:31PM +0530, Meenakshi Aggarwal wrote:
> Add NOR DXE phase driver, it installs BlockIO and Fvp
> protocol.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 98 +++
> .../NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c | 252 +++++++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c | 503 +++++++++++++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h | 146 ++++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf | 65 ++
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c | 816 +++++++++++++++++++++
> 6 files changed, 1880 insertions(+)
> create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.h
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> create mode 100644 Silicon/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
> new file mode 100644
> index 0000000..e254337
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc
> @@ -0,0 +1,98 @@
> +## @file
> +# FDF include file with FD definition that defines an empty variable store.
> +#
> +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
> +# Copyright (C) 2014, Red Hat, Inc.
> +# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
> +# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available
> +# under the terms and conditions of the BSD License which accompanies this
> +# distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> +# IMPLIED.
> +#
> +##
> +
> +[FD.LS1043aRdbNv_EFI]
> +BaseAddress = 0x60300000 #The base address of the FLASH device
> +Size = 0x000C0000 #The size in bytes of the FLASH device
> +ErasePolarity = 1
> +BlockSize = 0x1
> +NumBlocks = 0xC0000
> +
> +#
> +# Place NV Storage just above Platform Data Base
> +#
> +DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
> +DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
> +DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
> +DEFINE FTW_WORKING_SIZE = 0x00040000
> +DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
> +DEFINE FTW_SPARE_SIZE = 0x00040000
> +
> +#############################################################################
> +# LS1043ARDB NVRAM Area
> +# LS1043ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
> +#############################################################################
> +
> +
> +$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +#NV_VARIABLE_STORE
> +DATA = {
> + ## This is the EFI_FIRMWARE_VOLUME_HEADER
> + # ZeroVector []
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + # FileSystemGuid: gEfiSystemNvDataFvGuid =
> + # { 0xFFF12B8D, 0x7696, 0x4C8B,
> + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
> + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
> + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
> + # FvLength: 0xC0000
> + 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
> + # Signature "_FVH" # Attributes
> + 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
> + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
> + 0x48, 0x00, 0xC2, 0xF9, 0x00, 0x00, 0x00, 0x02,
> + # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
> + 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
> + # Blockmap[1]: End
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + ## This is the VARIABLE_STORE_HEADER
> + # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
> + # Signature: gEfiAuthenticatedVariableGuid =
> + # { 0xaaf32c78, 0x947b, 0x439a,
> + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
> + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
> + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
> + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
> + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
> + # This can speed up the Variable Dispatch a bit.
> + 0xB8, 0xFF, 0x03, 0x00,
> + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
> + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +#NV_FTW_WORKING
> +DATA = {
> + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
> + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
> + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
> + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
> + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
> + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
> + # WriteQueueSize: UINT64
> + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +#NV_FTW_SPARE
> diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
> new file mode 100644
> index 0000000..bc49fdc
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
> @@ -0,0 +1,252 @@
> +/** @NorFlashBlockIoDxe.c
> +
> + Based on NorFlash implementation available in
> + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c
> +
> + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/DebugLib.h>
> +#include <Library/NorFlashLib.h>
> +
> +#include <NorFlash.h>
> +#include "NorFlashDxe.h"
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoReset (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN BOOLEAN ExtendedVerification
> + )
> +{
> + NOR_FLASH_INSTANCE *Instance;
> +
> + Instance = INSTANCE_FROM_BLKIO_THIS (This);
> +
> + DEBUG ((DEBUG_INFO, "NorFlashBlockIoReset (MediaId=0x%x)\n",
> + This->Media->MediaId));
> +
> + return NorFlashPlatformReset (Instance->DeviceBaseAddress);
> +}
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoReadBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN UINT32 MediaId,
> + IN EFI_LBA Lba,
> + IN UINTN BufferSizeInBytes,
> + OUT VOID *Buffer
> + )
> +{
> + NOR_FLASH_INSTANCE *Instance;
> + EFI_STATUS Status;
> + EFI_BLOCK_IO_MEDIA *Media;
> + UINTN NumBlocks;
> + UINT8 *ReadBuffer;
> + UINTN BlockCount;
> + UINTN BlockSizeInBytes;
> + EFI_LBA CurrentBlock;
> +
> + Status = EFI_SUCCESS;
> +
> + if ((This == NULL) || (Buffer == NULL)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Instance = INSTANCE_FROM_BLKIO_THIS (This);
> + Media = This->Media;
> +
> + if (Media == NULL) {
> + DEBUG ((DEBUG_ERROR, "%a : Media is NULL\n", __FUNCTION__));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + NumBlocks = BufferSizeInBytes / Instance->Media.BlockSize ;
> +
> + DEBUG ((DEBUG_BLKIO,
> + "%a : (MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%p)\n",
> + __FUNCTION__, MediaId, Lba, BufferSizeInBytes, Buffer));
> +
> + if (!Media->MediaPresent) {
> + return EFI_NO_MEDIA;
> + }
> + if (Media->MediaId != MediaId) {
> + return EFI_MEDIA_CHANGED;
> + }
> + if ((Media->IoAlign >= 2) && (((UINTN)Buffer & (Media->IoAlign - 1)) != 0)) {
> + return EFI_INVALID_PARAMETER;
> + }
> + if (BufferSizeInBytes == 0) {
> + // Return if we have not any byte to read
> + return EFI_SUCCESS;
> + }
> + if ((BufferSizeInBytes % Media->BlockSize) != 0) {
> + // The size of the buffer must be a multiple of the block size
> + DEBUG ((DEBUG_ERROR, "%a : BlockSize in bytes = 0x%x\n", __FUNCTION__, BufferSizeInBytes));
> + return EFI_INVALID_PARAMETER;
> + }
> + if ((Lba + NumBlocks - 1) > Media->LastBlock) {
> + // All blocks must be within the device
> + DEBUG ((DEBUG_ERROR, "%a : Read will exceed last block %d, %d, %d \n",
> + __FUNCTION__, Lba, NumBlocks, Media->LastBlock));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + BlockSizeInBytes = Instance->Media.BlockSize;
> +
> + /* Because the target *Buffer is a pointer to VOID,
> + * we must put all the data into a pointer
> + * to a proper data type, so use *ReadBuffer */
> + ReadBuffer = (UINT8 *)Buffer;
> +
> + CurrentBlock = Lba;
> + // Read data block by Block
> + for (BlockCount = 0; BlockCount < NumBlocks; BlockCount++) {
> + DEBUG ((DEBUG_BLKIO, "%a: Reading block #%d\n", __FUNCTION__, (UINTN)CurrentBlock));
> +
> + Status = NorFlashPlatformRead (Instance, CurrentBlock, (UINTN)0 ,
> + BlockSizeInBytes, ReadBuffer);
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> +
> + CurrentBlock++;
> + ReadBuffer = ReadBuffer + BlockSizeInBytes;
> + }
> +
> + return Status;
> +}
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoWriteBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This,
> + IN UINT32 MediaId,
> + IN EFI_LBA Lba,
> + IN UINTN BufferSizeInBytes,
> + IN VOID *Buffer
> + )
> +{
> + NOR_FLASH_INSTANCE *Instance;
> + EFI_STATUS Status;
> + EFI_BLOCK_IO_MEDIA *Media;
> + UINTN NumBlocks;
> + EFI_LBA CurrentBlock;
> + UINTN BlockSizeInBytes;
> + UINT32 BlockCount;
> + UINTN SectorAddress;
> + UINT8 *WriteBuffer;
> +
> + Status = EFI_SUCCESS;
> +
> + if ((This == NULL) || (Buffer == NULL)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Instance = INSTANCE_FROM_BLKIO_THIS (This);
> + Media = This->Media;
> +
> + if (Media == NULL) {
> + DEBUG ((DEBUG_ERROR, "%a : Media is NULL\n", __FUNCTION__));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + NumBlocks = BufferSizeInBytes / Instance->Media.BlockSize ;
> +
> + DEBUG ((DEBUG_BLKIO,
> + "%a : (MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB) BufferPtr @ 0x%08x)\n",
> + __FUNCTION__, MediaId, Lba, BufferSizeInBytes, Buffer));
> +
> + if (!Media->MediaPresent) {
> + return EFI_NO_MEDIA;
> + }
> + if (Media->MediaId != MediaId) {
> + return EFI_MEDIA_CHANGED;
> + }
> + if (Media->ReadOnly) {
> + return EFI_WRITE_PROTECTED;
> + }
> + if (BufferSizeInBytes == 0) {
> + return EFI_BAD_BUFFER_SIZE;
> + }
> + if ((BufferSizeInBytes % Media->BlockSize) != 0) {
> + // The size of the buffer must be a multiple of the block size
> + DEBUG ((DEBUG_ERROR, "%a : BlockSize in bytes = 0x%x\n",__FUNCTION__, BufferSizeInBytes));
> + return EFI_INVALID_PARAMETER;
> + }
> + if ((Lba + NumBlocks - 1) > Media->LastBlock) {
> + // All blocks must be within the device
> + DEBUG ((DEBUG_ERROR, "%a: Write will exceed last block %d, %d, %d \n",
> + __FUNCTION__,Lba, NumBlocks, Media->LastBlock));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + BlockSizeInBytes = Instance->Media.BlockSize;
> +
> + WriteBuffer = (UINT8 *)Buffer;
> +
> + CurrentBlock = Lba;
> + // Program data block by Block
> + for (BlockCount = 0; BlockCount < NumBlocks; BlockCount++) {
> + DEBUG ((DEBUG_BLKIO, "%a: Writing block #%d\n", __FUNCTION__, (UINTN)CurrentBlock));
> + // Erase the Block(Sector) to be written to
> + SectorAddress = GET_NOR_BLOCK_ADDRESS (
> + Instance->RegionBaseAddress,
> + CurrentBlock,
> + Instance->Media.BlockSize
> + );
> +
> + Status = NorFlashPlatformEraseSector (Instance, (UINTN)SectorAddress);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a: Failed to erase Target 0x%x (0x%x) \n",
> + __FUNCTION__,SectorAddress, Status));
> + break;
> + }
> +
> + // Program Block(Sector) to be written to
> + Status = NorFlashWrite (Instance, CurrentBlock, (UINTN)0, &BlockSizeInBytes, WriteBuffer);
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> +
> + CurrentBlock++;
> + WriteBuffer = WriteBuffer + BlockSizeInBytes;
> + }
> +
> + return Status;
> +}
> +
> +//
> +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
> +//
> +EFI_STATUS
> +EFIAPI
> +NorFlashBlockIoFlushBlocks (
> + IN EFI_BLOCK_IO_PROTOCOL *This
> + )
> +{
> + DEBUG ((DEBUG_BLKIO, "%a NOT IMPLEMENTED (not required)\n", __FUNCTION__));
> +
> + // Nothing to do so just return without error
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
> new file mode 100644
> index 0000000..ab94662
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.c
> @@ -0,0 +1,503 @@
> +/** @file
> +
> + Based on NorFlash implementation available in
> + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c
> +
> + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/NorFlashLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiRuntimeLib.h>
> +
> +#include "NorFlashDxe.h"
> +
> +STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent;
> +
> +//
> +// Global variable declarations
> +//
> +NOR_FLASH_INSTANCE **mNorFlashInstances;
> +UINT32 mNorFlashDeviceCount;
Can the two above be STATIC?
Other than that, the only comment I have on the remainder of this
patch is that there are some _very_ long lines here, across multiple
files.
Some, like the "| // ...." comments are probably more helpful to keep
like that.
But for the actual functional bits of code, please try to stay below
(or near) 80 characters per line.
/
Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 18/41] LS1043 : Enable NOR driver for LS1043aRDB package.
2018-11-28 15:01 ` [PATCH edk2-platforms 18/41] LS1043 : Enable NOR driver for LS1043aRDB package Meenakshi Aggarwal
@ 2018-12-19 18:33 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-19 18:33 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Wed, Nov 28, 2018 at 08:31:32PM +0530, Meenakshi Aggarwal wrote:
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
I think I actually gave a
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
for this one last round.
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 15 ++++++++++++++-
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 9 ++++++++-
> 2 files changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index 48a7b5a..9a68cfd 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -41,6 +41,7 @@
> IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
> BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
> FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf
> + NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
>
> [PcdsFixedAtBuild.common]
>
> @@ -65,6 +66,13 @@
> gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
> gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
>
> + #
> + # NV Storage PCDs
> + #
> + gArmTokenSpaceGuid.PcdVFPEnabled|1
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000
> +
> ################################################################################
> #
> # Components Section - list of all EDK II Modules needed by this Platform
> @@ -74,10 +82,15 @@
> #
> # Architectural Protocols
> #
> - MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
> + }
> + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
>
> Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> + Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
>
> ##
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> index 417303d..6b27aed 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> @@ -55,6 +55,7 @@ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> FV = FVMAIN_COMPACT
>
> !include Platform/NXP/FVRules.fdf.inc
> +!include VarStore.fdf.inc
> ################################################################################
> #
> # FV Section
> @@ -104,7 +105,8 @@ READ_LOCK_STATUS = TRUE
> INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> - INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
>
> INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> @@ -124,6 +126,11 @@ READ_LOCK_STATUS = TRUE
> INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
>
> #
> + # NOR Driver
> + #
> + INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> +
> + #
> # Network modules
> #
> INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 19/41] Silicon/NXP:Add LS1046ARDB SoCLib Support
2018-11-28 15:01 ` [PATCH edk2-platforms 19/41] Silicon/NXP:Add LS1046ARDB SoCLib Support Meenakshi Aggarwal
@ 2018-12-19 18:41 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-19 18:41 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Vabhav
On Wed, Nov 28, 2018 at 08:31:33PM +0530, Meenakshi Aggarwal wrote:
> Provide Functions to initialize peripherals,
> print board and soc information.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 +
> Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 ++++++++++++++++++++++
> Silicon/NXP/LS1046A/LS1046A.dec | 22 +++++++++
> Silicon/NXP/LS1046A/LS1046A.dsc.inc | 68 ++++++++++++++++++++++++++++
> Silicon/NXP/Library/SocLib/Chassis.c | 1 +
> Silicon/NXP/Library/SocLib/Chassis.h | 1 +
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 48 ++++++++++++++++++++
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 2 +
> Silicon/NXP/Library/SocLib/LS1046aSocLib.inf | 53 ++++++++++++++++++++++
> Silicon/NXP/NxpQoriqLs.dec | 1 +
> 10 files changed, 252 insertions(+)
> create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec
> create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc.inc
> create mode 100644 Silicon/NXP/Library/SocLib/LS1046aSocLib.inf
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index 9a68cfd..b69ffa2 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -59,6 +59,7 @@
> gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
> + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|TRUE
>
> #
> # RTC Pcds
> diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h b/Silicon/NXP/LS1046A/Include/SocSerDes.h
> new file mode 100644
> index 0000000..957db0f
> --- /dev/null
> +++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h
> @@ -0,0 +1,55 @@
> +/** @file
> + The Header file of SerDes Module
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __LS1046A_SERDES_H__
> +#define __LS1046A_SERDES_H__
> +
> +#include <Chassis2/SerDes.h>
> +
> +SERDES_CONFIG SerDes1ConfigTbl[] = {
Whoops. I didn't pick up on this last time:
https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/5_source_files/53_include_files.html#537-include-files-shall-not-generate-code-or-define-data-variables
Can you move this to a .c file?
I guess this and SerDes2ConfigTbl could both be marked STATIC?
> + /* SerDes 1 */
> + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE } },
> + {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE } },
> + {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6 } },
> + {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, SGMII_FM1_DTSEC6 } },
> + {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, SGMII_FM1_DTSEC6 } },
> + {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6 } },
> + {}
> +};
> +
> +SERDES_CONFIG SerDes2ConfigTbl[] = {
> + /* SerDes 2 */
> + {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1 } },
> + {0x5559, {PCIE1, PCIE2, PCIE3, SATA } },
> + {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3 } },
> + {0x5506, {PCIE1, PCIE2, NONE, PCIE3 } },
> + {0x0506, {NONE, PCIE2, NONE, PCIE3 } },
> + {0x0559, {NONE, PCIE2, PCIE3, SATA } },
> + {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA } },
> + {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3 } },
> + {}
> +};
> +
> +SERDES_CONFIG *SerDesConfigTbl[] = {
> + SerDes1ConfigTbl,
> + SerDes2ConfigTbl
> +};
> +
> +#endif /* __LS1046A_SERDES_H */
> diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.dec
> new file mode 100644
> index 0000000..93fc80d
> --- /dev/null
> +++ b/Silicon/NXP/LS1046A/LS1046A.dec
> @@ -0,0 +1,22 @@
> +# LS1046A.dec
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x0001000A
1A?
(If that makes sense after changes.)
/
Leif
> +
> +[Guids.common]
> + gNxpLs1046ATokenSpaceGuid = {0x8d7ffac8, 0xb4d5, 0x43c3, {0xaa, 0x27, 0x84, 0xbc, 0x12, 0x01, 0x28, 0x10}}
> +
> +[Includes]
> + Include
> diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> new file mode 100644
> index 0000000..9f87028
> --- /dev/null
> +++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> @@ -0,0 +1,68 @@
> +# LS1046A.dsc
> +# LS1046A Soc package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +[PcdsDynamicDefault.common]
> +
> + #
> + # ARM General Interrupt Controller
> + gArmTokenSpaceGuid.PcdGicDistributorBase|0x01410000
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01420000
> +
> +[PcdsFixedAtBuild.common]
> +
> + #
> + # CCSR Address Space and other attached Memories
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
> + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000
> + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
> +
> +##
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> index 851174c..e8e69a6 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> @@ -45,6 +45,7 @@ GurRead (
> */
> STATIC CPU_TYPE CpuTypeList[] = {
> CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
> + CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
> };
>
> /*
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.h b/Silicon/NXP/Library/SocLib/Chassis.h
> index 5aa1209..5b7e5c4 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis.h
> +++ b/Silicon/NXP/Library/SocLib/Chassis.h
> @@ -56,6 +56,7 @@ CpuMaskNext (
>
> #define SVR_WO_E 0xFFFFFE
> #define SVR_LS1043A 0x879200
> +#define SVR_LS1046A 0x870700
>
> #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> #define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> index e79728e..62d761e 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> @@ -20,6 +20,7 @@
> #include <Library/BaseMemoryLib.h>
> #include <Library/DebugLib.h>
> #include <Library/IfcLib.h>
> +#include <Library/IoAccessLib.h>
> #include <Library/IoLib.h>
> #include <Library/PcdLib.h>
> #include <Library/PrintLib.h>
> @@ -138,6 +139,43 @@ GetSysInfo (
> }
>
> /**
> + Function to select pins depending upon pcd using supplemental
> + configuration unit(SCFG) extended RCW controlled pinmux control
> + register which contains the bits to provide pin multiplexing control.
> + This register is reset on HRESET.
> + **/
> +VOID
> +ConfigScfgMux (VOID)
> +{
> + CCSR_SCFG *Scfg;
> + UINT32 UsbPwrFault;
> +
> + Scfg = (VOID *)PcdGet64 (PcdScfgBaseAddr);
> + // Configures functionality of the IIC3_SCL to USB2_DRVVBUS
> + // Configures functionality of the IIC3_SDA to USB2_PWRFAULT
> +
> + // LS1043A
> + // Configures functionality of the IIC4_SCL to USB3_DRVVBUS
> + // Configures functionality of the IIC4_SDA to USB3_PWRFAULT
> +
> + // LS1046A
> + // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
> + if (PcdGetBool (PcdMuxToUsb3)) {
> + SwapMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_SELCR_USB);
> + } else {
> + SwapMmioWrite32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB);
> + }
> +
> + SwapMmioWrite32 ((UINTN)&Scfg->UsbDrvVBusSelCr, CCSR_SCFG_USBDRVVBUS_SELCR_USB1);
> + UsbPwrFault =
> + (CCSR_SCFG_USBPWRFAULT_DEDICATED << CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) |
> + (CCSR_SCFG_USBPWRFAULT_DEDICATED << CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) |
> + (CCSR_SCFG_USBPWRFAULT_SHARED << CCSR_SCFG_USBPWRFAULT_USB1_SHIFT);
> +
> + SwapMmioWrite32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault);
> +}
> +
> +/**
> Function to initialize SoC specific constructs
> CPU Info
> SoC Personality
> @@ -167,6 +205,16 @@ SocInit (
> PrintSoc ();
> IfcInit ();
> PrintBoardPersonality ();
> + //
> + // Due to the extensive functionality present on the chip and the limited number of external
> + // signals available, several functional blocks share signal resources through multiplexing.
> + // In this case when there is alternate functionality between multiple functional blocks,
> + // the signal's function is determined at the chip level (rather than at the block level)
> + // typically by a reset configuration word (RCW) option. Some of the signals' function are
> + // determined externel to RCW at Power-on Reset Sequence.
> + //
> + ConfigScfgMux ();
> +
>
> return;
> }
> diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> index af0790f..d93d66a 100644
> --- a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> @@ -47,5 +47,7 @@
> gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> diff --git a/Silicon/NXP/Library/SocLib/LS1046aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1046aSocLib.inf
> new file mode 100644
> index 0000000..7eb0180
> --- /dev/null
> +++ b/Silicon/NXP/Library/SocLib/LS1046aSocLib.inf
> @@ -0,0 +1,53 @@
> +# @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = SocLib
> + FILE_GUID = ddd5f950-8816-4d38-8f98-f42b07333f78
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SocLib
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/LS1046A/LS1046A.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + FpgaLib
> + IfcLib
> + IoAccessLib
> + SerialPortLib
> +
> +[Sources.common]
> + Chassis.c
> + Chassis2/Soc.c
> + SerDes.c
> +
> +[BuildOptions]
> + GCC:*_*_*_CC_FLAGS = -DCHASSIS2
> +
> +[FixedPcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index bd89da4..159ea65 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -101,6 +101,7 @@
> #
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
> gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
> + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE|BOOLEAN|0x00000252
>
> #
> # Clock PCDs
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 20/41] Silicon/NXP:Add support for PCF2129 Real Time Clock Library
2018-11-28 15:01 ` [PATCH edk2-platforms 20/41] Silicon/NXP:Add support for PCF2129 Real Time Clock Library Meenakshi Aggarwal
@ 2018-12-19 18:52 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-19 18:52 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Vabhav
On Wed, Nov 28, 2018 at 08:31:34PM +0530, Meenakshi Aggarwal wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Library to provide functions for NXP pcf2129 real time clock library
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Platform/NXP/NxpQoriqLs.dsc.inc | 1 +
> Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h | 52 +++
> Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c | 389 +++++++++++++++++++++
> .../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec | 29 ++
> .../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf | 47 +++
> 5 files changed, 518 insertions(+)
> create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec
> create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
>
> diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
> index 972dadc..5529a04 100644
> --- a/Platform/NXP/NxpQoriqLs.dsc.inc
> +++ b/Platform/NXP/NxpQoriqLs.dsc.inc
> @@ -34,6 +34,7 @@
> ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
> ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
> TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
> + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
> ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
> HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
> diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> new file mode 100644
> index 0000000..c862954
> --- /dev/null
> +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h
> @@ -0,0 +1,52 @@
> +/** Pcf2129Rtc.h
> +*
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __PCF2129RTC_H__
> +#define __PCF2129RTC_H__
> +
> +/*
> + * RTC register addresses
> + */
> +#define PCF2129_CTRL1_REG_ADDR 0x00 // Control Register 1
> +#define PCF2129_CTRL2_REG_ADDR 0x01 // Control Register 2
> +#define PCF2129_CTRL3_REG_ADDR 0x02 // Control Register 3
> +#define PCF2129_SEC_REG_ADDR 0x03
> +#define PCF2129_MIN_REG_ADDR 0x04
> +#define PCF2129_HR_REG_ADDR 0x05
> +#define PCF2129_DAY_REG_ADDR 0x06
> +#define PCF2129_WEEKDAY_REG_ADDR 0x07
> +#define PCF2129_MON_REG_ADDR 0x08
> +#define PCF2129_YR_REG_ADDR 0x09
> +
> +#define PCF2129_CTRL3_BIT_BLF BIT2 /* Battery Low Flag*/
> +
> +/*
> + * Masks for RTC registers
> + */
> +#define PCF2129_SECONDS_MASK 0x7F
> +#define PCF2129_MINUTES_MASK 0x7F
> +#define PCF2129_HOURS_MASK 0x3F
> +#define PCF2129_DAYS_MASK 0x3F
> +#define PCF2129_MONTHS_MASK 0x1F
> +
> +#define EPOCH_BASE_1990 1990
> +#define EPOCH_BASE_2000 2000
Too generic names.
Either add to edk2/EmbeddedPkg/Include/Library/TimeBaseLib.h
or add PCF2129_ prefix.
> +
> +typedef struct {
> + UINTN OperationCount;
> + EFI_I2C_OPERATION SetAddressOp;
> + EFI_I2C_OPERATION GetSetDateTimeOp;
> +} RTC_I2C_REQUEST;
PCF2129_I2C_REQUEST?
> +
> +#endif // __PCF2129RTC_H__
> diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> new file mode 100644
> index 0000000..90bad66
> --- /dev/null
> +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c
> @@ -0,0 +1,389 @@
> +/** @PCF2129RtcLib.c
> + Implement EFI RealTimeClock with runtime services via RTC Lib for PCF2129 RTC.
> +
> + Based on RTC implementation available in
> + EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
> +
> + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/RealTimeClockLib.h>
> +#include <Library/TimeBaseLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +#include <Protocol/I2cMaster.h>
> +
> +#include "Pcf2129Rtc.h"
> +
> +STATIC VOID *mDriverEventRegistration;
> +STATIC EFI_HANDLE mI2cMasterHandle;
> +STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
> +
> +/**
> + Write RTC register.
> +
> + @param RtcRegAddr Register offset of RTC to write.
> + @param Val Value to be written
> +
> +**/
> +
> +STATIC
> +VOID
> +RtcWrite (
> + IN UINT8 RtcRegAddr,
> + IN UINT8 Val
Val -> Value. (Throughout.)
> + )
> +{
> + RTC_I2C_REQUEST Req;
Req -> Request. (Throughout.)
With those two changes:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> + EFI_STATUS Status;
> +
> + Req.OperationCount = 2;
> +
> + Req.SetAddressOp.Flags = 0;
> + Req.SetAddressOp.LengthInBytes = 0;
> + Req.SetAddressOp.Buffer = &RtcRegAddr;
> +
> + Req.GetSetDateTimeOp.Flags = 0;
> + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
> + Req.GetSetDateTimeOp.Buffer = &Val;
> +
> + Status = mI2cMaster->StartRequest (
> + mI2cMaster,
> + FixedPcdGet8 (PcdI2cSlaveAddress),
> + (VOID *)&Req,
> + NULL,
> + NULL
> + );
> +
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
> + }
> +
> +}
> +
> +/**
> + Returns the current time and date information, and the time-keeping capabilities
> + of the hardware platform.
> +
> + @param Time A pointer to storage to receive a snapshot of the current time.
> + @param Capabilities An optional pointer to a buffer to receive the real time clock
> + device's capabilities.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_INVALID_PARAMETER Time is NULL.
> + @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
> +
> +**/
> +
> +EFI_STATUS
> +EFIAPI
> +LibGetTime (
> + OUT EFI_TIME *Time,
> + OUT EFI_TIME_CAPABILITIES *Capabilities
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 Buffer[10];
> + RTC_I2C_REQUEST Req;
> + UINT8 RtcRegAddr;
> + UINT16 EpochBase;
> +
> + Status = EFI_SUCCESS;
> + RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
> + Buffer[0] = 0;
> +
> + if (mI2cMaster == NULL) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + RtcWrite (PCF2129_CTRL1_REG_ADDR, Buffer[0]);
> +
> + if (Time == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Req.OperationCount = 2;
> +
> + Req.SetAddressOp.Flags = 0;
> + Req.SetAddressOp.LengthInBytes = 0;
> + Req.SetAddressOp.Buffer = &RtcRegAddr;
> +
> + Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
> + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Buffer);
> + Req.GetSetDateTimeOp.Buffer = Buffer;
> +
> + Status = mI2cMaster->StartRequest (
> + mI2cMaster,
> + FixedPcdGet8 (PcdI2cSlaveAddress),
> + (VOID *)&Req,
> + NULL,
> + NULL
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
> + }
> +
> + if (Buffer[PCF2129_CTRL3_REG_ADDR] & PCF2129_CTRL3_BIT_BLF) {
> + DEBUG((DEBUG_INFO, "### Warning: RTC battery status low, check/replace RTC battery.\n"));
> + }
> +
> + EpochBase = BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]) >= 98 ? EPOCH_BASE_1990 : EPOCH_BASE_2000;
> +
> + Time->Nanosecond = 0;
> + Time->Second = BcdToDecimal8 (Buffer[PCF2129_SEC_REG_ADDR] & PCF2129_SECONDS_MASK);
> + Time->Minute = BcdToDecimal8 (Buffer[PCF2129_MIN_REG_ADDR] & PCF2129_MINUTES_MASK);
> + Time->Hour = BcdToDecimal8 (Buffer[PCF2129_HR_REG_ADDR] & PCF2129_HOURS_MASK);
> + Time->Day = BcdToDecimal8 (Buffer[PCF2129_DAY_REG_ADDR] & PCF2129_DAYS_MASK);
> + Time->Month = BcdToDecimal8 (Buffer[PCF2129_MON_REG_ADDR] & PCF2129_MONTHS_MASK);
> + Time->Year = BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]) + EpochBase;
> +
> + return Status;
> +}
> +
> +/**
> + Sets the current local time and date information.
> +
> + @param Time A pointer to the current time.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_INVALID_PARAMETER A time field is out of range.
> + @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
> +
> +**/
> +
> +EFI_STATUS
> +EFIAPI
> +LibSetTime (
> + IN EFI_TIME *Time
> + )
> +{
> + UINT8 Buffer[8];
> + UINT8 Index;
> + EFI_STATUS Status;
> + RTC_I2C_REQUEST Req;
> + UINT8 RtcRegAddr;
> +
> + Index = 0;
> + Status = EFI_SUCCESS;
> + RtcRegAddr = PCF2129_CTRL1_REG_ADDR;
> +
> + if (mI2cMaster == NULL) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + // start register address
> + Buffer[Index++] = PCF2129_SEC_REG_ADDR;
> +
> + // hours, minutes and seconds
> + Buffer[Index++] = DecimalToBcd8 (Time->Second);
> + Buffer[Index++] = DecimalToBcd8 (Time->Minute);
> + Buffer[Index++] = DecimalToBcd8 (Time->Hour);
> + Buffer[Index++] = DecimalToBcd8 (Time->Day);
> + Buffer[Index++] = EfiTimeToWday (Time);
> + Buffer[Index++] = DecimalToBcd8 (Time->Month);
> + Buffer[Index++] = DecimalToBcd8 (Time->Year % 100);
> +
> + Req.OperationCount = 2;
> + Req.SetAddressOp.Flags = 0;
> + Req.SetAddressOp.LengthInBytes = 0;
> + Req.SetAddressOp.Buffer = &RtcRegAddr;
> +
> + Req.GetSetDateTimeOp.Flags = 0;
> + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Buffer);
> + Req.GetSetDateTimeOp.Buffer = Buffer;
> +
> + Status = mI2cMaster->StartRequest (
> + mI2cMaster,
> + FixedPcdGet8 (PcdI2cSlaveAddress),
> + (VOID *)&Req,
> + NULL,
> + NULL
> + );
> +
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
> + return Status;
> + }
> +
> + return Status;
> +}
> +
> +
> +/**
> + Returns the current wakeup alarm clock setting.
> +
> + @param Enabled Indicates if the alarm is currently enabled or disabled.
> + @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
> + @param Time The current alarm setting.
> +
> + @retval EFI_SUCCESS The alarm settings were returned.
> + @retval EFI_INVALID_PARAMETER Any parameter is NULL.
> + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
> + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibGetWakeupTime (
> + OUT BOOLEAN *Enabled,
> + OUT BOOLEAN *Pending,
> + OUT EFI_TIME *Time
> + )
> +{
> + // Not a required feature
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> +/**
> + Sets the system wakeup alarm clock time.
> +
> + @param Enabled Enable or disable the wakeup alarm.
> + @param Time If Enable is TRUE, the time to set the wakeup alarm for.
> +
> + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
> + Enable is FALSE, then the wakeup alarm was disabled.
> + @retval EFI_INVALID_PARAMETER A time field is out of range.
> + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
> + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibSetWakeupTime (
> + IN BOOLEAN Enabled,
> + OUT EFI_TIME *Time
> + )
> +{
> + // Not a required feature
> + return EFI_UNSUPPORTED;
> +}
> +
> +STATIC
> +VOID
> +I2cDriverRegistrationEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EFI_STATUS Status;
> + EFI_I2C_MASTER_PROTOCOL *I2cMaster;
> + UINTN BusFrequency;
> + EFI_HANDLE Handle;
> + UINTN BufferSize;
> +
> + //
> + // Try to connect the newly registered driver to our handle.
> + //
> + do {
> + BufferSize = sizeof (EFI_HANDLE);
> + Status = gBS->LocateHandle (ByRegisterNotify,
> + &gEfiI2cMasterProtocolGuid,
> + mDriverEventRegistration,
> + &BufferSize,
> + &Handle);
> + if (EFI_ERROR (Status)) {
> + if (Status != EFI_NOT_FOUND) {
> + DEBUG ((DEBUG_WARN, "%a: gBS->LocateHandle () returned %r\n",
> + __FUNCTION__, Status));
> + }
> + break;
> + }
> +
> + if (Handle != mI2cMasterHandle) {
> + continue;
> + }
> +
> + DEBUG ((DEBUG_INFO, "%a: found I2C master!\n", __FUNCTION__));
> +
> + gBS->CloseEvent (Event);
> +
> + Status = gBS->OpenProtocol (mI2cMasterHandle, &gEfiI2cMasterProtocolGuid,
> + (VOID **)&I2cMaster, gImageHandle, NULL,
> + EFI_OPEN_PROTOCOL_EXCLUSIVE);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = I2cMaster->Reset (I2cMaster);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
> + __FUNCTION__, Status));
> + break;
> + }
> +
> + BusFrequency = FixedPcdGet16 (PcdI2cBusFrequency);
> + Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
> + __FUNCTION__, Status));
> + break;
> + }
> +
> + mI2cMaster = I2cMaster;
> + break;
> + } while (TRUE);
> +}
> +
> +/**
> + This is the declaration of an EFI image entry point. This can be the entry point to an application
> + written to this specification, an EFI boot service driver, or an EFI runtime driver.
> +
> + @param ImageHandle Handle that identifies the loaded image.
> + @param SystemTable System Table for this image.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_DEVICE_ERROR The operation could not be started.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibRtcInitialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> +
> + EFI_STATUS Status;
> + UINTN BufferSize;
> +
> + //
> + // Find the handle that marks the controller
> + // that will provide the I2C master protocol.
> + //
> + BufferSize = sizeof (EFI_HANDLE);
> + Status = gBS->LocateHandle (
> + ByProtocol,
> + &gPcf2129RealTimeClockLibI2cMasterProtocolGuid,
> + NULL,
> + &BufferSize,
> + &mI2cMasterHandle
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Register a protocol registration notification callback on the driver
> + // binding protocol so we can attempt to connect our I2C master to it
> + // as soon as it appears.
> + //
> + EfiCreateProtocolNotifyEvent (
> + &gEfiI2cMasterProtocolGuid,
> + TPL_CALLBACK,
> + I2cDriverRegistrationEvent,
> + NULL,
> + &mDriverEventRegistration);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec
> new file mode 100644
> index 0000000..ea3fad6
> --- /dev/null
> +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec
> @@ -0,0 +1,29 @@
> +#/** @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#**/
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x0001001A
> + PACKAGE_NAME = Pcf2129RtcLib
> + PACKAGE_GUID = d6c2b7cf-4d3b-4173-8d99-fdcf9ba8403d
> + PACKAGE_VERSION = 0.1
> +
> +[Guids]
> + gPcf2129RtcLibTokenSpaceGuid = { 0xb67741d5, 0x0b12, 0x42e1, {0x85, 0xcd, 0x37, 0x1c, 0x5d, 0x59, 0xb7, 0xb0 }}
> +
> +[Protocols]
> + gPcf2129RealTimeClockLibI2cMasterProtocolGuid = { 0x8a1aac5e, 0xdffa, 0x4722, {0xba, 0x75, 0x55, 0x80, 0xda, 0x6a, 0x1b, 0x00 }}
> +
> +[PcdsFixedAtBuild]
> + gPcf2129RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001
> + gPcf2129RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002
> diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
> new file mode 100644
> index 0000000..fd19b63
> --- /dev/null
> +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
> @@ -0,0 +1,47 @@
> +#/** @Pcf2129RtcLib.inf
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = Pcf2129RtcLib
> + FILE_GUID = B661E02D-A90B-42AB-A5F9-CF841AAA43D9
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = RealTimeClockLib
> +
> +
> +[Sources.common]
> + Pcf2129RtcLib.c
> +
> +[Packages]
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec
> +
> +[LibraryClasses]
> + DebugLib
> + TimeBaseLib
> + UefiBootServicesTableLib
> + UefiLib
> +
> +[Protocols]
> + gEfiI2cMasterProtocolGuid ## CONSUMES
> + gPcf2129RealTimeClockLibI2cMasterProtocolGuid ## CONSUMES
> +
> +[Pcd]
> + gPcf2129RtcLibTokenSpaceGuid.PcdI2cSlaveAddress
> + gPcf2129RtcLibTokenSpaceGuid.PcdI2cBusFrequency
> +
> +[Depex]
> + gPcf2129RealTimeClockLibI2cMasterProtocolGuid ## CONSUMES
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 21/41] Platform/NXP: LS1046A RDB Board Library
2018-11-28 15:01 ` [PATCH edk2-platforms 21/41] Platform/NXP: LS1046A RDB Board Library Meenakshi Aggarwal
@ 2018-12-19 18:54 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-19 18:54 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Vabhav
On Wed, Nov 28, 2018 at 08:31:35PM +0530, Meenakshi Aggarwal wrote:
> Library to provide board specific timings for LS1046ARDB
> board with interfacing to IFC controller for accessing
> FPGA and NAND.
Expand IFC in commit message, please.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> .../NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h | 83 ++++++++++++++++++++++
> .../NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c | 61 ++++++++++++++++
> .../LS1046aRdbPkg/Library/BoardLib/BoardLib.inf | 31 ++++++++
> 3 files changed, 175 insertions(+)
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
>
> diff --git a/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h b/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
> new file mode 100644
> index 0000000..e15100d
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Include/IfcBoardSpecific.h
> @@ -0,0 +1,83 @@
> +/** IfcBoardSpecificLib.h
> +
> + IFC Flash Board Specific Macros and structure
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +#ifndef __IFC__BOARD_SPECIFIC_H__
> +#define __IFC__BOARD_SPECIFIC_H__
NXP_ and/or QORIQ_ prefix on include guards?
> +
> +#include <Ifc.h>
> +
> +// On board flash support
> +#define IFC_NAND_BUF_BASE 0x7E800000
> +
> +// On board Inegrated flash Controller chip select configuration
> +#define IFC_NOR_CS IFC_CS_MAX
> +#define IFC_NAND_CS IFC_CS0
> +#define IFC_FPGA_CS IFC_CS2
> +
> +// board-specific NAND timing
> +#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x7) | \
> + IFC_FTIM0_NAND_TWP(0x18) | \
> + IFC_FTIM0_NAND_TWCHT(0x7) | \
> + IFC_FTIM0_NAND_TWH(0xa))
> +
> +#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x32) | \
> + IFC_FTIM1_NAND_TWBE(0x39) | \
> + IFC_FTIM1_NAND_TRR(0xe) | \
> + IFC_FTIM1_NAND_TRP(0x18))
> +
> +#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0xf) | \
> + IFC_FTIM2_NAND_TREH(0xa) | \
> + IFC_FTIM2_NAND_TWHRE(0x1e))
> +
> +#define NAND_FTIM3 0x0
> +
> +#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BUF_BASE) \
> + | IFC_CSPR_PORT_SIZE_8 \
> + | IFC_CSPR_MSEL_NAND \
> + | IFC_CSPR_V)
> +
> +#define NAND_CSPR_EXT 0x0
> +#define NAND_AMASK 0xFFFF0000
> +
> +#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
> + | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
> + | IFC_CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
> + | IFC_CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
> + | IFC_CSOR_NAND_PGS_4K /* Page Size = 4K */ \
> + | IFC_CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
> + | IFC_CSOR_NAND_PB(6)) /* 2^6 Pages Per Block */
> +
> +// board-specific fpga timing
> +#define FPGA_BASE_PHYS 0x7fb00000
> +#define FPGA_CSPR_EXT 0x0
> +#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
> + IFC_CSPR_PORT_SIZE_8 | \
> + IFC_CSPR_MSEL_GPCM | \
> + IFC_CSPR_V)
> +
> +#define FPGA_AMASK IFC_AMASK(64 * 1024)
> +#define FPGA_CSOR IFC_CSOR_NOR_ADM_SHIFT(16)
> +
> +#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0x0e) | \
> + IFC_FTIM0_GPCM_TEADC(0x0e) | \
> + IFC_FTIM0_GPCM_TEAHC(0x0e))
> +#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \
> + IFC_FTIM1_GPCM_TRAD(0x3f))
> +#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \
> + IFC_FTIM2_GPCM_TCH(0xf) | \
> + IFC_FTIM2_GPCM_TWP(0x3E))
> +#define FPGA_FTIM3 0x0
> +
> +#endif //__IFC__BOARD_SPECIFIC_H__
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
> new file mode 100644
> index 0000000..0971935
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.c
> @@ -0,0 +1,61 @@
> +/** @file
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <IfcBoardSpecific.h>
> +
> +VOID
> +GetIfcNorFlashTimings (
> + IN IFC_TIMINGS * NorIfcTimings
> + )
> +{
> + NorIfcTimings->CS = IFC_NOR_CS;
> +
> + return ;
Drop space before ;
/
Leif
> +}
> +
> +VOID
> +GetIfcFpgaTimings (
> + IN IFC_TIMINGS *FpgaIfcTimings
> + )
> +{
> + FpgaIfcTimings->Ftim[0] = FPGA_FTIM0;
> + FpgaIfcTimings->Ftim[1] = FPGA_FTIM1;
> + FpgaIfcTimings->Ftim[2] = FPGA_FTIM2;
> + FpgaIfcTimings->Ftim[3] = FPGA_FTIM3;
> + FpgaIfcTimings->Cspr = FPGA_CSPR;
> + FpgaIfcTimings->CsprExt = FPGA_CSPR_EXT;
> + FpgaIfcTimings->Amask = FPGA_AMASK;
> + FpgaIfcTimings->Csor = FPGA_CSOR;
> + FpgaIfcTimings->CS = IFC_FPGA_CS;
> +
> + return;
> +}
> +
> +VOID
> +GetIfcNandFlashTimings (
> + IN IFC_TIMINGS * NandIfcTimings
> + )
> +{
> + NandIfcTimings->Ftim[0] = NAND_FTIM0;
> + NandIfcTimings->Ftim[1] = NAND_FTIM1;
> + NandIfcTimings->Ftim[2] = NAND_FTIM2;
> + NandIfcTimings->Ftim[3] = NAND_FTIM3;
> + NandIfcTimings->Cspr = NAND_CSPR;
> + NandIfcTimings->CsprExt = NAND_CSPR_EXT;
> + NandIfcTimings->Amask = NAND_AMASK;
> + NandIfcTimings->Csor = NAND_CSOR;
> + NandIfcTimings->CS = IFC_NAND_CS;
> +
> + return;
> +}
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
> new file mode 100644
> index 0000000..151c383
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
> @@ -0,0 +1,31 @@
> +# @file
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = BoardLib
> + FILE_GUID = 66041dab-97b4-4b45-b9b4-1209a2d55d7a
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = BoardLib
> +
> +[Sources.common]
> + BoardLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[FixedPcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 22/41] Platform/NXP: Add ArmPlatformLib for LS1046A
2018-11-28 15:01 ` [PATCH edk2-platforms 22/41] Platform/NXP: Add ArmPlatformLib for LS1046A Meenakshi Aggarwal
@ 2018-12-19 19:08 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-19 19:08 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Vabhav
On Wed, Nov 28, 2018 at 08:31:36PM +0530, Meenakshi Aggarwal wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Adding support of ArmPlatformLib for NXP LS1046ARDB board
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> .../Library/PlatformLib/ArmPlatformLib.c | 105 ++++++++++++++
> .../Library/PlatformLib/ArmPlatformLib.inf | 66 +++++++++
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 35 +++++
> .../Library/PlatformLib/NxpQoriqLsMem.c | 152 +++++++++++++++++++++
> 4 files changed, 358 insertions(+)
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> new file mode 100644
> index 0000000..c59a06a
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> @@ -0,0 +1,105 @@
> +/** ArmPlatformLib.c
> +*
> +* Contains board initialization functions.
> +*
> +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
> +*
> +* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +extern VOID SocInit (VOID);
Please import this through an include file.
> +
> +/**
> + Return the current Boot Mode
> +
> + This function returns the boot reason on the platform
> +
> +**/
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> + VOID
> + )
> +{
> + return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +/**
> + Placeholder for Platform Initialization
> +**/
> +EFI_STATUS
> +ArmPlatformInitialize (
> + IN UINTN MpId
> + )
> +{
> + SocInit ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +ARM_CORE_INFO LS1046aMpCoreInfoCTA72x4[] = {
STATIC?
m-prefix.
> + {
> + // Cluster 0, Core 0
> + 0x0, 0x0,
> +
> + // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (UINT64)0xFFFFFFFF
> + },
> +};
Move global variables before function definitions start:
https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/5_source_files/54_code_file_structure.html
> +
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> + OUT UINTN *CoreCount,
> + OUT ARM_CORE_INFO **ArmCoreTable
> + )
> +{
> + *CoreCount = sizeof (LS1046aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
> + *ArmCoreTable = LS1046aMpCoreInfoCTA72x4;
> +
> + return EFI_SUCCESS;
> +}
> +
> +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
STATIC?
Before function definitions.
> +
> +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
STATIC?
m-prefix?
Before function definitions?
/
Leif
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gArmMpCoreInfoPpiGuid,
> + &mMpCoreInfoPpi
> + }
> +};
> +
> +VOID
> +ArmPlatformGetPlatformPpiList (
> + OUT UINTN *PpiListSize,
> + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
> + )
> +{
> + *PpiListSize = sizeof (gPlatformPpiTable);
> + *PpiList = gPlatformPpiTable;
> +}
> +
> +
> +UINTN
> +ArmPlatformGetCorePosition (
> + IN UINTN MpId
> + )
> +{
> + return 1;
> +}
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> new file mode 100644
> index 0000000..49b57fc
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> @@ -0,0 +1,66 @@
> +# @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PlatformLib
> + FILE_GUID = 05a9029b-266f-421d-bb46-0e8385c64aa0
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ArmPlatformLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + ArmLib
> + SocLib
> +
> +[Sources.common]
> + NxpQoriqLsHelper.S | GCC
> + NxpQoriqLsMem.c
> + ArmPlatformLib.c
> +
> +[Ppis]
> + gArmMpCoreInfoPpiGuid
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdArmPrimaryCore
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> new file mode 100644
> index 0000000..6d54091
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> @@ -0,0 +1,35 @@
> +# @file
> +#
> +# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <AutoGen.h>
> +
> +.text
> +.align 2
> +
> +GCC_ASM_IMPORT(ArmReadMpidr)
> +
> +ASM_FUNC(ArmPlatformIsPrimaryCore)
> + tst x0, #3
> + cset x0, eq
> + ret
> +
> +ASM_FUNC(ArmPlatformPeiBootAction)
> + ret
> +
> +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
> + MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
> + ldrh w0, [x0]
> + ret
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> new file mode 100644
> index 0000000..64c5612
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> @@ -0,0 +1,152 @@
> +/** NxpQoriqLsMem.c
> +*
> +* Board memory specific Library.
> +*
> +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
> +*
> +* Copyright (c) 2011, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
> +
> +/**
> + Return the Virtual Memory Map of your platform
> +
> + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
> +
> + @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
> + Virtual Memory mapping. This array must be ended by a zero-filled
> + entry
> +
> +**/
> +
> +VOID
> +ArmPlatformGetVirtualMemoryMap (
> + IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
> + )
> +{
> + UINTN Index;
> + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> +
> + Index = 0;
> +
> + ASSERT (VirtualMemoryMap != NULL);
> +
> + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
> + EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
> +
> + if (VirtualMemoryTable == NULL) {
> + return;
> + }
> +
> + // DRAM1 (Must be 1st entry)
> + VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // CCSR Space
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // IFC region 1
> + //
> + // A-009241 : Unaligned write transactions to IFC may result in corruption of data
> + // Affects : IFC
> + // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
> + // writes on external IFC interface that can corrupt data on external flash.
> + // Impact : Data corruption on external flash may happen in case of unaligned writes to
> + // IFC memory space.
> + // Workaround: Following are the workarounds:
> + // For write transactions from core, IFC interface memories (including IFC SRAM)
> + // should be configured as device type memory in MMU.
> + // For write transactions from non-core masters (like system DMA), the address
> + // should be 16 byte aligned and the data size should be multiple of 16 bytes.
> + //
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // QMAN SWP
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // BMAN SWP
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // IFC region 2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DRAM2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram2Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // PCIe1
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe3
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DRAM3
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram3BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram3BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram3Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // QSPI region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // End of Table
> + VirtualMemoryTable[++Index].PhysicalBase = 0;
> + VirtualMemoryTable[Index].VirtualBase = 0;
> + VirtualMemoryTable[Index].Length = 0;
> + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
> +
> + ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> + *VirtualMemoryMap = VirtualMemoryTable;
> +}
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 23/41] Platform/NXP: Add Platform driver for LS1046 RDB board
2018-11-28 15:01 ` [PATCH edk2-platforms 23/41] Platform/NXP: Add Platform driver for LS1046 RDB board Meenakshi Aggarwal
@ 2018-12-19 22:05 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-19 22:05 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
Add a commit message please.
Like - what is going on with the handling of multiple I2c masters?
On Wed, Nov 28, 2018 at 08:31:37PM +0530, Meenakshi Aggarwal wrote:
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> .../Drivers/PlatformDxe/PlatformDxe.c | 119 +++++++++++++++++++++
> .../Drivers/PlatformDxe/PlatformDxe.inf | 58 ++++++++++
> 2 files changed, 177 insertions(+)
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> create mode 100644 Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
>
> diff --git a/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> new file mode 100644
> index 0000000..b74818e
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> @@ -0,0 +1,119 @@
> +/** @file
> + LS1046 RDB board DXE platform driver.
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +**/
> +
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +
> +#include <Protocol/NonDiscoverableDevice.h>
> +
> +typedef struct {
> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR StartDesc;
> + UINT8 EndDesc;
> +} ADDRESS_SPACE_DESCRIPTOR;
> +
> +STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
> +
> +STATIC
> +EFI_STATUS
> +RegisterDevice (
> + IN EFI_GUID *TypeGuid,
> + IN ADDRESS_SPACE_DESCRIPTOR *Desc,
> + OUT EFI_HANDLE *Handle
> + )
> +{
> + NON_DISCOVERABLE_DEVICE *Device;
> + EFI_STATUS Status;
> +
> + Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device));
> + if (Device == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + Device->Type = TypeGuid;
> + Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent;
> + Device->Resources = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Desc;
> +
> + Status = gBS->InstallMultipleProtocolInterfaces (Handle,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid, Device,
> + NULL);
> + if (EFI_ERROR (Status)) {
> + goto FreeDevice;
> + }
> + return EFI_SUCCESS;
> +
> +FreeDevice:
> + FreePool (Device);
> +
> + return Status;
> +}
> +
> +VOID
> +PopulateI2cInformation (
> + IN VOID
> + )
> +{
> + UINT32 Index;
> +
> + for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
> + mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
> + mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
> + mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
> + mI2cDesc[Index].StartDesc.GenFlag = 0;
> + mI2cDesc[Index].StartDesc.SpecificFlag = 0;
> + mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
> + mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
> + (Index * FixedPcdGet32 (PcdI2cSize));
> + mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
> + FixedPcdGet32 (PcdI2cSize) - 1;
> + mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
> + mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
> +
> + mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
This confuses me. Does this not add an end descriptor for every entry
- ensuring that only one controller would ever be properly registered?
> + }
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +PlatformDxeEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE Handle;
> +
> + Handle = NULL;
> +
> + PopulateI2cInformation ();
> +
> + Status = RegisterDevice (&gNxpNonDiscoverableI2cMasterGuid,
> + &mI2cDesc[3], &Handle);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Install the DS1307 I2C Master protocol on this handle so the RTC driver
> + // can identify it as the I2C master it can invoke directly.
> + //
> + Status = gBS->InstallProtocolInterface (&Handle,
> + &gPcf2129RealTimeClockLibI2cMasterProtocolGuid,
> + EFI_NATIVE_INTERFACE, NULL);
> + ASSERT_EFI_ERROR (Status);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> new file mode 100644
> index 0000000..2556af2
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> @@ -0,0 +1,58 @@
> +## @file
> +#
> +# Component description file for LS1046 DXE platform driver.
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PlatformDxe
> + FILE_GUID = 5bf02256-a7d2-4bfd-9934-2055358c6a6c
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PlatformDxeEntryPoint
> +
> +[Sources]
> + PlatformDxe.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + DebugLib
> + MemoryAllocationLib
> + PcdLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> + UefiLib
> +
> +[Guids]
> + gNxpNonDiscoverableI2cMasterGuid
> +
> +[Protocols]
> + gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
> + gPcf2129RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES
Align the ## PRODUCES comments please.
/
Leif
> +
> +[FixedPcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
> +
> +[Depex]
> + TRUE
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 24/41] Platform/NXP: Compilation for LS1046A RDB Board
2018-11-28 15:01 ` [PATCH edk2-platforms 24/41] Platform/NXP: Compilation for LS1046A RDB Board Meenakshi Aggarwal
@ 2018-12-20 17:39 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-20 17:39 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Vabhav
On Wed, Nov 28, 2018 at 08:31:38PM +0530, Meenakshi Aggarwal wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Adding firmware device,description and declaration files to enable
> compilation for NXP LS1046ARDB board.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec | 29 ++++
Now, I've not kept track, but if this directory was created
previously, the .dec should really have been added when files were
added to the Include directory.
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 90 ++++++++++++
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 198 +++++++++++++++++++++++++++
> 3 files changed, 317 insertions(+)
> create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
> create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
>
> diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
> new file mode 100644
> index 0000000..a872ade
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec
> @@ -0,0 +1,29 @@
> +# LS1046aRdbPkg.dec
> +# LS1046a board package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + PACKAGE_NAME = LS1046aRdbPkg
> + PACKAGE_GUID = c0c8d5e4-f63b-4470-89bc-73c13c13b247
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +# Supported Module Types:
> +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
> diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> new file mode 100644
> index 0000000..7eb08a9
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> @@ -0,0 +1,90 @@
> +# LS1046aRdbPkg.dsc
> +#
> +# LS1046ARDB Board package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + #
> + # Defines for default states. These can be changed on the command line.
> + # -D FLAG=VALUE
> + #
> + PLATFORM_NAME = LS1046aRdbPkg
> + PLATFORM_GUID = 43920156-3f3b-4199-9b29-c6db1fb792b0
> + OUTPUT_DIRECTORY = Build/LS1046aRdbPkg
> + FLASH_DEFINITION = Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> +
> +!include Platform/NXP/NxpQoriqLs.dsc.inc
> +!include Silicon/NXP/LS1046A/LS1046A.dsc.inc
> +
> +[LibraryClasses.common]
> + SocLib|Silicon/NXP/Library/SocLib/LS1046aSocLib.inf
> + ArmPlatformLib|Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> + IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> + RealTimeClockLib|Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf
> + IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
> + BoardLib|Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
> + FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf
> +
> +[PcdsFixedAtBuild.common]
> +
> + #
> + # LS1046a board Specific PCDs
> + # XX (DRAM - Region 1 2GB)
> + # (NOR - IFC Region 1 512MB)
> + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
> + gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
> + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
> +
> + #
> + # Board Specific Pcds
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x2
> +
> + #
> + # Big Endian IPs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
> +
> + #
> + # RTC Pcds
> + #
> + gPcf2129RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
> + gPcf2129RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> + #
> + # Architectural Protocols
> + #
> + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> +
> + Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> + Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> +
> + Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> + ##
> diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> new file mode 100644
> index 0000000..443b561
> --- /dev/null
> +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> @@ -0,0 +1,198 @@
> +# LS1046aRdbPkg.fdf
> +#
> +# FLASH layout file for LS1046a board.
> +#
> +# Copyright (c) 2016, Freescale Ltd. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into the Flash Device Image. Each FD section
> +# defines one flash "device" image. A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash" image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +################################################################################
> +
> +[FD.LS1046ARDB_EFI]
> +BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
> +Size = 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
> +ErasePolarity = 1
> +BlockSize = 0x1
> +NumBlocks = 0xED000
> +
> +################################################################################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +#
> +################################################################################
> +0x00000000|0x000ED000
> +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> +FV = FVMAIN_COMPACT
> +
> +!include Platform/NXP/FVRules.fdf.inc
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed within a flash
> +# device file. This section also defines order the components and modules are positioned
> +# within the image. The [FV] section consists of define statements, set statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
> +BlockSize = 0x1
> +NumBlocks = 0 # This FV gets compressed so make it just big enough
> +FvAlignment = 8 # FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF MdeModulePkg/Core/Dxe/DxeMain.inf
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +
> + #
> + # PI DXE Drivers producing Architectural Protocols (EFI Services)
> + #
> + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> +
> + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + INF Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> + INF Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> +
> + INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> +
> + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> +
> + #
> + # Multiple Console IO support
> + #
> + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
> +
> + #
> + # Network modules
> + #
Same thing as before with regards to NetworkPkg replacements for some
of the below.
/
Leif
> + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
> +!if $(NETWORK_IP6_ENABLE) == TRUE
> + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + INF NetworkPkg/TcpDxe/TcpDxe.inf
> + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> +!else
> + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> +!endif
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + INF FatPkg/FatPei/FatPei.inf
> + INF FatPkg/EnhancedFatDxe/Fat.inf
> +
> + #
> + # UEFI application (Shell Embedded Boot Loader)
> + #
> + INF ShellPkg/Application/Shell/Shell.inf
> +
> + #
> + # Bds
> + #
> + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + INF MdeModulePkg/Application/UiApp/UiApp.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment = 8
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF ArmPlatformPkg/PrePi/PeiUniCore.inf
> +
> + FILE FV_IMAGE = c1c1e1a2-3879-4b5e-9dd1-3df2ce60d8ec {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> + }
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 25/41] Silicon/NXP:SocLib support for initialization of peripherals
2018-11-28 15:01 ` [PATCH edk2-platforms 25/41] Silicon/NXP:SocLib support for initialization of peripherals Meenakshi Aggarwal
@ 2018-12-21 9:22 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 9:22 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Wasim Khan
On Wed, Nov 28, 2018 at 08:31:39PM +0530, Meenakshi Aggarwal wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
>
> Added SocInit function that initializes peripherals
> and print board and soc information for LS2088ARDB Board.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/Chassis3/SerDes.h | 91 ++++++++++++++
> Silicon/NXP/Include/Chassis3/Soc.h | 144 +++++++++++++++++++++
> Silicon/NXP/LS2088A/Include/SocSerDes.h | 67 ++++++++++
> Silicon/NXP/Library/SocLib/Chassis.c | 38 ++++++
> Silicon/NXP/Library/SocLib/Chassis.h | 17 +++
> Silicon/NXP/Library/SocLib/Chassis3/Soc.c | 180 +++++++++++++++++++++++++++
> Silicon/NXP/Library/SocLib/LS2088aSocLib.inf | 50 ++++++++
> Silicon/NXP/Library/SocLib/SerDes.c | 3 +
> 8 files changed, 590 insertions(+)
> create mode 100644 Silicon/NXP/Include/Chassis3/SerDes.h
> create mode 100644 Silicon/NXP/Include/Chassis3/Soc.h
> create mode 100644 Silicon/NXP/LS2088A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/Library/SocLib/Chassis3/Soc.c
> create mode 100644 Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
>
> diff --git a/Silicon/NXP/Include/Chassis3/SerDes.h b/Silicon/NXP/Include/Chassis3/SerDes.h
> new file mode 100644
> index 0000000..a77ddd5
> --- /dev/null
> +++ b/Silicon/NXP/Include/Chassis3/SerDes.h
> @@ -0,0 +1,91 @@
> +/** SerDes.h
> + The Header file of SerDes Module for Chassis 3
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __SERDES_H__
> +#define __SERDES_H__
NXP_ prefix?
> +
> +#include <Uefi/UefiBaseType.h>
> +
> +#define SRDS_MAX_LANES 8
> +
> +//
> +// SerDes lane protocols/devices
> +//
> +typedef enum {
> + NONE = 0,
> + PCIE1,
> + PCIE2,
> + PCIE3,
> + PCIE4,
> + SATA1,
> + SATA2,
> + XAUI1,
> + XAUI2,
> + XFI1,
> + XFI2,
> + XFI3,
> + XFI4,
> + XFI5,
> + XFI6,
> + XFI7,
> + XFI8,
> + SGMII1,
> + SGMII2,
> + SGMII3,
> + SGMII4,
> + SGMII5,
> + SGMII6,
> + SGMII7,
> + SGMII8,
> + SGMII9,
> + SGMII10,
> + SGMII11,
> + SGMII12,
> + SGMII13,
> + SGMII14,
> + SGMII15,
> + SGMII16,
> + QSGMII_A,
> + QSGMII_B,
> + QSGMII_C,
> + QSGMII_D,
> + // Number of entries in this enum
> + SERDES_PRTCL_COUNT
CamelCase for enum member names - throughout.
> +} SERDES_PROTOCOL;
> +
> +typedef enum {
> + SRDS_1 = 0,
> + SRDS_2,
> + SRDS_MAX_NUM
> +} SERDES_NUMBER;
> +
> +typedef struct {
> + UINT16 Protocol;
> + UINT8 SrdsLane[SRDS_MAX_LANES];
> +} SERDES_CONFIG;
> +
> +typedef VOID
> +(*SERDES_PROBE_LANES_CALLBACK) (
> + IN SERDES_PROTOCOL LaneProtocol,
> + IN VOID *Arg
> + );
> +
> +VOID
> +SerDesProbeLanes(
> + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> + IN VOID *Arg
> + );
> +
> +#endif /* __SERDES_H */
> diff --git a/Silicon/NXP/Include/Chassis3/Soc.h b/Silicon/NXP/Include/Chassis3/Soc.h
> new file mode 100644
> index 0000000..8d967e7
> --- /dev/null
> +++ b/Silicon/NXP/Include/Chassis3/Soc.h
> @@ -0,0 +1,144 @@
> +/** Soc.h
> +* Header defining the Base addresses, sizes, flags etc for chassis 1
> +*
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __SOC_H__
> +#define __SOC_H__
NXP_ prefix?
> +
> +#define FSL_CLK_GRPA_ADDR 0x01300000
> +#define FSL_CLK_GRPB_ADDR 0x01310000
> +
> +#define FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } /* LS208x */
> +#define TP_CLUSTER_EOC_MASK 0x80000000 /* Mask for End of clusters */
> +#define NUM_CC_PLLS 6
> +#define CLK_FREQ 100000000
> +#define MAX_CPUS 16
> +#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) != TP_CLUSTER_EOC_MASK)
> +
> +/* RCW SERDES MACRO */
> +#define RCWSR_INDEX 28
> +#define RCWSR_SRDS1_PRTCL_MASK 0x00ff0000
> +#define RCWSR_SRDS1_PRTCL_SHIFT 16
> +#define RCWSR_SRDS2_PRTCL_MASK 0xff000000
> +#define RCWSR_SRDS2_PRTCL_SHIFT 24
> +
> +/* SMMU Defintions */
> +#define SMMU_BASE_ADDR 0x05000000
> +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> +
> +#define SCR0_USFCFG_MASK 0x00000400
> +#define SCR0_CLIENTPD_MASK 0x00000001
> +#define SACR_PAGESIZE_MASK 0x00010000
> +
> +typedef struct {
> + UINTN FreqProcessor[MAX_CPUS];
> + UINTN FreqSystemBus;
> + UINTN FreqDdrBus;
> + UINTN FreqDdrBus2;
> + UINTN FreqLocalBus;
> + UINTN FreqSdhc;
> + UINTN FreqFman[1];
Fman?
Why [1]=?
> + UINTN FreqQman;
Qman?
> + UINTN FreqPme;
Pme?
> +} SYS_INFO;
> +
> +/* Device Configuration and Pin Control */
> +typedef struct {
> + UINT32 PorSr1; /* POR status 1 */
> + UINT32 PorSr2; /* POR status 2 */
> + UINT8 Res008[0x18];
Why is the first reserved field of the struct called #8?
Oh, 8 bytes in?
I would much rather see the offset written in a comment next to it.
Please use decimal size for array.
Also, please write out Reserved.
Both comments apply throughout.
> + UINT32 GppOrCr1; /* General-purpose POR configuration */
> + UINT32 GppOrCr2; /* General-purpose POR configuration 2 */
> + UINT32 DcfgFuseSr; /* Fuse status register */
Comment indentation.
> + UINT32 GppOrCr3;
> + UINT32 GppOrCr4;
> + UINT8 Res034[0x3C];
> + UINT32 DevDisr; /* Device disable control */
> + UINT32 DevDisr2; /* Device disable control 2 */
> + UINT32 DevDisr3; /* Device disable control 3 */
> + UINT32 DevDisr4; /* Device disable control 4 */
> + UINT32 DevDisr5; /* Device disable control 5 */
> + UINT32 DevDisr6; /* Device disable control 6 */
> + UINT32 DevDisr7; /* Device disable control 7 */
> + UINT8 Res08c[0x4];
> + UINT32 CoreDisrUpper; /* uppper portion for support of 64 cores */
> + UINT32 CoreDisrLower; /* lower portion for support of 64 cores */
> + UINT8 Res098[0x8];
> + UINT32 Pvr; /* Processor version */
> + UINT32 Svr; /* System version */
> + UINT32 Mvr; /* Manufacturing version */
> + UINT8 Res0ac[0x54];
> + UINT32 RcwSr[32]; /* Reset control word status */
> +#define CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT 2
> +#define CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK 0x1f
> +#define CHASSIS3_RCWSR_0_MEM_PLL_RAT_SHIFT 10
> +#define CHASSIS3_RCWSR_0_MEM_PLL_RAT_MASK 0x3f
> +#define CHASSIS3_RCWSR_0_MEM2_PLL_RAT_SHIFT 18
> +#define CHASSIS3_RCWSR_0_MEM2_PLL_RAT_MASK 0x3f
> + UINT8 Res180[0x80];
> + UINT32 ScratchRw[32]; /* Scratch Read/Write */
> + UINT8 Res280[0x80];
> + UINT32 ScratchW1R[4]; /* Scratch Read (Write once) */
> + UINT8 Res310[0xF0];
> + UINT32 BootLocPtrL; /* Low addr : Boot location pointer */
> + UINT32 BootLocPtrH; /* High addr : Boot location pointer */
> + UINT8 Res408[0xF8];
> + UINT8 Res500[0x240];
> + UINT32 TpItyp[64];
> + struct {
> + UINT32 Upper;
> + UINT32 Lower;
> + } TpCluster[3];
> + UINT8 Res858[0x7A8];
> +} CCSR_GUR;
> +
> +/* Clocking */
> +typedef struct {
> + struct {
> + UINT32 Csr; /* core cluster n clock control status */
> + UINT8 Res04[0x1C];
> + } ClkCnCsr[8];
> +} CCSR_CLT_CTRL;
> +
> +/* Clock Cluster */
> +typedef struct {
> + struct {
> + UINT8 Res00[0x10];
> + UINT32 Csr; /* core cluster n clock control status */
> + UINT8 Res14[0xC];
> + } HwnCsr[3];
> + UINT8 Res60[0x20];
> + struct {
> + UINT32 Gsr; /* core cluster n clock general status */
> + UINT8 Res84[0x1C];
> + } PllnGsr[3];
> + UINT8 Rese0[0x20];
> +} CCSR_CLK_CLUSTER;
> +
> +VOID
> +GetSysInfo (
> + OUT SYS_INFO *
> + );
> +
> +UINT32
> +EFIAPI
> +GurRead (
> + IN UINTN Address
> + );
> +
> +#endif /* __SOC_H__ */
> diff --git a/Silicon/NXP/LS2088A/Include/SocSerDes.h b/Silicon/NXP/LS2088A/Include/SocSerDes.h
> new file mode 100644
> index 0000000..9135423
> --- /dev/null
> +++ b/Silicon/NXP/LS2088A/Include/SocSerDes.h
> @@ -0,0 +1,67 @@
> +/** @file
> + The Header file of SerDes Module for LS2088A
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __SOC_SERDES_H__
> +#define __SOC_SERDES_H__
> +
> +#include <Chassis3/SerDes.h>
> +
> +SERDES_CONFIG SerDes1ConfigTbl[] = {
Needs to be in a .c file.
Also, STATIC and m-prefix.
> + // SerDes 1
> + { 0x03, { PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
> + { 0x05, { PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
> + { 0x07, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
> + { 0x09, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
> + { 0x0A, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
> + { 0x0C, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
> + { 0x0E, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } },
> + { 0x26, { SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
> + { 0x28, { SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
> + { 0x2A, { XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
> + { 0x2B, { SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
> + { 0x32, { XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
> + { 0x33, { PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B, QSGMII_A } },
> + { 0x35, { QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
> + {}
> +};
> +
> +SERDES_CONFIG SerDes2ConfigTbl[] = {
Same as above.
> + // SerDes 2
> + { 0x07, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
> + { 0x09, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
> + { 0x0A, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
> + { 0x0C, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
> + { 0x0E, { SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15, SGMII16 } },
> + { 0x3D, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
> + { 0x3E, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
> + { 0x3F, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
> + { 0x40, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
> + { 0x41, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
> + { 0x42, { PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
> + { 0x43, { PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
> + { 0x44, { PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
> + { 0x45, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, PCIE4 } },
> + { 0x47, { PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, SGMII16 } },
> + { 0x49, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } },
> + { 0x4A, { SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } },
> + {}
> +};
> +
> +SERDES_CONFIG *SerDesConfigTbl[] = {
Same as above, but g-prefix.
Probably want Nxp/Qoriq prefix too.
> + SerDes1ConfigTbl,
> + SerDes2ConfigTbl
> +};
> +
> +#endif /* __SOC_SERDES_H */
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> index e8e69a6..58f1ba7 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> @@ -16,6 +16,8 @@
> #include <Base.h>
> #ifdef CHASSIS2
> #include <Chassis2/Soc.h>
> +#elif CHASSIS3
> +#include <Chassis3/Soc.h>
> #endif
> #include <Library/BaseLib.h>
> #include <Library/IoAccessLib.h>
> @@ -46,6 +48,7 @@ GurRead (
> STATIC CPU_TYPE CpuTypeList[] = {
> CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
> CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
> + CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
> };
>
> /*
> @@ -133,6 +136,41 @@ CpuNumCores (
> }
>
> /*
> + * Return core's cluster
Need a more detailed description - what format is "Core"?
> + */
> +INT32
> +QoriqCoreToCluster (
> + IN UINTN Core
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINTN ClusterIndex;
> + UINTN Count;
> + UINT32 Cluster;
> + UINT32 Type;
> + UINTN InitiatorIndex;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClusterIndex = 0;
> + Count = 0;
> + do {
> + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> + Type = InitiatorType (Cluster, InitiatorIndex);
> + if (Type) {
> + if (Count == Core) {
> + return ClusterIndex;
> + }
> + Count++;
> + }
> + }
> + ClusterIndex++;
> + } while (CHECK_CLUSTER (Cluster));
> +
> + return -1; // cannot identify the cluster
Please use a #define.
> +}
> +
> +/*
> * Return the type of core i.e. A53, A57 etc of inputted
> * core number.
> */
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.h b/Silicon/NXP/Library/SocLib/Chassis.h
> index 5b7e5c4..3ac18bf 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis.h
> +++ b/Silicon/NXP/Library/SocLib/Chassis.h
> @@ -57,6 +57,7 @@ CpuMaskNext (
> #define SVR_WO_E 0xFFFFFE
> #define SVR_LS1043A 0x879200
> #define SVR_LS1046A 0x870700
> +#define SVR_LS2088A 0x870901
>
> #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> #define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> @@ -142,4 +143,20 @@ CpuNumCores (
> VOID
> );
>
> +/*
> + * Return the type of initiator for core/hardware accelerator for given core index.
> + */
> +UINTN
> +QoriqCoreToType (
> + IN UINTN Core
> + );
A function of this name was added in 3/41 - please move the
declaration to the same patch.
> +
> +/*
> + * Return the cluster of initiator for core/hardware accelerator for given core index.
> + */
> +INT32
> +QoriqCoreToCluster (
> + IN UINTN Core
> + );
> +
> #endif /* __CHASSIS_H__ */
> diff --git a/Silicon/NXP/Library/SocLib/Chassis3/Soc.c b/Silicon/NXP/Library/SocLib/Chassis3/Soc.c
> new file mode 100644
> index 0000000..0fc92f4
> --- /dev/null
> +++ b/Silicon/NXP/Library/SocLib/Chassis3/Soc.c
> @@ -0,0 +1,180 @@
> +/** @Soc.c
> + SoC specific Library containg functions to initialize various SoC components
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Chassis.h>
> +#include <Chassis3/Soc.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +VOID
> +GetSysInfo (
> + OUT SYS_INFO *PtrSysInfo
> + )
> +{
> + UINT32 Index;
> + CCSR_GUR *GurBase;
> + CCSR_CLT_CTRL *ClkBase;
> + CCSR_CLK_CLUSTER *ClkGrp[2] = {
That 2 looks superfluous.
> + (VOID *) (FSL_CLK_GRPA_ADDR),
> + (VOID *) (FSL_CLK_GRPB_ADDR)
> + };
> +
> + CONST UINT8 CoreCplxPll[16] = {
> + [0] = 0, // CC1 PPL / 1
> + [1] = 0, // CC1 PPL / 2
> + [2] = 0, // CC1 PPL / 4
> + [4] = 1, // CC2 PPL / 1
> + [5] = 1, // CC2 PPL / 2
> + [6] = 1, // CC2 PPL / 4
> + [8] = 2, // CC3 PPL / 1
> + [9] = 2, // CC3 PPL / 2
> + [10] = 2, // CC3 PPL / 4
> + [12] = 3, // CC4 PPL / 1
> + [13] = 3, // CC4 PPL / 2
> + [14] = 3, // CC4 PPL / 4
> + };
> +
> + CONST UINT8 CoreCplxPllDivisor[16] = {
> + [0] = 1, // CC1 PPL / 1
> + [1] = 2, // CC1 PPL / 2
> + [2] = 4, // CC1 PPL / 4
> + [4] = 1, // CC2 PPL / 1
> + [5] = 2, // CC2 PPL / 2
> + [6] = 4, // CC2 PPL / 4
> + [8] = 1, // CC3 PPL / 1
> + [9] = 2, // CC3 PPL / 2
> + [10] = 4, // CC3 PPL / 4
> + [12] = 1, // CC4 PPL / 1
> + [13] = 2, // CC4 PPL / 2
> + [14] = 4, // CC4 PPL / 4
> + };
> +
> + INT32 CcGroup[12] = FSL_CLUSTER_CLOCKS;
Why is this one initialised via a macro, but the others inline?
Also, why is this one not CONST, given the others, and the constant
initialiser?
Please move all of these preinitialised structures out of this
function and give them the STATIC attribute and an m-prefix.
And regardless of initialiser, that 12 looks like an accident waiting
to happen. Why is it 12? The initialiser has 4 elements. Can the 12
be dropped?
> + UINTN PllCount;
> + UINTN Cluster;
> + UINTN FreqCPll[NUM_CC_PLLS];
> + UINTN PllRatio[NUM_CC_PLLS];
> + UINTN SysClk;
> + UINT32 Cpu;
> + UINT32 CPllSel;
> + UINT32 CplxPll;
> + VOID *Offset;
> +
> + SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
> + SysClk = CLK_FREQ;
> +
> + PtrSysInfo->FreqSystemBus = SysClk;
> + PtrSysInfo->FreqDdrBus = PcdGet64 (PcdDdrClk);
> + PtrSysInfo->FreqDdrBus2 = PcdGet64 (PcdDdrClk);
> +
> + //
> + // selects the platform clock:SYSCLK ratio and calculate
> + // system frequency
> + //
> + PtrSysInfo->FreqSystemBus *=
> + (GurRead ((UINTN)&GurBase->RcwSr[0]) >> CHASSIS3_RCWSR_0_SYS_PLL_RAT_SHIFT) &
> + CHASSIS3_RCWSR_0_SYS_PLL_RAT_MASK;
This pattern, repeated thrice, seems ripe for a macro of some sort:
#define xxx(a, pll) (((a) >> CHASSIS3_RCWSR_0_ ## pll ## _PLL_RAT_SHIFT) & \
CHASSIS3_RCWSR_0_ ## pll ## _PLL_RAT_MASK)
?
Called as
xxx (GurRead ((UINTN)&GurBase->RcwSr[0]), SYS);
> +
> + //
> + // Platform clock is half of platform PLL
> + //
> + PtrSysInfo->FreqSystemBus /= PcdGet32 (PcdPlatformFreqDiv);
> +
> + //
> + // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
> + //
> + PtrSysInfo->FreqDdrBus *=
> + (GurRead ((UINTN)&GurBase->RcwSr[0]) >> CHASSIS3_RCWSR_0_MEM_PLL_RAT_SHIFT) &
> + CHASSIS3_RCWSR_0_MEM_PLL_RAT_MASK;
> +
> + PtrSysInfo->FreqDdrBus2 *=
> + (GurRead ((UINTN)&GurBase->RcwSr[0]) >> CHASSIS3_RCWSR_0_MEM2_PLL_RAT_SHIFT) &
> + CHASSIS3_RCWSR_0_MEM2_PLL_RAT_MASK;
> +
> + for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
> + Offset = (VOID *)((UINTN)ClkGrp[PllCount/3] +
Why /3? Can it be replaced by a #define?
> + __builtin_offsetof (CCSR_CLK_CLUSTER, PllnGsr[PllCount%3].Gsr));
Indent to be aligned with statement it is a continuation of.
> + PllRatio[PllCount] = (GurRead ((UINTN)Offset) >> 1) & 0x3f;
#define for that 0x3f please. And preferably for the 1 as well.
> + FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
> + }
> +
> + //
> + // Calculate Core frequency
> + //
> + ForEachCpu (Index, Cpu, CpuNumCores (), CpuMask ()) {
> + Cluster = QoriqCoreToCluster (Cpu);
> + ASSERT_EFI_ERROR (Cluster);
> + CPllSel = (GurRead ((UINTN)&ClkBase->ClkCnCsr[Cluster].Csr) >> 27) & 0xf;
#defines for 27 and 0xf?
> + CplxPll = CoreCplxPll[CPllSel];
> + CplxPll += CcGroup[Cluster] - 1;
Why -1? #define?
> + PtrSysInfo->FreqProcessor[Cpu] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
> + }
> + PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
> +}
> +
> +/**
> + Perform the early initialization.
> + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
> +
> +**/
> +VOID
> +SocInit (
> + VOID
> + )
> +{
> + CHAR8 Buffer[100];
> + UINTN CharCount;
> +
> + //
> + // Initialize SMMU
> + //
> + SmmuInit ();
> +
> + //
> + // Initialize the Serial Port.
> + // Early serial port initialization is required to print RCW,
> + // Soc and CPU infomation at the begining of UEFI boot.
> + //
> + SerialPortInitialize ();
> +
> + CharCount = AsciiSPrint (Buffer, sizeof (Buffer),
> + "\nUEFI firmware (version %s built at %a on %a)\n\r",
> + (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__);
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> +
> + //
> + // Print CPU information
> + //
Function name sufficient, comment not needed.
> + PrintCpuInfo ();
> +
> + //
> + // Print Reset Controll Word
> + //
> + PrintRCW ();
PrintResetControlWord ();
Then the comment can be deleted.
> +
> + //
> + // Print Soc Personality information
> + //
> + PrintSoc ();
PrintSocPersonalityInfo ();
Then the comment can be deleted.
/
Leif
> +}
> diff --git a/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf b/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
> new file mode 100644
> index 0000000..3d9237d
> --- /dev/null
> +++ b/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
> @@ -0,0 +1,50 @@
> +# @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = SocLib
> + FILE_GUID = 3b233a6a-0ee1-42a3-a7f7-c285b5ba80dc
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SocLib
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/LS2088A/LS2088A.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + IoAccessLib
> + SerialPortLib
> +
> +[Sources.common]
> + Chassis.c
> + Chassis3/Soc.c
> + SerDes.c
> +
> +[BuildOptions]
> + GCC:*_*_*_CC_FLAGS = -DCHASSIS3
> +
> +[FixedPcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDdrClk
> diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocLib/SerDes.c
> index e31e4f3..9eba8ae 100644
> --- a/Silicon/NXP/Library/SocLib/SerDes.c
> +++ b/Silicon/NXP/Library/SocLib/SerDes.c
> @@ -16,6 +16,9 @@
> #ifdef CHASSIS2
> #include <Chassis2/SerDes.h>
> #include <Chassis2/Soc.h>
> +#elif CHASSIS3
> +#include <Chassis3/SerDes.h>
> +#include <Chassis3/Soc.h>
> #endif
> #include <Library/DebugLib.h>
> #include <SocSerDes.h>
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 26/41] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB
2018-11-28 15:01 ` [PATCH edk2-platforms 26/41] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB Meenakshi Aggarwal
@ 2018-12-21 9:30 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 9:30 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Wasim Khan
On Wed, Nov 28, 2018 at 08:31:40PM +0530, Meenakshi Aggarwal wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
>
> Add support of ArmPlatformLib for NXP LS2088ARDB board
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> .../Library/PlatformLib/ArmPlatformLib.c | 106 ++++++++++++
> .../Library/PlatformLib/ArmPlatformLib.inf | 77 +++++++++
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 35 ++++
> .../Library/PlatformLib/NxpQoriqLsMem.c | 189 +++++++++++++++++++++
> 4 files changed, 407 insertions(+)
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> new file mode 100644
> index 0000000..90f14ba
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> @@ -0,0 +1,106 @@
> +/** ArmPlatformLib.c
> +*
> +* Contains board initialization functions.
> +*
> +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
> +*
> +* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +extern VOID SocInit (VOID);
Pull in declaration from some header file.
> +
> +/**
> + Return the current Boot Mode
> +
> + This function returns the boot reason on the platform
> +
> +**/
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> + VOID
> + )
> +{
> + return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +/**
> + Placeholder for Platform Initialization
> +
> +**/
> +EFI_STATUS
> +ArmPlatformInitialize (
> + IN UINTN MpId
> + )
> +{
> + SocInit ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +ARM_CORE_INFO LS2088aMpCoreInfoCTA72x4[] = {
STATIC.
m-prefix.
Move before all function definitions.
> + {
> + // Cluster 0, Core 0
> + 0x0, 0x0,
> +
> + // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (UINT64)0xFFFFFFFF
> + },
> +};
> +
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> + OUT UINTN *CoreCount,
> + OUT ARM_CORE_INFO **ArmCoreTable
> + )
> +{
> + *CoreCount = sizeof (LS2088aMpCoreInfoCTA72x4) / sizeof (ARM_CORE_INFO);
> + *ArmCoreTable = LS2088aMpCoreInfoCTA72x4;
> +
> + return EFI_SUCCESS;
> +}
> +
> +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
STATIC.
Move before all function definitions.
> +
> +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
STATIC.
m-prefix sufficient.
Move before all function definitions.
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gArmMpCoreInfoPpiGuid,
> + &mMpCoreInfoPpi
> + }
> +};
> +
> +VOID
> +ArmPlatformGetPlatformPpiList (
> + OUT UINTN *PpiListSize,
> + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
> + )
> +{
> + *PpiListSize = sizeof (gPlatformPpiTable);
> + *PpiList = gPlatformPpiTable;
> +}
> +
> +
> +UINTN
> +ArmPlatformGetCorePosition (
> + IN UINTN MpId
> + )
> +{
> + return 1;
> +}
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> new file mode 100644
> index 0000000..f5e5abd
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> @@ -0,0 +1,77 @@
> +#/** @file
> +#
> +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PlatformLib
> + FILE_GUID = d1361285-8a47-421c-9efd-6b262c9093fc
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ArmPlatformLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + ArmLib
> + SocLib
> +
> +[Sources.common]
> + ArmPlatformLib.c
> + NxpQoriqLsHelper.S | GCC
> + NxpQoriqLsMem.c
> +
> +
> +[Ppis]
> + gArmMpCoreInfoPpiGuid
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdArmPrimaryCore
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size
> + gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size
> + gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalSize
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsCacheSize
> +
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> new file mode 100644
> index 0000000..1917b02
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> @@ -0,0 +1,35 @@
> +#/** @file
> +#
> +# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#**/
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <AutoGen.h>
> +
> +.text
> +.align 2
> +
> +GCC_ASM_IMPORT(ArmReadMpidr)
> +
> +ASM_FUNC(ArmPlatformIsPrimaryCore)
> + tst x0, #3
> + cset x0, eq
> + ret
> +
> +ASM_FUNC(ArmPlatformPeiBootAction)
> + ret
> +
> +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
> + MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
> + ldrh w0, [x0]
> + ret
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> new file mode 100644
> index 0000000..ccb49f6
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> @@ -0,0 +1,189 @@
> +/** NxpQoriqLsMem.c
> +*
> +* Board memory specific Library.
> +*
> +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
> +*
> +* Copyright (c) 2011, ARM Limited. All rights reserved.
> +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
> +
> +//
> +// Calculate the MC (Management Complex) base address and DDR size based on
> +// if the MC is loaded in DDR low memory region or in DDR high memory region.
> +//
> +#if FixedPcdGetBool (PcdMcHighMemSupport)
> +#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemSize) - FixedPcdGet64 (PcdDpaa2McRamSize)
> +#define MC_BASE_ADDR FixedPcdGet64 (PcdDram2BaseAddr) + DDR_MEM_SIZE
> +#else
> +#define DDR_MEM_SIZE FixedPcdGet64 (PcdDramMemSize)
> +#define MC_BASE_ADDR FixedPcdGet64 (PcdDram1BaseAddr) - FixedPcdGet64 (PcdDpaa2McRamSize)
Very long lines. Drop some whitespace.
> +#endif
> +
> +
> +/**
> + Return the Virtual Memory Map of your platform
> +
> + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
> +
> + @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
> + Virtual Memory mapping. This array must be ended by a zero-filled
> + entry
I realise this is inherited from BeagleBoardMem.c, but please adjust
the line length of comment blocks to <= 80.
> +
> +**/
> +
> +VOID
> +ArmPlatformGetVirtualMemoryMap (
> + IN ARM_MEMORY_REGION_DESCRIPTOR ** VirtualMemoryMap
No space after **.
> + )
> +{
> + UINTN Index;
> + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> +
> + Index = 0;
> +
> + ASSERT (VirtualMemoryMap != NULL);
> +
> + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
> + EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
> +
> + if (VirtualMemoryTable == NULL) {
> + return;
> + }
> +
> + // DRAM1 (Must be 1st entry)
> + VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdDram1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDram1Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
> +
> + // CCSR Space
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // IFC region 1
> + //
> + // A-009241 : Unaligned write transactions to IFC may result in corruption of data
> + // Affects : IFC
> + // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
> + // writes on external IFC interface that can corrupt data on external flash.
> + // Impact : Data corruption on external flash may happen in case of unaligned writes to
> + // IFC memory space.
> + // Workaround: Following are the workarounds:
> + // For write transactions from core, IFC interface memories (including IFC SRAM)
> + // should be configured as device type memory in MMU.
> + // For write transactions from non-core masters (like system DMA), the address
> + // should be 16 byte aligned and the data size should be multiple of 16 bytes.
> + //
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // IFC region 2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // QSPI region 1
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // QSPI region 2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegion2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegion2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegion2Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
> +
> + // DRAM2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDram2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDram2BaseAddr);
> + VirtualMemoryTable[Index].Length = DDR_MEM_SIZE;
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
> +
> + // MC private DRAM
> + VirtualMemoryTable[++Index].PhysicalBase = MC_BASE_ADDR;
> + VirtualMemoryTable[Index].VirtualBase = MC_BASE_ADDR;
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2McRamSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe1
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe2
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe3
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe4
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp4BaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp4BaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp4BaseSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DPAA2 MC Portals region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2McPortalBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2McPortalBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2McPortalSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DPAA2 NI Portals region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2NiPortalsBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2NiPortalsBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2NiPortalsSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // DPAA2 QBMAN Portals - cache enabled region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ;
> +
> + // DPAA2 QBMAN Portals - cache inhibited region
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdDpaa2QBmanPortalsBaseAddr) + FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdDpaa2QBmanPortalSize) - FixedPcdGet64 (PcdDpaa2QBmanPortalsCacheSize);
And please wrap above 3 lines at +/-.
/
Leif
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // End of Table
> + VirtualMemoryTable[++Index].PhysicalBase = 0;
> + VirtualMemoryTable[Index].VirtualBase = 0;
> + VirtualMemoryTable[Index].Length = 0;
> + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
> +
> + ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> + *VirtualMemoryMap = VirtualMemoryTable;
> +}
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 27/41] Platform/NXP: Add Platform driver for LS2088 RDB board
2018-11-28 15:01 ` [PATCH edk2-platforms 27/41] Platform/NXP: Add Platform driver for LS2088 RDB board Meenakshi Aggarwal
@ 2018-12-21 9:35 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 9:35 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
Add a commit message describing what the driver does, please.
On Wed, Nov 28, 2018 at 08:31:41PM +0530, Meenakshi Aggarwal wrote:
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> .../Drivers/PlatformDxe/PlatformDxe.c | 119 +++++++++++++++++++++
> .../Drivers/PlatformDxe/PlatformDxe.inf | 58 ++++++++++
> 2 files changed, 177 insertions(+)
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> new file mode 100644
> index 0000000..667e750
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> @@ -0,0 +1,119 @@
> +/** @file
> + LS2088 RDB board DXE platform driver.
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +**/
> +
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +
> +#include <Protocol/NonDiscoverableDevice.h>
> +
> +typedef struct {
> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR StartDesc;
> + UINT8 EndDesc;
> +} ADDRESS_SPACE_DESCRIPTOR;
> +
> +STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
> +
> +STATIC
> +EFI_STATUS
> +RegisterDevice (
> + IN EFI_GUID *TypeGuid,
> + IN ADDRESS_SPACE_DESCRIPTOR *Desc,
> + OUT EFI_HANDLE *Handle
> + )
> +{
> + NON_DISCOVERABLE_DEVICE *Device;
> + EFI_STATUS Status;
> +
> + Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device));
> + if (Device == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + Device->Type = TypeGuid;
> + Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent;
> + Device->Resources = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Desc;
> +
> + Status = gBS->InstallMultipleProtocolInterfaces (Handle,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid, Device,
> + NULL);
> + if (EFI_ERROR (Status)) {
> + goto FreeDevice;
> + }
> + return EFI_SUCCESS;
> +
> +FreeDevice:
> + FreePool (Device);
> +
> + return Status;
> +}
> +
> +VOID
> +PopulateI2cInformation (
> + IN VOID
> + )
> +{
> + UINT32 Index;
> +
> + for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
> + mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
> + mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
> + mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
> + mI2cDesc[Index].StartDesc.GenFlag = 0;
> + mI2cDesc[Index].StartDesc.SpecificFlag = 0;
> + mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
> + mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
> + (Index * FixedPcdGet32 (PcdI2cSize));
> + mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
> + FixedPcdGet32 (PcdI2cSize) - 1;
> + mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
> + mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
> +
> + mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
This comes with the same problem I mentioned in a similar place for
another platform. Among other things, that gives the impression this
could be broken out into a separate helper library and fixed once
rather than several times.
/
Leif
> + }
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +PlatformDxeEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE Handle;
> +
> + Handle = NULL;
> +
> + PopulateI2cInformation ();
> +
> + Status = RegisterDevice (&gNxpNonDiscoverableI2cMasterGuid,
> + &mI2cDesc[0], &Handle);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Install the DS3232 I2C Master protocol on this handle so the RTC driver
> + // can identify it as the I2C master it can invoke directly.
> + //
> + Status = gBS->InstallProtocolInterface (&Handle,
> + &gDs3232RealTimeClockLibI2cMasterProtocolGuid,
> + EFI_NATIVE_INTERFACE, NULL);
> + ASSERT_EFI_ERROR (Status);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> new file mode 100644
> index 0000000..1972022
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> @@ -0,0 +1,58 @@
> +## @file
> +#
> +# Component description file for LS2088 DXE platform driver.
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PlatformDxe
> + FILE_GUID = 71dbcbc8-8cde-41ff-b51c-02fe338a60c3
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PlatformDxeEntryPoint
> +
> +[Sources]
> + PlatformDxe.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + DebugLib
> + MemoryAllocationLib
> + PcdLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> + UefiLib
> +
> +[Guids]
> + gNxpNonDiscoverableI2cMasterGuid
> +
> +[Protocols]
> + gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
> + gDs3232RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES
> +
> +[FixedPcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
> +
> +[Depex]
> + TRUE
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 28/41] Silicon/Maxim: DS3232 RTC Library Support
2018-11-28 15:01 ` [PATCH edk2-platforms 28/41] Silicon/Maxim: DS3232 RTC Library Support Meenakshi Aggarwal
@ 2018-12-21 9:56 ` Leif Lindholm
2018-12-21 10:01 ` Ard Biesheuvel
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 9:56 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Wasim Khan
On Wed, Nov 28, 2018 at 08:31:42PM +0530, Meenakshi Aggarwal wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
>
> Add Maxim DS3232 RTC Library support
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h | 49 +++
> Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c | 420 +++++++++++++++++++++
> .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec | 34 ++
> .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf | 50 +++
> 4 files changed, 553 insertions(+)
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
>
> diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
> new file mode 100644
> index 0000000..cd1a321
> --- /dev/null
> +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
> @@ -0,0 +1,49 @@
> +/** Ds3232Rtc.h
> +*
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __DS3232RTC_H__
> +#define __DS3232RTC_H__
> +
> +//RTC time register
> +#define DS3232_SEC_REG_ADDR 0x00
> +#define DS3232_MIN_REG_ADDR 0x01
> +#define DS3232_HR_REG_ADDR 0x02
> +#define DS3232_DAY_REG_ADDR 0x03
> +#define DS3232_DATE_REG_ADDR 0x04
> +#define DS3232_MON_REG_ADDR 0x05
> +#define DS3232_YR_REG_ADDR 0x06
> +
> +#define DS3232_SEC_BIT_CH 0x80 // Clock Halt (in Register 0)
> +
> +//RTC control register
> +#define DS3232_CTL_REG_ADDR 0x0e
> +#define DS3232_STAT_REG_ADDR 0x0f
> +
> +#define START_YEAR 1970
> +#define END_YEAR 2070
> +
> +//TIME MASKS
> +#define MASK_SEC 0x7F
> +#define MASK_MIN 0x7F
> +#define MASK_HOUR 0x3F
> +#define MASK_DAY 0x3F
> +#define MASK_MONTH 0x1F
> +
> +typedef struct {
> + UINTN OperationCount;
> + EFI_I2C_OPERATION SetAddressOp;
> + EFI_I2C_OPERATION GetSetDateTimeOp;
> +} RTC_I2C_REQUEST;
> +
> +#endif // __DS3232RTC_H__
> diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
> new file mode 100644
> index 0000000..3ab94a8
> --- /dev/null
> +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
> @@ -0,0 +1,420 @@
> +/** Ds3232RtcLib.c
> +* Implement EFI RealTimeClock via RTC Lib for DS3232 RTC.
> +*
> +* Based on RTC implementation available in
> +* EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
> +*
> +* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> +* Copyright 2017 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <PiDxe.h>
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/RealTimeClockLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +#include <Protocol/I2cMaster.h>
> +
> +#include "Ds3232Rtc.h"
> +
> +STATIC VOID *mDriverEventRegistration;
> +STATIC EFI_HANDLE mI2cMasterHandle;
> +STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
> +
> +/**
> + Read RTC register.
> +
> + @param SlaveDeviceAddress Slave device address offset of RTC to be read.
> + @param RtcRegAddr Register offset of RTC to be read.
> +
> + @retval Register Value read
> +
> +**/
> +STATIC
> +UINT8
> +RtcRead (
> + IN UINT8 SlaveDeviceAddress,
> + IN UINT8 RtcRegAddr
> + )
> +{
> + RTC_I2C_REQUEST Req;
> + EFI_STATUS Status;
> + UINT8 Val;
> +
> + Val = 0;
> +
> + Req.OperationCount = 2;
> +
> + Req.SetAddressOp.Flags = 0;
> + Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
> + Req.SetAddressOp.Buffer = &RtcRegAddr;
> +
> + Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
> + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
> + Req.GetSetDateTimeOp.Buffer = &Val;
> +
> + Status = mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress,
> + (VOID *)&Req,
> + NULL, NULL);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
> + }
> +
> + return Val;
> +}
> +
> +/**
> + Write RTC register.
> +
> + @param SlaveDeviceAddress Slave device address offset of RTC to be read.
> + @param RtcRegAddr Register offset of RTC to write.
> + @param Val Value to be written
> +
> +**/
> +STATIC
> +VOID
> +RtcWrite (
> + IN UINT8 SlaveDeviceAddress,
> + IN UINT8 RtcRegAddr,
> + IN UINT8 Val
> + )
> +{
> + RTC_I2C_REQUEST Req;
> + EFI_STATUS Status;
> +
> + Req.OperationCount = 2;
> +
> + Req.SetAddressOp.Flags = 0;
> + Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
> + Req.SetAddressOp.Buffer = &RtcRegAddr;
> +
> + Req.GetSetDateTimeOp.Flags = 0;
> + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
> + Req.GetSetDateTimeOp.Buffer = &Val;
> +
> + Status = mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress,
> + (VOID *)&Req,
> + NULL, NULL);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
> + }
> +}
> +
> +/**
> + Configure the MUX device connected to I2C.
> +
> + @param RegValue Value to write on mux device register address
> +
> +**/
> +VOID
> +ConfigureMuxDevice (
> + IN UINT8 RegValue
> + )
> +{
> + RtcWrite (FixedPcdGet8 (PcdMuxDeviceAddress), FixedPcdGet8 (PcdMuxControlRegOffset), RegValue);
> +}
> +
> +/**
> + Returns the current time and date information, and the time-keeping capabilities
> + of the hardware platform.
> +
> + @param Time A pointer to storage to receive a snapshot of the current time.
> + @param Capabilities An optional pointer to a buffer to receive the real time clock
> + device's capabilities.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_INVALID_PARAMETER Time is NULL.
> + @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibGetTime (
> + OUT EFI_TIME *Time,
> + OUT EFI_TIME_CAPABILITIES *Capabilities
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 Second;
> + UINT8 Minute;
> + UINT8 Hour;
> + UINT8 Day;
> + UINT8 Month;
> + UINT8 Year;
> +
> + if (mI2cMaster == NULL) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + Status = EFI_SUCCESS;
> +
> + //
> + // Check if the I2C device is connected though a MUX device.
> + //
> + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
Hmm, if this is the case, then I think we also need a RaiseTPL before
flipping the mux, and a RestoreTPL after we set it back to default.
This also needs to be done in any other modules accessing hardware
behind this mux. TPL_CALLBACK should be sufficient, as long as that's
what all of the modules use.
> + // Switch to the channel connected to Ds3232 RTC
> + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxRtcChannelValue));
> + }
> +
> + Second = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR);
> + Minute = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MIN_REG_ADDR);
> + Hour = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_HR_REG_ADDR);
> + Day = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_DATE_REG_ADDR);
> + Month = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MON_REG_ADDR);
> + Year = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_YR_REG_ADDR);
> +
Please put FixedPcdGet8 (PcdI2cSlaveAddress) into a temporary variable.
> + if (Second & DS3232_SEC_BIT_CH) {
> + DEBUG ((DEBUG_ERROR, "### Warning: RTC oscillator has stopped\n"));
> + /* clear the CH flag */
> + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR,
> + RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR) & ~DS3232_SEC_BIT_CH);
That should also clean up this line somewhat.
> + Status = EFI_DEVICE_ERROR;
> + goto EXIT;
> + }
> +
> + Time->Second = BcdToDecimal8 (Second & MASK_SEC);
> + Time->Minute = BcdToDecimal8 (Minute & MASK_MIN);
> + Time->Hour = BcdToDecimal8 (Hour & MASK_HOUR);
> + Time->Day = BcdToDecimal8 (Day & MASK_DAY);
> + Time->Month = BcdToDecimal8 (Month & MASK_MONTH);
> +
> + //
> + // RTC can save year 1970 to 2069
> + // On writing Year, save year % 100
> + // On Reading reversing the operation e.g. 2012
> + // write = 12 (2012 % 100)
> + // read = 2012 (12 + 2000)
> + //
> + Time->Year = BcdToDecimal8 (Year) +
> + (BcdToDecimal8 (Year) >= 70 ? START_YEAR - 70 : END_YEAR -70);
Please break the adjustment out into its own calculation and a
temmporary variable.
> +
> +EXIT:
> + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
> + // Switch to the default channel
> + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxDefaultChannelValue));
> + }
> +
> + return Status;
> +}
> +
> +/**
> + Sets the current local time and date information.
> +
> + @param Time A pointer to the current time.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_INVALID_PARAMETER A time field is out of range.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibSetTime (
> + IN EFI_TIME *Time
> + )
> +{
> + if (mI2cMaster == NULL) {
> + return EFI_DEVICE_ERROR;
> + }
> +
> + if (Time->Year < START_YEAR || Time->Year >= END_YEAR){
> + DEBUG ((DEBUG_ERROR, "WARNING: Year should be between 1970 and 2069!\n"));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Check if the I2C device is connected though a MUX device.
> + //
> + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
> + // Switch to the channel connected to Ds3232 RTC
> + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxRtcChannelValue));
> + }
> +
> + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_YR_REG_ADDR, DecimalToBcd8 (Time->Year % 100));
> + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MON_REG_ADDR, DecimalToBcd8 (Time->Month));
> + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_DATE_REG_ADDR, DecimalToBcd8 (Time->Day));
> + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_HR_REG_ADDR, DecimalToBcd8 (Time->Hour));
> + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MIN_REG_ADDR, DecimalToBcd8 (Time->Minute));
> + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR, DecimalToBcd8 (Time->Second));
FixedPcdGet8 (PcdI2cSlaveAddress) in a temporary variable, please.
/
Leif
> +
> + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
> + // Switch to the default channel
> + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxDefaultChannelValue));
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Returns the current wakeup alarm clock setting.
> +
> + @param Enabled Indicates if the alarm is currently enabled or disabled.
> + @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
> + @param Time The current alarm setting.
> +
> + @retval EFI_SUCCESS The alarm settings were returned.
> + @retval EFI_INVALID_PARAMETER Any parameter is NULL.
> + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibGetWakeupTime (
> + OUT BOOLEAN *Enabled,
> + OUT BOOLEAN *Pending,
> + OUT EFI_TIME *Time
> + )
> +{
> + // Currently not supporting this feature.
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + Sets the system wakeup alarm clock time.
> +
> + @param Enabled Enable or disable the wakeup alarm.
> + @param Time If Enable is TRUE, the time to set the wakeup alarm for.
> +
> + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
> + Enable is FALSE, then the wakeup alarm was disabled.
> + @retval EFI_INVALID_PARAMETER A time field is out of range.
> + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
> + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibSetWakeupTime (
> + IN BOOLEAN Enabled,
> + OUT EFI_TIME *Time
> + )
> +{
> + // Currently not supporting this feature.
> + return EFI_UNSUPPORTED;
> +}
> +
> +STATIC
> +VOID
> +I2cDriverRegistrationEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + EFI_STATUS Status;
> + EFI_I2C_MASTER_PROTOCOL *I2cMaster;
> + UINTN BusFrequency;
> + EFI_HANDLE Handle;
> + UINTN BufferSize;
> +
> + //
> + // Try to connect the newly registered driver to our handle.
> + //
> + do {
> + BufferSize = sizeof (EFI_HANDLE);
> + Status = gBS->LocateHandle (ByRegisterNotify,
> + &gEfiI2cMasterProtocolGuid,
> + mDriverEventRegistration,
> + &BufferSize,
> + &Handle);
> + if (EFI_ERROR (Status)) {
> + if (Status != EFI_NOT_FOUND) {
> + DEBUG ((DEBUG_WARN, "%a: gBS->LocateHandle () returned %r\n",
> + __FUNCTION__, Status));
> + }
> + break;
> + }
> +
> + if (Handle != mI2cMasterHandle) {
> + continue;
> + }
> +
> + DEBUG ((DEBUG_INFO, "%a: found I2C master!\n", __FUNCTION__));
> +
> + gBS->CloseEvent (Event);
> +
> + Status = gBS->OpenProtocol (mI2cMasterHandle, &gEfiI2cMasterProtocolGuid,
> + (VOID **)&I2cMaster, gImageHandle, NULL,
> + EFI_OPEN_PROTOCOL_EXCLUSIVE);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = I2cMaster->Reset (I2cMaster);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
> + __FUNCTION__, Status));
> + break;
> + }
> +
> + BusFrequency = FixedPcdGet16 (PcdI2cBusFrequency);
> + Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
> + __FUNCTION__, Status));
> + break;
> + }
> +
> + mI2cMaster = I2cMaster;
> + break;
> + } while (TRUE);
> +
> + return;
> +
> +}
> +
> +/**
> + This is the declaration of an EFI image entry point. This can be the entry point to an application
> + written to this specification, an EFI boot service driver.
> +
> + @param ImageHandle Handle that identifies the loaded image.
> + @param SystemTable System Table for this image.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibRtcInitialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + UINTN BufferSize;
> +
> + //
> + // Find the handle that marks the controller
> + // that will provide the I2C master protocol.
> + //
> + BufferSize = sizeof (EFI_HANDLE);
> + Status = gBS->LocateHandle (
> + ByProtocol,
> + &gDs3232RealTimeClockLibI2cMasterProtocolGuid,
> + NULL,
> + &BufferSize,
> + &mI2cMasterHandle
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Register a protocol registration notification callback on the driver
> + // binding protocol so we can attempt to connect our I2C master to it
> + // as soon as it appears.
> + //
> + EfiCreateProtocolNotifyEvent (
> + &gEfiI2cMasterProtocolGuid,
> + TPL_CALLBACK,
> + I2cDriverRegistrationEvent,
> + NULL,
> + &mDriverEventRegistration);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> new file mode 100644
> index 0000000..a0033a2
> --- /dev/null
> +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> @@ -0,0 +1,34 @@
> +#/** @file
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#**/
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x0001001A
> + PACKAGE_NAME = Ds3232RtcLib
> + PACKAGE_GUID = 0b4192f7-e404-4019-b2e5-1e6004da3313
> + PACKAGE_VERSION = 0.1
> +
> +[Guids]
> + gDs3232RtcLibTokenSpaceGuid = { 0x7960fc51, 0x0832, 0x4f0b, { 0xb4, 0x22, 0x53, 0x87, 0x03, 0xaa, 0x85, 0xda }}
> +
> +[Protocols]
> + gDs3232RealTimeClockLibI2cMasterProtocolGuid = { 0xa17eb2ee, 0xcadc, 0x40f1, { 0x8a, 0x45, 0x4d, 0x5a, 0xf3, 0xd6, 0xce, 0x53 }}
> +
> +[PcdsFixedAtBuild]
> + gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001
> + gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002
> + gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed|FALSE|BOOLEAN|0x00000003
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress|0|UINT8|0x00000004
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset|0|UINT8|0x00000005
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0|UINT8|0x00000006
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0|UINT8|0x00000007
> diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> new file mode 100644
> index 0000000..95664c1
> --- /dev/null
> +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> @@ -0,0 +1,50 @@
> +# @Ds3232RtcLib.inf
> +#
> +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = Ds3232RtcLib
> + FILE_GUID = 97f1f2c2-51e1-47ad-9660-70b33da1fe71
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = RealTimeClockLib
> +
> +[Sources.common]
> + Ds3232RtcLib.c
> +
> +[Packages]
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> +
> +[LibraryClasses]
> + DebugLib
> + UefiBootServicesTableLib
> + UefiLib
> +
> +[Protocols]
> + gEfiI2cMasterProtocolGuid ## CONSUMES
> + gDs3232RealTimeClockLibI2cMasterProtocolGuid ## CONSUMES
> +
> +[FixedPcd]
> + gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress
> + gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency
> + gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue
> +
> +[Depex]
> + gDs3232RealTimeClockLibI2cMasterProtocolGuid
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 28/41] Silicon/Maxim: DS3232 RTC Library Support
2018-12-21 9:56 ` Leif Lindholm
@ 2018-12-21 10:01 ` Ard Biesheuvel
0 siblings, 0 replies; 254+ messages in thread
From: Ard Biesheuvel @ 2018-12-21 10:01 UTC (permalink / raw)
To: Leif Lindholm
Cc: Meenakshi Aggarwal, Kinney, Michael D, edk2-devel@lists.01.org,
Udit Kumar, Varun Sethi, Wasim Khan
On Fri, 21 Dec 2018 at 10:56, Leif Lindholm <leif.lindholm@linaro.org> wrote:
>
> On Wed, Nov 28, 2018 at 08:31:42PM +0530, Meenakshi Aggarwal wrote:
> > From: Wasim Khan <wasim.khan@nxp.com>
> >
> > Add Maxim DS3232 RTC Library support
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> > Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> > ---
> > Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h | 49 +++
> > Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c | 420 +++++++++++++++++++++
> > .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec | 34 ++
> > .../Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf | 50 +++
> > 4 files changed, 553 insertions(+)
> > create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
> > create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
> > create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> > create mode 100644 Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> >
> > diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
> > new file mode 100644
> > index 0000000..cd1a321
> > --- /dev/null
> > +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232Rtc.h
> > @@ -0,0 +1,49 @@
> > +/** Ds3232Rtc.h
> > +*
> > +* Copyright 2017 NXP
> > +*
> > +* This program and the accompanying materials
> > +* are licensed and made available under the terms and conditions of the BSD License
> > +* which accompanies this distribution. The full text of the license may be found at
> > +* http://opensource.org/licenses/bsd-license.php
> > +*
> > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> > +*
> > +**/
> > +
> > +#ifndef __DS3232RTC_H__
> > +#define __DS3232RTC_H__
> > +
> > +//RTC time register
> > +#define DS3232_SEC_REG_ADDR 0x00
> > +#define DS3232_MIN_REG_ADDR 0x01
> > +#define DS3232_HR_REG_ADDR 0x02
> > +#define DS3232_DAY_REG_ADDR 0x03
> > +#define DS3232_DATE_REG_ADDR 0x04
> > +#define DS3232_MON_REG_ADDR 0x05
> > +#define DS3232_YR_REG_ADDR 0x06
> > +
> > +#define DS3232_SEC_BIT_CH 0x80 // Clock Halt (in Register 0)
> > +
> > +//RTC control register
> > +#define DS3232_CTL_REG_ADDR 0x0e
> > +#define DS3232_STAT_REG_ADDR 0x0f
> > +
> > +#define START_YEAR 1970
> > +#define END_YEAR 2070
> > +
> > +//TIME MASKS
> > +#define MASK_SEC 0x7F
> > +#define MASK_MIN 0x7F
> > +#define MASK_HOUR 0x3F
> > +#define MASK_DAY 0x3F
> > +#define MASK_MONTH 0x1F
> > +
> > +typedef struct {
> > + UINTN OperationCount;
> > + EFI_I2C_OPERATION SetAddressOp;
> > + EFI_I2C_OPERATION GetSetDateTimeOp;
> > +} RTC_I2C_REQUEST;
> > +
> > +#endif // __DS3232RTC_H__
> > diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
> > new file mode 100644
> > index 0000000..3ab94a8
> > --- /dev/null
> > +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.c
> > @@ -0,0 +1,420 @@
> > +/** Ds3232RtcLib.c
> > +* Implement EFI RealTimeClock via RTC Lib for DS3232 RTC.
> > +*
> > +* Based on RTC implementation available in
> > +* EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
> > +*
> > +* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> > +* Copyright 2017 NXP
> > +*
> > +* This program and the accompanying materials
> > +* are licensed and made available under the terms and conditions of the BSD License
> > +* which accompanies this distribution. The full text of the license may be found at
> > +* http://opensource.org/licenses/bsd-license.php
> > +*
> > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> > +*
> > +**/
> > +
> > +#include <PiDxe.h>
> > +#include <Base.h>
> > +#include <Library/BaseLib.h>
> > +#include <Library/DebugLib.h>
> > +#include <Library/RealTimeClockLib.h>
> > +#include <Library/UefiBootServicesTableLib.h>
> > +#include <Library/UefiLib.h>
> > +#include <Protocol/I2cMaster.h>
> > +
> > +#include "Ds3232Rtc.h"
> > +
> > +STATIC VOID *mDriverEventRegistration;
> > +STATIC EFI_HANDLE mI2cMasterHandle;
> > +STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
> > +
> > +/**
> > + Read RTC register.
> > +
> > + @param SlaveDeviceAddress Slave device address offset of RTC to be read.
> > + @param RtcRegAddr Register offset of RTC to be read.
> > +
> > + @retval Register Value read
> > +
> > +**/
> > +STATIC
> > +UINT8
> > +RtcRead (
> > + IN UINT8 SlaveDeviceAddress,
> > + IN UINT8 RtcRegAddr
> > + )
> > +{
> > + RTC_I2C_REQUEST Req;
> > + EFI_STATUS Status;
> > + UINT8 Val;
> > +
> > + Val = 0;
> > +
> > + Req.OperationCount = 2;
> > +
> > + Req.SetAddressOp.Flags = 0;
> > + Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
> > + Req.SetAddressOp.Buffer = &RtcRegAddr;
> > +
> > + Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
> > + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
> > + Req.GetSetDateTimeOp.Buffer = &Val;
> > +
> > + Status = mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress,
> > + (VOID *)&Req,
> > + NULL, NULL);
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
> > + }
> > +
> > + return Val;
> > +}
> > +
> > +/**
> > + Write RTC register.
> > +
> > + @param SlaveDeviceAddress Slave device address offset of RTC to be read.
> > + @param RtcRegAddr Register offset of RTC to write.
> > + @param Val Value to be written
> > +
> > +**/
> > +STATIC
> > +VOID
> > +RtcWrite (
> > + IN UINT8 SlaveDeviceAddress,
> > + IN UINT8 RtcRegAddr,
> > + IN UINT8 Val
> > + )
> > +{
> > + RTC_I2C_REQUEST Req;
> > + EFI_STATUS Status;
> > +
> > + Req.OperationCount = 2;
> > +
> > + Req.SetAddressOp.Flags = 0;
> > + Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
> > + Req.SetAddressOp.Buffer = &RtcRegAddr;
> > +
> > + Req.GetSetDateTimeOp.Flags = 0;
> > + Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
> > + Req.GetSetDateTimeOp.Buffer = &Val;
> > +
> > + Status = mI2cMaster->StartRequest (mI2cMaster, SlaveDeviceAddress,
> > + (VOID *)&Req,
> > + NULL, NULL);
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
> > + }
> > +}
> > +
> > +/**
> > + Configure the MUX device connected to I2C.
> > +
> > + @param RegValue Value to write on mux device register address
> > +
> > +**/
> > +VOID
> > +ConfigureMuxDevice (
> > + IN UINT8 RegValue
> > + )
> > +{
> > + RtcWrite (FixedPcdGet8 (PcdMuxDeviceAddress), FixedPcdGet8 (PcdMuxControlRegOffset), RegValue);
> > +}
> > +
> > +/**
> > + Returns the current time and date information, and the time-keeping capabilities
> > + of the hardware platform.
> > +
> > + @param Time A pointer to storage to receive a snapshot of the current time.
> > + @param Capabilities An optional pointer to a buffer to receive the real time clock
> > + device's capabilities.
> > +
> > + @retval EFI_SUCCESS The operation completed successfully.
> > + @retval EFI_INVALID_PARAMETER Time is NULL.
> > + @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +LibGetTime (
> > + OUT EFI_TIME *Time,
> > + OUT EFI_TIME_CAPABILITIES *Capabilities
> > + )
> > +{
> > + EFI_STATUS Status;
> > + UINT8 Second;
> > + UINT8 Minute;
> > + UINT8 Hour;
> > + UINT8 Day;
> > + UINT8 Month;
> > + UINT8 Year;
> > +
> > + if (mI2cMaster == NULL) {
> > + return EFI_DEVICE_ERROR;
> > + }
> > +
> > + Status = EFI_SUCCESS;
> > +
> > + //
> > + // Check if the I2C device is connected though a MUX device.
> > + //
> > + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
>
> Hmm, if this is the case, then I think we also need a RaiseTPL before
> flipping the mux, and a RestoreTPL after we set it back to default.
> This also needs to be done in any other modules accessing hardware
> behind this mux. TPL_CALLBACK should be sufficient, as long as that's
> what all of the modules use.
>
If this device is behind a mux that is controlled by the OS at
runtime, this RTC is not usable in UEFI.
> > + // Switch to the channel connected to Ds3232 RTC
> > + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxRtcChannelValue));
> > + }
> > +
> > + Second = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR);
> > + Minute = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MIN_REG_ADDR);
> > + Hour = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_HR_REG_ADDR);
> > + Day = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_DATE_REG_ADDR);
> > + Month = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MON_REG_ADDR);
> > + Year = RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_YR_REG_ADDR);
> > +
>
> Please put FixedPcdGet8 (PcdI2cSlaveAddress) into a temporary variable.
>
> > + if (Second & DS3232_SEC_BIT_CH) {
> > + DEBUG ((DEBUG_ERROR, "### Warning: RTC oscillator has stopped\n"));
> > + /* clear the CH flag */
> > + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR,
> > + RtcRead (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR) & ~DS3232_SEC_BIT_CH);
>
> That should also clean up this line somewhat.
>
> > + Status = EFI_DEVICE_ERROR;
> > + goto EXIT;
> > + }
> > +
> > + Time->Second = BcdToDecimal8 (Second & MASK_SEC);
> > + Time->Minute = BcdToDecimal8 (Minute & MASK_MIN);
> > + Time->Hour = BcdToDecimal8 (Hour & MASK_HOUR);
> > + Time->Day = BcdToDecimal8 (Day & MASK_DAY);
> > + Time->Month = BcdToDecimal8 (Month & MASK_MONTH);
> > +
> > + //
> > + // RTC can save year 1970 to 2069
> > + // On writing Year, save year % 100
> > + // On Reading reversing the operation e.g. 2012
> > + // write = 12 (2012 % 100)
> > + // read = 2012 (12 + 2000)
> > + //
> > + Time->Year = BcdToDecimal8 (Year) +
> > + (BcdToDecimal8 (Year) >= 70 ? START_YEAR - 70 : END_YEAR -70);
>
> Please break the adjustment out into its own calculation and a
> temmporary variable.
>
> > +
> > +EXIT:
> > + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
> > + // Switch to the default channel
> > + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxDefaultChannelValue));
> > + }
> > +
> > + return Status;
> > +}
> > +
> > +/**
> > + Sets the current local time and date information.
> > +
> > + @param Time A pointer to the current time.
> > +
> > + @retval EFI_SUCCESS The operation completed successfully.
> > + @retval EFI_INVALID_PARAMETER A time field is out of range.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +LibSetTime (
> > + IN EFI_TIME *Time
> > + )
> > +{
> > + if (mI2cMaster == NULL) {
> > + return EFI_DEVICE_ERROR;
> > + }
> > +
> > + if (Time->Year < START_YEAR || Time->Year >= END_YEAR){
> > + DEBUG ((DEBUG_ERROR, "WARNING: Year should be between 1970 and 2069!\n"));
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + //
> > + // Check if the I2C device is connected though a MUX device.
> > + //
> > + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
> > + // Switch to the channel connected to Ds3232 RTC
> > + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxRtcChannelValue));
> > + }
> > +
> > + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_YR_REG_ADDR, DecimalToBcd8 (Time->Year % 100));
> > + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MON_REG_ADDR, DecimalToBcd8 (Time->Month));
> > + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_DATE_REG_ADDR, DecimalToBcd8 (Time->Day));
> > + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_HR_REG_ADDR, DecimalToBcd8 (Time->Hour));
> > + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_MIN_REG_ADDR, DecimalToBcd8 (Time->Minute));
> > + RtcWrite (FixedPcdGet8 (PcdI2cSlaveAddress), DS3232_SEC_REG_ADDR, DecimalToBcd8 (Time->Second));
>
> FixedPcdGet8 (PcdI2cSlaveAddress) in a temporary variable, please.
>
> /
> Leif
>
> > +
> > + if (FixedPcdGetBool (PcdIsRtcDeviceMuxed)) {
> > + // Switch to the default channel
> > + ConfigureMuxDevice (FixedPcdGet8 (PcdMuxDefaultChannelValue));
> > + }
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +/**
> > + Returns the current wakeup alarm clock setting.
> > +
> > + @param Enabled Indicates if the alarm is currently enabled or disabled.
> > + @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
> > + @param Time The current alarm setting.
> > +
> > + @retval EFI_SUCCESS The alarm settings were returned.
> > + @retval EFI_INVALID_PARAMETER Any parameter is NULL.
> > + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +LibGetWakeupTime (
> > + OUT BOOLEAN *Enabled,
> > + OUT BOOLEAN *Pending,
> > + OUT EFI_TIME *Time
> > + )
> > +{
> > + // Currently not supporting this feature.
> > + return EFI_UNSUPPORTED;
> > +}
> > +
> > +/**
> > + Sets the system wakeup alarm clock time.
> > +
> > + @param Enabled Enable or disable the wakeup alarm.
> > + @param Time If Enable is TRUE, the time to set the wakeup alarm for.
> > +
> > + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
> > + Enable is FALSE, then the wakeup alarm was disabled.
> > + @retval EFI_INVALID_PARAMETER A time field is out of range.
> > + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
> > + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +LibSetWakeupTime (
> > + IN BOOLEAN Enabled,
> > + OUT EFI_TIME *Time
> > + )
> > +{
> > + // Currently not supporting this feature.
> > + return EFI_UNSUPPORTED;
> > +}
> > +
> > +STATIC
> > +VOID
> > +I2cDriverRegistrationEvent (
> > + IN EFI_EVENT Event,
> > + IN VOID *Context
> > + )
> > +{
> > + EFI_STATUS Status;
> > + EFI_I2C_MASTER_PROTOCOL *I2cMaster;
> > + UINTN BusFrequency;
> > + EFI_HANDLE Handle;
> > + UINTN BufferSize;
> > +
> > + //
> > + // Try to connect the newly registered driver to our handle.
> > + //
> > + do {
> > + BufferSize = sizeof (EFI_HANDLE);
> > + Status = gBS->LocateHandle (ByRegisterNotify,
> > + &gEfiI2cMasterProtocolGuid,
> > + mDriverEventRegistration,
> > + &BufferSize,
> > + &Handle);
> > + if (EFI_ERROR (Status)) {
> > + if (Status != EFI_NOT_FOUND) {
> > + DEBUG ((DEBUG_WARN, "%a: gBS->LocateHandle () returned %r\n",
> > + __FUNCTION__, Status));
> > + }
> > + break;
> > + }
> > +
> > + if (Handle != mI2cMasterHandle) {
> > + continue;
> > + }
> > +
> > + DEBUG ((DEBUG_INFO, "%a: found I2C master!\n", __FUNCTION__));
> > +
> > + gBS->CloseEvent (Event);
> > +
> > + Status = gBS->OpenProtocol (mI2cMasterHandle, &gEfiI2cMasterProtocolGuid,
> > + (VOID **)&I2cMaster, gImageHandle, NULL,
> > + EFI_OPEN_PROTOCOL_EXCLUSIVE);
> > + ASSERT_EFI_ERROR (Status);
> > +
> > + Status = I2cMaster->Reset (I2cMaster);
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
> > + __FUNCTION__, Status));
> > + break;
> > + }
> > +
> > + BusFrequency = FixedPcdGet16 (PcdI2cBusFrequency);
> > + Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
> > + __FUNCTION__, Status));
> > + break;
> > + }
> > +
> > + mI2cMaster = I2cMaster;
> > + break;
> > + } while (TRUE);
> > +
> > + return;
> > +
> > +}
> > +
> > +/**
> > + This is the declaration of an EFI image entry point. This can be the entry point to an application
> > + written to this specification, an EFI boot service driver.
> > +
> > + @param ImageHandle Handle that identifies the loaded image.
> > + @param SystemTable System Table for this image.
> > +
> > + @retval EFI_SUCCESS The operation completed successfully.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +LibRtcInitialize (
> > + IN EFI_HANDLE ImageHandle,
> > + IN EFI_SYSTEM_TABLE *SystemTable
> > + )
> > +{
> > + EFI_STATUS Status;
> > + UINTN BufferSize;
> > +
> > + //
> > + // Find the handle that marks the controller
> > + // that will provide the I2C master protocol.
> > + //
> > + BufferSize = sizeof (EFI_HANDLE);
> > + Status = gBS->LocateHandle (
> > + ByProtocol,
> > + &gDs3232RealTimeClockLibI2cMasterProtocolGuid,
> > + NULL,
> > + &BufferSize,
> > + &mI2cMasterHandle
> > + );
> > + ASSERT_EFI_ERROR (Status);
> > +
> > + //
> > + // Register a protocol registration notification callback on the driver
> > + // binding protocol so we can attempt to connect our I2C master to it
> > + // as soon as it appears.
> > + //
> > + EfiCreateProtocolNotifyEvent (
> > + &gEfiI2cMasterProtocolGuid,
> > + TPL_CALLBACK,
> > + I2cDriverRegistrationEvent,
> > + NULL,
> > + &mDriverEventRegistration);
> > +
> > + return EFI_SUCCESS;
> > +}
> > diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> > new file mode 100644
> > index 0000000..a0033a2
> > --- /dev/null
> > +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> > @@ -0,0 +1,34 @@
> > +#/** @file
> > +#
> > +# Copyright 2017 NXP
> > +#
> > +# This program and the accompanying materials
> > +# are licensed and made available under the terms and conditions of the BSD License
> > +# which accompanies this distribution. The full text of the license may be found at
> > +# http://opensource.org/licenses/bsd-license.php
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> > +#
> > +#**/
> > +
> > +[Defines]
> > + DEC_SPECIFICATION = 0x0001001A
> > + PACKAGE_NAME = Ds3232RtcLib
> > + PACKAGE_GUID = 0b4192f7-e404-4019-b2e5-1e6004da3313
> > + PACKAGE_VERSION = 0.1
> > +
> > +[Guids]
> > + gDs3232RtcLibTokenSpaceGuid = { 0x7960fc51, 0x0832, 0x4f0b, { 0xb4, 0x22, 0x53, 0x87, 0x03, 0xaa, 0x85, 0xda }}
> > +
> > +[Protocols]
> > + gDs3232RealTimeClockLibI2cMasterProtocolGuid = { 0xa17eb2ee, 0xcadc, 0x40f1, { 0x8a, 0x45, 0x4d, 0x5a, 0xf3, 0xd6, 0xce, 0x53 }}
> > +
> > +[PcdsFixedAtBuild]
> > + gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001
> > + gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002
> > + gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed|FALSE|BOOLEAN|0x00000003
> > + gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress|0|UINT8|0x00000004
> > + gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset|0|UINT8|0x00000005
> > + gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0|UINT8|0x00000006
> > + gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0|UINT8|0x00000007
> > diff --git a/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> > new file mode 100644
> > index 0000000..95664c1
> > --- /dev/null
> > +++ b/Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> > @@ -0,0 +1,50 @@
> > +# @Ds3232RtcLib.inf
> > +#
> > +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
> > +# Copyright 2017 NXP
> > +#
> > +# This program and the accompanying materials
> > +# are licensed and made available under the terms and conditions of the BSD License
> > +# which accompanies this distribution. The full text of the license may be found at
> > +# http://opensource.org/licenses/bsd-license.php
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> > +#
> > +#
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001A
> > + BASE_NAME = Ds3232RtcLib
> > + FILE_GUID = 97f1f2c2-51e1-47ad-9660-70b33da1fe71
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = RealTimeClockLib
> > +
> > +[Sources.common]
> > + Ds3232RtcLib.c
> > +
> > +[Packages]
> > + EmbeddedPkg/EmbeddedPkg.dec
> > + MdePkg/MdePkg.dec
> > + Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.dec
> > +
> > +[LibraryClasses]
> > + DebugLib
> > + UefiBootServicesTableLib
> > + UefiLib
> > +
> > +[Protocols]
> > + gEfiI2cMasterProtocolGuid ## CONSUMES
> > + gDs3232RealTimeClockLibI2cMasterProtocolGuid ## CONSUMES
> > +
> > +[FixedPcd]
> > + gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress
> > + gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency
> > + gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed
> > + gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress
> > + gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset
> > + gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue
> > + gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue
> > +
> > +[Depex]
> > + gDs3232RealTimeClockLibI2cMasterProtocolGuid
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 29/41] Compilation : Add the fdf, dsc and dec files
2018-11-28 15:01 ` [PATCH edk2-platforms 29/41] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
@ 2018-12-21 10:17 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 10:17 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Wasim Khan
On Wed, Nov 28, 2018 at 08:31:43PM +0530, Meenakshi Aggarwal wrote:
> The firmware device, description and declaration files for LS2088 board
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec | 29 ++++
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 96 +++++++++++++
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 200 +++++++++++++++++++++++++++
No 'Pkg' for dsc/fdf.
> Silicon/NXP/LS2088A/LS2088A.dec | 22 +++
Whereas this .dec should probably be a Pkg.
> Silicon/NXP/LS2088A/LS2088A.dsc.inc | 71 ++++++++++
> Silicon/NXP/NxpQoriqLs.dec | 13 ++
And this one (although I didn't spot this when added).
> 6 files changed, 431 insertions(+)
> create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
> create mode 100755 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> create mode 100644 Silicon/NXP/LS2088A/LS2088A.dec
> create mode 100644 Silicon/NXP/LS2088A/LS2088A.dsc.inc
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
> new file mode 100644
> index 0000000..93d2e5a
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
> @@ -0,0 +1,29 @@
> +# LS2088aRdbPkg.dec
> +# LS2088a board package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + PACKAGE_NAME = LS2088aRdbPkg
> + PACKAGE_GUID = 474e0c59-5f77-4060-82dd-9025ee4f4939
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +# Supported Module Types:
> +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
If needed, this file should have been added with the files added to
that directory.
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> new file mode 100755
> index 0000000..465c59e
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> @@ -0,0 +1,96 @@
> +# LS2088aRdbPkg.dsc
> +#
> +# LS2088ARDB Board package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + #
> + # Defines for default states. These can be changed on the command line.
> + # -D FLAG=VALUE
> + #
> + PLATFORM_NAME = LS2088aRdbPkg
Drop the 'Pkg'.
> + PLATFORM_GUID = be06d8bc-05eb-44d6-b39f-191e93617ebd
> + OUTPUT_DIRECTORY = Build/LS2088aRdbPkg
> + FLASH_DEFINITION = Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
Please use $(PLATFORM_NAME) instead of repeating the string in the two
lines above.
> + DEFINE MC_HIGH_MEM = TRUE
> +
> +!include Platform/NXP/NxpQoriqLs.dsc.inc
> +!include Silicon/NXP/LS2088A/LS2088A.dsc.inc
> +
> +[LibraryClasses.common]
> + SocLib|Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
> + ArmPlatformLib|Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> + IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> + RealTimeClockLib|Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> +
> +[PcdsFixedAtBuild.common]
> +
> +!if $(MC_HIGH_MEM) == TRUE # Management Complex loaded at the end of DDR2
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000 # Actual base address (0x0080000000)
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000 # 2 GB
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x80000000 # 2GB (PcdDpaa2McRamSize must be 512MB aligned)
> + gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|1
> + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0080000000 # Actual base
> + gArmTokenSpaceGuid.PcdSystemMemorySize|0x0080000000 # 2G
> +!else
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x00A0000000 # Actual base address (0x0080000000) + 512MB
> + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0060000000 # 2GB - 512MB
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x20000000 # 512MB (Fixed)
> + gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|0
> + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00A0000000 # Actual base + 512MB
> + gArmTokenSpaceGuid.PcdSystemMemorySize|0x0060000000 # 2G - 512MB
> +!endif
> + gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x380000000 # 14 GB
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x8080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x8800000000 # 512 GB
> + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
> +
> + #
> + # Board Specific Pcds
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0600
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x2
> + gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|133333333
> +
> + #
> + # RTC Pcds
> + #
> + gDs3232RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
> + gDs3232RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
> + gDs3232RtcLibTokenSpaceGuid.PcdIsRtcDeviceMuxed|TRUE
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxDeviceAddress|0x75
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxControlRegOffset|0x09
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0x09
> + gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0x08
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> + #
> + # Architectural Protocols
> + #
> + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
> + Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> + Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> new file mode 100644
> index 0000000..b526be1
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> @@ -0,0 +1,200 @@
> +# LS2088aRdbPkg.fdf
> +#
> +# FLASH layout file for LS2088a board.
> +#
> +# Copyright (c) 2016, Freescale Ltd. All rights reserved.
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +################################################################################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into the Flash Device Image. Each FD section
> +# defines one flash "device" image. A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash" image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +################################################################################
> +
> +[FD.LS2088aRdb_EFI]
> +BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
> +Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
> +ErasePolarity = 1
> +BlockSize = 0x1
> +NumBlocks = 0x00100000
> +
> +################################################################################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +#
> +################################################################################
> +0x00000000|0x00100000
> +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> +FV = FVMAIN_COMPACT
> +
> +!include Platform/NXP/FVRules.fdf.inc
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed within a flash
> +# device file. This section also defines order the components and modules are positioned
> +# within the image. The [FV] section consists of define statements, set statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
> +BlockSize = 0x1
> +NumBlocks = 0 # This FV gets compressed so make it just big enough
> +FvAlignment = 8 # FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF MdeModulePkg/Core/Dxe/DxeMain.inf
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +
> + #
> + # PI DXE Drivers producing Architectural Protocols (EFI Services)
> + #
> + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> +
> + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
> + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> +
> + INF Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> +
> + INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> +
> + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> +
> + #
> + # Multiple Console IO support
> + #
> + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
> +
> + #
> + # Network modules
> + #
Adjust for deprectaed modules.
> + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
> + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
> + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
> + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
> + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
> + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
> + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
> +!if $(NETWORK_IP6_ENABLE) == TRUE
> + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + INF NetworkPkg/TcpDxe/TcpDxe.inf
> + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> +!else
> + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
> +!endif
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + INF FatPkg/FatPei/FatPei.inf
> + INF FatPkg/EnhancedFatDxe/Fat.inf
> +
> + #
> + # UEFI application (Shell Embedded Boot Loader)
> + #
> + INF ShellPkg/Application/Shell/Shell.inf
> +
> + #
> + # Bds
> + #
> + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + INF MdeModulePkg/Application/UiApp/UiApp.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment = 8
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF ArmPlatformPkg/PrePi/PeiUniCore.inf
> +
> + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> + }
> +
> diff --git a/Silicon/NXP/LS2088A/LS2088A.dec b/Silicon/NXP/LS2088A/LS2088A.dec
> new file mode 100644
> index 0000000..8539c63
> --- /dev/null
> +++ b/Silicon/NXP/LS2088A/LS2088A.dec
> @@ -0,0 +1,22 @@
> +# LS2088A.dec
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials are licensed and made available under
> +# the terms and conditions of the BSD License which accompanies this distribution.
> +# The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x00010005
1A
> +
> +[Guids.common]
> + gNxpLs2088ATokenSpaceGuid = {0xaf770da7, 0x264c, 0x4857, {0x9d, 0xed, 0x56, 0x5e, 0x2c, 0x08, 0x7e, 0x26}}
> +
> +[Includes]
> + Include
But again, this file should have been added when files were added to
the Include directory.
/
Leif
> diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc.inc b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
> new file mode 100644
> index 0000000..8f7dbb5
> --- /dev/null
> +++ b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
> @@ -0,0 +1,71 @@
> +# LS2088A.dsc
> +# LS2088A Soc package.
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +[PcdsDynamicDefault.common]
> +
> + #
> + # ARM General Interrupt Controller
> + gArmTokenSpaceGuid.PcdGicDistributorBase|0x6000000
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x6100000
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x00
> +
> +[PcdsFixedAtBuild.common]
> +
> + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0C000000
> + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|266666666 #266MHz
> +
> + #
> + # ARM L2x0 PCDs
> + gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x10900000
> +
> + #
> + # CCSR Address Space and other attached Memories
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x1370000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x30000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x10000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x510000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0xF0000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x3EEA
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x20000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x10000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x400000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x10000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x2000000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000 # 32 GB
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x2800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 # 32 GB
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x3000000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 # 32 GB
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x3800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x800000000 # 32 GB
> + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x8080000000 # Extended System Memory Base
> + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0380000000 # 14GB Extended System Memory Size
> + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x3100000
> + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x10000
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x1E00000
> + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x02140000
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02000000
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> +
> +##
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index 159ea65..da148b7 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -91,6 +91,18 @@
> gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
>
> #
> + # DPAA2 PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McRamSize|0x0|UINT64|0x000001E0
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalBaseAddr|0x0|UINT64|0x000001E1
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2McPortalSize|0x0|UINT64|0x000001E2
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsBaseAddr|0x0|UINT64|0x000001E3
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2NiPortalsSize|0x0|UINT64|0x000001E4
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsBaseAddr|0x0|UINT64|0x000001E5
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalSize|0x0|UINT64|0x000001E6
> + gNxpQoriqLsTokenSpaceGuid.PcdDpaa2QBmanPortalsCacheSize|0x0|UINT64|0x000001E7
> +
> + #
> # NV Pcd
> #
> gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
> @@ -102,6 +114,7 @@
> gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
> gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
> gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE|BOOLEAN|0x00000252
> + gNxpQoriqLsTokenSpaceGuid.PcdMcHighMemSupport|FALSE|BOOLEAN|0x00000253
>
> #
> # Clock PCDs
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 30/41] Platform/NXP: LS2088A RDB Board Library
2018-11-28 15:01 ` [PATCH edk2-platforms 30/41] Platform/NXP: LS2088A RDB Board Library Meenakshi Aggarwal
@ 2018-12-21 10:20 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 10:20 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Wasim Khan
On Wed, Nov 28, 2018 at 08:31:44PM +0530, Meenakshi Aggarwal wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
>
> Library to provide board specific timings for LS2088ARDB
> board with interfacing to IFC controller for accessing
Expand IFC in commit message.
> NOR, NAND and FPGA.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> .../NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h | 114 +++++++++++++++++++++
> .../NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c | 69 +++++++++++++
> .../LS2088aRdbPkg/Library/BoardLib/BoardLib.inf | 28 +++++
> 3 files changed, 211 insertions(+)
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h b/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
> new file mode 100644
> index 0000000..174a242
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Include/IfcBoardSpecific.h
Nxp prefix?
> @@ -0,0 +1,114 @@
> +/** IfcBoardSpecificLib.h
> +
> + IFC Flash Board Specific Macros and structure
> +
> + Copyright 2017-2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +#ifndef __IFC__BOARD_SPECIFIC_H__
> +#define __IFC__BOARD_SPECIFIC_H__
NXP_ prefix?
> +
> +#include <Ifc.h>
> +
> +// On board flash support
> +#define IFC_NAND_BUF_BASE 0x530000000ULL
> +
> +// On board Inegrated flash Controller chip select configuration
> +#define IFC_NOR_CS IFC_CS0
> +#define IFC_NAND_CS IFC_CS2
> +#define IFC_FPGA_CS IFC_CS3
> +
> +
> +/* board-specific NAND timing */
> +#define NAND_FTIM0 (IFC_FTIM0_NAND_TCCST(0x0e) | \
> + IFC_FTIM0_NAND_TWP(0x30) | \
> + IFC_FTIM0_NAND_TWCHT(0x0e) | \
> + IFC_FTIM0_NAND_TWH(0x14))
> +
> +#define NAND_FTIM1 (IFC_FTIM1_NAND_TADLE(0x64) | \
> + IFC_FTIM1_NAND_TWBE(0xab) | \
> + IFC_FTIM1_NAND_TRR(0x1c) | \
> + IFC_FTIM1_NAND_TRP(0x30))
> +
> +#define NAND_FTIM2 (IFC_FTIM2_NAND_TRAD(0x1e) | \
> + IFC_FTIM2_NAND_TREH(0x14) | \
> + IFC_FTIM2_NAND_TWHRE(0x3c))
> +
> +#define NAND_FTIM3 0x0
> +
> +#define IFC_NAND_BASE_PHYS 0x30000000
> +#define NAND_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NAND_BASE_PHYS) \
> + | IFC_CSPR_PORT_SIZE_8 \
> + | IFC_CSPR_MSEL_NAND \
> + | IFC_CSPR_V)
> +
> +#define NAND_CSPR_EXT 0x0
> +#define NAND_AMASK 0xFFFF0000
> +
> +#define NAND_CSOR (IFC_CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
> + | IFC_CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
> + | IFC_CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
> + | IFC_CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
> + | IFC_CSOR_NAND_PGS_4K /* Page Size = 4K */ \
> + | IFC_CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
> + | IFC_CSOR_NAND_PB(7)) /* 2^7 Pages Per Block */
> +
> +// board-specific NOR timing
> +#define NOR_FTIM0 (IFC_FTIM0_NOR_TACSE(0x4) | \
> + IFC_FTIM0_NOR_TEADC(0x5) | \
> + IFC_FTIM0_NOR_TEAHC(0x5))
> +
> +#define NOR_FTIM1 (IFC_FTIM1_NOR_TACO(0x35) | \
> + IFC_FTIM1_NOR_TRAD_NOR(0x1a) | \
> + IFC_FTIM1_NOR_TSEQRAD_NOR(0x13))
> +
> +#define NOR_FTIM2 (IFC_FTIM2_NOR_TCS(0x4) | \
> + IFC_FTIM2_NOR_TCH(0x4) | \
> + IFC_FTIM2_NOR_TWPH(0xe) | \
> + IFC_FTIM2_NOR_TWP(0x1c))
> +
> +#define NOR_FTIM3 0x04000000
> +
> +#define IFC_FLASH_BASE_PHYS 0x80000000
> +#define NOR_CSPR (IFC_CSPR_PHYS_ADDR(IFC_FLASH_BASE_PHYS) \
> + | IFC_CSPR_PORT_SIZE_16 \
> + | IFC_CSPR_MSEL_NOR \
> + | IFC_CSPR_V)
> +
> +#define NOR_CSPR_EXT 0x0
> +#define NOR_AMASK IFC_AMASK(128*1024*1024)
> +#define NOR_CSOR IFC_CSOR_NOR_ADM_SHIFT(12)
> +
> +// board-specific fpga timing
> +#define FPGA_BASE_PHYS 0x20000000
> +#define FPGA_CSPR_EXT 0x0
> +#define FPGA_CSPR (IFC_CSPR_PHYS_ADDR(FPGA_BASE_PHYS) | \
> + IFC_CSPR_PORT_SIZE_8 | \
> + IFC_CSPR_MSEL_GPCM | \
> + IFC_CSPR_V)
> +
> +#define FPGA_AMASK IFC_AMASK(64 * 1024)
> +#define FPGA_CSOR IFC_CSOR_NOR_ADM_SHIFT(12)
> +
> +#define FPGA_FTIM0 (IFC_FTIM0_GPCM_TACSE(0xe) | \
> + IFC_FTIM0_GPCM_TEADC(0xe) | \
> + IFC_FTIM0_GPCM_TEAHC(0xe))
> +
> +#define FPGA_FTIM1 (IFC_FTIM1_GPCM_TACO(0xff) | \
> + IFC_FTIM1_GPCM_TRAD(0x3f))
> +
> +#define FPGA_FTIM2 (IFC_FTIM2_GPCM_TCS(0xf) | \
> + IFC_FTIM2_GPCM_TCH(0xf) | \
> + IFC_FTIM2_GPCM_TWP(0x3e))
> +
> +#define FPGA_FTIM3 0x0
> +
> +#endif //__IFC__BOARD_SPECIFIC_H__
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
> new file mode 100644
> index 0000000..936b789
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.c
> @@ -0,0 +1,69 @@
> +/** @file
> +
> + Copyright 2017-2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <IfcBoardSpecific.h>
> +
> +VOID
> +GetIfcNorFlashTimings (
> + IN IFC_TIMINGS * NorIfcTimings
> + )
> +{
> + NorIfcTimings->Ftim[0] = NOR_FTIM0;
> + NorIfcTimings->Ftim[1] = NOR_FTIM1;
> + NorIfcTimings->Ftim[2] = NOR_FTIM2;
> + NorIfcTimings->Ftim[3] = NOR_FTIM3;
> + NorIfcTimings->Cspr = NOR_CSPR;
> + NorIfcTimings->CsprExt = NOR_CSPR_EXT;
> + NorIfcTimings->Amask = NOR_AMASK;
> + NorIfcTimings->Csor = NOR_CSOR;
> + NorIfcTimings->CS = IFC_NOR_CS;
> +
> + return ;
Drop space before ;.
> +}
> +
> +VOID
> +GetIfcFpgaTimings (
> + IN IFC_TIMINGS *FpgaIfcTimings
> + )
> +{
> + FpgaIfcTimings->Ftim[0] = FPGA_FTIM0;
> + FpgaIfcTimings->Ftim[1] = FPGA_FTIM1;
> + FpgaIfcTimings->Ftim[2] = FPGA_FTIM2;
> + FpgaIfcTimings->Ftim[3] = FPGA_FTIM3;
> + FpgaIfcTimings->Cspr = FPGA_CSPR;
> + FpgaIfcTimings->CsprExt = FPGA_CSPR_EXT;
> + FpgaIfcTimings->Amask = FPGA_AMASK;
> + FpgaIfcTimings->Csor = FPGA_CSOR;
> + FpgaIfcTimings->CS = IFC_FPGA_CS;
> +
> + return;
> +}
> +
> +VOID
> +GetIfcNandFlashTimings (
> + IN IFC_TIMINGS * NandIfcTimings
> + )
> +{
> + NandIfcTimings->Ftim[0] = NAND_FTIM0;
> + NandIfcTimings->Ftim[1] = NAND_FTIM1;
> + NandIfcTimings->Ftim[2] = NAND_FTIM2;
> + NandIfcTimings->Ftim[3] = NAND_FTIM3;
> + NandIfcTimings->Cspr = NAND_CSPR;
> + NandIfcTimings->CsprExt = NAND_CSPR_EXT;
> + NandIfcTimings->Amask = NAND_AMASK;
> + NandIfcTimings->Csor = NAND_CSOR;
> + NandIfcTimings->CS = IFC_NAND_CS;
> +
> + return;
> +}
On the whole, this file looks an awful lot like it could use a single
implementation for all platforms, with platform-specific include
files. Is that doable?
/
Leif
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
> new file mode 100644
> index 0000000..5df84b1
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
> @@ -0,0 +1,28 @@
> +# @file
> +#
> +# Copyright 2017-2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = BoardLib
> + FILE_GUID = 13eacf2a-4338-48f4-88de-6ce4618e1a53
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = BoardLib
> +
> +[Sources.common]
> + BoardLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 31/41] Platform/NXP: LS2088 RDB Board FPGA library
2018-11-28 15:01 ` [PATCH edk2-platforms 31/41] Platform/NXP: LS2088 RDB Board FPGA library Meenakshi Aggarwal
@ 2018-12-21 10:22 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 10:22 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Wasim Khan
On Wed, Nov 28, 2018 at 08:31:45PM +0530, Meenakshi Aggarwal wrote:
> From: Wasim Khan <wasim.khan@nxp.com>
>
> Library to provide functions for accessing FPGA
> on LS2088ARDB board.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> ---
> .../NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h | 166 +++++++++++++++++++++
> .../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c | 115 ++++++++++++++
> .../NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf | 31 ++++
> 3 files changed, 312 insertions(+)
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
> create mode 100644 Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h b/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
> new file mode 100644
> index 0000000..84d1f02
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Include/Library/FpgaLib.h
> @@ -0,0 +1,166 @@
> +/** FpgaLib.h
> +* Header defining the LS2088a Fpga specific constants (Base addresses, sizes, flags)
> +*
> +* Copyright 2017-2018 NXP
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __LS2088A_FPGA_H__
> +#define __LS2088A_FPGA_H__
> +
> +typedef enum {
> + CLK_66,
> + CLK_83,
> + CLK_100,
> + CLK_125,
> + CLK_133
CamelCase names for enum members.
> +} SYSTEM_CLOCK;
> +
> +/*
> + * FPGA register set of LS2088ARDB board-specific.
> + */
> +typedef struct {
> + UINT8 Id; // ID value uniquely identifying each QorIQ board type
> + UINT8 Arch; // Board Version
> + UINT8 Ver; // FPGA Version
> + UINT8 Model; // Programming Model
> + UINT8 Minor; // Minor Revision Number
> + UINT8 CtlSys;
> + UINT8 Aux;
> + UINT8 ClkSpd;
> + UINT8 StatDut;
> + UINT8 StatSys;
> + UINT8 StatAlrm;
> + UINT8 Present;
> + UINT8 Present2;
> + UINT8 RcwCtl;
> + UINT8 CtlLed;
> + UINT8 I2cBlk;
> + UINT8 RcfgCtl;
> + UINT8 RcfgSt;
> + UINT8 DcmAd;
> + UINT8 DcmDa;
> + UINT8 Dcmd;
> + UINT8 Dmsg;
> + UINT8 Gdc;
> + UINT8 Gdd;
> + UINT8 Dmack;
> + UINT8 Res1[6];
Please write out Reserved, throughout.
> + UINT8 Watch;
> + UINT8 PwrCtl[2];
> + UINT8 Res2[2];
> + UINT8 PwrStat[4];
> + UINT8 Res3[8];
> + UINT8 ClkSpd2[2];
> + UINT8 Res4[2];
> + UINT8 Sclk[3];
> + UINT8 Res5;
> + UINT8 Dclk[3];
> + UINT8 Res6;
> + UINT8 ClkDspd[3];
> + UINT8 Res7;
> + UINT8 RstCtl;
> + UINT8 RstStat;
> + UINT8 RstRsn;
> + UINT8 RstFrc[2];
> + UINT8 Res8[11];
> + UINT8 BrdCfg[16];
> + UINT8 DutCfg[16];
> + UINT8 RcwAd[2];
> + UINT8 RcwData;
> + UINT8 Res9[5];
> + UINT8 PostCtl;
> + UINT8 PostStat;
> + UINT8 PostDat[2];
> + UINT8 Pid[4];
> + UINT8 GpioIo[4];
> + UINT8 GpioDir[4];
> + UINT8 Res10[20];
> + UINT8 RjtagCtl;
> + UINT8 RjtagDat;
> + UINT8 Res11[2];
> + UINT8 TrigSrc[4];
> + UINT8 TrigDst[4];
> + UINT8 TrigStat;
> + UINT8 Res12[3];
> + UINT8 TrigCtr[4];
> + UINT8 Res13[16];
> + UINT8 ClkFreq[6];
> + UINT8 ResC6[8];
> + UINT8 ClkBase[2];
> + UINT8 ResD0[8];
> + UINT8 Cms[2];
> + UINT8 ResC0[6];
> + UINT8 Aux2[4];
> + UINT8 Res14[10];
> + UINT8 AuxAd;
> + UINT8 AuxDa;
> + UINT8 Res15[16];
> +} FPGA_REG_SET;
> +
> +/**
> + Function to read FPGA register.
> +**/
> +UINT8
> +FpgaRead (
> + UINTN Reg
> + );
> +
> +/**
> + Function to write FPGA register.
> +**/
> +VOID
> +FpgaWrite (
> + UINTN Reg,
> + UINT8 Value
> + );
> +
> +/**
> + Function to initialize FPGA timings.
> +**/
> +VOID
> +FpgaInit (
> + VOID
> + );
> +
> +/**
> + Function to get system clock frequency.
> +**/
> +UINTN
> +GetBoardSysClk (
> + VOID
> + );
> +
> +/**
> + Function to print board personality.
> +**/
> +VOID
> +PrintBoardPersonality (
> + VOID
> + );
> +
> +#define FPGA_BASE_PHYS 0x520000000
> +
> +//SYSCLK
> +#define FPGA_CLK_MASK 0x0F // FPGA Clock Mask
> +#define SYSCLK_66_MHZ 66000000
> +#define SYSCLK_83_MHZ 83000000
> +#define SYSCLK_100_MHZ 100000000
> +#define SYSCLK_125_MHZ 125000000
> +#define SYSCLK_133_MHZ 133000000
> +
> +#define FPGA_VBANK_MASK 0x07
> +#define FPGA_CS_MASK 0x08
> +
> +#define FPGA_READ(Reg) FpgaRead (OFFSET_OF (FPGA_REG_SET, Reg))
> +#define FPGA_WRITE(Reg, Value) FpgaWrite (OFFSET_OF (FPGA_REG_SET, Reg), Value)
> +
> +#endif // __LS2088A_FPGA_H__
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
> new file mode 100644
> index 0000000..8948c21
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.c
> @@ -0,0 +1,115 @@
> +/** @FpgaLib.c
> + Fpga Library for LS2088A-RDB board, containing functions to
> + program and read the Fpga registers.
> +
> + FPGA is connected to IFC Controller and so MMIO APIs are used
> + to read/write FPGA registers
> +
> + Copyright 2017-2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/FpgaLib.h>
> +#include <Library/IoLib.h>
> +
> +/**
> + Function to read FPGA register.
> +
> + @param Reg Register offset of FPGA to read.
> +
> +**/
> +UINT8
> +FpgaRead (
> + IN UINTN Reg
> + )
> +{
> + VOID *Base;
> +
> + Base = (VOID *)FPGA_BASE_PHYS;
> +
> + return MmioRead8 ((UINTN)(Base + Reg));
> +}
> +
> +/**
> + Function to write FPGA register.
> +
> + @param Reg Register offset of FPGA to write.
> + @param Value Value to be written.
> +
> +**/
> +VOID
> +FpgaWrite (
> + IN UINTN Reg,
> + IN UINT8 Value
> + )
> +{
> + VOID *Base;
> +
> + Base = (VOID *)FPGA_BASE_PHYS;
> +
> + MmioWrite8 ((UINTN)(Base + Reg), Value);
> +}
> +
> +/**
> + Function to get board system clock frequency.
> +
> +**/
> +UINTN
> +GetBoardSysClk (
> + VOID
> + )
> +{
> + UINT8 SysclkConf;
> + SysclkConf = FPGA_READ (BrdCfg[1]);
> + switch (SysclkConf & FPGA_CLK_MASK) {
> + case CLK_66:
> + return SYSCLK_66_MHZ;
> + case CLK_83:
> + return SYSCLK_83_MHZ;
> + case CLK_100:
> + return SYSCLK_100_MHZ;
> + case CLK_125:
> + return SYSCLK_125_MHZ;
> + case CLK_133:
> + return SYSCLK_133_MHZ;
> + }
> + return SYSCLK_100_MHZ;
> +}
> +
> +/**
> + Function to print board personality.
> +
> +**/
> +VOID
> +PrintBoardPersonality (
> + VOID
> + )
> +{
> + UINT8 SwitchConf;
> + SwitchConf = FPGA_READ (Arch);
> +
> + DEBUG ((DEBUG_INFO, "Board Arch: V%d, ", SwitchConf >> 4));
> + DEBUG ((DEBUG_INFO, "Board version: %c, boot from ",
> + (SwitchConf & 0xf) + 'A'));
> +
> + SwitchConf = FPGA_READ (BrdCfg[0]);
> +
> + if (SwitchConf & FPGA_CS_MASK)
> + DEBUG ((DEBUG_INFO, "NAND\n"));
> + else
> + DEBUG ((DEBUG_INFO, "vBank: %d\n", (SwitchConf & FPGA_VBANK_MASK)));
> +
> + DEBUG ((DEBUG_INFO, "FPGA: v%d.%d\n", FPGA_READ (Ver),
> + FPGA_READ (Minor)));
> +}
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
> new file mode 100644
> index 0000000..e70723a
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
> @@ -0,0 +1,31 @@
> +# @FpgaLib.inf
> +#
> +# Copyright 2017-2018 NXP
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001000A
1A
/
Leif
> + BASE_NAME = FpgaLib
> + FILE_GUID = dd2ce2f3-f219-4b57-82fd-f1ff8ae8bf5a
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = FpgaLib
> +
> +[Sources.common]
> + FpgaLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + IoLib
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 32/41] LS2088 : Enable support of FpgaLib
2018-11-28 15:01 ` [PATCH edk2-platforms 32/41] LS2088 : Enable support of FpgaLib Meenakshi Aggarwal
@ 2018-12-21 10:23 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 10:23 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Wasim Khan
On Wed, Nov 28, 2018 at 08:31:46PM +0530, Meenakshi Aggarwal wrote:
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 3 +++
> Silicon/NXP/Include/Chassis3/Soc.h | 1 -
> Silicon/NXP/LS2088A/LS2088A.dsc.inc | 1 +
> Silicon/NXP/Library/SocLib/Chassis3/Soc.c | 13 ++++++++++++-
> Silicon/NXP/Library/SocLib/LS2088aSocLib.inf | 2 ++
> 5 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> index 465c59e..76d51a2 100755
> --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> @@ -39,6 +39,9 @@
> SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> RealTimeClockLib|Silicon/Maxim/Library/Ds3232RtcLib/Ds3232RtcLib.inf
> + IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
> + BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
> + FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
>
> [PcdsFixedAtBuild.common]
>
> diff --git a/Silicon/NXP/Include/Chassis3/Soc.h b/Silicon/NXP/Include/Chassis3/Soc.h
> index 8d967e7..0dd9eee 100644
> --- a/Silicon/NXP/Include/Chassis3/Soc.h
> +++ b/Silicon/NXP/Include/Chassis3/Soc.h
> @@ -22,7 +22,6 @@
> #define FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } /* LS208x */
> #define TP_CLUSTER_EOC_MASK 0x80000000 /* Mask for End of clusters */
> #define NUM_CC_PLLS 6
> -#define CLK_FREQ 100000000
> #define MAX_CPUS 16
> #define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) != TP_CLUSTER_EOC_MASK)
>
> diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc.inc b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
> index 8f7dbb5..2cff40f 100644
> --- a/Silicon/NXP/LS2088A/LS2088A.dsc.inc
> +++ b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
> @@ -67,5 +67,6 @@
> gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02000000
> gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000
>
> ##
> diff --git a/Silicon/NXP/Library/SocLib/Chassis3/Soc.c b/Silicon/NXP/Library/SocLib/Chassis3/Soc.c
> index 0fc92f4..d334bb7 100644
> --- a/Silicon/NXP/Library/SocLib/Chassis3/Soc.c
> +++ b/Silicon/NXP/Library/SocLib/Chassis3/Soc.c
> @@ -19,11 +19,15 @@
> #include <Library/BaseLib.h>
> #include <Library/BaseMemoryLib.h>
> #include <Library/DebugLib.h>
> +#include <Library/IfcLib.h>
> #include <Library/IoLib.h>
> #include <Library/PcdLib.h>
> #include <Library/PrintLib.h>
> #include <Library/SerialPortLib.h>
>
> +extern VOID PrintBoardPersonality (VOID);
> +extern UINTN GetBoardSysClk (VOID);
Please import these through an include file.
/
Leif
> +
> VOID
> GetSysInfo (
> OUT SYS_INFO *PtrSysInfo
> @@ -82,7 +86,7 @@ GetSysInfo (
>
> GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
> - SysClk = CLK_FREQ;
> + SysClk = GetBoardSysClk ();
>
> PtrSysInfo->FreqSystemBus = SysClk;
> PtrSysInfo->FreqDdrBus = PcdGet64 (PcdDdrClk);
> @@ -151,6 +155,8 @@ SocInit (
> //
> SmmuInit ();
>
> + IfcInit ();
> +
> //
> // Initialize the Serial Port.
> // Early serial port initialization is required to print RCW,
> @@ -177,4 +183,9 @@ SocInit (
> // Print Soc Personality information
> //
> PrintSoc ();
> +
> + //
> + // Print Board Personality information
> + //
> + PrintBoardPersonality ();
> }
> diff --git a/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf b/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
> index 3d9237d..9547f5a 100644
> --- a/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
> +++ b/Silicon/NXP/Library/SocLib/LS2088aSocLib.inf
> @@ -29,6 +29,8 @@
> [LibraryClasses]
> BaseLib
> DebugLib
> + FpgaLib
> + IfcLib
> IoAccessLib
> SerialPortLib
>
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 33/41] LS2088ARDB: Enable NOR driver and Runtime Services
2018-11-28 15:01 ` [PATCH edk2-platforms 33/41] LS2088ARDB: Enable NOR driver and Runtime Services Meenakshi Aggarwal
@ 2018-12-21 10:24 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 10:24 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Wasim Khan
On Wed, Nov 28, 2018 at 08:31:47PM +0530, Meenakshi Aggarwal wrote:
> Enable NOR driver and Runtime Services for LS2088ARDB Platform
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 15 ++++-
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 6 +-
> Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc | 99 ++++++++++++++++++++++++++++
> 3 files changed, 118 insertions(+), 2 deletions(-)
> create mode 100644 Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> index 76d51a2..e788581 100755
> --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> @@ -42,6 +42,7 @@
> IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
> BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
> FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
> + NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
>
> [PcdsFixedAtBuild.common]
>
> @@ -84,6 +85,13 @@
> gDs3232RtcLibTokenSpaceGuid.PcdMuxRtcChannelValue|0x09
> gDs3232RtcLibTokenSpaceGuid.PcdMuxDefaultChannelValue|0x08
>
> + #
> + # NV Storage PCDs
> + #
> + gArmTokenSpaceGuid.PcdVFPEnabled|1
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x580000000
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x580300000
> +
> ################################################################################
> #
> # Components Section - list of all EDK II Modules needed by this Platform
> @@ -93,7 +101,12 @@
> #
> # Architectural Protocols
> #
> - MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf{
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
> + }
> + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> + Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> index b526be1..61bb160 100644
> --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> @@ -55,6 +55,7 @@ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> FV = FVMAIN_COMPACT
>
> !include Platform/NXP/FVRules.fdf.inc
> +!include VarStore.fdf.inc
> ################################################################################
> #
> # FV Section
> @@ -103,7 +104,8 @@ READ_LOCK_STATUS = TRUE
> INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> - INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
>
> INF Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> @@ -124,6 +126,8 @@ READ_LOCK_STATUS = TRUE
> INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
>
> + INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> +
> #
> # Network modules
> #
> diff --git a/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
> new file mode 100644
> index 0000000..7d35042
> --- /dev/null
> +++ b/Platform/NXP/LS2088aRdbPkg/VarStore.fdf.inc
> @@ -0,0 +1,99 @@
> +## @file
> +# FDF include file with FD definition that defines an empty variable store.
> +#
> +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
> +# Copyright (C) 2014, Red Hat, Inc.
> +# Copyright (c) 2016, Linaro, Ltd. All rights reserved.
> +# Copyright (c) 2016, Freescale Semiconductor. All rights reserved.
> +# Copyright 2017-2018 NXP.
> +#
> +# This program and the accompanying materials are licensed and made available
> +# under the terms and conditions of the BSD License which accompanies this
> +# distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> +# IMPLIED.
> +#
> +##
> +
> +[FD.LS2088aRdbNv_EFI]
> +
> +BaseAddress = 0x580300000|gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase #The base address of the FLASH device
> +Size = 0x000C0000|gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize #The size in bytes of the FLASH device
> +ErasePolarity = 1
> +BlockSize = 0x1
> +NumBlocks = 0xC0000
> +
> +#
> +# Place NV Storage just above Platform Data Base
> +#
> +DEFINE NVRAM_AREA_VARIABLE_BASE = 0x00000000
> +DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x00040000
> +DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)
> +DEFINE FTW_WORKING_SIZE = 0x00040000
> +DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)
> +DEFINE FTW_SPARE_SIZE = 0x00040000
> +
> +#############################################################################
> +# LS2088ARDB NVRAM Area
> +# LS2088ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare
> +#############################################################################
> +
> +
> +$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +#NV_VARIABLE_STORE
> +DATA = {
> + ## This is the EFI_FIRMWARE_VOLUME_HEADER
> + # ZeroVector []
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + # FileSystemGuid: gEfiSystemNvDataFvGuid =
> + # { 0xFFF12B8D, 0x7696, 0x4C8B,
> + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
> + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
> + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
> + # FvLength: 0xC0000
> + 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
> + # Signature "_FVH" # Attributes
> + 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00,
> + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
> + 0x48, 0x00, 0xFA, 0xF5, 0x00, 0x00, 0x00, 0x02,
> + # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
> + 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
> + # Blockmap[1]: End
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + ## This is the VARIABLE_STORE_HEADER
> + # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
> + # Signature: gEfiAuthenticatedVariableGuid =
> + # { 0xaaf32c78, 0x947b, 0x439a,
> + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
> + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
> + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
> + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
> + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3ffb8
> + # This can speed up the Variable Dispatch a bit.
> + 0xB8, 0xFF, 0x03, 0x00,
> + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
> + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +#NV_FTW_WORKING
> +DATA = {
> + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
> + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
> + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
> + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
> + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
> + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
> + # WriteQueueSize: UINT64
> + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +#NV_FTW_SPARE
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 34/41] Silicon/NXP: Implement PciSegmentLib to support multiple RCs
2018-11-28 15:01 ` [PATCH edk2-platforms 34/41] Silicon/NXP: Implement PciSegmentLib to support multiple RCs Meenakshi Aggarwal
@ 2018-12-21 10:44 ` Ard Biesheuvel
2018-12-21 14:01 ` Leif Lindholm
1 sibling, 0 replies; 254+ messages in thread
From: Ard Biesheuvel @ 2018-12-21 10:44 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org,
Udit Kumar, Varun Sethi, Vabhav
On Wed, 28 Nov 2018 at 10:16, Meenakshi Aggarwal
<meenakshi.aggarwal@nxp.com> wrote:
>
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Multiple root complex support is not provided by standard library
> PciLib/PciExpressLib/PciSegmentLib, Reimplementing it and provide
> function for reading/writing into PCIe configuration Space.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/NxpPcie.h | 146 +++++
> Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 611 +++++++++++++++++++++
> .../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 41 ++
> 3 files changed, 798 insertions(+)
> create mode 100644 Silicon/NXP/Include/NxpPcie.h
> create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>
> diff --git a/Silicon/NXP/Include/NxpPcie.h b/Silicon/NXP/Include/NxpPcie.h
> new file mode 100644
> index 0000000..a0beefe
> --- /dev/null
> +++ b/Silicon/NXP/Include/NxpPcie.h
> @@ -0,0 +1,146 @@
> +/** @file
> + PCI memory configuration for NXP
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __NXP_PCIE_H__
> +#define __NXP_PCIE_H__
> +
> +// Segment 0
> +#define PCI_SEG0_NUM 0
> +#define PCI_SEG0_MMIO32_MIN 0x40000000
> +#define PCI_SEG0_MMIO32_MAX 0x4fffffff
> +#define PCI_SEG0_MMIO64_MIN PCI_SEG0_MMIO_MEMBASE + \
> + SEG_MEM_SIZE + \
> + MEM64_BASE
> +#define PCI_SEG0_MMIO64_MAX PCI_SEG0_MMIO64_MIN + MEM64_LIMIT
Please use () around expressions (throughout)
> +#define PCI_SEG0_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp1BaseAddr)
> +#define PCI_SEG0_DBI_BASE 0x03400000
> +#define PCI_SEG0_MMIO_OFFSET 0x0
> +#define PCI_SEG0_PORTIO_MEMBASE PCI_SEG0_MMIO_MEMBASE + SEG_IO_SIZE
> +#define PCI_SEG0_PORTIO_OFFSET 0x0
> +
> +// Segment 1
> +#define PCI_SEG1_NUM 1
> +#define PCI_SEG1_MMIO32_MIN 0x40000000
> +#define PCI_SEG1_MMIO32_MAX 0x4fffffff
> +#define PCI_SEG1_MMIO64_MIN PCI_SEG1_MMIO_MEMBASE + \
> + SEG_MEM_SIZE + \
> + MEM64_BASE
> +#define PCI_SEG1_MMIO64_MAX PCI_SEG1_MMIO64_MIN + MEM64_LIMIT
> +#define PCI_SEG1_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp2BaseAddr)
> +#define PCI_SEG1_DBI_BASE 0x03500000
> +#define PCI_SEG1_MMIO_OFFSET 0x10000000
> +#define PCI_SEG1_PORTIO_MEMBASE PCI_SEG1_MMIO_MEMBASE + SEG_IO_SIZE
> +#define PCI_SEG1_PORTIO_OFFSET 0x10000
> +
> +// Segment 2
> +#define PCI_SEG2_NUM 2
> +#define PCI_SEG2_MMIO32_MIN 0x40000000
> +#define PCI_SEG2_MMIO32_MAX 0x4fffffff
> +#define PCI_SEG2_MMIO64_MIN PCI_SEG2_MMIO_MEMBASE + \
> + SEG_MEM_SIZE + \
> + MEM64_BASE
> +#define PCI_SEG2_MMIO64_MAX PCI_SEG2_MMIO64_MIN + MEM64_LIMIT
> +#define PCI_SEG2_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp3BaseAddr)
> +#define PCI_SEG2_DBI_BASE 0x03600000
> +#define PCI_SEG2_MMIO_OFFSET 0x20000000
> +#define PCI_SEG2_PORTIO_MEMBASE PCI_SEG2_MMIO_MEMBASE + SEG_IO_SIZE
> +#define PCI_SEG2_PORTIO_OFFSET 0x20000
> +
> +// Segment 3
> +#define PCI_SEG3_NUM 3
> +#define PCI_SEG3_MMIO32_MIN 0x40000000
> +#define PCI_SEG3_MMIO32_MAX 0x4fffffff
> +#define PCI_SEG3_MMIO64_MIN PCI_SEG3_MMIO_MEMBASE + \
> + SEG_MEM_SIZE + \
> + MEM64_BASE
> +#define PCI_SEG3_MMIO64_MAX PCI_SEG3_MMIO64_MIN + MEM64_LIMIT
> +#define PCI_SEG3_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp4BaseAddr)
> +#define PCI_SEG3_DBI_BASE 0x03700000
> +#define PCI_SEG3_MMIO_OFFSET 0x30000000
> +#define PCI_SEG3_PORTIO_MEMBASE PCI_SEG3_MMIO_MEMBASE + SEG_IO_SIZE
> +#define PCI_SEG3_PORTIO_OFFSET 0x30000
> +
> +// Segment configuration
> +#define PCI_SEG_BUSNUM_MIN 0x0
> +#define PCI_SEG_BUSNUM_MAX 0xff
> +#define PCI_SEG_PORTIO_MIN 0x0
> +#define PCI_SEG_PORTIO_MAX 0xffff
> +#define PCI_SEG_MMIO32_MIN 0x40000000
> +#define PCI_SEG_MMIO32_MAX 0x4fffffff
> +#define PCI_SEG_MMIO32_DIFF 0x10000000
> +#define PCI_SEG_MMIO64_MAX_DIFF 0x3fffffff
> +#define SEG_CFG_SIZE 0x00001000
> +#define SEG_CFG_BUS 0x00000000
> +#define SEG_MEM_SIZE 0x40000000
> +#define SEG_MEM_LIMIT 0x7fffffff
> +#define SEG_MEM_BUS 0x40000000
> +#define SEG_IO_SIZE 0x00010000
> +#define SEG_IO_BUS 0x00000000
> +#define PCI_SEG_PORTIO_LIMIT (NUM_PCIE_CONTROLLER * SEG_IO_SIZE) + \
> + PCI_SEG_PORTIO_MAX
> +#define PCI_BASE_DIFF 0x800000000
> +#define PCI_DBI_SIZE_DIFF 0x100000
> +#define PCI_SEG0_PHY_CFG0_BASE PCI_SEG0_MMIO_MEMBASE
> +#define PCI_SEG0_PHY_CFG1_BASE PCI_SEG0_PHY_CFG0_BASE + SEG_CFG_SIZE
> +#define PCI_SEG0_PHY_MEM_BASE PCI_SEG0_MMIO64_MIN - MEM64_BASE
> +#define PCI_SEG0_PHY_MEM64_BASE PCI_SEG0_MMIO64_MIN
> +#define PCI_SEG0_PHY_IO_BASE PCI_SEG0_MMIO_MEMBASE + SEG_IO_SIZE
> +#define MEM64_BASE 0xC0000000 // MMIO64 starts at 4GB offset
> +#define MEM64_LIMIT 0x1FFFFFFFF
> +#define SEG_MEM64_BASE 0x100000000
> +
> +// iATU configuration
> +#define IATU_VIEWPORT_OFF 0x900
> +#define IATU_VIEWPORT_OUTBOUND 0
> +
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
> +
> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31
> +
> +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
> +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
> +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914
> +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918
> +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C
> +
> +#define IATU_REGION_INDEX0 0x0
> +#define IATU_REGION_INDEX1 0x1
> +#define IATU_REGION_INDEX2 0x2
> +#define IATU_REGION_INDEX3 0x3
> +#define IATU_REGION_INDEX4 0x4
> +
> +// PCIe Controller configuration
> +#define NUM_PCIE_CONTROLLER FixedPcdGet32 (PcdNumPciController)
> +#define PCI_LUT_DBG FixedPcdGet32 (PcdPcieLutDbg)
> +#define PCI_LUT_BASE FixedPcdGet32 (PcdPcieLutBase)
> +#define LTSSM_STATE_MASK 0x3f
> +#define LTSSM_PCIE_L0 0x11
> +#define PCI_LINK_CAP 0x7c
> +#define PCI_LINK_SPEED_MASK 0xf
> +#define PCI_CLASS_BRIDGE_PCI 0x6040010
> +#define PCI_CLASS_DEVICE 0x8
> +#define PCI_DBI_RO_WR_EN 0x8bc
> +#define PCI_BASE_ADDRESS_0 0x10
> +
> +VOID GetSerdesProtocolMaps (UINT64 *);
> +
> +BOOLEAN IsSerDesLaneProtocolConfigured (UINT64, UINT16);
> +
> +#endif
> diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> new file mode 100644
> index 0000000..3a3e24a
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> @@ -0,0 +1,611 @@
> +/** @file
> + PCI Segment Library for NXP SoCs with multiple RCs
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials are
> + licensed and made available under the terms and conditions of
> + the BSD License which accompanies this distribution. The full
> + text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/PciSegmentLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <NxpPcie.h>
> +
> +typedef enum {
> + PciCfgWidthUint8 = 0,
> + PciCfgWidthUint16,
> + PciCfgWidthUint32,
> + PciCfgWidthMax
> +} PCI_CFG_WIDTH;
> +
> +/**
> + Assert the validity of a PCI Segment address.
> + A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
> +
> + @param A The address to validate.
> + @param M Additional bits to assert to be zero.
> +
> +**/
> +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
> + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
> +
> +/**
> + Function to return PCIe Physical Address(PCIe view) or Controller
> + Address(CPU view) for different RCs
> +
> + @param Address Address passed from bus layer.
> +
> + @return Return PCIe CPU or Controller address.
> +
> +**/
> +STATIC
> +UINT64
> +PciSegmentLibGetConfigBase (
> + IN UINT64 Address
> + )
> +{
> +
> + UINT16 Segment;
> +
> + //
> + // Reading Segment number(47-32 bits) in Address
> + //
> + Segment = (Address >> 32);
> +
> + switch (Segment) {
> + // Root Complex 1
> + case PCI_SEG0_NUM:
> + // Reading bus number(bits 20-27)
> + if ((Address >> 20) & 1) {
> + return PCI_SEG0_MMIO_MEMBASE;
So you are returning PCI_SEG0_MMIO_MEMBASE for odd bus numbers and
PCI_SEG0_DBI_BASE for even bus numbers??
> + } else {
> + // On Bus 0 RCs are connected
> + return PCI_SEG0_DBI_BASE;
> + }
> + // Root Complex 2
> + case PCI_SEG1_NUM:
> + // Reading bus number(bits 20-27)
> + if ((Address >> 20) & 1) {
> + return PCI_SEG1_MMIO_MEMBASE;
> + } else {
> + // On Bus 0 RCs are connected
> + return PCI_SEG1_DBI_BASE;
> + }
> + // Root Complex 3
> + case PCI_SEG2_NUM:
> + // Reading bus number(bits 20-27)
> + if ((Address >> 20) & 1) {
> + return PCI_SEG2_MMIO_MEMBASE;
> + } else {
> + // On Bus 0 RCs are connected
> + return PCI_SEG2_DBI_BASE;
> + }
> + // Root Complex 4
> + case PCI_SEG3_NUM:
> + // Reading bus number(bits 20-27)
> + if ((Address >> 20) & 1) {
> + return PCI_SEG3_MMIO_MEMBASE;
> + } else {
> + // On Bus 0 RCs are connected
> + return PCI_SEG3_DBI_BASE;
> + }
> + default:
> + return 0;
> + }
> +
> +}
> +
> +/**
> + Internal worker function to ignore device
> +
> + @param Address The address that encodes BDF
> +
> + @return TRUE to ignore the devices
> +
> +**/
> +STATIC
> +BOOLEAN
> +IgnoreDevices (
> + IN UINT64 Address
> + )
> +{
> + //
> + // ignore devices > 0 on bus 0
> + //
> + if ((Address & 0xff00000) == 0 && (Address & 0xf8000) != 0) {
> + return TRUE;
> + }
> +
> + //
> + // ignore device > 0 on bus 1
> + //
> + if ((Address & 0xfe00000) == 0 && (Address & 0xf8000) != 0) {
> + return TRUE;
> + }
> +
> + return FALSE;
> +}
> +
> +/**
> + Internal worker function to read a PCI configuration register.
> +
> + @param Address The address that encodes the Segment, PCI Bus, Device,
> + Function and Register.
> + @param Width The width of data to read
> +
> + @return The value read from the PCI configuration register.
> +
> +**/
> +STATIC
> +UINT32
> +PciSegmentLibReadWorker (
> + IN UINT64 Address,
> + IN PCI_CFG_WIDTH Width
> + )
> +{
> + UINT64 Base;
> + UINT16 Offset;
> +
> + //
> + // Reading Function(12-0) bits in Address
> + //
> + Offset = (Address & (SIZE_4KB - 1));
> +
> + Base = PciSegmentLibGetConfigBase (Address);
> +
> + if (IgnoreDevices (Address)) {
> + return MAX_UINT32;
> + }
> +
> + switch (Width) {
> + case PciCfgWidthUint8:
> + return MmioRead8 (Base + Offset);
> + case PciCfgWidthUint16:
> + return MmioRead16 (Base + Offset);
> + case PciCfgWidthUint32:
> + return MmioRead32 (Base + Offset);
> + default:
> + ASSERT (FALSE);
> + }
> +
> + return CHAR_NULL;
> +}
> +
> +/**
> + Internal worker function to writes a PCI configuration register.
> +
> + @param Address The address that encodes the Segment, PCI Bus, Device,
> + Function and Register.
> + @param Width The width of data to write
> + @param Data The value to write.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +STATIC
> +UINT32
> +PciSegmentLibWriteWorker (
> + IN UINT64 Address,
> + IN PCI_CFG_WIDTH Width,
> + IN UINT32 Data
> + )
> +{
> + UINT64 Base;
> + UINT32 Offset;
> +
> + //
> + // Reading Function(12-0 bits) in Address
> + //
> + Offset = (Address & (SIZE_4KB - 1));
> +
> + Base = PciSegmentLibGetConfigBase (Address);
> +
> + if (IgnoreDevices (Address)) {
> + return MAX_UINT32;
> + }
> +
> + switch (Width) {
> + case PciCfgWidthUint8:
> + MmioWrite8 (Base + Offset, Data);
> + break;
> + case PciCfgWidthUint16:
> + MmioWrite16 (Base + Offset, Data);
> + break;
> + case PciCfgWidthUint32:
> + MmioWrite32 (Base + Offset, Data);
> + break;
> + default:
> + ASSERT (FALSE);
> + }
> +
> + return Data;
> +}
> +
> +/**
> + Register a PCI device so PCI configuration registers may be accessed after
> + SetVirtualAddressMap().
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Bus, Device,
> + Function and Register.
> +
> + @retval RETURN_SUCCESS The PCI device was registered for runtime access.
> + @retval RETURN_UNSUPPORTED An attempt was made to call this function
> + after ExitBootServices().
> + @retval RETURN_UNSUPPORTED The resources required to access the PCI device
> + at runtime could not be mapped.
> + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
> + complete the registration.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +PciSegmentRegisterForRuntimeAccess (
> + IN UINTN Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> + return RETURN_UNSUPPORTED;
> +}
> +
> +/**
> + Reads an 8-bit PCI configuration register.
> +
> + Reads and returns the 8-bit PCI configuration register specified by Address.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function,
> + and Register.
> +
> + @return The 8-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentRead8 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +
> + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
> +}
> +
> +/**
> + Writes an 8-bit PCI configuration register.
> +
> + Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
> + Value is returned. This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param Value The value to write.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentWrite8 (
> + IN UINT64 Address,
> + IN UINT8 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +
> + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
> +}
> +
> +/**
> + Reads a 16-bit PCI configuration register.
> +
> + Reads and returns the 16-bit PCI configuration register specified by Address.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +
> + @return The 16-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentRead16 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> +
> + return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
> +}
> +
> +/**
> + Writes a 16-bit PCI configuration register.
> +
> + Writes the 16-bit PCI configuration register specified by Address with the
> + value specified by Value.
> +
> + Value is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param Value The value to write.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentWrite16 (
> + IN UINT64 Address,
> + IN UINT16 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> +
> + return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
> +}
> +
> +/**
> + Reads a 32-bit PCI configuration register.
> +
> + Reads and returns the 32-bit PCI configuration register specified by Address.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function,
> + and Register.
> +
> + @return The 32-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentRead32 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> +
> + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
> +}
> +
> +/**
> + Writes a 32-bit PCI configuration register.
> +
> + Writes the 32-bit PCI configuration register specified by Address with the
> + value specified by Value.
> +
> + Value is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param Value The value to write.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentWrite32 (
> + IN UINT64 Address,
> + IN UINT32 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> +
> + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
> +}
> +
> +/**
> + Reads a range of PCI configuration registers into a caller supplied buffer.
> +
> + Reads the range of PCI configuration registers specified by StartAddress and
> + Size into the buffer specified by Buffer. This function only allows the PCI
> + configuration registers from a single PCI function to be read. Size is
> + returned.
> +
> + If any reserved bits in StartAddress are set, then ASSERT().
> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> + If Size > 0 and Buffer is NULL, then ASSERT().
> +
> + @param StartAddress The starting address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> + @param Size The size in bytes of the transfer.
> + @param Buffer The pointer to a buffer receiving the data read.
> +
> + @return Size
> +
> +**/
> +UINTN
> +EFIAPI
> +PciSegmentReadBuffer (
> + IN UINT64 StartAddress,
> + IN UINTN Size,
> + OUT VOID *Buffer
> + )
> +{
> + UINTN ReturnValue;
> +
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
> + // 0xFFF is used as limit for 4KB config space
> + ASSERT (((StartAddress & (SIZE_4KB - 1)) + Size) <= SIZE_4KB);
> +
> + if (Size == 0) {
> + return Size;
> + }
> +
> + ASSERT (Buffer != NULL);
> +
> + //
> + // Save Size for return
> + //
> + ReturnValue = Size;
> +
> + if ((StartAddress & BIT0) != 0) {
> + //
> + // Read a byte if StartAddress is byte aligned
> + //
> + *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
> + StartAddress += sizeof (UINT8);
> + Size -= sizeof (UINT8);
> + Buffer += sizeof (UINT8);
> + }
> +
> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> + //
> + // Read a word if StartAddress is word aligned
> + //
> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer += sizeof (UINT16);
> + }
> +
> + while (Size >= sizeof (UINT32)) {
> + //
> + // Read as many double words as possible
> + //
> + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
> + StartAddress += sizeof (UINT32);
> + Size -= sizeof (UINT32);
> + Buffer += sizeof (UINT32);
> + }
> +
> + if (Size >= sizeof (UINT16)) {
> + //
> + // Read the last remaining word if exist
> + //
> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer += sizeof (UINT16);
> + }
> +
> + if (Size >= sizeof (UINT8)) {
> + //
> + // Read the last remaining byte if exist
> + //
> + *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
> + }
> +
> + return ReturnValue;
> +}
> +
> +
> +/**
> + Copies the data in a caller supplied buffer to a specified range of PCI
> + configuration space.
> +
> + Writes the range of PCI configuration registers specified by StartAddress and
> + Size from the buffer specified by Buffer. This function only allows the PCI
> + configuration registers from a single PCI function to be written. Size is
> + returned.
> +
> + If any reserved bits in StartAddress are set, then ASSERT().
> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> + If Size > 0 and Buffer is NULL, then ASSERT().
> +
> + @param StartAddress The starting address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> + @param Size The size in bytes of the transfer.
> + @param Buffer The pointer to a buffer containing the data to write.
> +
> + @return The parameter of Size.
> +
> +**/
> +UINTN
> +EFIAPI
> +PciSegmentWriteBuffer (
> + IN UINT64 StartAddress,
> + IN UINTN Size,
> + IN VOID *Buffer
> + )
> +{
> + UINTN ReturnValue;
> +
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
> + // 0xFFF is used as limit for 4KB config space
> + ASSERT (((StartAddress & (SIZE_4KB - 1)) + Size) <= SIZE_4KB);
> +
> + if (Size == 0) {
> + return Size;
> + }
> +
> + ASSERT (Buffer != NULL);
> +
> + //
> + // Save Size for return
> + //
> + ReturnValue = Size;
> +
> + if ((StartAddress & BIT0) != 0) {
> + //
> + // Write a byte if StartAddress is byte aligned
> + //
> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> + StartAddress += sizeof (UINT8);
> + Size -= sizeof (UINT8);
> + Buffer += sizeof (UINT8);
> + }
> +
> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> + //
> + // Write a word if StartAddress is word aligned
> + //
> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer += sizeof (UINT16);
> + }
> +
> + while (Size >= sizeof (UINT32)) {
> + //
> + // Write as many double words as possible
> + //
> + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
> + StartAddress += sizeof (UINT32);
> + Size -= sizeof (UINT32);
> + Buffer += sizeof (UINT32);
> + }
> +
> + if (Size >= sizeof (UINT16)) {
> + //
> + // Write the last remaining word if exist
> + //
> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer += sizeof (UINT16);
> + }
> +
> + if (Size >= sizeof (UINT8)) {
> + //
> + // Write the last remaining byte if exist
> + //
> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> + }
> +
> + return ReturnValue;
> +}
> diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> new file mode 100644
> index 0000000..1ac83d4
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> @@ -0,0 +1,41 @@
> +## @file
> +# PCI Segment Library for NXP SoCs with multiple RCs
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php.
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PciSegmentLib
> + FILE_GUID = c9f59261-5a60-4a4c-82f6-1f520442e100
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciSegmentLib
> +
> +[Sources]
> + PciSegmentLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + IoLib
> + PcdLib
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 35/41] Silicon/NXP: Implement PciHostBridgeLib support
2018-11-28 15:01 ` [PATCH edk2-platforms 35/41] Silicon/NXP: Implement PciHostBridgeLib support Meenakshi Aggarwal
@ 2018-12-21 10:51 ` Ard Biesheuvel
2018-12-21 18:30 ` Leif Lindholm
1 sibling, 0 replies; 254+ messages in thread
From: Ard Biesheuvel @ 2018-12-21 10:51 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org,
Udit Kumar, Varun Sethi, Vabhav
On Wed, 28 Nov 2018 at 10:16, Meenakshi Aggarwal
<meenakshi.aggarwal@nxp.com> wrote:
>
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Implement the library that exposes the PCIe root complexes to the
> generic PCI host bridge driver,Putting SoC Specific low level init
> code for the RCs.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> ---
> .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 639 +++++++++++++++++++++
> .../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 51 ++
> 2 files changed, 690 insertions(+)
> create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>
> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> new file mode 100644
> index 0000000..a543d7d
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> @@ -0,0 +1,639 @@
> +/** @file
> + PCI Host Bridge Library instance for NXP SoCs
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <IndustryStandard/Pci22.h>
> +#include <Library/DebugLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PciHostBridgeLib.h>
> +#include <NxpPcie.h>
> +#include <Protocol/PciHostBridgeResourceAllocation.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +
> +#pragma pack(1)
> +typedef struct {
> + ACPI_HID_DEVICE_PATH AcpiDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
> +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
> +#pragma pack ()
> +
> +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG0_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG1_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG2_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG3_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + }
> +};
> +
> +STATIC
> +GLOBAL_REMOVE_IF_UNREFERENCED
> +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
> + L"Mem", L"I/O", L"Bus"
> +};
> +
> +#define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | \
> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE
> +
> +#define PCI_SUPPORT_ATTRIBUTES EFI_PCI_ATTRIBUTE_ISA_IO_16 | \
> + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
> + EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
> + EFI_PCI_ATTRIBUTE_VGA_IO_16 | \
> + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
> +
> +PCI_ROOT_BRIDGE mPciRootBridges[NUM_PCIE_CONTROLLER];
> +
> +/**
> + Function to set-up iATU outbound window for PCIe controller
> +
> + @param Dbi Address of PCIe host controller.
> + @param Idx Index of iATU outbound window.
> + @param Type Type(Cfg0/Cfg1/Mem/IO) of iATU outbound window.
> + @param Phys PCIe controller phy address for outbound window.
> + @param BusAdr PCIe controller bus address for outbound window.
> + @param Pcie Size of PCIe controller space(Cfg0/Cfg1/Mem/IO).
> +
> +**/
> +STATIC
> +VOID
> +PcieIatuOutboundSet (
> + IN EFI_PHYSICAL_ADDRESS Dbi,
> + IN UINT32 Idx,
> + IN UINT32 Type,
> + IN UINT64 Phys,
> + IN UINT64 BusAddr,
> + IN UINT64 Size
> + )
> +{
> + MmioWrite32 (Dbi + IATU_VIEWPORT_OFF,
> + (UINT32)(IATU_VIEWPORT_OUTBOUND | Idx));
> + MmioWrite32 (Dbi + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
> + (UINT32)Phys);
> + MmioWrite32 (Dbi + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(Phys >> 32));
> + MmioWrite32 (Dbi + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(Phys + Size - BIT0));
> + MmioWrite32 (Dbi + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
> + (UINT32)BusAddr);
> + MmioWrite32 (Dbi + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(BusAddr >> 32));
> + MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
> + (UINT32)Type);
> + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
> + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN);
> +}
> +
> +/**
> + Function to check PCIe controller LTSSM state
> +
> + @param Pcie Address of PCIe host controller.
> +
> +**/
> +STATIC
> +INTN
> +PcieLinkState (
> + IN EFI_PHYSICAL_ADDRESS Pcie
> + )
> +{
> + UINT32 State;
> +
> + //
> + // Reading PCIe controller LTSSM state
> + //
> + if (FeaturePcdGet (PcdPciLutBigEndian)) {
> + State = SwapMmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
> + LTSSM_STATE_MASK;
> + } else {
> + State = MmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
> + LTSSM_STATE_MASK;
> + }
> +
> + if (State < LTSSM_PCIE_L0) {
> + DEBUG ((DEBUG_INFO," Pcie Link error. LTSSM=0x%2x\n", State));
> + return EFI_SUCCESS;
> + }
> +
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + Helper function to check PCIe link state
> +
> + @param Pcie Address of PCIe host controller.
> +
> +**/
> +STATIC
> +INTN
> +PcieLinkUp (
> + IN EFI_PHYSICAL_ADDRESS Pcie
> + )
> +{
> + INTN State;
> + UINT32 Cap;
> +
> + State = PcieLinkState (Pcie);
> + if (State) {
> + return State;
> + }
> +
> + //
> + // Try to download speed to gen1
> + //
> + Cap = MmioRead32 ((UINTN)Pcie + PCI_LINK_CAP);
> + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, (UINT32)(Cap & (~PCI_LINK_SPEED_MASK)) | BIT0);
> + State = PcieLinkState (Pcie);
> + if (State) {
> + return State;
> + }
> +
> + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, Cap);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function checks whether PCIe is enabled or not
> + depending upon SoC serdes protocol map
> +
> + @param PcieNum PCIe number.
> +
> + @return The PCIe number enabled in map.
> + @return FALSE PCIe number is disabled in map.
> +
> +**/
> +STATIC
> +BOOLEAN
> +IsPcieNumEnabled(
> + IN UINTN PcieNum
> + )
> +{
> + UINT64 SerDes1ProtocolMap;
> +
> + SerDes1ProtocolMap = 0x0;
> +
> + //
> + // Reading serdes map
> + //
> + GetSerdesProtocolMaps (&SerDes1ProtocolMap);
> +
> + //
> + // Verify serdes line is configured in the map
> + //
> + if (PcieNum < NUM_PCIE_CONTROLLER) {
> + return IsSerDesLaneProtocolConfigured (SerDes1ProtocolMap, (PcieNum + BIT0));
> + } else {
> + DEBUG ((DEBUG_ERROR, "Device not supported\n"));
> + }
> +
> + return FALSE;
> +}
> +
> +/**
> + Function to set-up iATU outbound window for PCIe controller
> +
> + @param Pcie Address of PCIe host controller
> + @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
> + @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
> + @param MemBase PCIe controller phy address in MMIO32 Memory Space.
> + @param Mem64Base PCIe controller phy address in MMIO64 Memory Space.
> + @param IoBase PCIe controller phy address IO Space.
> +**/
> +STATIC
> +VOID
> +PcieSetupAtu (
> + IN EFI_PHYSICAL_ADDRESS Pcie,
> + IN EFI_PHYSICAL_ADDRESS Cfg0Base,
> + IN EFI_PHYSICAL_ADDRESS Cfg1Base,
> + IN EFI_PHYSICAL_ADDRESS MemBase,
> + IN EFI_PHYSICAL_ADDRESS Mem64Base,
> + IN EFI_PHYSICAL_ADDRESS IoBase
> + )
> +{
> +
> + //
> + // iATU : OUTBOUND WINDOW 0 : CFG0
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX0,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
> + Cfg0Base,
> + SEG_CFG_BUS,
> + SEG_CFG_SIZE);
> +
> + //
> + // iATU : OUTBOUND WINDOW 1 : CFG1
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX1,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
> + Cfg1Base,
> + SEG_CFG_BUS,
> + SEG_CFG_SIZE);
> + //
> + // iATU 2 : OUTBOUND WINDOW 2 : MMIO32
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX2,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | BIT12,
> + MemBase,
> + SEG_MEM_BUS,
> + SEG_MEM_SIZE);
> +
> + //
> + // iATU 3 : OUTBOUND WINDOW 3: IO
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX3,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
> + IoBase,
> + SEG_IO_BUS,
> + SEG_IO_SIZE);
> + //
> + // iATU 4 : OUTBOUND WINDOW 4 : MMIO64
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX4,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
> + Mem64Base,
> + SEG_MEM64_BASE,
> + MEM64_LIMIT);
> +
> + if (FeaturePcdGet (PcdPciDebug) == TRUE) {
> + INTN Cnt;
> + UINTN AddrTemp;
> +
> + for (Cnt = 0; Cnt <= IATU_REGION_INDEX4; Cnt++) {
> + MmioWrite32 ((UINTN)Pcie + IATU_VIEWPORT_OFF,
> + (UINT32)(IATU_VIEWPORT_OUTBOUND | Cnt));
> + DEBUG ((DEBUG_INFO,"iATU%d:\n", Cnt));
> + AddrTemp = (UINTN)((UINTN)Pcie + IATU_VIEWPORT_OFF);
> + DEBUG ((DEBUG_INFO,"iATU%d VIEWPORT REG Addr:%08lx Val:%08lx\n",
> + Cnt, AddrTemp, MmioRead32 (AddrTemp)));
> + DEBUG ((DEBUG_INFO,"iATU%d VIEWPORT REG:%08lx\n",
> + Cnt, MmioRead32 ((UINTN)Pcie + IATU_VIEWPORT_OFF)));
> + DEBUG ((DEBUG_INFO,"\tLOWER PHYS 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tUPPER PHYS 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tLOWER BUS 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tUPPER BUS 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tLIMIT 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_LIMIT_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tCR1 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_REGION_CTRL_1_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tCR2 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_REGION_CTRL_2_OFF_OUTBOUND_0)));
> + }
> + }
> +}
> +
> +/**
> + Helper function to set-up PCIe controller
> +
> + @param Pcie Address of PCIe host controller
> + @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
> + @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
> + @param MemBase PCIe controller phy address MMIO32 Memory Space.
> + @param Mem64Base PCIe controller phy address MMIO64 Memory Space.
> + @param IoBase PCIe controller phy address IO Space.
> +
> +**/
> +STATIC
> +VOID
> +PcieSetupCntrl (
> + IN EFI_PHYSICAL_ADDRESS Pcie,
> + IN EFI_PHYSICAL_ADDRESS Cfg0Base,
> + IN EFI_PHYSICAL_ADDRESS Cfg1Base,
> + IN EFI_PHYSICAL_ADDRESS MemBase,
> + IN EFI_PHYSICAL_ADDRESS Mem64Base,
> + IN EFI_PHYSICAL_ADDRESS IoBase
> + )
> +{
> + //
> + // iATU outbound set-up
> + //
> + PcieSetupAtu (Pcie, Cfg0Base, Cfg1Base, MemBase, Mem64Base, IoBase);
> +
> + //
> + // program correct class for RC
> + //
> + MmioWrite32 ((UINTN)Pcie + PCI_BASE_ADDRESS_0, (BIT0 - BIT0));
> + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)BIT0);
> + MmioWrite32 ((UINTN)Pcie + PCI_CLASS_DEVICE, (UINT32)PCI_CLASS_BRIDGE_PCI);
> + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)(BIT0 - BIT0));
> +}
> +
> +/**
> + Return all the root bridge instances in an array.
> +
> + @param Count Return the count of root bridge instances.
> +
> + @return All the root bridge instances in an array.
> +
> +**/
> +PCI_ROOT_BRIDGE *
> +EFIAPI
> +PciHostBridgeGetRootBridges (
> + OUT UINTN *Count
> + )
> +{
> + UINTN Idx;
> + UINTN Loop;
> + INTN LinkUp;
> + UINT64 PciPhyMemAddr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyMem64Addr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyCfg0Addr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyCfg1Addr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyIoAddr[NUM_PCIE_CONTROLLER];
> + UINT64 Regs[NUM_PCIE_CONTROLLER];
> + UINT8 PciEnabled[NUM_PCIE_CONTROLLER];
> +
> + *Count = 0;
> +
> + //
> + // Filling local array for
> + // PCIe controller Physical address space for Cfg0,Cfg1,Mem,IO
> + // Host Contoller address
> + //
> + for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
> + PciPhyMemAddr[Idx] = PCI_SEG0_PHY_MEM_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyCfg0Addr[Idx] = PCI_SEG0_PHY_CFG0_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyCfg1Addr[Idx] = PCI_SEG0_PHY_CFG1_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyIoAddr [Idx] = PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyMem64Addr[Idx] = PCI_SEG0_PHY_MEM64_BASE + (PCI_BASE_DIFF * Idx);
> + Regs[Idx] = PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx);
> + }
> +
Please get rid of this loop. Your RCs happen to be organized in some
way in memory, but you already introduced #defines that describe each
in detail, so you should refer to them explicitly, and no apply some
fuzzy math that may or may not be correct for variations of this
platform.
> + if (FeaturePcdGet (PcdPciDebug) == TRUE) {
> + DEBUG ((DEBUG_INFO, "In PCIE_INFO: %d\n", Idx));
> + DEBUG ((DEBUG_INFO, "PciNum:%d Info PCIe Controller Address: %016llx\n",
> + Idx,
> + Regs[Idx]));
> + DEBUG ((DEBUG_INFO, "Info CFG Values: %016llx:%016llx\n",
> + (UINT64)PciPhyCfg0Addr[Idx],
> + (UINT64)PciPhyCfg1Addr[Idx]));
> + DEBUG ((DEBUG_INFO, "Info Mem Values: %016llx\n",
> + (UINT64)PciPhyMemAddr[Idx]));
> + DEBUG ((DEBUG_INFO, "Info IO Values: %016llx\n",
> + (UINT64)PciPhyIoAddr[Idx]));
> + DEBUG ((DEBUG_INFO, "Info Mem64 Values: %016llx\n",
> + (UINT64)PciPhyMem64Addr[Idx]));
> + }
> +
> + for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
> + //
> + // Verify PCIe controller is enabled in Soc Serdes Map
> + //
> + if (!IsPcieNumEnabled (Idx)) {
> + DEBUG ((DEBUG_ERROR, "PCIE%d is disabled\n", (Idx + BIT0)));
> + //
> + // Continue with other PCIe controller
> + //
> + continue;
> + }
> + DEBUG ((DEBUG_INFO, "PCIE%d is Enabled\n", Idx + BIT0));
> +
> + //
> + // Verify PCIe controller LTSSM state
> + //
> + LinkUp = PcieLinkUp(Regs[Idx]);
> + if (!LinkUp) {
> + //
> + // Let the user know there's no PCIe link
> + //
> + DEBUG ((DEBUG_INFO,"no link, regs @ 0x%lx\n", Regs[Idx]));
> + //
> + // Continue with other PCIe controller
> + //
> + continue;
> + }
> + DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + BIT0));
> +
> + //
> + // Function to set up address translation unit outbound window for
> + // PCIe Controller
> + //
> + PcieSetupCntrl (Regs[Idx],
> + PciPhyCfg0Addr[Idx],
> + PciPhyCfg1Addr[Idx],
> + PciPhyMemAddr[Idx],
> + PciPhyMem64Addr[Idx],
> + PciPhyIoAddr[Idx]);
> + //
> + // Local array to index all enable PCIe controllers
> + //
> + PciEnabled[*Count] = Idx;
> +
> + *Count += BIT0;
Seriously?
> + }
> +
> + if (*Count == 0) {
> + return NULL;
> + } else {
> + for (Loop = 0; Loop < *Count; Loop++) {
> + mPciRootBridges[Loop].Segment = PciEnabled[Loop];
> + mPciRootBridges[Loop].Supports = PCI_SUPPORT_ATTRIBUTES;
> + mPciRootBridges[Loop].Attributes = PCI_SUPPORT_ATTRIBUTES;
> + mPciRootBridges[Loop].DmaAbove4G = TRUE;
> + mPciRootBridges[Loop].NoExtendedConfigSpace = FALSE;
> + mPciRootBridges[Loop].ResourceAssigned = FALSE;
> + mPciRootBridges[Loop].AllocationAttributes = PCI_ALLOCATION_ATTRIBUTES;
> + mPciRootBridges[Loop].Bus.Base = PCI_SEG_BUSNUM_MIN;
> + mPciRootBridges[Loop].Bus.Limit = PCI_SEG_BUSNUM_MAX;
> + mPciRootBridges[Loop].Io.Base = PCI_SEG_PORTIO_MIN;
> + mPciRootBridges[Loop].Io.Limit = PCI_SEG_PORTIO_MAX;
> + mPciRootBridges[Loop].Io.Translation = MAX_UINT64 -
> + (PciEnabled[Loop] *
> + SEG_IO_SIZE) + 1;
> + mPciRootBridges[Loop].Mem.Base = PCI_SEG_MMIO32_MIN;
> + mPciRootBridges[Loop].Mem.Limit = PCI_SEG_MMIO32_MAX;
> + mPciRootBridges[Loop].Mem.Translation = MAX_UINT64 -
> + (PciEnabled[Loop] *
> + PCI_SEG_MMIO32_DIFF) + 1;
> + mPciRootBridges[Loop].MemAbove4G.Base = PciPhyMemAddr[PciEnabled[Loop]];
> + mPciRootBridges[Loop].MemAbove4G.Limit = PciPhyMemAddr[PciEnabled[Loop]] +
> + PCI_SEG_MMIO64_MAX_DIFF;
> + //
> + // No separate ranges for prefetchable and non-prefetchable BARs
> + //
> + mPciRootBridges[Loop].PMem.Base = MAX_UINT64;
> + mPciRootBridges[Loop].PMem.Limit = 0;
> + mPciRootBridges[Loop].PMemAbove4G.Base = MAX_UINT64;
> + mPciRootBridges[Loop].PMemAbove4G.Limit = 0;
> + mPciRootBridges[Loop].DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PciEnabled[Loop]];
> + }
> +
> + return mPciRootBridges;
> + }
> +}
> +
> +/**
> + Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
> +
> + @param Bridges The root bridge instances array.
> + @param Count The count of the array.
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeFreeRootBridges (
> + PCI_ROOT_BRIDGE *Bridges,
> + UINTN Count
> + )
> +{
> +}
> +
> +/**
> + Inform the platform that the resource conflict happens.
> +
> + @param HostBridgeHandle Handle of the Host Bridge.
> + @param Configuration Pointer to PCI I/O and PCI memory resource
> + descriptors. The Configuration contains the resources
> + for all the root bridges. The resource for each root
> + bridge is terminated with END descriptor and an
> + additional END is appended indicating the end of the
> + entire resources. The resource descriptor field
> + values follow the description in
> + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
> + .SubmitResources().
> +
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeResourceConflict (
> + EFI_HANDLE HostBridgeHandle,
> + VOID *Configuration
> + )
> +{
> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
> + UINTN RootBridgeIndex;
> + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
> +
> + RootBridgeIndex = 0;
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
> + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
> + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
> + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
> + ASSERT (Descriptor->ResType <
> + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));
> + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
> + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
> + Descriptor->AddrLen, Descriptor->AddrRangeMax
> + ));
> + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
> + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
> + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
> + ((Descriptor->SpecificFlag &
> + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
> + ) != 0) ? L" (Prefetchable)" : L""
> + ));
> + }
> + }
> + //
> + // Skip the END descriptor for root bridge
> + //
> + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
> + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
> + );
> + }
> +
> + return;
> +}
> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> new file mode 100644
> index 0000000..4f1c4d2
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> @@ -0,0 +1,51 @@
> +## @file
> +# PCI Host Bridge Library instance for NXP ARM SOC
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials are licensed and made available
> +# under the terms and conditions of the BSD License which accompanies this
> +# distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> +# IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PciHostBridgeLib
> + FILE_GUID = f4c99bcc-5c95-49ad-b0f3-fc5b611dc9c1
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciHostBridgeLib
> +
> +[Sources]
> + PciHostBridgeLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + DebugLib
> + DevicePathLib
> + IoAccessLib
> + MemoryAllocationLib
> + PcdLib
> + SocLib
> + UefiBootServicesTableLib
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 36/41] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
2018-11-28 15:01 ` [PATCH edk2-platforms 36/41] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL Meenakshi Aggarwal
@ 2018-12-21 11:09 ` Ard Biesheuvel
2018-12-21 18:49 ` Leif Lindholm
1 sibling, 0 replies; 254+ messages in thread
From: Ard Biesheuvel @ 2018-12-21 11:09 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: Leif Lindholm, Kinney, Michael D, edk2-devel@lists.01.org,
Udit Kumar, Varun Sethi, Vabhav
On Wed, 28 Nov 2018 at 10:16, Meenakshi Aggarwal
<meenakshi.aggarwal@nxp.com> wrote:
>
> From: Vabhav <vabhav.sharma@nxp.com>
>
> NXP SOC has mutiple PCIe RCs,Adding respective implementation of
> EFI_CPU_IO2_PROTOCOL to provide Memory Space Read/Write functions
> used by generic Host Bridge Driver including correct value for
> the translation offset during MMIO accesses
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 633 ++++++++++++++++++++++
> Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 49 ++
> 2 files changed, 682 insertions(+)
> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> create mode 100644 Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
>
> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> new file mode 100644
> index 0000000..b5c175b
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> @@ -0,0 +1,633 @@
> +/** @file
> + Produces the CPU I/O 2 Protocol.
> +
> + Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <NxpPcie.h>
> +#include <Protocol/CpuIo2.h>
> +
> +#define MAX_IO_PORT_ADDRESS PCI_SEG_PORTIO_LIMIT
> +
> +//
> +// Handle for the CPU I/O 2 Protocol
> +//
> +STATIC EFI_HANDLE mHandle;
> +
> +//
> +// Lookup table for increment values based on transfer widths
> +//
> +STATIC CONST UINT8 mInStride[] = {
> + 1, // EfiCpuIoWidthUint8
> + 2, // EfiCpuIoWidthUint16
> + 4, // EfiCpuIoWidthUint32
> + 8, // EfiCpuIoWidthUint64
> + 0, // EfiCpuIoWidthFifoUint8
> + 0, // EfiCpuIoWidthFifoUint16
> + 0, // EfiCpuIoWidthFifoUint32
> + 0, // EfiCpuIoWidthFifoUint64
> + 1, // EfiCpuIoWidthFillUint8
> + 2, // EfiCpuIoWidthFillUint16
> + 4, // EfiCpuIoWidthFillUint32
> + 8 // EfiCpuIoWidthFillUint64
> +};
> +
> +//
> +// Lookup table for increment values based on transfer widths
> +//
> +STATIC CONST UINT8 mOutStride[] = {
> + 1, // EfiCpuIoWidthUint8
> + 2, // EfiCpuIoWidthUint16
> + 4, // EfiCpuIoWidthUint32
> + 8, // EfiCpuIoWidthUint64
> + 1, // EfiCpuIoWidthFifoUint8
> + 2, // EfiCpuIoWidthFifoUint16
> + 4, // EfiCpuIoWidthFifoUint32
> + 8, // EfiCpuIoWidthFifoUint64
> + 0, // EfiCpuIoWidthFillUint8
> + 0, // EfiCpuIoWidthFillUint16
> + 0, // EfiCpuIoWidthFillUint32
> + 0 // EfiCpuIoWidthFillUint64
> +};
> +
> +/**
> + Check parameters to a CPU I/O 2 Protocol service request.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[in] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The parameters for this request pass the checks.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +CpuIoCheckParameter (
> + IN BOOLEAN MmioOperation,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + UINT64 MaxCount;
> + UINT64 Limit;
> +
> + //
> + // Check to see if Buffer is NULL
> + //
> + if (Buffer == NULL) {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Check to see if Width is in the valid range
> + //
> + if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // For FIFO type, the target address won't increase during the access,
> + // so treat Count as 1
> + //
> + if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
> + Count = 1;
> + }
> +
> + //
> + // Check to see if Width is in the valid range for I/O Port operations
> + //
> + Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
> + if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Check to see if Address is aligned
> + //
> + if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Check to see if any address associated with this transfer exceeds the maximum
> + // allowed address. The maximum address implied by the parameters passed in is
> + // Address + Size * Count. If the following condition is met, then the transfer
> + // is not supported.
> + //
> + // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
> + //
> + // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
> + // can also be the maximum integer value supported by the CPU, this range
> + // check must be adjusted to avoid all oveflow conditions.
> + //
> + Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
> + if (Count == 0) {
> + if (Address > Limit) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> + } else {
> + MaxCount = RShiftU64 (Limit, Width);
> + if (MaxCount < (Count - 1)) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> + }
> +
> + //
> + // Check to see if Buffer is aligned
> + //
> + if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
> + ASSERT (FALSE);
> + return EFI_UNSUPPORTED;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Reads memory-mapped registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[out] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuMemoryServiceRead (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 InStride;
> + UINT8 OutStride;
> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
> + UINT8 *Uint8Buffer;
> +
> + //
> + // Make sure the parameters are valid
> + //
> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if ((Address >= (PCI_SEG0_MMIO32_MIN + PCI_SEG0_MMIO_OFFSET)) &&
> + (Address <= (PCI_SEG0_MMIO32_MAX + PCI_SEG0_MMIO_OFFSET))) {
> + Address += PCI_SEG0_MMIO_MEMBASE - PCI_SEG0_MMIO_OFFSET;
> + } else if ((Address >= (PCI_SEG1_MMIO32_MIN + PCI_SEG1_MMIO_OFFSET)) &&
> + (Address <= (PCI_SEG1_MMIO32_MAX + PCI_SEG1_MMIO_OFFSET))) {
> + Address += PCI_SEG1_MMIO_MEMBASE - PCI_SEG1_MMIO_OFFSET;
> + } else if ((Address >= (PCI_SEG2_MMIO32_MIN + PCI_SEG2_MMIO_OFFSET)) &&
> + (Address <= (PCI_SEG2_MMIO32_MAX + PCI_SEG2_MMIO_OFFSET))) {
> + Address += PCI_SEG2_MMIO_MEMBASE - PCI_SEG2_MMIO_OFFSET;
> + } else if ((Address >= (PCI_SEG3_MMIO32_MIN + PCI_SEG3_MMIO_OFFSET)) &&
> + (Address <= (PCI_SEG3_MMIO32_MAX + PCI_SEG3_MMIO_OFFSET))) {
> + Address += PCI_SEG3_MMIO_MEMBASE - PCI_SEG3_MMIO_OFFSET;
> + } else {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
Please put this in a helper function instead of duplicating it.
> + //
> + // Select loop based on the width of the transfer
> + //
> + InStride = mInStride[Width];
> + OutStride = mOutStride[Width];
> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
> + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
> + if (OperationWidth == EfiCpuIoWidthUint8) {
> + *Uint8Buffer = MmioRead8 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
> + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
> + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
> + *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Writes memory-mapped registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[in] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuMemoryServiceWrite (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 InStride;
> + UINT8 OutStride;
> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
> + UINT8 *Uint8Buffer;
> +
> + //
> + // Make sure the parameters are valid
> + //
> + Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if ((Address >= (PCI_SEG0_MMIO32_MIN + PCI_SEG0_MMIO_OFFSET)) &&
> + (Address <= (PCI_SEG0_MMIO32_MAX + PCI_SEG0_MMIO_OFFSET))) {
> + Address += PCI_SEG0_MMIO_MEMBASE - PCI_SEG0_MMIO_OFFSET;
> + } else if ((Address >= (PCI_SEG1_MMIO32_MIN + PCI_SEG1_MMIO_OFFSET)) &&
> + (Address <= (PCI_SEG1_MMIO32_MAX + PCI_SEG1_MMIO_OFFSET))) {
> + Address += PCI_SEG1_MMIO_MEMBASE - PCI_SEG1_MMIO_OFFSET;
> + } else if ((Address >= (PCI_SEG2_MMIO32_MIN + PCI_SEG2_MMIO_OFFSET)) &&
> + (Address <= (PCI_SEG2_MMIO32_MAX + PCI_SEG2_MMIO_OFFSET))) {
> + Address += PCI_SEG2_MMIO_MEMBASE - PCI_SEG2_MMIO_OFFSET;
> + } else if ((Address >= (PCI_SEG3_MMIO32_MIN + PCI_SEG3_MMIO_OFFSET)) &&
> + (Address <= (PCI_SEG3_MMIO32_MAX + PCI_SEG3_MMIO_OFFSET))) {
> + Address += PCI_SEG3_MMIO_MEMBASE - PCI_SEG3_MMIO_OFFSET;
> + } else {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Select loop based on the width of the transfer
> + //
> + InStride = mInStride[Width];
> + OutStride = mOutStride[Width];
> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
> + for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
> + if (OperationWidth == EfiCpuIoWidthUint8) {
> + MmioWrite8 ((UINTN)Address, *Uint8Buffer);
> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
> + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
> + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
> + } else if (OperationWidth == EfiCpuIoWidthUint64) {
> + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Reads I/O registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[out] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuIoServiceRead (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 InStride;
> + UINT8 OutStride;
> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
> + UINT8 *Uint8Buffer;
> +
> + //
> + // Make sure the parameters are valid
> + //
> + Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG0_PORTIO_OFFSET)) &&
> + (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG0_PORTIO_OFFSET))) {
> + Address += PCI_SEG0_PORTIO_MEMBASE - PCI_SEG0_PORTIO_OFFSET;
> + } else if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG1_PORTIO_OFFSET)) &&
> + (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG1_PORTIO_OFFSET))) {
> + Address += PCI_SEG1_PORTIO_MEMBASE - PCI_SEG1_PORTIO_OFFSET;
> + } else if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG2_PORTIO_OFFSET)) &&
> + (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG2_PORTIO_OFFSET))) {
> + Address += PCI_SEG2_PORTIO_MEMBASE - PCI_SEG2_PORTIO_OFFSET;
> + } else if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG3_PORTIO_OFFSET)) &&
> + (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG3_PORTIO_OFFSET))) {
> + Address += PCI_SEG3_PORTIO_MEMBASE - PCI_SEG3_PORTIO_OFFSET;
> + } else {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Select loop based on the width of the transfer
> + //
> + InStride = mInStride[Width];
> + OutStride = mOutStride[Width];
> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
> +
> + for (Uint8Buffer = Buffer; Count > 0;
> + Address += InStride, Uint8Buffer += OutStride, Count--) {
> + if (OperationWidth == EfiCpuIoWidthUint8) {
> + *Uint8Buffer = MmioRead8 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
> + *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
> + *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Write I/O registers.
> +
> + The I/O operations are carried out exactly as requested. The caller is responsible
> + for satisfying any alignment and I/O width restrictions that a PI System on a
> + platform might require. For example on some platforms, width requests of
> + EfiCpuIoWidthUint64 do not work.
> +
> + If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
> + or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
> + each of the Count operations that is performed.
> +
> + If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
> + EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times on the same Address.
> +
> + If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
> + EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
> + incremented for each of the Count operations that is performed. The read or
> + write operation is performed Count times from the first element of Buffer.
> +
> + @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
> + @param[in] Width Signifies the width of the I/O or Memory operation.
> + @param[in] Address The base address of the I/O operation.
> + @param[in] Count The number of I/O operations to perform. The number of
> + bytes moved is Width size * Count, starting at Address.
> + @param[in] Buffer For read operations, the destination buffer to store the results.
> + For write operations, the source buffer from which to write data.
> +
> + @retval EFI_SUCCESS The data was read from or written to the PI system.
> + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
> + @retval EFI_INVALID_PARAMETER Buffer is NULL.
> + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
> + @retval EFI_UNSUPPORTED The address range specified by Address, Width,
> + and Count is not valid for this PI system.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +CpuIoServiceWrite (
> + IN EFI_CPU_IO2_PROTOCOL *This,
> + IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
> + IN UINT64 Address,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 InStride;
> + UINT8 OutStride;
> + EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
> + UINT8 *Uint8Buffer;
> +
> + //
> + // Make sure the parameters are valid
> + //
> + Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG0_PORTIO_OFFSET)) &&
> + (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG0_PORTIO_OFFSET))) {
> + Address += PCI_SEG0_PORTIO_MEMBASE - PCI_SEG0_PORTIO_OFFSET;
> + } else if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG1_PORTIO_OFFSET)) &&
> + (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG1_PORTIO_OFFSET))) {
> + Address += PCI_SEG1_PORTIO_MEMBASE - PCI_SEG1_PORTIO_OFFSET;
> + } else if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG2_PORTIO_OFFSET)) &&
> + (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG2_PORTIO_OFFSET))) {
> + Address += PCI_SEG2_PORTIO_MEMBASE - PCI_SEG2_PORTIO_OFFSET;
> + } else if ((Address >= (PCI_SEG_PORTIO_MIN + PCI_SEG3_PORTIO_OFFSET)) &&
> + (Address <= (PCI_SEG_PORTIO_MAX + PCI_SEG3_PORTIO_OFFSET))) {
> + Address += PCI_SEG3_PORTIO_MEMBASE - PCI_SEG3_PORTIO_OFFSET;
> + } else {
> + ASSERT (FALSE);
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + //
> + // Select loop based on the width of the transfer
> + //
> + InStride = mInStride[Width];
> + OutStride = mOutStride[Width];
> + OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
> +
> + for (Uint8Buffer = (UINT8 *)Buffer; Count > 0;
> + Address += InStride, Uint8Buffer += OutStride, Count--) {
> + if (OperationWidth == EfiCpuIoWidthUint8) {
> + MmioWrite8 ((UINTN)Address, *Uint8Buffer);
> + } else if (OperationWidth == EfiCpuIoWidthUint16) {
> + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
> + } else if (OperationWidth == EfiCpuIoWidthUint32) {
> + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +//
> +// CPU I/O 2 Protocol instance
> +//
> +STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
> + {
> + CpuMemoryServiceRead,
> + CpuMemoryServiceWrite
> + },
> + {
> + CpuIoServiceRead,
> + CpuIoServiceWrite
> + }
> +};
> +
> +
> +/**
> + The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
> +
> + @param[in] ImageHandle The firmware allocated handle for the EFI image.
> + @param[in] SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The entry point is executed successfully.
> + @retval other Some error occurs when executing this entry point.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +PciCpuIo2Initialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> +
> + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &mHandle,
> + &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
> + NULL
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> diff --git a/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> new file mode 100644
> index 0000000..7e958b1
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> @@ -0,0 +1,49 @@
> +## @file
> +# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PciCpuIo2Dxe
> + FILE_GUID = 7bff18d7-9aae-434b-9c06-f10a7e157eac
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PciCpuIo2Initialize
> +
> +[Sources]
> + PciCpuIo2Dxe.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + IoLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController
> +
> +[Protocols]
> + gEfiCpuIo2ProtocolGuid ## PRODUCES
> +
> +[Depex]
> + TRUE
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 34/41] Silicon/NXP: Implement PciSegmentLib to support multiple RCs
2018-11-28 15:01 ` [PATCH edk2-platforms 34/41] Silicon/NXP: Implement PciSegmentLib to support multiple RCs Meenakshi Aggarwal
2018-12-21 10:44 ` Ard Biesheuvel
@ 2018-12-21 14:01 ` Leif Lindholm
1 sibling, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 14:01 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Vabhav
On Wed, Nov 28, 2018 at 08:31:48PM +0530, Meenakshi Aggarwal wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Multiple root complex support is not provided by standard library
> PciLib/PciExpressLib/PciSegmentLib, Reimplementing it and provide
> function for reading/writing into PCIe configuration Space.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/NxpPcie.h | 146 +++++
> Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 611 +++++++++++++++++++++
> .../NXP/Library/PciSegmentLib/PciSegmentLib.inf | 41 ++
> 3 files changed, 798 insertions(+)
> create mode 100644 Silicon/NXP/Include/NxpPcie.h
> create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> create mode 100644 Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
>
> diff --git a/Silicon/NXP/Include/NxpPcie.h b/Silicon/NXP/Include/NxpPcie.h
> new file mode 100644
> index 0000000..a0beefe
> --- /dev/null
> +++ b/Silicon/NXP/Include/NxpPcie.h
> @@ -0,0 +1,146 @@
> +/** @file
> + PCI memory configuration for NXP
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __NXP_PCIE_H__
> +#define __NXP_PCIE_H__
> +
> +// Segment 0
> +#define PCI_SEG0_NUM 0
> +#define PCI_SEG0_MMIO32_MIN 0x40000000
> +#define PCI_SEG0_MMIO32_MAX 0x4fffffff
> +#define PCI_SEG0_MMIO64_MIN PCI_SEG0_MMIO_MEMBASE + \
> + SEG_MEM_SIZE + \
> + MEM64_BASE
> +#define PCI_SEG0_MMIO64_MAX PCI_SEG0_MMIO64_MIN + MEM64_LIMIT
> +#define PCI_SEG0_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp1BaseAddr)
> +#define PCI_SEG0_DBI_BASE 0x03400000
> +#define PCI_SEG0_MMIO_OFFSET 0x0
> +#define PCI_SEG0_PORTIO_MEMBASE PCI_SEG0_MMIO_MEMBASE + SEG_IO_SIZE
> +#define PCI_SEG0_PORTIO_OFFSET 0x0
> +
> +// Segment 1
> +#define PCI_SEG1_NUM 1
> +#define PCI_SEG1_MMIO32_MIN 0x40000000
> +#define PCI_SEG1_MMIO32_MAX 0x4fffffff
> +#define PCI_SEG1_MMIO64_MIN PCI_SEG1_MMIO_MEMBASE + \
> + SEG_MEM_SIZE + \
> + MEM64_BASE
> +#define PCI_SEG1_MMIO64_MAX PCI_SEG1_MMIO64_MIN + MEM64_LIMIT
> +#define PCI_SEG1_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp2BaseAddr)
> +#define PCI_SEG1_DBI_BASE 0x03500000
> +#define PCI_SEG1_MMIO_OFFSET 0x10000000
> +#define PCI_SEG1_PORTIO_MEMBASE PCI_SEG1_MMIO_MEMBASE + SEG_IO_SIZE
> +#define PCI_SEG1_PORTIO_OFFSET 0x10000
> +
> +// Segment 2
> +#define PCI_SEG2_NUM 2
> +#define PCI_SEG2_MMIO32_MIN 0x40000000
> +#define PCI_SEG2_MMIO32_MAX 0x4fffffff
> +#define PCI_SEG2_MMIO64_MIN PCI_SEG2_MMIO_MEMBASE + \
> + SEG_MEM_SIZE + \
> + MEM64_BASE
> +#define PCI_SEG2_MMIO64_MAX PCI_SEG2_MMIO64_MIN + MEM64_LIMIT
> +#define PCI_SEG2_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp3BaseAddr)
> +#define PCI_SEG2_DBI_BASE 0x03600000
> +#define PCI_SEG2_MMIO_OFFSET 0x20000000
> +#define PCI_SEG2_PORTIO_MEMBASE PCI_SEG2_MMIO_MEMBASE + SEG_IO_SIZE
> +#define PCI_SEG2_PORTIO_OFFSET 0x20000
> +
> +// Segment 3
> +#define PCI_SEG3_NUM 3
> +#define PCI_SEG3_MMIO32_MIN 0x40000000
> +#define PCI_SEG3_MMIO32_MAX 0x4fffffff
> +#define PCI_SEG3_MMIO64_MIN PCI_SEG3_MMIO_MEMBASE + \
> + SEG_MEM_SIZE + \
> + MEM64_BASE
> +#define PCI_SEG3_MMIO64_MAX PCI_SEG3_MMIO64_MIN + MEM64_LIMIT
> +#define PCI_SEG3_MMIO_MEMBASE FixedPcdGet64 (PcdPciExp4BaseAddr)
> +#define PCI_SEG3_DBI_BASE 0x03700000
> +#define PCI_SEG3_MMIO_OFFSET 0x30000000
> +#define PCI_SEG3_PORTIO_MEMBASE PCI_SEG3_MMIO_MEMBASE + SEG_IO_SIZE
> +#define PCI_SEG3_PORTIO_OFFSET 0x30000
> +
> +// Segment configuration
> +#define PCI_SEG_BUSNUM_MIN 0x0
> +#define PCI_SEG_BUSNUM_MAX 0xff
> +#define PCI_SEG_PORTIO_MIN 0x0
> +#define PCI_SEG_PORTIO_MAX 0xffff
> +#define PCI_SEG_MMIO32_MIN 0x40000000
> +#define PCI_SEG_MMIO32_MAX 0x4fffffff
> +#define PCI_SEG_MMIO32_DIFF 0x10000000
> +#define PCI_SEG_MMIO64_MAX_DIFF 0x3fffffff
> +#define SEG_CFG_SIZE 0x00001000
> +#define SEG_CFG_BUS 0x00000000
> +#define SEG_MEM_SIZE 0x40000000
> +#define SEG_MEM_LIMIT 0x7fffffff
> +#define SEG_MEM_BUS 0x40000000
> +#define SEG_IO_SIZE 0x00010000
> +#define SEG_IO_BUS 0x00000000
> +#define PCI_SEG_PORTIO_LIMIT (NUM_PCIE_CONTROLLER * SEG_IO_SIZE) + \
> + PCI_SEG_PORTIO_MAX
> +#define PCI_BASE_DIFF 0x800000000
> +#define PCI_DBI_SIZE_DIFF 0x100000
> +#define PCI_SEG0_PHY_CFG0_BASE PCI_SEG0_MMIO_MEMBASE
> +#define PCI_SEG0_PHY_CFG1_BASE PCI_SEG0_PHY_CFG0_BASE + SEG_CFG_SIZE
> +#define PCI_SEG0_PHY_MEM_BASE PCI_SEG0_MMIO64_MIN - MEM64_BASE
> +#define PCI_SEG0_PHY_MEM64_BASE PCI_SEG0_MMIO64_MIN
> +#define PCI_SEG0_PHY_IO_BASE PCI_SEG0_MMIO_MEMBASE + SEG_IO_SIZE
> +#define MEM64_BASE 0xC0000000 // MMIO64 starts at 4GB offset
> +#define MEM64_LIMIT 0x1FFFFFFFF
> +#define SEG_MEM64_BASE 0x100000000
> +
> +// iATU configuration
> +#define IATU_VIEWPORT_OFF 0x900
> +#define IATU_VIEWPORT_OUTBOUND 0
> +
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0 0x904
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM 0x0
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO 0x2
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0 0x4
> +#define IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1 0x5
> +
> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0 0x908
> +#define IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN BIT31
> +
> +#define IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 0x90C
> +#define IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 0x910
> +#define IATU_LIMIT_ADDR_OFF_OUTBOUND_0 0x914
> +#define IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 0x918
> +#define IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 0x91C
> +
> +#define IATU_REGION_INDEX0 0x0
> +#define IATU_REGION_INDEX1 0x1
> +#define IATU_REGION_INDEX2 0x2
> +#define IATU_REGION_INDEX3 0x3
> +#define IATU_REGION_INDEX4 0x4
> +
> +// PCIe Controller configuration
> +#define NUM_PCIE_CONTROLLER FixedPcdGet32 (PcdNumPciController)
> +#define PCI_LUT_DBG FixedPcdGet32 (PcdPcieLutDbg)
> +#define PCI_LUT_BASE FixedPcdGet32 (PcdPcieLutBase)
> +#define LTSSM_STATE_MASK 0x3f
> +#define LTSSM_PCIE_L0 0x11
> +#define PCI_LINK_CAP 0x7c
> +#define PCI_LINK_SPEED_MASK 0xf
> +#define PCI_CLASS_BRIDGE_PCI 0x6040010
> +#define PCI_CLASS_DEVICE 0x8
> +#define PCI_DBI_RO_WR_EN 0x8bc
> +#define PCI_BASE_ADDRESS_0 0x10
> +
> +VOID GetSerdesProtocolMaps (UINT64 *);
> +
> +BOOLEAN IsSerDesLaneProtocolConfigured (UINT64, UINT16);
> +
> +#endif
> diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> new file mode 100644
> index 0000000..3a3e24a
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c
> @@ -0,0 +1,611 @@
> +/** @file
> + PCI Segment Library for NXP SoCs with multiple RCs
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials are
> + licensed and made available under the terms and conditions of
> + the BSD License which accompanies this distribution. The full
> + text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/PciSegmentLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <NxpPcie.h>
> +
> +typedef enum {
> + PciCfgWidthUint8 = 0,
> + PciCfgWidthUint16,
> + PciCfgWidthUint32,
> + PciCfgWidthMax
> +} PCI_CFG_WIDTH;
Please move to local include file.
> +
> +/**
> + Assert the validity of a PCI Segment address.
> + A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
Why?
Because of the memory map in the SoC?
If so, please list those requirements rather than just which bits are affected.
> +
> + @param A The address to validate.
> + @param M Additional bits to assert to be zero.
> +
> +**/
> +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
> + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
Please move to local include file.
> +
> +/**
> + Function to return PCIe Physical Address(PCIe view) or Controller
> + Address(CPU view) for different RCs
> +
> + @param Address Address passed from bus layer.
> +
> + @return Return PCIe CPU or Controller address.
> +
> +**/
> +STATIC
> +UINT64
> +PciSegmentLibGetConfigBase (
> + IN UINT64 Address
> + )
> +{
> +
> + UINT16 Segment;
> +
> + //
> + // Reading Segment number(47-32 bits) in Address
> + //
> + Segment = (Address >> 32);
Assumes 63-48 are zero.
Could this be a macro, which also did proper masking?
> +
> + switch (Segment) {
> + // Root Complex 1
> + case PCI_SEG0_NUM:
> + // Reading bus number(bits 20-27)
> + if ((Address >> 20) & 1) {
No, this is reading bit 20. With a comment describing why 0000001 is
MMIO_MBASE and anything else is DBI_BASE, that's probably fine. But
the comment does not reflect the operation performed.
Could this be a macro?
> + return PCI_SEG0_MMIO_MEMBASE;
> + } else {
> + // On Bus 0 RCs are connected
> + return PCI_SEG0_DBI_BASE;
> + }
> + // Root Complex 2
> + case PCI_SEG1_NUM:
> + // Reading bus number(bits 20-27)
> + if ((Address >> 20) & 1) {
Same comment as above.
Could use the same macro.
> + return PCI_SEG1_MMIO_MEMBASE;
> + } else {
> + // On Bus 0 RCs are connected
> + return PCI_SEG1_DBI_BASE;
> + }
> + // Root Complex 3
> + case PCI_SEG2_NUM:
> + // Reading bus number(bits 20-27)
> + if ((Address >> 20) & 1) {
Same comment as above.
Could use the same macro.
> + return PCI_SEG2_MMIO_MEMBASE;
> + } else {
> + // On Bus 0 RCs are connected
> + return PCI_SEG2_DBI_BASE;
> + }
> + // Root Complex 4
> + case PCI_SEG3_NUM:
> + // Reading bus number(bits 20-27)
> + if ((Address >> 20) & 1) {
Same comment as above.
Could use the same macro.
> + return PCI_SEG3_MMIO_MEMBASE;
> + } else {
> + // On Bus 0 RCs are connected
> + return PCI_SEG3_DBI_BASE;
> + }
> + default:
> + return 0;
PLease use a define to show you're returning an error and not the
address 0.
> + }
> +
> +}
> +
> +/**
> + Internal worker function to ignore device
> +
> + @param Address The address that encodes BDF
> +
> + @return TRUE to ignore the devices
> +
> +**/
> +STATIC
> +BOOLEAN
> +IgnoreDevices (
> + IN UINT64 Address
> + )
> +{
> + //
> + // ignore devices > 0 on bus 0
> + //
> + if ((Address & 0xff00000) == 0 && (Address & 0xf8000) != 0) {
Macros please.
> + return TRUE;
> + }
> +
> + //
> + // ignore device > 0 on bus 1
> + //
> + if ((Address & 0xfe00000) == 0 && (Address & 0xf8000) != 0) {
Macros please.
> + return TRUE;
> + }
> +
> + return FALSE;
> +}
> +
> +/**
> + Internal worker function to read a PCI configuration register.
> +
> + @param Address The address that encodes the Segment, PCI Bus, Device,
> + Function and Register.
> + @param Width The width of data to read
> +
> + @return The value read from the PCI configuration register.
> +
> +**/
> +STATIC
> +UINT32
> +PciSegmentLibReadWorker (
> + IN UINT64 Address,
> + IN PCI_CFG_WIDTH Width
> + )
> +{
> + UINT64 Base;
> + UINT16 Offset;
> +
> + //
> + // Reading Function(12-0) bits in Address
> + //
> + Offset = (Address & (SIZE_4KB - 1));
This would read bits 11-0.
> +
> + Base = PciSegmentLibGetConfigBase (Address);
> +
> + if (IgnoreDevices (Address)) {
> + return MAX_UINT32;
> + }
> +
> + switch (Width) {
> + case PciCfgWidthUint8:
> + return MmioRead8 (Base + Offset);
> + case PciCfgWidthUint16:
> + return MmioRead16 (Base + Offset);
> + case PciCfgWidthUint32:
> + return MmioRead32 (Base + Offset);
> + default:
> + ASSERT (FALSE);
> + }
> +
> + return CHAR_NULL;
This is not a string parsing function, please choose (or create) a
better define.
> +}
> +
> +/**
> + Internal worker function to writes a PCI configuration register.
> +
> + @param Address The address that encodes the Segment, PCI Bus, Device,
> + Function and Register.
> + @param Width The width of data to write
> + @param Data The value to write.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +STATIC
> +UINT32
> +PciSegmentLibWriteWorker (
> + IN UINT64 Address,
> + IN PCI_CFG_WIDTH Width,
> + IN UINT32 Data
> + )
> +{
> + UINT64 Base;
> + UINT32 Offset;
> +
> + //
> + // Reading Function(12-0 bits) in Address
> + //
> + Offset = (Address & (SIZE_4KB - 1));
11-0.
> +
> + Base = PciSegmentLibGetConfigBase (Address);
> +
> + if (IgnoreDevices (Address)) {
> + return MAX_UINT32;
> + }
> +
> + switch (Width) {
> + case PciCfgWidthUint8:
> + MmioWrite8 (Base + Offset, Data);
> + break;
> + case PciCfgWidthUint16:
> + MmioWrite16 (Base + Offset, Data);
> + break;
> + case PciCfgWidthUint32:
> + MmioWrite32 (Base + Offset, Data);
> + break;
> + default:
> + ASSERT (FALSE);
This means we're failing silently if (somehow) we ended up attempting
a 64-bit write. That feels less than ideal.
> + }
> +
> + return Data;
> +}
> +
> +/**
> + Register a PCI device so PCI configuration registers may be accessed after
> + SetVirtualAddressMap().
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Bus, Device,
> + Function and Register.
> +
> + @retval RETURN_SUCCESS The PCI device was registered for runtime access.
> + @retval RETURN_UNSUPPORTED An attempt was made to call this function
> + after ExitBootServices().
> + @retval RETURN_UNSUPPORTED The resources required to access the PCI device
> + at runtime could not be mapped.
> + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
> + complete the registration.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +PciSegmentRegisterForRuntimeAccess (
> + IN UINTN Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> + return RETURN_UNSUPPORTED;
> +}
> +
> +/**
> + Reads an 8-bit PCI configuration register.
> +
> + Reads and returns the 8-bit PCI configuration register specified by Address.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function,
> + and Register.
> +
> + @return The 8-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentRead8 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +
> + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
No space after (UINT8).
> +}
> +
> +/**
> + Writes an 8-bit PCI configuration register.
> +
> + Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
> + Value is returned. This function must guarantee that all PCI read and write operations are serialized.
> +
> + If any reserved bits in Address are set, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param Value The value to write.
> +
> + @return The value written to the PCI configuration register.
> +
> +**/
> +UINT8
> +EFIAPI
> +PciSegmentWrite8 (
> + IN UINT64 Address,
> + IN UINT8 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
> +
> + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
No space after (UINT8).
> +}
> +
> +/**
> + Reads a 16-bit PCI configuration register.
> +
> + Reads and returns the 16-bit PCI configuration register specified by Address.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> +
> + @return The 16-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentRead16 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
This demonstrates the opaqueness of the macro's "additional bits to
check". There is zero chance anyone who didn't just look at that macro
would understand the meaning of that 1.
Please create macros ALIGN_8, ALIGN_16, ALIGN_32 and use those.
> +
> + return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
No space after (UINT16).
(Please address throughout.)
/
Leif
> +}
> +
> +/**
> + Writes a 16-bit PCI configuration register.
> +
> + Writes the 16-bit PCI configuration register specified by Address with the
> + value specified by Value.
> +
> + Value is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 16-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
> + @param Value The value to write.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT16
> +EFIAPI
> +PciSegmentWrite16 (
> + IN UINT64 Address,
> + IN UINT16 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
> +
> + return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
> +}
> +
> +/**
> + Reads a 32-bit PCI configuration register.
> +
> + Reads and returns the 32-bit PCI configuration register specified by Address.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device, Function,
> + and Register.
> +
> + @return The 32-bit PCI configuration register specified by Address.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentRead32 (
> + IN UINT64 Address
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> +
> + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
> +}
> +
> +/**
> + Writes a 32-bit PCI configuration register.
> +
> + Writes the 32-bit PCI configuration register specified by Address with the
> + value specified by Value.
> +
> + Value is returned.
> +
> + If any reserved bits in Address are set, then ASSERT().
> + If Address is not aligned on a 32-bit boundary, then ASSERT().
> +
> + @param Address The address that encodes the PCI Segment, Bus, Device,
> + Function, and Register.
> + @param Value The value to write.
> +
> + @return The parameter of Value.
> +
> +**/
> +UINT32
> +EFIAPI
> +PciSegmentWrite32 (
> + IN UINT64 Address,
> + IN UINT32 Value
> + )
> +{
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
> +
> + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
> +}
> +
> +/**
> + Reads a range of PCI configuration registers into a caller supplied buffer.
> +
> + Reads the range of PCI configuration registers specified by StartAddress and
> + Size into the buffer specified by Buffer. This function only allows the PCI
> + configuration registers from a single PCI function to be read. Size is
> + returned.
> +
> + If any reserved bits in StartAddress are set, then ASSERT().
> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> + If Size > 0 and Buffer is NULL, then ASSERT().
> +
> + @param StartAddress The starting address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> + @param Size The size in bytes of the transfer.
> + @param Buffer The pointer to a buffer receiving the data read.
> +
> + @return Size
> +
> +**/
> +UINTN
> +EFIAPI
> +PciSegmentReadBuffer (
> + IN UINT64 StartAddress,
> + IN UINTN Size,
> + OUT VOID *Buffer
> + )
> +{
> + UINTN ReturnValue;
> +
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
> + // 0xFFF is used as limit for 4KB config space
> + ASSERT (((StartAddress & (SIZE_4KB - 1)) + Size) <= SIZE_4KB);
> +
> + if (Size == 0) {
> + return Size;
> + }
> +
> + ASSERT (Buffer != NULL);
> +
> + //
> + // Save Size for return
> + //
> + ReturnValue = Size;
> +
> + if ((StartAddress & BIT0) != 0) {
> + //
> + // Read a byte if StartAddress is byte aligned
> + //
> + *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
> + StartAddress += sizeof (UINT8);
> + Size -= sizeof (UINT8);
> + Buffer += sizeof (UINT8);
> + }
> +
> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> + //
> + // Read a word if StartAddress is word aligned
> + //
> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer += sizeof (UINT16);
> + }
> +
> + while (Size >= sizeof (UINT32)) {
> + //
> + // Read as many double words as possible
> + //
> + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
> + StartAddress += sizeof (UINT32);
> + Size -= sizeof (UINT32);
> + Buffer += sizeof (UINT32);
> + }
> +
> + if (Size >= sizeof (UINT16)) {
> + //
> + // Read the last remaining word if exist
> + //
> + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer += sizeof (UINT16);
> + }
> +
> + if (Size >= sizeof (UINT8)) {
> + //
> + // Read the last remaining byte if exist
> + //
> + *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
> + }
> +
> + return ReturnValue;
> +}
> +
> +
> +/**
> + Copies the data in a caller supplied buffer to a specified range of PCI
> + configuration space.
> +
> + Writes the range of PCI configuration registers specified by StartAddress and
> + Size from the buffer specified by Buffer. This function only allows the PCI
> + configuration registers from a single PCI function to be written. Size is
> + returned.
> +
> + If any reserved bits in StartAddress are set, then ASSERT().
> + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
> + If Size > 0 and Buffer is NULL, then ASSERT().
> +
> + @param StartAddress The starting address that encodes the PCI Segment, Bus,
> + Device, Function and Register.
> + @param Size The size in bytes of the transfer.
> + @param Buffer The pointer to a buffer containing the data to write.
> +
> + @return The parameter of Size.
> +
> +**/
> +UINTN
> +EFIAPI
> +PciSegmentWriteBuffer (
> + IN UINT64 StartAddress,
> + IN UINTN Size,
> + IN VOID *Buffer
> + )
> +{
> + UINTN ReturnValue;
> +
> + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
> + // 0xFFF is used as limit for 4KB config space
> + ASSERT (((StartAddress & (SIZE_4KB - 1)) + Size) <= SIZE_4KB);
> +
> + if (Size == 0) {
> + return Size;
> + }
> +
> + ASSERT (Buffer != NULL);
> +
> + //
> + // Save Size for return
> + //
> + ReturnValue = Size;
> +
> + if ((StartAddress & BIT0) != 0) {
> + //
> + // Write a byte if StartAddress is byte aligned
> + //
> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> + StartAddress += sizeof (UINT8);
> + Size -= sizeof (UINT8);
> + Buffer += sizeof (UINT8);
> + }
> +
> + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
> + //
> + // Write a word if StartAddress is word aligned
> + //
> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer += sizeof (UINT16);
> + }
> +
> + while (Size >= sizeof (UINT32)) {
> + //
> + // Write as many double words as possible
> + //
> + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
> + StartAddress += sizeof (UINT32);
> + Size -= sizeof (UINT32);
> + Buffer += sizeof (UINT32);
> + }
> +
> + if (Size >= sizeof (UINT16)) {
> + //
> + // Write the last remaining word if exist
> + //
> + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
> + StartAddress += sizeof (UINT16);
> + Size -= sizeof (UINT16);
> + Buffer += sizeof (UINT16);
> + }
> +
> + if (Size >= sizeof (UINT8)) {
> + //
> + // Write the last remaining byte if exist
> + //
> + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
> + }
> +
> + return ReturnValue;
> +}
> diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> new file mode 100644
> index 0000000..1ac83d4
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> @@ -0,0 +1,41 @@
> +## @file
> +# PCI Segment Library for NXP SoCs with multiple RCs
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php.
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PciSegmentLib
> + FILE_GUID = c9f59261-5a60-4a4c-82f6-1f520442e100
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciSegmentLib
> +
> +[Sources]
> + PciSegmentLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + IoLib
> + PcdLib
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 35/41] Silicon/NXP: Implement PciHostBridgeLib support
2018-11-28 15:01 ` [PATCH edk2-platforms 35/41] Silicon/NXP: Implement PciHostBridgeLib support Meenakshi Aggarwal
2018-12-21 10:51 ` Ard Biesheuvel
@ 2018-12-21 18:30 ` Leif Lindholm
1 sibling, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 18:30 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Vabhav
On Wed, Nov 28, 2018 at 08:31:49PM +0530, Meenakshi Aggarwal wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Implement the library that exposes the PCIe root complexes to the
> generic PCI host bridge driver,Putting SoC Specific low level init
> code for the RCs.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> ---
> .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 639 +++++++++++++++++++++
> .../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 51 ++
> 2 files changed, 690 insertions(+)
> create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>
> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> new file mode 100644
> index 0000000..a543d7d
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c
> @@ -0,0 +1,639 @@
> +/** @file
> + PCI Host Bridge Library instance for NXP SoCs
> +
> + Copyright 2018 NXP
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +#include <IndustryStandard/Pci22.h>
> +#include <Library/DebugLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PciHostBridgeLib.h>
> +#include <NxpPcie.h>
> +#include <Protocol/PciHostBridgeResourceAllocation.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +
> +#pragma pack(1)
> +typedef struct {
> + ACPI_HID_DEVICE_PATH AcpiDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
> +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
> +#pragma pack ()
> +
> +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG0_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG1_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG2_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + },
> + {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
> + }
> + },
> + EISA_PNP_ID (0x0A08), // PCI Express
> + PCI_SEG3_NUM
> + },
> +
> + {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> + }
> +};
> +
> +STATIC
> +GLOBAL_REMOVE_IF_UNREFERENCED
> +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
> + L"Mem", L"I/O", L"Bus"
> +};
> +
> +#define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | \
> + EFI_PCI_HOST_BRIDGE_MEM64_DECODE
> +
> +#define PCI_SUPPORT_ATTRIBUTES EFI_PCI_ATTRIBUTE_ISA_IO_16 | \
> + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
> + EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
> + EFI_PCI_ATTRIBUTE_VGA_IO_16 | \
> + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16
> +
> +PCI_ROOT_BRIDGE mPciRootBridges[NUM_PCIE_CONTROLLER];
> +
> +/**
> + Function to set-up iATU outbound window for PCIe controller
> +
> + @param Dbi Address of PCIe host controller.
> + @param Idx Index of iATU outbound window.
> + @param Type Type(Cfg0/Cfg1/Mem/IO) of iATU outbound window.
> + @param Phys PCIe controller phy address for outbound window.
> + @param BusAdr PCIe controller bus address for outbound window.
> + @param Pcie Size of PCIe controller space(Cfg0/Cfg1/Mem/IO).
> +
> +**/
> +STATIC
> +VOID
> +PcieIatuOutboundSet (
> + IN EFI_PHYSICAL_ADDRESS Dbi,
> + IN UINT32 Idx,
> + IN UINT32 Type,
> + IN UINT64 Phys,
> + IN UINT64 BusAddr,
> + IN UINT64 Size
> + )
> +{
> + MmioWrite32 (Dbi + IATU_VIEWPORT_OFF,
> + (UINT32)(IATU_VIEWPORT_OUTBOUND | Idx));
Indentation in continuation should be one step further.
Please address below as well.
> + MmioWrite32 (Dbi + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0,
> + (UINT32)Phys);
> + MmioWrite32 (Dbi + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(Phys >> 32));
> + MmioWrite32 (Dbi + IATU_LIMIT_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(Phys + Size - BIT0));
What's with the BIT0 arithmetic?
> + MmioWrite32 (Dbi + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0,
> + (UINT32)BusAddr);
> + MmioWrite32 (Dbi + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0,
> + (UINT32)(BusAddr >> 32));
> + MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0,
> + (UINT32)Type);
> + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0,
> + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN);
> +}
> +
> +/**
> + Function to check PCIe controller LTSSM state
> +
> + @param Pcie Address of PCIe host controller.
> +
> +**/
> +STATIC
> +INTN
> +PcieLinkState (
> + IN EFI_PHYSICAL_ADDRESS Pcie
> + )
> +{
> + UINT32 State;
> +
> + //
> + // Reading PCIe controller LTSSM state
> + //
> + if (FeaturePcdGet (PcdPciLutBigEndian)) {
> + State = SwapMmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
> + LTSSM_STATE_MASK;
> + } else {
> + State = MmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) &
> + LTSSM_STATE_MASK;
> + }
> +
> + if (State < LTSSM_PCIE_L0) {
> + DEBUG ((DEBUG_INFO," Pcie Link error. LTSSM=0x%2x\n", State));
> + return EFI_SUCCESS;
> + }
> +
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + Helper function to check PCIe link state
> +
> + @param Pcie Address of PCIe host controller.
> +
> +**/
> +STATIC
> +INTN
> +PcieLinkUp (
> + IN EFI_PHYSICAL_ADDRESS Pcie
> + )
> +{
> + INTN State;
> + UINT32 Cap;
> +
> + State = PcieLinkState (Pcie);
> + if (State) {
> + return State;
> + }
> +
> + //
> + // Try to download speed to gen1
> + //
> + Cap = MmioRead32 ((UINTN)Pcie + PCI_LINK_CAP);
> + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, (UINT32)(Cap & (~PCI_LINK_SPEED_MASK)) | BIT0);
What does BIT0 signify here?
> + State = PcieLinkState (Pcie);
> + if (State) {
> + return State;
> + }
> +
> + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, Cap);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + This function checks whether PCIe is enabled or not
> + depending upon SoC serdes protocol map
> +
> + @param PcieNum PCIe number.
> +
> + @return The PCIe number enabled in map.
> + @return FALSE PCIe number is disabled in map.
> +
> +**/
> +STATIC
> +BOOLEAN
> +IsPcieNumEnabled(
> + IN UINTN PcieNum
> + )
> +{
> + UINT64 SerDes1ProtocolMap;
> +
> + SerDes1ProtocolMap = 0x0;
> +
> + //
> + // Reading serdes map
> + //
> + GetSerdesProtocolMaps (&SerDes1ProtocolMap);
> +
> + //
> + // Verify serdes line is configured in the map
> + //
> + if (PcieNum < NUM_PCIE_CONTROLLER) {
> + return IsSerDesLaneProtocolConfigured (SerDes1ProtocolMap, (PcieNum + BIT0));
So, I'm getting the feeling a global search-and-replace on BIT0 may
have happened in this file/patch. Please have a look and see where the
numeral 1 is what was intended, where a #define with a descriptive
alias for BIT0 was intended, and where actually BIT0 was intended.
> + } else {
> + DEBUG ((DEBUG_ERROR, "Device not supported\n"));
> + }
> +
> + return FALSE;
> +}
> +
> +/**
> + Function to set-up iATU outbound window for PCIe controller
> +
> + @param Pcie Address of PCIe host controller
> + @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
> + @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
> + @param MemBase PCIe controller phy address in MMIO32 Memory Space.
> + @param Mem64Base PCIe controller phy address in MMIO64 Memory Space.
> + @param IoBase PCIe controller phy address IO Space.
> +**/
> +STATIC
> +VOID
> +PcieSetupAtu (
> + IN EFI_PHYSICAL_ADDRESS Pcie,
> + IN EFI_PHYSICAL_ADDRESS Cfg0Base,
> + IN EFI_PHYSICAL_ADDRESS Cfg1Base,
> + IN EFI_PHYSICAL_ADDRESS MemBase,
> + IN EFI_PHYSICAL_ADDRESS Mem64Base,
> + IN EFI_PHYSICAL_ADDRESS IoBase
> + )
> +{
> +
> + //
> + // iATU : OUTBOUND WINDOW 0 : CFG0
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX0,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0,
> + Cfg0Base,
> + SEG_CFG_BUS,
> + SEG_CFG_SIZE);
I'll just point out here that I'm nearly certain this indentation
pattern violates the coding style. But I kind of like it :)
> +
> + //
> + // iATU : OUTBOUND WINDOW 1 : CFG1
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX1,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1,
> + Cfg1Base,
> + SEG_CFG_BUS,
> + SEG_CFG_SIZE);
> + //
> + // iATU 2 : OUTBOUND WINDOW 2 : MMIO32
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX2,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | BIT12,
> + MemBase,
> + SEG_MEM_BUS,
> + SEG_MEM_SIZE);
> +
> + //
> + // iATU 3 : OUTBOUND WINDOW 3: IO
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX3,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO,
> + IoBase,
> + SEG_IO_BUS,
> + SEG_IO_SIZE);
> + //
> + // iATU 4 : OUTBOUND WINDOW 4 : MMIO64
> + //
> + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX4,
> + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM,
> + Mem64Base,
> + SEG_MEM64_BASE,
> + MEM64_LIMIT);
> +
> + if (FeaturePcdGet (PcdPciDebug) == TRUE) {
> + INTN Cnt;
Cnt -> Count;
> + UINTN AddrTemp;
> +
> + for (Cnt = 0; Cnt <= IATU_REGION_INDEX4; Cnt++) {
> + MmioWrite32 ((UINTN)Pcie + IATU_VIEWPORT_OFF,
> + (UINT32)(IATU_VIEWPORT_OUTBOUND | Cnt));
> + DEBUG ((DEBUG_INFO,"iATU%d:\n", Cnt));
> + AddrTemp = (UINTN)((UINTN)Pcie + IATU_VIEWPORT_OFF);
> + DEBUG ((DEBUG_INFO,"iATU%d VIEWPORT REG Addr:%08lx Val:%08lx\n",
> + Cnt, AddrTemp, MmioRead32 (AddrTemp)));
> + DEBUG ((DEBUG_INFO,"iATU%d VIEWPORT REG:%08lx\n",
> + Cnt, MmioRead32 ((UINTN)Pcie + IATU_VIEWPORT_OFF)));
> + DEBUG ((DEBUG_INFO,"\tLOWER PHYS 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tUPPER PHYS 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tLOWER BUS 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tUPPER BUS 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tLIMIT 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_LIMIT_ADDR_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tCR1 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_REGION_CTRL_1_OFF_OUTBOUND_0)));
> + DEBUG ((DEBUG_INFO,"\tCR2 0x%08x\n",
> + MmioRead32 ((UINTN)Pcie + IATU_REGION_CTRL_2_OFF_OUTBOUND_0)));
> + }
> + }
> +}
> +
> +/**
> + Helper function to set-up PCIe controller
> +
> + @param Pcie Address of PCIe host controller
> + @param Cfg0Base PCIe controller phy address Type0 Configuration Space.
> + @param Cfg1Base PCIe controller phy address Type1 Configuration Space.
> + @param MemBase PCIe controller phy address MMIO32 Memory Space.
> + @param Mem64Base PCIe controller phy address MMIO64 Memory Space.
> + @param IoBase PCIe controller phy address IO Space.
> +
> +**/
> +STATIC
> +VOID
> +PcieSetupCntrl (
> + IN EFI_PHYSICAL_ADDRESS Pcie,
> + IN EFI_PHYSICAL_ADDRESS Cfg0Base,
> + IN EFI_PHYSICAL_ADDRESS Cfg1Base,
> + IN EFI_PHYSICAL_ADDRESS MemBase,
> + IN EFI_PHYSICAL_ADDRESS Mem64Base,
> + IN EFI_PHYSICAL_ADDRESS IoBase
> + )
> +{
> + //
> + // iATU outbound set-up
> + //
> + PcieSetupAtu (Pcie, Cfg0Base, Cfg1Base, MemBase, Mem64Base, IoBase);
> +
> + //
> + // program correct class for RC
> + //
> + MmioWrite32 ((UINTN)Pcie + PCI_BASE_ADDRESS_0, (BIT0 - BIT0));
> + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)BIT0);
> + MmioWrite32 ((UINTN)Pcie + PCI_CLASS_DEVICE, (UINT32)PCI_CLASS_BRIDGE_PCI);
> + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)(BIT0 - BIT0));
> +}
> +
> +/**
> + Return all the root bridge instances in an array.
> +
> + @param Count Return the count of root bridge instances.
> +
> + @return All the root bridge instances in an array.
> +
> +**/
> +PCI_ROOT_BRIDGE *
> +EFIAPI
> +PciHostBridgeGetRootBridges (
> + OUT UINTN *Count
> + )
> +{
> + UINTN Idx;
Idx -> Index.
> + UINTN Loop;
> + INTN LinkUp;
> + UINT64 PciPhyMemAddr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyMem64Addr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyCfg0Addr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyCfg1Addr[NUM_PCIE_CONTROLLER];
> + UINT64 PciPhyIoAddr[NUM_PCIE_CONTROLLER];
> + UINT64 Regs[NUM_PCIE_CONTROLLER];
> + UINT8 PciEnabled[NUM_PCIE_CONTROLLER];
> +
> + *Count = 0;
> +
> + //
> + // Filling local array for
> + // PCIe controller Physical address space for Cfg0,Cfg1,Mem,IO
> + // Host Contoller address
> + //
> + for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
> + PciPhyMemAddr[Idx] = PCI_SEG0_PHY_MEM_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyCfg0Addr[Idx] = PCI_SEG0_PHY_CFG0_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyCfg1Addr[Idx] = PCI_SEG0_PHY_CFG1_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyIoAddr [Idx] = PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx);
> + PciPhyMem64Addr[Idx] = PCI_SEG0_PHY_MEM64_BASE + (PCI_BASE_DIFF * Idx);
> + Regs[Idx] = PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx);
> + }
> +
> + if (FeaturePcdGet (PcdPciDebug) == TRUE) {
> + DEBUG ((DEBUG_INFO, "In PCIE_INFO: %d\n", Idx));
> + DEBUG ((DEBUG_INFO, "PciNum:%d Info PCIe Controller Address: %016llx\n",
> + Idx,
> + Regs[Idx]));
> + DEBUG ((DEBUG_INFO, "Info CFG Values: %016llx:%016llx\n",
> + (UINT64)PciPhyCfg0Addr[Idx],
> + (UINT64)PciPhyCfg1Addr[Idx]));
> + DEBUG ((DEBUG_INFO, "Info Mem Values: %016llx\n",
> + (UINT64)PciPhyMemAddr[Idx]));
> + DEBUG ((DEBUG_INFO, "Info IO Values: %016llx\n",
> + (UINT64)PciPhyIoAddr[Idx]));
> + DEBUG ((DEBUG_INFO, "Info Mem64 Values: %016llx\n",
> + (UINT64)PciPhyMem64Addr[Idx]));
> + }
> +
> + for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) {
> + //
> + // Verify PCIe controller is enabled in Soc Serdes Map
> + //
> + if (!IsPcieNumEnabled (Idx)) {
> + DEBUG ((DEBUG_ERROR, "PCIE%d is disabled\n", (Idx + BIT0)));
> + //
> + // Continue with other PCIe controller
> + //
> + continue;
> + }
> + DEBUG ((DEBUG_INFO, "PCIE%d is Enabled\n", Idx + BIT0));
> +
> + //
> + // Verify PCIe controller LTSSM state
> + //
> + LinkUp = PcieLinkUp(Regs[Idx]);
Space after (.
> + if (!LinkUp) {
> + //
> + // Let the user know there's no PCIe link
> + //
> + DEBUG ((DEBUG_INFO,"no link, regs @ 0x%lx\n", Regs[Idx]));
> + //
> + // Continue with other PCIe controller
> + //
> + continue;
> + }
> + DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + BIT0));
> +
> + //
> + // Function to set up address translation unit outbound window for
> + // PCIe Controller
> + //
> + PcieSetupCntrl (Regs[Idx],
> + PciPhyCfg0Addr[Idx],
> + PciPhyCfg1Addr[Idx],
> + PciPhyMemAddr[Idx],
> + PciPhyMem64Addr[Idx],
> + PciPhyIoAddr[Idx]);
> + //
> + // Local array to index all enable PCIe controllers
> + //
> + PciEnabled[*Count] = Idx;
> +
> + *Count += BIT0;
> + }
> +
> + if (*Count == 0) {
> + return NULL;
> + } else {
No need for the else, anything after the NULL return is just the rest
of the function, and can lose a level of indentation.
> + for (Loop = 0; Loop < *Count; Loop++) {
> + mPciRootBridges[Loop].Segment = PciEnabled[Loop];
> + mPciRootBridges[Loop].Supports = PCI_SUPPORT_ATTRIBUTES;
> + mPciRootBridges[Loop].Attributes = PCI_SUPPORT_ATTRIBUTES;
> + mPciRootBridges[Loop].DmaAbove4G = TRUE;
> + mPciRootBridges[Loop].NoExtendedConfigSpace = FALSE;
> + mPciRootBridges[Loop].ResourceAssigned = FALSE;
> + mPciRootBridges[Loop].AllocationAttributes = PCI_ALLOCATION_ATTRIBUTES;
> + mPciRootBridges[Loop].Bus.Base = PCI_SEG_BUSNUM_MIN;
> + mPciRootBridges[Loop].Bus.Limit = PCI_SEG_BUSNUM_MAX;
> + mPciRootBridges[Loop].Io.Base = PCI_SEG_PORTIO_MIN;
> + mPciRootBridges[Loop].Io.Limit = PCI_SEG_PORTIO_MAX;
> + mPciRootBridges[Loop].Io.Translation = MAX_UINT64 -
> + (PciEnabled[Loop] *
> + SEG_IO_SIZE) + 1;
> + mPciRootBridges[Loop].Mem.Base = PCI_SEG_MMIO32_MIN;
> + mPciRootBridges[Loop].Mem.Limit = PCI_SEG_MMIO32_MAX;
> + mPciRootBridges[Loop].Mem.Translation = MAX_UINT64 -
> + (PciEnabled[Loop] *
> + PCI_SEG_MMIO32_DIFF) + 1;
> + mPciRootBridges[Loop].MemAbove4G.Base = PciPhyMemAddr[PciEnabled[Loop]];
> + mPciRootBridges[Loop].MemAbove4G.Limit = PciPhyMemAddr[PciEnabled[Loop]] +
> + PCI_SEG_MMIO64_MAX_DIFF;
> + //
> + // No separate ranges for prefetchable and non-prefetchable BARs
> + //
> + mPciRootBridges[Loop].PMem.Base = MAX_UINT64;
> + mPciRootBridges[Loop].PMem.Limit = 0;
> + mPciRootBridges[Loop].PMemAbove4G.Base = MAX_UINT64;
> + mPciRootBridges[Loop].PMemAbove4G.Limit = 0;
> + mPciRootBridges[Loop].DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PciEnabled[Loop]];
> + }
> +
> + return mPciRootBridges;
> + }
> +}
> +
> +/**
> + Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
> +
> + @param Bridges The root bridge instances array.
> + @param Count The count of the array.
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeFreeRootBridges (
> + PCI_ROOT_BRIDGE *Bridges,
> + UINTN Count
> + )
> +{
A comment that/why nothing is needed here wouldn't go amiss.
/
Leif
> +}
> +
> +/**
> + Inform the platform that the resource conflict happens.
> +
> + @param HostBridgeHandle Handle of the Host Bridge.
> + @param Configuration Pointer to PCI I/O and PCI memory resource
> + descriptors. The Configuration contains the resources
> + for all the root bridges. The resource for each root
> + bridge is terminated with END descriptor and an
> + additional END is appended indicating the end of the
> + entire resources. The resource descriptor field
> + values follow the description in
> + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
> + .SubmitResources().
> +
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeResourceConflict (
> + EFI_HANDLE HostBridgeHandle,
> + VOID *Configuration
> + )
> +{
> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
> + UINTN RootBridgeIndex;
> + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
> +
> + RootBridgeIndex = 0;
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
> + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
> + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
> + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
> + ASSERT (Descriptor->ResType <
> + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));
> + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
> + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
> + Descriptor->AddrLen, Descriptor->AddrRangeMax
> + ));
> + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
> + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
> + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
> + ((Descriptor->SpecificFlag &
> + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
> + ) != 0) ? L" (Prefetchable)" : L""
> + ));
> + }
> + }
> + //
> + // Skip the END descriptor for root bridge
> + //
> + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
> + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
> + );
> + }
> +
> + return;
> +}
> diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> new file mode 100644
> index 0000000..4f1c4d2
> --- /dev/null
> +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> @@ -0,0 +1,51 @@
> +## @file
> +# PCI Host Bridge Library instance for NXP ARM SOC
> +#
> +# Copyright 2018 NXP
> +#
> +# This program and the accompanying materials are licensed and made available
> +# under the terms and conditions of the BSD License which accompanies this
> +# distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> +# IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PciHostBridgeLib
> + FILE_GUID = f4c99bcc-5c95-49ad-b0f3-fc5b611dc9c1
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciHostBridgeLib
> +
> +[Sources]
> + PciHostBridgeLib.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + DebugLib
> + DevicePathLib
> + IoAccessLib
> + MemoryAllocationLib
> + PcdLib
> + SocLib
> + UefiBootServicesTableLib
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 36/41] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL
2018-11-28 15:01 ` [PATCH edk2-platforms 36/41] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL Meenakshi Aggarwal
2018-12-21 11:09 ` Ard Biesheuvel
@ 2018-12-21 18:49 ` Leif Lindholm
1 sibling, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 18:49 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Vabhav
On Wed, Nov 28, 2018 at 08:31:50PM +0530, Meenakshi Aggarwal wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> NXP SOC has mutiple PCIe RCs,Adding respective implementation of
> EFI_CPU_IO2_PROTOCOL to provide Memory Space Read/Write functions
> used by generic Host Bridge Driver including correct value for
> the translation offset during MMIO accesses
Could you let me know (not necessarily in the commit message) which
implementation this is based on, so that I can have a look
specifically at the diff?
Really not a fan of this code, but most of the bits I dislike are
copied from elsewhere. I will try to remember to go back and make the
original(s) more C-like after the holidays.
/
Leif
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 37/41] Compilation: Update the fdf, dsc and dec files.
2018-11-28 15:01 ` [PATCH edk2-platforms 37/41] Compilation: Update the fdf, dsc and dec files Meenakshi Aggarwal
@ 2018-12-21 18:51 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 18:51 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Vabhav
On Wed, Nov 28, 2018 at 08:31:51PM +0530, Meenakshi Aggarwal wrote:
> LS1043A PCIe compilation and update firmware device,
> description and declaration files.Defining Embedded Package
> PCD which should be at least 20 for 64K PCIe IO size required
> for CPU hob during PEI phase to Add IO space post PEI phase.
One change per patch please.
This one needs to be at least two.
/
Leif
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 16 ++++++++++++++++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 7 +++++++
> .../LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++
> .../LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
> Platform/NXP/NxpQoriqLs.dsc.inc | 2 ++
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 4 ++++
> Silicon/NXP/NxpQoriqLs.dec | 10 ++++++++++
> 7 files changed, 47 insertions(+)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> index b69ffa2..b43c81a 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -42,6 +42,8 @@
> BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf
> FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf
> NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
> + PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> + PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>
> [PcdsFixedAtBuild.common]
>
> @@ -74,6 +76,13 @@
> gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000
> gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000
>
> + #
> + # PCI PCDs.
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x10000
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x7FC
> +
> ################################################################################
> #
> # Components Section - list of all EDK II Modules needed by this Platform
> @@ -94,4 +103,11 @@
> Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
>
> + Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
> + }
> + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> ##
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> index 6b27aed..d02b3cc 100644
> --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> @@ -131,6 +131,13 @@ READ_LOCK_STATUS = TRUE
> INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
>
> #
> + # PCI
> + #
> + INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> + #
> # Network modules
> #
> INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> index 7feac56..f2c8b66 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> @@ -65,3 +65,5 @@
> gNxpQoriqLsTokenSpaceGuid.PcdDram3Size
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize
> diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> index 64c5612..1ef3292 100644
> --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> @@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap (
> VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> + // ROM Space
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdRomBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> // IFC region 1
> //
> // A-009241 : Unaligned write transactions to IFC may result in corruption of data
> diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
> index 5529a04..063d0b8 100644
> --- a/Platform/NXP/NxpQoriqLs.dsc.inc
> +++ b/Platform/NXP/NxpQoriqLs.dsc.inc
> @@ -245,6 +245,8 @@
>
> gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
>
> + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|20
> +
> #
> # Optional feature to help prevent EFI memory map fragments
> # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> index a4eb117..f3220fa 100644
> --- a/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> @@ -64,6 +64,9 @@
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3
> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
>
> #
> # Big Endian IPs
> @@ -71,5 +74,6 @@
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE
>
> ##
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index da148b7..aae0a34 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -78,6 +78,16 @@
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129
> gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0|UINT64|0x0000012B
> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x0|UINT64|0x0000012C
> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x0|UINT64|0x0000012D
> +
> + #
> + # PCI PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x000001D0
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x000001D1
> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE|BOOLEAN|0x000001D2
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|0|UINT32|0x000001D3
>
> #
> # IFC PCDs
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 38/41] DWC3 : Add DWC3 USB controller initialization driver.
2018-11-28 15:01 ` [PATCH edk2-platforms 38/41] DWC3 : Add DWC3 USB controller initialization driver Meenakshi Aggarwal
@ 2018-12-21 19:03 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 19:03 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Wed, Nov 28, 2018 at 08:31:52PM +0530, Meenakshi Aggarwal wrote:
> Add support of DWC3 controller driver which
> Performs DWC3 controller initialization and
> Register itself as NonDiscoverableMmioDevice
So this is just a platform hook to load a memory mapped USB
controller that turns Xhci compliant once properly enabled?
I'm not going to insist on it, but this looks like half of it should
go into Silicon/Synopsys, and the other half be part of the platform
initialisation library.
/
Leif
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c | 218 +++++++++++++++++++++++++++
> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h | 144 ++++++++++++++++++
> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf | 48 ++++++
> Silicon/NXP/NxpQoriqLs.dec | 5 +
> 4 files changed, 415 insertions(+)
> create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
> create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
> create mode 100644 Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
>
> diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
> new file mode 100644
> index 0000000..0a9c821
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.c
> @@ -0,0 +1,218 @@
> +/** @file
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/NonDiscoverableDeviceRegistrationLib.h>
> +
> +#include "UsbHcd.h"
> +
> +STATIC
> +VOID
> +XhciSetBeatBurstLength (
> + IN UINTN UsbReg
> + )
> +{
> + DWC3 *Dwc3Reg;
> +
> + Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET);
> +
> + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GSBusCfg0, ~USB3_ENABLE_BEAT_BURST_MASK,
> + USB3_ENABLE_BEAT_BURST);
> + MmioOr32 ((UINTN)&Dwc3Reg->GSBusCfg1, USB3_SET_BEAT_BURST_LIMIT);
> +
> + return;
> +}
> +
> +STATIC
> +VOID
> +Dwc3SetFladj (
> + IN DWC3 *Dwc3Reg,
> + IN UINT32 Val
> + )
> +{
> + MmioOr32 ((UINTN)&Dwc3Reg->GFLAdj, GFLADJ_30MHZ_REG_SEL |
> + GFLADJ_30MHZ(Val));
> +}
> +
> +VOID
> +Dwc3SetMode (
> + IN DWC3 *Dwc3Reg,
> + IN UINT32 Mode
> + )
> +{
> + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GCtl,
> + ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
> + DWC3_GCTL_PRTCAPDIR(Mode));
> +}
> +
> +STATIC
> +VOID
> +Dwc3CoreSoftReset (
> + IN DWC3 *Dwc3Reg
> + )
> +{
> + MmioOr32 ((UINTN)&Dwc3Reg->GCtl, DWC3_GCTL_CORESOFTRESET);
> + MmioOr32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
> + MmioOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
> + MmioAnd32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], ~DWC3_GUSB3PIPECTL_PHYSOFTRST);
> + MmioAnd32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg, ~DWC3_GUSB2PHYCFG_PHYSOFTRST);
> + MmioAnd32 ((UINTN)&Dwc3Reg->GCtl, ~DWC3_GCTL_CORESOFTRESET);
> +
> + return;
> +}
> +
> +STATIC
> +EFI_STATUS
> +Dwc3CoreInit (
> + IN DWC3 *Dwc3Reg
> + )
> +{
> + UINT32 Revision;
> + UINT32 Reg;
> + UINTN Dwc3Hwparams1;
> +
> + Revision = MmioRead32 ((UINTN)&Dwc3Reg->GSnpsId);
> + //
> + // This should read as 0x5533, ascii of U3(DWC_usb3) followed by revision number
> + //
> + if ((Revision & DWC3_GSNPSID_MASK) != DWC3_SYNOPSYS_ID) {
> + DEBUG ((DEBUG_ERROR,"This is not a DesignWare USB3 DRD Core.\n"));
> + return EFI_NOT_FOUND;
> + }
> +
> + Dwc3CoreSoftReset (Dwc3Reg);
> +
> + Reg = MmioRead32 ((UINTN)&Dwc3Reg->GCtl);
> + Reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
> + Reg &= ~DWC3_GCTL_DISSCRAMBLE;
> +
> + Dwc3Hwparams1 = MmioRead32 ((UINTN)&Dwc3Reg->GHwParams1);
> +
> + if (DWC3_GHWPARAMS1_EN_PWROPT(Dwc3Hwparams1) == DWC3_GHWPARAMS1_EN_PWROPT_CLK) {
> + Reg &= ~DWC3_GCTL_DSBLCLKGTNG;
> + } else {
> + DEBUG ((DEBUG_ERROR,"No power optimization available.\n"));
> + }
> +
> + if ((Revision & DWC3_RELEASE_MASK) < DWC3_RELEASE_190a) {
> + Reg |= DWC3_GCTL_U2RSTECN;
> + }
> +
> + MmioWrite32 ((UINTN)&Dwc3Reg->GCtl, Reg);
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +XhciCoreInit (
> + IN UINTN UsbReg
> + )
> +{
> + EFI_STATUS Status;
> + DWC3 *Dwc3Reg;
> +
> + Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET);
> +
> + Status = Dwc3CoreInit (Dwc3Reg);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "Dwc3CoreInit Failed for controller 0x%x (0x%x) \n",
> + UsbReg, Status));
> + return Status;
> + }
> +
> + Dwc3SetMode (Dwc3Reg, DWC3_GCTL_PRTCAP_HOST);
> +
> + Dwc3SetFladj (Dwc3Reg, GFLADJ_30MHZ_DEFAULT);
> +
> + return Status;
> +}
> +
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +InitializeUsbController (
> + IN UINTN UsbReg
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = XhciCoreInit (UsbReg);
> +
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Change beat burst and outstanding pipelined transfers requests
> + //
> + XhciSetBeatBurstLength (UsbReg);
> +
> + return Status;
> +}
> +
> +/**
> + The Entry Point of module. It follows the standard UEFI driver model.
> +
> + @param[in] ImageHandle The firmware allocated handle for the EFI image.
> + @param[in] SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The entry point is executed successfully.
> + @retval other Some error occurs when executing this entry point.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +InitializeUsbHcd (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + UINT32 NumUsbController;
> + UINT32 ControllerAddr;
> +
> + Status = EFI_SUCCESS;
> + NumUsbController = PcdGet32 (PcdNumUsbController);
> +
> + while (NumUsbController) {
> + NumUsbController--;
> + ControllerAddr = PcdGet32 (PcdUsbBaseAddr) +
> + (NumUsbController * PcdGet32 (PcdUsbSize));
> +
> + Status = InitializeUsbController (ControllerAddr);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "USB Controller initialization Failed for %d (0x%x)\n",
> + ControllerAddr, Status));
> + continue;
> + }
> +
> + Status = RegisterNonDiscoverableMmioDevice (
> + NonDiscoverableDeviceTypeXhci,
> + NonDiscoverableDeviceDmaTypeNonCoherent,
> + NULL,
> + NULL,
> + 1,
> + ControllerAddr, PcdGet32 (PcdUsbSize)
> + );
> +
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "Failed to register USB device (0x%x) with error 0x%x \n",
> + ControllerAddr, Status));
> + }
> + }
> +
> + return Status;
> +}
> diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
> new file mode 100644
> index 0000000..99d86dc
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.h
> @@ -0,0 +1,144 @@
> +/** @file
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef __USB_HCD__
> +#define __USB_HCD__
> +
> +#include <Base.h>
> +
> +/* Global constants */
> +#define DWC3_GSNPSID_MASK 0xffff0000
> +#define DWC3_SYNOPSYS_ID 0x55330000
> +#define DWC3_RELEASE_MASK 0xffff
> +#define DWC3_REG_OFFSET 0xC100
> +#define DWC3_RELEASE_190a 0x190a
> +
> +/* Global Configuration Register */
> +#define DWC3_GCTL_U2RSTECN BIT16
> +#define DWC3_GCTL_PRTCAPDIR(N) ((N) << 12)
> +#define DWC3_GCTL_PRTCAP_HOST 1
> +#define DWC3_GCTL_PRTCAP_OTG 3
> +#define DWC3_GCTL_CORESOFTRESET BIT11
> +#define DWC3_GCTL_SCALEDOWN(N) ((N) << 4)
> +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
> +#define DWC3_GCTL_DISSCRAMBLE BIT3
> +#define DWC3_GCTL_DSBLCLKGTNG BIT0
> +
> +/* Global HWPARAMS1 Register */
> +#define DWC3_GHWPARAMS1_EN_PWROPT(N) (((N) & (3 << 24)) >> 24)
> +#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
> +
> +/* Global USB2 PHY Configuration Register */
> +#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT31
> +
> +/* Global USB3 PIPE Control Register */
> +#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT31
> +
> +/* Global Frame Length Adjustment Register */
> +#define GFLADJ_30MHZ_REG_SEL BIT7
> +#define GFLADJ_30MHZ(N) ((N) & 0x3f)
> +#define GFLADJ_30MHZ_DEFAULT 0x20
> +
> +/* Default to the FSL XHCI defines */
> +#define USB3_ENABLE_BEAT_BURST 0xF
> +#define USB3_ENABLE_BEAT_BURST_MASK 0xFF
> +#define USB3_SET_BEAT_BURST_LIMIT 0xF00
> +
> +typedef struct {
> + UINT32 GEvntAdrLo;
> + UINT32 GEvntAdrHi;
> + UINT32 GEvntSiz;
> + UINT32 GEvntCount;
> +} G_EVENT_BUFFER;
> +
> +typedef struct {
> + UINT32 DDepCmdPar2;
> + UINT32 DDepCmdPar1;
> + UINT32 DDepCmdPar0;
> + UINT32 DDepCmd;
> +} D_PHYSICAL_EP;
> +
> +typedef struct {
> + UINT32 GSBusCfg0;
> + UINT32 GSBusCfg1;
> + UINT32 GTxThrCfg;
> + UINT32 GRxThrCfg;
> + UINT32 GCtl;
> + UINT32 Res1;
> + UINT32 GSts;
> + UINT32 Res2;
> + UINT32 GSnpsId;
> + UINT32 GGpio;
> + UINT32 GUid;
> + UINT32 GUctl;
> + UINT64 GBusErrAddr;
> + UINT64 GPrtbImap;
> + UINT32 GHwParams0;
> + UINT32 GHwParams1;
> + UINT32 GHwParams2;
> + UINT32 GHwParams3;
> + UINT32 GHwParams4;
> + UINT32 GHwParams5;
> + UINT32 GHwParams6;
> + UINT32 GHwParams7;
> + UINT32 GDbgFifoSpace;
> + UINT32 GDbgLtssm;
> + UINT32 GDbgLnmcc;
> + UINT32 GDbgBmu;
> + UINT32 GDbgLspMux;
> + UINT32 GDbgLsp;
> + UINT32 GDbgEpInfo0;
> + UINT32 GDbgEpInfo1;
> + UINT64 GPrtbImapHs;
> + UINT64 GPrtbImapFs;
> + UINT32 Res3[28];
> + UINT32 GUsb2PhyCfg[16];
> + UINT32 GUsb2I2cCtl[16];
> + UINT32 GUsb2PhyAcc[16];
> + UINT32 GUsb3PipeCtl[16];
> + UINT32 GTxFifoSiz[32];
> + UINT32 GRxFifoSiz[32];
> + G_EVENT_BUFFER GEvntBuf[32];
> + UINT32 GHwParams8;
> + UINT32 Res4[11];
> + UINT32 GFLAdj;
> + UINT32 Res5[51];
> + UINT32 DCfg;
> + UINT32 DCtl;
> + UINT32 DEvten;
> + UINT32 DSts;
> + UINT32 DGCmdPar;
> + UINT32 DGCmd;
> + UINT32 Res6[2];
> + UINT32 DAlepena;
> + UINT32 Res7[55];
> + D_PHYSICAL_EP DPhyEpCmd[32];
> + UINT32 Res8[128];
> + UINT32 OCfg;
> + UINT32 OCtl;
> + UINT32 OEvt;
> + UINT32 OEvtEn;
> + UINT32 OSts;
> + UINT32 Res9[3];
> + UINT32 AdpCfg;
> + UINT32 AdpCtl;
> + UINT32 AdpEvt;
> + UINT32 AdpEvten;
> + UINT32 BcCfg;
> + UINT32 Res10;
> + UINT32 BcEvt;
> + UINT32 BcEvten;
> +} DWC3;
> +
> +#endif
> diff --git a/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
> new file mode 100644
> index 0000000..ac74bc6
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
> @@ -0,0 +1,48 @@
> +# UsbHcd.inf
> +#
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001a
> + BASE_NAME = UsbHcdDxe
> + FILE_GUID = 196e7c2a-37b2-4b85-8683-718588952449
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = InitializeUsbHcd
> +
> +[Sources.common]
> + UsbHcd.c
> +
> +[Packages]
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + DebugLib
> + IoLib
> + MemoryAllocationLib
> + NonDiscoverableDeviceRegistrationLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> +
> +[FixedPcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController
> + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize
> +
> +[Depex]
> + TRUE
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> index aae0a34..dd2c314 100644
> --- a/Silicon/NXP/NxpQoriqLs.dec
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -82,6 +82,11 @@
> gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x0|UINT64|0x0000012D
>
> #
> + # USB PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|0|UINT32|0x00000170
> +
> + #
> # PCI PCDs
> #
> gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x000001D0
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 40/41] Platform/NXP:PCIe enablement for LS1046A RDB
2018-11-28 15:01 ` [PATCH edk2-platforms 40/41] Platform/NXP:PCIe enablement for LS1046A RDB Meenakshi Aggarwal
@ 2018-12-21 19:05 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 19:05 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Vabhav
On Wed, Nov 28, 2018 at 08:31:54PM +0530, Meenakshi Aggarwal wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Compilation: Update the fdf, dsc and dec files.
The diffstat below tells me that. The commit message is supposed to
tell me what is changed, and why.
/
Leif
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 15 +++++++++++++++
> Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 7 +++++++
> .../LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++
> .../NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
> Silicon/NXP/LS1046A/LS1046A.dsc.inc | 3 +++
> 5 files changed, 33 insertions(+)
>
> diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> index 7eb08a9..57f2043 100644
> --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc
> @@ -41,6 +41,8 @@
> IfcLib|Silicon/NXP/Library/IfcLib/IfcLib.inf
> BoardLib|Platform/NXP/LS1046aRdbPkg/Library/BoardLib/BoardLib.inf
> FpgaLib|Silicon/NXP/Library/FpgaLib/FpgaLib.inf
> + PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> + PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>
> [PcdsFixedAtBuild.common]
>
> @@ -65,6 +67,7 @@
> gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE
>
> #
> # RTC Pcds
> @@ -72,6 +75,12 @@
> gPcf2129RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
> gPcf2129RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
>
> + #
> + # PCI PCDs.
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x80000
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC
> ################################################################################
> #
> # Components Section - list of all EDK II Modules needed by this Platform
> @@ -85,6 +94,12 @@
>
> Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> + Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
> + }
> + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
>
> Platform/NXP/LS1046aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> ##
> diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> index 443b561..887f386 100644
> --- a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf
> @@ -124,6 +124,13 @@ READ_LOCK_STATUS = TRUE
> INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
>
> #
> + # PCI
> + #
> + INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> + #
> # Network modules
> #
> INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> index 49b57fc..5e09757 100644
> --- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> @@ -42,6 +42,8 @@
> gArmTokenSpaceGuid.PcdArmPrimaryCore
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
> diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> index 64c5612..1ef3292 100644
> --- a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> @@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap (
> VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> + // ROM Space
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdRomBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> // IFC region 1
> //
> // A-009241 : Unaligned write transactions to IFC may result in corruption of data
> diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> index 9f87028..59a6150 100644
> --- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> +++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
> @@ -64,5 +64,8 @@
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3
> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
>
> ##
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 41/41] Platform/NXP:PCIe enablement for LS2088A RDB
2018-11-28 15:01 ` [PATCH edk2-platforms 41/41] Platform/NXP:PCIe enablement for LS2088A RDB Meenakshi Aggarwal
@ 2018-12-21 19:05 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 19:05 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi,
Vabhav
On Wed, Nov 28, 2018 at 08:31:55PM +0530, Meenakshi Aggarwal wrote:
> From: Vabhav <vabhav.sharma@nxp.com>
>
> Compilation: Update the fdf, dsc and dec files.
Please add a commit message. This isn't one.
/
Leif
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Vabhav <vabhav.sharma@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc | 17 +++++++++++++++++
> Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf | 7 +++++++
> .../Library/PlatformLib/ArmPlatformLib.inf | 2 ++
> .../LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++
> Silicon/NXP/LS2088A/LS2088A.dsc.inc | 3 +++
> 5 files changed, 35 insertions(+)
>
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> index e074991..aefc214 100755
> --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.dsc
> @@ -43,6 +43,8 @@
> BoardLib|Platform/NXP/LS2088aRdbPkg/Library/BoardLib/BoardLib.inf
> FpgaLib|Platform/NXP/LS2088aRdbPkg/Library/FpgaLib/FpgaLib.inf
> NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf
> + PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf
> + PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf
>
> [PcdsFixedAtBuild.common]
>
> @@ -92,6 +94,13 @@
> gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x580000000
> gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x580300000
>
> + #
> + # PCI PCDs.
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x80000
> + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x407FC
> +
> ################################################################################
> #
> # Components Section - list of all EDK II Modules needed by this Platform
> @@ -111,3 +120,11 @@
> Platform/NXP/LS2088aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
> Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf
> + Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
> + <PcdsFixedAtBuild>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F
> + }
> + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> + ##
> diff --git a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> index 62f084d..d32c5a0 100644
> --- a/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> +++ b/Platform/NXP/LS2088aRdbPkg/LS2088aRdbPkg.fdf
> @@ -129,6 +129,13 @@ READ_LOCK_STATUS = TRUE
> INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf
>
> #
> + # PCI
> + #
> + INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
> + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> +
> + #
> # Network modules
> #
> INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> index f5e5abd..0b836a8 100644
> --- a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> @@ -44,6 +44,8 @@
> gArmTokenSpaceGuid.PcdArmPrimaryCore
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
> gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
> diff --git a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> index ccb49f6..8b2145b 100644
> --- a/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> +++ b/Platform/NXP/LS2088aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> @@ -80,6 +80,12 @@ ArmPlatformGetVirtualMemoryMap (
> VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>
> + // ROM Space
> + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr);
> + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdRomBaseAddr);
> + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> // IFC region 1
> //
> // A-009241 : Unaligned write transactions to IFC may result in corruption of data
> diff --git a/Silicon/NXP/LS2088A/LS2088A.dsc.inc b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
> index 0d8fd82..831edea 100644
> --- a/Silicon/NXP/LS2088A/LS2088A.dsc.inc
> +++ b/Silicon/NXP/LS2088A/LS2088A.dsc.inc
> @@ -69,5 +69,8 @@
> gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x02240000
> gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController|2
> + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|4
> + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000
> + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000
>
> ##
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/41] Silicon/NXP: Add Library to return Mmio APIs pointer
2018-11-28 15:01 ` [PATCH edk2-platforms 01/41] Silicon/NXP: Add Library to return Mmio APIs pointer Meenakshi Aggarwal
@ 2018-12-21 19:17 ` Leif Lindholm
2018-12-26 5:00 ` Meenakshi Aggarwal
0 siblings, 1 reply; 254+ messages in thread
From: Leif Lindholm @ 2018-12-21 19:17 UTC (permalink / raw)
To: Meenakshi Aggarwal
Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, udit.kumar, v.sethi
On Wed, Nov 28, 2018 at 08:31:15PM +0530, Meenakshi Aggarwal wrote:
> This library add supports to return pointer to
> MMIO APIs on basis of Swap flag.
> If Flag is True then MMION APIs returened in which data
> swapped after reading from MMIO and before write using MMIO.
I conspicuously left this one for last.
First thing I would like to see is splitting the setting up of
function pointers bit from the actual I/O accesses (separate patches).
The I/O functions belong in edk2 MdeModulePkg (or possibly
EmbeddedPkg, of for some reason they don't want it in MdePkg).
But regardless, please send that as a separate patch, preceding the
edk2-platforms set.
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/Library/IoAccessLib.h | 332 +++++++++++++++++++
> Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 410 ++++++++++++++++++++++++
> Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf | 32 ++
> 3 files changed, 774 insertions(+)
> create mode 100644 Silicon/NXP/Include/Library/IoAccessLib.h
> create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
>
> diff --git a/Silicon/NXP/Include/Library/IoAccessLib.h b/Silicon/NXP/Include/Library/IoAccessLib.h
> new file mode 100644
> index 0000000..f7372a5
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/IoAccessLib.h
> @@ -0,0 +1,332 @@
> +/** @file
> + *
> + * Copyright 2017 NXP
> + *
> + * This program and the accompanying materials
> + * are licensed and made available under the terms and conditions of the BSD License
> + * which accompanies this distribution. The full text of the license may be found at
> + * http://opensource.org/licenses/bsd-license.php
> + *
> + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> + *
> + **/
> +
> +#ifndef __IO_ACCESS_LIB_H__
> +#define __IO_ACCESS_LIB_H__
> +
> +#include <Base.h>
> +
> +///
> +/// Structure to have pointer to R/W
> +/// Mmio operations for 16 bits.
> +///
> +typedef struct _MMIO_OPERATIONS_16 {
> + UINT16 (*Read) (UINTN Address);
> + UINT16 (*Write) (UINTN Address, UINT16 Value);
> + UINT16 (*Or) (UINTN Address, UINT16 Or);
> + UINT16 (*And) (UINTN Address, UINT16 AND);
> + UINT16 (*AndThenOr) (UINTN Address, UINT16 And, UINT16 Or);
> +} MMIO_OPERATIONS_16;
I have sort of hinted at this in earlier comments on this set:
Why separate structs for different access sizes?
I don't expect there will be a noticeable image size or performance
difference if they are all put into one structure. And if there is. we
can conditionalise the inclusion of different widths with FixedPcds.
So I would like for just a single GetMmioOperations() function that
returns a single struct. And I would like for the member functions to
have the access size as the suffix to their names, just like the
regular IoLib functions.
> +
> +///
> +/// Structure to have pointer to R/W
> +/// Mmio operations for 32 bits.
> +///
> +typedef struct _MMIO_OPERATIONS_32 {
> + UINT32 (*Read) (UINTN Address);
> + UINT32 (*Write) (UINTN Address, UINT32 Value);
> + UINT32 (*Or) (UINTN Address, UINT32 Or);
> + UINT32 (*And) (UINTN Address, UINT32 AND);
> + UINT32 (*AndThenOr) (UINTN Address, UINT32 And, UINT32 Or);
> +} MMIO_OPERATIONS_32;
> +
> +///
> +/// Structure to have pointer to R/W
> +/// Mmio operations for 64 bits.
> +///
> +typedef struct _MMIO_OPERATIONS_64 {
> + UINT64 (*Read) (UINTN Address);
> + UINT64 (*Write) (UINTN Address, UINT64 Value);
> + UINT64 (*Or) (UINTN Address, UINT64 Or);
> + UINT64 (*And) (UINTN Address, UINT64 AND);
> + UINT64 (*AndThenOr) (UINTN Address, UINT64 And, UINT64 Or);
> +} MMIO_OPERATIONS_64;
> +
> +/**
> + Function to return pointer to 16 bit Mmio operations.
> +
> + @param Swap Flag to tell if Swap is needed or not
> + on Mmio Operations.
> +
> + @return Pointer to Mmio Operations.
> +
> +**/
> +MMIO_OPERATIONS_16 *
> +GetMmioOperations16 (
> + IN BOOLEAN Swap
> + );
> +
> +/**
> + Function to return pointer to 32 bit Mmio operations.
> +
> + @param Swap Flag to tell if Swap is needed or not
> + on Mmio Operations.
> +
> + @return Pointer to Mmio Operations.
> +
> +**/
> +MMIO_OPERATIONS_32 *
> +GetMmioOperations32 (
> + IN BOOLEAN Swap
> + );
> +
> +/**
> + Function to return pointer to 64 bit Mmio operations.
> +
> + @param Swap Flag to tell if Swap is needed or not
> + on Mmio Operations.
> +
> + @return Pointer to Mmio Operations.
> +
> +**/
> +MMIO_OPERATIONS_64 *
> +GetMmioOperations64 (
> + IN BOOLEAN Swap
> + );
> +
> +/**
> + MmioRead16 for Big-Endian modules.
There is nothing inherently Big-Endian about this.
It is byte-swapping.
This concludes my review of this set, and I will now disappear on
holiday until 7 January.
Best Regards,
Leif
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioRead16 (
> + IN UINTN Address
> + );
> +
> +/**
> + MmioRead32 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioRead32 (
> + IN UINTN Address
> + );
> +
> +/**
> + MmioRead64 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioRead64 (
> + IN UINTN Address
> + );
> +
> +/**
> + MmioWrite16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioWrite16 (
> + IN UINTN Address,
> + IN UINT16 Value
> + );
> +
> +/**
> + MmioWrite32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + );
> +
> +/**
> + MmioWrite64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioWrite64 (
> + IN UINTN Address,
> + IN UINT64 Value
> + );
> +
> +/**
> + MmioAndThenOr16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioAndThenOr16 (
> + IN UINTN Address,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + );
> +
> +/**
> + MmioAndThenOr32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioAndThenOr32 (
> + IN UINTN Address,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + );
> +
> +/**
> + MmioAndThenOr64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioAndThenOr64 (
> + IN UINTN Address,
> + IN UINT64 AndData,
> + IN UINT64 OrData
> + );
> +
> +/**
> + MmioOr16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioOr16 (
> + IN UINTN Address,
> + IN UINT16 OrData
> + );
> +
> +/**
> + MmioOr32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioOr32 (
> + IN UINTN Address,
> + IN UINT32 OrData
> + );
> +
> +/**
> + MmioOr64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioOr64 (
> + IN UINTN Address,
> + IN UINT64 OrData
> + );
> +
> +/**
> + MmioAnd16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioAnd16 (
> + IN UINTN Address,
> + IN UINT16 AndData
> + );
> +
> +/**
> + MmioAnd32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioAnd32 (
> + IN UINTN Address,
> + IN UINT32 AndData
> + );
> +
> +/**
> + MmioAnd64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioAnd64 (
> + IN UINTN Address,
> + IN UINT64 AndData
> + );
> +
> +#endif /* __IO_ACCESS_LIB_H__ */
> diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> new file mode 100644
> index 0000000..0260777
> --- /dev/null
> +++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> @@ -0,0 +1,410 @@
> +/** IoAccessLib.c
> +
> + Provide MMIO APIs for BE modules.
> +
> + Copyright 2017 NXP
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/IoLib.h>
> +
> +/**
> + MmioRead16 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioRead16 (
> + IN UINTN Address
> + )
> +{
> + return SwapBytes16 (MmioRead16 (Address));
> +}
> +
> +/**
> + MmioRead32 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioRead32 (
> + IN UINTN Address
> + )
> +{
> + return SwapBytes32 (MmioRead32 (Address));
> +}
> +
> +/**
> + MmioRead64 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioRead64 (
> + IN UINTN Address
> + )
> +{
> + return SwapBytes64 (MmioRead64 (Address));
> +}
> +
> +/**
> + MmioWrite16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioWrite16 (
> + IN UINTN Address,
> + IN UINT16 Value
> + )
> +{
> + return MmioWrite16 (Address, SwapBytes16 (Value));
> +}
> +
> +/**
> + MmioWrite32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + return MmioWrite32 (Address, SwapBytes32 (Value));
> +}
> +
> +/**
> + MmioWrite64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioWrite64 (
> + IN UINTN Address,
> + IN UINT64 Value
> + )
> +{
> + return MmioWrite64 (Address, SwapBytes64 (Value));
> +}
> +
> +/**
> + MmioAndThenOr16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioAndThenOr16 (
> + IN UINTN Address,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + )
> +{
> + AndData = SwapBytes16 (AndData);
> + OrData = SwapBytes16 (OrData);
> +
> + return MmioAndThenOr16 (Address, AndData, OrData);
> +}
> +
> +/**
> + MmioAndThenOr32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioAndThenOr32 (
> + IN UINTN Address,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + )
> +{
> + AndData = SwapBytes32 (AndData);
> + OrData = SwapBytes32 (OrData);
> +
> + return MmioAndThenOr32 (Address, AndData, OrData);
> +}
> +
> +/**
> + MmioAndThenOr64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioAndThenOr64 (
> + IN UINTN Address,
> + IN UINT64 AndData,
> + IN UINT64 OrData
> + )
> +{
> + AndData = SwapBytes64 (AndData);
> + OrData = SwapBytes64 (OrData);
> +
> + return MmioAndThenOr64 (Address, AndData, OrData);
> +}
> +
> +/**
> + MmioOr16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioOr16 (
> + IN UINTN Address,
> + IN UINT16 OrData
> + )
> +{
> + return MmioOr16 (Address, SwapBytes16 (OrData));
> +}
> +
> +/**
> + MmioOr32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioOr32 (
> + IN UINTN Address,
> + IN UINT32 OrData
> + )
> +{
> + return MmioOr32 (Address, SwapBytes32 (OrData));
> +}
> +
> +/**
> + MmioOr64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioOr64 (
> + IN UINTN Address,
> + IN UINT64 OrData
> + )
> +{
> + return MmioOr64 (Address, SwapBytes64 (OrData));
> +}
> +
> +/**
> + MmioAnd16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioAnd16 (
> + IN UINTN Address,
> + IN UINT16 AndData
> + )
> +{
> + return MmioAnd16 (Address, SwapBytes16 (AndData));
> +}
> +
> +/**
> + MmioAnd32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioAnd32 (
> + IN UINTN Address,
> + IN UINT32 AndData
> + )
> +{
> + return MmioAnd32 (Address, SwapBytes32 (AndData));
> +}
> +
> +/**
> + MmioAnd64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioAnd64 (
> + IN UINTN Address,
> + IN UINT64 AndData
> + )
> +{
> + return MmioAnd64 (Address, SwapBytes64 (AndData));
> +}
> +
> +STATIC MMIO_OPERATIONS_16 SwappingFunctions16 = {
> + SwapMmioRead16,
> + SwapMmioWrite16,
> + SwapMmioOr16,
> + SwapMmioAnd16,
> + SwapMmioAndThenOr16,
> +};
> +
> +STATIC MMIO_OPERATIONS_16 NonSwappingFunctions16 = {
> + MmioRead16,
> + MmioWrite16,
> + MmioOr16,
> + MmioAnd16,
> + MmioAndThenOr16,
> +};
> +
> +STATIC MMIO_OPERATIONS_32 SwappingFunctions32 = {
> + SwapMmioRead32,
> + SwapMmioWrite32,
> + SwapMmioOr32,
> + SwapMmioAnd32,
> + SwapMmioAndThenOr32,
> +};
> +
> +STATIC MMIO_OPERATIONS_32 NonSwappingFunctions32 = {
> + MmioRead32,
> + MmioWrite32,
> + MmioOr32,
> + MmioAnd32,
> + MmioAndThenOr32,
> +};
> +
> +STATIC MMIO_OPERATIONS_64 SwappingFunctions64 = {
> + SwapMmioRead64,
> + SwapMmioWrite64,
> + SwapMmioOr64,
> + SwapMmioAnd64,
> + SwapMmioAndThenOr64,
> +};
> +
> +STATIC MMIO_OPERATIONS_64 NonSwappingFunctions64 = {
> + MmioRead64,
> + MmioWrite64,
> + MmioOr64,
> + MmioAnd64,
> + MmioAndThenOr64,
> +};
> +
> +/**
> + Function to return pointer to 16 bit Mmio operations.
> +
> + @param Swap Flag to tell if Swap is needed or not
> + on Mmio Operations.
> +
> + @return Pointer to Mmio Operations.
> +
> +**/
> +MMIO_OPERATIONS_16 *
> +GetMmioOperations16 (BOOLEAN Swap) {
> + if (Swap) {
> + return &SwappingFunctions16;
> + } else {
> + return &NonSwappingFunctions16;
> + }
> +}
> +
> +/**
> + Function to return pointer to 32 bit Mmio operations.
> +
> + @param Swap Flag to tell if Swap is needed or not
> + on Mmio Operations.
> +
> + @return Pointer to Mmio Operations.
> +
> +**/
> +MMIO_OPERATIONS_32 *
> +GetMmioOperations32 (BOOLEAN Swap) {
> + if (Swap) {
> + return &SwappingFunctions32;
> + } else {
> + return &NonSwappingFunctions32;
> + }
> +}
> +
> +/**
> + Function to return pointer to 64 bit Mmio operations.
> +
> + @param Swap Flag to tell if Swap is needed or not
> + on Mmio Operations.
> +
> + @return Pointer to Mmio Operations.
> +
> +**/
> +MMIO_OPERATIONS_64 *
> +GetMmioOperations64 (BOOLEAN Swap) {
> + if (Swap) {
> + return &SwappingFunctions64;
> + } else {
> + return &NonSwappingFunctions64;
> + }
> +}
> diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> new file mode 100644
> index 0000000..e2e7606
> --- /dev/null
> +++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> @@ -0,0 +1,32 @@
> +## @IoAccessLib.inf
> +
> +# Copyright 2017 NXP
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = IoAccessLib
> + FILE_GUID = 28d77333-77eb-4faf-8735-130e5eb3e343
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = IoAccessLib
> +
> +[Sources.common]
> + IoAccessLib.c
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + IoLib
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/41] Silicon/NXP: Add Library to return Mmio APIs pointer
2018-12-21 19:17 ` Leif Lindholm
@ 2018-12-26 5:00 ` Meenakshi Aggarwal
0 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2018-12-26 5:00 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
edk2-devel@lists.01.org, Udit Kumar, Varun Sethi
Thank you Ard and Leif for all the comments, we will work on your review comments and share the next version soon.
> -----Original Message-----
> From: Leif Lindholm <leif.lindholm@linaro.org>
> Sent: Saturday, December 22, 2018 12:48 AM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; michael.d.kinney@intel.com; edk2-
> devel@lists.01.org; Udit Kumar <udit.kumar@nxp.com>; Varun Sethi
> <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms 01/41] Silicon/NXP: Add Library to return
> Mmio APIs pointer
>
> On Wed, Nov 28, 2018 at 08:31:15PM +0530, Meenakshi Aggarwal wrote:
> > This library add supports to return pointer to MMIO APIs on basis of
> > Swap flag.
> > If Flag is True then MMION APIs returened in which data swapped after
> > reading from MMIO and before write using MMIO.
>
> I conspicuously left this one for last.
>
> First thing I would like to see is splitting the setting up of function pointers bit
> from the actual I/O accesses (separate patches).
>
> The I/O functions belong in edk2 MdeModulePkg (or possibly EmbeddedPkg, of
> for some reason they don't want it in MdePkg).
> But regardless, please send that as a separate patch, preceding the edk2-
> platforms set.
>
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> > ---
> > Silicon/NXP/Include/Library/IoAccessLib.h | 332 +++++++++++++++++++
> > Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 410
> ++++++++++++++++++++++++
> > Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf | 32 ++
> > 3 files changed, 774 insertions(+)
> > create mode 100644 Silicon/NXP/Include/Library/IoAccessLib.h
> > create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> > create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> >
> > diff --git a/Silicon/NXP/Include/Library/IoAccessLib.h
> > b/Silicon/NXP/Include/Library/IoAccessLib.h
> > new file mode 100644
> > index 0000000..f7372a5
> > --- /dev/null
> > +++ b/Silicon/NXP/Include/Library/IoAccessLib.h
> > @@ -0,0 +1,332 @@
> > +/** @file
> > + *
> > + * Copyright 2017 NXP
> > + *
> > + * This program and the accompanying materials
> > + * are licensed and made available under the terms and conditions of
> > +the BSD License
> > + * which accompanies this distribution. The full text of the
> > +license may be found at
> > + *
> > +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> > +nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi
> >
> +.aggarwal%40nxp.com%7C7d85cd38d02e4e6bbdc208d6677905c6%7C686ea1d
> 3bc2b
> >
> +4c6fa92cd99c5c301635%7C0%7C0%7C636810166817008412&sdata=OU
> EJ2URy5
> > +LX7wpvNs9f%2BK01Q1nahX2nWPNO67yOT57M%3D&reserved=0
> > + *
> > + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > +BASIS,
> > + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > + *
> > + **/
> > +
> > +#ifndef __IO_ACCESS_LIB_H__
> > +#define __IO_ACCESS_LIB_H__
> > +
> > +#include <Base.h>
> > +
> > +///
> > +/// Structure to have pointer to R/W /// Mmio operations for 16
> > +bits.
> > +///
> > +typedef struct _MMIO_OPERATIONS_16 {
> > + UINT16 (*Read) (UINTN Address);
> > + UINT16 (*Write) (UINTN Address, UINT16 Value);
> > + UINT16 (*Or) (UINTN Address, UINT16 Or);
> > + UINT16 (*And) (UINTN Address, UINT16 AND);
> > + UINT16 (*AndThenOr) (UINTN Address, UINT16 And, UINT16 Or); }
> > +MMIO_OPERATIONS_16;
>
> I have sort of hinted at this in earlier comments on this set:
>
> Why separate structs for different access sizes?
> I don't expect there will be a noticeable image size or performance difference if
> they are all put into one structure. And if there is. we can conditionalise the
> inclusion of different widths with FixedPcds.
>
> So I would like for just a single GetMmioOperations() function that returns a
> single struct. And I would like for the member functions to have the access size
> as the suffix to their names, just like the regular IoLib functions.
>
> > +
> > +///
> > +/// Structure to have pointer to R/W /// Mmio operations for 32
> > +bits.
> > +///
> > +typedef struct _MMIO_OPERATIONS_32 {
> > + UINT32 (*Read) (UINTN Address);
> > + UINT32 (*Write) (UINTN Address, UINT32 Value);
> > + UINT32 (*Or) (UINTN Address, UINT32 Or);
> > + UINT32 (*And) (UINTN Address, UINT32 AND);
> > + UINT32 (*AndThenOr) (UINTN Address, UINT32 And, UINT32 Or); }
> > +MMIO_OPERATIONS_32;
> > +
> > +///
> > +/// Structure to have pointer to R/W /// Mmio operations for 64
> > +bits.
> > +///
> > +typedef struct _MMIO_OPERATIONS_64 {
> > + UINT64 (*Read) (UINTN Address);
> > + UINT64 (*Write) (UINTN Address, UINT64 Value);
> > + UINT64 (*Or) (UINTN Address, UINT64 Or);
> > + UINT64 (*And) (UINTN Address, UINT64 AND);
> > + UINT64 (*AndThenOr) (UINTN Address, UINT64 And, UINT64 Or); }
> > +MMIO_OPERATIONS_64;
> > +
> > +/**
> > + Function to return pointer to 16 bit Mmio operations.
> > +
> > + @param Swap Flag to tell if Swap is needed or not
> > + on Mmio Operations.
> > +
> > + @return Pointer to Mmio Operations.
> > +
> > +**/
> > +MMIO_OPERATIONS_16 *
> > +GetMmioOperations16 (
> > + IN BOOLEAN Swap
> > + );
> > +
> > +/**
> > + Function to return pointer to 32 bit Mmio operations.
> > +
> > + @param Swap Flag to tell if Swap is needed or not
> > + on Mmio Operations.
> > +
> > + @return Pointer to Mmio Operations.
> > +
> > +**/
> > +MMIO_OPERATIONS_32 *
> > +GetMmioOperations32 (
> > + IN BOOLEAN Swap
> > + );
> > +
> > +/**
> > + Function to return pointer to 64 bit Mmio operations.
> > +
> > + @param Swap Flag to tell if Swap is needed or not
> > + on Mmio Operations.
> > +
> > + @return Pointer to Mmio Operations.
> > +
> > +**/
> > +MMIO_OPERATIONS_64 *
> > +GetMmioOperations64 (
> > + IN BOOLEAN Swap
> > + );
> > +
> > +/**
> > + MmioRead16 for Big-Endian modules.
>
> There is nothing inherently Big-Endian about this.
> It is byte-swapping.
>
> This concludes my review of this set, and I will now disappear on holiday until 7
> January.
>
> Best Regards,
>
> Leif
>
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +SwapMmioRead16 (
> > + IN UINTN Address
> > + );
> > +
> > +/**
> > + MmioRead32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +SwapMmioRead32 (
> > + IN UINTN Address
> > + );
> > +
> > +/**
> > + MmioRead64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +SwapMmioRead64 (
> > + IN UINTN Address
> > + );
> > +
> > +/**
> > + MmioWrite16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +SwapMmioWrite16 (
> > + IN UINTN Address,
> > + IN UINT16 Value
> > + );
> > +
> > +/**
> > + MmioWrite32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +SwapMmioWrite32 (
> > + IN UINTN Address,
> > + IN UINT32 Value
> > + );
> > +
> > +/**
> > + MmioWrite64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +SwapMmioWrite64 (
> > + IN UINTN Address,
> > + IN UINT64 Value
> > + );
> > +
> > +/**
> > + MmioAndThenOr16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > + @param OrData The value to OR with the result of the AND operation.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +SwapMmioAndThenOr16 (
> > + IN UINTN Address,
> > + IN UINT16 AndData,
> > + IN UINT16 OrData
> > + );
> > +
> > +/**
> > + MmioAndThenOr32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > + @param OrData The value to OR with the result of the AND operation.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +SwapMmioAndThenOr32 (
> > + IN UINTN Address,
> > + IN UINT32 AndData,
> > + IN UINT32 OrData
> > + );
> > +
> > +/**
> > + MmioAndThenOr64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > + @param OrData The value to OR with the result of the AND operation.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +SwapMmioAndThenOr64 (
> > + IN UINTN Address,
> > + IN UINT64 AndData,
> > + IN UINT64 OrData
> > + );
> > +
> > +/**
> > + MmioOr16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param OrData The value to OR with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +SwapMmioOr16 (
> > + IN UINTN Address,
> > + IN UINT16 OrData
> > + );
> > +
> > +/**
> > + MmioOr32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param OrData The value to OR with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +SwapMmioOr32 (
> > + IN UINTN Address,
> > + IN UINT32 OrData
> > + );
> > +
> > +/**
> > + MmioOr64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param OrData The value to OR with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +SwapMmioOr64 (
> > + IN UINTN Address,
> > + IN UINT64 OrData
> > + );
> > +
> > +/**
> > + MmioAnd16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +SwapMmioAnd16 (
> > + IN UINTN Address,
> > + IN UINT16 AndData
> > + );
> > +
> > +/**
> > + MmioAnd32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +SwapMmioAnd32 (
> > + IN UINTN Address,
> > + IN UINT32 AndData
> > + );
> > +
> > +/**
> > + MmioAnd64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +SwapMmioAnd64 (
> > + IN UINTN Address,
> > + IN UINT64 AndData
> > + );
> > +
> > +#endif /* __IO_ACCESS_LIB_H__ */
> > diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> > b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> > new file mode 100644
> > index 0000000..0260777
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> > @@ -0,0 +1,410 @@
> > +/** IoAccessLib.c
> > +
> > + Provide MMIO APIs for BE modules.
> > +
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials are licensed and made
> > + available under the terms and conditions of the BSD License which
> > + accompanies this distribution. The full text of the license may be
> > + found at
> > +
> > + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop
> > + ensource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenaks
> > +
> hi.aggarwal%40nxp.com%7C7d85cd38d02e4e6bbdc208d6677905c6%7C686ea1
> d3b
> > +
> c2b4c6fa92cd99c5c301635%7C0%7C0%7C636810166817008412&sdata=O
> UEJ2
> > + URy5LX7wpvNs9f%2BK01Q1nahX2nWPNO67yOT57M%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#include <Base.h>
> > +#include <Library/BaseLib.h>
> > +#include <Library/IoAccessLib.h>
> > +#include <Library/IoLib.h>
> > +
> > +/**
> > + MmioRead16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +SwapMmioRead16 (
> > + IN UINTN Address
> > + )
> > +{
> > + return SwapBytes16 (MmioRead16 (Address)); }
> > +
> > +/**
> > + MmioRead32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +SwapMmioRead32 (
> > + IN UINTN Address
> > + )
> > +{
> > + return SwapBytes32 (MmioRead32 (Address)); }
> > +
> > +/**
> > + MmioRead64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to read.
> > +
> > + @return The value read.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +SwapMmioRead64 (
> > + IN UINTN Address
> > + )
> > +{
> > + return SwapBytes64 (MmioRead64 (Address)); }
> > +
> > +/**
> > + MmioWrite16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +SwapMmioWrite16 (
> > + IN UINTN Address,
> > + IN UINT16 Value
> > + )
> > +{
> > + return MmioWrite16 (Address, SwapBytes16 (Value)); }
> > +
> > +/**
> > + MmioWrite32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +SwapMmioWrite32 (
> > + IN UINTN Address,
> > + IN UINT32 Value
> > + )
> > +{
> > + return MmioWrite32 (Address, SwapBytes32 (Value)); }
> > +
> > +/**
> > + MmioWrite64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param Value The value to write to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +SwapMmioWrite64 (
> > + IN UINTN Address,
> > + IN UINT64 Value
> > + )
> > +{
> > + return MmioWrite64 (Address, SwapBytes64 (Value)); }
> > +
> > +/**
> > + MmioAndThenOr16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > + @param OrData The value to OR with the result of the AND operation.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +SwapMmioAndThenOr16 (
> > + IN UINTN Address,
> > + IN UINT16 AndData,
> > + IN UINT16 OrData
> > + )
> > +{
> > + AndData = SwapBytes16 (AndData);
> > + OrData = SwapBytes16 (OrData);
> > +
> > + return MmioAndThenOr16 (Address, AndData, OrData); }
> > +
> > +/**
> > + MmioAndThenOr32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > + @param OrData The value to OR with the result of the AND operation.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +SwapMmioAndThenOr32 (
> > + IN UINTN Address,
> > + IN UINT32 AndData,
> > + IN UINT32 OrData
> > + )
> > +{
> > + AndData = SwapBytes32 (AndData);
> > + OrData = SwapBytes32 (OrData);
> > +
> > + return MmioAndThenOr32 (Address, AndData, OrData); }
> > +
> > +/**
> > + MmioAndThenOr64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > + @param OrData The value to OR with the result of the AND operation.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +SwapMmioAndThenOr64 (
> > + IN UINTN Address,
> > + IN UINT64 AndData,
> > + IN UINT64 OrData
> > + )
> > +{
> > + AndData = SwapBytes64 (AndData);
> > + OrData = SwapBytes64 (OrData);
> > +
> > + return MmioAndThenOr64 (Address, AndData, OrData); }
> > +
> > +/**
> > + MmioOr16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param OrData The value to OR with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +SwapMmioOr16 (
> > + IN UINTN Address,
> > + IN UINT16 OrData
> > + )
> > +{
> > + return MmioOr16 (Address, SwapBytes16 (OrData)); }
> > +
> > +/**
> > + MmioOr32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param OrData The value to OR with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +SwapMmioOr32 (
> > + IN UINTN Address,
> > + IN UINT32 OrData
> > + )
> > +{
> > + return MmioOr32 (Address, SwapBytes32 (OrData)); }
> > +
> > +/**
> > + MmioOr64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param OrData The value to OR with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +SwapMmioOr64 (
> > + IN UINTN Address,
> > + IN UINT64 OrData
> > + )
> > +{
> > + return MmioOr64 (Address, SwapBytes64 (OrData)); }
> > +
> > +/**
> > + MmioAnd16 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +SwapMmioAnd16 (
> > + IN UINTN Address,
> > + IN UINT16 AndData
> > + )
> > +{
> > + return MmioAnd16 (Address, SwapBytes16 (AndData)); }
> > +
> > +/**
> > + MmioAnd32 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +SwapMmioAnd32 (
> > + IN UINTN Address,
> > + IN UINT32 AndData
> > + )
> > +{
> > + return MmioAnd32 (Address, SwapBytes32 (AndData)); }
> > +
> > +/**
> > + MmioAnd64 for Big-Endian modules.
> > +
> > + @param Address The MMIO register to write.
> > + @param AndData The value to AND with the read value from the MMIO
> register.
> > +
> > + @return The value written back to the MMIO register.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +SwapMmioAnd64 (
> > + IN UINTN Address,
> > + IN UINT64 AndData
> > + )
> > +{
> > + return MmioAnd64 (Address, SwapBytes64 (AndData)); }
> > +
> > +STATIC MMIO_OPERATIONS_16 SwappingFunctions16 = {
> > + SwapMmioRead16,
> > + SwapMmioWrite16,
> > + SwapMmioOr16,
> > + SwapMmioAnd16,
> > + SwapMmioAndThenOr16,
> > +};
> > +
> > +STATIC MMIO_OPERATIONS_16 NonSwappingFunctions16 = {
> > + MmioRead16,
> > + MmioWrite16,
> > + MmioOr16,
> > + MmioAnd16,
> > + MmioAndThenOr16,
> > +};
> > +
> > +STATIC MMIO_OPERATIONS_32 SwappingFunctions32 = {
> > + SwapMmioRead32,
> > + SwapMmioWrite32,
> > + SwapMmioOr32,
> > + SwapMmioAnd32,
> > + SwapMmioAndThenOr32,
> > +};
> > +
> > +STATIC MMIO_OPERATIONS_32 NonSwappingFunctions32 = {
> > + MmioRead32,
> > + MmioWrite32,
> > + MmioOr32,
> > + MmioAnd32,
> > + MmioAndThenOr32,
> > +};
> > +
> > +STATIC MMIO_OPERATIONS_64 SwappingFunctions64 = {
> > + SwapMmioRead64,
> > + SwapMmioWrite64,
> > + SwapMmioOr64,
> > + SwapMmioAnd64,
> > + SwapMmioAndThenOr64,
> > +};
> > +
> > +STATIC MMIO_OPERATIONS_64 NonSwappingFunctions64 = {
> > + MmioRead64,
> > + MmioWrite64,
> > + MmioOr64,
> > + MmioAnd64,
> > + MmioAndThenOr64,
> > +};
> > +
> > +/**
> > + Function to return pointer to 16 bit Mmio operations.
> > +
> > + @param Swap Flag to tell if Swap is needed or not
> > + on Mmio Operations.
> > +
> > + @return Pointer to Mmio Operations.
> > +
> > +**/
> > +MMIO_OPERATIONS_16 *
> > +GetMmioOperations16 (BOOLEAN Swap) {
> > + if (Swap) {
> > + return &SwappingFunctions16;
> > + } else {
> > + return &NonSwappingFunctions16;
> > + }
> > +}
> > +
> > +/**
> > + Function to return pointer to 32 bit Mmio operations.
> > +
> > + @param Swap Flag to tell if Swap is needed or not
> > + on Mmio Operations.
> > +
> > + @return Pointer to Mmio Operations.
> > +
> > +**/
> > +MMIO_OPERATIONS_32 *
> > +GetMmioOperations32 (BOOLEAN Swap) {
> > + if (Swap) {
> > + return &SwappingFunctions32;
> > + } else {
> > + return &NonSwappingFunctions32;
> > + }
> > +}
> > +
> > +/**
> > + Function to return pointer to 64 bit Mmio operations.
> > +
> > + @param Swap Flag to tell if Swap is needed or not
> > + on Mmio Operations.
> > +
> > + @return Pointer to Mmio Operations.
> > +
> > +**/
> > +MMIO_OPERATIONS_64 *
> > +GetMmioOperations64 (BOOLEAN Swap) {
> > + if (Swap) {
> > + return &SwappingFunctions64;
> > + } else {
> > + return &NonSwappingFunctions64;
> > + }
> > +}
> > diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> > b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> > new file mode 100644
> > index 0000000..e2e7606
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> > @@ -0,0 +1,32 @@
> > +## @IoAccessLib.inf
> > +
> > +# Copyright 2017 NXP
> > +#
> > +# This program and the accompanying materials # are licensed and
> > +made available under the terms and conditions of the BSD License #
> > +which accompanies this distribution. The full text of the license
> > +may be found at #
> > +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> > +nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi
> >
> +.aggarwal%40nxp.com%7C7d85cd38d02e4e6bbdc208d6677905c6%7C686ea1d
> 3bc2b
> >
> +4c6fa92cd99c5c301635%7C0%7C0%7C636810166817008412&sdata=OU
> EJ2URy5
> > +LX7wpvNs9f%2BK01Q1nahX2nWPNO67yOT57M%3D&reserved=0
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> > +#
> > +##
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001A
> > + BASE_NAME = IoAccessLib
> > + FILE_GUID = 28d77333-77eb-4faf-8735-130e5eb3e343
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = IoAccessLib
> > +
> > +[Sources.common]
> > + IoAccessLib.c
> > +
> > +[Packages]
> > + MdeModulePkg/MdeModulePkg.dec
> > + MdePkg/MdePkg.dec
> > + Silicon/NXP/NxpQoriqLs.dec
> > +
> > +[LibraryClasses]
> > + IoLib
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 02/41] Silicon/NXP : Add support for Watchdog driver
2018-12-17 17:36 ` Leif Lindholm
@ 2019-01-29 5:32 ` Meenakshi Aggarwal
0 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-01-29 5:32 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
edk2-devel@lists.01.org, Udit Kumar, Varun Sethi
> -----Original Message-----
> From: Leif Lindholm <leif.lindholm@linaro.org>
> Sent: Monday, December 17, 2018 11:06 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; michael.d.kinney@intel.com; edk2-
> devel@lists.01.org; Udit Kumar <udit.kumar@nxp.com>; Varun Sethi
> <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms 02/41] Silicon/NXP : Add support for
> Watchdog driver
>
> Starting with this one, since that was the biggest pain point last time around.
>
> On Wed, Nov 28, 2018 at 08:31:16PM +0530, Meenakshi Aggarwal wrote:
> > Installs watchdog timer arch protocol
>
> As per the email I just cc:d you on: unless the hardware supports configuration in
> a mode where it could be used for a compliant
> EFI_WATCHDOG_TIMER_ARCH_PROTOCOL (i.e., trigger a software event rather
> than a hardware reset), please rewrite this driver such that it does not register as
> that protocol.
>
Decided to use watchdog driver from MdeModulePkg.
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> > ---
> > Silicon/NXP/Drivers/WatchDog/WatchDog.c | 402
> +++++++++++++++++++++++++++
> > Silicon/NXP/Drivers/WatchDog/WatchDog.h | 39 +++
> > Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf | 47 ++++
> > 3 files changed, 488 insertions(+)
> > create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c
> > create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h
> > create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
>
> I would appreciate if you could follow
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.
> com%2Ftianocore%2Ftianocore.github.io%2Fwiki%2FLaszlo%27s-unkempt-git-
> guide-for-edk2-contributors-and-maintainers%23contrib-
> 23&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7Cc5cb603bead
> b4855f07608d6644624a1%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> %7C636806649758902154&sdata=NSs8taX%2F4oV0yhHmNEWVR%2Btzp3
> TqzuLnIy97t2R8dvs%3D&reserved=0
> when submitting the next revision. It greatly assists with reviewing.
>
Ok, will do.
> > diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.c
> > b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
> > new file mode 100644
> > index 0000000..1b1a3b5
> > --- /dev/null
> > +++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
> > @@ -0,0 +1,402 @@
> > +/** WatchDog.c
> > +*
> > +* Based on Watchdog driver implemenation available in
> > +* ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c
> > +*
> > +* Copyright 2017 NXP
>
> May want to change this to 2017-2018
> Also, format should be
> Copyright (c) ... NXP. All rights reserved.
>
Will change the year to 2017-2019,
but I cant add (c) as it will not be approved by NXP's TAs.
> > +*
> > +* This program and the accompanying materials
> > +* are licensed and made available under the terms and conditions of
> > +the BSD License
> > +* which accompanies this distribution. The full text of the license
> > +may be found at
> > +*
> > +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> > +nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi
> >
> +.aggarwal%40nxp.com%7Cc5cb603beadb4855f07608d6644624a1%7C686ea1d
> 3bc2b
> >
> +4c6fa92cd99c5c301635%7C0%7C0%7C636806649758902154&sdata=RLV
> E%2Bxi
> > +qQaQnHRKR7Spc6QYdx1pHPnKyqheLBqIinU4%3D&reserved=0
> > +*
> > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > +BASIS,
> > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +*
> > +**/
> > +
> > +#include <PiDxe.h>
> > +#include <Library/BaseLib.h>
> > +#include <Library/IoAccessLib.h>
> > +#include <Library/DebugLib.h>
> > +#include <Library/PcdLib.h>
> > +#include <Library/UefiBootServicesTableLib.h>
> > +#include <Protocol/WatchdogTimer.h>
> > +
> > +#include "WatchDog.h"
> > +
> > +STATIC EFI_EVENT EfiExitBootServicesEvent; STATIC EFI_EVENT
> > +WdogFeedEvent;
>
> m-prefix for both above please.
>
> Can you do a search-and-replace Wdog -> Watchdog and WDOG -> WATCHDOG
> please?
>
> > +STATIC MMIO_OPERATIONS_16 *mMmioOps;
> > +
> > +
> > +STATIC
> > +VOID
> > +WdogPing (
> > + VOID
> > + )
> > +{
> > + //
> > + // To reload a timeout value to the counter the proper service
> > +sequence begins by
> > + // writing 0x_5555 followed by 0x_AAAA to the Watchdog Service Register
> (WDOG_WSR).
> > + // This service sequence will reload the counter with the timeout
> > +value WT[7:0] of
> > + // Watchdog Control Register (WDOG_WCR).
> > + //
> > +
> > + mMmioOps->Write (PcdGet64 (PcdWdog1BaseAddr) +
> WDOG_WSR_OFFSET,
> > + WDOG_SERVICE_SEQ1);
>
> The memory access operations really need to encode size.
> I would strongly prefer mMmioOps->Write16.
>
> You could also tidy the call sites up with something like
>
> #define WATCHDOG_ADDRESS(register) (PcdGet64 (PcdWdog1BaseAddr),
> WATCHDOG_ ## register ## _OFFSET)
>
> So the invocation becomes
>
> mMmioOps->Write16 (WATCHDOG_ADDRESS (WSR),
> WATCHDOG_SERVICE_SEQ1);
>
>
> > + mMmioOps->Write (PcdGet64 (PcdWdog1BaseAddr) +
> WDOG_WSR_OFFSET,
> > + WDOG_SERVICE_SEQ2); }
> > +
> > +/**
> > + Stop the Wdog watchdog timer from counting down.
> > +**/
> > +STATIC
> > +VOID
> > +WdogStop (
> > + VOID
> > + )
> > +{
> > + // Watchdog cannot be disabled by software once started.
> > + // At best, we can keep reload counter with maximum value
> > +
> > + mMmioOps->AndThenOr (PcdGet64 (PcdWdog1BaseAddr) +
> WDOG_WCR_OFFSET,
> > + (UINT16)(~WDOG_WCR_WT),
> > + (WD_COUNT (WT_MAX_TIME) & WD_COUNT_MASK));
> > + WdogPing ();
> > +}
> > +
> > +/**
> > + Starts the Wdog counting down by feeding Service register with
> > + desired pattern.
> > + The count down will start from the value stored in the Load
> > +register,
> > + not from the value where it was previously stopped.
> > +**/
> > +STATIC
> > +VOID
> > +WdogStart (
> > + VOID
> > + )
> > +{
> > + //Reload the timeout value
> > + WdogPing ();
> > +}
> > +
> > +/**
> > + On exiting boot services we must make sure the Wdog Watchdog Timer
> > + is stopped.
> > +**/
> > +STATIC
> > +VOID
> > +EFIAPI
> > +ExitBootServicesEvent (
> > + IN EFI_EVENT Event,
> > + IN VOID *Context
> > + )
> > +{
> > + WdogStop ();
> > +}
> > +
> > +/**
> > + This function registers the handler NotifyFunction so it is called
> > +every time
> > + the watchdog timer expires. It also passes the amount of time
> > +since the last
> > + handler call to the NotifyFunction.
> > + If NotifyFunction is not NULL and a handler is not already
> > +registered,
> > + then the new handler is registered and EFI_SUCCESS is returned.
> > + If NotifyFunction is NULL, and a handler is already registered,
> > + then that handler is unregistered.
> > + If an attempt is made to register a handler when a handler is
> > +already registered,
> > + then EFI_ALREADY_STARTED is returned.
> > + If an attempt is made to unregister a handler when a handler is not
> > +registered,
> > + then EFI_INVALID_PARAMETER is returned.
> > +
> > + @param This The EFI_TIMER_ARCH_PROTOCOL instance.
> > + @param NotifyFunction The function to call when a timer interrupt fires.
> This
> > + function executes at TPL_HIGH_LEVEL. The DXE Core will
> > + register a handler for the timer interrupt, so it can know
> > + how much time has passed. This information is used to
> > + signal timer based events. NULL will unregister the handler.
> > +
> > + @retval EFI_SUCCESS The watchdog timer handler was registered.
> > + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler
> is already
> > + registered.
> > + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler
> was not
> > + previously registered.
> > +
> > +**/
> > +STATIC
> > +EFI_STATUS
> > +EFIAPI
> > +WdogRegisterHandler (
> > + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
> > + IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
> > + )
> > +{
> > + // ERROR: This function is not supported.
> > + // The hardware watchdog will reset the board
> > + return EFI_INVALID_PARAMETER;
> > +}
> > +
> > +/**
> > +
> > + This function adjusts the period of timer interrupts to the value
> > + specified by TimerPeriod. If the timer period is updated, then the
> > + selected timer period is stored in EFI_TIMER.TimerPeriod, and
> > + EFI_SUCCESS is returned. If the timer hardware is not programmable, then
> EFI_UNSUPPORTED is returned.
> > + If an error occurs while attempting to update the timer period,
> > + then the timer hardware will be put back in its state prior to this
> > + call, and EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then
> > + the timer interrupt is disabled. This is not the same as disabling the CPU's
> interrupts.
> > + Instead, it must either turn off the timer hardware, or it must
> > + adjust the interrupt controller so that a CPU interrupt is not
> > + generated when the timer interrupt fires.
> > +
> > + @param This The EFI_TIMER_ARCH_PROTOCOL instance.
> > + @param TimerPeriod The rate to program the timer interrupt in 100 nS
> units. If
> > + the timer hardware is not programmable, then
> EFI_UNSUPPORTED is
> > + returned. If the timer is programmable, then the timer period
> > + will be rounded up to the nearest timer period that is
> supported
> > + by the timer hardware. If TimerPeriod is set to 0, then the
> > + timer interrupts will be disabled.
> > +
> > +
> > + @retval EFI_SUCCESS The timer period was changed.
> > + @retval EFI_UNSUPPORTED The platform cannot change the period of
> the timer interrupt.
> > + @retval EFI_DEVICE_ERROR The timer period could not be changed due
> to a device error.
> > +
> > +**/
> > +STATIC
> > +EFI_STATUS
> > +EFIAPI
> > +WdogSetTimerPeriod (
> > + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
> > + IN UINT64 TimerPeriod // In 100ns units
> > + )
> > +{
> > + EFI_STATUS Status;
> > + UINT64 TimerPeriodInSec;
> > + UINT16 Val;
> > +
> > + Status = EFI_SUCCESS;
> > +
> > + if (TimerPeriod == 0) {
> > + // This is a watchdog stop request
> > + WdogStop ();
> > + return Status;
> > + } else {
> > + // Convert the TimerPeriod (in 100 ns unit) to an equivalent
> > + second value
> > +
> > + TimerPeriodInSec = DivU64x32 (TimerPeriod, NANO_SECOND_BASE);
> > +
> > + // The registers in the Wdog are only 32 bits
> > + if (TimerPeriodInSec > WT_MAX_TIME) {
> > + // We could load the watchdog with the maximum supported value but
> > + // if a smaller value was requested, this could have the watchdog
> > + // triggering before it was intended.
> > + // Better generate an error to let the caller know.
> > + Status = EFI_DEVICE_ERROR;
> > + return Status;
> > + }
> > +
> > + // set the new timeout value in the WCR
> > + // Convert the timeout value from Seconds to timer count
> > + Val = ((WD_COUNT(TimerPeriodInSec) & WD_COUNT_MASK) << 8);
> > +
> > + mMmioOps->AndThenOr (PcdGet64 (PcdWdog1BaseAddr) +
> WDOG_WCR_OFFSET,
> > + (UINT16)(~WDOG_WCR_WT),
> > + Val);
> > + // Start the watchdog
> > + WdogStart ();
> > + }
> > +
> > + return Status;
> > +}
> > +
> > +/**
> > + This function retrieves the period of timer interrupts in 100 ns
> > +units,
> > + returns that value in TimerPeriod, and returns EFI_SUCCESS. If
> > +TimerPeriod
> > + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod
> > +of 0 is
> > + returned, then the timer is currently disabled.
> > +
> > + @param This The EFI_TIMER_ARCH_PROTOCOL instance.
> > + @param TimerPeriod A pointer to the timer period to retrieve in 100 ns
> units. If
> > + 0 is returned, then the timer is currently disabled.
> > +
> > +
> > + @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
> > + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
> > +
> > +**/
> > +STATIC
> > +EFI_STATUS
> > +EFIAPI
> > +WdogGetTimerPeriod (
> > + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
> > + OUT UINT64 *TimerPeriod
> > + )
> > +{
> > + EFI_STATUS Status;
> > + UINT64 ReturnValue;
> > + UINT16 Val;
> > +
> > + Status = EFI_SUCCESS;
> > +
> > + if (TimerPeriod == NULL) {
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + // Check if the watchdog is stopped if ((mMmioOps->Read (PcdGet64
> > + (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET)
> > + & WDOG_WCR_WDE) == 0 ) {
> > + // It is stopped, so return zero.
> > + ReturnValue = 0;
> > + } else {
> > + // Convert the Watchdog ticks into equivalent TimerPeriod second value.
> > + Val = (mMmioOps->Read (PcdGet64 (PcdWdog1BaseAddr) +
> WDOG_WCR_OFFSET)
> > + & WDOG_WCR_WT ) >> 8;
> > + ReturnValue = WD_SEC(Val);
> > + }
> > +
> > + *TimerPeriod = ReturnValue;
> > + return Status;
> > +}
> > +
> > +/**
> > + Interface structure for the Watchdog Architectural Protocol.
> > +
> > + @par Protocol Description:
> > + This protocol provides a service to set the amount of time to wait
> > + before firing the watchdog timer, and it also provides a service to
> > + register a handler that is invoked when the watchdog timer fires.
> > +
> > + @par When the watchdog timer fires, control will be passed to a
> > + handler if one has been registered. If no handler has been
> > + registered, or the registered handler returns, then the system will
> > + be reset by calling the Runtime Service ResetSystem().
> > +
> > + @param RegisterHandler
> > + Registers a handler that will be called each time the
> > + watchdogtimer interrupt fires. TimerPeriod defines the minimum
> > + time between timer interrupts, so TimerPeriod will also be the
> > + minimum time between calls to the registered handler.
> > + NOTE: If the watchdog resets the system in hardware, then
> > + this function will not have any chance of executing.
> > +
> > + @param SetTimerPeriod
> > + Sets the period of the timer interrupt in 100 nS units.
> > + This function is optional, and may return EFI_UNSUPPORTED.
> > + If this function is supported, then the timer period will be
> > + rounded up to the nearest supported timer period.
> > +
> > + @param GetTimerPeriod
> > + Retrieves the period of the timer interrupt in 100 nS units.
> > +
> > +**/
> > +STATIC
> > +EFI_WATCHDOG_TIMER_ARCH_PROTOCOL gWatchdogTimer = {
>
> g implies global (as in visible to all modules). Please use 'm' for module-local
> globals.
>
> > + WdogRegisterHandler,
> > + WdogSetTimerPeriod,
> > + WdogGetTimerPeriod
> > +};
> > +
> > +/**
> > + Call back function when the timer event is signaled.
> > + This function will feed the watchdog with maximum value
> > + so that system wont reset in idle case e.g. stopped on UEFI shell.
> > +
> > + @param[in] Event The Event this notify function registered to.
> > + @param[in] Context Pointer to the context data registered to the
> > + Event.
> > +
> > +**/
> > +VOID
> > +EFIAPI
> > +WdogFeed (
> > + IN EFI_EVENT Event,
> > + IN VOID* Context
> > + )
> > +{
> > + WdogPing();
> > +}
> > +/**
> > + Initialize state information for the Watchdog Timer Architectural Protocol.
> > +
> > + @param ImageHandle of the loaded driver
> > + @param SystemTable Pointer to the System Table
> > +
> > + @retval EFI_SUCCESS Protocol registered
> > + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
> > + @retval EFI_DEVICE_ERROR Hardware problems
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +WdogInitialize (
> > + IN EFI_HANDLE ImageHandle,
> > + IN EFI_SYSTEM_TABLE *SystemTable
> > + )
> > +{
> > + EFI_STATUS Status;
> > + EFI_HANDLE Handle;
> > +
> > + mMmioOps = GetMmioOperations16 (FixedPcdGetBool
> > + (PcdWdogBigEndian));
> > +
> > + mMmioOps->AndThenOr (PcdGet64 (PcdWdog1BaseAddr) +
> WDOG_WCR_OFFSET,
> > + (UINT16)(~WDOG_WCR_WT),
> > + (WD_COUNT (WT_MAX_TIME) & WD_COUNT_MASK));
> > +
> > + mMmioOps->Or (PcdGet64 (PcdWdog1BaseAddr) + WDOG_WCR_OFFSET,
> > + WDOG_WCR_WDE);
> > +
> > + //
> > + // Make sure the Watchdog Timer Architectural Protocol // has not
> > + been installed in the system yet.
> > + // This will avoid conflicts with the universal watchdog //
> > + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL,
> > + &gEfiWatchdogTimerArchProtocolGuid);
> > +
> > + // Register for an ExitBootServicesEvent Status = gBS->CreateEvent
> > + (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,
> > + ExitBootServicesEvent, NULL,
> > + &EfiExitBootServicesEvent); if (EFI_ERROR (Status)) {
> > + Status = EFI_OUT_OF_RESOURCES;
> > + return Status;
> > + }
> > +
> > + //
> > + // Start the timer to feed Watchdog with maximum timeout value.
> > + //
> > + Status = gBS->CreateEvent (
> > + EVT_TIMER | EVT_NOTIFY_SIGNAL,
> > + TPL_NOTIFY,
> > + WdogFeed,
> > + NULL,
> > + &WdogFeedEvent
> > + );
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > +
> > + Status = gBS->SetTimer (WdogFeedEvent, TimerPeriodic,
> > + WT_FEED_INTERVAL); if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > +
> > + // Install the Timer Architectural Protocol onto a new handle
> > + Handle = NULL; Status = gBS->InstallMultipleProtocolInterfaces (
> > + &Handle,
> > + &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer,
> > + NULL
> > + );
> > + if (EFI_ERROR (Status)) {
> > + gBS->CloseEvent (EfiExitBootServicesEvent);
> > + Status = EFI_OUT_OF_RESOURCES;
> > + return Status;
> > + }
> > +
> > + WdogPing ();
> > +
> > + return Status;
> > +}
> > diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.h
> > b/Silicon/NXP/Drivers/WatchDog/WatchDog.h
> > new file mode 100644
> > index 0000000..9542608
> > --- /dev/null
> > +++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.h
> > @@ -0,0 +1,39 @@
> > +/** WatchDog.h
> > +*
> > +* Copyright 2017 NXP
> > +*
> > +* This program and the accompanying materials
> > +* are licensed and made available under the terms and conditions of
> > +the BSD License
> > +* which accompanies this distribution. The full text of the license
> > +may be found at
> > +*
> > +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> > +nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi
> >
> +.aggarwal%40nxp.com%7Cc5cb603beadb4855f07608d6644624a1%7C686ea1d
> 3bc2b
> >
> +4c6fa92cd99c5c301635%7C0%7C0%7C636806649758902154&sdata=RLV
> E%2Bxi
> > +qQaQnHRKR7Spc6QYdx1pHPnKyqheLBqIinU4%3D&reserved=0
> > +*
> > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > +BASIS,
> > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +*
> > +**/
> > +
> > +#ifndef __WATCHDOG_H__
> > +#define __WATCHDOG_H__
> > +
> > +#define WDOG_SIZE 0x1000
> > +#define WDOG_WCR_OFFSET 0
> > +#define WDOG_WSR_OFFSET 2
> > +#define WDOG_WRSR_OFFSET 4
> > +#define WDOG_WICR_OFFSET 6
> > +#define WDOG_WCR_WT (0xFF << 8)
> > +#define WDOG_WCR_WDE (1 << 2)
> > +#define WDOG_SERVICE_SEQ1 0x5555
> > +#define WDOG_SERVICE_SEQ2 0xAAAA
> > +#define WDOG_WCR_WDZST 0x1
> > +#define WDOG_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
> > +
> > +#define WT_MAX_TIME 128
>
> WT?
>
> > +#define WD_COUNT(Sec) (((Sec) * 2 - 1) << 8)
> > +#define WD_COUNT_MASK 0xff00
> > +#define WD_SEC(Cnt) (((Cnt) + 1) / 2)
>
> WD?
>
> /
> Leif
>
> > +
> > +#define NANO_SECOND_BASE 10000000
> > +
> > +#define WT_FEED_INTERVAL (WT_MAX_TIME * NANO_SECOND_BASE)
> > +
> > +#endif //__WATCHDOG_H__
> > diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> > b/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> > new file mode 100644
> > index 0000000..a311bdc
> > --- /dev/null
> > +++ b/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> > @@ -0,0 +1,47 @@
> > +# WatchDog.inf
> > +#
> > +# Component description file for WatchDog module # # Copyright
> > +2017 NXP # # This program and the accompanying materials # are
> > +licensed and made available under the terms and conditions of the BSD
> > +License # which accompanies this distribution. The full text of the
> > +license may be found at #
> > +https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fope
> > +nsource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi
> >
> +.aggarwal%40nxp.com%7Cc5cb603beadb4855f07608d6644624a1%7C686ea1d
> 3bc2b
> >
> +4c6fa92cd99c5c301635%7C0%7C0%7C636806649758902154&sdata=RLV
> E%2Bxi
> > +qQaQnHRKR7Spc6QYdx1pHPnKyqheLBqIinU4%3D&reserved=0
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > +BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> > +#
> > +#
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001A
> > + BASE_NAME = WatchDogDxe
> > + FILE_GUID = 0358b544-ec65-4339-89cd-cad60a3dd787
> > + MODULE_TYPE = DXE_DRIVER
> > + VERSION_STRING = 1.0
> > + ENTRY_POINT = WdogInitialize
> > +
> > +[Sources.common]
> > + WatchDog.c
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > + Silicon/NXP/NxpQoriqLs.dec
> > +
> > +[LibraryClasses]
> > + BaseLib
> > + IoAccessLib
> > + PcdLib
> > + UefiBootServicesTableLib
> > + UefiDriverEntryPoint
> > +
> > +[Pcd]
> > + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr
> > + gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian
> > +
> > +[Protocols]
> > + gEfiWatchdogTimerArchProtocolGuid
> > +
> > +[Depex]
> > + TRUE
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 10/41] Readme : Add Readme.md file.
2018-12-18 18:41 ` Leif Lindholm
@ 2019-02-01 5:43 ` Meenakshi Aggarwal
0 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-02-01 5:43 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
edk2-devel@lists.01.org, Udit Kumar, Varun Sethi
> -----Original Message-----
> From: Leif Lindholm <leif.lindholm@linaro.org>
> Sent: Wednesday, December 19, 2018 12:11 AM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; michael.d.kinney@intel.com; edk2-
> devel@lists.01.org; Udit Kumar <udit.kumar@nxp.com>; Varun Sethi
> <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms 10/41] Readme : Add Readme.md file.
>
> On Wed, Nov 28, 2018 at 08:31:24PM +0530, Meenakshi Aggarwal wrote:
> > Readme.md to explain how to build NXP board packages.
> >
>
> Could you add a link to this file from top-level Readme.md (towards the very
> end)?
>
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> > ---
> > Platform/NXP/Readme.md | 24 ++++++++++++++++++++++++
> > 1 file changed, 24 insertions(+)
> > create mode 100644 Platform/NXP/Readme.md
> >
> > diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md new file
> > mode 100644 index 0000000..902bafe
> > --- /dev/null
> > +++ b/Platform/NXP/Readme.md
> > @@ -0,0 +1,24 @@
> > +Support for all NXP boards is available in this directory.
> > +
> > +# How to build
> > +
> > +1. Set toolchain path.
> > +
> > + export
> > + PATH=<TOOLCHAIN_PATH>/gcc-linaro-4.9-2016.02-x86_64_aarch64-linux-
> gn
> > + u/bin/:$PATH
> > +
> > +2. Export following variables needed for compilation.
> > +
> > + export CROSS_COMPILE=aarch64-linux-gnu-
> > + export GCC_ARCH_PREFIX=GCC49_AARCH64_PREFIX
> > + export GCC49_AARCH64_PREFIX=aarch64-linux-gnu-
> > + export PACKAGES_PATH=<EDK2_PATH>/edk2/edk2-platforms
> > +
>
> Can you check whether you are happy with the generic build instructions in the
> top-level Readme.md and improve those if not?
> Then you could reference those rather than repeating.
>
Ok, will check the common Readme.md
> /
> Leif
>
> > +3. Build desired board package
> > +
> > + source edksetup.sh
> > + build -p "path to package's description (.dsc) file" -a AARCH64 -t
> > + GCC49 -b DEBUG/RELEASE clean
> > +
> > + e.g.
> > + build -p
> "$PACKAGES_PATH/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc" -a
> AARCH64 -t GCC49 -b DEBUG clean
> > + build -p
> > + "$PACKAGES_PATH/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc" -a
> > + AARCH64 -t GCC49 -b DEBUG
> > +
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC controller
2018-12-18 18:45 ` Leif Lindholm
@ 2019-02-01 5:55 ` Meenakshi Aggarwal
0 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-02-01 5:55 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
edk2-devel@lists.01.org, Udit Kumar, Varun Sethi
> -----Original Message-----
> From: Leif Lindholm <leif.lindholm@linaro.org>
> Sent: Wednesday, December 19, 2018 12:16 AM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; michael.d.kinney@intel.com; edk2-
> devel@lists.01.org; Udit Kumar <udit.kumar@nxp.com>; Varun Sethi
> <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC
> controller
>
> On Wed, Nov 28, 2018 at 08:31:25PM +0530, Meenakshi Aggarwal wrote:
> > This header file contain IFC controller timing structure, chip select
> > enum and other IFC macros.
>
> Please expand the IFC acronym here (like is done in file header below).
>
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> > ---
> > Silicon/NXP/Include/Ifc.h | 423
> > ++++++++++++++++++++++++++++++++++++++++++++++
>
> Please Update at least filename Ifc.h->NxpIfc.h
>
> > 1 file changed, 423 insertions(+)
> > create mode 100644 Silicon/NXP/Include/Ifc.h
> >
> > diff --git a/Silicon/NXP/Include/Ifc.h b/Silicon/NXP/Include/Ifc.h new
> > file mode 100644 index 0000000..6babb22
> > --- /dev/null
> > +++ b/Silicon/NXP/Include/Ifc.h
> > @@ -0,0 +1,423 @@
> > +/** @Ifc.h
> > +
> > + The integrated flash controller (IFC) is used to interface with
> > + external asynchronous NAND flash, asynchronous NOR flash, SRAM, generic
> ASIC memories and EPROM.
> > +
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials are licensed and made
> > + available under the terms and conditions of the BSD License which
> > + accompanies this distribution. The full text of the license may be
> > + found at
> > +
> > + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop
> > + ensource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenaks
> > +
> hi.aggarwal%40nxp.com%7Cf5720bda0a8c4ab0dd6708d6651904fb%7C686ea1d
> 3b
> > +
> c2b4c6fa92cd99c5c301635%7C0%7C0%7C636807555468004917&sdata=df
> OWZ
> > + Z2yXCKi55Cl94sAEGYx739%2FXCiK1yX3Wm6lTow%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#ifndef __IFC_H__
> > +#define __IFC_H__
>
> Please add NXP_ prefix.
>
> (I am less concerned about the actual defines below.)
>
> > +
> > +#include <Library/BaseLib.h>
>
> Is BaseLib.h really used by this file?
Yes, it is needed for HighBitSet32() used in this file.
> If not, please drop it.
>
> > +#include <Uefi.h>
> > +
> > +#define IFC_BANK_COUNT 4
> > +
> > +#define IFC_CSPR_REG_LEN 148
> > +#define IFC_AMASK_REG_LEN 144
> > +#define IFC_CSOR_REG_LEN 144
> > +#define IFC_FTIM_REG_LEN 576
> > +
> > +#define IFC_CSPR_USED_LEN sizeof (IFC_CSPR) * \
> > + IFC_BANK_COUNT
> > +
> > +#define IFC_AMASK_USED_LEN sizeof (IFC_AMASK) * \
> > + IFC_BANK_COUNT
> > +
> > +#define IFC_CSOR_USED_LEN sizeof (IFC_CSOR) * \
> > + IFC_BANK_COUNT
> > +
> > +#define IFC_FTIM_USED_LEN sizeof (IFC_FTIM) * \
> > + IFC_BANK_COUNT
> > +
> > +/* List of commands */
> > +#define IFC_NAND_CMD_RESET 0xFF
> > +#define IFC_NAND_CMD_READID 0x90
> > +#define IFC_NAND_CMD_STATUS 0x70
> > +#define IFC_NAND_CMD_READ0 0x00
> > +#define IFC_NAND_CMD_READSTART 0x30
> > +#define IFC_NAND_CMD_ERASE1 0x60
> > +#define IFC_NAND_CMD_ERASE2 0xD0
> > +#define IFC_NAND_CMD_SEQIN 0x80
> > +#define IFC_NAND_CMD_PAGEPROG 0x10
> > +#define MAX_RETRY_COUNT 150000
> > +
> > +
> > +#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
> > +
> > +/*
> > + * NAND Event and Error Status Register (NAND_EVTER_STAT) */
> > +
> > +/* Operation Complete */
> > +#define IFC_NAND_EVTER_STAT_OPC 0x80000000
> > +
> > +/* Flash Timeout Error */
> > +#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
> > +
> > +/* Write Protect Error */
> > +#define IFC_NAND_EVTER_STAT_WPER 0x04000000
> > +
> > +/* ECC Error */
> > +#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
> > +
> > +/*
> > + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
> > +*/
> > +
> > +/* NAND Machine specific opcodes OP0-OP14*/
> > +#define IFC_NAND_FIR0_OP0 0xFC000000
> > +#define IFC_NAND_FIR0_OP0_SHIFT 26
> > +#define IFC_NAND_FIR0_OP1 0x03F00000
> > +#define IFC_NAND_FIR0_OP1_SHIFT 20
> > +#define IFC_NAND_FIR0_OP2 0x000FC000
> > +#define IFC_NAND_FIR0_OP2_SHIFT 14
> > +#define IFC_NAND_FIR0_OP3 0x00003F00
> > +#define IFC_NAND_FIR0_OP3_SHIFT 8
> > +#define IFC_NAND_FIR0_OP4 0x000000FC
> > +#define IFC_NAND_FIR0_OP4_SHIFT 2
> > +#define IFC_NAND_FIR1_OP5 0xFC000000
> > +#define IFC_NAND_FIR1_OP5_SHIFT 26
> > +#define IFC_NAND_FIR1_OP6 0x03F00000
> > +#define IFC_NAND_FIR1_OP6_SHIFT 20
> > +#define IFC_NAND_FIR1_OP7 0x000FC000
> > +#define IFC_NAND_FIR1_OP7_SHIFT 14
> > +#define IFC_NAND_FIR1_OP8 0x00003F00
> > +#define IFC_NAND_FIR1_OP8_SHIFT 8
> > +#define IFC_NAND_FIR1_OP9 0x000000FC
> > +#define IFC_NAND_FIR1_OP9_SHIFT 2
> > +#define IFC_NAND_FIR2_OP10 0xFC000000
> > +#define IFC_NAND_FIR2_OP10_SHIFT 26
> > +#define IFC_NAND_FIR2_OP11 0x03F00000
> > +#define IFC_NAND_FIR2_OP11_SHIFT 20
> > +#define IFC_NAND_FIR2_OP12 0x000FC000
> > +#define IFC_NAND_FIR2_OP12_SHIFT 14
> > +#define IFC_NAND_FIR2_OP13 0x00003F00
> > +#define IFC_NAND_FIR2_OP13_SHIFT 8
> > +#define IFC_NAND_FIR2_OP14 0x000000FC
> > +#define IFC_NAND_FIR2_OP14_SHIFT 2
> > +
> > +/*
> > + * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) */
> > +
> > +/* General purpose FCM flash command bytes CMD0-CMD7 */
> > +#define IFC_NAND_FCR0_CMD0 0xFF000000
> > +#define IFC_NAND_FCR0_CMD0_SHIFT 24
> > +#define IFC_NAND_FCR0_CMD1 0x00FF0000
> > +#define IFC_NAND_FCR0_CMD1_SHIFT 16
> > +#define IFC_NAND_FCR0_CMD2 0x0000FF00
> > +#define IFC_NAND_FCR0_CMD2_SHIFT 8
> > +#define IFC_NAND_FCR0_CMD3 0x000000FF
> > +#define IFC_NAND_FCR0_CMD3_SHIFT 0
> > +#define IFC_NAND_FCR1_CMD4 0xFF000000
> > +#define IFC_NAND_FCR1_CMD4_SHIFT 24
> > +#define IFC_NAND_FCR1_CMD5 0x00FF0000
> > +#define IFC_NAND_FCR1_CMD5_SHIFT 16
> > +#define IFC_NAND_FCR1_CMD6 0x0000FF00
> > +#define IFC_NAND_FCR1_CMD6_SHIFT 8
> > +#define IFC_NAND_FCR1_CMD7 0x000000FF
> > +#define IFC_NAND_FCR1_CMD7_SHIFT 0
> > +
> > +/* Timing registers for NAND Flash */
> > +
> > +#define IFC_FTIM0_NAND_TCCST_SHIFT 25
> > +#define IFC_FTIM0_NAND_TCCST(n) ((n) <<
> IFC_FTIM0_NAND_TCCST_SHIFT)
> > +#define IFC_FTIM0_NAND_TWP_SHIFT 16
> > +#define IFC_FTIM0_NAND_TWP(n) ((n) << IFC_FTIM0_NAND_TWP_SHIFT)
> > +#define IFC_FTIM0_NAND_TWCHT_SHIFT 8
> > +#define IFC_FTIM0_NAND_TWCHT(n) ((n) <<
> IFC_FTIM0_NAND_TWCHT_SHIFT)
> > +#define IFC_FTIM0_NAND_TWH_SHIFT 0
> > +#define IFC_FTIM0_NAND_TWH(n) ((n) << IFC_FTIM0_NAND_TWH_SHIFT)
> > +#define IFC_FTIM1_NAND_TADLE_SHIFT 24
> > +#define IFC_FTIM1_NAND_TADLE(n) ((n) <<
> IFC_FTIM1_NAND_TADLE_SHIFT)
> > +#define IFC_FTIM1_NAND_TWBE_SHIFT 16
> > +#define IFC_FTIM1_NAND_TWBE(n) ((n) <<
> IFC_FTIM1_NAND_TWBE_SHIFT)
> > +#define IFC_FTIM1_NAND_TRR_SHIFT 8
> > +#define IFC_FTIM1_NAND_TRR(n) ((n) << IFC_FTIM1_NAND_TRR_SHIFT)
> > +#define IFC_FTIM1_NAND_TRP_SHIFT 0
> > +#define IFC_FTIM1_NAND_TRP(n) ((n) << IFC_FTIM1_NAND_TRP_SHIFT)
> > +#define IFC_FTIM2_NAND_TRAD_SHIFT 21
> > +#define IFC_FTIM2_NAND_TRAD(n) ((n) <<
> IFC_FTIM2_NAND_TRAD_SHIFT)
> > +#define IFC_FTIM2_NAND_TREH_SHIFT 11
> > +#define IFC_FTIM2_NAND_TREH(n) ((n) <<
> IFC_FTIM2_NAND_TREH_SHIFT)
> > +#define IFC_FTIM2_NAND_TWHRE_SHIFT 0
> > +#define IFC_FTIM2_NAND_TWHRE(n) ((n) <<
> IFC_FTIM2_NAND_TWHRE_SHIFT)
> > +#define IFC_FTIM3_NAND_TWW_SHIFT 24
> > +#define IFC_FTIM3_NAND_TWW(n) ((n) <<
> IFC_FTIM3_NAND_TWW_SHIFT)
> > +
> > +/*
> > + * Flash ROW and COL Address Register (ROWn, COLn) */
> > +
> > +/* Main/spare region locator */
> > +#define IFC_NAND_COL_MS 0x80000000
> > +
> > +/* Column Address */
> > +#define IFC_NAND_COL_CA_MASK 0x00000FFF
> > +
> > +#define NAND_STATUS_WP 0x80
> > +
> > +/*
> > + * NAND Event and Error Enable Register (NAND_EVTER_EN) */
> > +
> > +/* Operation complete event enable */
> > +#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
> > +
> > +/* Page read complete event enable */ #define
> > +IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
> > +
> > +/* Flash Timeout error enable */
> > +#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
> > +
> > +/* Write Protect error enable */
> > +#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
> > +
> > +/* ECC error logging enable */
> > +#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
> > +
> > +/*
> > + * CSPR - Chip Select Property Register */
> > +
> > +#define IFC_CSPR_BA 0xFFFF0000
> > +#define IFC_CSPR_BA_SHIFT 16
> > +#define IFC_CSPR_PORT_SIZE 0x00000180
> > +#define IFC_CSPR_PORT_SIZE_SHIFT 7
> > +
> > +// Port Size 8 bit
> > +#define IFC_CSPR_PORT_SIZE_8 0x00000080
> > +
> > +// Port Size 16 bit
> > +#define IFC_CSPR_PORT_SIZE_16 0x00000100
> > +
> > +// Port Size 32 bit
> > +#define IFC_CSPR_PORT_SIZE_32 0x00000180
> > +
> > +// Write Protect
> > +#define IFC_CSPR_WP 0x00000040
> > +#define IFC_CSPR_WP_SHIFT 6
> > +
> > +// Machine Select
> > +#define IFC_CSPR_MSEL 0x00000006
> > +#define IFC_CSPR_MSEL_SHIFT 1
> > +
> > +// NOR
> > +#define IFC_CSPR_MSEL_NOR 0x00000000
> > +
> > +/* NAND */
> > +#define IFC_CSPR_MSEL_NAND 0x00000002
> > +
> > +/* GPCM */
> > +#define IFC_CSPR_MSEL_GPCM 0x00000004
> > +
> > +// Bank Valid
> > +#define IFC_CSPR_V 0x00000001
> > +#define IFC_CSPR_V_SHIFT 0
> > +
> > +/*
> > + * Chip Select Option Register - NOR Flash Mode */
> > +
> > +// Enable Address shift Mode
> > +#define IFC_CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
> > +
> > +// Page Read Enable from NOR device
> > +#define IFC_CSOR_NOR_PGRD_EN 0x10000000
> > +
> > +// AVD Toggle Enable during Burst Program
> > +#define IFC_CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
> > +
> > +// Address Data Multiplexing Shift
> > +#define IFC_CSOR_NOR_ADM_MASK 0x0003E000
> > +#define IFC_CSOR_NOR_ADM_SHIFT_SHIFT 13
> > +#define IFC_CSOR_NOR_ADM_SHIFT(n) ((n) <<
> IFC_CSOR_NOR_ADM_SHIFT_SHIFT)
> > +
> > +// Type of the NOR device hooked
> > +#define IFC_CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
> > +#define IFC_CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
> > +
> > +// Time for Read Enable High to Output High Impedance
> > +#define IFC_CSOR_NOR_TRHZ_MASK 0x0000001C
> > +#define IFC_CSOR_NOR_TRHZ_SHIFT 2
> > +#define IFC_CSOR_NOR_TRHZ_20 0x00000000
> > +#define IFC_CSOR_NOR_TRHZ_40 0x00000004
> > +#define IFC_CSOR_NOR_TRHZ_60 0x00000008
> > +#define IFC_CSOR_NOR_TRHZ_80 0x0000000C
> > +#define IFC_CSOR_NOR_TRHZ_100 0x00000010
> > +
> > +// Buffer control disable
> > +#define IFC_CSOR_NOR_BCTLD 0x00000001
> > +
> > +/*
> > + * Chip Select Option Register IFC_NAND Machine */
> > +
> > +/* Enable ECC Encoder */
> > +#define IFC_CSOR_NAND_ECC_ENC_EN 0x80000000
> > +#define IFC_CSOR_NAND_ECC_MODE_MASK 0x30000000
> > +
> > +/* 4 bit correction per 520 Byte sector */ #define
> > +IFC_CSOR_NAND_ECC_MODE_4 0x00000000
> > +
> > +/* 8 bit correction per 528 Byte sector */ #define
> > +IFC_CSOR_NAND_ECC_MODE_8 0x10000000
> > +
> > +/* Enable ECC Decoder */
> > +#define IFC_CSOR_NAND_ECC_DEC_EN 0x04000000
> > +
> > +/* Row Address Length */
> > +#define IFC_CSOR_NAND_RAL_MASK 0x01800000 #define
> > +IFC_CSOR_NAND_RAL_SHIFT 20
> > +#define IFC_CSOR_NAND_RAL_1 0x00000000
> > +#define IFC_CSOR_NAND_RAL_2 0x00800000
> > +#define IFC_CSOR_NAND_RAL_3 0x01000000
> > +#define IFC_CSOR_NAND_RAL_4 0x01800000
> > +
> > +/* Page Size 512b, 2k, 4k */
> > +#define IFC_CSOR_NAND_PGS_MASK 0x00180000 #define
> > +IFC_CSOR_NAND_PGS_SHIFT 16
> > +#define IFC_CSOR_NAND_PGS_512 0x00000000
> > +#define IFC_CSOR_NAND_PGS_2K 0x00080000
> > +#define IFC_CSOR_NAND_PGS_4K 0x00100000
> > +#define IFC_CSOR_NAND_PGS_8K 0x00180000
> > +
> > +/* Spare region Size */
> > +#define IFC_CSOR_NAND_SPRZ_MASK 0x0000E000
> > +#define IFC_CSOR_NAND_SPRZ_SHIFT 13
> > +#define IFC_CSOR_NAND_SPRZ_16 0x00000000
> > +#define IFC_CSOR_NAND_SPRZ_64 0x00002000
> > +#define IFC_CSOR_NAND_SPRZ_128 0x00004000
> > +#define IFC_CSOR_NAND_SPRZ_210 0x00006000
> > +#define IFC_CSOR_NAND_SPRZ_218 0x00008000
> > +#define IFC_CSOR_NAND_SPRZ_224 0x0000A000
> > +#define IFC_CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
> > +
> > +/* Pages Per Block */
> > +#define IFC_CSOR_NAND_PB_MASK 0x00000700
> > +#define IFC_CSOR_NAND_PB_SHIFT 8
> > +#define IFC_CSOR_NAND_PB(n) (n-5) << IFC_CSOR_NAND_PB_SHIFT
> > +
> > +/* Time for Read Enable High to Output High Impedance */
> > +#define IFC_CSOR_NAND_TRHZ_MASK 0x0000001C
> > +#define IFC_CSOR_NAND_TRHZ_SHIFT 2
> > +#define IFC_CSOR_NAND_TRHZ_20 0x00000000
> > +#define IFC_CSOR_NAND_TRHZ_40 0x00000004
> > +#define IFC_CSOR_NAND_TRHZ_60 0x00000008
> > +#define IFC_CSOR_NAND_TRHZ_80 0x0000000C
> > +#define IFC_CSOR_NAND_TRHZ_100 0x00000010
> > +
> > +/*
> > + * FTIM0 - NOR Flash Mode
> > + */
> > +#define IFC_FTIM0_NOR 0xF03F3F3F
> > +#define IFC_FTIM0_NOR_TACSE_SHIFT 28
> > +#define IFC_FTIM0_NOR_TACSE(n) ((n) << IFC_FTIM0_NOR_TACSE_SHIFT)
> > +#define IFC_FTIM0_NOR_TEADC_SHIFT 16
> > +#define IFC_FTIM0_NOR_TEADC(n) ((n) << IFC_FTIM0_NOR_TEADC_SHIFT)
> > +#define IFC_FTIM0_NOR_TAVDS_SHIFT 8
> > +#define IFC_FTIM0_NOR_TAVDS(n) ((n) << IFC_FTIM0_NOR_TAVDS_SHIFT)
> > +#define IFC_FTIM0_NOR_TEAHC_SHIFT 0
> > +#define IFC_FTIM0_NOR_TEAHC(n) ((n) << IFC_FTIM0_NOR_TEAHC_SHIFT)
> > +
> > +/*
> > + * FTIM1 - NOR Flash Mode
> > + */
> > +#define IFC_FTIM1_NOR 0xFF003F3F
> > +#define IFC_FTIM1_NOR_TACO_SHIFT 24
> > +#define IFC_FTIM1_NOR_TACO(n) ((n) <<
> IFC_FTIM1_NOR_TACO_SHIFT)
> > +#define IFC_FTIM1_NOR_TRAD_NOR_SHIFT 8
> > +#define IFC_FTIM1_NOR_TRAD_NOR(n) ((n) <<
> IFC_FTIM1_NOR_TRAD_NOR_SHIFT)
> > +#define IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
> > +#define IFC_FTIM1_NOR_TSEQRAD_NOR(n) ((n) <<
> IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT)
> > +
> > +/*
> > + * FTIM2 - NOR Flash Mode
> > + */
> > +#define IFC_FTIM2_NOR 0x0F3CFCFF
> > +#define IFC_FTIM2_NOR_TCS_SHIFT 24
> > +#define IFC_FTIM2_NOR_TCS(n) ((n) << IFC_FTIM2_NOR_TCS_SHIFT)
> > +#define IFC_FTIM2_NOR_TCH_SHIFT 18
> > +#define IFC_FTIM2_NOR_TCH(n) ((n) << IFC_FTIM2_NOR_TCH_SHIFT)
> > +#define IFC_FTIM2_NOR_TWPH_SHIFT 10
> > +#define IFC_FTIM2_NOR_TWPH(n) ((n) <<
> IFC_FTIM2_NOR_TWPH_SHIFT)
> > +#define IFC_FTIM2_NOR_TWP_SHIFT 0
> > +#define IFC_FTIM2_NOR_TWP(n) ((n) << IFC_FTIM2_NOR_TWP_SHIFT)
> > +
> > +/*
> > + * FTIM0 - Normal GPCM Mode
> > + */
> > +#define IFC_FTIM0_GPCM 0xF03F3F3F
> > +#define IFC_FTIM0_GPCM_TACSE_SHIFT 28
> > +#define IFC_FTIM0_GPCM_TACSE(n) ((n) <<
> IFC_FTIM0_GPCM_TACSE_SHIFT)
> > +#define IFC_FTIM0_GPCM_TEADC_SHIFT 16
> > +#define IFC_FTIM0_GPCM_TEADC(n) ((n) <<
> IFC_FTIM0_GPCM_TEADC_SHIFT)
> > +#define IFC_FTIM0_GPCM_TAVDS_SHIFT 8
> > +#define IFC_FTIM0_GPCM_TAVDS(n) ((n) <<
> IFC_FTIM0_GPCM_TAVDS_SHIFT)
> > +#define IFC_FTIM0_GPCM_TEAHC_SHIFT 0
> > +#define IFC_FTIM0_GPCM_TEAHC(n) ((n) <<
> IFC_FTIM0_GPCM_TEAHC_SHIFT)
> > +
> > +/*
> > + * FTIM1 - Normal GPCM Mode
> > + */
> > +#define IFC_FTIM1_GPCM 0xFF003F00
> > +#define IFC_FTIM1_GPCM_TACO_SHIFT 24
> > +#define IFC_FTIM1_GPCM_TACO(n) ((n) <<
> IFC_FTIM1_GPCM_TACO_SHIFT)
> > +#define IFC_FTIM1_GPCM_TRAD_SHIFT 8
> > +#define IFC_FTIM1_GPCM_TRAD(n) ((n) <<
> IFC_FTIM1_GPCM_TRAD_SHIFT)
> > +
> > +/*
> > + * FTIM2 - Normal GPCM Mode
> > + */
> > +#define IFC_FTIM2_GPCM 0x0F3C00FF
> > +#define IFC_FTIM2_GPCM_TCS_SHIFT 24
> > +#define IFC_FTIM2_GPCM_TCS(n) ((n) << IFC_FTIM2_GPCM_TCS_SHIFT)
> > +#define IFC_FTIM2_GPCM_TCH_SHIFT 18
> > +#define IFC_FTIM2_GPCM_TCH(n) ((n) <<
> IFC_FTIM2_GPCM_TCH_SHIFT)
> > +#define IFC_FTIM2_GPCM_TWP_SHIFT 0
> > +#define IFC_FTIM2_GPCM_TWP(n) ((n) <<
> IFC_FTIM2_GPCM_TWP_SHIFT)
> > +
> > +/* Convert an address into the right format for the CSPR Registers */
> > +#define IFC_CSPR_PHYS_ADDR(x) (((UINTN)x) & 0xffff0000)
> > +
> > +/*
> > + * Address Mask Register
> > + */
> > +#define IFC_AMASK_MASK 0xFFFF0000
> > +#define IFC_AMASK_SHIFT 16
> > +#define IFC_AMASK(n) (IFC_AMASK_MASK << \
> > + (HighBitSet32(n) - IFC_AMASK_SHIFT))
> > +
> > +typedef enum {
> > + IFC_CS0 = 0,
> > + IFC_CS1,
> > + IFC_CS2,
> > + IFC_CS3,
> > + IFC_CS4,
> > + IFC_CS5,
> > + IFC_CS6,
> > + IFC_CS7,
> > + IFC_CS_MAX,
>
> CamelCase for member names, please.
>
> /
> Leif
>
> > +} IFC_CHIP_SEL;
> > +
> > +typedef struct {
> > + UINT32 Ftim[IFC_BANK_COUNT];
> > + UINT32 CsprExt;
> > + UINT32 Cspr;
> > + UINT32 Csor;
> > + UINT32 Amask;
> > + UINT8 CS;
> > +} IFC_TIMINGS;
> > +
> > +#endif //__IFC_H__
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 13/41] Silicon/NXP : Add support of IfcLib
2018-12-19 13:25 ` Leif Lindholm
@ 2019-02-01 6:53 ` Meenakshi Aggarwal
0 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-02-01 6:53 UTC (permalink / raw)
To: Leif Lindholm
Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com,
edk2-devel@lists.01.org, Udit Kumar, Varun Sethi
> -----Original Message-----
> From: Leif Lindholm <leif.lindholm@linaro.org>
> Sent: Wednesday, December 19, 2018 6:56 PM
> To: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> Cc: ard.biesheuvel@linaro.org; michael.d.kinney@intel.com; edk2-
> devel@lists.01.org; Udit Kumar <udit.kumar@nxp.com>; Varun Sethi
> <V.Sethi@nxp.com>
> Subject: Re: [PATCH edk2-platforms 13/41] Silicon/NXP : Add support of IfcLib
>
> On Wed, Nov 28, 2018 at 08:31:27PM +0530, Meenakshi Aggarwal wrote:
> > Add support of IfcLib, it will be used to perform any operation on IFC
> > controller.
>
> Expand acronym.
>
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> > ---
> > Silicon/NXP/Include/Library/IfcLib.h | 26 +++++
> > Silicon/NXP/Library/IfcLib/IfcLib.c | 150 +++++++++++++++++++++++++++
> > Silicon/NXP/Library/IfcLib/IfcLib.h | 190
> ++++++++++++++++++++++++++++++++++
> > Silicon/NXP/Library/IfcLib/IfcLib.inf | 38 +++++++
>
> Names Ifc -> NxpIfc please.
>
Is this renaming really needed for IfcLib, I can change the guard and header file name.
Please suggest?
> > Silicon/NXP/NxpQoriqLs.dec | 1 +
> > 5 files changed, 405 insertions(+)
> > create mode 100644 Silicon/NXP/Include/Library/IfcLib.h
> > create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.c
> > create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.h
> > create mode 100644 Silicon/NXP/Library/IfcLib/IfcLib.inf
> >
> > diff --git a/Silicon/NXP/Include/Library/IfcLib.h
> > b/Silicon/NXP/Include/Library/IfcLib.h
> > new file mode 100644
> > index 0000000..8d2c151
> > --- /dev/null
> > +++ b/Silicon/NXP/Include/Library/IfcLib.h
> > @@ -0,0 +1,26 @@
> > +/** @IfcLib.h
> > +
> > + The integrated flash controller (IFC) is used to interface with
> > + external asynchronous NAND flash, asynchronous NOR flash, SRAM, generic
> ASIC memories and EPROM.
> > +
> > + Copyright 2018 NXP
> > +
> > + This program and the accompanying materials are licensed and made
> > + available under the terms and conditions of the BSD License which
> > + accompanies this distribution. The full text of the license may be
> > + found at
> > +
> > + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop
> > + ensource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenaks
> > +
> hi.aggarwal%40nxp.com%7C62c0401c65ac481e650508d665b57ea9%7C686ea1
> d3b
> > +
> c2b4c6fa92cd99c5c301635%7C0%7C0%7C636808227519182943&sdata=4
> UMgN
> > + 7laz86jDwTlvJrHWkqdum8qmZPGWrhESvjHBMQ%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#ifndef __IFC_LIB_H__
> > +#define __IFC_LIB_H__
>
> Header guard NXP_ (and/or QORIQ_) prefix.
>
> > +
> > +VOID
> > +IfcInit (
> > + VOID
> > + );
> > +
> > +#endif //__IFC_LIB_H__
> > diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.c
> > b/Silicon/NXP/Library/IfcLib/IfcLib.c
> > new file mode 100644
> > index 0000000..8cf02ae
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/IfcLib/IfcLib.c
> > @@ -0,0 +1,150 @@
> > +/** @IfcLib.c
> > +
> > + The integrated flash controller (IFC) is used to interface with
> > + external asynchronous/ synchronous NAND flash, asynchronous NOR
> > + flash, SRAM, generic ASIC memory and EPROM.
> > + It has eight chip-selects, to which a maximum of eight flash
> > + devices can be attached, although only one of these can be accessed at any
> given time.
> > +
> > + Copyright 2018 NXP
> > +
> > + This program and the accompanying materials are licensed and made
> > + available under the terms and conditions of the BSD License which
> > + accompanies this distribution. The full text of the license may be
> > + found at
> > +
> > + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop
> > + ensource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenaks
> > +
> hi.aggarwal%40nxp.com%7C62c0401c65ac481e650508d665b57ea9%7C686ea1
> d3b
> > +
> c2b4c6fa92cd99c5c301635%7C0%7C0%7C636808227519182943&sdata=4
> UMgN
> > + 7laz86jDwTlvJrHWkqdum8qmZPGWrhESvjHBMQ%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#include <Library/IoAccessLib.h>
> > +#include "IfcLib.h"
> > +
> > +STATIC MMIO_OPERATIONS_32 *mMmioOps;
> > +
> > +STATIC UINT8 mNandCS;
> > +STATIC UINT8 mNorCS;
> > +STATIC UINT8 mFpgaCS;
> > +
> > +VOID
>
> Local only?
> If so, STATIC please.
>
> > +SetTimings (
> > + IN UINT8 CS,
> > + IN IFC_TIMINGS IfcTimings
> > + )
> > +{
> > + IFC_REGS* IfcRegs;
> > +
> > + IfcRegs = (IFC_REGS*)PcdGet64 (PcdIfcBaseAddr);
> > +
> > + // Configure Extended chip select property registers
> > + mMmioOps->Write ((UINTN)&IfcRegs->CsprCs[CS].CsprExt,
> > + IfcTimings.CsprExt);
> > +
> > + // Configure Fpga timing registers
> > + mMmioOps->Write ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM0],
> > + IfcTimings.Ftim[0]); mMmioOps->Write
> > + ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM1], IfcTimings.Ftim[1]);
> > + mMmioOps->Write ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM2],
> > + IfcTimings.Ftim[2]); mMmioOps->Write
> > + ((UINTN)&IfcRegs->FtimCs[CS].Ftim[IFC_FTIM3], IfcTimings.Ftim[3]);
> > +
> > + // Configure chip select option registers mMmioOps->Write
> > + ((UINTN)&IfcRegs->CsprCs[CS].Cspr, IfcTimings.Cspr);
> > +
> > + // Configure address mask registers mMmioOps->Write
> > + ((UINTN)&IfcRegs->AmaskCs[CS].Amask, IfcTimings.Amask);
> > +
> > + // Configure chip select property registers mMmioOps->Write
> > + ((UINTN)&IfcRegs->CsorCs[CS].Csor, IfcTimings.Csor);
> > +
> > + return;
> > +}
> > +
> > +VOID
>
> Local only?
> If so, STATIC please.
>
> > +NandInit(
> > + VOID
> > + )
> > +{
> > + IFC_REGS* IfcRegs;
> > + IFC_TIMINGS NandIfcTimings;
> > +
> > + IfcRegs = (IFC_REGS*)PcdGet64 (PcdIfcBaseAddr);
> > +
> > + // Get Nand Flash Timings
> > + GetIfcNandFlashTimings (&NandIfcTimings);
> > +
> > + // Validate chip select
> > + if (NandIfcTimings.CS < IFC_CS_MAX) {
> > + mNandCS = NandIfcTimings.CS;
> > +
> > + // clear event registers
> > + mMmioOps->Write ((UINTN)&IfcRegs->IfcNand.PgrdcmplEvtStat, ~0U);
> > +
> > + mMmioOps->Write ((UINTN)&IfcRegs->IfcNand.NandEvterStat, ~0U);
> > +
> > + // Enable error and event for any detected errors
> > + mMmioOps->Write ((UINTN)&IfcRegs->IfcNand.NandEvterEn,
> > + IFC_NAND_EVTER_EN_OPC_EN |
>
> Indentation should be to function name, not struct name.
> (Please address throughout.)
>
> > + IFC_NAND_EVTER_EN_PGRDCMPL_EN |
> > + IFC_NAND_EVTER_EN_FTOER_EN |
> > + IFC_NAND_EVTER_EN_WPER_EN);
> > + mMmioOps->Write ((UINTN)&IfcRegs->IfcNand.Ncfgr, 0x0);
> > +
> > + SetTimings (mNandCS, NandIfcTimings); }
> > +
> > + return;
> > +}
> > +
> > +VOID
>
> Local only?
> If so, STATIC please.
>
> > +FpgaInit (
> > + VOID
> > + )
> > +{
> > + IFC_TIMINGS FpgaIfcTimings;
> > +
> > + // Get Fpga Flash Timings
> > + GetIfcFpgaTimings (&FpgaIfcTimings);
> > +
> > + // Validate chip select
> > + if (FpgaIfcTimings.CS < IFC_CS_MAX) {
> > + mFpgaCS = FpgaIfcTimings.CS;
> > + SetTimings (mFpgaCS, FpgaIfcTimings); }
> > +
> > + return;
> > +}
> > +
> > +VOID
> > +NorInit (
> > + VOID
> > + )
> > +{
> > + IFC_TIMINGS NorIfcTimings;
> > +
> > + // Get NOR Flash Timings
> > + GetIfcNorFlashTimings (&NorIfcTimings);
> > +
> > + // Validate chip select
> > + if (NorIfcTimings.CS < IFC_CS_MAX) {
> > + mNorCS = NorIfcTimings.CS;
> > + SetTimings (mNorCS, NorIfcTimings); }
> > +
> > + return;
> > +}
> > +
> > +//
> > +// IFC has NOR , NAND and FPGA
> > +//
> > +VOID
> > +IfcInit (
> > + VOID
> > + )
> > +{
> > + mMmioOps = GetMmioOperations32 (FixedPcdGetBool (PcdIfcBigEndian));
> > +
> > + NorInit();
> > + NandInit();
> > + FpgaInit();
> > +
> > + return;
> > +}
> > diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.h
> > b/Silicon/NXP/Library/IfcLib/IfcLib.h
> > new file mode 100644
> > index 0000000..38ce247
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/IfcLib/IfcLib.h
> > @@ -0,0 +1,190 @@
> > +/** @IfcLib.h
> > +
> > + The integrated flash controller (IFC) is used to interface with
> > + external asynchronous/ synchronous NAND flash, asynchronous NOR
> > + flash, SRAM, generic ASIC memory and EPROM.
> > + It has eight chip-selects, to which a maximum of eight flash
> > + devices can be attached, although only one of these can be accessed at any
> given time.
> > +
> > + Copyright 2017 NXP
> > +
> > + This program and the accompanying materials are licensed and made
> > + available under the terms and conditions of the BSD License which
> > + accompanies this distribution. The full text of the license may be
> > + found at
> > +
> > + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop
> > + ensource.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenaks
> > +
> hi.aggarwal%40nxp.com%7C62c0401c65ac481e650508d665b57ea9%7C686ea1
> d3b
> > +
> c2b4c6fa92cd99c5c301635%7C0%7C0%7C636808227519182943&sdata=4
> UMgN
> > + 7laz86jDwTlvJrHWkqdum8qmZPGWrhESvjHBMQ%3D&reserved=0
> > +
> > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> > + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER EXPRESS OR IMPLIED.
> > +
> > +**/
> > +
> > +#ifndef __IFC_LIB_H__
> > +#define __IFC_LIB_H__
>
> NXP_ and/or QORIQ_ prefix?
>
> > +
> > +#include <Ifc.h>
> > +#include <Uefi.h>
> > +
> > +#define IFC_NAND_RESERVED_SIZE FixedPcdGet32
> (PcdIfcNandReservedSize)
> > +
> > +typedef enum {
> > + IFC_FTIM0 = 0,
> > + IFC_FTIM1,
> > + IFC_FTIM2,
> > + IFC_FTIM3,
>
> CamelCase member names please, throughout.
>
> > +} IFC_FTIMS;
> > +
> > +typedef struct {
> > + UINT32 CsprExt;
> > + UINT32 Cspr;
> > + UINT32 Res;
> > +} IFC_CSPR;
> > +
> > +typedef struct {
> > + UINT32 Amask;
>
> AddressMask?
>
> > + UINT32 Res[0x2];
>
> Is this "Reserved"?
> If so, please write out in full.
> Also please drop the hex prefix.
> Apples throughout.
>
> > +} IFC_AMASK;
> > +
> > +typedef struct {
> > + UINT32 Csor;
> > + UINT32 CsorExt;
> > + UINT32 Res;
> > +} IFC_CSOR;
> > +
> > +typedef struct {
> > + UINT32 Ftim[4];
> > + UINT32 Res[0x8];
> > +}IFC_FTIM ;
> > +
> > +typedef struct {
> > + UINT32 Ncfgr;
> > + UINT32 Res1[0x4];
> > + UINT32 NandFcr0;
> > + UINT32 NandFcr1;
> > + UINT32 Res2[0x8];
> > + UINT32 Row0;
> > + UINT32 Res3;
> > + UINT32 Col0;
> > + UINT32 Res4;
> > + UINT32 Row1;
> > + UINT32 Res5;
> > + UINT32 Col1;
> > + UINT32 Res6;
> > + UINT32 Row2;
> > + UINT32 Res7;
> > + UINT32 Col2;
> > + UINT32 Res8;
> > + UINT32 Row3;
> > + UINT32 Res9;
> > + UINT32 Col3;
> > + UINT32 Res10[0x24];
> > + UINT32 NandFbcr;
> > + UINT32 Res11;
> > + UINT32 NandFir0;
> > + UINT32 NandFir1;
> > + UINT32 nandFir2;
> > + UINT32 Res12[0x10];
> > + UINT32 NandCsel;
> > + UINT32 Res13;
> > + UINT32 NandSeqStrt;
> > + UINT32 Res14;
> > + UINT32 NandEvterStat;
> > + UINT32 Res15;
> > + UINT32 PgrdcmplEvtStat;
> > + UINT32 Res16[0x2];
> > + UINT32 NandEvterEn;
> > + UINT32 Res17[0x2];
> > + UINT32 NandEvterIntrEn;
> > + UINT32 Res18[0x2];
> > + UINT32 NandErattr0;
> > + UINT32 NandErattr1;
> > + UINT32 Res19[0x10];
> > + UINT32 NandFsr;
> > + UINT32 Res20;
> > + UINT32 NandEccstat[4];
> > + UINT32 Res21[0x20];
> > + UINT32 NanNdcr;
> > + UINT32 Res22[0x2];
> > + UINT32 NandAutobootTrgr;
> > + UINT32 Res23;
> > + UINT32 NandMdr;
> > + UINT32 Res24[0x5C];
> > +} IFC_NAND;
> > +
> > +/*
> > + * IFC controller NOR Machine registers */ typedef struct {
> > + UINT32 NorEvterStat;
> > + UINT32 Res1[0x2];
> > + UINT32 NorEvterEn;
> > + UINT32 Res2[0x2];
> > + UINT32 NorEvterIntrEn;
> > + UINT32 Res3[0x2];
> > + UINT32 NorErattr0;
> > + UINT32 NorErattr1;
> > + UINT32 NorErattr2;
> > + UINT32 Res4[0x4];
> > + UINT32 NorCr;
> > + UINT32 Res5[0xEF];
> > +} IFC_NOR;
> > +
> > +/*
> > + * IFC controller GPCM Machine registers
> > + */
> > +typedef struct {
>
> extra space
>
> > + UINT32 GpcmEvterStat;
> > + UINT32 Res1[0x2];
> > + UINT32 GpcmEvterEn;
> > + UINT32 Res2[0x2];
> > + UINT32 gpcmEvterIntrEn;
> > + UINT32 Res3[0x2];
> > + UINT32 GpcmErattr0;
> > + UINT32 GpcmErattr1;
> > + UINT32 GcmErattr2;
> > + UINT32 GpcmStat;
> > +} IFC_GPCM;
> > +
> > +/*
> > + * IFC Controller Registers
> > + */
> > +typedef struct {
> > + UINT32 IfcRev;
> > + UINT32 Res1[0x2];
> > + IFC_CSPR CsprCs[IFC_BANK_COUNT];
> > + UINT8 Res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
> > + IFC_AMASK AmaskCs[IFC_BANK_COUNT];
> > + UINT8 Res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
> > + IFC_CSOR CsorCs[IFC_BANK_COUNT];
> > + UINT8 Res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
> > + IFC_FTIM FtimCs[IFC_BANK_COUNT];
> > + UINT8 Res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
> > + UINT32 RbStat;
> > + UINT32 RbMap;
> > + UINT32 WpMap;
> > + UINT32 IfcGcr;
> > + UINT32 Res7[0x2];
> > + UINT32 CmEvter_stat;
> > + UINT32 Res8[0x2];
> > + UINT32 CmEvterEn;
> > + UINT32 Res9[0x2];
> > + UINT32 CmEvterIntrEn;
> > + UINT32 Res10[0x2];
> > + UINT32 CmErattr0;
> > + UINT32 CmErattr1;
> > + UINT32 Res11[0x2];
> > + UINT32 IfcCcr;
> > + UINT32 IfcCsr;
> > + UINT32 DdrCcrLow;
> > + UINT32 Res12[IFC_NAND_RESERVED_SIZE];
> > + IFC_NAND IfcNand;
> > + IFC_NOR IfcNor;
> > + IFC_GPCM IfcGpcm;
> > +} IFC_REGS;
> > +
> > +extern VOID GetIfcNorFlashTimings (IFC_TIMINGS * NorIfcTimings);
> > +
> > +extern VOID GetIfcFpgaTimings (IFC_TIMINGS *FpgaIfcTimings);
> > +
> > +extern VOID GetIfcNandFlashTimings (IFC_TIMINGS * NandIfcTimings);
>
> Please move these function declarations to the (first) patch that adds
> implementations of these functions.
>
> > +
> > +#endif //__IFC_LIB_H__
> > diff --git a/Silicon/NXP/Library/IfcLib/IfcLib.inf
> b/Silicon/NXP/Library/IfcLib/IfcLib.inf
> > new file mode 100644
> > index 0000000..989eb44
> > --- /dev/null
> > +++ b/Silicon/NXP/Library/IfcLib/IfcLib.inf
> > @@ -0,0 +1,38 @@
> > +# IfcLib.inf
> > +#
> > +# Component description file for IFC Library
> > +#
> > +# Copyright 2018 NXP
> > +#
> > +# This program and the accompanying materials
> > +# are licensed and made available under the terms and conditions of the BSD
> License
> > +# which accompanies this distribution. The full text of the license may be
> found at
> > +#
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fopenso
> urce.org%2Flicenses%2Fbsd-
> license.php&data=02%7C01%7Cmeenakshi.aggarwal%40nxp.com%7C62c0
> 401c65ac481e650508d665b57ea9%7C686ea1d3bc2b4c6fa92cd99c5c301635%7
> C0%7C0%7C636808227519182943&sdata=4UMgN7laz86jDwTlvJrHWkqdu
> m8qmZPGWrhESvjHBMQ%3D&reserved=0
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> > +#
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001A
> > + BASE_NAME = IfcLib
>
> Nxp
>
> > + FILE_GUID = a465d76c-0785-4ee7-bd72-767983d575a2
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = IfcLib
>
> Nxp
>
> /
> Leif
>
> > +
> > +[Sources.common]
> > + IfcLib.c
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > + Silicon/NXP/NxpQoriqLs.dec
> > +
> > +[LibraryClasses]
> > + BoardLib
> > + IoAccessLib
> > +
> > +[FixedPcd]
> > + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr
> > + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian
> > + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize
> > diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> > index df64ad6..bd89da4 100644
> > --- a/Silicon/NXP/NxpQoriqLs.dec
> > +++ b/Silicon/NXP/NxpQoriqLs.dec
> > @@ -77,6 +77,7 @@
> > gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000128
> > gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129
> > gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A
> > + gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0|UINT64|0x0000012B
> >
> > #
> > # IFC PCDs
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 01/12] Silicon/NXP: Add Library to provide Mmio APIs with swapped data.
[not found] ` <1570639758-30355-2-git-send-email-meenakshi.aggarwal@nxp.com>
@ 2019-10-10 10:17 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-10-10 10:17 UTC (permalink / raw)
To: Meenakshi Aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, v.sethi
On Wed, Oct 09, 2019 at 10:19:07PM +0530, Meenakshi Aggarwal wrote:
> This library provided MMIO APIs for modules need swapping.
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
This looks good to me.
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
I will merge this into Silicon/NXP initially once the set is ready to
go in, and migrate it across to edk2 at a later date.
> ---
> Silicon/NXP/Include/Library/IoAccessLib.h | 248 +++++++++++++++++++
> Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 302 ++++++++++++++++++++++++
> Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf | 26 ++
If we need another revision of this set, please follow the
format-patch steps from
https://github.com/tianocore/tianocore.github.io/wiki/Laszlo's-unkempt-git-guide-for-edk2-contributors-and-maintainers
Executing <edk2>/BaseTools/Scripts/SetupGit.py inside your repository
sets some of the flags persistently there, including the most
important one - the "orderfile", which helps code review
substantially.
/
Leif
> 3 files changed, 576 insertions(+)
> create mode 100644 Silicon/NXP/Include/Library/IoAccessLib.h
> create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
>
> diff --git a/Silicon/NXP/Include/Library/IoAccessLib.h b/Silicon/NXP/Include/Library/IoAccessLib.h
> new file mode 100644
> index 0000000..b72e65c
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/IoAccessLib.h
> @@ -0,0 +1,248 @@
> +/** @file
> + *
> + * Copyright 2017-2019 NXP
> + *
> + * SPDX-License-Identifier: BSD-2-Clause-Patent
> + *
> + **/
> +
> +#ifndef IO_ACCESS_LIB_H_
> +#define IO_ACCESS_LIB_H_
> +
> +#include <Base.h>
> +
> +/**
> + MmioRead16 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioRead16 (
> + IN UINTN Address
> + );
> +
> +/**
> + MmioRead32 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioRead32 (
> + IN UINTN Address
> + );
> +
> +/**
> + MmioRead64 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioRead64 (
> + IN UINTN Address
> + );
> +
> +/**
> + MmioWrite16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioWrite16 (
> + IN UINTN Address,
> + IN UINT16 Value
> + );
> +
> +/**
> + MmioWrite32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + );
> +
> +/**
> + MmioWrite64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioWrite64 (
> + IN UINTN Address,
> + IN UINT64 Value
> + );
> +
> +/**
> + MmioAndThenOr16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioAndThenOr16 (
> + IN UINTN Address,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + );
> +
> +/**
> + MmioAndThenOr32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioAndThenOr32 (
> + IN UINTN Address,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + );
> +
> +/**
> + MmioAndThenOr64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioAndThenOr64 (
> + IN UINTN Address,
> + IN UINT64 AndData,
> + IN UINT64 OrData
> + );
> +
> +/**
> + MmioOr16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioOr16 (
> + IN UINTN Address,
> + IN UINT16 OrData
> + );
> +
> +/**
> + MmioOr32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioOr32 (
> + IN UINTN Address,
> + IN UINT32 OrData
> + );
> +
> +/**
> + MmioOr64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioOr64 (
> + IN UINTN Address,
> + IN UINT64 OrData
> + );
> +
> +/**
> + MmioAnd16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioAnd16 (
> + IN UINTN Address,
> + IN UINT16 AndData
> + );
> +
> +/**
> + MmioAnd32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioAnd32 (
> + IN UINTN Address,
> + IN UINT32 AndData
> + );
> +
> +/**
> + MmioAnd64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioAnd64 (
> + IN UINTN Address,
> + IN UINT64 AndData
> + );
> +
> +#endif /* IO_ACCESS_LIB_H_ */
> diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> new file mode 100644
> index 0000000..e9e535f
> --- /dev/null
> +++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> @@ -0,0 +1,302 @@
> +/** IoAccessLib.c
> +
> + Provide MMIO APIs for BE modules.
> +
> + Copyright 2017-2019 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/IoLib.h>
> +
> +/**
> + MmioRead16 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioRead16 (
> + IN UINTN Address
> + )
> +{
> + return SwapBytes16 (MmioRead16 (Address));
> +}
> +
> +/**
> + MmioRead32 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioRead32 (
> + IN UINTN Address
> + )
> +{
> + return SwapBytes32 (MmioRead32 (Address));
> +}
> +
> +/**
> + MmioRead64 for Big-Endian modules.
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioRead64 (
> + IN UINTN Address
> + )
> +{
> + return SwapBytes64 (MmioRead64 (Address));
> +}
> +
> +/**
> + MmioWrite16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioWrite16 (
> + IN UINTN Address,
> + IN UINT16 Value
> + )
> +{
> + return MmioWrite16 (Address, SwapBytes16 (Value));
> +}
> +
> +/**
> + MmioWrite32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + return MmioWrite32 (Address, SwapBytes32 (Value));
> +}
> +
> +/**
> + MmioWrite64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioWrite64 (
> + IN UINTN Address,
> + IN UINT64 Value
> + )
> +{
> + return MmioWrite64 (Address, SwapBytes64 (Value));
> +}
> +
> +/**
> + MmioAndThenOr16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioAndThenOr16 (
> + IN UINTN Address,
> + IN UINT16 AndData,
> + IN UINT16 OrData
> + )
> +{
> + AndData = SwapBytes16 (AndData);
> + OrData = SwapBytes16 (OrData);
> +
> + return MmioAndThenOr16 (Address, AndData, OrData);
> +}
> +
> +/**
> + MmioAndThenOr32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioAndThenOr32 (
> + IN UINTN Address,
> + IN UINT32 AndData,
> + IN UINT32 OrData
> + )
> +{
> + AndData = SwapBytes32 (AndData);
> + OrData = SwapBytes32 (OrData);
> +
> + return MmioAndThenOr32 (Address, AndData, OrData);
> +}
> +
> +/**
> + MmioAndThenOr64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> + @param OrData The value to OR with the result of the AND operation.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioAndThenOr64 (
> + IN UINTN Address,
> + IN UINT64 AndData,
> + IN UINT64 OrData
> + )
> +{
> + AndData = SwapBytes64 (AndData);
> + OrData = SwapBytes64 (OrData);
> +
> + return MmioAndThenOr64 (Address, AndData, OrData);
> +}
> +
> +/**
> + MmioOr16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioOr16 (
> + IN UINTN Address,
> + IN UINT16 OrData
> + )
> +{
> + return MmioOr16 (Address, SwapBytes16 (OrData));
> +}
> +
> +/**
> + MmioOr32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioOr32 (
> + IN UINTN Address,
> + IN UINT32 OrData
> + )
> +{
> + return MmioOr32 (Address, SwapBytes32 (OrData));
> +}
> +
> +/**
> + MmioOr64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param OrData The value to OR with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioOr64 (
> + IN UINTN Address,
> + IN UINT64 OrData
> + )
> +{
> + return MmioOr64 (Address, SwapBytes64 (OrData));
> +}
> +
> +/**
> + MmioAnd16 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +SwapMmioAnd16 (
> + IN UINTN Address,
> + IN UINT16 AndData
> + )
> +{
> + return MmioAnd16 (Address, SwapBytes16 (AndData));
> +}
> +
> +/**
> + MmioAnd32 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +SwapMmioAnd32 (
> + IN UINTN Address,
> + IN UINT32 AndData
> + )
> +{
> + return MmioAnd32 (Address, SwapBytes32 (AndData));
> +}
> +
> +/**
> + MmioAnd64 for Big-Endian modules.
> +
> + @param Address The MMIO register to write.
> + @param AndData The value to AND with the read value from the MMIO register.
> +
> + @return The value written back to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +SwapMmioAnd64 (
> + IN UINTN Address,
> + IN UINT64 AndData
> + )
> +{
> + return MmioAnd64 (Address, SwapBytes64 (AndData));
> +}
> diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> new file mode 100644
> index 0000000..4f3af46
> --- /dev/null
> +++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> @@ -0,0 +1,26 @@
> +## @IoAccessLib.inf
> +
> +# Copyright 2017-2019 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = IoAccessLib
> + FILE_GUID = 28d77333-77eb-4faf-8735-130e5eb3e343
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = IoAccessLib
> +
> +[Sources.common]
> + IoAccessLib.c
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + IoLib
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 02/12] Silicon/NXP: Add function to return swapped Mmio APIs pointer
[not found] ` <1570639758-30355-3-git-send-email-meenakshi.aggarwal@nxp.com>
@ 2019-10-10 10:23 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-10-10 10:23 UTC (permalink / raw)
To: Meenakshi Aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, v.sethi
On Wed, Oct 09, 2019 at 10:19:08PM +0530, Meenakshi Aggarwal wrote:
> Add support to return pointer to MMIO APIs on basis of Swap flag.
> If Flag is True then MMIO APIs returned in which data
> swapped after reading from MMIO and before write using MMIO.
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/Library/IoAccessLib.h | 78 ++++++++++++++++++++
> Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 102 ++++++++++++++++++++++++++
> 2 files changed, 180 insertions(+)
>
> diff --git a/Silicon/NXP/Include/Library/IoAccessLib.h b/Silicon/NXP/Include/Library/IoAccessLib.h
> index b72e65c..1e7c028 100644
> --- a/Silicon/NXP/Include/Library/IoAccessLib.h
> +++ b/Silicon/NXP/Include/Library/IoAccessLib.h
> @@ -11,6 +11,84 @@
>
> #include <Base.h>
>
> +///
> +/// Structure to have pointer to R/W
> +/// Mmio operations for 16 bits.
> +///
> +typedef struct _MMIO_OPERATIONS_16 {
> + UINT16 (*Read16) (UINTN Address);
> + UINT16 (*Write16) (UINTN Address, UINT16 Value);
> + UINT16 (*Or16) (UINTN Address, UINT16 Or);
> + UINT16 (*And16) (UINTN Address, UINT16 AND);
> + UINT16 (*AndThenOr16) (UINTN Address, UINT16 And, UINT16 Or);
The idea of having variables called "Or" and "And" makes my head hurt.
Thankfully, they are not called that in the actual implementations.
If you change all the "AND" to "AndData" and all the "Or" to "OrData"
in this file:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> +} MMIO_OPERATIONS_16;
> +
> +///
> +/// Structure to have pointer to R/W
> +/// Mmio operations for 32 bits.
> +///
> +typedef struct _MMIO_OPERATIONS_32 {
> + UINT32 (*Read32) (UINTN Address);
> + UINT32 (*Write32) (UINTN Address, UINT32 Value);
> + UINT32 (*Or32) (UINTN Address, UINT32 Or);
> + UINT32 (*And32) (UINTN Address, UINT32 AND);
> + UINT32 (*AndThenOr32) (UINTN Address, UINT32 And, UINT32 Or);
> +} MMIO_OPERATIONS_32;
> +
> +///
> +/// Structure to have pointer to R/W
> +/// Mmio operations for 64 bits.
> +///
> +typedef struct _MMIO_OPERATIONS_64 {
> + UINT64 (*Read64) (UINTN Address);
> + UINT64 (*Write64) (UINTN Address, UINT64 Value);
> + UINT64 (*Or64) (UINTN Address, UINT64 Or);
> + UINT64 (*And64) (UINTN Address, UINT64 AND);
> + UINT64 (*AndThenOr64) (UINTN Address, UINT64 And, UINT64 Or);
> +} MMIO_OPERATIONS_64;
> +
> +/**
> + Function to return pointer to 16 bit Mmio operations.
> +
> + @param Swap Flag to tell if Swap is needed or not
> + on Mmio Operations.
> +
> + @return Pointer to Mmio Operations.
> +
> +**/
> +MMIO_OPERATIONS_16 *
> +GetMmioOperations16 (
> + IN BOOLEAN Swap
> + );
> +
> +/**
> + Function to return pointer to 32 bit Mmio operations.
> +
> + @param Swap Flag to tell if Swap is needed or not
> + on Mmio Operations.
> +
> + @return Pointer to Mmio Operations.
> +
> +**/
> +MMIO_OPERATIONS_32 *
> +GetMmioOperations32 (
> + IN BOOLEAN Swap
> + );
> +
> +/**
> + Function to return pointer to 64 bit Mmio operations.
> +
> + @param Swap Flag to tell if Swap is needed or not
> + on Mmio Operations.
> +
> + @return Pointer to Mmio Operations.
> +
> +**/
> +MMIO_OPERATIONS_64 *
> +GetMmioOperations64 (
> + IN BOOLEAN Swap
> + );
> +
> /**
> MmioRead16 for Big-Endian modules.
>
> diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> index e9e535f..6ed83d0 100644
> --- a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> +++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> @@ -300,3 +300,105 @@ SwapMmioAnd64 (
> {
> return MmioAnd64 (Address, SwapBytes64 (AndData));
> }
> +
> +STATIC MMIO_OPERATIONS_16 SwappingFunctions16 = {
> + SwapMmioRead16,
> + SwapMmioWrite16,
> + SwapMmioOr16,
> + SwapMmioAnd16,
> + SwapMmioAndThenOr16,
> +};
> +
> +STATIC MMIO_OPERATIONS_16 NonSwappingFunctions16 = {
> + MmioRead16,
> + MmioWrite16,
> + MmioOr16,
> + MmioAnd16,
> + MmioAndThenOr16,
> +};
> +
> +STATIC MMIO_OPERATIONS_32 SwappingFunctions32 = {
> + SwapMmioRead32,
> + SwapMmioWrite32,
> + SwapMmioOr32,
> + SwapMmioAnd32,
> + SwapMmioAndThenOr32,
> +};
> +
> +STATIC MMIO_OPERATIONS_32 NonSwappingFunctions32 = {
> + MmioRead32,
> + MmioWrite32,
> + MmioOr32,
> + MmioAnd32,
> + MmioAndThenOr32,
> +};
> +
> +STATIC MMIO_OPERATIONS_64 SwappingFunctions64 = {
> + SwapMmioRead64,
> + SwapMmioWrite64,
> + SwapMmioOr64,
> + SwapMmioAnd64,
> + SwapMmioAndThenOr64,
> +};
> +
> +STATIC MMIO_OPERATIONS_64 NonSwappingFunctions64 = {
> + MmioRead64,
> + MmioWrite64,
> + MmioOr64,
> + MmioAnd64,
> + MmioAndThenOr64,
> +};
> +
> +/**
> + Function to return pointer to 16 bit Mmio operations.
> +
> + @param Swap Flag to tell if Swap is needed or not
> + on Mmio Operations.
> +
> + @return Pointer to Mmio Operations.
> +
> +**/
> +MMIO_OPERATIONS_16 *
> +GetMmioOperations16 (BOOLEAN Swap) {
> + if (Swap) {
> + return &SwappingFunctions16;
> + } else {
> + return &NonSwappingFunctions16;
> + }
> +}
> +
> +/**
> + Function to return pointer to 32 bit Mmio operations.
> +
> + @param Swap Flag to tell if Swap is needed or not
> + on Mmio Operations.
> +
> + @return Pointer to Mmio Operations.
> +
> +**/
> +MMIO_OPERATIONS_32 *
> +GetMmioOperations32 (BOOLEAN Swap) {
> + if (Swap) {
> + return &SwappingFunctions32;
> + } else {
> + return &NonSwappingFunctions32;
> + }
> +}
> +
> +/**
> + Function to return pointer to 64 bit Mmio operations.
> +
> + @param Swap Flag to tell if Swap is needed or not
> + on Mmio Operations.
> +
> + @return Pointer to Mmio Operations.
> +
> +**/
> +MMIO_OPERATIONS_64 *
> +GetMmioOperations64 (BOOLEAN Swap) {
> + if (Swap) {
> + return &SwappingFunctions64;
> + } else {
> + return &NonSwappingFunctions64;
> + }
> +}
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 03/12] Silicon/NXP : Add support for Watchdog driver
[not found] ` <1570639758-30355-4-git-send-email-meenakshi.aggarwal@nxp.com>
@ 2019-10-10 10:39 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-10-10 10:39 UTC (permalink / raw)
To: Meenakshi Aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, devel, v.sethi
Hi Meenakshi,
As you will have no doubt noticed, edk2-devel@lists.01.org has been
retired - we are now using devel@edk2.groups.io, please subscribe (and
post patches) to that one instead.
I have bounced my replies to your first two patches there, and will
try to remember to manually change the list address in my replies to
the remaining patches.
On Wed, Oct 09, 2019 at 10:19:09PM +0530, Meenakshi Aggarwal wrote:
> Installs watchdog timer arch protocol
>
I am a little bit surprised by this patch being submitted again - in
our last communication on this set (29 January), you said
"Decided to use watchdog driver from MdeModulePkg."
Did you change your mind? This driver still registers a
EFI_WATCHDOG_TIMER_ARCH_PROTOCOL, which is a poor match for what this
hardware actually does.
Best Regards,
Leif
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Drivers/WatchDog/WatchDog.c | 396 +++++++++++++++++++++++++++
> Silicon/NXP/Drivers/WatchDog/WatchDog.h | 32 +++
> Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf | 41 +++
> 3 files changed, 469 insertions(+)
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
>
> diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.c b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
> new file mode 100644
> index 0000000..c2d104a
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.c
> @@ -0,0 +1,396 @@
> +/** WatchDog.c
> +*
> +* Based on Watchdog driver implemenation available in
> +* ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805Watchdog.c
> +*
> +* Copyright 2017-2019 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <PiDxe.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Protocol/WatchdogTimer.h>
> +
> +#include "WatchDog.h"
> +
> +STATIC EFI_EVENT mEfiExitBootServicesEvent;
> +STATIC EFI_EVENT mWatchdogFeedEvent;
> +STATIC MMIO_OPERATIONS_16 *mMmioOps;
> +
> +
> +STATIC
> +VOID
> +WatchdogPing (
> + VOID
> + )
> +{
> + //
> + // To reload a timeout value to the counter the proper service sequence begins by
> + // writing 0x_5555 followed by 0x_AAAA to the Watchdog Service Register (WATCHDOG_WSR).
> + // This service sequence will reload the counter with the timeout value WATCHDOG[7:0] of
> + // Watchdog Control Register (WATCHDOG_WCR).
> + //
> +
> + mMmioOps->Write16 (PcdGet64 (PcdWatchdog1BaseAddr) + WATCHDOG_WSR_OFFSET,
> + WATCHDOG_SERVICE_SEQ1);
> + mMmioOps->Write16 (PcdGet64 (PcdWatchdog1BaseAddr) + WATCHDOG_WSR_OFFSET,
> + WATCHDOG_SERVICE_SEQ2);
> +}
> +
> +/**
> + Stop the Watchdog watchdog timer from counting down.
> +**/
> +STATIC
> +VOID
> +WatchdogStop (
> + VOID
> + )
> +{
> + // Watchdog cannot be disabled by software once started.
> + // At best, we can keep reload counter with maximum value
> +
> + mMmioOps->AndThenOr16 (PcdGet64 (PcdWatchdog1BaseAddr) + WATCHDOG_WCR_OFFSET,
> + (UINT16)(~WATCHDOG_WCR_TIMEOUT),
> + (WATCHDOG_COUNT (WATCHDOG_MAX_TIME) & WATCHDOG_COUNT_MASK));
> + WatchdogPing ();
> +}
> +
> +/**
> + Starts the Watchdog counting down by feeding Service register with
> + desired pattern.
> + The count down will start from the value stored in the Load register,
> + not from the value where it was previously stopped.
> +**/
> +STATIC
> +VOID
> +WatchdogStart (
> + VOID
> + )
> +{
> + //Reload the timeout value
> + WatchdogPing ();
> +}
> +
> +/**
> + On exiting boot services we must make sure the Watchdog Watchdog Timer
> + is stopped.
> +**/
> +STATIC
> +VOID
> +EFIAPI
> +ExitBootServicesEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + WatchdogStop ();
> +}
> +
> +/**
> + This function registers the handler NotifyFunction so it is called every time
> + the watchdog timer expires. It also passes the amount of time since the last
> + handler call to the NotifyFunction.
> + If NotifyFunction is not NULL and a handler is not already registered,
> + then the new handler is registered and EFI_SUCCESS is returned.
> + If NotifyFunction is NULL, and a handler is already registered,
> + then that handler is unregistered.
> + If an attempt is made to register a handler when a handler is already registered,
> + then EFI_ALREADY_STARTED is returned.
> + If an attempt is made to unregister a handler when a handler is not registered,
> + then EFI_INVALID_PARAMETER is returned.
> +
> + @param This The EFI_TIMER_ARCH_PROTOCOL instance.
> + @param NotifyFunction The function to call when a timer interrupt fires. This
> + function executes at TPL_HIGH_LEVEL. The DXE Core will
> + register a handler for the timer interrupt, so it can know
> + how much time has passed. This information is used to
> + signal timer based events. NULL will unregister the handler.
> +
> + @retval EFI_SUCCESS The watchdog timer handler was registered.
> + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
> + registered.
> + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
> + previously registered.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +WatchdogRegisterHandler (
> + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
> + IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
> + )
> +{
> + // ERROR: This function is not supported.
> + // The hardware watchdog will reset the board
> + return EFI_INVALID_PARAMETER;
> +}
> +
> +/**
> +
> + This function adjusts the period of timer interrupts to the value specified
> + by TimerPeriod. If the timer period is updated, then the selected timer
> + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
> + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
> + If an error occurs while attempting to update the timer period, then the
> + timer hardware will be put back in its state prior to this call, and
> + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
> + is disabled. This is not the same as disabling the CPU's interrupts.
> + Instead, it must either turn off the timer hardware, or it must adjust the
> + interrupt controller so that a CPU interrupt is not generated when the timer
> + interrupt fires.
> +
> + @param This The EFI_TIMER_ARCH_PROTOCOL instance.
> + @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
> + the timer hardware is not programmable, then EFI_UNSUPPORTED is
> + returned. If the timer is programmable, then the timer period
> + will be rounded up to the nearest timer period that is supported
> + by the timer hardware. If TimerPeriod is set to 0, then the
> + timer interrupts will be disabled.
> +
> +
> + @retval EFI_SUCCESS The timer period was changed.
> + @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
> + @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +WatchdogSetTimerPeriod (
> + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
> + IN UINT64 TimerPeriod // In 100ns units
> + )
> +{
> + EFI_STATUS Status;
> + UINT64 TimerPeriodInSec;
> + UINT16 Val;
> +
> + Status = EFI_SUCCESS;
> +
> + if (TimerPeriod == 0) {
> + // This is a watchdog stop request
> + WatchdogStop ();
> + return Status;
> + } else {
> + // Convert the TimerPeriod (in 100 ns unit) to an equivalent second value
> +
> + TimerPeriodInSec = DivU64x32 (TimerPeriod, NANO_SECOND_BASE);
> +
> + // The registers in the Watchdog are only 32 bits
> + if (TimerPeriodInSec > WATCHDOG_MAX_TIME) {
> + // We could load the watchdog with the maximum supported value but
> + // if a smaller value was requested, this could have the watchdog
> + // triggering before it was intended.
> + // Better generate an error to let the caller know.
> + Status = EFI_DEVICE_ERROR;
> + return Status;
> + }
> +
> + // set the new timeout value in the WCR
> + // Convert the timeout value from Seconds to timer count
> + Val = ((WATCHDOG_COUNT(TimerPeriodInSec) & WATCHDOG_COUNT_MASK) << 8);
> +
> + mMmioOps->AndThenOr16 (PcdGet64 (PcdWatchdog1BaseAddr) + WATCHDOG_WCR_OFFSET,
> + (UINT16)(~WATCHDOG_WCR_TIMEOUT),
> + Val);
> + // Start the watchdog
> + WatchdogStart ();
> + }
> +
> + return Status;
> +}
> +
> +/**
> + This function retrieves the period of timer interrupts in 100 ns units,
> + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
> + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
> + returned, then the timer is currently disabled.
> +
> + @param This The EFI_TIMER_ARCH_PROTOCOL instance.
> + @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
> + 0 is returned, then the timer is currently disabled.
> +
> +
> + @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
> + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +WatchdogGetTimerPeriod (
> + IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
> + OUT UINT64 *TimerPeriod
> + )
> +{
> + EFI_STATUS Status;
> + UINT64 ReturnValue;
> + UINT16 Val;
> +
> + Status = EFI_SUCCESS;
> +
> + if (TimerPeriod == NULL) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + // Check if the watchdog is stopped
> + if ((mMmioOps->Read16 (PcdGet64 (PcdWatchdog1BaseAddr) + WATCHDOG_WCR_OFFSET)
> + & WATCHDOG_WCR_ENABLE) == 0 ) {
> + // It is stopped, so return zero.
> + ReturnValue = 0;
> + } else {
> + // Convert the Watchdog ticks into equivalent TimerPeriod second value.
> + Val = (mMmioOps->Read16 (PcdGet64 (PcdWatchdog1BaseAddr) + WATCHDOG_WCR_OFFSET)
> + & WATCHDOG_WCR_TIMEOUT ) >> 8;
> + ReturnValue = WATCHDOG_SEC(Val);
> + }
> +
> + *TimerPeriod = ReturnValue;
> + return Status;
> +}
> +
> +/**
> + Interface structure for the Watchdog Architectural Protocol.
> +
> + @par Protocol Description:
> + This protocol provides a service to set the amount of time to wait
> + before firing the watchdog timer, and it also provides a service to
> + register a handler that is invoked when the watchdog timer fires.
> +
> + @par When the watchdog timer fires, control will be passed to a handler
> + if one has been registered. If no handler has been registered,
> + or the registered handler returns, then the system will be
> + reset by calling the Runtime Service ResetSystem().
> +
> + @param RegisterHandler
> + Registers a handler that will be called each time the
> + watchdogtimer interrupt fires. TimerPeriod defines the minimum
> + time between timer interrupts, so TimerPeriod will also
> + be the minimum time between calls to the registered
> + handler.
> + NOTE: If the watchdog resets the system in hardware, then
> + this function will not have any chance of executing.
> +
> + @param SetTimerPeriod
> + Sets the period of the timer interrupt in 100 nS units.
> + This function is optional, and may return EFI_UNSUPPORTED.
> + If this function is supported, then the timer period will
> + be rounded up to the nearest supported timer period.
> +
> + @param GetTimerPeriod
> + Retrieves the period of the timer interrupt in 100 nS units.
> +
> +**/
> +STATIC
> +EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = {
> + WatchdogRegisterHandler,
> + WatchdogSetTimerPeriod,
> + WatchdogGetTimerPeriod
> +};
> +
> +/**
> + Call back function when the timer event is signaled.
> + This function will feed the watchdog with maximum value
> + so that system wont reset in idle case e.g. stopped on UEFI shell.
> +
> + @param[in] Event The Event this notify function registered to.
> + @param[in] Context Pointer to the context data registered to the
> + Event.
> +
> +**/
> +VOID
> +EFIAPI
> +WatchdogFeed (
> + IN EFI_EVENT Event,
> + IN VOID* Context
> + )
> +{
> + WatchdogPing();
> +}
> +/**
> + Initialize state information for the Watchdog Timer Architectural Protocol.
> +
> + @param ImageHandle of the loaded driver
> + @param SystemTable Pointer to the System Table
> +
> + @retval EFI_SUCCESS Protocol registered
> + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
> + @retval EFI_DEVICE_ERROR Hardware problems
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +WatchdogInitialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE Handle;
> +
> + mMmioOps = GetMmioOperations16 (FixedPcdGetBool (PcdWatchdogBigEndian));
> +
> + mMmioOps->AndThenOr16 (PcdGet64 (PcdWatchdog1BaseAddr) + WATCHDOG_WCR_OFFSET,
> + (UINT16)(~WATCHDOG_WCR_TIMEOUT),
> + (WATCHDOG_COUNT (WATCHDOG_MAX_TIME) & WATCHDOG_COUNT_MASK));
> +
> + mMmioOps->Or16 (PcdGet64 (PcdWatchdog1BaseAddr) + WATCHDOG_WCR_OFFSET, WATCHDOG_WCR_ENABLE);
> +
> + //
> + // Make sure the Watchdog Timer Architectural Protocol
> + // has not been installed in the system yet.
> + // This will avoid conflicts with the universal watchdog
> + //
> + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid);
> +
> + // Register for an ExitBootServicesEvent
> + Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,
> + ExitBootServicesEvent, NULL, &mEfiExitBootServicesEvent);
> + if (EFI_ERROR (Status)) {
> + Status = EFI_OUT_OF_RESOURCES;
> + return Status;
> + }
> +
> + //
> + // Start the timer to feed Watchdog with maximum timeout value.
> + //
> + Status = gBS->CreateEvent (
> + EVT_TIMER | EVT_NOTIFY_SIGNAL,
> + TPL_NOTIFY,
> + WatchdogFeed,
> + NULL,
> + &mWatchdogFeedEvent
> + );
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + Status = gBS->SetTimer (mWatchdogFeedEvent, TimerPeriodic, WATCHDOG_FEED_INTERVAL);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + // Install the Timer Architectural Protocol onto a new handle
> + Handle = NULL;
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &Handle,
> + &gEfiWatchdogTimerArchProtocolGuid, &mWatchdogTimer,
> + NULL
> + );
> + if (EFI_ERROR (Status)) {
> + gBS->CloseEvent (mEfiExitBootServicesEvent);
> + Status = EFI_OUT_OF_RESOURCES;
> + return Status;
> + }
> +
> + WatchdogPing ();
> +
> + return Status;
> +}
> diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDog.h b/Silicon/NXP/Drivers/WatchDog/WatchDog.h
> new file mode 100644
> index 0000000..8262a69
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/WatchDog/WatchDog.h
> @@ -0,0 +1,32 @@
> +/** WatchDog.h
> +*
> +* Copyright 2017-2019 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#ifndef WATCHDOG_H_
> +#define WATCHDOG_H_
> +
> +#define WATCHDOG_SIZE 0x1000
> +#define WATCHDOG_WCR_OFFSET 0
> +#define WATCHDOG_WSR_OFFSET 2
> +#define WATCHDOG_WRSR_OFFSET 4
> +#define WATCHDOG_WICR_OFFSET 6
> +#define WATCHDOG_WCR_TIMEOUT (0xFF << 8)
> +#define WATCHDOG_WCR_ENABLE (1 << 2)
> +#define WATCHDOG_SERVICE_SEQ1 0x5555
> +#define WATCHDOG_SERVICE_SEQ2 0xAAAA
> +#define WATCHDOG_WCR_WRE (1 << 3) /* -> WATCHDOG Reset Enable */
> +
> +#define WATCHDOG_MAX_TIME 128
> +#define WATCHDOG_COUNT(Sec) (((Sec) * 2 - 1) << 8)
> +#define WATCHDOG_COUNT_MASK 0xff00
> +#define WATCHDOG_SEC(Cnt) (((Cnt) + 1) / 2)
> +
> +#define NANO_SECOND_BASE 10000000
> +
> +#define WATCHDOG_FEED_INTERVAL (WATCHDOG_MAX_TIME * NANO_SECOND_BASE)
> +
> +#endif //WATCHDOG_H_
> diff --git a/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf b/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> new file mode 100644
> index 0000000..2d410a9
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> @@ -0,0 +1,41 @@
> +# WatchDog.inf
> +#
> +# Component description file for WatchDog module
> +#
> +# Copyright 2017-2019 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = WatchDogDxe
> + FILE_GUID = 0358b544-ec65-4339-89cd-cad60a3dd787
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = WatchdogInitialize
> +
> +[Sources.common]
> + WatchDog.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + IoAccessLib
> + PcdLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian
> +
> +[Protocols]
> + gEfiWatchdogTimerArchProtocolGuid
> +
> +[Depex]
> + TRUE
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 04/12] SocLib : Add support for initialization of peripherals
[not found] ` <1570639758-30355-5-git-send-email-meenakshi.aggarwal@nxp.com>
@ 2019-10-10 11:17 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-10-10 11:17 UTC (permalink / raw)
To: Meenakshi Aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, devel, v.sethi
On Wed, Oct 09, 2019 at 10:19:10PM +0530, Meenakshi Aggarwal wrote:
> Add SocInit function that initializes peripherals
> and print board and soc information.
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 ++++
> Silicon/NXP/Include/Chassis2/NxpSoc.h | 361 +++++++++++++++++++
> Silicon/NXP/Include/DramInfo.h | 38 ++
> Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 +++
> Silicon/NXP/Library/SocLib/Chassis.c | 498 +++++++++++++++++++++++++++
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 162 +++++++++
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 45 +++
> Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ++++++++
> Silicon/NXP/Library/SocLib/SerDes.c | 268 ++++++++++++++
> 9 files changed, 1621 insertions(+)
> create mode 100644 Silicon/NXP/Include/Chassis2/LsSerDes.h
> create mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
> create mode 100644 Silicon/NXP/Include/DramInfo.h
> create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
> create mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> create mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> create mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
> create mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
>
> diff --git a/Silicon/NXP/Include/Chassis2/LsSerDes.h b/Silicon/NXP/Include/Chassis2/LsSerDes.h
> new file mode 100644
> index 0000000..9afbc52
> --- /dev/null
> +++ b/Silicon/NXP/Include/Chassis2/LsSerDes.h
> @@ -0,0 +1,62 @@
> +/** LsSerDes.h
> + The Header file of SerDes Module for Chassis 2
> +
> + Copyright 2017-2019 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef LS_SERDES_H_
> +#define LS_SERDES_H_
> +
> +#include <Uefi/UefiBaseType.h>
> +
> +#define SRDS_MAX_LANES 4
> +
> +typedef enum {
> + None = 0,
> + Pcie1,
> + Pcie2,
> + Pcie3,
> + Sata,
> + SgmiiFm1Dtsec1,
> + SgmiiFm1Dtsec2,
> + SgmiiFm1Dtsec5,
> + SgmiiFm1Dtsec6,
> + SgmiiFm1Dtsec9,
> + SgmiiFm1Dtsec10,
> + QsgmiiFm1A,
> + XfiFm1Mac9,
> + XfiFm1Mac10,
> + Sgmii2500Fm1Dtsec2,
> + Sgmii2500Fm1Dtsec5,
> + Sgmii2500Fm1Dtsec9,
> + Sgmii2500Fm1Dtsec10,
> + SerdesPrtclCount
> +} SERDES_PROTOCOL;
> +
> +typedef enum {
> + Srds1 = 0,
> + Srds2,
> + SrdsMaxNum
> +} SERDES_NUMBER;
> +
> +typedef struct {
> + UINT16 Protocol;
> + UINT8 SrdsLane[SRDS_MAX_LANES];
> +} SERDES_CONFIG;
> +
> +typedef VOID
> +(*SERDES_PROBE_LANES_CALLBACK) (
> + IN SERDES_PROTOCOL LaneProtocol,
> + IN VOID *Arg
> + );
> +
> +VOID
> +SerDesProbeLanes(
> + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> + IN VOID *Arg
> + );
> +
> +#endif /* LS_SERDES_H_ */
> diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> new file mode 100644
> index 0000000..f05a813
> --- /dev/null
> +++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
> @@ -0,0 +1,361 @@
> +/** Soc.h
> +* Header defining the Base addresses, sizes, flags etc for chassis 1
> +*
> +* Copyright 2017-2019 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#ifndef NXP_SOC_H_
> +#define NXP_SOC_H_
> +
> +#define HWA_CGA_M1_CLK_SEL 0xe0000000
> +#define HWA_CGA_M1_CLK_SHIFT 29
> +
> +#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
> +#define NUM_CC_PLLS 2
> +#define CLK_FREQ 100000000
> +#define MAX_CPUS 4
> +#define NUM_FMAN 1
> +#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
> +
> +/* RCW SERDES MACRO */
> +#define RCWSR_INDEX 4
> +#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
> +#define RCWSR_SRDS1_PRTCL_SHIFT 16
> +#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
> +#define RCWSR_SRDS2_PRTCL_SHIFT 0
> +
> +/* SMMU Defintions */
> +#define SMMU_BASE_ADDR 0x09000000
> +#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
> +#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
> +#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
> +#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
> +#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
> +
> +#define SCR0_USFCFG_MASK 0x00000400
> +#define SCR0_CLIENTPD_MASK 0x00000001
> +#define SACR_PAGESIZE_MASK 0x00010000
> +#define IDR1_PAGESIZE_MASK 0x80000000
> +
> +typedef struct {
> + UINTN FreqProcessor[MAX_CPUS];
> + UINTN FreqSystemBus;
> + UINTN FreqDdrBus;
> + UINTN FreqLocalBus;
> + UINTN FreqSdhc;
> + UINTN FreqFman[NUM_FMAN];
> + UINTN FreqQman;
> +} SYS_INFO;
> +
> +/* Device Configuration and Pin Control */
> +typedef struct {
> + UINT32 PorSr1; /* POR status 1 */
> +#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
> + UINT32 PorSr2; /* POR status 2 */
> + UINT8 Res008[0x20-0x8];
> + UINT32 GppOrCr1; /* General-purpose POR configuration */
> + UINT32 GppOrCr2;
> + UINT32 DcfgFuseSr; /* Fuse status register */
> + UINT8 Res02c[0x70-0x2c];
> + UINT32 DevDisr; /* Device disable control */
> + UINT32 DevDisr2; /* Device disable control 2 */
> + UINT32 DevDisr3; /* Device disable control 3 */
> + UINT32 DevDisr4; /* Device disable control 4 */
> + UINT32 DevDisr5; /* Device disable control 5 */
> + UINT32 DevDisr6; /* Device disable control 6 */
> + UINT32 DevDisr7; /* Device disable control 7 */
> + UINT8 Res08c[0x94-0x8c];
> + UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
> + UINT32 CoreDisrL; /* lower portion for support of 64 cores */
> + UINT8 Res09c[0xa0-0x9c];
> + UINT32 Pvr; /* Processor version */
> + UINT32 Svr; /* System version */
> + UINT32 Mvr; /* Manufacturing version */
> + UINT8 Res0ac[0xb0-0xac];
> + UINT32 RstCr; /* Reset control */
> + UINT32 RstRqPblSr; /* Reset request preboot loader status */
> + UINT8 Res0b8[0xc0-0xb8];
> + UINT32 RstRqMr1; /* Reset request mask */
> + UINT8 Res0c4[0xc8-0xc4];
> + UINT32 RstRqSr1; /* Reset request status */
> + UINT8 Res0cc[0xd4-0xcc];
> + UINT32 RstRqWdTmrL; /* Reset request WDT mask */
> + UINT8 Res0d8[0xdc-0xd8];
> + UINT32 RstRqWdtSrL; /* Reset request WDT status */
> + UINT8 Res0e0[0xe4-0xe0];
> + UINT32 BrrL; /* Boot release */
> + UINT8 Res0e8[0x100-0xe8];
> + UINT32 RcwSr[16]; /* Reset control word status */
> +#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
> +#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
> +#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
> +#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
> + UINT8 Res140[0x200-0x140];
> + UINT32 ScratchRw[4]; /* Scratch Read/Write */
> + UINT8 Res210[0x300-0x210];
> + UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
> + UINT8 Res310[0x400-0x310];
> + UINT32 CrstSr[12];
> + UINT8 Res430[0x500-0x430];
> + /* PCI Express n Logical I/O Device Number register */
> + UINT32 DcfgCcsrPex1LiodNr;
> + UINT32 DcfgCcsrPex2LiodNr;
> + UINT32 DcfgCcsrPex3LiodNr;
> + UINT32 DcfgCcsrPex4LiodNr;
> + /* RIO n Logical I/O Device Number register */
> + UINT32 DcfgCcsrRio1LiodNr;
> + UINT32 DcfgCcsrRio2LiodNr;
> + UINT32 DcfgCcsrRio3LiodNr;
> + UINT32 DcfgCcsrRio4LiodNr;
> + /* USB Logical I/O Device Number register */
> + UINT32 DcfgCcsrUsb1LiodNr;
> + UINT32 DcfgCcsrUsb2LiodNr;
> + UINT32 DcfgCcsrUsb3LiodNr;
> + UINT32 DcfgCcsrUsb4LiodNr;
> + /* SD/MMC Logical I/O Device Number register */
> + UINT32 DcfgCcsrSdMmc1LiodNr;
> + UINT32 DcfgCcsrSdMmc2LiodNr;
> + UINT32 DcfgCcsrSdMmc3LiodNr;
> + UINT32 DcfgCcsrSdMmc4LiodNr;
> + /* RIO Message Unit Logical I/O Device Number register */
> + UINT32 DcfgCcsrRiomaintLiodNr;
> + UINT8 Res544[0x550-0x544];
> + UINT32 SataLiodNr[4];
> + UINT8 Res560[0x570-0x560];
> + UINT32 DcfgCcsrMisc1LiodNr;
> + UINT32 DcfgCcsrMisc2LiodNr;
> + UINT32 DcfgCcsrMisc3LiodNr;
> + UINT32 DcfgCcsrMisc4LiodNr;
> + UINT32 DcfgCcsrDma1LiodNr;
> + UINT32 DcfgCcsrDma2LiodNr;
> + UINT32 DcfgCcsrDma3LiodNr;
> + UINT32 DcfgCcsrDma4LiodNr;
> + UINT32 DcfgCcsrSpare1LiodNr;
> + UINT32 DcfgCcsrSpare2LiodNr;
> + UINT32 DcfgCcsrSpare3LiodNr;
> + UINT32 DcfgCcsrSpare4LiodNr;
> + UINT8 Res5a0[0x600-0x5a0];
> + UINT32 DcfgCcsrPblSr;
> + UINT32 PamuBypENr;
> + UINT32 DmaCr1;
> + UINT8 Res60c[0x610-0x60c];
> + UINT32 DcfgCcsrGenSr1;
> + UINT32 DcfgCcsrGenSr2;
> + UINT32 DcfgCcsrGenSr3;
> + UINT32 DcfgCcsrGenSr4;
> + UINT32 DcfgCcsrGenCr1;
> + UINT32 DcfgCcsrGenCr2;
> + UINT32 DcfgCcsrGenCr3;
> + UINT32 DcfgCcsrGenCr4;
> + UINT32 DcfgCcsrGenCr5;
> + UINT32 DcfgCcsrGenCr6;
> + UINT32 DcfgCcsrGenCr7;
> + UINT8 Res63c[0x658-0x63c];
> + UINT32 DcfgCcsrcGenSr1;
> + UINT32 DcfgCcsrcGenSr0;
> + UINT8 Res660[0x678-0x660];
> + UINT32 DcfgCcsrcGenCr1;
> + UINT32 DcfgCcsrcGenCr0;
> + UINT8 Res680[0x700-0x680];
> + UINT32 DcfgCcsrSrIoPstecr;
> + UINT32 DcfgCcsrDcsrCr;
> + UINT8 Res708[0x740-0x708]; /* add more registers when needed */
> + UINT32 TpItyp[64]; /* Topology Initiator Type Register */
> + struct {
> + UINT32 Upper;
> + UINT32 Lower;
> + } TpCluster[16];
> + UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
> + UINT32 DcfgCcsrQmBmWarmRst;
> + UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
> + UINT32 DcfgCcsrReserved0;
> + UINT32 DcfgCcsrReserved1;
> +} CCSR_GUR;
> +
> +/* Supplemental Configuration Unit */
> +typedef struct {
> + UINT8 Res000[0x070-0x000];
> + UINT32 Usb1Prm1Cr;
> + UINT32 Usb1Prm2Cr;
> + UINT32 Usb1Prm3Cr;
> + UINT32 Usb2Prm1Cr;
> + UINT32 Usb2Prm2Cr;
> + UINT32 Usb2Prm3Cr;
> + UINT32 Usb3Prm1Cr;
> + UINT32 Usb3Prm2Cr;
> + UINT32 Usb3Prm3Cr;
> + UINT8 Res094[0x100-0x094];
> + UINT32 Usb2Icid;
> + UINT32 Usb3Icid;
> + UINT8 Res108[0x114-0x108];
> + UINT32 DmaIcid;
> + UINT32 SataIcid;
> + UINT32 Usb1Icid;
> + UINT32 QeIcid;
> + UINT32 SdhcIcid;
> + UINT32 EdmaIcid;
> + UINT32 EtrIcid;
> + UINT32 Core0SftRst;
> + UINT32 Core1SftRst;
> + UINT32 Core2SftRst;
> + UINT32 Core3SftRst;
> + UINT8 Res140[0x158-0x140];
> + UINT32 AltCBar;
> + UINT32 QspiCfg;
> + UINT8 Res160[0x180-0x160];
> + UINT32 DmaMcr;
> + UINT8 Res184[0x188-0x184];
> + UINT32 GicAlign;
> + UINT32 DebugIcid;
> + UINT8 Res190[0x1a4-0x190];
> + UINT32 SnpCnfGcr;
> +#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
> +#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
> +#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
> +#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
> +#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
> +#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
> +#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
> +#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
> +#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
> +#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
> + UINT8 Res1a8[0x1ac-0x1a8];
> + UINT32 IntpCr;
> + UINT8 Res1b0[0x204-0x1b0];
> + UINT32 CoreSrEnCr;
> + UINT8 Res208[0x220-0x208];
> + UINT32 RvBar00;
> + UINT32 RvBar01;
> + UINT32 RvBar10;
> + UINT32 RvBar11;
> + UINT32 RvBar20;
> + UINT32 RvBar21;
> + UINT32 RvBar30;
> + UINT32 RvBar31;
> + UINT32 LpmCsr;
> + UINT8 Res244[0x400-0x244];
> + UINT32 QspIdQScr;
> + UINT32 EcgTxcMcr;
> + UINT32 SdhcIoVSelCr;
> + UINT32 RcwPMuxCr0;
> + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> + *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> + *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
> + Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
> +#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
> + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
> + *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
> + *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
> + Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
> +#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
> + UINT32 UsbDrvVBusSelCr;
> +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
> +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
> +#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
> + UINT32 UsbPwrFaultSelCr;
> +#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
> +#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
> +#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
> +#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
> +#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
> +#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
> + UINT32 UsbRefclkSelcr1;
> + UINT32 UsbRefclkSelcr2;
> + UINT32 UsbRefclkSelcr3;
> + UINT8 Res424[0x600-0x424];
> + UINT32 ScratchRw[4];
> + UINT8 Res610[0x680-0x610];
> + UINT32 CoreBCr;
> + UINT8 Res684[0x1000-0x684];
> + UINT32 Pex1MsiIr;
> + UINT32 Pex1MsiR;
> + UINT8 Res1008[0x2000-0x1008];
> + UINT32 Pex2;
> + UINT32 Pex2MsiR;
> + UINT8 Res2008[0x3000-0x2008];
> + UINT32 Pex3MsiIr;
> + UINT32 Pex3MsiR;
> +} CCSR_SCFG;
> +
> +#define USB_TXVREFTUNE 0x9
> +#define USB_SQRXTUNE 0xFC7FFFFF
> +#define USB_PCSTXSWINGFULL 0x47
> +#define USB_PHY_RX_EQ_VAL_1 0x0000
> +#define USB_PHY_RX_EQ_VAL_2 0x8000
> +#define USB_PHY_RX_EQ_VAL_3 0x8003
> +#define USB_PHY_RX_EQ_VAL_4 0x800b
> +
> +/*USB_PHY_SS memory map*/
> +typedef struct {
> + UINT16 IpIdcodeLo;
> + UINT16 SupIdcodeHi;
> + UINT8 Res4[0x0006-0x0004];
> + UINT16 RtuneDebug;
> + UINT16 RtuneStat;
> + UINT16 SupSsPhase;
> + UINT16 SsFreq;
> + UINT8 ResE[0x0020-0x000e];
> + UINT16 Ateovrd;
> + UINT16 MpllOvrdInLo;
> + UINT8 Res24[0x0026-0x0024];
> + UINT16 SscOvrdIn;
> + UINT8 Res28[0x002A-0x0028];
> + UINT16 LevelOvrdIn;
> + UINT8 Res2C[0x0044-0x002C];
> + UINT16 ScopeCount;
> + UINT8 Res46[0x0060-0x0046];
> + UINT16 MpllLoopCtl;
> + UINT8 Res62[0x006C-0x0062];
> + UINT16 SscClkCntrl;
> + UINT8 Res6E[0x2002-0x006E];
> + UINT16 Lane0TxOvrdInHi;
> + UINT16 Lane0TxOvrdDrvLo;
> + UINT8 Res2006[0x200C-0x2006];
> + UINT16 Lane0RxOvrdInHi;
> + UINT8 Res200E[0x2022-0x200E];
> + UINT16 Lane0TxCmWaitTimeOvrd;
> + UINT8 Res2024[0x202A-0x2024];
> + UINT16 Lane0TxLbertCtl;
> + UINT16 Lane0RxLbertCtl;
> + UINT16 Lane0RxLbertErr;
> + UINT8 Res2030[0x205A-0x2030];
> + UINT16 Lane0TxAltBlock;
> +} CCSR_USB_PHY;
> +
> +/* Clocking */
> +typedef struct {
> + struct {
> + UINT32 ClkCnCSr; /* core cluster n clock control status */
> + UINT8 Res004[0x0c];
> + UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
> + UINT8 Res014[0x0c];
> + } ClkcSr[4];
> + UINT8 Res040[0x780]; /* 0x100 */
> + struct {
> + UINT32 PllCnGSr;
> + UINT8 Res804[0x1c];
> + } PllCgSr[NUM_CC_PLLS];
> + UINT8 Res840[0x1c0];
> + UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
> + UINT8 Resa04[0x1fc];
> + UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
> + UINT8 Resc04[0x1c];
> + UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
> + UINT8 Resc24[0x3dc];
> +} CCSR_CLOCK;
> +
> +VOID
> +GetSysInfo (
> + OUT SYS_INFO *
> + );
> +
> +UINT32
> +EFIAPI
> +GurRead (
> + IN UINTN Address
> + );
> +
> +#endif /* NXP_SOC_H_ */
> diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h
> new file mode 100644
> index 0000000..a934aae
> --- /dev/null
> +++ b/Silicon/NXP/Include/DramInfo.h
> @@ -0,0 +1,38 @@
> +/** @file
> +* Header defining the structure for Dram Information
> +*
> +* Copyright 2019 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#ifndef DRAM_INFO_H_
> +#define DRAM_INFO_H_
> +
> +#include <Uefi/UefiBaseType.h>
> +
> +#define SMC_DRAM_BANK_INFO (0xC200FF12)
> +
> +typedef struct {
> + UINTN BaseAddress;
> + UINTN Size;
> +} DRAM_REGION_INFO;
> +
> +typedef struct {
> + UINT32 NumOfDrams;
> + UINT32 Reserved;
> + DRAM_REGION_INFO DramRegion[3];
> +} DRAM_INFO;
> +
> +EFI_STATUS
> +GetDramBankInfo (
> + IN OUT DRAM_INFO *DramInfo
> + );
> +
> +VOID
> +UpdateDpaaDram (
> + IN OUT DRAM_INFO *DramInfo
> + );
> +
> +#endif /* DRAM_INFO_H_ */
> diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
> new file mode 100644
> index 0000000..2d1c6f1
> --- /dev/null
> +++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h
> @@ -0,0 +1,51 @@
> +/** @file
> + The Header file of SerDes Module for LS1043A
> +
> + Copyright 2017-2019 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef SOC_SERDES_H_
> +#define SOC_SERDES_H_
> +
> +#ifdef CHASSIS2
> +#include <Chassis2/LsSerDes.h>
> +#endif
> +
> +SERDES_CONFIG SerDes1ConfigTbl[] = {
> + /* SerDes 1 */
> + {0x1555, {XfiFm1Mac9, Pcie1, Pcie2, Pcie3 } },
> + {0x2555, {Sgmii2500Fm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
> + {0x4555, {QsgmiiFm1A, Pcie1, Pcie2, Pcie3 } },
> + {0x4558, {QsgmiiFm1A, Pcie1, Pcie2, Sata } },
> + {0x1355, {XfiFm1Mac9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
> + {0x2355, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
> + {0x3335, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, Pcie3 } },
> + {0x3355, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
> + {0x3358, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Sata } },
> + {0x3555, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
> + {0x3558, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Sata } },
> + {0x7000, {Pcie1, Pcie1, Pcie1, Pcie1 } },
> + {0x9998, {Pcie1, Pcie2, Pcie3, Sata } },
> + {0x6058, {Pcie1, Pcie1, Pcie2, Sata } },
> + {0x1455, {XfiFm1Mac9, QsgmiiFm1A, Pcie2, Pcie3 } },
> + {0x2455, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
> + {0x2255, {Sgmii2500Fm1Dtsec9, Sgmii2500Fm1Dtsec2, Pcie2, Pcie3 } },
> + {0x3333, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
> + {0x1460, {XfiFm1Mac9, QsgmiiFm1A, Pcie3, Pcie3 } },
> + {0x2460, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
> + {0x3460, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
> + {0x3455, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
> + {0x9960, {Pcie1, Pcie2, Pcie3, Pcie3 } },
> + {0x2233, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 }},
> + {0x2533, {Sgmii2500Fm1Dtsec9, Pcie1, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
> + {}
> +};
> +
> +SERDES_CONFIG *SerDesConfigTbl[] = {
> + SerDes1ConfigTbl
> +};
> +
> +#endif /* SOC_SERDES_H_ */
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> new file mode 100644
> index 0000000..5dda6f8
> --- /dev/null
> +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> @@ -0,0 +1,498 @@
> +/** @file
> + SoC specific Library containg functions to initialize various SoC components
> +
> + Copyright 2017-2019 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#ifdef CHASSIS2
> +#include <Chassis2/NxpSoc.h>
> +#elif CHASSIS3
> +#include <Chassis3/NxpSoc.h>
> +#endif
> +#include <Library/ArmSmcLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +#include <DramInfo.h>
> +#include "NxpChassis.h"
> +
> +/*
> + * Structure to list available SOCs.
> + * Name, Soc Version, Number of Cores
> + */
> +STATIC CPU_TYPE mCpuTypeList[] = {
> + CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
> + CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
> + CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
> +};
> +
> +UINT32
> +EFIAPI
> +GurRead (
> + IN UINTN Address
> + )
> +{
> + if (FixedPcdGetBool (PcdGurBigEndian)) {
> + return SwapMmioRead32 (Address);
> + } else {
> + return MmioRead32 (Address);
> + }
> +}
> +
> +/*
> + * Return the type of initiator (core or hardware accelerator)
> + */
> +UINT32
> +InitiatorType (
> + IN UINT32 Cluster,
> + IN UINTN InitId
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINT32 Idx;
> + UINT32 Type;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
> + Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
> +
> + if (Type & TP_ITYP_AV_MASK) {
> + return Type;
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * Return the mask for number of cores on this SOC.
> + */
> +UINT32
> +CpuMask (
> + VOID
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINTN ClusterIndex;
> + UINTN Count;
> + UINT32 Cluster;
> + UINT32 Type;
> + UINT32 Mask;
> + UINTN InitiatorIndex;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClusterIndex = 0;
> + Count = 0;
> + Mask = 0;
> +
> + do {
> + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> + Type = InitiatorType (Cluster, InitiatorIndex);
> + if (Type) {
> + if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) {
> + Mask |= 1 << Count;
> + }
> + Count++;
> + }
> + }
> + ClusterIndex++;
> + } while (CHECK_CLUSTER (Cluster));
> +
> + return Mask;
> +}
> +
> +/*
> + * Return the number of cores on this SOC.
> + */
> +UINTN
> +CpuNumCores (
> + VOID
> + )
> +{
> + UINTN Count;
> + UINTN Num;
> +
> + Count = 0;
> + Num = CpuMask ();
> +
> + while (Num) {
> + Count += Num & 1;
> + Num >>= 1;
> + }
> +
> + return Count;
> +}
> +
> +/*
> + * Return core's cluster
> + */
> +INT32
> +QoriqCoreToCluster (
> + IN UINTN Core
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINTN ClusterIndex;
> + UINTN Count;
> + UINT32 Cluster;
> + UINT32 Type;
> + UINTN InitiatorIndex;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClusterIndex = 0;
> + Count = 0;
> + do {
> + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> + Type = InitiatorType (Cluster, InitiatorIndex);
> + if (Type) {
> + if (Count == Core) {
> + return ClusterIndex;
> + }
> + Count++;
> + }
> + }
> + ClusterIndex++;
> + } while (CHECK_CLUSTER (Cluster));
> +
> + return -1; // cannot identify the cluster
> +}
> +
> +/*
> + * Return the type of core i.e. A53, A57 etc of inputted
> + * core number.
> + */
> +UINTN
> +QoriqCoreToType (
> + IN UINTN Core
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINTN ClusterIndex;
> + UINTN Count;
> + UINT32 Cluster;
> + UINT32 Type;
> + UINTN InitiatorIndex;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClusterIndex = 0;
> + Count = 0;
> +
> + do {
> + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> + Type = InitiatorType (Cluster, InitiatorIndex);
> + if (Type) {
> + if (Count == Core) {
> + return Type;
> + }
> + Count++;
> + }
> + }
> + ClusterIndex++;
> + } while (CHECK_CLUSTER (Cluster));
> +
> + return EFI_NOT_FOUND; /* cannot identify the cluster */
> +}
> +
> +STATIC
> +UINTN
> +CpuMaskNext (
> + IN UINTN Cpu,
> + IN UINTN Mask
> + )
> +{
> + for (Cpu++; !((1 << Cpu) & Mask); Cpu++);
> +
> + return Cpu;
> +}
> +
> +/*
> + * Print CPU information
> + */
> +VOID
> +PrintCpuInfo (
> + VOID
> + )
> +{
> + SYS_INFO SysInfo;
> + UINTN CoreIndex;
> + UINTN Core;
> + UINT32 Type;
> + UINT32 NumCpus;
> + UINT32 Mask;
> + CHAR8 *CoreName;
> +
> + GetSysInfo (&SysInfo);
> + DEBUG ((DEBUG_INIT, "Clock Configuration:"));
> +
> + NumCpus = CpuNumCores ();
> + Mask = CpuMask ();
> +
> + for (CoreIndex = 0, Core = CpuMaskNext(-1, Mask);
> + CoreIndex < NumCpus;
> + CoreIndex++, Core = CpuMaskNext(Core, Mask))
> + {
> + if (!(CoreIndex % 3)) {
> + DEBUG ((DEBUG_INIT, "\n "));
> + }
> +
> + Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
> + switch (Type) {
> + case TY_ITYP_VERSION_A7:
> + CoreName = "A7";
> + break;
> + case TY_ITYP_VERSION_A53:
> + CoreName = "A53";
> + break;
> + case TY_ITYP_VERSION_A57:
> + CoreName = "A57";
> + break;
> + case TY_ITYP_VERSION_A72:
> + CoreName = "A72";
> + break;
> + default:
> + CoreName = " Unknown Core ";
> + }
> + DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ",
> + Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ));
> + }
> +
> + DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ));
> + DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ));
> +
> + if (SysInfo.FreqFman[0] != 0) {
> + DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ));
> + }
> +
> + DEBUG ((DEBUG_INIT, "\n"));
> +}
> +
> +/*
> + * Return system bus frequency
> + */
> +UINT64
> +GetBusFrequency (
> + VOID
> + )
> +{
> + SYS_INFO SocSysInfo;
> +
> + GetSysInfo (&SocSysInfo);
> +
> + return SocSysInfo.FreqSystemBus;
> +}
> +
> +/*
> + * Return SDXC bus frequency
> + */
> +UINT64
> +GetSdxcFrequency (
> + VOID
> + )
> +{
> + SYS_INFO SocSysInfo;
> +
> + GetSysInfo (&SocSysInfo);
> +
> + return SocSysInfo.FreqSdhc;
> +}
> +
> +/*
> + * Print Soc information
> + */
> +VOID
> +PrintSoc (
> + VOID
> + )
> +{
> + CHAR8 Buf[20];
> + CCSR_GUR *GurBase;
> + UINTN Count;
> + //
> + // Svr : System Version Register
> + //
> + UINTN Svr;
> + UINTN Ver;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> +
> + Svr = GurRead ((UINTN)&GurBase->Svr);
> + Ver = SVR_SOC_VER (Svr);
> +
> + for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
> + if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
> + AsciiStrCpyS (Buf, AsciiStrnLenS (mCpuTypeList[Count].Name, 7) + 1,
mCpuTypeList[Count].Name is statically defined - you would be
able to use sizeof() instead (and not need the + 1 adjustment).
The use of the live-coded integer nullifies the point of using
AsciiStrnLenS anyway.
However, the second parameter is "DestMax", not "SourceMax" - so
sizeof (Buf) is what you actually want here.
> + (CONST CHAR8 *)mCpuTypeList[Count].Name);
That CONST belongs in the struct declararation, not at point of use.
> +
> + if (IS_E_PROCESSOR (Svr)) {
> + AsciiStrCatS (Buf,
> + (AsciiStrLen (Buf) + AsciiStrLen ((CONST CHAR8 *)"E") + 1),
> + (CONST CHAR8 *)"E");
Again, "DestMax" is simply sizeof (Buf).
And why do we need to cast string literals to "CONST CHAR 8 *"?
Isn't that their type already? (Certainly works fine without them at
my end.)
No comments beyond this point.
/
Leif
> + }
> + break;
> + }
> + }
> +
> + DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
> + Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
> +
> + return;
> +}
> +
> +/*
> + * Dump RCW (Reset Control Word) on console
> + */
> +VOID
> +PrintRCW (
> + VOID
> + )
> +{
> + CCSR_GUR *Base;
> + UINTN Count;
> +
> + Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> +
> + /*
> + * Display the RCW, so that no one gets confused as to what RCW
> + * we're actually using for this boot.
> + */
> +
> + DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):"));
> + for (Count = 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) {
> + UINT32 Rcw = SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]);
> +
> + if ((Count % 4) == 0) {
> + DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4));
> + }
> +
> + DEBUG ((DEBUG_INIT, " %08x", Rcw));
> + }
> +
> + DEBUG ((DEBUG_INIT, "\n"));
> +}
> +
> +/*
> + * Setup SMMU in bypass mode
> + * and also set its pagesize
> + */
> +VOID
> +SmmuInit (
> + VOID
> + )
> +{
> + UINT32 Value;
> +
> + /* set pagesize as 64K and ssmu-500 in bypass mode */
> + Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
> + MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
> +
> + Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> + MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
> +
> + Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
> + MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
> +}
> +
> +/*
> + * Return current Soc Name form mCpuTypeList
> + */
> +CHAR8 *
> +GetSocName (
> + VOID
> + )
> +{
> + UINT8 Count;
> + UINTN Svr;
> + UINTN Ver;
> + CCSR_GUR *GurBase;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> +
> + Svr = GurRead ((UINTN)&GurBase->Svr);
> + Ver = SVR_SOC_VER (Svr);
> +
> + for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
> + if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
> + return (CHAR8 *)mCpuTypeList[Count].Name;
> + }
> + }
> +
> + return NULL;
> +}
> +
> +UINTN
> +GetDramSize (
> + IN VOID
> + )
> +{
> + ARM_SMC_ARGS ArmSmcArgs;
> +
> + ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> + ArmSmcArgs.Arg1 = -1;
> +
> + ArmCallSmc (&ArmSmcArgs);
> +
> + if (ArmSmcArgs.Arg0) {
> + return 0;
> + } else {
> + return ArmSmcArgs.Arg1;
> + }
> +}
> +
> +EFI_STATUS
> +GetDramBankInfo (
> + IN OUT DRAM_INFO *DramInfo
> + )
> +{
> + ARM_SMC_ARGS ArmSmcArgs;
> + UINT32 I;
> + UINTN DramSize;
> +
> + DramSize = GetDramSize ();
> + DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize));
> +
> + // Ensure DramSize has been set
> + ASSERT (DramSize != 0);
> +
> + I = 0;
> +
> + do {
> + ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
> + ArmSmcArgs.Arg1 = I;
> +
> + ArmCallSmc (&ArmSmcArgs);
> + if (ArmSmcArgs.Arg0) {
> + if (I > 0) {
> + break;
> + } else {
> + ASSERT (ArmSmcArgs.Arg0 == 0);
> + }
> + }
> +
> + DramInfo->DramRegion[I].BaseAddress = ArmSmcArgs.Arg1;
> + DramInfo->DramRegion[I].Size = ArmSmcArgs.Arg2;
> +
> + DramSize -= DramInfo->DramRegion[I].Size;
> +
> + DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n",
> + I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size));
> +
> + I++;
> + } while (DramSize);
> +
> + DramInfo->NumOfDrams = I;
> +
> + DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDrams));
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> new file mode 100644
> index 0000000..bfb8b8c
> --- /dev/null
> +++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> @@ -0,0 +1,162 @@
> +/** @Soc.c
> + SoC specific Library containg functions to initialize various SoC components
> +
> + Copyright 2017-2019 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#include <NxpChassis.h>
> +#include <Chassis2/NxpSoc.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +/**
> + Calculate the frequency of various controllers and
> + populate the passed structure with frequuencies.
> +
> + @param PtrSysInfo Input structure to populate with
> + frequencies.
> +**/
> +VOID
> +GetSysInfo (
> + OUT SYS_INFO *PtrSysInfo
> + )
> +{
> + CCSR_GUR *GurBase;
> + CCSR_CLOCK *ClkBase;
> + UINTN CpuIndex;
> + UINT32 TempRcw;
> + UINT32 CPllSel;
> + UINT32 CplxPll;
> + CONST UINT8 CoreCplxPll[8] = {
> + [0] = 0, /* CC1 PPL / 1 */
> + [1] = 0, /* CC1 PPL / 2 */
> + [4] = 1, /* CC2 PPL / 1 */
> + [5] = 1, /* CC2 PPL / 2 */
> + };
> +
> + CONST UINT8 CoreCplxPllDivisor[8] = {
> + [0] = 1, /* CC1 PPL / 1 */
> + [1] = 2, /* CC1 PPL / 2 */
> + [4] = 1, /* CC2 PPL / 1 */
> + [5] = 2, /* CC2 PPL / 2 */
> + };
> +
> + UINTN PllCount;
> + UINTN FreqCPll[NUM_CC_PLLS];
> + UINTN PllRatio[NUM_CC_PLLS];
> + UINTN SysClk;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
> + SysClk = CLK_FREQ;
> +
> + SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
> +
> + PtrSysInfo->FreqSystemBus = SysClk;
> + PtrSysInfo->FreqDdrBus = SysClk;
> +
> + //
> + // selects the platform clock:SYSCLK ratio and calculate
> + // system frequency
> + //
> + PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> + CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> + CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> + //
> + // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
> + //
> + PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
> + CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
> + CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
> +
> + for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
> + PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
> + if (PllRatio[PllCount] > 4) {
> + FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
> + } else {
> + FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
> + }
> + }
> +
> + //
> + // Calculate Core frequency
> + //
> + for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
> + CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) & 0xf;
> + CplxPll = CoreCplxPll[CPllSel];
> +
> + PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
> + }
> +
> + //
> + // Calculate FMAN frequency
> + //
> + TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
> + switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
> + case 2:
> + PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
> + break;
> + case 3:
> + PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
> + break;
> + case 4:
> + PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
> + break;
> + case 5:
> + PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
> + break;
> + case 6:
> + PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
> + break;
> + case 7:
> + PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
> + break;
> + default:
> + DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
> + break;
> + }
> + PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
> + PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
> +}
> +
> +/**
> + Function to initialize SoC specific constructs
> + CPU Info
> + SoC Personality
> + Board Personality
> + RCW prints
> + **/
> +VOID
> +SocInit (
> + VOID
> + )
> +{
> + SmmuInit ();
> +
> + //
> + // Early init serial Port to get board information.
> + //
> + SerialPortInitialize ();
> + DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
> + (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
> +
> + PrintCpuInfo ();
> +
> + //
> + // Print Reset control Word
> + //
> + PrintRCW ();
> + PrintSoc ();
> +
> + return;
> +}
> diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> new file mode 100644
> index 0000000..cb670a1
> --- /dev/null
> +++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> @@ -0,0 +1,45 @@
> +# @file
> +#
> +# Copyright 2017-2019 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = SocLib
> + FILE_GUID = e868c5ca-9729-43ae-bff4-438c67de8c68
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SocLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> + Silicon/NXP/LS1043A/LS1043A.dec
> +
> +[LibraryClasses]
> + ArmSmcLib
> + BaseLib
> + DebugLib
> + IoAccessLib
> + SerialPortLib
> +
> +[Sources.common]
> + Chassis.c
> + Chassis2/Soc.c
> + SerDes.c
> +
> +[BuildOptions]
> + GCC:*_*_*_CC_FLAGS = -DCHASSIS2
> +
> +[FixedPcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
> diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
> new file mode 100644
> index 0000000..99f6439
> --- /dev/null
> +++ b/Silicon/NXP/Library/SocLib/NxpChassis.h
> @@ -0,0 +1,136 @@
> +/** @file
> +* Header defining the Base addresses, sizes, flags etc for chassis 1
> +*
> +* Copyright 2017-2019 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#ifndef NXP_CHASSIS_H_
> +#define NXP_CHASSIS_H_
> +
> +#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
> +#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
> +#define TP_ITYP_TYPE_ARM 0x0
> +#define TP_ITYP_TYPE_PPC 0x1
> +#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
> +#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
> +#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
> +#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
> +#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
> +#define TP_INIT_PER_CLUSTER 4
> +
> +#define TY_ITYP_VERSION_A7 0x1
> +#define TY_ITYP_VERSION_A53 0x2
> +#define TY_ITYP_VERSION_A57 0x3
> +#define TY_ITYP_VERSION_A72 0x4
> +
> +#define CPU_TYPE_ENTRY(N, V, NC) { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
> +
> +#define SVR_WO_E 0xFFFFFE
> +#define SVR_LS1043A 0x879200
> +#define SVR_LS1046A 0x870700
> +#define SVR_LS2088A 0x870901
> +
> +#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
> +#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
> +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
> +#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
> +
> +#define MHZ 1000000
> +
> +typedef struct {
> + CHAR8 *Name;
> + UINT32 SocVer;
> + UINT32 NumCores;
> +} CPU_TYPE;
> +
> +typedef struct {
> + UINTN CpuClk; /* CPU clock in Hz! */
> + UINTN BusClk;
> + UINTN MemClk;
> + UINTN PciClk;
> + UINTN SdhcClk;
> +} SOC_CLOCK_INFO;
> +
> +/*
> + * Print Soc information
> + */
> +VOID
> +PrintSoc (
> + VOID
> + );
> +
> +/*
> + * Initialize Clock structure
> + */
> +VOID
> +ClockInit (
> + VOID
> + );
> +
> +/*
> + * Setup SMMU in bypass mode
> + * and also set its pagesize
> + */
> +VOID
> +SmmuInit (
> + VOID
> + );
> +
> +/*
> + * Print CPU information
> + */
> +VOID
> +PrintCpuInfo (
> + VOID
> + );
> +
> +/*
> + * Dump RCW (Reset Control Word) on console
> + */
> +VOID
> +PrintRCW (
> + VOID
> + );
> +
> +UINT32
> +InitiatorType (
> + IN UINT32 Cluster,
> + IN UINTN InitId
> + );
> +
> +/*
> + * Return the mask for number of cores on this SOC.
> + */
> +UINT32
> +CpuMask (
> + VOID
> + );
> +
> +/*
> + * Return the number of cores on this SOC.
> + */
> +UINTN
> +CpuNumCores (
> + VOID
> + );
> +
> +/*
> + * Return the type of initiator for core/hardware accelerator for given core index.
> + */
> +UINTN
> +QoriqCoreToType (
> + IN UINTN Core
> + );
> +
> +/*
> + * Return the cluster of initiator for core/hardware accelerator for given core index.
> + */
> +INT32
> +QoriqCoreToCluster (
> + IN UINTN Core
> + );
> +
> +#endif /* NXP_CHASSIS_H_ */
> diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocLib/SerDes.c
> new file mode 100644
> index 0000000..b9909d9
> --- /dev/null
> +++ b/Silicon/NXP/Library/SocLib/SerDes.c
> @@ -0,0 +1,268 @@
> +/** SerDes.c
> + Provides the basic interfaces for SerDes Module
> +
> + Copyright 2017-2019 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifdef CHASSIS2
> +#include <Chassis2/LsSerDes.h>
> +#include <Chassis2/NxpSoc.h>
> +#elif CHASSIS3
> +#include <Chassis3/LsSerDes.h>
> +#include <Chassis3/NxpSoc.h>
> +#endif
> +#include <Library/DebugLib.h>
> +#include <SocSerDes.h>
> +#include <Uefi.h>
> +
> +/**
> + Function to get serdes Lane protocol corresponding to
> + serdes protocol.
> +
> + @param SerDes Serdes number.
> + @param Cfg Serdes Protocol.
> + @param Lane Serdes Lane number.
> +
> + @return Serdes Lane protocol.
> +
> +**/
> +STATIC
> +SERDES_PROTOCOL
> +GetSerDesPrtcl (
> + IN INTN SerDes,
> + IN INTN Cfg,
> + IN INTN Lane
> + )
> +{
> + SERDES_CONFIG *Config;
> +
> + if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
> + return 0;
> + }
> +
> + Config = SerDesConfigTbl[SerDes];
> + while (Config->Protocol) {
> + if (Config->Protocol == Cfg) {
> + return Config->SrdsLane[Lane];
> + }
> + Config++;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to check if inputted protocol is a valid serdes protocol.
> +
> + @param SerDes Serdes number.
> + @param Prtcl Serdes Protocol to be verified.
> +
> + @return EFI_INVALID_PARAMETER Input parameter in invalid.
> + @return EFI_NOT_FOUND Serdes Protocol not a valid protocol.
> + @return EFI_SUCCESS Serdes Protocol is a valid protocol.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +CheckSerDesPrtclValid (
> + IN INTN SerDes,
> + IN UINT32 Prtcl
> + )
> +{
> + SERDES_CONFIG *Config;
> + INTN Cnt;
> +
> + if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + Config = SerDesConfigTbl[SerDes];
> + while (Config->Protocol) {
> + if (Config->Protocol == Prtcl) {
> + DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl));
> + break;
> + }
> + Config++;
> + }
> +
> + if (!Config->Protocol) {
> + return EFI_NOT_FOUND;
> + }
> +
> + for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
> + if (Config->SrdsLane[Cnt] != None) {
> + return EFI_SUCCESS;
> + }
> + }
> +
> + return EFI_NOT_FOUND;
> +}
> +
> +/**
> + Function to fill serdes map information.
> +
> + @param Srds Serdes number.
> + @param SerdesProtocolMask Serdes Protocol Mask.
> + @param SerdesProtocolShift Serdes Protocol shift value.
> + @param SerDesPrtclMap Pointer to Serdes Protocol map.
> +
> +**/
> +STATIC
> +VOID
> +LSSerDesMap (
> + IN UINT32 Srds,
> + IN UINT32 SerdesProtocolMask,
> + IN UINT32 SerdesProtocolShift,
> + OUT UINT64 *SerDesPrtclMap
> + )
> +{
> + CCSR_GUR *Gur;
> + UINT32 SrdsProt;
> + INTN Lane;
> + UINT32 Flag;
> +
> + Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + *SerDesPrtclMap = 0x0;
> + Flag = 0;
> +
> + SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
> + SrdsProt >>= SerdesProtocolShift;
> +
> + DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
> + Srds + 1, SrdsProt, SrdsProt));
> +
> + if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
> + DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
> + Srds + 1, SrdsProt));
> + Flag++;
> + }
> +
> + for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
> + SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
> + if (LanePrtcl >= SerdesPrtclCount) {
> + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
> + Flag++;
> + } else {
> + *SerDesPrtclMap |= (1u << LanePrtcl);
> + }
> + }
> +
> + if (Flag) {
> + DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
> + } else {
> + DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
> + }
> +}
> +
> +/**
> + Get lane protocol on provided serdes lane and execute callback function.
> +
> + @param Srds Serdes number.
> + @param SerdesProtocolMask Mask to get Serdes Protocol for Srds
> + @param SerdesProtocolShift Shift value to get Serdes Protocol for Srds.
> + @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
> + @param Arg Pointer to Arguments to be passed to callback function.
> +
> +**/
> +STATIC
> +VOID
> +SerDesInstanceProbeLanes (
> + IN UINT32 Srds,
> + IN UINT32 SerdesProtocolMask,
> + IN UINT32 SerdesProtocolShift,
> + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> + IN VOID *Arg
> + )
> +{
> +
> + CCSR_GUR *Gur;
> + UINT32 SrdsProt;
> + INTN Lane;
> +
> + Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
> +
> + SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
> + SrdsProt >>= SerdesProtocolShift;
> +
> + /*
> + * Invoke callback for all lanes in the SerDes instance:
> + */
> + for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
> + SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
> + if ((LanePrtcl >= SerdesPrtclCount) || (LanePrtcl < None)) {
> + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
> + } else if (LanePrtcl != None) {
> + SerDesLaneProbeCallback (LanePrtcl, Arg);
> + }
> + }
> +}
> +
> +/**
> + Probe all serdes lanes for lane protocol and execute provided callback function.
> +
> + @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
> + @param Arg Pointer to Arguments to be passed to callback function.
> +
> +**/
> +VOID
> +SerDesProbeLanes (
> + IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
> + IN VOID *Arg
> + )
> +{
> + SerDesInstanceProbeLanes (Srds1,
> + RCWSR_SRDS1_PRTCL_MASK,
> + RCWSR_SRDS1_PRTCL_SHIFT,
> + SerDesLaneProbeCallback,
> + Arg);
> +
> + if (PcdGetBool (PcdSerdes2Enabled)) {
> + SerDesInstanceProbeLanes (Srds2,
> + RCWSR_SRDS2_PRTCL_MASK,
> + RCWSR_SRDS2_PRTCL_SHIFT,
> + SerDesLaneProbeCallback,
> + Arg);
> + }
> +}
> +
> +/**
> + Function to return Serdes protocol map for all serdes available on board.
> +
> + @param SerDesPrtclMap Pointer to Serdes protocl map.
> +
> +**/
> +VOID
> +GetSerdesProtocolMaps (
> + OUT UINT64 *SerDesPrtclMap
> + )
> +{
> + LSSerDesMap (Srds1,
> + RCWSR_SRDS1_PRTCL_MASK,
> + RCWSR_SRDS1_PRTCL_SHIFT,
> + SerDesPrtclMap);
> +
> + if (PcdGetBool (PcdSerdes2Enabled)) {
> + LSSerDesMap (Srds2,
> + RCWSR_SRDS2_PRTCL_MASK,
> + RCWSR_SRDS2_PRTCL_SHIFT,
> + SerDesPrtclMap);
> + }
> +
> +}
> +
> +BOOLEAN
> +IsSerDesLaneProtocolConfigured (
> + IN UINT64 SerDesPrtclMap,
> + IN SERDES_PROTOCOL Device
> + )
> +{
> + if ((Device >= SerdesPrtclCount) || (Device < None)) {
> + ASSERT ((Device > None) && (Device < SerdesPrtclCount));
> + DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device));
> + }
> +
> + return (SerDesPrtclMap & (1u << Device)) != 0 ;
> +}
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 06/12] Silicon/NXP: Add support for I2c driver
[not found] ` <1570639758-30355-7-git-send-email-meenakshi.aggarwal@nxp.com>
@ 2019-10-10 14:51 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-10-10 14:51 UTC (permalink / raw)
To: Meenakshi Aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, v.sethi
On Wed, Oct 09, 2019 at 10:19:12PM +0530, Meenakshi Aggarwal wrote:
> I2C driver produces gEfiI2cMasterProtocolGuid which can be
> used by other modules.
A few minor comments on this one, inline below.
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Drivers/I2cDxe/ComponentName.c | 179 ++++++++
> Silicon/NXP/Drivers/I2cDxe/DriverBinding.c | 235 ++++++++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 690 +++++++++++++++++++++++++++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 100 +++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 58 +++
> 5 files changed, 1262 insertions(+)
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/ComponentName.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
>
> diff --git a/Silicon/NXP/Drivers/I2cDxe/ComponentName.c b/Silicon/NXP/Drivers/I2cDxe/ComponentName.c
> new file mode 100644
> index 0000000..a71d75c
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/I2cDxe/ComponentName.c
> @@ -0,0 +1,179 @@
> +/** @file
> +
> + Copyright 2018-2019 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include "I2cDxe.h"
> +
> +STATIC EFI_UNICODE_STRING_TABLE mNxpI2cDriverNameTable[] = {
> + {
> + "en",
> + (CHAR16 *)L"Nxp I2C Driver"
This should not need an explicit cast. The type is already (CHAR16 *).
> + },
> + { }
> +};
> +
> +STATIC EFI_UNICODE_STRING_TABLE mNxpI2cControllerNameTable[] = {
> + {
> + "en",
> + (CHAR16 *)L"Nxp I2C Controller"
This should not need an explicit cast. The type is already (CHAR16 *).
> + },
> + { }
> +};
> +
> +/**
> + Retrieves a Unicode string that is the user readable name of the driver.
> +
> + This function retrieves the user readable name of a driver in the form of a
> + Unicode string. If the driver specified by This has a user readable name in
> + the language specified by Language, then a pointer to the driver name is
> + returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
> + by This does not support the language specified by Language,
> + then EFI_UNSUPPORTED is returned.
> +
> + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
> + EFI_COMPONENT_NAME_PROTOCOL instance.
> +
> + @param Language[in] A pointer to a Null-terminated ASCII string
> + array indicating the language. This is the
> + language of the driver name that the caller is
> + requesting, and it must match one of the
> + languages specified in SupportedLanguages. The
> + number of languages supported by a driver is up
> + to the driver writer. Language is specified
> + in RFC 4646 or ISO 639-2 language code format.
> +
> + @param DriverName[out] A pointer to the Unicode string to return.
> + This Unicode string is the name of the
> + driver specified by This in the language
> + specified by Language.
> +
> + @retval EFI_SUCCESS The Unicode string for the Driver specified by
> + This and the language specified by Language was
> + returned in DriverName.
> +
> + @retval EFI_INVALID_PARAMETER Language is NULL.
> +
> + @retval EFI_INVALID_PARAMETER DriverName is NULL.
> +
> + @retval EFI_UNSUPPORTED The driver specified by This does not support
> + the language specified by Language.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +NxpI2cGetDriverName (
> + IN EFI_COMPONENT_NAME2_PROTOCOL *This,
> + IN CHAR8 *Language,
> + OUT CHAR16 **DriverName
> + )
> +{
> + return LookupUnicodeString2 (Language,
> + This->SupportedLanguages,
> + mNxpI2cDriverNameTable,
> + DriverName,
> + FALSE);
> +}
> +
> +/**
> + Retrieves a Unicode string that is the user readable name of the controller
> + that is being managed by a driver.
> +
> + This function retrieves the user readable name of the controller specified by
> + ControllerHandle and ChildHandle in the form of a Unicode string. If the
> + driver specified by This has a user readable name in the language specified by
> + Language, then a pointer to the controller name is returned in ControllerName,
> + and EFI_SUCCESS is returned. If the driver specified by This is not currently
> + managing the controller specified by ControllerHandle and ChildHandle,
> + then EFI_UNSUPPORTED is returned. If the driver specified by This does not
> + support the language specified by Language, then EFI_UNSUPPORTED is returned.
> +
> + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
> + EFI_COMPONENT_NAME_PROTOCOL instance.
> +
> + @param ControllerHandle[in] The handle of a controller that the driver
> + specified by This is managing. This handle
> + specifies the controller whose name is to be
> + returned.
> +
> + @param ChildHandle[in] The handle of the child controller to retrieve
> + the name of. This is an optional parameter that
> + may be NULL. It will be NULL for device
> + drivers. It will also be NULL for a bus drivers
> + that wish to retrieve the name of the bus
> + controller. It will not be NULL for a bus
> + driver that wishes to retrieve the name of a
> + child controller.
> +
> + @param Language[in] A pointer to a Null-terminated ASCII string
> + array indicating the language. This is the
> + language of the driver name that the caller is
> + requesting, and it must match one of the
> + languages specified in SupportedLanguages. The
> + number of languages supported by a driver is up
> + to the driver writer. Language is specified in
> + RFC 4646 or ISO 639-2 language code format.
> +
> + @param ControllerName[out] A pointer to the Unicode string to return.
> + This Unicode string is the name of the
> + controller specified by ControllerHandle and
> + ChildHandle in the language specified by
> + Language from the point of view of the driver
> + specified by This.
> +
> + @retval EFI_SUCCESS The Unicode string for the user readable name in
> + the language specified by Language for the
> + driver specified by This was returned in
> + DriverName.
> +
> + @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
> +
> + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
> + EFI_HANDLE.
> +
> + @retval EFI_INVALID_PARAMETER Language is NULL.
> +
> + @retval EFI_INVALID_PARAMETER ControllerName is NULL.
> +
> + @retval EFI_UNSUPPORTED The driver specified by This is not currently
> + managing the controller specified by
> + ControllerHandle and ChildHandle.
> +
> + @retval EFI_UNSUPPORTED The driver specified by This does not support
> + the language specified by Language.
> +
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +NxpI2cGetControllerName (
> + IN EFI_COMPONENT_NAME2_PROTOCOL *This,
> + IN EFI_HANDLE ControllerHandle,
> + IN EFI_HANDLE ChildHandle OPTIONAL,
> + IN CHAR8 *Language,
> + OUT CHAR16 **ControllerName
> + )
> +{
> + if (ChildHandle != NULL) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + return LookupUnicodeString2 (Language,
> + This->SupportedLanguages,
> + mNxpI2cControllerNameTable,
> + ControllerName,
> + FALSE);
> +}
> +
> +//
> +// EFI Component Name 2 Protocol
> +//
> +EFI_COMPONENT_NAME2_PROTOCOL gNxpI2cDriverComponentName2 = {
> + NxpI2cGetDriverName,
> + NxpI2cGetControllerName,
> + "en"
> +};
> diff --git a/Silicon/NXP/Drivers/I2cDxe/DriverBinding.c b/Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
> new file mode 100644
> index 0000000..5932044
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
> @@ -0,0 +1,235 @@
> +/** @file
> +
> + Copyright 2018-2019 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +
> +#include <Protocol/DriverBinding.h>
> +
> +#include "I2cDxe.h"
> +
> +/**
> + Tests to see if this driver supports a given controller.
> +
> + @param This[in] A pointer to the EFI_DRIVER_BINDING_PROTOCOL
> + instance.
> + @param ControllerHandle[in] The handle of the controller to test.
> + @param RemainingDevicePath[in] The remaining device path.
> + (Ignored - this is not a bus driver.)
> +
> + @retval EFI_SUCCESS The driver supports this controller.
> + @retval EFI_ALREADY_STARTED The device specified by ControllerHandle is
> + already being managed by the driver specified
> + by This.
> + @retval EFI_UNSUPPORTED The device specified by ControllerHandle is
> + not supported by the driver specified by This.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +NxpI2cDriverBindingSupported (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE ControllerHandle,
> + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
> + )
> +{
> + NON_DISCOVERABLE_DEVICE *Dev;
> + EFI_STATUS Status;
> +
> + //
> + // Connect to the non-discoverable device
> + //
> + Status = gBS->OpenProtocol (ControllerHandle,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid,
> + (VOID **) &Dev,
> + This->DriverBindingHandle,
> + ControllerHandle,
> + EFI_OPEN_PROTOCOL_BY_DRIVER);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if (CompareGuid (Dev->Type, &gNxpNonDiscoverableI2cMasterGuid)) {
> + Status = EFI_SUCCESS;
> + } else {
> + Status = EFI_UNSUPPORTED;
> + }
> +
> + //
> + // Clean up.
> + //
> + gBS->CloseProtocol (ControllerHandle,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid,
> + This->DriverBindingHandle,
> + ControllerHandle);
> +
> + return Status;
> +}
> +
> +
> +/**
> + Starts a device controller or a bus controller.
> +
> + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL
> + instance.
> + @param[in] ControllerHandle The handle of the device to start. This
> + handle must support a protocol interface that
> + supplies an I/O abstraction to the driver.
> + @param[in] RemainingDevicePath The remaining portion of the device path.
> + (Ignored - this is not a bus driver.)
> +
> + @retval EFI_SUCCESS The device was started.
> + @retval EFI_DEVICE_ERROR The device could not be started due to a
> + device error.
> + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
> + lack of resources.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +NxpI2cDriverBindingStart (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE ControllerHandle,
> + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL
> + )
> +{
> + return NxpI2cInit (This->DriverBindingHandle, ControllerHandle);
> +}
> +
> +
> +/**
> + Stops a device controller or a bus controller.
> +
> + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL
> + instance.
> + @param[in] ControllerHandle A handle to the device being stopped. The handle
> + must support a bus specific I/O protocol for the
> + driver to use to stop the device.
> + @param[in] NumberOfChildren The number of child device handles in
> + ChildHandleBuffer.
> + @param[in] ChildHandleBuffer An array of child handles to be freed. May be
> + NULL if NumberOfChildren is 0.
> +
> + @retval EFI_SUCCESS The device was stopped.
> + @retval EFI_DEVICE_ERROR The device could not be stopped due to a device
> + error.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +NxpI2cDriverBindingStop (
> + IN EFI_DRIVER_BINDING_PROTOCOL *This,
> + IN EFI_HANDLE ControllerHandle,
> + IN UINTN NumberOfChildren,
> + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL
> + )
> +{
> + return NxpI2cRelease (This->DriverBindingHandle, ControllerHandle);
> +}
> +
> +
> +STATIC EFI_DRIVER_BINDING_PROTOCOL gNxpI2cDriverBinding = {
> + NxpI2cDriverBindingSupported,
> + NxpI2cDriverBindingStart,
> + NxpI2cDriverBindingStop,
> + 0xa,
> + NULL,
> + NULL
> +};
> +
> +
> +/**
> + The entry point of I2c UEFI Driver.
> +
> + @param ImageHandle The image handle of the UEFI Driver.
> + @param SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The Driver or UEFI Driver exited normally.
> + @retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than
> + SystemTable->Hdr.Revision.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +I2cDxeEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> +
> + //
> + // Add the driver to the list of drivers
> + //
> + Status = EfiLibInstallDriverBindingComponentName2 (
> + ImageHandle, SystemTable, &gNxpI2cDriverBinding, ImageHandle,
> + NULL, &gNxpI2cDriverComponentName2);
> + ASSERT_EFI_ERROR (Status);
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> +/**
> + Unload function for the I2c UEFI Driver.
> +
> + @param ImageHandle[in] The allocated handle for the EFI image
> +
> + @retval EFI_SUCCESS The driver was unloaded successfully
> + @retval EFI_INVALID_PARAMETER ImageHandle is not a valid image handle.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +I2cDxeUnload (
> + IN EFI_HANDLE ImageHandle
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE *HandleBuffer;
> + UINTN HandleCount;
> + UINTN Index;
> +
> + //
> + // Retrieve all USB I/O handles in the handle database
> + //
> + Status = gBS->LocateHandleBuffer (ByProtocol,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid,
> + NULL,
> + &HandleCount,
> + &HandleBuffer);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + //
> + // Disconnect the driver from the handles in the handle database
> + //
> + for (Index = 0; Index < HandleCount; Index++) {
> + Status = gBS->DisconnectController (HandleBuffer[Index],
> + gImageHandle,
> + NULL);
> + }
> +
> + //
> + // Free the handle array
> + //
> + gBS->FreePool (HandleBuffer);
> +
> + //
> + // Uninstall protocols installed by the driver in its entrypoint
> + //
> + Status = gBS->UninstallMultipleProtocolInterfaces (ImageHandle,
> + &gEfiDriverBindingProtocolGuid,
> + &gNxpI2cDriverBinding,
> + NULL
> + );
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> new file mode 100644
> index 0000000..7c04b76
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> @@ -0,0 +1,690 @@
> +/** I2cDxe.c
> + I2c driver APIs for read, write, initialize, set speed and reset
> +
> + Copyright 2017-2019 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +
> +#include "I2cDxe.h"
> +
> +STATIC CONST CLK_DIV mClkDiv[] = {
> + { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
> + { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
> + { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
> + { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
> + { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
> + { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
> + { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
> + { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
> + { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
> + { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
> + { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
> + { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
> + { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
> + { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
> + { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }
> +};
> +
> +/**
> + Calculate and return proper clock divider
> +
> + @param Rate desired clock rate
> +
> + @retval ClkDiv Index value used to get Bus Clock Rate
> +
> +**/
> +STATIC
> +UINT8
> +GetClkDivIndex (
> + IN UINT32 Rate
> + )
> +{
> + UINTN ClkRate;
> + UINT32 Div;
> + UINT8 Index;
> +
> + Index = 0;
> + ClkRate = GetBusFrequency ();
> +
> + Div = (ClkRate + Rate - 1) / Rate;
> +
> + if (Div < mClkDiv[0].SCLDivider) {
> + return 0;
> + }
> +
> + do {
> + if (mClkDiv[Index].SCLDivider >= Div ) {
> + return Index;
> + }
> + } while (Index < ARRAY_SIZE (mClkDiv));
> +
> + return ARRAY_SIZE (mClkDiv) - 1;
> +}
> +
> +/**
> + Function used to check if i2c is in mentioned state or not
> +
> + @param I2cRegs Pointer to I2C registers
> + @param State i2c state need to be checked
> +
> + @retval EFI_NOT_READY Arbitration was lost
> + @retval EFI_TIMEOUT Timeout occured
> + @retval CurrState Value of state register
> +
> +**/
> +STATIC
> +EFI_STATUS
> +WaitForI2cState (
> + IN I2C_REGS *I2cRegs,
> + IN UINT32 State
> + )
> +{
> + UINT8 CurrState;
> + UINT64 Count;
> +
> + for (Count = 0; Count < I2C_STATE_RETRIES; Count++) {
> + MemoryFence ();
> + CurrState = MmioRead8 ((UINTN)&I2cRegs->I2cSr);
> + if (CurrState & I2C_SR_IAL) {
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, CurrState | I2C_SR_IAL);
> + return EFI_NOT_READY;
Indentation funky - both lines should be 2 spaces deeper than if.
> + }
> +
> + if ((CurrState & (State >> 8)) == (UINT8)State) {
> + return CurrState;
> + }
> + }
> +
> + return EFI_TIMEOUT;
> +}
> +
> +/**
> + Function to transfer byte on i2c
> +
> + @param I2cRegs Pointer to i2c registers
> + @param Byte Byte to be transferred on i2c bus
> +
> + @retval EFI_NOT_READY Arbitration was lost
> + @retval EFI_TIMEOUT Timeout occured
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Data transfer was succesful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +TransferByte (
> + IN I2C_REGS *I2cRegs,
> + IN UINT8 Byte
> + )
> +{
> + EFI_STATUS RetVal;
> +
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> + MmioWrite8 ((UINTN)&I2cRegs->I2cDr, Byte);
> +
> + RetVal = WaitForI2cState (I2cRegs, IIF);
> + if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
> + return RetVal;
> + }
> +
> + if (RetVal & I2C_SR_RX_NO_AK) {
> + return EFI_NOT_FOUND;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to stop transaction on i2c bus
> +
> + @param I2cRegs Pointer to i2c registers
> +
> + @retval EFI_NOT_READY Arbitration was lost
> + @retval EFI_TIMEOUT Timeout occured
> + @retval EFI_SUCCESS Stop operation was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +I2cStop (
> + IN I2C_REGS *I2cRegs
> + )
> +{
> + EFI_STATUS RetVal;
> + UINT32 Temp;
> +
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> +
> + Temp &= ~(I2C_CR_MSTA | I2C_CR_MTX);
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> +
> + RetVal = WaitForI2cState (I2cRegs, BUS_IDLE);
> +
> + if (RetVal < 0) {
> + return RetVal;
> + } else {
> + return EFI_SUCCESS;
> + }
> +}
> +
> +/**
> + Function to send start signal, Chip Address and
> + memory offset
> +
> + @param I2cRegs Pointer to i2c base registers
> + @param Chip Chip Address
> + @param Offset Slave memory's offset
> + @param AddressLength length of chip address
> +
> + @retval EFI_NOT_READY Arbitration lost
> + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Read was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +InitTransfer (
> + IN I2C_REGS *I2cRegs,
> + IN UINT8 Chip,
> + IN UINT32 Offset,
> + IN INT32 AddressLength
> + )
> +{
> + UINT32 Temp;
> + EFI_STATUS RetVal;
> +
> + // Enable I2C controller
> + if (MmioRead8 ((UINTN)&I2cRegs->I2cCr) & I2C_CR_IDIS) {
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IEN);
> + }
> +
> + if (MmioRead8 ((UINTN)&I2cRegs->I2cAdr) == (Chip << 1)) {
> + MmioWrite8 ((UINTN)&I2cRegs->I2cAdr, (Chip << 1) ^ 2);
> + }
> +
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> + RetVal = WaitForI2cState (I2cRegs, BUS_IDLE);
> + if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
> + return RetVal;
> + }
> +
> + // Start I2C transaction
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> + // set to master mode
> + Temp |= I2C_CR_MSTA;
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> +
> + RetVal = WaitForI2cState (I2cRegs, BUS_BUSY);
> + if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
> + return RetVal;
> + }
> +
> + Temp |= I2C_CR_MTX | I2C_CR_TX_NO_AK;
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> +
> + // write slave Address
> + RetVal = TransferByte (I2cRegs, Chip << 1);
> + if (RetVal != EFI_SUCCESS) {
> + return RetVal;
> + }
> +
> + if (AddressLength >= 0) {
> + while (AddressLength--) {
> + RetVal = TransferByte (I2cRegs, (Offset >> (AddressLength * 8)) & 0xff);
> + if (RetVal != EFI_SUCCESS)
> + return RetVal;
> + }
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to check if i2c bus is idle
> +
> + @param Base Pointer to base address of I2c controller
> +
> + @retval EFI_SUCCESS
> +
> +**/
> +STATIC
> +INT32
> +I2cBusIdle (
> + IN VOID *Base
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to initiate data transfer on i2c bus
> +
> + @param I2cRegs Pointer to i2c base registers
> + @param Chip Chip Address
> + @param Offset Slave memory's offset
> + @param AddressLength length of chip address
> +
> + @retval EFI_NOT_READY Arbitration lost
> + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Read was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +InitDataTransfer (
> + IN I2C_REGS *I2cRegs,
> + IN UINT8 Chip,
> + IN UINT32 Offset,
> + IN INT32 AddressLength
> + )
> +{
> + EFI_STATUS RetVal;
> + INT32 Retry;
> +
> + for (Retry = 0; Retry < RETRY_COUNT; Retry++) {
> + RetVal = InitTransfer (I2cRegs, Chip, Offset, AddressLength);
> + if (RetVal == EFI_SUCCESS) {
> + return EFI_SUCCESS;
> + }
> +
> + I2cStop (I2cRegs);
> +
> + if (EFI_NOT_FOUND == RetVal) {
> + return RetVal;
> + }
> +
> + // Disable controller
> + if (RetVal != EFI_NOT_READY) {
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
> + }
> +
> + if (I2cBusIdle (I2cRegs) < 0) {
> + break;
> + }
> + }
> + return RetVal;
> +}
> +
> +/**
> + Function to read data using i2c bus
> +
> + @param BaseAddr I2c Controller Base Address
> + @param Chip Address of slave device from where data to be read
> + @param Offset Offset of slave memory
> + @param AddressLength Address length of slave
> + @param Buffer A pointer to the destination buffer for the data
> + @param Len Length of data to be read
> +
> + @retval EFI_NOT_READY Arbitration lost
> + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Read was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +I2cDataRead (
> + IN UINTN BaseAddr,
> + IN UINT8 Chip,
> + IN UINT32 Offset,
> + IN UINT32 AddressLength,
> + IN UINT8 *Buffer,
> + IN UINT32 Len
> + )
> +{
> + EFI_STATUS RetVal;
> + UINT32 Temp;
> + INT32 I;
> + I2C_REGS *I2cRegs;
> +
> + I2cRegs = (I2C_REGS *)(BaseAddr);
> +
> + RetVal = InitDataTransfer (I2cRegs, Chip, Offset, AddressLength);
> + if (RetVal != EFI_SUCCESS) {
> + return RetVal;
> + }
> +
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> + Temp |= I2C_CR_RSTA;
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> +
> + RetVal = TransferByte (I2cRegs, (Chip << 1) | 1);
> + if (RetVal != EFI_SUCCESS) {
> + I2cStop (I2cRegs);
> + return RetVal;
> + }
> +
> + // setup bus to read data
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> + Temp &= ~(I2C_CR_MTX | I2C_CR_TX_NO_AK);
> + if (Len == 1) {
> + Temp |= I2C_CR_TX_NO_AK;
> + }
> +
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> +
> + // Dummy Read to initiate recieve operation
> + MmioRead8 ((UINTN)&I2cRegs->I2cDr);
> +
> + for (I = 0; I < Len; I++) {
> + RetVal = WaitForI2cState (I2cRegs, IIF);
> + if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
> + I2cStop (I2cRegs);
> + return RetVal;
> + }
> + //
> + // It must generate STOP before read I2DR to prevent
> + // controller from generating another clock cycle
> + //
> + if (I == (Len - 1)) {
> + I2cStop (I2cRegs);
> + } else if (I == (Len - 2)) {
> + Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
> + Temp |= I2C_CR_TX_NO_AK;
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
> + }
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
> + Buffer[I] = MmioRead8 ((UINTN)&I2cRegs->I2cDr);
> + }
> +
> + I2cStop (I2cRegs);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to write data using i2c bus
> +
> + @param BaseAddr I2c Controller Base Address
> + @param Chip Address of slave device where data to be written
> + @param Offset Offset of slave memory
> + @param AddressLength Address length of slave
> + @param Buffer A pointer to the source buffer for the data
> + @param Len Length of data to be write
> +
> + @retval EFI_NOT_READY Arbitration lost
> + @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
> + @retval EFI_NOT_FOUND ACK was not recieved
> + @retval EFI_SUCCESS Read was successful
> +
> +**/
> +STATIC
> +EFI_STATUS
> +I2cDataWrite (
> + IN UINTN BaseAddr,
> + IN UINT8 Chip,
> + IN UINT32 Offset,
> + IN INT32 AddressLength,
> + OUT UINT8 *Buffer,
> + IN INT32 Len
> + )
> +{
> + EFI_STATUS RetVal;
> + I2C_REGS *I2cRegs;
> + INT32 I;
> +
> + I2cRegs = (I2C_REGS *)BaseAddr;
> +
> + RetVal = InitDataTransfer (I2cRegs, Chip, Offset, AddressLength);
> + if (RetVal != EFI_SUCCESS) {
> + return RetVal;
> + }
> +
> + // Write operation
> + for (I = 0; I < Len; I++) {
> + RetVal = TransferByte (I2cRegs, Buffer[I]);
> + if (RetVal != EFI_SUCCESS) {
> + break;
> + }
> + }
> +
> + I2cStop (I2cRegs);
> + return RetVal;
> +}
> +
> +/**
> + Function to set i2c bus frequency
> +
> + @param This Pointer to I2c master protocol
> + @param BusClockHertz value to be set
> +
> + @retval EFI_SUCCESS Operation successfull
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +SetBusFrequency (
> + IN CONST EFI_I2C_MASTER_PROTOCOL *This,
> + IN OUT UINTN *BusClockHertz
> + )
> +{
> + I2C_REGS *I2cRegs;
> + UINT8 ClkId;
> + UINT8 SpeedId;
> + NXP_I2C_MASTER *I2c;
> +
> + I2c = NXP_I2C_FROM_THIS (This);
> +
> + I2cRegs = (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin);
> +
> + ClkId = GetClkDivIndex (*BusClockHertz);
> + SpeedId = mClkDiv[ClkId].BusClockRate;
> +
> + // Store divider value
> + MmioWrite8 ((UINTN)&I2cRegs->I2cFdr, SpeedId);
> +
> + MemoryFence ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Function to reset I2c Controller
> +
> + @param This Pointer to I2c master protocol
> +
> + @return EFI_SUCCESS Operation successfull
> +**/
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +Reset (
> + IN CONST EFI_I2C_MASTER_PROTOCOL *This
> + )
> +{
> + I2C_REGS *I2cRegs;
> + NXP_I2C_MASTER *I2c;
> +
> + I2c = NXP_I2C_FROM_THIS (This);
> +
> + I2cRegs = (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin);
> +
> + // Reset module
> + MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
> + MmioWrite8 ((UINTN)&I2cRegs->I2cSr, 0);
> +
> + MemoryFence ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +EFIAPI
> +StartRequest (
> + IN CONST EFI_I2C_MASTER_PROTOCOL *This,
> + IN UINTN SlaveAddress,
> + IN EFI_I2C_REQUEST_PACKET *RequestPacket,
> + IN EFI_EVENT Event OPTIONAL,
> + OUT EFI_STATUS *I2cStatus OPTIONAL
> + )
> +{
> + NXP_I2C_MASTER *I2c;
> + UINT32 Count;
> + INT32 RetVal;
> + UINT32 Length;
> + UINT8 *Buffer;
> + UINT32 Flag;
> + UINT32 RegAddress;
> + UINT32 OffsetLength;
> +
> + RegAddress = 0;
> +
> + I2c = NXP_I2C_FROM_THIS (This);
> +
> + if (RequestPacket->OperationCount <= 0) {
> + DEBUG ((DEBUG_ERROR,"%a: Operation count is not valid %d\n",
> + __FUNCTION__, RequestPacket->OperationCount));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + OffsetLength = RequestPacket->Operation[0].LengthInBytes;
> + RegAddress = *RequestPacket->Operation[0].Buffer;
> +
> + for (Count = 1; Count < RequestPacket->OperationCount; Count++) {
> + Flag = RequestPacket->Operation[Count].Flags;
> + Length = RequestPacket->Operation[Count].LengthInBytes;
> + Buffer = RequestPacket->Operation[Count].Buffer;
> +
> + if (Length <= 0) {
> + DEBUG ((DEBUG_ERROR,"%a: Invalid length of buffer %d\n",
> + __FUNCTION__, Length));
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + if (Flag == I2C_FLAG_READ) {
> + RetVal = I2cDataRead (I2c->Dev->Resources[0].AddrRangeMin, SlaveAddress,
> + RegAddress, OffsetLength, Buffer, Length);
Funky indentation.
> + if (RetVal != EFI_SUCCESS) {
> + DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n",
> + __FUNCTION__, RetVal));
> + return RetVal;
> + }
> + } else if (Flag == I2C_FLAG_WRITE) {
> + RetVal = I2cDataWrite (I2c->Dev->Resources[0].AddrRangeMin, SlaveAddress,
> + RegAddress, OffsetLength, Buffer, Length);
Funky indentation.
> + if (RetVal != EFI_SUCCESS) {
> + DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n",
> + __FUNCTION__, RetVal));
> + return RetVal;
> + }
> + } else {
> + DEBUG ((DEBUG_ERROR,"%a: Invalid Flag %d\n",
> + __FUNCTION__, Flag));
> + return EFI_INVALID_PARAMETER;
> + }
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC CONST EFI_I2C_CONTROLLER_CAPABILITIES I2cControllerCapabilities = {
STATIC global variables should have 'm' prefix, and be defined before
all functions.
/
Leif
> + 0,
> + 0,
> + 0,
> + 0
> +};
> +
> +EFI_STATUS
> +NxpI2cInit (
> + IN EFI_HANDLE DriverBindingHandle,
> + IN EFI_HANDLE ControllerHandle
> + )
> +{
> + EFI_STATUS RetVal;
> + NON_DISCOVERABLE_DEVICE *Dev;
> + NXP_I2C_MASTER *I2c;
> +
> + RetVal = gBS->OpenProtocol (ControllerHandle,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid,
> + (VOID **)&Dev, DriverBindingHandle,
> + ControllerHandle, EFI_OPEN_PROTOCOL_BY_DRIVER);
> + if (EFI_ERROR (RetVal)) {
> + return RetVal;
> + }
> +
> + I2c = AllocateZeroPool (sizeof (NXP_I2C_MASTER));
> +
> + I2c->Signature = NXP_I2C_SIGNATURE;
> + I2c->I2cMaster.SetBusFrequency = SetBusFrequency;
> + I2c->I2cMaster.Reset = Reset;
> + I2c->I2cMaster.StartRequest = StartRequest;
> + I2c->I2cMaster.I2cControllerCapabilities = &I2cControllerCapabilities;
> + I2c->Dev = Dev;
> +
> + CopyGuid (&I2c->DevicePath.Vendor.Guid, &gEfiCallerIdGuid);
> + I2c->DevicePath.MmioBase = I2c->Dev->Resources[0].AddrRangeMin;
> + SetDevicePathNodeLength (&I2c->DevicePath.Vendor,
> + sizeof (I2c->DevicePath) - sizeof (I2c->DevicePath.End));
> + SetDevicePathEndNode (&I2c->DevicePath.End);
> +
> + RetVal = gBS->InstallMultipleProtocolInterfaces (&ControllerHandle,
> + &gEfiI2cMasterProtocolGuid, (VOID**)&I2c->I2cMaster,
> + &gEfiDevicePathProtocolGuid, &I2c->DevicePath,
> + NULL);
> +
> + if (EFI_ERROR (RetVal)) {
> + FreePool (I2c);
> + gBS->CloseProtocol (ControllerHandle,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid,
> + DriverBindingHandle,
> + ControllerHandle);
> + }
> +
> + return RetVal;
> +}
> +
> +EFI_STATUS
> +NxpI2cRelease (
> + IN EFI_HANDLE DriverBindingHandle,
> + IN EFI_HANDLE ControllerHandle
> + )
> +{
> + EFI_I2C_MASTER_PROTOCOL *I2cMaster;
> + EFI_STATUS RetVal;
> + NXP_I2C_MASTER *I2c;
> +
> + RetVal = gBS->HandleProtocol (ControllerHandle,
> + &gEfiI2cMasterProtocolGuid,
> + (VOID **)&I2cMaster);
> + ASSERT_EFI_ERROR (RetVal);
> + if (EFI_ERROR (RetVal)) {
> + return RetVal;
> + }
> +
> + I2c = NXP_I2C_FROM_THIS (I2cMaster);
> +
> + RetVal = gBS->UninstallMultipleProtocolInterfaces (ControllerHandle,
> + &gEfiI2cMasterProtocolGuid, I2cMaster,
> + &gEfiDevicePathProtocolGuid, &I2c->DevicePath,
> + NULL);
> + if (EFI_ERROR (RetVal)) {
> + return RetVal;
> + }
> +
> + RetVal = gBS->CloseProtocol (ControllerHandle,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid,
> + DriverBindingHandle,
> + ControllerHandle);
> + ASSERT_EFI_ERROR (RetVal);
> + if (EFI_ERROR (RetVal)) {
> + return RetVal;
> + }
> +
> + gBS->FreePool (I2c);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> new file mode 100644
> index 0000000..02a29a5
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> @@ -0,0 +1,100 @@
> +/** I2cDxe.h
> + Header defining the constant, base address amd function for I2C controller
> +
> + Copyright 2017-2019 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef I2C_DXE_H_
> +#define I2C_DXE_H_
> +
> +#include <Library/UefiLib.h>
> +#include <Uefi.h>
> +
> +#include <Protocol/I2cMaster.h>
> +#include <Protocol/NonDiscoverableDevice.h>
> +
> +#define I2C_CR_IIEN (1 << 6)
> +#define I2C_CR_MSTA (1 << 5)
> +#define I2C_CR_MTX (1 << 4)
> +#define I2C_CR_TX_NO_AK (1 << 3)
> +#define I2C_CR_RSTA (1 << 2)
> +
> +#define I2C_SR_ICF (1 << 7)
> +#define I2C_SR_IBB (1 << 5)
> +#define I2C_SR_IAL (1 << 4)
> +#define I2C_SR_IIF (1 << 1)
> +#define I2C_SR_RX_NO_AK (1 << 0)
> +
> +#define I2C_CR_IEN (0 << 7)
> +#define I2C_CR_IDIS (1 << 7)
> +#define I2C_SR_IIF_CLEAR (1 << 1)
> +
> +#define BUS_IDLE (0 | (I2C_SR_IBB << 8))
> +#define BUS_BUSY (I2C_SR_IBB | (I2C_SR_IBB << 8))
> +#define IIF (I2C_SR_IIF | (I2C_SR_IIF << 8))
> +
> +#define I2C_FLAG_WRITE 0x0
> +
> +#define I2C_STATE_RETRIES 50000
> +
> +#define RETRY_COUNT 3
> +
> +#define NXP_I2C_SIGNATURE SIGNATURE_32 ('N', 'I', '2', 'C')
> +#define NXP_I2C_FROM_THIS(a) CR ((a), NXP_I2C_MASTER, \
> + I2cMaster, NXP_I2C_SIGNATURE)
> +
> +extern EFI_COMPONENT_NAME2_PROTOCOL gNxpI2cDriverComponentName2;
> +
> +#pragma pack(1)
> +typedef struct {
> + VENDOR_DEVICE_PATH Vendor;
> + UINT64 MmioBase;
> + EFI_DEVICE_PATH_PROTOCOL End;
> +} NXP_I2C_DEVICE_PATH;
> +#pragma pack()
> +
> +typedef struct {
> + UINT32 Signature;
> + EFI_I2C_MASTER_PROTOCOL I2cMaster;
> + NXP_I2C_DEVICE_PATH DevicePath;
> + NON_DISCOVERABLE_DEVICE *Dev;
> +} NXP_I2C_MASTER;
> +
> +/**
> + Record defining i2c registers
> +**/
> +typedef struct {
> + UINT8 I2cAdr;
> + UINT8 I2cFdr;
> + UINT8 I2cCr;
> + UINT8 I2cSr;
> + UINT8 I2cDr;
> +} I2C_REGS;
> +
> +typedef struct {
> + UINT16 SCLDivider;
> + UINT16 BusClockRate;
> +} CLK_DIV;
> +
> +extern
> +UINT64
> +GetBusFrequency (
> + VOID
> + );
> +
> +EFI_STATUS
> +NxpI2cInit (
> + IN EFI_HANDLE DriverBindingHandle,
> + IN EFI_HANDLE ControllerHandle
> + );
> +
> +EFI_STATUS
> +NxpI2cRelease (
> + IN EFI_HANDLE DriverBindingHandle,
> + IN EFI_HANDLE ControllerHandle
> + );
> +
> +#endif //I2C_DXE_H_
> diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> new file mode 100644
> index 0000000..0c0bf63
> --- /dev/null
> +++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> @@ -0,0 +1,58 @@
> +# @file
> +#
> +# Component description file for I2c driver
> +#
> +# Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
> +# Copyright 2017-2019 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = I2cDxe
> + FILE_GUID = 5f2927ba-1b04-4d5f-8bef-2b50c635d1e7
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = I2cDxeEntryPoint
> + UNLOAD = I2cDxeUnload
> +
> +[Sources.common]
> + ComponentName.c
> + DriverBinding.c
> + I2cDxe.c
> +
> +[LibraryClasses]
> + ArmLib
> + BaseMemoryLib
> + DevicePathLib
> + IoLib
> + MemoryAllocationLib
> + PcdLib
> + SocLib
> + TimerLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> + UefiLib
> +
> +[Guids]
> + gNxpNonDiscoverableI2cMasterGuid
> +
> +[Packages]
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[Protocols]
> + gEdkiiNonDiscoverableDeviceProtocolGuid ## TO_START
> + gEfiI2cMasterProtocolGuid ## BY_START
> +
> +[Pcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
> +
> +[Depex]
> + TRUE
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 08/12] Silicon/NXP : Add MemoryInitPei Library
[not found] ` <1570639758-30355-9-git-send-email-meenakshi.aggarwal@nxp.com>
@ 2019-10-10 15:07 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-10-10 15:07 UTC (permalink / raw)
To: Meenakshi Aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, devel, v.sethi
On Wed, Oct 09, 2019 at 10:19:14PM +0530, Meenakshi Aggarwal wrote:
> Add MemoryInitPei Library for NXP platforms.
> It has changes to get DRAM information from TFA.
Changelog information belongs below ---, or in the cover letter.
Please reword so this simply states that it retreieves DRAM
information from TF-A.
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> .../NXP/Library/MemoryInitPei/MemoryInitPeiLib.c | 139 +++++++++++++++++++++
> .../NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf | 48 +++++++
> 2 files changed, 187 insertions(+)
> create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
>
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> new file mode 100644
> index 0000000..9889d57
> --- /dev/null
> +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> @@ -0,0 +1,139 @@
> +/** @file
> +*
> +* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
> +*
> +* Copyright 2019 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Library/ArmMmuLib.h>
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +
> +#include <DramInfo.h>
> +
> +VOID
> +BuildMemoryTypeInformationHob (
> + VOID
> + );
> +
> +VOID
> +InitMmu (
> + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
> + )
> +{
> +
> + VOID *TranslationTableBase;
> + UINTN TranslationTableSize;
> + RETURN_STATUS Status;
> +
> + //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in
Very long line, please wrap.
> + // DRAM (even at the top of DRAM as it is the first permanent memory allocation)
> + Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n"));
> + }
> +}
> +
> +/*++
> +
> +Routine Description:
> +
> +
> +
> +Arguments:
> +
> + FileHandle - Handle of the file being invoked.
> + PeiServices - Describes the list of possible PEI Services.
> +
> +Returns:
> +
> + Status - EFI_SUCCESS if the boot mode could be set
> +
> +--*/
> +EFI_STATUS
> +EFIAPI
> +MemoryPeim (
> + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
> + IN UINT64 UefiMemorySize
> + )
> +{
> + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
> + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
> + EFI_PEI_HOB_POINTERS NextHob;
> + BOOLEAN Found;
> + DRAM_INFO DramInfo;
> +
> + // Get Virtual Memory Map from the Platform Library
> + ArmPlatformGetVirtualMemoryMap (&MemoryTable);
This function is added by the subsequent patch.
If there are no benefits to the current order, please reverse them.
> +
> + //
> + // Ensure MemoryTable[0].Length which is size of DRAM has been set
> + // by ArmPlatformGetVirtualMemoryMap ()
> + //
> + ASSERT (MemoryTable[0].Length != 0);
> +
> + //
> + // Now, the permanent memory has been installed, we can call AllocatePages()
> + //
> + ResourceAttributes = (
> + EFI_RESOURCE_ATTRIBUTE_PRESENT |
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_TESTED
Funky indentation.
> + );
> +
> + if (GetDramBankInfo (&DramInfo)) {
> + DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
> + return EFI_UNSUPPORTED;
> + }
> +
> + while (DramInfo.NumOfDrams--) {
> + //
> + // Check if the resource for the main system memory has been declared
> + //
> + Found = FALSE;
> + NextHob.Raw = GetHobList ();
> + while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
> + if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
> + (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >= NextHob.ResourceDescriptor->PhysicalStart) &&
> + (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength <=
> + DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo.DramRegion[DramInfo.NumOfDrams].Size))
> + {
> + Found = TRUE;
> + break;
> + }
> + NextHob.Raw = GET_NEXT_HOB (NextHob);
> + }
> +
> + if (!Found) {
> + // Reserved the memory space occupied by the firmware volume
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + ResourceAttributes,
> + DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress,
> + DramInfo.DramRegion[DramInfo.NumOfDrams].Size
Funky indentation.
> + );
> + }
> + }
> +
> + // Build Memory Allocation Hob
> + InitMmu (MemoryTable);
> +
> + if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
> + // Optional feature that helps prevent EFI memory map fragmentation.
> + BuildMemoryTypeInformationHob ();
> + }
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> new file mode 100644
> index 0000000..806da6d
> --- /dev/null
> +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> @@ -0,0 +1,48 @@
> +#/** @file
> +#
> +# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
> +# Copyright 2019 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x00010005
Bump spec version?
> + BASE_NAME = ArmMemoryInitPeiLib
> + FILE_GUID = 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM DXE_DRIVER
> +
> +[Sources]
> + MemoryInitPeiLib.c
> +
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
Please sort Packages alphabetically.
> +
> +[LibraryClasses]
> + DebugLib
> + HobLib
> + ArmMmuLib
> + ArmPlatformLib
> + PcdLib
Plese sort LibraryClasses alphabetically.
/
Leif
> +
> +[Guids]
> + gEfiMemoryTypeInformationGuid
> +
> +[FeaturePcd]
> + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
> +
> +[Pcd]
> + gArmTokenSpaceGuid.PcdSystemMemoryBase
> + gArmTokenSpaceGuid.PcdSystemMemorySize
> +
> +[Depex]
> + TRUE
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 10/12] Platform/NXP: Add Platform driver for LS1043 RDB board
[not found] ` <1570639758-30355-11-git-send-email-meenakshi.aggarwal@nxp.com>
@ 2019-10-10 15:12 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-10-10 15:12 UTC (permalink / raw)
To: Meenakshi Aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, v.sethi
On Wed, Oct 09, 2019 at 10:19:16PM +0530, Meenakshi Aggarwal wrote:
> Platform driver will be used for platform specific work.
> At present, it populate i2c driver structure with platform
> specific information and install RTC on i2c.
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> .../Drivers/PlatformDxe/PlatformDxe.c | 114 +++++++++++++++++++++
> .../Drivers/PlatformDxe/PlatformDxe.inf | 52 ++++++++++
> 2 files changed, 166 insertions(+)
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> new file mode 100644
> index 0000000..f89dcde
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> @@ -0,0 +1,114 @@
> +/** @file
> + LS1043 DXE platform driver.
> +
> + Copyright 2018-2019 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +
> +#include <Protocol/NonDiscoverableDevice.h>
> +
> +typedef struct {
> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR StartDesc;
> + UINT8 EndDesc;
> +} ADDRESS_SPACE_DESCRIPTOR;
> +
> +STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
> +
> +STATIC
> +EFI_STATUS
> +RegisterDevice (
> + IN EFI_GUID *TypeGuid,
> + IN ADDRESS_SPACE_DESCRIPTOR *Desc,
> + OUT EFI_HANDLE *Handle
> + )
> +{
> + NON_DISCOVERABLE_DEVICE *Device;
> + EFI_STATUS Status;
> +
> + Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device));
> + if (Device == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + Device->Type = TypeGuid;
> + Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent;
> + Device->Resources = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Desc;
> +
> + Status = gBS->InstallMultipleProtocolInterfaces (Handle,
> + &gEdkiiNonDiscoverableDeviceProtocolGuid, Device,
> + NULL);
> + if (EFI_ERROR (Status)) {
> + goto FreeDevice;
> + }
> + return EFI_SUCCESS;
> +
> +FreeDevice:
> + FreePool (Device);
> +
> + return Status;
> +}
> +
> +VOID
> +PopulateI2cInformation (
> + IN VOID
> + )
> +{
> + UINT32 Index;
> +
> + for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
> + mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
> + mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
> + mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
> + mI2cDesc[Index].StartDesc.GenFlag = 0;
> + mI2cDesc[Index].StartDesc.SpecificFlag = 0;
> + mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
> + mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
> + (Index * FixedPcdGet32 (PcdI2cSize));
> + mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
> + FixedPcdGet32 (PcdI2cSize) - 1;
> + mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
> + mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
> +
> + mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
> + }
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +PlatformDxeEntryPoint (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE Handle;
> +
> + Handle = NULL;
> +
> + PopulateI2cInformation ();
> +
> + Status = RegisterDevice (&gNxpNonDiscoverableI2cMasterGuid,
> + &mI2cDesc[0], &Handle);
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Install the DS1307 I2C Master protocol on this handle so the RTC driver
> + // can identify it as the I2C master it can invoke directly.
> + //
> + Status = gBS->InstallProtocolInterface (&Handle,
> + &gDs1307RealTimeClockLibI2cMasterProtocolGuid,
> + EFI_NATIVE_INTERFACE, NULL);
> + ASSERT_EFI_ERROR (Status);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> new file mode 100644
> index 0000000..d689cf4
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> @@ -0,0 +1,52 @@
> +## @file
> +#
> +# Component description file for LS1043 DXE platform driver.
> +#
> +# Copyright 2018-2019 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = PlatformDxe
> + FILE_GUID = 21108101-adcd-4123-930e-a2354a554db7
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PlatformDxeEntryPoint
> +
> +[Sources]
> + PlatformDxe.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + DebugLib
> + MemoryAllocationLib
> + PcdLib
> + UefiBootServicesTableLib
> + UefiDriverEntryPoint
> + UefiLib
> +
> +[Guids]
> + gNxpNonDiscoverableI2cMasterGuid
> +
> +[Protocols]
> + gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
> + gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES
> +
> +[FixedPcd]
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
> +
> +[Depex]
> + TRUE
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 11/12] Compilation : Add the fdf, dsc and dec files.
[not found] ` <1570639758-30355-12-git-send-email-meenakshi.aggarwal@nxp.com>
@ 2019-10-10 15:17 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-10-10 15:17 UTC (permalink / raw)
To: Meenakshi Aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, v.sethi
On Wed, Oct 09, 2019 at 10:19:17PM +0530, Meenakshi Aggarwal wrote:
> The firmware device, description and declaration files.
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Platform/NXP/FVRules.fdf.inc | 93 +++++++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 23 ++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 84 ++++++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 169 ++++++++++++
> Platform/NXP/NxpQoriqLs.dsc.inc | 373 +++++++++++++++++++++++++++
> Silicon/NXP/LS1043A/LS1043A.dec | 16 ++
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 61 +++++
> Silicon/NXP/NxpQoriqLs.dec | 103 ++++++++
> 8 files changed, 922 insertions(+)
> create mode 100644 Platform/NXP/FVRules.fdf.inc
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> create mode 100644 Platform/NXP/NxpQoriqLs.dsc.inc
> create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
> create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc.inc
> create mode 100644 Silicon/NXP/NxpQoriqLs.dec
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 12/12] Readme : Add Readme.md file.
[not found] ` <1570639758-30355-13-git-send-email-meenakshi.aggarwal@nxp.com>
@ 2019-10-10 15:19 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-10-10 15:19 UTC (permalink / raw)
To: Meenakshi Aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, edk2-devel, v.sethi
On Wed, Oct 09, 2019 at 10:19:18PM +0530, Meenakshi Aggarwal wrote:
> Readme.md to explain how to build NXP board packages.
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Platform/NXP/Readme.md | 8 ++++++++
> Readme.md | 3 +++
> 2 files changed, 11 insertions(+)
> create mode 100644 Platform/NXP/Readme.md
>
> diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md
> new file mode 100644
> index 0000000..112be46
> --- /dev/null
> +++ b/Platform/NXP/Readme.md
> @@ -0,0 +1,8 @@
> +Support for all NXP boards is available in this directory.
> +
> +# How to build
> +
> +Please follow top-level Readme.md for build instructions..
> +
> +Supported toolchain is GCC 4.9
Hmm, why?
Certainly builds fine with gcc version 8.3.0 (Debian 8.3.0-2).
> +
Git gets a little bit angry at adding a file that ends with a blank
line, please drop that.
/
Leif
> diff --git a/Readme.md b/Readme.md
> index 1befd0b..104c33f 100644
> --- a/Readme.md
> +++ b/Readme.md
> @@ -246,6 +246,9 @@ For more information, see the
> ## Socionext
> * [SynQuacer](Platform/Socionext/DeveloperBox)
>
> +## NXP
> +* [LS1043aRdb](Platform/NXP/LS1043aRdbPkg)
> +
> # Maintainers
>
> See [Maintainers.txt](Maintainers.txt).
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [PATCH edk2-platforms 00/12] NXP : Add support of LS1043 SoC.
[not found] ` <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com>
` (8 preceding siblings ...)
[not found] ` <1570639758-30355-13-git-send-email-meenakshi.aggarwal@nxp.com>
@ 2019-10-10 15:27 ` Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
10 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-10-10 15:27 UTC (permalink / raw)
To: Meenakshi Aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, devel, v.sethi
Thanks for this.
On the whole, the watchdog situation is the only real concern I have
with regards to merging this set, the rest is pretty much all code
style, and there's not much left of that.
Looking forward to a v2, and finally merging some of this - but I warn
you that I am on holiday Friday/Monday, so will not be able to have
another look until Tuesday (UK time).
Best Regards,
Leif
On Wed, Oct 09, 2019 at 10:19:06PM +0530, Meenakshi Aggarwal wrote:
> We have combined all review comments recieved till now.
> Major changes are:
> - Created SocLib
> - Divided Swapped MMIO APIs in two separate patches.
> - Removed local helper script for compilation.
>
> Following patches will add support of LS1043 SoC in edk2-platforms.
>
> We will send patches to support LS2088 and LS1046 SoC after LS1043 gets merged.
>
> Our directory structure will be:
>
> edk2-platforms
> |-- Platform
> | |-- NXP
> | | |-- FVRules.fdf.inc
> | | |-- LS1043aRdbPkg
> | | | |-- Drivers
> | | | | `-- PlatformDxe
> | | | | |-- PlatformDxe.c
> | | | | `-- PlatformDxe.inf
> | | | |-- Library
> | | | | `-- PlatformLib
> | | | | |-- ArmPlatformLib.c
> | | | | |-- ArmPlatformLib.inf
> | | | | |-- NxpQoriqLsHelper.S
> | | | | `-- NxpQoriqLsMem.c
> | | | |-- LS1043aRdbPkg.dec
> | | | |-- LS1043aRdbPkg.dsc
> | | | `-- LS1043aRdbPkg.fdf
> | | |-- NxpQoriqLs.dsc.inc
> | | `-- Readme.md
> |-- Silicon
> | |-- Maxim
> | | `-- Library
> | | `-- Ds1307RtcLib
> | | |-- Ds1307Rtc.h
> | | |-- Ds1307RtcLib.c
> | | |-- Ds1307RtcLib.dec
> | | `-- Ds1307RtcLib.inf
> | |-- NXP
> | | |-- Drivers
> | | | |-- I2cDxe
> | | | | |-- ComponentName.c
> | | | | |-- DriverBinding.c
> | | | | |-- I2cDxe.c
> | | | | |-- I2cDxe.h
> | | | | `-- I2cDxe.inf
> | | | `-- WatchDog
> | | | |-- WatchDog.c
> | | | |-- WatchDogDxe.inf
> | | | `-- WatchDog.h
> | | |-- Include
> | | | |-- Chassis2
> | | | | |-- LsSerDes.h
> | | | | `-- NxpSoc.h
> | | | |-- DramInfo.h
> | | | `-- Library
> | | | `-- IoAccessLib.h
> | | |-- Library
> | | | |-- DUartPortLib
> | | | | |-- DUart.h
> | | | | |-- DUartPortLib.c
> | | | | `-- DUartPortLib.inf
> | | | |-- IoAccessLib
> | | | | |-- IoAccessLib.c
> | | | | `-- IoAccessLib.inf
> | | | |-- MemoryInitPei
> | | | | |-- MemoryInitPeiLib.c
> | | | | `-- MemoryInitPeiLib.inf
> | | | |-- Pcf8563RealTimeClockLib
> | | | | |-- Pcf8563RealTimeClockLib.c
> | | | | |-- Pcf8563RealTimeClockLib.dec
> | | | | `-- Pcf8563RealTimeClockLib.inf
> | | | `-- SocLib
> | | | |-- Chassis2
> | | | | `-- Soc.c
> | | | |-- Chassis.c
> | | | |-- LS1043aSocLib.inf
> | | | |-- NxpChassis.h
> | | | `-- SerDes.c
> | | |-- LS1043A
> | | | |-- Include
> | | | | `-- SocSerDes.h
> | | | |-- LS1043A.dec
> | | | `-- LS1043A.dsc.inc
> | | `-- NxpQoriqLs.dec
>
>
> In Silicon/NXP, we are keeping our SoC specific information and all Drivers and Library which are used by SoCs.
>
> Platform/NXP/ will host our board packages and build script.
>
> Board specific libraries and header files will reside inside board package.
>
>
> Looking forward for your kind support in upstreaming our boards in edk2-platforms.
>
>
> Meenakshi Aggarwal (12):
> Silicon/NXP: Add Library to provide Mmio APIs with swapped data.
> Silicon/NXP: Add function to return swapped Mmio APIs pointer
> Silicon/NXP : Add support for Watchdog driver
> SocLib : Add support for initialization of peripherals
> Silicon/NXP : Add support for DUART library
> Silicon/NXP: Add support for I2c driver
> Silicon/Maxim : Add support for DS1307 RTC library
> Silicon/NXP : Add MemoryInitPei Library
> Platform/NXP: Add support for ArmPlatformLib
> Platform/NXP: Add Platform driver for LS1043 RDB board
> Compilation : Add the fdf, dsc and dec files.
> Readme : Add Readme.md file.
>
> Platform/NXP/FVRules.fdf.inc | 93 +++
> .../Drivers/PlatformDxe/PlatformDxe.c | 114 ++++
> .../Drivers/PlatformDxe/PlatformDxe.inf | 52 ++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 23 +
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 84 +++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 169 +++++
> .../Library/PlatformLib/ArmPlatformLib.c | 98 +++
> .../Library/PlatformLib/ArmPlatformLib.inf | 55 ++
> .../Library/PlatformLib/NxpQoriqLsHelper.S | 31 +
> .../Library/PlatformLib/NxpQoriqLsMem.c | 144 +++++
> Platform/NXP/NxpQoriqLs.dsc.inc | 373 +++++++++++
> Platform/NXP/Readme.md | 8 +
> Readme.md | 3 +
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h | 48 ++
> Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 372 +++++++++++
> .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec | 23 +
> .../Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf | 40 ++
> Silicon/NXP/Drivers/I2cDxe/ComponentName.c | 179 ++++++
> Silicon/NXP/Drivers/I2cDxe/DriverBinding.c | 235 +++++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 690 +++++++++++++++++++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 100 +++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 58 ++
> Silicon/NXP/Drivers/WatchDog/WatchDog.c | 396 ++++++++++++
> Silicon/NXP/Drivers/WatchDog/WatchDog.h | 32 +
> Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf | 41 ++
> Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 ++
> Silicon/NXP/Include/Chassis2/NxpSoc.h | 361 +++++++++++
> Silicon/NXP/Include/DramInfo.h | 38 ++
> Silicon/NXP/Include/Library/IoAccessLib.h | 326 ++++++++++
> Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 ++
> Silicon/NXP/LS1043A/LS1043A.dec | 16 +
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 61 ++
> Silicon/NXP/Library/DUartPortLib/DUart.h | 122 ++++
> Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 364 +++++++++++
> Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 34 +
> Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 404 ++++++++++++
> Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf | 26 +
> .../NXP/Library/MemoryInitPei/MemoryInitPeiLib.c | 139 +++++
> .../NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf | 48 ++
> Silicon/NXP/Library/SocLib/Chassis.c | 498 +++++++++++++++
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 162 +++++
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 45 ++
> Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ++++
> Silicon/NXP/Library/SocLib/SerDes.c | 268 ++++++++
> Silicon/NXP/NxpQoriqLs.dec | 103 +++
> 45 files changed, 6725 insertions(+)
> create mode 100644 Platform/NXP/FVRules.fdf.inc
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
> create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
> create mode 100644 Platform/NXP/NxpQoriqLs.dsc.inc
> create mode 100644 Platform/NXP/Readme.md
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
> create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/ComponentName.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
> create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.c
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDog.h
> create mode 100644 Silicon/NXP/Drivers/WatchDog/WatchDogDxe.inf
> create mode 100644 Silicon/NXP/Include/Chassis2/LsSerDes.h
> create mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
> create mode 100644 Silicon/NXP/Include/DramInfo.h
> create mode 100644 Silicon/NXP/Include/Library/IoAccessLib.h
> create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
> create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
> create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc.inc
> create mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
> create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
> create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
> create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> create mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
> create mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
> create mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> create mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
> create mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
> create mode 100644 Silicon/NXP/NxpQoriqLs.dec
>
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v2 00/11] NXP : Add support of LS1043 SoC.
[not found] ` <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com>
` (9 preceding siblings ...)
2019-10-10 15:27 ` [PATCH edk2-platforms 00/12] NXP : Add support of LS1043 SoC Leif Lindholm
@ 2019-11-21 16:25 ` Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 01/11] Silicon/NXP: Add Library to provide Mmio APIs with swapped data Meenakshi Aggarwal
` (11 more replies)
10 siblings, 12 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-11-21 16:25 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, devel
Cc: v.sethi, Meenakshi Aggarwal
We have combined all review comments recieved till now.
Major changes are:
- Using Watchdog driver from MdeModulePkg
Following patches will add support of LS1043 SoC in edk2-platforms.
We will send patches to support LS2088 and LS1046 SoC after LS1043 gets merged.
Our directory structure will be:
edk2-platforms
|-- Platform
| |-- NXP
| | |-- FVRules.fdf.inc
| | |-- LS1043aRdbPkg
| | | |-- Drivers
| | | | `-- PlatformDxe
| | | | |-- PlatformDxe.c
| | | | `-- PlatformDxe.inf
| | | |-- Library
| | | | `-- PlatformLib
| | | | |-- ArmPlatformLib.c
| | | | |-- ArmPlatformLib.inf
| | | | |-- NxpQoriqLsHelper.S
| | | | `-- NxpQoriqLsMem.c
| | | |-- LS1043aRdbPkg.dec
| | | |-- LS1043aRdbPkg.dsc
| | | `-- LS1043aRdbPkg.fdf
| | |-- NxpQoriqLs.dsc.inc
| | `-- Readme.md
|-- Silicon
| |-- Maxim
| | `-- Library
| | `-- Ds1307RtcLib
| | |-- Ds1307Rtc.h
| | |-- Ds1307RtcLib.c
| | |-- Ds1307RtcLib.dec
| | `-- Ds1307RtcLib.inf
| |-- NXP
| | |-- Drivers
| | | |-- I2cDxe
| | | | |-- ComponentName.c
| | | | |-- DriverBinding.c
| | | | |-- I2cDxe.c
| | | | |-- I2cDxe.h
| | | | `-- I2cDxe.inf
| | |-- Include
| | | |-- Chassis2
| | | | |-- LsSerDes.h
| | | | `-- NxpSoc.h
| | | |-- DramInfo.h
| | | `-- Library
| | | `-- IoAccessLib.h
| | |-- Library
| | | |-- DUartPortLib
| | | | |-- DUart.h
| | | | |-- DUartPortLib.c
| | | | `-- DUartPortLib.inf
| | | |-- IoAccessLib
| | | | |-- IoAccessLib.c
| | | | `-- IoAccessLib.inf
| | | |-- MemoryInitPei
| | | | |-- MemoryInitPeiLib.c
| | | | `-- MemoryInitPeiLib.inf
| | | |-- Pcf8563RealTimeClockLib
| | | | |-- Pcf8563RealTimeClockLib.c
| | | | |-- Pcf8563RealTimeClockLib.dec
| | | | `-- Pcf8563RealTimeClockLib.inf
| | | `-- SocLib
| | | |-- Chassis2
| | | | `-- Soc.c
| | | |-- Chassis.c
| | | |-- LS1043aSocLib.inf
| | | |-- NxpChassis.h
| | | `-- SerDes.c
| | |-- LS1043A
| | | |-- Include
| | | | `-- SocSerDes.h
| | | |-- LS1043A.dec
| | | `-- LS1043A.dsc.inc
| | `-- NxpQoriqLs.dec
In Silicon/NXP, we are keeping our SoC specific information and all Drivers and Library which are used by SoCs.
Platform/NXP/ will host our board packages and build script.
Board specific libraries and header files will reside inside board package.
Looking forward for your kind support in upstreaming our boards in edk2-platforms.
Meenakshi Aggarwal (11):
Silicon/NXP: Add Library to provide Mmio APIs with swapped data.
Silicon/NXP: Add function to return swapped Mmio APIs pointer
SocLib : Add support for initialization of peripherals
Silicon/NXP : Add support for DUART library
Silicon/NXP: Add support for I2c driver
Silicon/Maxim : Add support for DS1307 RTC library
Silicon/NXP : Add MemoryInitPei Library
Platform/NXP: Add support for ArmPlatformLib
Platform/NXP: Add Platform driver for LS1043 RDB board
Compilation : Add the fdf, dsc and dec files.
Readme : Add Readme.md file.
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 23 +
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec | 23 +
Silicon/NXP/LS1043A/LS1043A.dec | 16 +
Silicon/NXP/NxpQoriqLs.dec | 103 +++
Platform/NXP/NxpQoriqLs.dsc.inc | 368 +++++++++++
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 61 ++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 77 +++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 167 +++++
Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf | 52 ++
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 55 ++
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf | 40 ++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 58 ++
Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 34 +
Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf | 26 +
Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf | 48 ++
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 45 ++
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h | 48 ++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 100 +++
Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 ++
Silicon/NXP/Include/Chassis2/NxpSoc.h | 361 ++++++++++
Silicon/NXP/Include/DramInfo.h | 38 ++
Silicon/NXP/Include/Library/IoAccessLib.h | 326 +++++++++
Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 ++
Silicon/NXP/Library/DUartPortLib/DUart.h | 122 ++++
Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ++++
Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c | 114 ++++
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c | 98 +++
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 144 ++++
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 372 +++++++++++
Silicon/NXP/Drivers/I2cDxe/ComponentName.c | 179 +++++
Silicon/NXP/Drivers/I2cDxe/DriverBinding.c | 235 +++++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 690 ++++++++++++++++++++
Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 364 +++++++++++
Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 404 ++++++++++++
Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c | 139 ++++
Silicon/NXP/Library/SocLib/Chassis.c | 498 ++++++++++++++
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 162 +++++
Silicon/NXP/Library/SocLib/SerDes.c | 268 ++++++++
Platform/NXP/FVRules.fdf.inc | 93 +++
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S | 31 +
Platform/NXP/Readme.md | 5 +
Readme.md | 3 +
42 files changed, 6239 insertions(+)
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
create mode 100644 Silicon/NXP/NxpQoriqLs.dec
create mode 100644 Platform/NXP/NxpQoriqLs.dsc.inc
create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc.inc
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
create mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
create mode 100644 Silicon/NXP/Include/Chassis2/LsSerDes.h
create mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
create mode 100644 Silicon/NXP/Include/DramInfo.h
create mode 100644 Silicon/NXP/Include/Library/IoAccessLib.h
create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
create mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/ComponentName.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
create mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
create mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
create mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
create mode 100644 Platform/NXP/FVRules.fdf.inc
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/Readme.md
--
1.9.1
^ permalink raw reply [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v2 01/11] Silicon/NXP: Add Library to provide Mmio APIs with swapped data.
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
@ 2019-11-21 16:25 ` Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 02/11] Silicon/NXP: Add function to return swapped Mmio APIs pointer Meenakshi Aggarwal
` (10 subsequent siblings)
11 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-11-21 16:25 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, devel
Cc: v.sethi, Meenakshi Aggarwal
This library provided MMIO APIs for modules need swapping.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf | 26 ++
Silicon/NXP/Include/Library/IoAccessLib.h | 248 ++++++++++++++++
Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 302 ++++++++++++++++++++
3 files changed, 576 insertions(+)
diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
new file mode 100644
index 000000000000..4f3af4647e95
--- /dev/null
+++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
@@ -0,0 +1,26 @@
+## @IoAccessLib.inf
+
+# Copyright 2017-2019 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = IoAccessLib
+ FILE_GUID = 28d77333-77eb-4faf-8735-130e5eb3e343
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = IoAccessLib
+
+[Sources.common]
+ IoAccessLib.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ IoLib
diff --git a/Silicon/NXP/Include/Library/IoAccessLib.h b/Silicon/NXP/Include/Library/IoAccessLib.h
new file mode 100644
index 000000000000..b72e65c83091
--- /dev/null
+++ b/Silicon/NXP/Include/Library/IoAccessLib.h
@@ -0,0 +1,248 @@
+/** @file
+ *
+ * Copyright 2017-2019 NXP
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#ifndef IO_ACCESS_LIB_H_
+#define IO_ACCESS_LIB_H_
+
+#include <Base.h>
+
+/**
+ MmioRead16 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+SwapMmioRead16 (
+ IN UINTN Address
+ );
+
+/**
+ MmioRead32 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+SwapMmioRead32 (
+ IN UINTN Address
+ );
+
+/**
+ MmioRead64 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+SwapMmioRead64 (
+ IN UINTN Address
+ );
+
+/**
+ MmioWrite16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ );
+
+/**
+ MmioWrite32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ );
+
+/**
+ MmioWrite64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ );
+
+/**
+ MmioAndThenOr16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ MmioAndThenOr32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ MmioAndThenOr64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioAndThenOr64 (
+ IN UINTN Address,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ );
+
+/**
+ MmioOr16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ );
+
+/**
+ MmioOr32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ );
+
+/**
+ MmioOr64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioOr64 (
+ IN UINTN Address,
+ IN UINT64 OrData
+ );
+
+/**
+ MmioAnd16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ );
+
+/**
+ MmioAnd32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ );
+
+/**
+ MmioAnd64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioAnd64 (
+ IN UINTN Address,
+ IN UINT64 AndData
+ );
+
+#endif /* IO_ACCESS_LIB_H_ */
diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
new file mode 100644
index 000000000000..e9e535fc2f85
--- /dev/null
+++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
@@ -0,0 +1,302 @@
+/** IoAccessLib.c
+
+ Provide MMIO APIs for BE modules.
+
+ Copyright 2017-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/IoLib.h>
+
+/**
+ MmioRead16 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+SwapMmioRead16 (
+ IN UINTN Address
+ )
+{
+ return SwapBytes16 (MmioRead16 (Address));
+}
+
+/**
+ MmioRead32 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+SwapMmioRead32 (
+ IN UINTN Address
+ )
+{
+ return SwapBytes32 (MmioRead32 (Address));
+}
+
+/**
+ MmioRead64 for Big-Endian modules.
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+SwapMmioRead64 (
+ IN UINTN Address
+ )
+{
+ return SwapBytes64 (MmioRead64 (Address));
+}
+
+/**
+ MmioWrite16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ )
+{
+ return MmioWrite16 (Address, SwapBytes16 (Value));
+}
+
+/**
+ MmioWrite32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ return MmioWrite32 (Address, SwapBytes32 (Value));
+}
+
+/**
+ MmioWrite64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ )
+{
+ return MmioWrite64 (Address, SwapBytes64 (Value));
+}
+
+/**
+ MmioAndThenOr16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ AndData = SwapBytes16 (AndData);
+ OrData = SwapBytes16 (OrData);
+
+ return MmioAndThenOr16 (Address, AndData, OrData);
+}
+
+/**
+ MmioAndThenOr32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ AndData = SwapBytes32 (AndData);
+ OrData = SwapBytes32 (OrData);
+
+ return MmioAndThenOr32 (Address, AndData, OrData);
+}
+
+/**
+ MmioAndThenOr64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+ @param OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioAndThenOr64 (
+ IN UINTN Address,
+ IN UINT64 AndData,
+ IN UINT64 OrData
+ )
+{
+ AndData = SwapBytes64 (AndData);
+ OrData = SwapBytes64 (OrData);
+
+ return MmioAndThenOr64 (Address, AndData, OrData);
+}
+
+/**
+ MmioOr16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ )
+{
+ return MmioOr16 (Address, SwapBytes16 (OrData));
+}
+
+/**
+ MmioOr32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ )
+{
+ return MmioOr32 (Address, SwapBytes32 (OrData));
+}
+
+/**
+ MmioOr64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param OrData The value to OR with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioOr64 (
+ IN UINTN Address,
+ IN UINT64 OrData
+ )
+{
+ return MmioOr64 (Address, SwapBytes64 (OrData));
+}
+
+/**
+ MmioAnd16 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+SwapMmioAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ )
+{
+ return MmioAnd16 (Address, SwapBytes16 (AndData));
+}
+
+/**
+ MmioAnd32 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+SwapMmioAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ )
+{
+ return MmioAnd32 (Address, SwapBytes32 (AndData));
+}
+
+/**
+ MmioAnd64 for Big-Endian modules.
+
+ @param Address The MMIO register to write.
+ @param AndData The value to AND with the read value from the MMIO register.
+
+ @return The value written back to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+SwapMmioAnd64 (
+ IN UINTN Address,
+ IN UINT64 AndData
+ )
+{
+ return MmioAnd64 (Address, SwapBytes64 (AndData));
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v2 02/11] Silicon/NXP: Add function to return swapped Mmio APIs pointer
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 01/11] Silicon/NXP: Add Library to provide Mmio APIs with swapped data Meenakshi Aggarwal
@ 2019-11-21 16:25 ` Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 03/11] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
` (9 subsequent siblings)
11 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-11-21 16:25 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, devel
Cc: v.sethi, Meenakshi Aggarwal
Add support to return pointer to MMIO APIs on basis of Swap flag.
If Flag is True then MMIO APIs returned in which data
swapped after reading from MMIO and before write using MMIO.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/NXP/Include/Library/IoAccessLib.h | 78 +++++++++++++++
Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 102 ++++++++++++++++++++
2 files changed, 180 insertions(+)
diff --git a/Silicon/NXP/Include/Library/IoAccessLib.h b/Silicon/NXP/Include/Library/IoAccessLib.h
index b72e65c83091..0b708d544fa7 100644
--- a/Silicon/NXP/Include/Library/IoAccessLib.h
+++ b/Silicon/NXP/Include/Library/IoAccessLib.h
@@ -11,6 +11,84 @@
#include <Base.h>
+///
+/// Structure to have pointer to R/W
+/// Mmio operations for 16 bits.
+///
+typedef struct _MMIO_OPERATIONS_16 {
+ UINT16 (*Read16) (UINTN Address);
+ UINT16 (*Write16) (UINTN Address, UINT16 Value);
+ UINT16 (*Or16) (UINTN Address, UINT16 OrData);
+ UINT16 (*And16) (UINTN Address, UINT16 AndData);
+ UINT16 (*AndThenOr16) (UINTN Address, UINT16 AndData, UINT16 OrData);
+} MMIO_OPERATIONS_16;
+
+///
+/// Structure to have pointer to R/W
+/// Mmio operations for 32 bits.
+///
+typedef struct _MMIO_OPERATIONS_32 {
+ UINT32 (*Read32) (UINTN Address);
+ UINT32 (*Write32) (UINTN Address, UINT32 Value);
+ UINT32 (*Or32) (UINTN Address, UINT32 OrData);
+ UINT32 (*And32) (UINTN Address, UINT32 AndData);
+ UINT32 (*AndThenOr32) (UINTN Address, UINT32 AndData, UINT32 OrData);
+} MMIO_OPERATIONS_32;
+
+///
+/// Structure to have pointer to R/W
+/// Mmio operations for 64 bits.
+///
+typedef struct _MMIO_OPERATIONS_64 {
+ UINT64 (*Read64) (UINTN Address);
+ UINT64 (*Write64) (UINTN Address, UINT64 Value);
+ UINT64 (*Or64) (UINTN Address, UINT64 OrData);
+ UINT64 (*And64) (UINTN Address, UINT64 AndData);
+ UINT64 (*AndThenOr64) (UINTN Address, UINT64 AndData, UINT64 OrData);
+} MMIO_OPERATIONS_64;
+
+/**
+ Function to return pointer to 16 bit Mmio operations.
+
+ @param Swap Flag to tell if Swap is needed or not
+ on Mmio Operations.
+
+ @return Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_16 *
+GetMmioOperations16 (
+ IN BOOLEAN Swap
+ );
+
+/**
+ Function to return pointer to 32 bit Mmio operations.
+
+ @param Swap Flag to tell if Swap is needed or not
+ on Mmio Operations.
+
+ @return Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_32 *
+GetMmioOperations32 (
+ IN BOOLEAN Swap
+ );
+
+/**
+ Function to return pointer to 64 bit Mmio operations.
+
+ @param Swap Flag to tell if Swap is needed or not
+ on Mmio Operations.
+
+ @return Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_64 *
+GetMmioOperations64 (
+ IN BOOLEAN Swap
+ );
+
/**
MmioRead16 for Big-Endian modules.
diff --git a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
index e9e535fc2f85..6ed83d019a6e 100644
--- a/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
+++ b/Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
@@ -300,3 +300,105 @@ SwapMmioAnd64 (
{
return MmioAnd64 (Address, SwapBytes64 (AndData));
}
+
+STATIC MMIO_OPERATIONS_16 SwappingFunctions16 = {
+ SwapMmioRead16,
+ SwapMmioWrite16,
+ SwapMmioOr16,
+ SwapMmioAnd16,
+ SwapMmioAndThenOr16,
+};
+
+STATIC MMIO_OPERATIONS_16 NonSwappingFunctions16 = {
+ MmioRead16,
+ MmioWrite16,
+ MmioOr16,
+ MmioAnd16,
+ MmioAndThenOr16,
+};
+
+STATIC MMIO_OPERATIONS_32 SwappingFunctions32 = {
+ SwapMmioRead32,
+ SwapMmioWrite32,
+ SwapMmioOr32,
+ SwapMmioAnd32,
+ SwapMmioAndThenOr32,
+};
+
+STATIC MMIO_OPERATIONS_32 NonSwappingFunctions32 = {
+ MmioRead32,
+ MmioWrite32,
+ MmioOr32,
+ MmioAnd32,
+ MmioAndThenOr32,
+};
+
+STATIC MMIO_OPERATIONS_64 SwappingFunctions64 = {
+ SwapMmioRead64,
+ SwapMmioWrite64,
+ SwapMmioOr64,
+ SwapMmioAnd64,
+ SwapMmioAndThenOr64,
+};
+
+STATIC MMIO_OPERATIONS_64 NonSwappingFunctions64 = {
+ MmioRead64,
+ MmioWrite64,
+ MmioOr64,
+ MmioAnd64,
+ MmioAndThenOr64,
+};
+
+/**
+ Function to return pointer to 16 bit Mmio operations.
+
+ @param Swap Flag to tell if Swap is needed or not
+ on Mmio Operations.
+
+ @return Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_16 *
+GetMmioOperations16 (BOOLEAN Swap) {
+ if (Swap) {
+ return &SwappingFunctions16;
+ } else {
+ return &NonSwappingFunctions16;
+ }
+}
+
+/**
+ Function to return pointer to 32 bit Mmio operations.
+
+ @param Swap Flag to tell if Swap is needed or not
+ on Mmio Operations.
+
+ @return Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_32 *
+GetMmioOperations32 (BOOLEAN Swap) {
+ if (Swap) {
+ return &SwappingFunctions32;
+ } else {
+ return &NonSwappingFunctions32;
+ }
+}
+
+/**
+ Function to return pointer to 64 bit Mmio operations.
+
+ @param Swap Flag to tell if Swap is needed or not
+ on Mmio Operations.
+
+ @return Pointer to Mmio Operations.
+
+**/
+MMIO_OPERATIONS_64 *
+GetMmioOperations64 (BOOLEAN Swap) {
+ if (Swap) {
+ return &SwappingFunctions64;
+ } else {
+ return &NonSwappingFunctions64;
+ }
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v2 03/11] SocLib : Add support for initialization of peripherals
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 01/11] Silicon/NXP: Add Library to provide Mmio APIs with swapped data Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 02/11] Silicon/NXP: Add function to return swapped Mmio APIs pointer Meenakshi Aggarwal
@ 2019-11-21 16:25 ` Meenakshi Aggarwal
2019-11-26 16:43 ` Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 04/11] Silicon/NXP : Add support for DUART library Meenakshi Aggarwal
` (8 subsequent siblings)
11 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-11-21 16:25 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, devel
Cc: v.sethi, Meenakshi Aggarwal
Add SocInit function that initializes peripherals
and print board and soc information.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 45 ++
Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 +++
Silicon/NXP/Include/Chassis2/NxpSoc.h | 361 ++++++++++++++
Silicon/NXP/Include/DramInfo.h | 38 ++
Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 ++
Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ++++++
Silicon/NXP/Library/SocLib/Chassis.c | 498 ++++++++++++++++++++
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 162 +++++++
Silicon/NXP/Library/SocLib/SerDes.c | 268 +++++++++++
9 files changed, 1621 insertions(+)
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
new file mode 100644
index 000000000000..cb670a12797e
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -0,0 +1,45 @@
+# @file
+#
+# Copyright 2017-2019 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SocLib
+ FILE_GUID = e868c5ca-9729-43ae-bff4-438c67de8c68
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/LS1043A/LS1043A.dec
+
+[LibraryClasses]
+ ArmSmcLib
+ BaseLib
+ DebugLib
+ IoAccessLib
+ SerialPortLib
+
+[Sources.common]
+ Chassis.c
+ Chassis2/Soc.c
+ SerDes.c
+
+[BuildOptions]
+ GCC:*_*_*_CC_FLAGS = -DCHASSIS2
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
diff --git a/Silicon/NXP/Include/Chassis2/LsSerDes.h b/Silicon/NXP/Include/Chassis2/LsSerDes.h
new file mode 100644
index 000000000000..9afbc522398a
--- /dev/null
+++ b/Silicon/NXP/Include/Chassis2/LsSerDes.h
@@ -0,0 +1,62 @@
+/** LsSerDes.h
+ The Header file of SerDes Module for Chassis 2
+
+ Copyright 2017-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef LS_SERDES_H_
+#define LS_SERDES_H_
+
+#include <Uefi/UefiBaseType.h>
+
+#define SRDS_MAX_LANES 4
+
+typedef enum {
+ None = 0,
+ Pcie1,
+ Pcie2,
+ Pcie3,
+ Sata,
+ SgmiiFm1Dtsec1,
+ SgmiiFm1Dtsec2,
+ SgmiiFm1Dtsec5,
+ SgmiiFm1Dtsec6,
+ SgmiiFm1Dtsec9,
+ SgmiiFm1Dtsec10,
+ QsgmiiFm1A,
+ XfiFm1Mac9,
+ XfiFm1Mac10,
+ Sgmii2500Fm1Dtsec2,
+ Sgmii2500Fm1Dtsec5,
+ Sgmii2500Fm1Dtsec9,
+ Sgmii2500Fm1Dtsec10,
+ SerdesPrtclCount
+} SERDES_PROTOCOL;
+
+typedef enum {
+ Srds1 = 0,
+ Srds2,
+ SrdsMaxNum
+} SERDES_NUMBER;
+
+typedef struct {
+ UINT16 Protocol;
+ UINT8 SrdsLane[SRDS_MAX_LANES];
+} SERDES_CONFIG;
+
+typedef VOID
+(*SERDES_PROBE_LANES_CALLBACK) (
+ IN SERDES_PROTOCOL LaneProtocol,
+ IN VOID *Arg
+ );
+
+VOID
+SerDesProbeLanes(
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ );
+
+#endif /* LS_SERDES_H_ */
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
new file mode 100644
index 000000000000..f05a813750e8
--- /dev/null
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -0,0 +1,361 @@
+/** Soc.h
+* Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+* Copyright 2017-2019 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef NXP_SOC_H_
+#define NXP_SOC_H_
+
+#define HWA_CGA_M1_CLK_SEL 0xe0000000
+#define HWA_CGA_M1_CLK_SHIFT 29
+
+#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
+#define NUM_CC_PLLS 2
+#define CLK_FREQ 100000000
+#define MAX_CPUS 4
+#define NUM_FMAN 1
+#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
+
+/* RCW SERDES MACRO */
+#define RCWSR_INDEX 4
+#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
+#define RCWSR_SRDS1_PRTCL_SHIFT 16
+#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
+#define RCWSR_SRDS2_PRTCL_SHIFT 0
+
+/* SMMU Defintions */
+#define SMMU_BASE_ADDR 0x09000000
+#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
+#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
+#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
+
+#define SCR0_USFCFG_MASK 0x00000400
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SACR_PAGESIZE_MASK 0x00010000
+#define IDR1_PAGESIZE_MASK 0x80000000
+
+typedef struct {
+ UINTN FreqProcessor[MAX_CPUS];
+ UINTN FreqSystemBus;
+ UINTN FreqDdrBus;
+ UINTN FreqLocalBus;
+ UINTN FreqSdhc;
+ UINTN FreqFman[NUM_FMAN];
+ UINTN FreqQman;
+} SYS_INFO;
+
+/* Device Configuration and Pin Control */
+typedef struct {
+ UINT32 PorSr1; /* POR status 1 */
+#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
+ UINT32 PorSr2; /* POR status 2 */
+ UINT8 Res008[0x20-0x8];
+ UINT32 GppOrCr1; /* General-purpose POR configuration */
+ UINT32 GppOrCr2;
+ UINT32 DcfgFuseSr; /* Fuse status register */
+ UINT8 Res02c[0x70-0x2c];
+ UINT32 DevDisr; /* Device disable control */
+ UINT32 DevDisr2; /* Device disable control 2 */
+ UINT32 DevDisr3; /* Device disable control 3 */
+ UINT32 DevDisr4; /* Device disable control 4 */
+ UINT32 DevDisr5; /* Device disable control 5 */
+ UINT32 DevDisr6; /* Device disable control 6 */
+ UINT32 DevDisr7; /* Device disable control 7 */
+ UINT8 Res08c[0x94-0x8c];
+ UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
+ UINT32 CoreDisrL; /* lower portion for support of 64 cores */
+ UINT8 Res09c[0xa0-0x9c];
+ UINT32 Pvr; /* Processor version */
+ UINT32 Svr; /* System version */
+ UINT32 Mvr; /* Manufacturing version */
+ UINT8 Res0ac[0xb0-0xac];
+ UINT32 RstCr; /* Reset control */
+ UINT32 RstRqPblSr; /* Reset request preboot loader status */
+ UINT8 Res0b8[0xc0-0xb8];
+ UINT32 RstRqMr1; /* Reset request mask */
+ UINT8 Res0c4[0xc8-0xc4];
+ UINT32 RstRqSr1; /* Reset request status */
+ UINT8 Res0cc[0xd4-0xcc];
+ UINT32 RstRqWdTmrL; /* Reset request WDT mask */
+ UINT8 Res0d8[0xdc-0xd8];
+ UINT32 RstRqWdtSrL; /* Reset request WDT status */
+ UINT8 Res0e0[0xe4-0xe0];
+ UINT32 BrrL; /* Boot release */
+ UINT8 Res0e8[0x100-0xe8];
+ UINT32 RcwSr[16]; /* Reset control word status */
+#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
+#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
+#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
+#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
+ UINT8 Res140[0x200-0x140];
+ UINT32 ScratchRw[4]; /* Scratch Read/Write */
+ UINT8 Res210[0x300-0x210];
+ UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
+ UINT8 Res310[0x400-0x310];
+ UINT32 CrstSr[12];
+ UINT8 Res430[0x500-0x430];
+ /* PCI Express n Logical I/O Device Number register */
+ UINT32 DcfgCcsrPex1LiodNr;
+ UINT32 DcfgCcsrPex2LiodNr;
+ UINT32 DcfgCcsrPex3LiodNr;
+ UINT32 DcfgCcsrPex4LiodNr;
+ /* RIO n Logical I/O Device Number register */
+ UINT32 DcfgCcsrRio1LiodNr;
+ UINT32 DcfgCcsrRio2LiodNr;
+ UINT32 DcfgCcsrRio3LiodNr;
+ UINT32 DcfgCcsrRio4LiodNr;
+ /* USB Logical I/O Device Number register */
+ UINT32 DcfgCcsrUsb1LiodNr;
+ UINT32 DcfgCcsrUsb2LiodNr;
+ UINT32 DcfgCcsrUsb3LiodNr;
+ UINT32 DcfgCcsrUsb4LiodNr;
+ /* SD/MMC Logical I/O Device Number register */
+ UINT32 DcfgCcsrSdMmc1LiodNr;
+ UINT32 DcfgCcsrSdMmc2LiodNr;
+ UINT32 DcfgCcsrSdMmc3LiodNr;
+ UINT32 DcfgCcsrSdMmc4LiodNr;
+ /* RIO Message Unit Logical I/O Device Number register */
+ UINT32 DcfgCcsrRiomaintLiodNr;
+ UINT8 Res544[0x550-0x544];
+ UINT32 SataLiodNr[4];
+ UINT8 Res560[0x570-0x560];
+ UINT32 DcfgCcsrMisc1LiodNr;
+ UINT32 DcfgCcsrMisc2LiodNr;
+ UINT32 DcfgCcsrMisc3LiodNr;
+ UINT32 DcfgCcsrMisc4LiodNr;
+ UINT32 DcfgCcsrDma1LiodNr;
+ UINT32 DcfgCcsrDma2LiodNr;
+ UINT32 DcfgCcsrDma3LiodNr;
+ UINT32 DcfgCcsrDma4LiodNr;
+ UINT32 DcfgCcsrSpare1LiodNr;
+ UINT32 DcfgCcsrSpare2LiodNr;
+ UINT32 DcfgCcsrSpare3LiodNr;
+ UINT32 DcfgCcsrSpare4LiodNr;
+ UINT8 Res5a0[0x600-0x5a0];
+ UINT32 DcfgCcsrPblSr;
+ UINT32 PamuBypENr;
+ UINT32 DmaCr1;
+ UINT8 Res60c[0x610-0x60c];
+ UINT32 DcfgCcsrGenSr1;
+ UINT32 DcfgCcsrGenSr2;
+ UINT32 DcfgCcsrGenSr3;
+ UINT32 DcfgCcsrGenSr4;
+ UINT32 DcfgCcsrGenCr1;
+ UINT32 DcfgCcsrGenCr2;
+ UINT32 DcfgCcsrGenCr3;
+ UINT32 DcfgCcsrGenCr4;
+ UINT32 DcfgCcsrGenCr5;
+ UINT32 DcfgCcsrGenCr6;
+ UINT32 DcfgCcsrGenCr7;
+ UINT8 Res63c[0x658-0x63c];
+ UINT32 DcfgCcsrcGenSr1;
+ UINT32 DcfgCcsrcGenSr0;
+ UINT8 Res660[0x678-0x660];
+ UINT32 DcfgCcsrcGenCr1;
+ UINT32 DcfgCcsrcGenCr0;
+ UINT8 Res680[0x700-0x680];
+ UINT32 DcfgCcsrSrIoPstecr;
+ UINT32 DcfgCcsrDcsrCr;
+ UINT8 Res708[0x740-0x708]; /* add more registers when needed */
+ UINT32 TpItyp[64]; /* Topology Initiator Type Register */
+ struct {
+ UINT32 Upper;
+ UINT32 Lower;
+ } TpCluster[16];
+ UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
+ UINT32 DcfgCcsrQmBmWarmRst;
+ UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
+ UINT32 DcfgCcsrReserved0;
+ UINT32 DcfgCcsrReserved1;
+} CCSR_GUR;
+
+/* Supplemental Configuration Unit */
+typedef struct {
+ UINT8 Res000[0x070-0x000];
+ UINT32 Usb1Prm1Cr;
+ UINT32 Usb1Prm2Cr;
+ UINT32 Usb1Prm3Cr;
+ UINT32 Usb2Prm1Cr;
+ UINT32 Usb2Prm2Cr;
+ UINT32 Usb2Prm3Cr;
+ UINT32 Usb3Prm1Cr;
+ UINT32 Usb3Prm2Cr;
+ UINT32 Usb3Prm3Cr;
+ UINT8 Res094[0x100-0x094];
+ UINT32 Usb2Icid;
+ UINT32 Usb3Icid;
+ UINT8 Res108[0x114-0x108];
+ UINT32 DmaIcid;
+ UINT32 SataIcid;
+ UINT32 Usb1Icid;
+ UINT32 QeIcid;
+ UINT32 SdhcIcid;
+ UINT32 EdmaIcid;
+ UINT32 EtrIcid;
+ UINT32 Core0SftRst;
+ UINT32 Core1SftRst;
+ UINT32 Core2SftRst;
+ UINT32 Core3SftRst;
+ UINT8 Res140[0x158-0x140];
+ UINT32 AltCBar;
+ UINT32 QspiCfg;
+ UINT8 Res160[0x180-0x160];
+ UINT32 DmaMcr;
+ UINT8 Res184[0x188-0x184];
+ UINT32 GicAlign;
+ UINT32 DebugIcid;
+ UINT8 Res190[0x1a4-0x190];
+ UINT32 SnpCnfGcr;
+#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
+#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
+#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
+#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
+#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
+#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
+#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
+#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
+#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
+#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
+ UINT8 Res1a8[0x1ac-0x1a8];
+ UINT32 IntpCr;
+ UINT8 Res1b0[0x204-0x1b0];
+ UINT32 CoreSrEnCr;
+ UINT8 Res208[0x220-0x208];
+ UINT32 RvBar00;
+ UINT32 RvBar01;
+ UINT32 RvBar10;
+ UINT32 RvBar11;
+ UINT32 RvBar20;
+ UINT32 RvBar21;
+ UINT32 RvBar30;
+ UINT32 RvBar31;
+ UINT32 LpmCsr;
+ UINT8 Res244[0x400-0x244];
+ UINT32 QspIdQScr;
+ UINT32 EcgTxcMcr;
+ UINT32 SdhcIoVSelCr;
+ UINT32 RcwPMuxCr0;
+ /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+ *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+ *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
+ Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
+#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
+ /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+ *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+ *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
+ Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
+#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
+ UINT32 UsbDrvVBusSelCr;
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
+ UINT32 UsbPwrFaultSelCr;
+#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
+#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
+#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
+#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
+#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
+#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
+ UINT32 UsbRefclkSelcr1;
+ UINT32 UsbRefclkSelcr2;
+ UINT32 UsbRefclkSelcr3;
+ UINT8 Res424[0x600-0x424];
+ UINT32 ScratchRw[4];
+ UINT8 Res610[0x680-0x610];
+ UINT32 CoreBCr;
+ UINT8 Res684[0x1000-0x684];
+ UINT32 Pex1MsiIr;
+ UINT32 Pex1MsiR;
+ UINT8 Res1008[0x2000-0x1008];
+ UINT32 Pex2;
+ UINT32 Pex2MsiR;
+ UINT8 Res2008[0x3000-0x2008];
+ UINT32 Pex3MsiIr;
+ UINT32 Pex3MsiR;
+} CCSR_SCFG;
+
+#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8003
+#define USB_PHY_RX_EQ_VAL_4 0x800b
+
+/*USB_PHY_SS memory map*/
+typedef struct {
+ UINT16 IpIdcodeLo;
+ UINT16 SupIdcodeHi;
+ UINT8 Res4[0x0006-0x0004];
+ UINT16 RtuneDebug;
+ UINT16 RtuneStat;
+ UINT16 SupSsPhase;
+ UINT16 SsFreq;
+ UINT8 ResE[0x0020-0x000e];
+ UINT16 Ateovrd;
+ UINT16 MpllOvrdInLo;
+ UINT8 Res24[0x0026-0x0024];
+ UINT16 SscOvrdIn;
+ UINT8 Res28[0x002A-0x0028];
+ UINT16 LevelOvrdIn;
+ UINT8 Res2C[0x0044-0x002C];
+ UINT16 ScopeCount;
+ UINT8 Res46[0x0060-0x0046];
+ UINT16 MpllLoopCtl;
+ UINT8 Res62[0x006C-0x0062];
+ UINT16 SscClkCntrl;
+ UINT8 Res6E[0x2002-0x006E];
+ UINT16 Lane0TxOvrdInHi;
+ UINT16 Lane0TxOvrdDrvLo;
+ UINT8 Res2006[0x200C-0x2006];
+ UINT16 Lane0RxOvrdInHi;
+ UINT8 Res200E[0x2022-0x200E];
+ UINT16 Lane0TxCmWaitTimeOvrd;
+ UINT8 Res2024[0x202A-0x2024];
+ UINT16 Lane0TxLbertCtl;
+ UINT16 Lane0RxLbertCtl;
+ UINT16 Lane0RxLbertErr;
+ UINT8 Res2030[0x205A-0x2030];
+ UINT16 Lane0TxAltBlock;
+} CCSR_USB_PHY;
+
+/* Clocking */
+typedef struct {
+ struct {
+ UINT32 ClkCnCSr; /* core cluster n clock control status */
+ UINT8 Res004[0x0c];
+ UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
+ UINT8 Res014[0x0c];
+ } ClkcSr[4];
+ UINT8 Res040[0x780]; /* 0x100 */
+ struct {
+ UINT32 PllCnGSr;
+ UINT8 Res804[0x1c];
+ } PllCgSr[NUM_CC_PLLS];
+ UINT8 Res840[0x1c0];
+ UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
+ UINT8 Resa04[0x1fc];
+ UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
+ UINT8 Resc04[0x1c];
+ UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
+ UINT8 Resc24[0x3dc];
+} CCSR_CLOCK;
+
+VOID
+GetSysInfo (
+ OUT SYS_INFO *
+ );
+
+UINT32
+EFIAPI
+GurRead (
+ IN UINTN Address
+ );
+
+#endif /* NXP_SOC_H_ */
diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h
new file mode 100644
index 000000000000..a934aaeff1f5
--- /dev/null
+++ b/Silicon/NXP/Include/DramInfo.h
@@ -0,0 +1,38 @@
+/** @file
+* Header defining the structure for Dram Information
+*
+* Copyright 2019 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef DRAM_INFO_H_
+#define DRAM_INFO_H_
+
+#include <Uefi/UefiBaseType.h>
+
+#define SMC_DRAM_BANK_INFO (0xC200FF12)
+
+typedef struct {
+ UINTN BaseAddress;
+ UINTN Size;
+} DRAM_REGION_INFO;
+
+typedef struct {
+ UINT32 NumOfDrams;
+ UINT32 Reserved;
+ DRAM_REGION_INFO DramRegion[3];
+} DRAM_INFO;
+
+EFI_STATUS
+GetDramBankInfo (
+ IN OUT DRAM_INFO *DramInfo
+ );
+
+VOID
+UpdateDpaaDram (
+ IN OUT DRAM_INFO *DramInfo
+ );
+
+#endif /* DRAM_INFO_H_ */
diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
new file mode 100644
index 000000000000..2d1c6f10f932
--- /dev/null
+++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h
@@ -0,0 +1,51 @@
+/** @file
+ The Header file of SerDes Module for LS1043A
+
+ Copyright 2017-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SOC_SERDES_H_
+#define SOC_SERDES_H_
+
+#ifdef CHASSIS2
+#include <Chassis2/LsSerDes.h>
+#endif
+
+SERDES_CONFIG SerDes1ConfigTbl[] = {
+ /* SerDes 1 */
+ {0x1555, {XfiFm1Mac9, Pcie1, Pcie2, Pcie3 } },
+ {0x2555, {Sgmii2500Fm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
+ {0x4555, {QsgmiiFm1A, Pcie1, Pcie2, Pcie3 } },
+ {0x4558, {QsgmiiFm1A, Pcie1, Pcie2, Sata } },
+ {0x1355, {XfiFm1Mac9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
+ {0x2355, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
+ {0x3335, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, Pcie3 } },
+ {0x3355, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
+ {0x3358, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Sata } },
+ {0x3555, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
+ {0x3558, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Sata } },
+ {0x7000, {Pcie1, Pcie1, Pcie1, Pcie1 } },
+ {0x9998, {Pcie1, Pcie2, Pcie3, Sata } },
+ {0x6058, {Pcie1, Pcie1, Pcie2, Sata } },
+ {0x1455, {XfiFm1Mac9, QsgmiiFm1A, Pcie2, Pcie3 } },
+ {0x2455, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
+ {0x2255, {Sgmii2500Fm1Dtsec9, Sgmii2500Fm1Dtsec2, Pcie2, Pcie3 } },
+ {0x3333, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
+ {0x1460, {XfiFm1Mac9, QsgmiiFm1A, Pcie3, Pcie3 } },
+ {0x2460, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
+ {0x3460, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
+ {0x3455, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
+ {0x9960, {Pcie1, Pcie2, Pcie3, Pcie3 } },
+ {0x2233, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 }},
+ {0x2533, {Sgmii2500Fm1Dtsec9, Pcie1, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
+ {}
+};
+
+SERDES_CONFIG *SerDesConfigTbl[] = {
+ SerDes1ConfigTbl
+};
+
+#endif /* SOC_SERDES_H_ */
diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
new file mode 100644
index 000000000000..99f6439d8f35
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/NxpChassis.h
@@ -0,0 +1,136 @@
+/** @file
+* Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+* Copyright 2017-2019 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef NXP_CHASSIS_H_
+#define NXP_CHASSIS_H_
+
+#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
+#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
+#define TP_ITYP_TYPE_ARM 0x0
+#define TP_ITYP_TYPE_PPC 0x1
+#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
+#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
+#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
+#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
+#define TP_INIT_PER_CLUSTER 4
+
+#define TY_ITYP_VERSION_A7 0x1
+#define TY_ITYP_VERSION_A53 0x2
+#define TY_ITYP_VERSION_A57 0x3
+#define TY_ITYP_VERSION_A72 0x4
+
+#define CPU_TYPE_ENTRY(N, V, NC) { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
+
+#define SVR_WO_E 0xFFFFFE
+#define SVR_LS1043A 0x879200
+#define SVR_LS1046A 0x870700
+#define SVR_LS2088A 0x870901
+
+#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
+#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
+#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
+#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
+
+#define MHZ 1000000
+
+typedef struct {
+ CHAR8 *Name;
+ UINT32 SocVer;
+ UINT32 NumCores;
+} CPU_TYPE;
+
+typedef struct {
+ UINTN CpuClk; /* CPU clock in Hz! */
+ UINTN BusClk;
+ UINTN MemClk;
+ UINTN PciClk;
+ UINTN SdhcClk;
+} SOC_CLOCK_INFO;
+
+/*
+ * Print Soc information
+ */
+VOID
+PrintSoc (
+ VOID
+ );
+
+/*
+ * Initialize Clock structure
+ */
+VOID
+ClockInit (
+ VOID
+ );
+
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+VOID
+SmmuInit (
+ VOID
+ );
+
+/*
+ * Print CPU information
+ */
+VOID
+PrintCpuInfo (
+ VOID
+ );
+
+/*
+ * Dump RCW (Reset Control Word) on console
+ */
+VOID
+PrintRCW (
+ VOID
+ );
+
+UINT32
+InitiatorType (
+ IN UINT32 Cluster,
+ IN UINTN InitId
+ );
+
+/*
+ * Return the mask for number of cores on this SOC.
+ */
+UINT32
+CpuMask (
+ VOID
+ );
+
+/*
+ * Return the number of cores on this SOC.
+ */
+UINTN
+CpuNumCores (
+ VOID
+ );
+
+/*
+ * Return the type of initiator for core/hardware accelerator for given core index.
+ */
+UINTN
+QoriqCoreToType (
+ IN UINTN Core
+ );
+
+/*
+ * Return the cluster of initiator for core/hardware accelerator for given core index.
+ */
+INT32
+QoriqCoreToCluster (
+ IN UINTN Core
+ );
+
+#endif /* NXP_CHASSIS_H_ */
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
new file mode 100644
index 000000000000..5dda6f8c2662
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -0,0 +1,498 @@
+/** @file
+ SoC specific Library containg functions to initialize various SoC components
+
+ Copyright 2017-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#ifdef CHASSIS2
+#include <Chassis2/NxpSoc.h>
+#elif CHASSIS3
+#include <Chassis3/NxpSoc.h>
+#endif
+#include <Library/ArmSmcLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include <DramInfo.h>
+#include "NxpChassis.h"
+
+/*
+ * Structure to list available SOCs.
+ * Name, Soc Version, Number of Cores
+ */
+STATIC CPU_TYPE mCpuTypeList[] = {
+ CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
+ CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
+ CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
+};
+
+UINT32
+EFIAPI
+GurRead (
+ IN UINTN Address
+ )
+{
+ if (FixedPcdGetBool (PcdGurBigEndian)) {
+ return SwapMmioRead32 (Address);
+ } else {
+ return MmioRead32 (Address);
+ }
+}
+
+/*
+ * Return the type of initiator (core or hardware accelerator)
+ */
+UINT32
+InitiatorType (
+ IN UINT32 Cluster,
+ IN UINTN InitId
+ )
+{
+ CCSR_GUR *GurBase;
+ UINT32 Idx;
+ UINT32 Type;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
+ Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
+
+ if (Type & TP_ITYP_AV_MASK) {
+ return Type;
+ }
+
+ return 0;
+}
+
+/*
+ * Return the mask for number of cores on this SOC.
+ */
+UINT32
+CpuMask (
+ VOID
+ )
+{
+ CCSR_GUR *GurBase;
+ UINTN ClusterIndex;
+ UINTN Count;
+ UINT32 Cluster;
+ UINT32 Type;
+ UINT32 Mask;
+ UINTN InitiatorIndex;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClusterIndex = 0;
+ Count = 0;
+ Mask = 0;
+
+ do {
+ Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+ for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+ Type = InitiatorType (Cluster, InitiatorIndex);
+ if (Type) {
+ if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) {
+ Mask |= 1 << Count;
+ }
+ Count++;
+ }
+ }
+ ClusterIndex++;
+ } while (CHECK_CLUSTER (Cluster));
+
+ return Mask;
+}
+
+/*
+ * Return the number of cores on this SOC.
+ */
+UINTN
+CpuNumCores (
+ VOID
+ )
+{
+ UINTN Count;
+ UINTN Num;
+
+ Count = 0;
+ Num = CpuMask ();
+
+ while (Num) {
+ Count += Num & 1;
+ Num >>= 1;
+ }
+
+ return Count;
+}
+
+/*
+ * Return core's cluster
+ */
+INT32
+QoriqCoreToCluster (
+ IN UINTN Core
+ )
+{
+ CCSR_GUR *GurBase;
+ UINTN ClusterIndex;
+ UINTN Count;
+ UINT32 Cluster;
+ UINT32 Type;
+ UINTN InitiatorIndex;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClusterIndex = 0;
+ Count = 0;
+ do {
+ Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+ for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+ Type = InitiatorType (Cluster, InitiatorIndex);
+ if (Type) {
+ if (Count == Core) {
+ return ClusterIndex;
+ }
+ Count++;
+ }
+ }
+ ClusterIndex++;
+ } while (CHECK_CLUSTER (Cluster));
+
+ return -1; // cannot identify the cluster
+}
+
+/*
+ * Return the type of core i.e. A53, A57 etc of inputted
+ * core number.
+ */
+UINTN
+QoriqCoreToType (
+ IN UINTN Core
+ )
+{
+ CCSR_GUR *GurBase;
+ UINTN ClusterIndex;
+ UINTN Count;
+ UINT32 Cluster;
+ UINT32 Type;
+ UINTN InitiatorIndex;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClusterIndex = 0;
+ Count = 0;
+
+ do {
+ Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+ for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+ Type = InitiatorType (Cluster, InitiatorIndex);
+ if (Type) {
+ if (Count == Core) {
+ return Type;
+ }
+ Count++;
+ }
+ }
+ ClusterIndex++;
+ } while (CHECK_CLUSTER (Cluster));
+
+ return EFI_NOT_FOUND; /* cannot identify the cluster */
+}
+
+STATIC
+UINTN
+CpuMaskNext (
+ IN UINTN Cpu,
+ IN UINTN Mask
+ )
+{
+ for (Cpu++; !((1 << Cpu) & Mask); Cpu++);
+
+ return Cpu;
+}
+
+/*
+ * Print CPU information
+ */
+VOID
+PrintCpuInfo (
+ VOID
+ )
+{
+ SYS_INFO SysInfo;
+ UINTN CoreIndex;
+ UINTN Core;
+ UINT32 Type;
+ UINT32 NumCpus;
+ UINT32 Mask;
+ CHAR8 *CoreName;
+
+ GetSysInfo (&SysInfo);
+ DEBUG ((DEBUG_INIT, "Clock Configuration:"));
+
+ NumCpus = CpuNumCores ();
+ Mask = CpuMask ();
+
+ for (CoreIndex = 0, Core = CpuMaskNext(-1, Mask);
+ CoreIndex < NumCpus;
+ CoreIndex++, Core = CpuMaskNext(Core, Mask))
+ {
+ if (!(CoreIndex % 3)) {
+ DEBUG ((DEBUG_INIT, "\n "));
+ }
+
+ Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
+ switch (Type) {
+ case TY_ITYP_VERSION_A7:
+ CoreName = "A7";
+ break;
+ case TY_ITYP_VERSION_A53:
+ CoreName = "A53";
+ break;
+ case TY_ITYP_VERSION_A57:
+ CoreName = "A57";
+ break;
+ case TY_ITYP_VERSION_A72:
+ CoreName = "A72";
+ break;
+ default:
+ CoreName = " Unknown Core ";
+ }
+ DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ",
+ Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ));
+ }
+
+ DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ));
+ DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ));
+
+ if (SysInfo.FreqFman[0] != 0) {
+ DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ));
+ }
+
+ DEBUG ((DEBUG_INIT, "\n"));
+}
+
+/*
+ * Return system bus frequency
+ */
+UINT64
+GetBusFrequency (
+ VOID
+ )
+{
+ SYS_INFO SocSysInfo;
+
+ GetSysInfo (&SocSysInfo);
+
+ return SocSysInfo.FreqSystemBus;
+}
+
+/*
+ * Return SDXC bus frequency
+ */
+UINT64
+GetSdxcFrequency (
+ VOID
+ )
+{
+ SYS_INFO SocSysInfo;
+
+ GetSysInfo (&SocSysInfo);
+
+ return SocSysInfo.FreqSdhc;
+}
+
+/*
+ * Print Soc information
+ */
+VOID
+PrintSoc (
+ VOID
+ )
+{
+ CHAR8 Buf[20];
+ CCSR_GUR *GurBase;
+ UINTN Count;
+ //
+ // Svr : System Version Register
+ //
+ UINTN Svr;
+ UINTN Ver;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+ Svr = GurRead ((UINTN)&GurBase->Svr);
+ Ver = SVR_SOC_VER (Svr);
+
+ for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
+ if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
+ AsciiStrCpyS (Buf, AsciiStrnLenS (mCpuTypeList[Count].Name, 7) + 1,
+ (CONST CHAR8 *)mCpuTypeList[Count].Name);
+
+ if (IS_E_PROCESSOR (Svr)) {
+ AsciiStrCatS (Buf,
+ (AsciiStrLen (Buf) + AsciiStrLen ((CONST CHAR8 *)"E") + 1),
+ (CONST CHAR8 *)"E");
+ }
+ break;
+ }
+ }
+
+ DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
+ Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
+
+ return;
+}
+
+/*
+ * Dump RCW (Reset Control Word) on console
+ */
+VOID
+PrintRCW (
+ VOID
+ )
+{
+ CCSR_GUR *Base;
+ UINTN Count;
+
+ Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+ /*
+ * Display the RCW, so that no one gets confused as to what RCW
+ * we're actually using for this boot.
+ */
+
+ DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):"));
+ for (Count = 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) {
+ UINT32 Rcw = SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]);
+
+ if ((Count % 4) == 0) {
+ DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4));
+ }
+
+ DEBUG ((DEBUG_INIT, " %08x", Rcw));
+ }
+
+ DEBUG ((DEBUG_INIT, "\n"));
+}
+
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+VOID
+SmmuInit (
+ VOID
+ )
+{
+ UINT32 Value;
+
+ /* set pagesize as 64K and ssmu-500 in bypass mode */
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
+ MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
+}
+
+/*
+ * Return current Soc Name form mCpuTypeList
+ */
+CHAR8 *
+GetSocName (
+ VOID
+ )
+{
+ UINT8 Count;
+ UINTN Svr;
+ UINTN Ver;
+ CCSR_GUR *GurBase;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+ Svr = GurRead ((UINTN)&GurBase->Svr);
+ Ver = SVR_SOC_VER (Svr);
+
+ for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
+ if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
+ return (CHAR8 *)mCpuTypeList[Count].Name;
+ }
+ }
+
+ return NULL;
+}
+
+UINTN
+GetDramSize (
+ IN VOID
+ )
+{
+ ARM_SMC_ARGS ArmSmcArgs;
+
+ ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
+ ArmSmcArgs.Arg1 = -1;
+
+ ArmCallSmc (&ArmSmcArgs);
+
+ if (ArmSmcArgs.Arg0) {
+ return 0;
+ } else {
+ return ArmSmcArgs.Arg1;
+ }
+}
+
+EFI_STATUS
+GetDramBankInfo (
+ IN OUT DRAM_INFO *DramInfo
+ )
+{
+ ARM_SMC_ARGS ArmSmcArgs;
+ UINT32 I;
+ UINTN DramSize;
+
+ DramSize = GetDramSize ();
+ DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize));
+
+ // Ensure DramSize has been set
+ ASSERT (DramSize != 0);
+
+ I = 0;
+
+ do {
+ ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
+ ArmSmcArgs.Arg1 = I;
+
+ ArmCallSmc (&ArmSmcArgs);
+ if (ArmSmcArgs.Arg0) {
+ if (I > 0) {
+ break;
+ } else {
+ ASSERT (ArmSmcArgs.Arg0 == 0);
+ }
+ }
+
+ DramInfo->DramRegion[I].BaseAddress = ArmSmcArgs.Arg1;
+ DramInfo->DramRegion[I].Size = ArmSmcArgs.Arg2;
+
+ DramSize -= DramInfo->DramRegion[I].Size;
+
+ DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n",
+ I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size));
+
+ I++;
+ } while (DramSize);
+
+ DramInfo->NumOfDrams = I;
+
+ DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDrams));
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
new file mode 100644
index 000000000000..bfb8b8cb339a
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -0,0 +1,162 @@
+/** @Soc.c
+ SoC specific Library containg functions to initialize various SoC components
+
+ Copyright 2017-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <NxpChassis.h>
+#include <Chassis2/NxpSoc.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+/**
+ Calculate the frequency of various controllers and
+ populate the passed structure with frequuencies.
+
+ @param PtrSysInfo Input structure to populate with
+ frequencies.
+**/
+VOID
+GetSysInfo (
+ OUT SYS_INFO *PtrSysInfo
+ )
+{
+ CCSR_GUR *GurBase;
+ CCSR_CLOCK *ClkBase;
+ UINTN CpuIndex;
+ UINT32 TempRcw;
+ UINT32 CPllSel;
+ UINT32 CplxPll;
+ CONST UINT8 CoreCplxPll[8] = {
+ [0] = 0, /* CC1 PPL / 1 */
+ [1] = 0, /* CC1 PPL / 2 */
+ [4] = 1, /* CC2 PPL / 1 */
+ [5] = 1, /* CC2 PPL / 2 */
+ };
+
+ CONST UINT8 CoreCplxPllDivisor[8] = {
+ [0] = 1, /* CC1 PPL / 1 */
+ [1] = 2, /* CC1 PPL / 2 */
+ [4] = 1, /* CC2 PPL / 1 */
+ [5] = 2, /* CC2 PPL / 2 */
+ };
+
+ UINTN PllCount;
+ UINTN FreqCPll[NUM_CC_PLLS];
+ UINTN PllRatio[NUM_CC_PLLS];
+ UINTN SysClk;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
+ SysClk = CLK_FREQ;
+
+ SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
+
+ PtrSysInfo->FreqSystemBus = SysClk;
+ PtrSysInfo->FreqDdrBus = SysClk;
+
+ //
+ // selects the platform clock:SYSCLK ratio and calculate
+ // system frequency
+ //
+ PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+ CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+ CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+ //
+ // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
+ //
+ PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+ CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
+ CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+
+ for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
+ PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
+ if (PllRatio[PllCount] > 4) {
+ FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
+ } else {
+ FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
+ }
+ }
+
+ //
+ // Calculate Core frequency
+ //
+ for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
+ CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) & 0xf;
+ CplxPll = CoreCplxPll[CPllSel];
+
+ PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
+ }
+
+ //
+ // Calculate FMAN frequency
+ //
+ TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
+ switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
+ case 2:
+ PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
+ break;
+ case 3:
+ PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
+ break;
+ case 4:
+ PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
+ break;
+ case 5:
+ PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
+ break;
+ case 6:
+ PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
+ break;
+ case 7:
+ PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
+ break;
+ default:
+ DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
+ break;
+ }
+ PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
+ PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
+}
+
+/**
+ Function to initialize SoC specific constructs
+ CPU Info
+ SoC Personality
+ Board Personality
+ RCW prints
+ **/
+VOID
+SocInit (
+ VOID
+ )
+{
+ SmmuInit ();
+
+ //
+ // Early init serial Port to get board information.
+ //
+ SerialPortInitialize ();
+ DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
+ (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
+
+ PrintCpuInfo ();
+
+ //
+ // Print Reset control Word
+ //
+ PrintRCW ();
+ PrintSoc ();
+
+ return;
+}
diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocLib/SerDes.c
new file mode 100644
index 000000000000..b9909d922138
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/SerDes.c
@@ -0,0 +1,268 @@
+/** SerDes.c
+ Provides the basic interfaces for SerDes Module
+
+ Copyright 2017-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifdef CHASSIS2
+#include <Chassis2/LsSerDes.h>
+#include <Chassis2/NxpSoc.h>
+#elif CHASSIS3
+#include <Chassis3/LsSerDes.h>
+#include <Chassis3/NxpSoc.h>
+#endif
+#include <Library/DebugLib.h>
+#include <SocSerDes.h>
+#include <Uefi.h>
+
+/**
+ Function to get serdes Lane protocol corresponding to
+ serdes protocol.
+
+ @param SerDes Serdes number.
+ @param Cfg Serdes Protocol.
+ @param Lane Serdes Lane number.
+
+ @return Serdes Lane protocol.
+
+**/
+STATIC
+SERDES_PROTOCOL
+GetSerDesPrtcl (
+ IN INTN SerDes,
+ IN INTN Cfg,
+ IN INTN Lane
+ )
+{
+ SERDES_CONFIG *Config;
+
+ if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
+ return 0;
+ }
+
+ Config = SerDesConfigTbl[SerDes];
+ while (Config->Protocol) {
+ if (Config->Protocol == Cfg) {
+ return Config->SrdsLane[Lane];
+ }
+ Config++;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to check if inputted protocol is a valid serdes protocol.
+
+ @param SerDes Serdes number.
+ @param Prtcl Serdes Protocol to be verified.
+
+ @return EFI_INVALID_PARAMETER Input parameter in invalid.
+ @return EFI_NOT_FOUND Serdes Protocol not a valid protocol.
+ @return EFI_SUCCESS Serdes Protocol is a valid protocol.
+
+**/
+STATIC
+EFI_STATUS
+CheckSerDesPrtclValid (
+ IN INTN SerDes,
+ IN UINT32 Prtcl
+ )
+{
+ SERDES_CONFIG *Config;
+ INTN Cnt;
+
+ if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Config = SerDesConfigTbl[SerDes];
+ while (Config->Protocol) {
+ if (Config->Protocol == Prtcl) {
+ DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl));
+ break;
+ }
+ Config++;
+ }
+
+ if (!Config->Protocol) {
+ return EFI_NOT_FOUND;
+ }
+
+ for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
+ if (Config->SrdsLane[Cnt] != None) {
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+ Function to fill serdes map information.
+
+ @param Srds Serdes number.
+ @param SerdesProtocolMask Serdes Protocol Mask.
+ @param SerdesProtocolShift Serdes Protocol shift value.
+ @param SerDesPrtclMap Pointer to Serdes Protocol map.
+
+**/
+STATIC
+VOID
+LSSerDesMap (
+ IN UINT32 Srds,
+ IN UINT32 SerdesProtocolMask,
+ IN UINT32 SerdesProtocolShift,
+ OUT UINT64 *SerDesPrtclMap
+ )
+{
+ CCSR_GUR *Gur;
+ UINT32 SrdsProt;
+ INTN Lane;
+ UINT32 Flag;
+
+ Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ *SerDesPrtclMap = 0x0;
+ Flag = 0;
+
+ SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
+ SrdsProt >>= SerdesProtocolShift;
+
+ DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
+ Srds + 1, SrdsProt, SrdsProt));
+
+ if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
+ DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
+ Srds + 1, SrdsProt));
+ Flag++;
+ }
+
+ for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
+ SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
+ if (LanePrtcl >= SerdesPrtclCount) {
+ DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
+ Flag++;
+ } else {
+ *SerDesPrtclMap |= (1u << LanePrtcl);
+ }
+ }
+
+ if (Flag) {
+ DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
+ }
+}
+
+/**
+ Get lane protocol on provided serdes lane and execute callback function.
+
+ @param Srds Serdes number.
+ @param SerdesProtocolMask Mask to get Serdes Protocol for Srds
+ @param SerdesProtocolShift Shift value to get Serdes Protocol for Srds.
+ @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
+ @param Arg Pointer to Arguments to be passed to callback function.
+
+**/
+STATIC
+VOID
+SerDesInstanceProbeLanes (
+ IN UINT32 Srds,
+ IN UINT32 SerdesProtocolMask,
+ IN UINT32 SerdesProtocolShift,
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ )
+{
+
+ CCSR_GUR *Gur;
+ UINT32 SrdsProt;
+ INTN Lane;
+
+ Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
+
+ SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
+ SrdsProt >>= SerdesProtocolShift;
+
+ /*
+ * Invoke callback for all lanes in the SerDes instance:
+ */
+ for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
+ SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
+ if ((LanePrtcl >= SerdesPrtclCount) || (LanePrtcl < None)) {
+ DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
+ } else if (LanePrtcl != None) {
+ SerDesLaneProbeCallback (LanePrtcl, Arg);
+ }
+ }
+}
+
+/**
+ Probe all serdes lanes for lane protocol and execute provided callback function.
+
+ @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
+ @param Arg Pointer to Arguments to be passed to callback function.
+
+**/
+VOID
+SerDesProbeLanes (
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ )
+{
+ SerDesInstanceProbeLanes (Srds1,
+ RCWSR_SRDS1_PRTCL_MASK,
+ RCWSR_SRDS1_PRTCL_SHIFT,
+ SerDesLaneProbeCallback,
+ Arg);
+
+ if (PcdGetBool (PcdSerdes2Enabled)) {
+ SerDesInstanceProbeLanes (Srds2,
+ RCWSR_SRDS2_PRTCL_MASK,
+ RCWSR_SRDS2_PRTCL_SHIFT,
+ SerDesLaneProbeCallback,
+ Arg);
+ }
+}
+
+/**
+ Function to return Serdes protocol map for all serdes available on board.
+
+ @param SerDesPrtclMap Pointer to Serdes protocl map.
+
+**/
+VOID
+GetSerdesProtocolMaps (
+ OUT UINT64 *SerDesPrtclMap
+ )
+{
+ LSSerDesMap (Srds1,
+ RCWSR_SRDS1_PRTCL_MASK,
+ RCWSR_SRDS1_PRTCL_SHIFT,
+ SerDesPrtclMap);
+
+ if (PcdGetBool (PcdSerdes2Enabled)) {
+ LSSerDesMap (Srds2,
+ RCWSR_SRDS2_PRTCL_MASK,
+ RCWSR_SRDS2_PRTCL_SHIFT,
+ SerDesPrtclMap);
+ }
+
+}
+
+BOOLEAN
+IsSerDesLaneProtocolConfigured (
+ IN UINT64 SerDesPrtclMap,
+ IN SERDES_PROTOCOL Device
+ )
+{
+ if ((Device >= SerdesPrtclCount) || (Device < None)) {
+ ASSERT ((Device > None) && (Device < SerdesPrtclCount));
+ DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device));
+ }
+
+ return (SerDesPrtclMap & (1u << Device)) != 0 ;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v2 04/11] Silicon/NXP : Add support for DUART library
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
` (2 preceding siblings ...)
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 03/11] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
@ 2019-11-21 16:25 ` Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 05/11] Silicon/NXP: Add support for I2c driver Meenakshi Aggarwal
` (7 subsequent siblings)
11 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-11-21 16:25 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, devel
Cc: v.sethi, Meenakshi Aggarwal
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 34 ++
Silicon/NXP/Library/DUartPortLib/DUart.h | 122 +++++++
Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 364 ++++++++++++++++++++
3 files changed, 520 insertions(+)
diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
new file mode 100644
index 000000000000..7a2fa619b027
--- /dev/null
+++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
@@ -0,0 +1,34 @@
+# DUartPortLib.inf
+#
+# Component description file for DUartPortLib module
+#
+# Copyright (c) 2013, Freescale Ltd. All rights reserved.
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = DUartPortLib
+ FILE_GUID = c42dfe79-8de5-429e-a055-2d0a58591498
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialPortLib
+
+[Sources.common]
+ DUartPortLib.c
+
+[LibraryClasses]
+ PcdLib
+ SocLib
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
diff --git a/Silicon/NXP/Library/DUartPortLib/DUart.h b/Silicon/NXP/Library/DUartPortLib/DUart.h
new file mode 100644
index 000000000000..c71e2ce55d1d
--- /dev/null
+++ b/Silicon/NXP/Library/DUartPortLib/DUart.h
@@ -0,0 +1,122 @@
+/** DUart.h
+* Header defining the DUART constants (Base addresses, sizes, flags)
+*
+* Based on Serial I/O Port library headers available in PL011Uart.h
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef DUART_H_
+#define DUART_H_
+
+// FIFO Control Register
+#define DUART_FCR_FIFO_EN 0x01 /* Fifo enable */
+#define DUART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
+#define DUART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
+#define DUART_FCR_DMA_SELECT 0x08 /* For DMA applications */
+#define DUART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
+#define DUART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
+#define DUART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
+#define DUART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
+#define DUART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
+#define DUART_FCR_RXSR 0x02 /* Receiver soft reset */
+#define DUART_FCR_TXSR 0x04 /* Transmitter soft reset */
+
+// Modem Control Register
+#define DUART_MCR_DTR 0x01 /* Reserved */
+#define DUART_MCR_RTS 0x02 /* RTS */
+#define DUART_MCR_OUT1 0x04 /* Reserved */
+#define DUART_MCR_OUT2 0x08 /* Reserved */
+#define DUART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define DUART_MCR_AFE 0x20 /* AFE (Auto Flow Control) */
+#define DUART_MCR_DMA_EN 0x04
+#define DUART_MCR_TX_DFR 0x08
+
+// Line Control Register
+/*
+* Note: if the word length is 5 bits (DUART_LCR_WLEN5), then setting
+* DUART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+*/
+#define DUART_LCR_WLS_MSK 0x03 /* character length select mask */
+#define DUART_LCR_WLS_5 0x00 /* 5 bit character length */
+#define DUART_LCR_WLS_6 0x01 /* 6 bit character length */
+#define DUART_LCR_WLS_7 0x02 /* 7 bit character length */
+#define DUART_LCR_WLS_8 0x03 /* 8 bit character length */
+#define DUART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
+#define DUART_LCR_PEN 0x08 /* Parity eneble */
+#define DUART_LCR_EPS 0x10 /* Even Parity Select */
+#define DUART_LCR_STKP 0x20 /* Stick Parity */
+#define DUART_LCR_SBRK 0x40 /* Set Break */
+#define DUART_LCR_BKSE 0x80 /* Bank select enable */
+#define DUART_LCR_DLAB 0x80 /* Divisor latch access bit */
+
+// Line Status Register
+#define DUART_LSR_DR 0x01 /* Data ready */
+#define DUART_LSR_OE 0x02 /* Overrun */
+#define DUART_LSR_PE 0x04 /* Parity error */
+#define DUART_LSR_FE 0x08 /* Framing error */
+#define DUART_LSR_BI 0x10 /* Break */
+#define DUART_LSR_THRE 0x20 /* Xmit holding register empty */
+#define DUART_LSR_TEMT 0x40 /* Xmitter empty */
+#define DUART_LSR_ERR 0x80 /* Error */
+
+// Modem Status Register
+#define DUART_MSR_DCTS 0x01 /* Delta CTS */
+#define DUART_MSR_DDSR 0x02 /* Reserved */
+#define DUART_MSR_TERI 0x04 /* Reserved */
+#define DUART_MSR_DDCD 0x08 /* Reserved */
+#define DUART_MSR_CTS 0x10 /* Clear to Send */
+#define DUART_MSR_DSR 0x20 /* Reserved */
+#define DUART_MSR_RI 0x40 /* Reserved */
+#define DUART_MSR_DCD 0x80 /* Reserved */
+
+// Interrupt Identification Register
+#define DUART_IIR_NO_INT 0x01 /* No interrupts pending */
+#define DUART_IIR_ID 0x06 /* Mask for the interrupt ID */
+#define DUART_IIR_MSI 0x00 /* Modem status interrupt */
+#define DUART_IIR_THRI 0x02 /* Transmitter holding register empty */
+#define DUART_IIR_RDI 0x04 /* Receiver data interrupt */
+#define DUART_IIR_RLSI 0x06 /* Receiver line status interrupt */
+
+// Interrupt Enable Register
+#define DUART_IER_MSI 0x08 /* Enable Modem status interrupt */
+#define DUART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
+#define DUART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
+#define DUART_IER_RDI 0x01 /* Enable receiver data interrupt */
+
+// LCR defaults
+#define DUART_LCR_8N1 0x03
+#define DUART_LCRVAL DUART_LCR_8N1 /* 8 data, 1 stop, no parity */
+#define DUART_MCRVAL (DUART_MCR_DTR | \
+ DUART_MCR_RTS) /* RTS/DTR */
+#define DUART_FCRVAL (DUART_FCR_FIFO_EN | \
+ DUART_FCR_RXSR | \
+ DUART_FCR_TXSR) /* Clear & enable FIFOs */
+
+#define URBR 0x0
+#define UTHR 0x0
+#define UDLB 0x0
+#define UDMB 0x1
+#define UIER 0x1
+#define UIIR 0x2
+#define UFCR 0x2
+#define UAFR 0x2
+#define ULCR 0x3
+#define UMCR 0x4
+#define ULSR 0x5
+#define UMSR 0x6
+#define USCR 0x7
+#define UDSR 0x10
+
+extern
+UINT64
+GetBusFrequency (
+ VOID
+ );
+
+#endif /* DUART_H_ */
diff --git a/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
new file mode 100644
index 000000000000..c3c738d3cca8
--- /dev/null
+++ b/Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
@@ -0,0 +1,364 @@
+/** DuartPortLib.c
+ DUART (NS16550) library functions
+
+ Based on Serial I/O Port library functions available in PL011SerialPortLib.c
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2012 - 2013, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+ Copyright 2017 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+
+#include "DUart.h"
+
+STATIC CONST UINT32 mInvalidControlBits = (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE | \
+ EFI_SERIAL_DATA_TERMINAL_READY);
+
+/**
+ Assert or deassert the control signals on a serial port.
+ The following control signals are set according their bit settings :
+ . Request to Send
+ . Data Terminal Ready
+
+ @param[in] Control The following bits are taken into account :
+ . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
+ "Request To Send" control signal if this bit is
+ equal to one/zero.
+ . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
+ the "Data Terminal Ready" control signal if this
+ bit is equal to one/zero.
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
+ the hardware loopback if this bit is equal to
+ one/zero.
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
+ disable the hardware flow control based on CTS (Clear
+ To Send) and RTS (Ready To Send) control signals.
+
+ @retval EFI_SUCCESS The new control bits were set on the device.
+ @retval EFI_UNSUPPORTED The device does not support this operation.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortSetControl (
+ IN UINT32 Control
+ )
+{
+ UINT32 McrBits;
+ UINTN UartBase;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ if (Control & (mInvalidControlBits)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ McrBits = MmioRead8 (UartBase + UMCR);
+
+ if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
+ McrBits |= DUART_MCR_RTS;
+ } else {
+ McrBits &= ~DUART_MCR_RTS;
+ }
+
+ if (Control & EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE) {
+ McrBits |= DUART_MCR_LOOP;
+ } else {
+ McrBits &= ~DUART_MCR_LOOP;
+ }
+
+ if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
+ McrBits |= DUART_MCR_AFE;
+ } else {
+ McrBits &= ~DUART_MCR_AFE;
+ }
+
+ MmioWrite32 (UartBase + UMCR, McrBits);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Retrieve the status of the control bits on a serial device.
+
+ @param[out] Control Status of the control bits on a serial device :
+
+ . EFI_SERIAL_DATA_CLEAR_TO_SEND,
+ EFI_SERIAL_DATA_SET_READY,
+ EFI_SERIAL_RING_INDICATE,
+ EFI_SERIAL_CARRIER_DETECT,
+ EFI_SERIAL_REQUEST_TO_SEND,
+ EFI_SERIAL_DATA_TERMINAL_READY
+ are all related to the DTE (Data Terminal Equipment)
+ and DCE (Data Communication Equipment) modes of
+ operation of the serial device.
+ . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
+ receive buffer is empty, 0 otherwise.
+ . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
+ transmit buffer is empty, 0 otherwise.
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
+ the hardware loopback is enabled (the ouput feeds the
+ receive buffer), 0 otherwise.
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one if
+ a loopback is accomplished by software, 0 otherwise.
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
+ one if the hardware flow control based on CTS (Clear
+ To Send) and RTS (Ready To Send) control signals is
+ enabled, 0 otherwise.
+
+ @retval EFI_SUCCESS The control bits were read from the serial device.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortGetControl (
+ OUT UINT32 *Control
+ )
+{
+ UINT32 MsrRegister;
+ UINT32 McrRegister;
+ UINT32 LsrRegister;
+ UINTN UartBase;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ MsrRegister = MmioRead8 (UartBase + UMSR);
+ McrRegister = MmioRead8 (UartBase + UMCR);
+ LsrRegister = MmioRead8 (UartBase + ULSR);
+
+ *Control = 0;
+
+ if ((MsrRegister & DUART_MSR_CTS) == DUART_MSR_CTS) {
+ *Control |= EFI_SERIAL_CLEAR_TO_SEND;
+ }
+
+ if ((McrRegister & DUART_MCR_RTS) == DUART_MCR_RTS) {
+ *Control |= EFI_SERIAL_REQUEST_TO_SEND;
+ }
+
+ if ((LsrRegister & DUART_LSR_TEMT) == DUART_LSR_TEMT) {
+ *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+ }
+
+ if ((McrRegister & DUART_MCR_AFE) == DUART_MCR_AFE) {
+ *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
+ }
+
+ if ((McrRegister & DUART_MCR_LOOP) == DUART_MCR_LOOP) {
+ *Control |= EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/*
+ * Return Baud divisor on basis of Baudrate
+ */
+UINT32
+CalculateBaudDivisor (
+ IN UINT64 BaudRate
+ )
+{
+ UINTN DUartClk;
+ UINTN FreqSystemBus;
+
+ FreqSystemBus = GetBusFrequency ();
+ DUartClk = FreqSystemBus/PcdGet32(PcdPlatformFreqDiv);
+
+ return ((DUartClk)/(BaudRate * 16));
+}
+
+/*
+ Initialise the serial port to the specified settings.
+ All unspecified settings will be set to the default values.
+
+ @return Always return EFI_SUCCESS or EFI_INVALID_PARAMETER.
+
+ **/
+VOID
+EFIAPI
+DuartInitializePort (
+ IN UINT64 BaudRate
+ )
+{
+ UINTN UartBase;
+ UINT32 BaudDivisor;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+ BaudDivisor = CalculateBaudDivisor (BaudRate);
+
+
+ while (!(MmioRead8 (UartBase + ULSR) & DUART_LSR_TEMT));
+
+ //
+ // Enable and assert interrupt when new data is available on
+ // external device,
+ // setup data format, setup baud divisor
+ //
+ MmioWrite8 (UartBase + UIER, 0x1);
+ MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
+ MmioWrite8 (UartBase + UDLB, 0);
+ MmioWrite8 (UartBase + UDMB, 0);
+ MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
+ MmioWrite8 (UartBase + UMCR, DUART_MCRVAL);
+ MmioWrite8 (UartBase + UFCR, DUART_FCRVAL);
+ MmioWrite8 (UartBase + ULCR, DUART_LCR_BKSE | DUART_LCRVAL);
+ MmioWrite8 (UartBase + UDLB, BaudDivisor & 0xff);
+ MmioWrite8 (UartBase + UDMB, (BaudDivisor >> 8) & 0xff);
+ MmioWrite8 (UartBase + ULCR, DUART_LCRVAL);
+
+ return;
+}
+
+/**
+ Programmed hardware of Serial port.
+
+ @return Always return EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ UINT64 BaudRate;
+ BaudRate = (UINTN)PcdGet64 (PcdUartDefaultBaudRate);
+
+
+ DuartInitializePort (BaudRate);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write data to serial device.
+
+ @param Buffer Point of data buffer which need to be written.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Write data failed.
+ @retval !0 Actual number of bytes written to serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
+{
+ UINT8 *Final;
+ UINTN UartBase;
+
+ Final = &Buffer[NumberOfBytes];
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ while (Buffer < Final) {
+ while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_THRE) == 0);
+ MmioWrite8 (UartBase + UTHR, *Buffer++);
+ }
+
+ return NumberOfBytes;
+}
+
+/**
+ Read data from serial device and save the data in buffer.
+
+ @param Buffer Point of data buffer which need to be written.
+ @param NumberOfBytes Number of output bytes which are cached in Buffer.
+
+ @retval 0 Read data failed.
+ @retval !0 Actual number of bytes read from serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
+{
+ UINTN Count;
+ UINTN UartBase;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
+ // Loop while waiting for a new char(s) to arrive in the
+ // RxFIFO
+ while ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) == 0);
+
+ *Buffer = MmioRead8 (UartBase + URBR);
+ }
+
+ return NumberOfBytes;
+}
+
+/**
+ Check to see if any data is available to be read from the debug device.
+
+ @retval EFI_SUCCESS At least one byte of data is available to be read
+ @retval EFI_NOT_READY No data is available to be read
+ @retval EFI_DEVICE_ERROR The serial device is not functioning properly
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+ UINTN UartBase;
+
+ UartBase = (UINTN)PcdGet64 (PcdSerialRegisterBase);
+
+ return ((MmioRead8 (UartBase + ULSR) & DUART_LSR_DR) != 0);
+}
+
+/**
+ Set new attributes to LS1043a.
+
+ @param BaudRate The baud rate of the serial device. If the baud rate is not supported,
+ the speed will be reduced down to the nearest supported one and the
+ variable's value will be updated accordingly.
+ @param ReceiveFifoDepth The number of characters the device will buffer on input. If the specified
+ value is not supported, the variable's value will be reduced down to the
+ nearest supported one.
+ @param Timeout If applicable, the number of microseconds the device will wait
+ before timing out a Read or a Write operation.
+ @param Parity If applicable, this is the EFI_PARITY_TYPE that is computed or checked
+ as each character is transmitted or received. If the device does not
+ support parity, the value is the default parity value.
+ @param DataBits The number of data bits in each character
+ @param StopBits If applicable, the EFI_STOP_BITS_TYPE number of stop bits per character.
+ If the device does not support stop bits, the value is the default stop
+ bit value.
+
+ @retval EFI_SUCCESS All attributes were set correctly on the serial device.
+
+**/
+EFI_STATUS
+EFIAPI
+SerialPortSetAttributes (
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+ )
+{
+ DuartInitializePort (*BaudRate);
+
+ return EFI_SUCCESS;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v2 05/11] Silicon/NXP: Add support for I2c driver
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
` (3 preceding siblings ...)
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 04/11] Silicon/NXP : Add support for DUART library Meenakshi Aggarwal
@ 2019-11-21 16:25 ` Meenakshi Aggarwal
2019-11-26 17:00 ` Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 06/11] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi Aggarwal
` (6 subsequent siblings)
11 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-11-21 16:25 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, devel
Cc: v.sethi, Meenakshi Aggarwal
I2C driver produces gEfiI2cMasterProtocolGuid which can be
used by other modules.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Notes:
v2:
- indentation correction
- STATIC variable with 'm' prefix
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 58 ++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 100 +++
Silicon/NXP/Drivers/I2cDxe/ComponentName.c | 179 +++++
Silicon/NXP/Drivers/I2cDxe/DriverBinding.c | 235 +++++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 690 ++++++++++++++++++++
5 files changed, 1262 insertions(+)
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
new file mode 100644
index 000000000000..0c0bf63bb2e2
--- /dev/null
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
@@ -0,0 +1,58 @@
+# @file
+#
+# Component description file for I2c driver
+#
+# Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017-2019 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = I2cDxe
+ FILE_GUID = 5f2927ba-1b04-4d5f-8bef-2b50c635d1e7
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = I2cDxeEntryPoint
+ UNLOAD = I2cDxeUnload
+
+[Sources.common]
+ ComponentName.c
+ DriverBinding.c
+ I2cDxe.c
+
+[LibraryClasses]
+ ArmLib
+ BaseMemoryLib
+ DevicePathLib
+ IoLib
+ MemoryAllocationLib
+ PcdLib
+ SocLib
+ TimerLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Guids]
+ gNxpNonDiscoverableI2cMasterGuid
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[Protocols]
+ gEdkiiNonDiscoverableDeviceProtocolGuid ## TO_START
+ gEfiI2cMasterProtocolGuid ## BY_START
+
+[Pcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
+
+[Depex]
+ TRUE
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
new file mode 100644
index 000000000000..02a29a5cf2b9
--- /dev/null
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
@@ -0,0 +1,100 @@
+/** I2cDxe.h
+ Header defining the constant, base address amd function for I2C controller
+
+ Copyright 2017-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef I2C_DXE_H_
+#define I2C_DXE_H_
+
+#include <Library/UefiLib.h>
+#include <Uefi.h>
+
+#include <Protocol/I2cMaster.h>
+#include <Protocol/NonDiscoverableDevice.h>
+
+#define I2C_CR_IIEN (1 << 6)
+#define I2C_CR_MSTA (1 << 5)
+#define I2C_CR_MTX (1 << 4)
+#define I2C_CR_TX_NO_AK (1 << 3)
+#define I2C_CR_RSTA (1 << 2)
+
+#define I2C_SR_ICF (1 << 7)
+#define I2C_SR_IBB (1 << 5)
+#define I2C_SR_IAL (1 << 4)
+#define I2C_SR_IIF (1 << 1)
+#define I2C_SR_RX_NO_AK (1 << 0)
+
+#define I2C_CR_IEN (0 << 7)
+#define I2C_CR_IDIS (1 << 7)
+#define I2C_SR_IIF_CLEAR (1 << 1)
+
+#define BUS_IDLE (0 | (I2C_SR_IBB << 8))
+#define BUS_BUSY (I2C_SR_IBB | (I2C_SR_IBB << 8))
+#define IIF (I2C_SR_IIF | (I2C_SR_IIF << 8))
+
+#define I2C_FLAG_WRITE 0x0
+
+#define I2C_STATE_RETRIES 50000
+
+#define RETRY_COUNT 3
+
+#define NXP_I2C_SIGNATURE SIGNATURE_32 ('N', 'I', '2', 'C')
+#define NXP_I2C_FROM_THIS(a) CR ((a), NXP_I2C_MASTER, \
+ I2cMaster, NXP_I2C_SIGNATURE)
+
+extern EFI_COMPONENT_NAME2_PROTOCOL gNxpI2cDriverComponentName2;
+
+#pragma pack(1)
+typedef struct {
+ VENDOR_DEVICE_PATH Vendor;
+ UINT64 MmioBase;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} NXP_I2C_DEVICE_PATH;
+#pragma pack()
+
+typedef struct {
+ UINT32 Signature;
+ EFI_I2C_MASTER_PROTOCOL I2cMaster;
+ NXP_I2C_DEVICE_PATH DevicePath;
+ NON_DISCOVERABLE_DEVICE *Dev;
+} NXP_I2C_MASTER;
+
+/**
+ Record defining i2c registers
+**/
+typedef struct {
+ UINT8 I2cAdr;
+ UINT8 I2cFdr;
+ UINT8 I2cCr;
+ UINT8 I2cSr;
+ UINT8 I2cDr;
+} I2C_REGS;
+
+typedef struct {
+ UINT16 SCLDivider;
+ UINT16 BusClockRate;
+} CLK_DIV;
+
+extern
+UINT64
+GetBusFrequency (
+ VOID
+ );
+
+EFI_STATUS
+NxpI2cInit (
+ IN EFI_HANDLE DriverBindingHandle,
+ IN EFI_HANDLE ControllerHandle
+ );
+
+EFI_STATUS
+NxpI2cRelease (
+ IN EFI_HANDLE DriverBindingHandle,
+ IN EFI_HANDLE ControllerHandle
+ );
+
+#endif //I2C_DXE_H_
diff --git a/Silicon/NXP/Drivers/I2cDxe/ComponentName.c b/Silicon/NXP/Drivers/I2cDxe/ComponentName.c
new file mode 100644
index 000000000000..a71d75c2913a
--- /dev/null
+++ b/Silicon/NXP/Drivers/I2cDxe/ComponentName.c
@@ -0,0 +1,179 @@
+/** @file
+
+ Copyright 2018-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "I2cDxe.h"
+
+STATIC EFI_UNICODE_STRING_TABLE mNxpI2cDriverNameTable[] = {
+ {
+ "en",
+ (CHAR16 *)L"Nxp I2C Driver"
+ },
+ { }
+};
+
+STATIC EFI_UNICODE_STRING_TABLE mNxpI2cControllerNameTable[] = {
+ {
+ "en",
+ (CHAR16 *)L"Nxp I2C Controller"
+ },
+ { }
+};
+
+/**
+ Retrieves a Unicode string that is the user readable name of the driver.
+
+ This function retrieves the user readable name of a driver in the form of a
+ Unicode string. If the driver specified by This has a user readable name in
+ the language specified by Language, then a pointer to the driver name is
+ returned in DriverName, and EFI_SUCCESS is returned. If the driver specified
+ by This does not support the language specified by Language,
+ then EFI_UNSUPPORTED is returned.
+
+ @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+ EFI_COMPONENT_NAME_PROTOCOL instance.
+
+ @param Language[in] A pointer to a Null-terminated ASCII string
+ array indicating the language. This is the
+ language of the driver name that the caller is
+ requesting, and it must match one of the
+ languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up
+ to the driver writer. Language is specified
+ in RFC 4646 or ISO 639-2 language code format.
+
+ @param DriverName[out] A pointer to the Unicode string to return.
+ This Unicode string is the name of the
+ driver specified by This in the language
+ specified by Language.
+
+ @retval EFI_SUCCESS The Unicode string for the Driver specified by
+ This and the language specified by Language was
+ returned in DriverName.
+
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+
+ @retval EFI_INVALID_PARAMETER DriverName is NULL.
+
+ @retval EFI_UNSUPPORTED The driver specified by This does not support
+ the language specified by Language.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+NxpI2cGetDriverName (
+ IN EFI_COMPONENT_NAME2_PROTOCOL *This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
+ )
+{
+ return LookupUnicodeString2 (Language,
+ This->SupportedLanguages,
+ mNxpI2cDriverNameTable,
+ DriverName,
+ FALSE);
+}
+
+/**
+ Retrieves a Unicode string that is the user readable name of the controller
+ that is being managed by a driver.
+
+ This function retrieves the user readable name of the controller specified by
+ ControllerHandle and ChildHandle in the form of a Unicode string. If the
+ driver specified by This has a user readable name in the language specified by
+ Language, then a pointer to the controller name is returned in ControllerName,
+ and EFI_SUCCESS is returned. If the driver specified by This is not currently
+ managing the controller specified by ControllerHandle and ChildHandle,
+ then EFI_UNSUPPORTED is returned. If the driver specified by This does not
+ support the language specified by Language, then EFI_UNSUPPORTED is returned.
+
+ @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or
+ EFI_COMPONENT_NAME_PROTOCOL instance.
+
+ @param ControllerHandle[in] The handle of a controller that the driver
+ specified by This is managing. This handle
+ specifies the controller whose name is to be
+ returned.
+
+ @param ChildHandle[in] The handle of the child controller to retrieve
+ the name of. This is an optional parameter that
+ may be NULL. It will be NULL for device
+ drivers. It will also be NULL for a bus drivers
+ that wish to retrieve the name of the bus
+ controller. It will not be NULL for a bus
+ driver that wishes to retrieve the name of a
+ child controller.
+
+ @param Language[in] A pointer to a Null-terminated ASCII string
+ array indicating the language. This is the
+ language of the driver name that the caller is
+ requesting, and it must match one of the
+ languages specified in SupportedLanguages. The
+ number of languages supported by a driver is up
+ to the driver writer. Language is specified in
+ RFC 4646 or ISO 639-2 language code format.
+
+ @param ControllerName[out] A pointer to the Unicode string to return.
+ This Unicode string is the name of the
+ controller specified by ControllerHandle and
+ ChildHandle in the language specified by
+ Language from the point of view of the driver
+ specified by This.
+
+ @retval EFI_SUCCESS The Unicode string for the user readable name in
+ the language specified by Language for the
+ driver specified by This was returned in
+ DriverName.
+
+ @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
+
+ @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid
+ EFI_HANDLE.
+
+ @retval EFI_INVALID_PARAMETER Language is NULL.
+
+ @retval EFI_INVALID_PARAMETER ControllerName is NULL.
+
+ @retval EFI_UNSUPPORTED The driver specified by This is not currently
+ managing the controller specified by
+ ControllerHandle and ChildHandle.
+
+ @retval EFI_UNSUPPORTED The driver specified by This does not support
+ the language specified by Language.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+NxpI2cGetControllerName (
+ IN EFI_COMPONENT_NAME2_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
+ )
+{
+ if (ChildHandle != NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ return LookupUnicodeString2 (Language,
+ This->SupportedLanguages,
+ mNxpI2cControllerNameTable,
+ ControllerName,
+ FALSE);
+}
+
+//
+// EFI Component Name 2 Protocol
+//
+EFI_COMPONENT_NAME2_PROTOCOL gNxpI2cDriverComponentName2 = {
+ NxpI2cGetDriverName,
+ NxpI2cGetControllerName,
+ "en"
+};
diff --git a/Silicon/NXP/Drivers/I2cDxe/DriverBinding.c b/Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
new file mode 100644
index 000000000000..59320447b5fd
--- /dev/null
+++ b/Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
@@ -0,0 +1,235 @@
+/** @file
+
+ Copyright 2018-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/DriverBinding.h>
+
+#include "I2cDxe.h"
+
+/**
+ Tests to see if this driver supports a given controller.
+
+ @param This[in] A pointer to the EFI_DRIVER_BINDING_PROTOCOL
+ instance.
+ @param ControllerHandle[in] The handle of the controller to test.
+ @param RemainingDevicePath[in] The remaining device path.
+ (Ignored - this is not a bus driver.)
+
+ @retval EFI_SUCCESS The driver supports this controller.
+ @retval EFI_ALREADY_STARTED The device specified by ControllerHandle is
+ already being managed by the driver specified
+ by This.
+ @retval EFI_UNSUPPORTED The device specified by ControllerHandle is
+ not supported by the driver specified by This.
+
+**/
+EFI_STATUS
+EFIAPI
+NxpI2cDriverBindingSupported (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
+ )
+{
+ NON_DISCOVERABLE_DEVICE *Dev;
+ EFI_STATUS Status;
+
+ //
+ // Connect to the non-discoverable device
+ //
+ Status = gBS->OpenProtocol (ControllerHandle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ (VOID **) &Dev,
+ This->DriverBindingHandle,
+ ControllerHandle,
+ EFI_OPEN_PROTOCOL_BY_DRIVER);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (CompareGuid (Dev->Type, &gNxpNonDiscoverableI2cMasterGuid)) {
+ Status = EFI_SUCCESS;
+ } else {
+ Status = EFI_UNSUPPORTED;
+ }
+
+ //
+ // Clean up.
+ //
+ gBS->CloseProtocol (ControllerHandle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ This->DriverBindingHandle,
+ ControllerHandle);
+
+ return Status;
+}
+
+
+/**
+ Starts a device controller or a bus controller.
+
+ @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL
+ instance.
+ @param[in] ControllerHandle The handle of the device to start. This
+ handle must support a protocol interface that
+ supplies an I/O abstraction to the driver.
+ @param[in] RemainingDevicePath The remaining portion of the device path.
+ (Ignored - this is not a bus driver.)
+
+ @retval EFI_SUCCESS The device was started.
+ @retval EFI_DEVICE_ERROR The device could not be started due to a
+ device error.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a
+ lack of resources.
+
+**/
+EFI_STATUS
+EFIAPI
+NxpI2cDriverBindingStart (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL
+ )
+{
+ return NxpI2cInit (This->DriverBindingHandle, ControllerHandle);
+}
+
+
+/**
+ Stops a device controller or a bus controller.
+
+ @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL
+ instance.
+ @param[in] ControllerHandle A handle to the device being stopped. The handle
+ must support a bus specific I/O protocol for the
+ driver to use to stop the device.
+ @param[in] NumberOfChildren The number of child device handles in
+ ChildHandleBuffer.
+ @param[in] ChildHandleBuffer An array of child handles to be freed. May be
+ NULL if NumberOfChildren is 0.
+
+ @retval EFI_SUCCESS The device was stopped.
+ @retval EFI_DEVICE_ERROR The device could not be stopped due to a device
+ error.
+
+**/
+EFI_STATUS
+EFIAPI
+NxpI2cDriverBindingStop (
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,
+ IN EFI_HANDLE ControllerHandle,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer OPTIONAL
+ )
+{
+ return NxpI2cRelease (This->DriverBindingHandle, ControllerHandle);
+}
+
+
+STATIC EFI_DRIVER_BINDING_PROTOCOL gNxpI2cDriverBinding = {
+ NxpI2cDriverBindingSupported,
+ NxpI2cDriverBindingStart,
+ NxpI2cDriverBindingStop,
+ 0xa,
+ NULL,
+ NULL
+};
+
+
+/**
+ The entry point of I2c UEFI Driver.
+
+ @param ImageHandle The image handle of the UEFI Driver.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The Driver or UEFI Driver exited normally.
+ @retval EFI_INCOMPATIBLE_VERSION _gUefiDriverRevision is greater than
+ SystemTable->Hdr.Revision.
+
+**/
+EFI_STATUS
+EFIAPI
+I2cDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Add the driver to the list of drivers
+ //
+ Status = EfiLibInstallDriverBindingComponentName2 (
+ ImageHandle, SystemTable, &gNxpI2cDriverBinding, ImageHandle,
+ NULL, &gNxpI2cDriverComponentName2);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Unload function for the I2c UEFI Driver.
+
+ @param ImageHandle[in] The allocated handle for the EFI image
+
+ @retval EFI_SUCCESS The driver was unloaded successfully
+ @retval EFI_INVALID_PARAMETER ImageHandle is not a valid image handle.
+
+**/
+EFI_STATUS
+EFIAPI
+I2cDxeUnload (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ UINTN Index;
+
+ //
+ // Retrieve all USB I/O handles in the handle database
+ //
+ Status = gBS->LocateHandleBuffer (ByProtocol,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Disconnect the driver from the handles in the handle database
+ //
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->DisconnectController (HandleBuffer[Index],
+ gImageHandle,
+ NULL);
+ }
+
+ //
+ // Free the handle array
+ //
+ gBS->FreePool (HandleBuffer);
+
+ //
+ // Uninstall protocols installed by the driver in its entrypoint
+ //
+ Status = gBS->UninstallMultipleProtocolInterfaces (ImageHandle,
+ &gEfiDriverBindingProtocolGuid,
+ &gNxpI2cDriverBinding,
+ NULL
+ );
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
new file mode 100644
index 000000000000..853c426fbca2
--- /dev/null
+++ b/Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
@@ -0,0 +1,690 @@
+/** I2cDxe.c
+ I2c driver APIs for read, write, initialize, set speed and reset
+
+ Copyright 2017-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/TimerLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include "I2cDxe.h"
+
+STATIC CONST EFI_I2C_CONTROLLER_CAPABILITIES mI2cControllerCapabilities = {
+ 0,
+ 0,
+ 0,
+ 0
+};
+
+STATIC CONST CLK_DIV mClkDiv[] = {
+ { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
+ { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
+ { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
+ { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
+ { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
+ { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
+ { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
+ { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
+ { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
+ { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
+ { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
+ { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
+ { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
+ { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
+ { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }
+};
+
+/**
+ Calculate and return proper clock divider
+
+ @param Rate desired clock rate
+
+ @retval ClkDiv Index value used to get Bus Clock Rate
+
+**/
+STATIC
+UINT8
+GetClkDivIndex (
+ IN UINT32 Rate
+ )
+{
+ UINTN ClkRate;
+ UINT32 Div;
+ UINT8 Index;
+
+ Index = 0;
+ ClkRate = GetBusFrequency ();
+
+ Div = (ClkRate + Rate - 1) / Rate;
+
+ if (Div < mClkDiv[0].SCLDivider) {
+ return 0;
+ }
+
+ do {
+ if (mClkDiv[Index].SCLDivider >= Div ) {
+ return Index;
+ }
+ Index++;
+ } while (Index < ARRAY_SIZE (mClkDiv));
+
+ return (ARRAY_SIZE (mClkDiv) - 1);
+}
+
+/**
+ Function used to check if i2c is in mentioned state or not
+
+ @param I2cRegs Pointer to I2C registers
+ @param State i2c state need to be checked
+
+ @retval EFI_NOT_READY Arbitration was lost
+ @retval EFI_TIMEOUT Timeout occured
+ @retval CurrState Value of state register
+
+**/
+STATIC
+EFI_STATUS
+WaitForI2cState (
+ IN I2C_REGS *I2cRegs,
+ IN UINT32 State
+ )
+{
+ UINT8 CurrState;
+ UINT64 Count;
+
+ for (Count = 0; Count < I2C_STATE_RETRIES; Count++) {
+ MemoryFence ();
+ CurrState = MmioRead8 ((UINTN)&I2cRegs->I2cSr);
+ if (CurrState & I2C_SR_IAL) {
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, CurrState | I2C_SR_IAL);
+ return EFI_NOT_READY;
+ }
+
+ if ((CurrState & (State >> 8)) == (UINT8)State) {
+ return CurrState;
+ }
+ }
+
+ return EFI_TIMEOUT;
+}
+
+/**
+ Function to transfer byte on i2c
+
+ @param I2cRegs Pointer to i2c registers
+ @param Byte Byte to be transferred on i2c bus
+
+ @retval EFI_NOT_READY Arbitration was lost
+ @retval EFI_TIMEOUT Timeout occured
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Data transfer was succesful
+
+**/
+STATIC
+EFI_STATUS
+TransferByte (
+ IN I2C_REGS *I2cRegs,
+ IN UINT8 Byte
+ )
+{
+ EFI_STATUS RetVal;
+
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+ MmioWrite8 ((UINTN)&I2cRegs->I2cDr, Byte);
+
+ RetVal = WaitForI2cState (I2cRegs, IIF);
+ if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
+ return RetVal;
+ }
+
+ if (RetVal & I2C_SR_RX_NO_AK) {
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to stop transaction on i2c bus
+
+ @param I2cRegs Pointer to i2c registers
+
+ @retval EFI_NOT_READY Arbitration was lost
+ @retval EFI_TIMEOUT Timeout occured
+ @retval EFI_SUCCESS Stop operation was successful
+
+**/
+STATIC
+EFI_STATUS
+I2cStop (
+ IN I2C_REGS *I2cRegs
+ )
+{
+ EFI_STATUS RetVal;
+ UINT32 Temp;
+
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+
+ Temp &= ~(I2C_CR_MSTA | I2C_CR_MTX);
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+ RetVal = WaitForI2cState (I2cRegs, BUS_IDLE);
+
+ if (RetVal < 0) {
+ return RetVal;
+ } else {
+ return EFI_SUCCESS;
+ }
+}
+
+/**
+ Function to send start signal, Chip Address and
+ memory offset
+
+ @param I2cRegs Pointer to i2c base registers
+ @param Chip Chip Address
+ @param Offset Slave memory's offset
+ @param AddressLength length of chip address
+
+ @retval EFI_NOT_READY Arbitration lost
+ @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Read was successful
+
+**/
+STATIC
+EFI_STATUS
+InitTransfer (
+ IN I2C_REGS *I2cRegs,
+ IN UINT8 Chip,
+ IN UINT32 Offset,
+ IN INT32 AddressLength
+ )
+{
+ UINT32 Temp;
+ EFI_STATUS RetVal;
+
+ // Enable I2C controller
+ if (MmioRead8 ((UINTN)&I2cRegs->I2cCr) & I2C_CR_IDIS) {
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IEN);
+ }
+
+ if (MmioRead8 ((UINTN)&I2cRegs->I2cAdr) == (Chip << 1)) {
+ MmioWrite8 ((UINTN)&I2cRegs->I2cAdr, (Chip << 1) ^ 2);
+ }
+
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+ RetVal = WaitForI2cState (I2cRegs, BUS_IDLE);
+ if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
+ return RetVal;
+ }
+
+ // Start I2C transaction
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+ // set to master mode
+ Temp |= I2C_CR_MSTA;
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+ RetVal = WaitForI2cState (I2cRegs, BUS_BUSY);
+ if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
+ return RetVal;
+ }
+
+ Temp |= I2C_CR_MTX | I2C_CR_TX_NO_AK;
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+ // write slave Address
+ RetVal = TransferByte (I2cRegs, Chip << 1);
+ if (RetVal != EFI_SUCCESS) {
+ return RetVal;
+ }
+
+ if (AddressLength >= 0) {
+ while (AddressLength--) {
+ RetVal = TransferByte (I2cRegs, (Offset >> (AddressLength * 8)) & 0xff);
+ if (RetVal != EFI_SUCCESS)
+ return RetVal;
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to check if i2c bus is idle
+
+ @param Base Pointer to base address of I2c controller
+
+ @retval EFI_SUCCESS
+
+**/
+STATIC
+INT32
+I2cBusIdle (
+ IN VOID *Base
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to initiate data transfer on i2c bus
+
+ @param I2cRegs Pointer to i2c base registers
+ @param Chip Chip Address
+ @param Offset Slave memory's offset
+ @param AddressLength length of chip address
+
+ @retval EFI_NOT_READY Arbitration lost
+ @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Read was successful
+
+**/
+STATIC
+EFI_STATUS
+InitDataTransfer (
+ IN I2C_REGS *I2cRegs,
+ IN UINT8 Chip,
+ IN UINT32 Offset,
+ IN INT32 AddressLength
+ )
+{
+ EFI_STATUS RetVal;
+ INT32 Retry;
+
+ for (Retry = 0; Retry < RETRY_COUNT; Retry++) {
+ RetVal = InitTransfer (I2cRegs, Chip, Offset, AddressLength);
+ if (RetVal == EFI_SUCCESS) {
+ return EFI_SUCCESS;
+ }
+
+ I2cStop (I2cRegs);
+
+ if (EFI_NOT_FOUND == RetVal) {
+ return RetVal;
+ }
+
+ // Disable controller
+ if (RetVal != EFI_NOT_READY) {
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
+ }
+
+ if (I2cBusIdle (I2cRegs) < 0) {
+ break;
+ }
+ }
+ return RetVal;
+}
+
+/**
+ Function to read data using i2c bus
+
+ @param BaseAddr I2c Controller Base Address
+ @param Chip Address of slave device from where data to be read
+ @param Offset Offset of slave memory
+ @param AddressLength Address length of slave
+ @param Buffer A pointer to the destination buffer for the data
+ @param Len Length of data to be read
+
+ @retval EFI_NOT_READY Arbitration lost
+ @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Read was successful
+
+**/
+STATIC
+EFI_STATUS
+I2cDataRead (
+ IN UINTN BaseAddr,
+ IN UINT8 Chip,
+ IN UINT32 Offset,
+ IN UINT32 AddressLength,
+ IN UINT8 *Buffer,
+ IN UINT32 Len
+ )
+{
+ EFI_STATUS RetVal;
+ UINT32 Temp;
+ INT32 I;
+ I2C_REGS *I2cRegs;
+
+ I2cRegs = (I2C_REGS *)(BaseAddr);
+
+ RetVal = InitDataTransfer (I2cRegs, Chip, Offset, AddressLength);
+ if (RetVal != EFI_SUCCESS) {
+ return RetVal;
+ }
+
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+ Temp |= I2C_CR_RSTA;
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+
+ RetVal = TransferByte (I2cRegs, (Chip << 1) | 1);
+ if (RetVal != EFI_SUCCESS) {
+ I2cStop (I2cRegs);
+ return RetVal;
+ }
+
+ // setup bus to read data
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+ Temp &= ~(I2C_CR_MTX | I2C_CR_TX_NO_AK);
+ if (Len == 1) {
+ Temp |= I2C_CR_TX_NO_AK;
+ }
+
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+
+ // Dummy Read to initiate recieve operation
+ MmioRead8 ((UINTN)&I2cRegs->I2cDr);
+
+ for (I = 0; I < Len; I++) {
+ RetVal = WaitForI2cState (I2cRegs, IIF);
+ if ((RetVal == EFI_TIMEOUT) || (RetVal == EFI_NOT_READY)) {
+ I2cStop (I2cRegs);
+ return RetVal;
+ }
+ //
+ // It must generate STOP before read I2DR to prevent
+ // controller from generating another clock cycle
+ //
+ if (I == (Len - 1)) {
+ I2cStop (I2cRegs);
+ } else if (I == (Len - 2)) {
+ Temp = MmioRead8 ((UINTN)&I2cRegs->I2cCr);
+ Temp |= I2C_CR_TX_NO_AK;
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, Temp);
+ }
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, I2C_SR_IIF_CLEAR);
+ Buffer[I] = MmioRead8 ((UINTN)&I2cRegs->I2cDr);
+ }
+
+ I2cStop (I2cRegs);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to write data using i2c bus
+
+ @param BaseAddr I2c Controller Base Address
+ @param Chip Address of slave device where data to be written
+ @param Offset Offset of slave memory
+ @param AddressLength Address length of slave
+ @param Buffer A pointer to the source buffer for the data
+ @param Len Length of data to be write
+
+ @retval EFI_NOT_READY Arbitration lost
+ @retval EFI_TIMEOUT Failed to initialize data transfer in predefined time
+ @retval EFI_NOT_FOUND ACK was not recieved
+ @retval EFI_SUCCESS Read was successful
+
+**/
+STATIC
+EFI_STATUS
+I2cDataWrite (
+ IN UINTN BaseAddr,
+ IN UINT8 Chip,
+ IN UINT32 Offset,
+ IN INT32 AddressLength,
+ OUT UINT8 *Buffer,
+ IN INT32 Len
+ )
+{
+ EFI_STATUS RetVal;
+ I2C_REGS *I2cRegs;
+ INT32 I;
+
+ I2cRegs = (I2C_REGS *)BaseAddr;
+
+ RetVal = InitDataTransfer (I2cRegs, Chip, Offset, AddressLength);
+ if (RetVal != EFI_SUCCESS) {
+ return RetVal;
+ }
+
+ // Write operation
+ for (I = 0; I < Len; I++) {
+ RetVal = TransferByte (I2cRegs, Buffer[I]);
+ if (RetVal != EFI_SUCCESS) {
+ break;
+ }
+ }
+
+ I2cStop (I2cRegs);
+ return RetVal;
+}
+
+/**
+ Function to set i2c bus frequency
+
+ @param This Pointer to I2c master protocol
+ @param BusClockHertz value to be set
+
+ @retval EFI_SUCCESS Operation successfull
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+SetBusFrequency (
+ IN CONST EFI_I2C_MASTER_PROTOCOL *This,
+ IN OUT UINTN *BusClockHertz
+ )
+{
+ I2C_REGS *I2cRegs;
+ UINT8 ClkId;
+ UINT8 SpeedId;
+ NXP_I2C_MASTER *I2c;
+
+ I2c = NXP_I2C_FROM_THIS (This);
+
+ I2cRegs = (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin);
+
+ ClkId = GetClkDivIndex (*BusClockHertz);
+ SpeedId = mClkDiv[ClkId].BusClockRate;
+
+ // Store divider value
+ MmioWrite8 ((UINTN)&I2cRegs->I2cFdr, SpeedId);
+
+ MemoryFence ();
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to reset I2c Controller
+
+ @param This Pointer to I2c master protocol
+
+ @return EFI_SUCCESS Operation successfull
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+Reset (
+ IN CONST EFI_I2C_MASTER_PROTOCOL *This
+ )
+{
+ I2C_REGS *I2cRegs;
+ NXP_I2C_MASTER *I2c;
+
+ I2c = NXP_I2C_FROM_THIS (This);
+
+ I2cRegs = (I2C_REGS *)(I2c->Dev->Resources[0].AddrRangeMin);
+
+ // Reset module
+ MmioWrite8 ((UINTN)&I2cRegs->I2cCr, I2C_CR_IDIS);
+ MmioWrite8 ((UINTN)&I2cRegs->I2cSr, 0);
+
+ MemoryFence ();
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+EFIAPI
+StartRequest (
+ IN CONST EFI_I2C_MASTER_PROTOCOL *This,
+ IN UINTN SlaveAddress,
+ IN EFI_I2C_REQUEST_PACKET *RequestPacket,
+ IN EFI_EVENT Event OPTIONAL,
+ OUT EFI_STATUS *I2cStatus OPTIONAL
+ )
+{
+ NXP_I2C_MASTER *I2c;
+ UINT32 Count;
+ INT32 RetVal;
+ UINT32 Length;
+ UINT8 *Buffer;
+ UINT32 Flag;
+ UINT32 RegAddress;
+ UINT32 OffsetLength;
+
+ RegAddress = 0;
+
+ I2c = NXP_I2C_FROM_THIS (This);
+
+ if (RequestPacket->OperationCount <= 0) {
+ DEBUG ((DEBUG_ERROR,"%a: Operation count is not valid %d\n",
+ __FUNCTION__, RequestPacket->OperationCount));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ OffsetLength = RequestPacket->Operation[0].LengthInBytes;
+ RegAddress = *RequestPacket->Operation[0].Buffer;
+
+ for (Count = 1; Count < RequestPacket->OperationCount; Count++) {
+ Flag = RequestPacket->Operation[Count].Flags;
+ Length = RequestPacket->Operation[Count].LengthInBytes;
+ Buffer = RequestPacket->Operation[Count].Buffer;
+
+ if (Length <= 0) {
+ DEBUG ((DEBUG_ERROR,"%a: Invalid length of buffer %d\n",
+ __FUNCTION__, Length));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (Flag == I2C_FLAG_READ) {
+ RetVal = I2cDataRead (I2c->Dev->Resources[0].AddrRangeMin, SlaveAddress,
+ RegAddress, OffsetLength, Buffer, Length);
+ if (RetVal != EFI_SUCCESS) {
+ DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n",
+ __FUNCTION__, RetVal));
+ return RetVal;
+ }
+ } else if (Flag == I2C_FLAG_WRITE) {
+ RetVal = I2cDataWrite (I2c->Dev->Resources[0].AddrRangeMin, SlaveAddress,
+ RegAddress, OffsetLength, Buffer, Length);
+ if (RetVal != EFI_SUCCESS) {
+ DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n",
+ __FUNCTION__, RetVal));
+ return RetVal;
+ }
+ } else {
+ DEBUG ((DEBUG_ERROR,"%a: Invalid Flag %d\n", __FUNCTION__, Flag));
+ return EFI_INVALID_PARAMETER;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NxpI2cInit (
+ IN EFI_HANDLE DriverBindingHandle,
+ IN EFI_HANDLE ControllerHandle
+ )
+{
+ EFI_STATUS RetVal;
+ NON_DISCOVERABLE_DEVICE *Dev;
+ NXP_I2C_MASTER *I2c;
+
+ RetVal = gBS->OpenProtocol (ControllerHandle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ (VOID **)&Dev, DriverBindingHandle,
+ ControllerHandle, EFI_OPEN_PROTOCOL_BY_DRIVER);
+ if (EFI_ERROR (RetVal)) {
+ return RetVal;
+ }
+
+ I2c = AllocateZeroPool (sizeof (NXP_I2C_MASTER));
+
+ I2c->Signature = NXP_I2C_SIGNATURE;
+ I2c->I2cMaster.SetBusFrequency = SetBusFrequency;
+ I2c->I2cMaster.Reset = Reset;
+ I2c->I2cMaster.StartRequest = StartRequest;
+ I2c->I2cMaster.I2cControllerCapabilities = &mI2cControllerCapabilities;
+ I2c->Dev = Dev;
+
+ CopyGuid (&I2c->DevicePath.Vendor.Guid, &gEfiCallerIdGuid);
+ I2c->DevicePath.MmioBase = I2c->Dev->Resources[0].AddrRangeMin;
+ SetDevicePathNodeLength (&I2c->DevicePath.Vendor,
+ sizeof (I2c->DevicePath) - sizeof (I2c->DevicePath.End));
+ SetDevicePathEndNode (&I2c->DevicePath.End);
+
+ RetVal = gBS->InstallMultipleProtocolInterfaces (&ControllerHandle,
+ &gEfiI2cMasterProtocolGuid, (VOID**)&I2c->I2cMaster,
+ &gEfiDevicePathProtocolGuid, &I2c->DevicePath,
+ NULL);
+
+ if (EFI_ERROR (RetVal)) {
+ FreePool (I2c);
+ gBS->CloseProtocol (ControllerHandle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ DriverBindingHandle,
+ ControllerHandle);
+ }
+
+ return RetVal;
+}
+
+EFI_STATUS
+NxpI2cRelease (
+ IN EFI_HANDLE DriverBindingHandle,
+ IN EFI_HANDLE ControllerHandle
+ )
+{
+ EFI_I2C_MASTER_PROTOCOL *I2cMaster;
+ EFI_STATUS RetVal;
+ NXP_I2C_MASTER *I2c;
+
+ RetVal = gBS->HandleProtocol (ControllerHandle,
+ &gEfiI2cMasterProtocolGuid,
+ (VOID **)&I2cMaster);
+ ASSERT_EFI_ERROR (RetVal);
+ if (EFI_ERROR (RetVal)) {
+ return RetVal;
+ }
+
+ I2c = NXP_I2C_FROM_THIS (I2cMaster);
+
+ RetVal = gBS->UninstallMultipleProtocolInterfaces (ControllerHandle,
+ &gEfiI2cMasterProtocolGuid, I2cMaster,
+ &gEfiDevicePathProtocolGuid, &I2c->DevicePath,
+ NULL);
+ if (EFI_ERROR (RetVal)) {
+ return RetVal;
+ }
+
+ RetVal = gBS->CloseProtocol (ControllerHandle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid,
+ DriverBindingHandle,
+ ControllerHandle);
+ ASSERT_EFI_ERROR (RetVal);
+ if (EFI_ERROR (RetVal)) {
+ return RetVal;
+ }
+
+ gBS->FreePool (I2c);
+
+ return EFI_SUCCESS;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v2 06/11] Silicon/Maxim : Add support for DS1307 RTC library
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
` (4 preceding siblings ...)
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 05/11] Silicon/NXP: Add support for I2c driver Meenakshi Aggarwal
@ 2019-11-21 16:25 ` Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 07/11] Silicon/NXP : Add MemoryInitPei Library Meenakshi Aggarwal
` (5 subsequent siblings)
11 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-11-21 16:25 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, devel
Cc: v.sethi, Meenakshi Aggarwal
Real time clock Apis on top of I2C Apis
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec | 23 ++
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf | 40 +++
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h | 48 +++
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 372 ++++++++++++++++++++
4 files changed, 483 insertions(+)
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
new file mode 100644
index 000000000000..27283e714732
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
@@ -0,0 +1,23 @@
+#/** @file
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+ PACKAGE_NAME = Ds1307RtcLib
+ PACKAGE_GUID = 0c095cf6-834d-4fa2-a5a0-31ac35591ad2
+ PACKAGE_VERSION = 0.1
+
+[Guids]
+ gDs1307RtcLibTokenSpaceGuid = { 0xd939eb84, 0xa95a, 0x46a0, { 0xa8, 0x2b, 0xb9, 0x64, 0x30, 0xcf, 0xf5, 0x99 }}
+
+[Protocols]
+ gDs1307RealTimeClockLibI2cMasterProtocolGuid = { 0xd37c4d54, 0x1bca, 0x49e0, { 0xa0, 0x4a, 0x5c, 0x37, 0x59, 0x38, 0xc7, 0xec}}
+
+[PcdsFixedAtBuild]
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT8|0x00000001
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|0|UINT32|0x00000002
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
new file mode 100644
index 000000000000..b92f658bfc46
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
@@ -0,0 +1,40 @@
+# @Ds1307RtcLib.inf
+#
+# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Ds1307RtcLib
+ FILE_GUID = 7112fb46-8dda-4a41-ac40-bf212fedfc08
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+[Sources.common]
+ Ds1307RtcLib.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
+
+[LibraryClasses]
+ DebugLib
+ UefiBootServicesTableLib
+ UefiLib
+
+[Protocols]
+ gEfiI2cMasterProtocolGuid ## CONSUMES
+ gDs1307RealTimeClockLibI2cMasterProtocolGuid ## CONSUMES
+
+[FixedPcd]
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency
+
+[Depex]
+ gDs1307RealTimeClockLibI2cMasterProtocolGuid
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
new file mode 100644
index 000000000000..aa5b3583ec7e
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
@@ -0,0 +1,48 @@
+/** Ds1307Rtc.h
+*
+* Copyright 2017 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef DS1307RTC_H_
+#define DS1307RTC_H_
+
+/*
+ * RTC time register
+ */
+#define DS1307_SEC_REG_ADDR 0x00
+#define DS1307_MIN_REG_ADDR 0x01
+#define DS1307_HR_REG_ADDR 0x02
+#define DS1307_DAY_REG_ADDR 0x03
+#define DS1307_DATE_REG_ADDR 0x04
+#define DS1307_MON_REG_ADDR 0x05
+#define DS1307_YR_REG_ADDR 0x06
+
+#define DS1307_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
+
+/*
+ * RTC control register
+ */
+#define DS1307_CTL_REG_ADDR 0x07
+
+#define START_YEAR 1970
+#define END_YEAR 2070
+
+/*
+ * TIME MASKS
+ */
+#define MASK_SEC 0x7F
+#define MASK_MIN 0x7F
+#define MASK_HOUR 0x3F
+#define MASK_DAY 0x3F
+#define MASK_MONTH 0x1F
+
+typedef struct {
+ UINTN OperationCount;
+ EFI_I2C_OPERATION SetAddressOp;
+ EFI_I2C_OPERATION GetSetDateTimeOp;
+} RTC_I2C_REQUEST;
+
+#endif // DS1307RTC_H_
diff --git a/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
new file mode 100644
index 000000000000..88dc198ffec8
--- /dev/null
+++ b/Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
@@ -0,0 +1,372 @@
+/** Ds1307RtcLib.c
+ Implement EFI RealTimeClock via RTC Lib for DS1307 RTC.
+
+ Based on RTC implementation available in
+ EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright 2017 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Protocol/I2cMaster.h>
+
+#include "Ds1307Rtc.h"
+
+STATIC VOID *mDriverEventRegistration;
+STATIC EFI_HANDLE mI2cMasterHandle;
+STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster;
+
+/**
+ Read RTC register.
+
+ @param RtcRegAddr Register offset of RTC to be read.
+
+ @retval Register Value read
+
+**/
+
+STATIC
+UINT8
+RtcRead (
+ IN UINT8 RtcRegAddr
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+ UINT8 Val;
+
+ Val = 0;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = I2C_FLAG_READ;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr));
+ }
+
+ return Val;
+}
+
+/**
+ Write RTC register.
+
+ @param RtcRegAddr Register offset of RTC to write.
+ @param Val Value to be written
+
+**/
+
+STATIC
+VOID
+RtcWrite (
+ IN UINT8 RtcRegAddr,
+ IN UINT8 Val
+ )
+{
+ RTC_I2C_REQUEST Req;
+ EFI_STATUS Status;
+
+ Req.OperationCount = 2;
+
+ Req.SetAddressOp.Flags = 0;
+ Req.SetAddressOp.LengthInBytes = sizeof (RtcRegAddr);
+ Req.SetAddressOp.Buffer = &RtcRegAddr;
+
+ Req.GetSetDateTimeOp.Flags = 0;
+ Req.GetSetDateTimeOp.LengthInBytes = sizeof (Val);
+ Req.GetSetDateTimeOp.Buffer = &Val;
+
+ Status = mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSlaveAddress),
+ (VOID *)&Req,
+ NULL, NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr));
+ }
+}
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+
+**/
+
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Second;
+ UINT8 Minute;
+ UINT8 Hour;
+ UINT8 Day;
+ UINT8 Month;
+ UINT8 Year;
+
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ Status = EFI_SUCCESS;
+
+ Second = RtcRead (DS1307_SEC_REG_ADDR);
+ Minute = RtcRead (DS1307_MIN_REG_ADDR);
+ Hour = RtcRead (DS1307_HR_REG_ADDR);
+ Day = RtcRead (DS1307_DATE_REG_ADDR);
+ Month = RtcRead (DS1307_MON_REG_ADDR);
+ Year = RtcRead (DS1307_YR_REG_ADDR);
+
+ if (Second & DS1307_SEC_BIT_CH) {
+ DEBUG ((DEBUG_ERROR, "### Warning: RTC oscillator has stopped\n"));
+ /* clear the CH flag */
+ RtcWrite (DS1307_SEC_REG_ADDR,
+ RtcRead (DS1307_SEC_REG_ADDR) & ~DS1307_SEC_BIT_CH);
+ Status = EFI_DEVICE_ERROR;
+ }
+
+ Time->Second = BcdToDecimal8 (Second & MASK_SEC);
+ Time->Minute = BcdToDecimal8 (Minute & MASK_MIN);
+ Time->Hour = BcdToDecimal8 (Hour & MASK_HOUR);
+ Time->Day = BcdToDecimal8 (Day & MASK_DAY);
+ Time->Month = BcdToDecimal8 (Month & MASK_MONTH);
+
+ //
+ // RTC can save year 1970 to 2069
+ // On writing Year, save year % 100
+ // On Reading reversing the operation e.g. 2012
+ // write = 12 (2012 % 100)
+ // read = 2012 (12 + 2000)
+ //
+ Time->Year = BcdToDecimal8 (Year) +
+ (BcdToDecimal8 (Year) >= 70 ? START_YEAR - 70 : END_YEAR -70);
+
+ return Status;
+}
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ if (mI2cMaster == NULL) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ if (Time->Year < START_YEAR || Time->Year >= END_YEAR){
+ DEBUG ((DEBUG_ERROR, "WARNING: Year should be between 1970 and 2069!\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ RtcWrite (DS1307_YR_REG_ADDR, DecimalToBcd8 (Time->Year % 100));
+ RtcWrite (DS1307_MON_REG_ADDR, DecimalToBcd8 (Time->Month));
+ RtcWrite (DS1307_DATE_REG_ADDR, DecimalToBcd8 (Time->Day));
+ RtcWrite (DS1307_HR_REG_ADDR, DecimalToBcd8 (Time->Hour));
+ RtcWrite (DS1307_MIN_REG_ADDR, DecimalToBcd8 (Time->Minute));
+ RtcWrite (DS1307_SEC_REG_ADDR, DecimalToBcd8 (Time->Second));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this
+ platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // The DS1307 does not support setting the alarm
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // The DS1307 does not support setting the alarm
+ return EFI_UNSUPPORTED;
+}
+
+STATIC
+VOID
+I2cDriverRegistrationEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ EFI_I2C_MASTER_PROTOCOL *I2cMaster;
+ UINTN BusFrequency;
+ EFI_HANDLE Handle;
+ UINTN BufferSize;
+
+ //
+ // Try to connect the newly registered driver to our handle.
+ //
+ do {
+ BufferSize = sizeof (EFI_HANDLE);
+ Status = gBS->LocateHandle (ByRegisterNotify,
+ &gEfiI2cMasterProtocolGuid,
+ mDriverEventRegistration,
+ &BufferSize,
+ &Handle);
+ if (EFI_ERROR (Status)) {
+ if (Status != EFI_NOT_FOUND) {
+ DEBUG ((DEBUG_WARN, "%a: gBS->LocateHandle () returned %r\n",
+ __FUNCTION__, Status));
+ }
+ break;
+ }
+
+ if (Handle != mI2cMasterHandle) {
+ continue;
+ }
+
+ DEBUG ((DEBUG_INFO, "%a: found I2C master!\n", __FUNCTION__));
+
+ gBS->CloseEvent (Event);
+
+ Status = gBS->OpenProtocol (mI2cMasterHandle, &gEfiI2cMasterProtocolGuid,
+ (VOID **)&I2cMaster, gImageHandle, NULL,
+ EFI_OPEN_PROTOCOL_EXCLUSIVE);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = I2cMaster->Reset (I2cMaster);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n",
+ __FUNCTION__, Status));
+ break;
+ }
+
+ BusFrequency = FixedPcdGet16 (PcdI2cBusFrequency);
+ Status = I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n",
+ __FUNCTION__, Status));
+ break;
+ }
+
+ mI2cMaster = I2cMaster;
+ break;
+ } while (TRUE);
+
+ return;
+}
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN BufferSize;
+
+ //
+ // Find the handle that marks the controller
+ // that will provide the I2C master protocol.
+ //
+ BufferSize = sizeof (EFI_HANDLE);
+ Status = gBS->LocateHandle (
+ ByProtocol,
+ &gDs1307RealTimeClockLibI2cMasterProtocolGuid,
+ NULL,
+ &BufferSize,
+ &mI2cMasterHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register a protocol registration notification callback on the driver
+ // binding protocol so we can attempt to connect our I2C master to it
+ // as soon as it appears.
+ //
+ EfiCreateProtocolNotifyEvent (
+ &gEfiI2cMasterProtocolGuid,
+ TPL_CALLBACK,
+ I2cDriverRegistrationEvent,
+ NULL,
+ &mDriverEventRegistration);
+
+ return EFI_SUCCESS;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v2 07/11] Silicon/NXP : Add MemoryInitPei Library
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
` (5 preceding siblings ...)
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 06/11] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi Aggarwal
@ 2019-11-21 16:25 ` Meenakshi Aggarwal
2019-11-26 16:55 ` [edk2-devel] " Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 08/11] Platform/NXP: Add support for ArmPlatformLib Meenakshi Aggarwal
` (4 subsequent siblings)
11 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-11-21 16:25 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, devel
Cc: v.sethi, Meenakshi Aggarwal
Add MemoryInitPei Library for NXP platforms.
It has changes to get DRAM information from TFA.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf | 48 +++++++
Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c | 139 ++++++++++++++++++++
2 files changed, 187 insertions(+)
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
new file mode 100644
index 000000000000..806da6d9ab9a
--- /dev/null
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
@@ -0,0 +1,48 @@
+#/** @file
+#
+# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+# Copyright 2019 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmMemoryInitPeiLib
+ FILE_GUID = 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM DXE_DRIVER
+
+[Sources]
+ MemoryInitPeiLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ ArmMmuLib
+ ArmPlatformLib
+ PcdLib
+
+[Guids]
+ gEfiMemoryTypeInformationGuid
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
+[Depex]
+ TRUE
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
new file mode 100644
index 000000000000..9889d5730261
--- /dev/null
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
@@ -0,0 +1,139 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*
+* Copyright 2019 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <PiPei.h>
+
+#include <Library/ArmMmuLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+#include <DramInfo.h>
+
+VOID
+BuildMemoryTypeInformationHob (
+ VOID
+ );
+
+VOID
+InitMmu (
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
+ )
+{
+
+ VOID *TranslationTableBase;
+ UINTN TranslationTableSize;
+ RETURN_STATUS Status;
+
+ //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in
+ // DRAM (even at the top of DRAM as it is the first permanent memory allocation)
+ Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n"));
+ }
+}
+
+/*++
+
+Routine Description:
+
+
+
+Arguments:
+
+ FileHandle - Handle of the file being invoked.
+ PeiServices - Describes the list of possible PEI Services.
+
+Returns:
+
+ Status - EFI_SUCCESS if the boot mode could be set
+
+--*/
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
+ IN UINT64 UefiMemorySize
+ )
+{
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
+ EFI_PEI_HOB_POINTERS NextHob;
+ BOOLEAN Found;
+ DRAM_INFO DramInfo;
+
+ // Get Virtual Memory Map from the Platform Library
+ ArmPlatformGetVirtualMemoryMap (&MemoryTable);
+
+ //
+ // Ensure MemoryTable[0].Length which is size of DRAM has been set
+ // by ArmPlatformGetVirtualMemoryMap ()
+ //
+ ASSERT (MemoryTable[0].Length != 0);
+
+ //
+ // Now, the permanent memory has been installed, we can call AllocatePages()
+ //
+ ResourceAttributes = (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED
+ );
+
+ if (GetDramBankInfo (&DramInfo)) {
+ DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ while (DramInfo.NumOfDrams--) {
+ //
+ // Check if the resource for the main system memory has been declared
+ //
+ Found = FALSE;
+ NextHob.Raw = GetHobList ();
+ while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
+ if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
+ (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >= NextHob.ResourceDescriptor->PhysicalStart) &&
+ (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength <=
+ DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo.DramRegion[DramInfo.NumOfDrams].Size))
+ {
+ Found = TRUE;
+ break;
+ }
+ NextHob.Raw = GET_NEXT_HOB (NextHob);
+ }
+
+ if (!Found) {
+ // Reserved the memory space occupied by the firmware volume
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress,
+ DramInfo.DramRegion[DramInfo.NumOfDrams].Size
+ );
+ }
+ }
+
+ // Build Memory Allocation Hob
+ InitMmu (MemoryTable);
+
+ if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
+ // Optional feature that helps prevent EFI memory map fragmentation.
+ BuildMemoryTypeInformationHob ();
+ }
+
+ return EFI_SUCCESS;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v2 08/11] Platform/NXP: Add support for ArmPlatformLib
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
` (6 preceding siblings ...)
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 07/11] Silicon/NXP : Add MemoryInitPei Library Meenakshi Aggarwal
@ 2019-11-21 16:25 ` Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 09/11] Platform/NXP: Add Platform driver for LS1043 RDB board Meenakshi Aggarwal
` (3 subsequent siblings)
11 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-11-21 16:25 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, devel
Cc: v.sethi, Meenakshi Aggarwal
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 55 ++++++++
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c | 98 +++++++++++++
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 144 ++++++++++++++++++++
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S | 31 +++++
4 files changed, 328 insertions(+)
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
new file mode 100644
index 000000000000..f7ae74afc6ca
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
@@ -0,0 +1,55 @@
+# @file
+#
+# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+# Copyright 2017, 2019 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformLib
+ FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ArmLib
+ SocLib
+
+[Sources.common]
+ NxpQoriqLsHelper.S | GCC
+ NxpQoriqLsMem.c
+ ArmPlatformLib.c
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
new file mode 100644
index 000000000000..eac7d4aa4e47
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
@@ -0,0 +1,98 @@
+/** ArmPlatformLib.c
+*
+* Contains board initialization functions.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017 NXP
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+extern VOID SocInit (VOID);
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Placeholder for Platform Initialization
+**/
+EFI_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ SocInit ();
+
+ return EFI_SUCCESS;
+}
+
+ARM_CORE_INFO LS1043aMpCoreInfoCTA53x4[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ },
+};
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = sizeof (LS1043aMpCoreInfoCTA53x4) / sizeof (ARM_CORE_INFO);
+ *ArmCoreTable = LS1043aMpCoreInfoCTA53x4;
+
+ return EFI_SUCCESS;
+}
+
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
+
+
+UINTN
+ArmPlatformGetCorePosition (
+ IN UINTN MpId
+ )
+{
+ return 1;
+}
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
new file mode 100644
index 000000000000..c6c256da0727
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
@@ -0,0 +1,144 @@
+/** NxpQoriqLsMem.c
+*
+* Board memory specific Library.
+*
+* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved.
+* Copyright 2017, 2019 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <DramInfo.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
+ )
+{
+ UINTN Index;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+ DRAM_INFO DramInfo;
+
+ Index = 0;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages (
+ EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ if (GetDramBankInfo (&DramInfo)) {
+ DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
+ return;
+ }
+
+
+ for (Index = 0; Index < DramInfo.NumOfDrams; Index++) {
+ // DRAM1 (Must be 1st entry)
+ VirtualMemoryTable[Index].PhysicalBase = DramInfo.DramRegion[Index].BaseAddress;
+ VirtualMemoryTable[Index].VirtualBase = DramInfo.DramRegion[Index].BaseAddress;
+ VirtualMemoryTable[Index].Length = DramInfo.DramRegion[Index].Size;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+ }
+
+ // CCSR Space
+ VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdCcsrBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // IFC region 1
+ //
+ // A-009241 : Unaligned write transactions to IFC may result in corruption of data
+ // Affects : IFC
+ // Description: 16 byte unaligned write from system bus to IFC may result in extra unintended
+ // writes on external IFC interface that can corrupt data on external flash.
+ // Impact : Data corruption on external flash may happen in case of unaligned writes to
+ // IFC memory space.
+ // Workaround: Following are the workarounds:
+ // For write transactions from core, IFC interface memories (including IFC SRAM)
+ // should be configured as device type memory in MMU.
+ // For write transactions from non-core masters (like system DMA), the address
+ // should be 16 byte aligned and the data size should be multiple of 16 bytes.
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion1Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // QMAN SWP
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQmanSwpBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQmanSwpSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // BMAN SWP
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdBmanSwpBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdBmanSwpSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // IFC region 2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdIfcRegion2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdIfcRegion2Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe1
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp1BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp1BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe2
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp2BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp2BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe3
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExp3BaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExp3BaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // QSPI region
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdQspiRegionBaseAddr);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdQspiRegionSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
new file mode 100644
index 000000000000..84ee8c9f9700
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
@@ -0,0 +1,31 @@
+# @file
+#
+# Copyright (c) 2012-2013, ARM Limited. All rights reserved.
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+#include <AsmMacroIoLibV8.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_IMPORT(ArmReadMpidr)
+
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ tst x0, #3
+ cset x0, eq
+ ret
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+EL1_OR_EL2(x0)
+1:
+2:
+ ret
+
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore))
+ ldrh w0, [x0]
+ ret
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v2 09/11] Platform/NXP: Add Platform driver for LS1043 RDB board
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
` (7 preceding siblings ...)
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 08/11] Platform/NXP: Add support for ArmPlatformLib Meenakshi Aggarwal
@ 2019-11-21 16:25 ` Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 10/11] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
` (2 subsequent siblings)
11 siblings, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-11-21 16:25 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, devel
Cc: v.sethi, Meenakshi Aggarwal
Platform driver will be used for platform specific work.
At present, it populate i2c driver structure with platform
specific information and install RTC on i2c.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf | 52 +++++++++
Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c | 114 ++++++++++++++++++++
2 files changed, 166 insertions(+)
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
new file mode 100644
index 000000000000..d689cf4db58e
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
@@ -0,0 +1,52 @@
+## @file
+#
+# Component description file for LS1043 DXE platform driver.
+#
+# Copyright 2018-2019 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = PlatformDxe
+ FILE_GUID = 21108101-adcd-4123-930e-a2354a554db7
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PlatformDxeEntryPoint
+
+[Sources]
+ PlatformDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ MemoryAllocationLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiLib
+
+[Guids]
+ gNxpNonDiscoverableI2cMasterGuid
+
+[Protocols]
+ gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES
+ gDs1307RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES
+
+[FixedPcd]
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController
+
+[Depex]
+ TRUE
diff --git a/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
new file mode 100644
index 000000000000..f89dcdeff3c1
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
@@ -0,0 +1,114 @@
+/** @file
+ LS1043 DXE platform driver.
+
+ Copyright 2018-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+
+#include <Protocol/NonDiscoverableDevice.h>
+
+typedef struct {
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR StartDesc;
+ UINT8 EndDesc;
+} ADDRESS_SPACE_DESCRIPTOR;
+
+STATIC ADDRESS_SPACE_DESCRIPTOR mI2cDesc[FixedPcdGet64 (PcdNumI2cController)];
+
+STATIC
+EFI_STATUS
+RegisterDevice (
+ IN EFI_GUID *TypeGuid,
+ IN ADDRESS_SPACE_DESCRIPTOR *Desc,
+ OUT EFI_HANDLE *Handle
+ )
+{
+ NON_DISCOVERABLE_DEVICE *Device;
+ EFI_STATUS Status;
+
+ Device = (NON_DISCOVERABLE_DEVICE *)AllocateZeroPool (sizeof (*Device));
+ if (Device == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Device->Type = TypeGuid;
+ Device->DmaType = NonDiscoverableDeviceDmaTypeNonCoherent;
+ Device->Resources = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Desc;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (Handle,
+ &gEdkiiNonDiscoverableDeviceProtocolGuid, Device,
+ NULL);
+ if (EFI_ERROR (Status)) {
+ goto FreeDevice;
+ }
+ return EFI_SUCCESS;
+
+FreeDevice:
+ FreePool (Device);
+
+ return Status;
+}
+
+VOID
+PopulateI2cInformation (
+ IN VOID
+ )
+{
+ UINT32 Index;
+
+ for (Index = 0; Index < FixedPcdGet32 (PcdNumI2cController); Index++) {
+ mI2cDesc[Index].StartDesc.Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
+ mI2cDesc[Index].StartDesc.Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
+ mI2cDesc[Index].StartDesc.ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
+ mI2cDesc[Index].StartDesc.GenFlag = 0;
+ mI2cDesc[Index].StartDesc.SpecificFlag = 0;
+ mI2cDesc[Index].StartDesc.AddrSpaceGranularity = 32;
+ mI2cDesc[Index].StartDesc.AddrRangeMin = FixedPcdGet64 (PcdI2c0BaseAddr) +
+ (Index * FixedPcdGet32 (PcdI2cSize));
+ mI2cDesc[Index].StartDesc.AddrRangeMax = mI2cDesc[Index].StartDesc.AddrRangeMin +
+ FixedPcdGet32 (PcdI2cSize) - 1;
+ mI2cDesc[Index].StartDesc.AddrTranslationOffset = 0;
+ mI2cDesc[Index].StartDesc.AddrLen = FixedPcdGet32 (PcdI2cSize);
+
+ mI2cDesc[Index].EndDesc = ACPI_END_TAG_DESCRIPTOR;
+ }
+}
+
+EFI_STATUS
+EFIAPI
+PlatformDxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ Handle = NULL;
+
+ PopulateI2cInformation ();
+
+ Status = RegisterDevice (&gNxpNonDiscoverableI2cMasterGuid,
+ &mI2cDesc[0], &Handle);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install the DS1307 I2C Master protocol on this handle so the RTC driver
+ // can identify it as the I2C master it can invoke directly.
+ //
+ Status = gBS->InstallProtocolInterface (&Handle,
+ &gDs1307RealTimeClockLibI2cMasterProtocolGuid,
+ EFI_NATIVE_INTERFACE, NULL);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v2 10/11] Compilation : Add the fdf, dsc and dec files.
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
` (8 preceding siblings ...)
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 09/11] Platform/NXP: Add Platform driver for LS1043 RDB board Meenakshi Aggarwal
@ 2019-11-21 16:25 ` Meenakshi Aggarwal
2019-11-26 16:56 ` [edk2-devel] " Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 11/11] Readme : Add Readme.md file Meenakshi Aggarwal
2020-01-24 22:25 ` [edk2-platforms] [PATCH v3 00/11] Add support of LS1043 SoC Meenakshi Aggarwal
11 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-11-21 16:25 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, devel
Cc: v.sethi, Meenakshi Aggarwal
The firmware device, description and declaration files.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 23 ++
Silicon/NXP/LS1043A/LS1043A.dec | 16 +
Silicon/NXP/NxpQoriqLs.dec | 103 ++++++
Platform/NXP/NxpQoriqLs.dsc.inc | 368 ++++++++++++++++++++
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 61 ++++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 77 ++++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 167 +++++++++
Platform/NXP/FVRules.fdf.inc | 93 +++++
8 files changed, 908 insertions(+)
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
new file mode 100644
index 000000000000..ed56db0222e4
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
@@ -0,0 +1,23 @@
+# LS1043aRdbPkg.dec
+# LS1043a board package.
+#
+# Copyright 2017-2019 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ PACKAGE_NAME = LS1043aRdbPkg
+ PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
diff --git a/Silicon/NXP/LS1043A/LS1043A.dec b/Silicon/NXP/LS1043A/LS1043A.dec
new file mode 100644
index 000000000000..cd79949790f0
--- /dev/null
+++ b/Silicon/NXP/LS1043A/LS1043A.dec
@@ -0,0 +1,16 @@
+# LS1043A.dec
+#
+# Copyright 2017-2019 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+
+[Guids.common]
+ gNxpLs1043ATokenSpaceGuid = {0x6834fe45, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
+
+[Includes]
+ Include
diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
new file mode 100644
index 000000000000..764b9bb0e2d3
--- /dev/null
+++ b/Silicon/NXP/NxpQoriqLs.dec
@@ -0,0 +1,103 @@
+# @file.
+#
+# Copyright 2017-2019 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001A
+ PACKAGE_VERSION = 0.1
+
+[Includes]
+ Include
+
+[Guids.common]
+ gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
+ gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
+
+[PcdsFixedAtBuild.common]
+ #
+ # Pcds for I2C Controller
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002
+
+ #
+ # Pcds for base address and size
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
+ gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
+ gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
+ gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x0|UINT64|0x00000104
+ gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
+ gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
+ gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
+ gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
+ gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
+ gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x0000011A
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D
+ gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x0000011E
+ gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x0000011F
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000120
+ gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000121
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123
+
+ #
+ # IFC PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
+ gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
+
+ #
+ # NV Pcd
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
+ gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211
+
+ #
+ # Platform PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
+
+ #
+ # Clock PCDs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
+ gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1
+
+ #
+ # Pcds to support Big Endian IPs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
+ gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
+ gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
new file mode 100644
index 000000000000..fa5f30dd3909
--- /dev/null
+++ b/Platform/NXP/NxpQoriqLs.dsc.inc
@@ -0,0 +1,368 @@
+# @file
+#
+# Copyright 2017-2019 NXP.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001A
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
+[LibraryClasses.common]
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+ ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+ BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+ PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+ # Networking Requirements
+ NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf
+
+ # ARM GIC400 General Interrupt Driver
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+ SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+
+[LibraryClasses.common.SEC]
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+ LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+ MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
+
+ # 1/123 faster than Stm or Vstm version
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+ # Uncomment to turn on GDB stub in SEC.
+ #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+
+[LibraryClasses.common.PEIM]
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
+
+[LibraryClasses.AARCH64]
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[BuildOptions]
+ RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu cortex-a9
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
+ GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+ # It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+ gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+[PcdsDynamicDefault.common]
+ #
+ # Set video resolution for boot options and for text setup.
+ # PlatformDxe can set the former at runtime.
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
+
+[PcdsDynamicHii.common.DEFAULT]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
+
+[PcdsFixedAtBuild.common]
+ gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|1 # Only one core
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|2000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000001
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000045
+!endif
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|20
+
+ #
+ # Optional feature to help prevent EFI memory map fragments
+ # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+ # Values are in EFI Pages (4K). DXE Core will make sure that
+ # at least this much of each type of memory can be allocated
+ # from a single memory range. This way you only end up with
+ # maximum of two fragements for each type in the memory map
+ # (the memory used, and the free memory that was prereserved
+ # but not used).
+ #
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ # Serial Terminal
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+ # Timer
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
+
+ # We want to use the Shell Libraries but don't want it to initialise
+ # automatically. We initialise the libraries when the command is called by the
+ # Shell.
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+
+ # Use the serial console for both ConIn & ConOut
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000
+!ifdef $(NO_SHELL_PROFILES)
+ gEfiShellPkgTokenSpaceGuid.PcdShellProfileMask|0x00
+!endif #$(NO_SHELL_PROFILES)
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # SEC
+ #
+ ArmPlatformPkg/PrePi/PeiUniCore.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+ # FDT installation
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ FatPkg/FatPei/FatPei.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Example Application
+ #
+ MdeModulePkg/Application/HelloWorld/HelloWorld.inf
+ ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+!ifndef $(NO_SHELL_PROFILES)
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+!endif #$(NO_SHELL_PROFILES)
+ }
+
+ ##
diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
new file mode 100644
index 000000000000..dbd680b0ad28
--- /dev/null
+++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
@@ -0,0 +1,61 @@
+# LS1043A.dsc
+# LS1043A Soc package.
+#
+# Copyright 2017-2019 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsDynamicDefault.common]
+
+ #
+ # ARM General Interrupt Controller
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
+
+[PcdsFixedAtBuild.common]
+
+ #
+ # CCSR Address Space and other attached Memories
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
+ gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
+ gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
+ gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
+ gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
+ gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x02AD0000
+ gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
+ gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
+ gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
+ gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
+
+ #
+ # Big Endian IPs
+ #
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
+ gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|TRUE
+
+##
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
new file mode 100644
index 000000000000..c8105593533f
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
@@ -0,0 +1,77 @@
+# LS1043aRdbPkg.dsc
+#
+# LS1043ARDB Board package.
+#
+# Copyright 2017-2019 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ #
+ # Defines for default states. These can be changed on the command line.
+ # -D FLAG=VALUE
+ #
+ PLATFORM_NAME = LS1043aRdbPkg
+ PLATFORM_GUID = 60169ec4-d2b4-44f8-825e-f8684fd42e4f
+ OUTPUT_DIRECTORY = Build/LS1043aRdbPkg
+ FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
+
+!include Platform/NXP/NxpQoriqLs.dsc.inc
+!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
+
+[LibraryClasses.common]
+ SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
+ ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
+ ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
+ SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
+ IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
+ RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
+
+[PcdsFixedAtBuild.common]
+
+ #
+ # LS1043a board Specific PCDs
+ # XX (DRAM - Region 1 2GB)
+ # (NOR - IFC Region 1 512MB)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
+
+ #
+ # Board Specific Pcds
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
+
+ #
+ # RTC Pcds
+ #
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
+ gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # Architectural Protocols
+ #
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <PcdsFixedAtBuild>
+ gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
+ }
+
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+ Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+
+ ##
diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
new file mode 100644
index 000000000000..8d66f36d7407
--- /dev/null
+++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
@@ -0,0 +1,167 @@
+# LS1043aRdbPkg.fdf
+#
+# FLASH layout file for LS1043a board.
+#
+# Copyright (c) 2016, Freescale Ltd. All rights reserved.
+# Copyright 2017-2019 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.LS1043ARDB_EFI]
+BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
+Size = 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
+ErasePolarity = 1
+BlockSize = 0x1
+NumBlocks = 0xED000
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+0x00000000|0x000ED000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+!include Platform/NXP/FVRules.fdf.inc
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
+BlockSize = 0x1
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
+
+ INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
+
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/FatPei/FatPei.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc
new file mode 100644
index 000000000000..c9fba65dae85
--- /dev/null
+++ b/Platform/NXP/FVRules.fdf.inc
@@ -0,0 +1,93 @@
+# FvRules.fdf.inc
+#
+# Rules for creating FD.
+#
+# Copyright 2017-2019 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v2 11/11] Readme : Add Readme.md file.
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
` (9 preceding siblings ...)
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 10/11] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
@ 2019-11-21 16:25 ` Meenakshi Aggarwal
2019-11-26 16:58 ` Leif Lindholm
2020-01-24 22:25 ` [edk2-platforms] [PATCH v3 00/11] Add support of LS1043 SoC Meenakshi Aggarwal
11 siblings, 1 reply; 254+ messages in thread
From: Meenakshi Aggarwal @ 2019-11-21 16:25 UTC (permalink / raw)
To: ard.biesheuvel, leif.lindholm, michael.d.kinney, devel
Cc: v.sethi, Meenakshi Aggarwal
Readme.md to explain how to build NXP board packages.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Platform/NXP/Readme.md | 5 +++++
Readme.md | 3 +++
2 files changed, 8 insertions(+)
diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md
new file mode 100644
index 000000000000..2d60d7cb3044
--- /dev/null
+++ b/Platform/NXP/Readme.md
@@ -0,0 +1,5 @@
+Support for all NXP boards is available in this directory.
+
+# How to build
+
+Please follow top-level Readme.md for build instructions..
diff --git a/Readme.md b/Readme.md
index 1befd0b5448a..104c33f557e5 100644
--- a/Readme.md
+++ b/Readme.md
@@ -246,6 +246,9 @@ For more information, see the
## Socionext
* [SynQuacer](Platform/Socionext/DeveloperBox)
+## NXP
+* [LS1043aRdb](Platform/NXP/LS1043aRdbPkg)
+
# Maintainers
See [Maintainers.txt](Maintainers.txt).
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* Re: [edk2-platforms] [PATCH v2 03/11] SocLib : Add support for initialization of peripherals
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 03/11] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
@ 2019-11-26 16:43 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-11-26 16:43 UTC (permalink / raw)
To: Meenakshi Aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, devel, v.sethi
I am a bit confused - none of the feedback from last review seems to
have been addressed. Comments below.
On Thu, Nov 21, 2019 at 21:55:06 +0530, Meenakshi Aggarwal wrote:
> Add SocInit function that initializes peripherals
> and print board and soc information.
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 45 ++
> Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 +++
> Silicon/NXP/Include/Chassis2/NxpSoc.h | 361 ++++++++++++++
> Silicon/NXP/Include/DramInfo.h | 38 ++
> Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 ++
> Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ++++++
> Silicon/NXP/Library/SocLib/Chassis.c | 498 ++++++++++++++++++++
> Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 162 +++++++
> Silicon/NXP/Library/SocLib/SerDes.c | 268 +++++++++++
> 9 files changed, 1621 insertions(+)
> diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
> new file mode 100644
> index 000000000000..5dda6f8c2662
> --- /dev/null
> +++ b/Silicon/NXP/Library/SocLib/Chassis.c
> @@ -0,0 +1,498 @@
> +/** @file
> + SoC specific Library containg functions to initialize various SoC components
> +
> + Copyright 2017-2019 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Base.h>
> +#ifdef CHASSIS2
> +#include <Chassis2/NxpSoc.h>
> +#elif CHASSIS3
> +#include <Chassis3/NxpSoc.h>
> +#endif
> +#include <Library/ArmSmcLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +#include <DramInfo.h>
> +#include "NxpChassis.h"
> +
> +/*
> + * Structure to list available SOCs.
> + * Name, Soc Version, Number of Cores
> + */
> +STATIC CPU_TYPE mCpuTypeList[] = {
> + CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
> + CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
> + CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
> +};
> +
> +UINT32
> +EFIAPI
> +GurRead (
> + IN UINTN Address
> + )
> +{
> + if (FixedPcdGetBool (PcdGurBigEndian)) {
> + return SwapMmioRead32 (Address);
> + } else {
> + return MmioRead32 (Address);
> + }
> +}
> +
> +/*
> + * Return the type of initiator (core or hardware accelerator)
> + */
> +UINT32
> +InitiatorType (
> + IN UINT32 Cluster,
> + IN UINTN InitId
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINT32 Idx;
> + UINT32 Type;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
> + Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
> +
> + if (Type & TP_ITYP_AV_MASK) {
> + return Type;
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * Return the mask for number of cores on this SOC.
> + */
> +UINT32
> +CpuMask (
> + VOID
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINTN ClusterIndex;
> + UINTN Count;
> + UINT32 Cluster;
> + UINT32 Type;
> + UINT32 Mask;
> + UINTN InitiatorIndex;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClusterIndex = 0;
> + Count = 0;
> + Mask = 0;
> +
> + do {
> + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> + Type = InitiatorType (Cluster, InitiatorIndex);
> + if (Type) {
> + if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) {
> + Mask |= 1 << Count;
> + }
> + Count++;
> + }
> + }
> + ClusterIndex++;
> + } while (CHECK_CLUSTER (Cluster));
> +
> + return Mask;
> +}
> +
> +/*
> + * Return the number of cores on this SOC.
> + */
> +UINTN
> +CpuNumCores (
> + VOID
> + )
> +{
> + UINTN Count;
> + UINTN Num;
> +
> + Count = 0;
> + Num = CpuMask ();
> +
> + while (Num) {
> + Count += Num & 1;
> + Num >>= 1;
> + }
> +
> + return Count;
> +}
> +
> +/*
> + * Return core's cluster
> + */
> +INT32
> +QoriqCoreToCluster (
> + IN UINTN Core
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINTN ClusterIndex;
> + UINTN Count;
> + UINT32 Cluster;
> + UINT32 Type;
> + UINTN InitiatorIndex;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClusterIndex = 0;
> + Count = 0;
> + do {
> + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> + Type = InitiatorType (Cluster, InitiatorIndex);
> + if (Type) {
> + if (Count == Core) {
> + return ClusterIndex;
> + }
> + Count++;
> + }
> + }
> + ClusterIndex++;
> + } while (CHECK_CLUSTER (Cluster));
> +
> + return -1; // cannot identify the cluster
> +}
> +
> +/*
> + * Return the type of core i.e. A53, A57 etc of inputted
> + * core number.
> + */
> +UINTN
> +QoriqCoreToType (
> + IN UINTN Core
> + )
> +{
> + CCSR_GUR *GurBase;
> + UINTN ClusterIndex;
> + UINTN Count;
> + UINT32 Cluster;
> + UINT32 Type;
> + UINTN InitiatorIndex;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> + ClusterIndex = 0;
> + Count = 0;
> +
> + do {
> + Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
> + for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
> + Type = InitiatorType (Cluster, InitiatorIndex);
> + if (Type) {
> + if (Count == Core) {
> + return Type;
> + }
> + Count++;
> + }
> + }
> + ClusterIndex++;
> + } while (CHECK_CLUSTER (Cluster));
> +
> + return EFI_NOT_FOUND; /* cannot identify the cluster */
> +}
> +
> +STATIC
> +UINTN
> +CpuMaskNext (
> + IN UINTN Cpu,
> + IN UINTN Mask
> + )
> +{
> + for (Cpu++; !((1 << Cpu) & Mask); Cpu++);
> +
> + return Cpu;
> +}
> +
> +/*
> + * Print CPU information
> + */
> +VOID
> +PrintCpuInfo (
> + VOID
> + )
> +{
> + SYS_INFO SysInfo;
> + UINTN CoreIndex;
> + UINTN Core;
> + UINT32 Type;
> + UINT32 NumCpus;
> + UINT32 Mask;
> + CHAR8 *CoreName;
> +
> + GetSysInfo (&SysInfo);
> + DEBUG ((DEBUG_INIT, "Clock Configuration:"));
> +
> + NumCpus = CpuNumCores ();
> + Mask = CpuMask ();
> +
> + for (CoreIndex = 0, Core = CpuMaskNext(-1, Mask);
> + CoreIndex < NumCpus;
> + CoreIndex++, Core = CpuMaskNext(Core, Mask))
> + {
> + if (!(CoreIndex % 3)) {
> + DEBUG ((DEBUG_INIT, "\n "));
> + }
> +
> + Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
> + switch (Type) {
> + case TY_ITYP_VERSION_A7:
> + CoreName = "A7";
> + break;
> + case TY_ITYP_VERSION_A53:
> + CoreName = "A53";
> + break;
> + case TY_ITYP_VERSION_A57:
> + CoreName = "A57";
> + break;
> + case TY_ITYP_VERSION_A72:
> + CoreName = "A72";
> + break;
> + default:
> + CoreName = " Unknown Core ";
> + }
> + DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ",
> + Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ));
> + }
> +
> + DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ));
> + DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ));
> +
> + if (SysInfo.FreqFman[0] != 0) {
> + DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ));
> + }
> +
> + DEBUG ((DEBUG_INIT, "\n"));
> +}
> +
> +/*
> + * Return system bus frequency
> + */
> +UINT64
> +GetBusFrequency (
> + VOID
> + )
> +{
> + SYS_INFO SocSysInfo;
> +
> + GetSysInfo (&SocSysInfo);
> +
> + return SocSysInfo.FreqSystemBus;
> +}
> +
> +/*
> + * Return SDXC bus frequency
> + */
> +UINT64
> +GetSdxcFrequency (
> + VOID
> + )
> +{
> + SYS_INFO SocSysInfo;
> +
> + GetSysInfo (&SocSysInfo);
> +
> + return SocSysInfo.FreqSdhc;
> +}
> +
> +/*
> + * Print Soc information
> + */
> +VOID
> +PrintSoc (
> + VOID
> + )
> +{
> + CHAR8 Buf[20];
> + CCSR_GUR *GurBase;
> + UINTN Count;
> + //
> + // Svr : System Version Register
> + //
> + UINTN Svr;
> + UINTN Ver;
> +
> + GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
> +
> + Svr = GurRead ((UINTN)&GurBase->Svr);
> + Ver = SVR_SOC_VER (Svr);
> +
> + for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
> + if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
> + AsciiStrCpyS (Buf, AsciiStrnLenS (mCpuTypeList[Count].Name, 7) + 1,
As I said in previous review - the second parameter should be sizeof (Buf).
> + (CONST CHAR8 *)mCpuTypeList[Count].Name);
> +
> + if (IS_E_PROCESSOR (Svr)) {
> + AsciiStrCatS (Buf,
> + (AsciiStrLen (Buf) + AsciiStrLen ((CONST CHAR8 *)"E") + 1),
And here too.
> + (CONST CHAR8 *)"E");
And please drop all casts to CHAR8 * in this function (as requested in
previous review) - they are not needed.
> + }
> + break;
> + }
> + }
> +
> + DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
> + Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
> +
> + return;
> +}
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [edk2-devel] [edk2-platforms] [PATCH v2 07/11] Silicon/NXP : Add MemoryInitPei Library
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 07/11] Silicon/NXP : Add MemoryInitPei Library Meenakshi Aggarwal
@ 2019-11-26 16:55 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-11-26 16:55 UTC (permalink / raw)
To: devel, meenakshi.aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, v.sethi
On Thu, Nov 21, 2019 at 21:55:10 +0530, Meenakshi Aggarwal wrote:
> Add MemoryInitPei Library for NXP platforms.
> It has changes to get DRAM information from TFA.
>
Only the feedback on the commit message has been addressed (but the
message is now fine). There were several more comments on this
patch. Please revisit and resubmit.
Best Regards,
Leif
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
> ---
> Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf | 48 +++++++
> Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c | 139 ++++++++++++++++++++
> 2 files changed, 187 insertions(+)
>
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> new file mode 100644
> index 000000000000..806da6d9ab9a
> --- /dev/null
> +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> @@ -0,0 +1,48 @@
> +#/** @file
> +#
> +# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
> +# Copyright 2019 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = ArmMemoryInitPeiLib
> + FILE_GUID = 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM DXE_DRIVER
> +
> +[Sources]
> + MemoryInitPeiLib.c
> +
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + Silicon/NXP/NxpQoriqLs.dec
> +
> +[LibraryClasses]
> + DebugLib
> + HobLib
> + ArmMmuLib
> + ArmPlatformLib
> + PcdLib
> +
> +[Guids]
> + gEfiMemoryTypeInformationGuid
> +
> +[FeaturePcd]
> + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
> +
> +[Pcd]
> + gArmTokenSpaceGuid.PcdSystemMemoryBase
> + gArmTokenSpaceGuid.PcdSystemMemorySize
> +
> +[Depex]
> + TRUE
> diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> new file mode 100644
> index 000000000000..9889d5730261
> --- /dev/null
> +++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
> @@ -0,0 +1,139 @@
> +/** @file
> +*
> +* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
> +*
> +* Copyright 2019 NXP
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Library/ArmMmuLib.h>
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +
> +#include <DramInfo.h>
> +
> +VOID
> +BuildMemoryTypeInformationHob (
> + VOID
> + );
> +
> +VOID
> +InitMmu (
> + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
> + )
> +{
> +
> + VOID *TranslationTableBase;
> + UINTN TranslationTableSize;
> + RETURN_STATUS Status;
> +
> + //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table resides in
> + // DRAM (even at the top of DRAM as it is the first permanent memory allocation)
> + Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n"));
> + }
> +}
> +
> +/*++
> +
> +Routine Description:
> +
> +
> +
> +Arguments:
> +
> + FileHandle - Handle of the file being invoked.
> + PeiServices - Describes the list of possible PEI Services.
> +
> +Returns:
> +
> + Status - EFI_SUCCESS if the boot mode could be set
> +
> +--*/
> +EFI_STATUS
> +EFIAPI
> +MemoryPeim (
> + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
> + IN UINT64 UefiMemorySize
> + )
> +{
> + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
> + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
> + EFI_PEI_HOB_POINTERS NextHob;
> + BOOLEAN Found;
> + DRAM_INFO DramInfo;
> +
> + // Get Virtual Memory Map from the Platform Library
> + ArmPlatformGetVirtualMemoryMap (&MemoryTable);
> +
> + //
> + // Ensure MemoryTable[0].Length which is size of DRAM has been set
> + // by ArmPlatformGetVirtualMemoryMap ()
> + //
> + ASSERT (MemoryTable[0].Length != 0);
> +
> + //
> + // Now, the permanent memory has been installed, we can call AllocatePages()
> + //
> + ResourceAttributes = (
> + EFI_RESOURCE_ATTRIBUTE_PRESENT |
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_TESTED
> + );
> +
> + if (GetDramBankInfo (&DramInfo)) {
> + DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
> + return EFI_UNSUPPORTED;
> + }
> +
> + while (DramInfo.NumOfDrams--) {
> + //
> + // Check if the resource for the main system memory has been declared
> + //
> + Found = FALSE;
> + NextHob.Raw = GetHobList ();
> + while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
> + if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
> + (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >= NextHob.ResourceDescriptor->PhysicalStart) &&
> + (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength <=
> + DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo.DramRegion[DramInfo.NumOfDrams].Size))
> + {
> + Found = TRUE;
> + break;
> + }
> + NextHob.Raw = GET_NEXT_HOB (NextHob);
> + }
> +
> + if (!Found) {
> + // Reserved the memory space occupied by the firmware volume
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + ResourceAttributes,
> + DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress,
> + DramInfo.DramRegion[DramInfo.NumOfDrams].Size
> + );
> + }
> + }
> +
> + // Build Memory Allocation Hob
> + InitMmu (MemoryTable);
> +
> + if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
> + // Optional feature that helps prevent EFI memory map fragmentation.
> + BuildMemoryTypeInformationHob ();
> + }
> +
> + return EFI_SUCCESS;
> +}
> --
> 1.9.1
>
>
>
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [edk2-devel] [edk2-platforms] [PATCH v2 10/11] Compilation : Add the fdf, dsc and dec files.
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 10/11] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
@ 2019-11-26 16:56 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-11-26 16:56 UTC (permalink / raw)
To: devel, meenakshi.aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, v.sethi
On Thu, Nov 21, 2019 at 21:55:13 +0530, Meenakshi Aggarwal wrote:
> The firmware device, description and declaration files.
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
I gave this patch
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
last time around.
/
Leif
> ---
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 23 ++
> Silicon/NXP/LS1043A/LS1043A.dec | 16 +
> Silicon/NXP/NxpQoriqLs.dec | 103 ++++++
> Platform/NXP/NxpQoriqLs.dsc.inc | 368 ++++++++++++++++++++
> Silicon/NXP/LS1043A/LS1043A.dsc.inc | 61 ++++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 77 ++++
> Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 167 +++++++++
> Platform/NXP/FVRules.fdf.inc | 93 +++++
> 8 files changed, 908 insertions(+)
>
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> new file mode 100644
> index 000000000000..ed56db0222e4
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
> @@ -0,0 +1,23 @@
> +# LS1043aRdbPkg.dec
> +# LS1043a board package.
> +#
> +# Copyright 2017-2019 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +[Defines]
> + PACKAGE_NAME = LS1043aRdbPkg
> + PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +# Supported Module Types:
> +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +#
> +################################################################################
> +[Includes.common]
> + Include # Root include for the package
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dec b/Silicon/NXP/LS1043A/LS1043A.dec
> new file mode 100644
> index 000000000000..cd79949790f0
> --- /dev/null
> +++ b/Silicon/NXP/LS1043A/LS1043A.dec
> @@ -0,0 +1,16 @@
> +# LS1043A.dec
> +#
> +# Copyright 2017-2019 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x0001001A
> +
> +[Guids.common]
> + gNxpLs1043ATokenSpaceGuid = {0x6834fe45, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> +
> +[Includes]
> + Include
> diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec
> new file mode 100644
> index 000000000000..764b9bb0e2d3
> --- /dev/null
> +++ b/Silicon/NXP/NxpQoriqLs.dec
> @@ -0,0 +1,103 @@
> +# @file.
> +#
> +# Copyright 2017-2019 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x0001001A
> + PACKAGE_VERSION = 0.1
> +
> +[Includes]
> + Include
> +
> +[Guids.common]
> + gNxpQoriqLsTokenSpaceGuid = {0x98657342, 0x4aee, 0x4fc6, {0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xf2}}
> + gNxpNonDiscoverableI2cMasterGuid = { 0x5f2c099c, 0x54a3, 0x4dd4, {0x9e, 0xc5, 0xe9, 0x12, 0x8c, 0x36, 0x81, 0x6a}}
> +
> +[PcdsFixedAtBuild.common]
> + #
> + # Pcds for I2C Controller
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000001
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000002
> +
> + #
> + # Pcds for base address and size
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x0|UINT64|0x00000100
> + gNxpQoriqLsTokenSpaceGuid.PcdPiFdSize|0x0|UINT32|0x00000101
> + gNxpQoriqLsTokenSpaceGuid.PcdPiFdBaseAddress|0x0|UINT64|0x00000102
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x0|UINT64|0x00000103
> + gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x0|UINT64|0x00000104
> + gNxpQoriqLsTokenSpaceGuid.PcdDdrBaseAddr|0x0|UINT64|0x00000105
> + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x0|UINT64|0x00000106
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x0|UINT64|0x00000107
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x0|UINT64|0x00000108
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x0|UINT32|0x00000109
> + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x0000010A
> + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x0000010B
> + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x0000010C
> + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x0000010D
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0|UINT64|0x0000010E
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0|UINT64|0x0000010F
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0|UINT64|0x00000110
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0|UINT64|0x00000111
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x0|UINT64|0x00000112
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x0|UINT64|0x00000113
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x0|UINT64|0x00000114
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x0|UINT64|0x00000115
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x0|UINT64|0x00000116
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x0|UINT64|0x00000117
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr|0x0|UINT64|0x0000118
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseSize|0x0|UINT64|0x0000119
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x0|UINT64|0x0000011A
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x0|UINT64|0x0000011B
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2BaseAddr|0x0|UINT64|0x0000011C
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegion2Size|0x0|UINT64|0x0000011D
> + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExBase|0x0|UINT64|0x0000011E
> + gNxpQoriqLsTokenSpaceGuid.PcdSystemMemoryExSize|0x0|UINT64|0x0000011F
> + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr|0x0|UINT32|0x00000120
> + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize|0x0|UINT32|0x00000121
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x0|UINT64|0x00000122
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000123
> +
> + #
> + # IFC PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x0|UINT64|0x00000190
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x0|UINT64|0x00000191
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0|UINT64|0x00000192
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x0|UINT64|0x00000193
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x0|UINT32|0x00000194
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x0|UINT64|0x00000195
> + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x0|UINT64|0x00000196
> +
> + #
> + # NV Pcd
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase|0x0|UINT64|0x00000210
> + gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize|0x0|UINT64|0x00000211
> +
> + #
> + # Platform PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x0|UINT32|0x00000250
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE|BOOLEAN|0x00000251
> +
> + #
> + # Clock PCDs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdSysClk|0x0|UINT64|0x000002A0
> + gNxpQoriqLsTokenSpaceGuid.PcdDdrClk|0x0|UINT64|0x000002A1
> +
> + #
> + # Pcds to support Big Endian IPs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdMmcBigEndian|FALSE|BOOLEAN|0x0000310
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311
> + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312
> + gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|FALSE|BOOLEAN|0x00000313
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314
> diff --git a/Platform/NXP/NxpQoriqLs.dsc.inc b/Platform/NXP/NxpQoriqLs.dsc.inc
> new file mode 100644
> index 000000000000..fa5f30dd3909
> --- /dev/null
> +++ b/Platform/NXP/NxpQoriqLs.dsc.inc
> @@ -0,0 +1,368 @@
> +# @file
> +#
> +# Copyright 2017-2019 NXP.
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + #
> + # Defines for default states. These can be changed on the command line.
> + # -D FLAG=VALUE
> + #
> + PLATFORM_VERSION = 0.1
> + DSC_SPECIFICATION = 0x0001001A
> + SUPPORTED_ARCHITECTURES = AARCH64
> + BUILD_TARGETS = DEBUG|RELEASE|NOOPT
> + SKUID_IDENTIFIER = DEFAULT
> +
> +[LibraryClasses.common]
> + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
> + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
> + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
> + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
> + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
> + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
> + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
> + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
> + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
> + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
> +
> + # Networking Requirements
> + NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf
> +
> + # ARM GIC400 General Interrupt Driver
> + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
> + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
> + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
> + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
> + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
> + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
> + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
> + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
> + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
> + SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
> + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
> + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
> + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
> + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
> + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
> + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
> + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
> + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
> + DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf
> + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
> + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
> + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
> + NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf
> + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
> + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
> + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
> + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
> + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf
> + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
> +
> +[LibraryClasses.common.SEC]
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
> + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
> + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
> + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
> + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
> + MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> +
> + # 1/123 faster than Stm or Vstm version
> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> +
> + # Uncomment to turn on GDB stub in SEC.
> + #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
> +
> +[LibraryClasses.common.PEIM]
> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
> + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
> + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
> +
> +[LibraryClasses.common.DXE_CORE]
> + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
> + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
> + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
> +
> +[LibraryClasses.common.DXE_DRIVER]
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> + MemoryInitPeiLib|Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
> +
> +[LibraryClasses.common.UEFI_APPLICATION]
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> +
> +[LibraryClasses.common.UEFI_DRIVER]
> + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> +
> +[LibraryClasses.common.DXE_RUNTIME_DRIVER]
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
> +
> +[LibraryClasses.AARCH64]
> + #
> + # It is not possible to prevent the ARM compiler for generic intrinsic functions.
> + # This library provides the instrinsic functions generate by a given compiler.
> + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
> + #
> + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
> +
> +[BuildOptions]
> + RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu cortex-a9
> +
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
> + GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
> + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +
> +[PcdsFeatureFlag.common]
> + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
> + # It could be set FALSE to save size.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
> + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
> +
> + # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
> + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
> + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
> + gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
> +
> +[PcdsDynamicDefault.common]
> + #
> + # Set video resolution for boot options and for text setup.
> + # PlatformDxe can set the former at runtime.
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
> +
> +[PcdsDynamicHii.common.DEFAULT]
> + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10
> +
> +[PcdsFixedAtBuild.common]
> + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
> + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
> + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
> + gArmPlatformTokenSpaceGuid.PcdCoreCount|1 # Only one core
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|2000000
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
> + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
> + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
> + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
> + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
> + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
> +
> +!if $(TARGET) == RELEASE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000001
> +!else
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x81000045
> +!endif
> +
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +
> + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|20
> +
> + #
> + # Optional feature to help prevent EFI memory map fragments
> + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
> + # Values are in EFI Pages (4K). DXE Core will make sure that
> + # at least this much of each type of memory can be allocated
> + # from a single memory range. This way you only end up with
> + # maximum of two fragements for each type in the memory map
> + # (the memory used, and the free memory that was prereserved
> + # but not used).
> + #
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
> +
> + # Serial Terminal
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
> + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
> +
> + # Timer
> + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
> +
> + # We want to use the Shell Libraries but don't want it to initialise
> + # automatically. We initialise the libraries when the command is called by the
> + # Shell.
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> +
> + # Use the serial console for both ConIn & ConOut
> + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|16000
> +!ifdef $(NO_SHELL_PROFILES)
> + gEfiShellPkgTokenSpaceGuid.PcdShellProfileMask|0x00
> +!endif #$(NO_SHELL_PROFILES)
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> + #
> + # SEC
> + #
> + ArmPlatformPkg/PrePi/PeiUniCore.inf
> + MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + }
> +
> + #
> + # DXE
> + #
> + MdeModulePkg/Core/Dxe/DxeMain.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
> + }
> + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + }
> +
> + #
> + # Architectural Protocols
> + #
> + ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> + EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> +
> + # FDT installation
> + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
> + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> + ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + FatPkg/FatPei/FatPei.inf
> + FatPkg/EnhancedFatDxe/Fat.inf
> +
> + #
> + # Bds
> + #
> + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + MdeModulePkg/Application/UiApp/UiApp.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
> + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
> + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
> + }
> + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> +
> + #
> + # Example Application
> + #
> + MdeModulePkg/Application/HelloWorld/HelloWorld.inf
> + ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> + ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> + ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> + ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> + ShellPkg/Application/Shell/Shell.inf {
> + <LibraryClasses>
> + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
> +!ifndef $(NO_SHELL_PROFILES)
> + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
> +!endif #$(NO_SHELL_PROFILES)
> + }
> +
> + ##
> diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc.inc b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> new file mode 100644
> index 000000000000..dbd680b0ad28
> --- /dev/null
> +++ b/Silicon/NXP/LS1043A/LS1043A.dsc.inc
> @@ -0,0 +1,61 @@
> +# LS1043A.dsc
> +# LS1043A Soc package.
> +#
> +# Copyright 2017-2019 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +[PcdsDynamicDefault.common]
> +
> + #
> + # ARM General Interrupt Controller
> + gArmTokenSpaceGuid.PcdGicDistributorBase|0x01401000
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x01402000
> +
> +[PcdsFixedAtBuild.common]
> +
> + #
> + # CCSR Address Space and other attached Memories
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000
> + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000
> + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000
> + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000
> + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000
> + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000
> + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000
> + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000
> + gNxpQoriqLsTokenSpaceGuid.PcdWatchdog1BaseAddr|0x02AD0000
> + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000
> + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000
> + gNxpQoriqLsTokenSpaceGuid.PcdI2cSize|0x10000
> + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000
> + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000
> +
> + #
> + # Big Endian IPs
> + #
> + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE
> + gNxpQoriqLsTokenSpaceGuid.PcdWatchdogBigEndian|TRUE
> +
> +##
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> new file mode 100644
> index 000000000000..c8105593533f
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
> @@ -0,0 +1,77 @@
> +# LS1043aRdbPkg.dsc
> +#
> +# LS1043ARDB Board package.
> +#
> +# Copyright 2017-2019 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + #
> + # Defines for default states. These can be changed on the command line.
> + # -D FLAG=VALUE
> + #
> + PLATFORM_NAME = LS1043aRdbPkg
> + PLATFORM_GUID = 60169ec4-d2b4-44f8-825e-f8684fd42e4f
> + OUTPUT_DIRECTORY = Build/LS1043aRdbPkg
> + FLASH_DEFINITION = Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> +
> +!include Platform/NXP/NxpQoriqLs.dsc.inc
> +!include Silicon/NXP/LS1043A/LS1043A.dsc.inc
> +
> +[LibraryClasses.common]
> + SocLib|Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
> + ArmPlatformLib|Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
> + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
> + SerialPortLib|Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
> + IoAccessLib|Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
> + RealTimeClockLib|Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
> +
> +[PcdsFixedAtBuild.common]
> +
> + #
> + # LS1043a board Specific PCDs
> + # XX (DRAM - Region 1 2GB)
> + # (NOR - IFC Region 1 512MB)
> + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
> + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7BE00000
> + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000
> +
> + #
> + # Board Specific Pcds
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x021c0500
> + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE
> + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1
> +
> + #
> + # RTC Pcds
> + #
> + gDs1307RtcLibTokenSpaceGuid.PcdI2cSlaveAddress|0x68
> + gDs1307RtcLibTokenSpaceGuid.PcdI2cBusFrequency|100000
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> + #
> + # Architectural Protocols
> + #
> + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
> + <PcdsFixedAtBuild>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE
> + }
> +
> + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> + Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> + Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> +
> + ##
> diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> new file mode 100644
> index 000000000000..8d66f36d7407
> --- /dev/null
> +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
> @@ -0,0 +1,167 @@
> +# LS1043aRdbPkg.fdf
> +#
> +# FLASH layout file for LS1043a board.
> +#
> +# Copyright (c) 2016, Freescale Ltd. All rights reserved.
> +# Copyright 2017-2019 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +################################################################################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into the Flash Device Image. Each FD section
> +# defines one flash "device" image. A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash" image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +################################################################################
> +
> +[FD.LS1043ARDB_EFI]
> +BaseAddress = 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device.
> +Size = 0x000ED000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device
> +ErasePolarity = 1
> +BlockSize = 0x1
> +NumBlocks = 0xED000
> +
> +################################################################################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +#
> +################################################################################
> +0x00000000|0x000ED000
> +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> +FV = FVMAIN_COMPACT
> +
> +!include Platform/NXP/FVRules.fdf.inc
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed within a flash
> +# device file. This section also defines order the components and modules are positioned
> +# within the image. The [FV] section consists of define statements, set statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +FvNameGuid = 1037c42b-8452-4c41-aac7-41e6c31468da
> +BlockSize = 0x1
> +NumBlocks = 0 # This FV gets compressed so make it just big enough
> +FvAlignment = 8 # FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF MdeModulePkg/Core/Dxe/DxeMain.inf
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +
> + #
> + # PI DXE Drivers producing Architectural Protocols (EFI Services)
> + #
> + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> +
> + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + INF Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
> + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
> + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> +
> + INF Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
> +
> + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> +
> + #
> + # Multiple Console IO support
> + #
> + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + INF FatPkg/FatPei/FatPei.inf
> + INF FatPkg/EnhancedFatDxe/Fat.inf
> +
> + #
> + # UEFI application (Shell Embedded Boot Loader)
> + #
> + INF ShellPkg/Application/Shell/Shell.inf
> +
> + #
> + # Bds
> + #
> + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + INF MdeModulePkg/Application/UiApp/UiApp.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment = 8
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF ArmPlatformPkg/PrePi/PeiUniCore.inf
> +
> + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> + }
> diff --git a/Platform/NXP/FVRules.fdf.inc b/Platform/NXP/FVRules.fdf.inc
> new file mode 100644
> index 000000000000..c9fba65dae85
> --- /dev/null
> +++ b/Platform/NXP/FVRules.fdf.inc
> @@ -0,0 +1,93 @@
> +# FvRules.fdf.inc
> +#
> +# Rules for creating FD.
> +#
> +# Copyright 2017-2019 NXP
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +################################################################################
> +#
> +# Rules are use with the [FV] section's module INF type to define
> +# how an FFS file is created for a given INF file. The following Rule are the default
> +# rules for the different module type. User can add the customized rules to define the
> +# content of the FFS file.
> +#
> +################################################################################
> +
> +[Rule.Common.SEC]
> + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> + TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + }
> +
> +[Rule.Common.PEI_CORE]
> + FILE PEI_CORE = $(NAMED_GUID) {
> + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING ="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.PEIM]
> + FILE PEIM = $(NAMED_GUID) {
> + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.PEIM.TIANOCOMPRESSED]
> + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
> + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> + }
> +
> +[Rule.Common.DXE_CORE]
> + FILE DXE_CORE = $(NAMED_GUID) {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +
> +[Rule.Common.UEFI_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.DXE_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.DXE_RUNTIME_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.UEFI_APPLICATION]
> + FILE APPLICATION = $(NAMED_GUID) {
> + UI STRING ="$(MODULE_NAME)" Optional
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + }
> +
> +[Rule.Common.UEFI_DRIVER.BINARY]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional |.depex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_APPLICATION.BINARY]
> + FILE APPLICATION = $(NAMED_GUID) {
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> + }
> --
> 1.9.1
>
>
>
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [edk2-platforms] [PATCH v2 11/11] Readme : Add Readme.md file.
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 11/11] Readme : Add Readme.md file Meenakshi Aggarwal
@ 2019-11-26 16:58 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-11-26 16:58 UTC (permalink / raw)
To: Meenakshi Aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, devel, v.sethi
On Thu, Nov 21, 2019 at 21:55:14 +0530, Meenakshi Aggarwal wrote:
> Readme.md to explain how to build NXP board packages.
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Can you resubmit just the updated files as a v3 please?
(Just delete the ones I have not commented on after git format-patch,
but before git send-email.)
Once the remaining minor issues have been addressed, this port is now
ready to go in.
Best Regards,
Leif
> ---
> Platform/NXP/Readme.md | 5 +++++
> Readme.md | 3 +++
> 2 files changed, 8 insertions(+)
>
> diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md
> new file mode 100644
> index 000000000000..2d60d7cb3044
> --- /dev/null
> +++ b/Platform/NXP/Readme.md
> @@ -0,0 +1,5 @@
> +Support for all NXP boards is available in this directory.
> +
> +# How to build
> +
> +Please follow top-level Readme.md for build instructions..
> diff --git a/Readme.md b/Readme.md
> index 1befd0b5448a..104c33f557e5 100644
> --- a/Readme.md
> +++ b/Readme.md
> @@ -246,6 +246,9 @@ For more information, see the
> ## Socionext
> * [SynQuacer](Platform/Socionext/DeveloperBox)
>
> +## NXP
> +* [LS1043aRdb](Platform/NXP/LS1043aRdbPkg)
> +
> # Maintainers
>
> See [Maintainers.txt](Maintainers.txt).
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 254+ messages in thread
* Re: [edk2-platforms] [PATCH v2 05/11] Silicon/NXP: Add support for I2c driver
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 05/11] Silicon/NXP: Add support for I2c driver Meenakshi Aggarwal
@ 2019-11-26 17:00 ` Leif Lindholm
0 siblings, 0 replies; 254+ messages in thread
From: Leif Lindholm @ 2019-11-26 17:00 UTC (permalink / raw)
To: Meenakshi Aggarwal; +Cc: ard.biesheuvel, michael.d.kinney, devel, v.sethi
On Thu, Nov 21, 2019 at 21:55:08 +0530, Meenakshi Aggarwal wrote:
> I2C driver produces gEfiI2cMasterProtocolGuid which can be
> used by other modules.
>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Sorry, I missed the
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
on this file.
No need to resubmit with v3.
> ---
>
> Notes:
> v2:
> - indentation correction
> - STATIC variable with 'm' prefix
>
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 58 ++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 100 +++
> Silicon/NXP/Drivers/I2cDxe/ComponentName.c | 179 +++++
> Silicon/NXP/Drivers/I2cDxe/DriverBinding.c | 235 +++++++
> Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 690 ++++++++++++++++++++
> 5 files changed, 1262 insertions(+)
^ permalink raw reply [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v3 00/11] Add support of LS1043 SoC
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
` (10 preceding siblings ...)
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 11/11] Readme : Add Readme.md file Meenakshi Aggarwal
@ 2020-01-24 22:25 ` Meenakshi Aggarwal
2020-01-24 22:25 ` [edk2-platforms] [PATCH v3 03/11] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
2020-01-24 22:25 ` [edk2-platforms] [PATCH v3 08/11] Silicon/NXP : Add MemoryInitPei Library Meenakshi Aggarwal
11 siblings, 2 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2020-01-24 22:25 UTC (permalink / raw)
To: ard.biesheuvel, leif, michael.d.kinney, devel; +Cc: v.sethi, Meenakshi Aggarwal
We have combined all review comments recieved till now.
Sending only below 2 patches from patch set which has modification:
1. SocLib : Add support for initialization of peripherals
2. Silicon/NXP : Add MemoryInitPei Library
- swapped patch 7 and 8 as suggested in review comments.
Following patches will add support of LS1043 SoC in edk2-platforms.
We will send patches to support LX2160, LS2088 and LS1046 SoC after LS1043 gets merged.
Our directory structure is:
edk2-platforms
|-- Platform
| |-- NXP
| | |-- FVRules.fdf.inc
| | |-- LS1043aRdbPkg
| | | |-- Drivers
| | | | `-- PlatformDxe
| | | | |-- PlatformDxe.c
| | | | `-- PlatformDxe.inf
| | | |-- Library
| | | | `-- PlatformLib
| | | | |-- ArmPlatformLib.c
| | | | |-- ArmPlatformLib.inf
| | | | |-- NxpQoriqLsHelper.S
| | | | `-- NxpQoriqLsMem.c
| | | |-- LS1043aRdbPkg.dec
| | | |-- LS1043aRdbPkg.dsc
| | | `-- LS1043aRdbPkg.fdf
| | |-- NxpQoriqLs.dsc.inc
| | `-- Readme.md
|-- Silicon
| |-- Maxim
| | `-- Library
| | `-- Ds1307RtcLib
| | |-- Ds1307Rtc.h
| | |-- Ds1307RtcLib.c
| | |-- Ds1307RtcLib.dec
| | `-- Ds1307RtcLib.inf
| |-- NXP
| | |-- Drivers
| | | |-- I2cDxe
| | | | |-- ComponentName.c
| | | | |-- DriverBinding.c
| | | | |-- I2cDxe.c
| | | | |-- I2cDxe.h
| | | | `-- I2cDxe.inf
| | |-- Include
| | | |-- Chassis2
| | | | |-- LsSerDes.h
| | | | `-- NxpSoc.h
| | | |-- DramInfo.h
| | | `-- Library
| | | `-- IoAccessLib.h
| | |-- Library
| | | |-- DUartPortLib
| | | | |-- DUart.h
| | | | |-- DUartPortLib.c
| | | | `-- DUartPortLib.inf
| | | |-- IoAccessLib
| | | | |-- IoAccessLib.c
| | | | `-- IoAccessLib.inf
| | | |-- MemoryInitPei
| | | | |-- MemoryInitPeiLib.c
| | | | `-- MemoryInitPeiLib.inf
| | | |-- Pcf8563RealTimeClockLib
| | | | |-- Pcf8563RealTimeClockLib.c
| | | | |-- Pcf8563RealTimeClockLib.dec
| | | | `-- Pcf8563RealTimeClockLib.inf
| | | `-- SocLib
| | | |-- Chassis2
| | | | `-- Soc.c
| | | |-- Chassis.c
| | | |-- LS1043aSocLib.inf
| | | |-- NxpChassis.h
| | | `-- SerDes.c
| | |-- LS1043A
| | | |-- Include
| | | | `-- SocSerDes.h
| | | |-- LS1043A.dec
| | | `-- LS1043A.dsc.inc
| | `-- NxpQoriqLs.dec
In Silicon/NXP, we are keeping our SoC specific information and all Drivers and Library which are used by SoCs.
Platform/NXP/ will host our board packages and build script.
Board specific libraries and header files will reside inside board package.
Looking forward for your kind support in upstreaming our boards in edk2-platforms.
Meenakshi Aggarwal (11):
Silicon/NXP: Add Library to provide Mmio APIs with swapped data.
Silicon/NXP: Add function to return swapped Mmio APIs pointer
SocLib : Add support for initialization of peripherals
Silicon/NXP : Add support for DUART library
Silicon/NXP: Add support for I2c driver
Silicon/Maxim : Add support for DS1307 RTC library
Platform/NXP: Add support for ArmPlatformLib
Silicon/NXP : Add MemoryInitPei Library
Platform/NXP: Add Platform driver for LS1043 RDB board
Compilation : Add the fdf, dsc and dec files.
Readme : Add Readme.md file.
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec | 23 +
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec | 23 +
Silicon/NXP/LS1043A/LS1043A.dec | 16 +
Silicon/NXP/NxpQoriqLs.dec | 103 +++
Platform/NXP/NxpQoriqLs.dsc.inc | 368 +++++++++++
Silicon/NXP/LS1043A/LS1043A.dsc.inc | 61 ++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 77 +++
Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 167 +++++
Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf | 52 ++
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 55 ++
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf | 40 ++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf | 58 ++
Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf | 34 +
Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf | 26 +
Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf | 48 ++
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 45 ++
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h | 48 ++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.h | 100 +++
Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 ++
Silicon/NXP/Include/Chassis2/NxpSoc.h | 361 ++++++++++
Silicon/NXP/Include/DramInfo.h | 38 ++
Silicon/NXP/Include/Library/IoAccessLib.h | 326 +++++++++
Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 ++
Silicon/NXP/Library/DUartPortLib/DUart.h | 122 ++++
Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ++++
Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c | 114 ++++
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c | 98 +++
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 144 ++++
Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c | 372 +++++++++++
Silicon/NXP/Drivers/I2cDxe/ComponentName.c | 179 +++++
Silicon/NXP/Drivers/I2cDxe/DriverBinding.c | 235 +++++++
Silicon/NXP/Drivers/I2cDxe/I2cDxe.c | 690 ++++++++++++++++++++
Silicon/NXP/Library/DUartPortLib/DUartPortLib.c | 364 +++++++++++
Silicon/NXP/Library/IoAccessLib/IoAccessLib.c | 404 ++++++++++++
Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c | 140 ++++
Silicon/NXP/Library/SocLib/Chassis.c | 495 ++++++++++++++
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 162 +++++
Silicon/NXP/Library/SocLib/SerDes.c | 268 ++++++++
Platform/NXP/FVRules.fdf.inc | 93 +++
Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S | 31 +
Platform/NXP/Readme.md | 5 +
Readme.md | 3 +
42 files changed, 6237 insertions(+)
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dec
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.dec
create mode 100644 Silicon/NXP/LS1043A/LS1043A.dec
create mode 100644 Silicon/NXP/NxpQoriqLs.dec
create mode 100644 Platform/NXP/NxpQoriqLs.dsc.inc
create mode 100644 Silicon/NXP/LS1043A/LS1043A.dsc.inc
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc
create mode 100644 Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.inf
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.inf
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.inf
create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.inf
create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
create mode 100644 Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307Rtc.h
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.h
create mode 100644 Silicon/NXP/Include/Chassis2/LsSerDes.h
create mode 100644 Silicon/NXP/Include/Chassis2/NxpSoc.h
create mode 100644 Silicon/NXP/Include/DramInfo.h
create mode 100644 Silicon/NXP/Include/Library/IoAccessLib.h
create mode 100644 Silicon/NXP/LS1043A/Include/SocSerDes.h
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUart.h
create mode 100644 Silicon/NXP/Library/SocLib/NxpChassis.h
create mode 100644 Platform/NXP/LS1043aRdbPkg/Drivers/PlatformDxe/PlatformDxe.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.c
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c
create mode 100644 Silicon/Maxim/Library/Ds1307RtcLib/Ds1307RtcLib.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/ComponentName.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/DriverBinding.c
create mode 100644 Silicon/NXP/Drivers/I2cDxe/I2cDxe.c
create mode 100644 Silicon/NXP/Library/DUartPortLib/DUartPortLib.c
create mode 100644 Silicon/NXP/Library/IoAccessLib/IoAccessLib.c
create mode 100644 Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
create mode 100644 Silicon/NXP/Library/SocLib/Chassis.c
create mode 100644 Silicon/NXP/Library/SocLib/Chassis2/Soc.c
create mode 100644 Silicon/NXP/Library/SocLib/SerDes.c
create mode 100644 Platform/NXP/FVRules.fdf.inc
create mode 100644 Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S
create mode 100644 Platform/NXP/Readme.md
--
1.9.1
^ permalink raw reply [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v3 03/11] SocLib : Add support for initialization of peripherals
2020-01-24 22:25 ` [edk2-platforms] [PATCH v3 00/11] Add support of LS1043 SoC Meenakshi Aggarwal
@ 2020-01-24 22:25 ` Meenakshi Aggarwal
2020-01-24 22:25 ` [edk2-platforms] [PATCH v3 08/11] Silicon/NXP : Add MemoryInitPei Library Meenakshi Aggarwal
1 sibling, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2020-01-24 22:25 UTC (permalink / raw)
To: ard.biesheuvel, leif, michael.d.kinney, devel; +Cc: v.sethi, Meenakshi Aggarwal
Add SocInit function that initializes peripherals
and print board and soc information.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Library/SocLib/LS1043aSocLib.inf | 45 ++
Silicon/NXP/Include/Chassis2/LsSerDes.h | 62 +++
Silicon/NXP/Include/Chassis2/NxpSoc.h | 361 ++++++++++++++
Silicon/NXP/Include/DramInfo.h | 38 ++
Silicon/NXP/LS1043A/Include/SocSerDes.h | 51 ++
Silicon/NXP/Library/SocLib/NxpChassis.h | 136 ++++++
Silicon/NXP/Library/SocLib/Chassis.c | 495 ++++++++++++++++++++
Silicon/NXP/Library/SocLib/Chassis2/Soc.c | 162 +++++++
Silicon/NXP/Library/SocLib/SerDes.c | 268 +++++++++++
9 files changed, 1618 insertions(+)
diff --git a/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
new file mode 100644
index 000000000000..cb670a12797e
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/LS1043aSocLib.inf
@@ -0,0 +1,45 @@
+# @file
+#
+# Copyright 2017-2019 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = SocLib
+ FILE_GUID = e868c5ca-9729-43ae-bff4-438c67de8c68
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SocLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+ Silicon/NXP/LS1043A/LS1043A.dec
+
+[LibraryClasses]
+ ArmSmcLib
+ BaseLib
+ DebugLib
+ IoAccessLib
+ SerialPortLib
+
+[Sources.common]
+ Chassis.c
+ Chassis2/Soc.c
+ SerDes.c
+
+[BuildOptions]
+ GCC:*_*_*_CC_FLAGS = -DCHASSIS2
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+ gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian
+ gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv
+ gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr
+ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled
diff --git a/Silicon/NXP/Include/Chassis2/LsSerDes.h b/Silicon/NXP/Include/Chassis2/LsSerDes.h
new file mode 100644
index 000000000000..9afbc522398a
--- /dev/null
+++ b/Silicon/NXP/Include/Chassis2/LsSerDes.h
@@ -0,0 +1,62 @@
+/** LsSerDes.h
+ The Header file of SerDes Module for Chassis 2
+
+ Copyright 2017-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef LS_SERDES_H_
+#define LS_SERDES_H_
+
+#include <Uefi/UefiBaseType.h>
+
+#define SRDS_MAX_LANES 4
+
+typedef enum {
+ None = 0,
+ Pcie1,
+ Pcie2,
+ Pcie3,
+ Sata,
+ SgmiiFm1Dtsec1,
+ SgmiiFm1Dtsec2,
+ SgmiiFm1Dtsec5,
+ SgmiiFm1Dtsec6,
+ SgmiiFm1Dtsec9,
+ SgmiiFm1Dtsec10,
+ QsgmiiFm1A,
+ XfiFm1Mac9,
+ XfiFm1Mac10,
+ Sgmii2500Fm1Dtsec2,
+ Sgmii2500Fm1Dtsec5,
+ Sgmii2500Fm1Dtsec9,
+ Sgmii2500Fm1Dtsec10,
+ SerdesPrtclCount
+} SERDES_PROTOCOL;
+
+typedef enum {
+ Srds1 = 0,
+ Srds2,
+ SrdsMaxNum
+} SERDES_NUMBER;
+
+typedef struct {
+ UINT16 Protocol;
+ UINT8 SrdsLane[SRDS_MAX_LANES];
+} SERDES_CONFIG;
+
+typedef VOID
+(*SERDES_PROBE_LANES_CALLBACK) (
+ IN SERDES_PROTOCOL LaneProtocol,
+ IN VOID *Arg
+ );
+
+VOID
+SerDesProbeLanes(
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ );
+
+#endif /* LS_SERDES_H_ */
diff --git a/Silicon/NXP/Include/Chassis2/NxpSoc.h b/Silicon/NXP/Include/Chassis2/NxpSoc.h
new file mode 100644
index 000000000000..f05a813750e8
--- /dev/null
+++ b/Silicon/NXP/Include/Chassis2/NxpSoc.h
@@ -0,0 +1,361 @@
+/** Soc.h
+* Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+* Copyright 2017-2019 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef NXP_SOC_H_
+#define NXP_SOC_H_
+
+#define HWA_CGA_M1_CLK_SEL 0xe0000000
+#define HWA_CGA_M1_CLK_SHIFT 29
+
+#define TP_CLUSTER_EOC_MASK 0xc0000000 /* end of clusters mask */
+#define NUM_CC_PLLS 2
+#define CLK_FREQ 100000000
+#define MAX_CPUS 4
+#define NUM_FMAN 1
+#define CHECK_CLUSTER(Cluster) ((Cluster & TP_CLUSTER_EOC_MASK) == 0x0)
+
+/* RCW SERDES MACRO */
+#define RCWSR_INDEX 4
+#define RCWSR_SRDS1_PRTCL_MASK 0xffff0000
+#define RCWSR_SRDS1_PRTCL_SHIFT 16
+#define RCWSR_SRDS2_PRTCL_MASK 0x0000ffff
+#define RCWSR_SRDS2_PRTCL_SHIFT 0
+
+/* SMMU Defintions */
+#define SMMU_BASE_ADDR 0x09000000
+#define SMMU_REG_SCR0 (SMMU_BASE_ADDR + 0x0)
+#define SMMU_REG_SACR (SMMU_BASE_ADDR + 0x10)
+#define SMMU_REG_IDR1 (SMMU_BASE_ADDR + 0x24)
+#define SMMU_REG_NSCR0 (SMMU_BASE_ADDR + 0x400)
+#define SMMU_REG_NSACR (SMMU_BASE_ADDR + 0x410)
+
+#define SCR0_USFCFG_MASK 0x00000400
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SACR_PAGESIZE_MASK 0x00010000
+#define IDR1_PAGESIZE_MASK 0x80000000
+
+typedef struct {
+ UINTN FreqProcessor[MAX_CPUS];
+ UINTN FreqSystemBus;
+ UINTN FreqDdrBus;
+ UINTN FreqLocalBus;
+ UINTN FreqSdhc;
+ UINTN FreqFman[NUM_FMAN];
+ UINTN FreqQman;
+} SYS_INFO;
+
+/* Device Configuration and Pin Control */
+typedef struct {
+ UINT32 PorSr1; /* POR status 1 */
+#define CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
+ UINT32 PorSr2; /* POR status 2 */
+ UINT8 Res008[0x20-0x8];
+ UINT32 GppOrCr1; /* General-purpose POR configuration */
+ UINT32 GppOrCr2;
+ UINT32 DcfgFuseSr; /* Fuse status register */
+ UINT8 Res02c[0x70-0x2c];
+ UINT32 DevDisr; /* Device disable control */
+ UINT32 DevDisr2; /* Device disable control 2 */
+ UINT32 DevDisr3; /* Device disable control 3 */
+ UINT32 DevDisr4; /* Device disable control 4 */
+ UINT32 DevDisr5; /* Device disable control 5 */
+ UINT32 DevDisr6; /* Device disable control 6 */
+ UINT32 DevDisr7; /* Device disable control 7 */
+ UINT8 Res08c[0x94-0x8c];
+ UINT32 CoreDisrU; /* uppper portion for support of 64 cores */
+ UINT32 CoreDisrL; /* lower portion for support of 64 cores */
+ UINT8 Res09c[0xa0-0x9c];
+ UINT32 Pvr; /* Processor version */
+ UINT32 Svr; /* System version */
+ UINT32 Mvr; /* Manufacturing version */
+ UINT8 Res0ac[0xb0-0xac];
+ UINT32 RstCr; /* Reset control */
+ UINT32 RstRqPblSr; /* Reset request preboot loader status */
+ UINT8 Res0b8[0xc0-0xb8];
+ UINT32 RstRqMr1; /* Reset request mask */
+ UINT8 Res0c4[0xc8-0xc4];
+ UINT32 RstRqSr1; /* Reset request status */
+ UINT8 Res0cc[0xd4-0xcc];
+ UINT32 RstRqWdTmrL; /* Reset request WDT mask */
+ UINT8 Res0d8[0xdc-0xd8];
+ UINT32 RstRqWdtSrL; /* Reset request WDT status */
+ UINT8 Res0e0[0xe4-0xe0];
+ UINT32 BrrL; /* Boot release */
+ UINT8 Res0e8[0x100-0xe8];
+ UINT32 RcwSr[16]; /* Reset control word status */
+#define CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
+#define CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
+#define CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
+#define CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
+ UINT8 Res140[0x200-0x140];
+ UINT32 ScratchRw[4]; /* Scratch Read/Write */
+ UINT8 Res210[0x300-0x210];
+ UINT32 ScratcHw1R[4]; /* Scratch Read (Write once) */
+ UINT8 Res310[0x400-0x310];
+ UINT32 CrstSr[12];
+ UINT8 Res430[0x500-0x430];
+ /* PCI Express n Logical I/O Device Number register */
+ UINT32 DcfgCcsrPex1LiodNr;
+ UINT32 DcfgCcsrPex2LiodNr;
+ UINT32 DcfgCcsrPex3LiodNr;
+ UINT32 DcfgCcsrPex4LiodNr;
+ /* RIO n Logical I/O Device Number register */
+ UINT32 DcfgCcsrRio1LiodNr;
+ UINT32 DcfgCcsrRio2LiodNr;
+ UINT32 DcfgCcsrRio3LiodNr;
+ UINT32 DcfgCcsrRio4LiodNr;
+ /* USB Logical I/O Device Number register */
+ UINT32 DcfgCcsrUsb1LiodNr;
+ UINT32 DcfgCcsrUsb2LiodNr;
+ UINT32 DcfgCcsrUsb3LiodNr;
+ UINT32 DcfgCcsrUsb4LiodNr;
+ /* SD/MMC Logical I/O Device Number register */
+ UINT32 DcfgCcsrSdMmc1LiodNr;
+ UINT32 DcfgCcsrSdMmc2LiodNr;
+ UINT32 DcfgCcsrSdMmc3LiodNr;
+ UINT32 DcfgCcsrSdMmc4LiodNr;
+ /* RIO Message Unit Logical I/O Device Number register */
+ UINT32 DcfgCcsrRiomaintLiodNr;
+ UINT8 Res544[0x550-0x544];
+ UINT32 SataLiodNr[4];
+ UINT8 Res560[0x570-0x560];
+ UINT32 DcfgCcsrMisc1LiodNr;
+ UINT32 DcfgCcsrMisc2LiodNr;
+ UINT32 DcfgCcsrMisc3LiodNr;
+ UINT32 DcfgCcsrMisc4LiodNr;
+ UINT32 DcfgCcsrDma1LiodNr;
+ UINT32 DcfgCcsrDma2LiodNr;
+ UINT32 DcfgCcsrDma3LiodNr;
+ UINT32 DcfgCcsrDma4LiodNr;
+ UINT32 DcfgCcsrSpare1LiodNr;
+ UINT32 DcfgCcsrSpare2LiodNr;
+ UINT32 DcfgCcsrSpare3LiodNr;
+ UINT32 DcfgCcsrSpare4LiodNr;
+ UINT8 Res5a0[0x600-0x5a0];
+ UINT32 DcfgCcsrPblSr;
+ UINT32 PamuBypENr;
+ UINT32 DmaCr1;
+ UINT8 Res60c[0x610-0x60c];
+ UINT32 DcfgCcsrGenSr1;
+ UINT32 DcfgCcsrGenSr2;
+ UINT32 DcfgCcsrGenSr3;
+ UINT32 DcfgCcsrGenSr4;
+ UINT32 DcfgCcsrGenCr1;
+ UINT32 DcfgCcsrGenCr2;
+ UINT32 DcfgCcsrGenCr3;
+ UINT32 DcfgCcsrGenCr4;
+ UINT32 DcfgCcsrGenCr5;
+ UINT32 DcfgCcsrGenCr6;
+ UINT32 DcfgCcsrGenCr7;
+ UINT8 Res63c[0x658-0x63c];
+ UINT32 DcfgCcsrcGenSr1;
+ UINT32 DcfgCcsrcGenSr0;
+ UINT8 Res660[0x678-0x660];
+ UINT32 DcfgCcsrcGenCr1;
+ UINT32 DcfgCcsrcGenCr0;
+ UINT8 Res680[0x700-0x680];
+ UINT32 DcfgCcsrSrIoPstecr;
+ UINT32 DcfgCcsrDcsrCr;
+ UINT8 Res708[0x740-0x708]; /* add more registers when needed */
+ UINT32 TpItyp[64]; /* Topology Initiator Type Register */
+ struct {
+ UINT32 Upper;
+ UINT32 Lower;
+ } TpCluster[16];
+ UINT8 Res8c0[0xa00-0x8c0]; /* add more registers when needed */
+ UINT32 DcfgCcsrQmBmWarmRst;
+ UINT8 Resa04[0xa20-0xa04]; /* add more registers when needed */
+ UINT32 DcfgCcsrReserved0;
+ UINT32 DcfgCcsrReserved1;
+} CCSR_GUR;
+
+/* Supplemental Configuration Unit */
+typedef struct {
+ UINT8 Res000[0x070-0x000];
+ UINT32 Usb1Prm1Cr;
+ UINT32 Usb1Prm2Cr;
+ UINT32 Usb1Prm3Cr;
+ UINT32 Usb2Prm1Cr;
+ UINT32 Usb2Prm2Cr;
+ UINT32 Usb2Prm3Cr;
+ UINT32 Usb3Prm1Cr;
+ UINT32 Usb3Prm2Cr;
+ UINT32 Usb3Prm3Cr;
+ UINT8 Res094[0x100-0x094];
+ UINT32 Usb2Icid;
+ UINT32 Usb3Icid;
+ UINT8 Res108[0x114-0x108];
+ UINT32 DmaIcid;
+ UINT32 SataIcid;
+ UINT32 Usb1Icid;
+ UINT32 QeIcid;
+ UINT32 SdhcIcid;
+ UINT32 EdmaIcid;
+ UINT32 EtrIcid;
+ UINT32 Core0SftRst;
+ UINT32 Core1SftRst;
+ UINT32 Core2SftRst;
+ UINT32 Core3SftRst;
+ UINT8 Res140[0x158-0x140];
+ UINT32 AltCBar;
+ UINT32 QspiCfg;
+ UINT8 Res160[0x180-0x160];
+ UINT32 DmaMcr;
+ UINT8 Res184[0x188-0x184];
+ UINT32 GicAlign;
+ UINT32 DebugIcid;
+ UINT8 Res190[0x1a4-0x190];
+ UINT32 SnpCnfGcr;
+#define CCSR_SCFG_SNPCNFGCR_SECRDSNP BIT31
+#define CCSR_SCFG_SNPCNFGCR_SECWRSNP BIT30
+#define CCSR_SCFG_SNPCNFGCR_SATARDSNP BIT23
+#define CCSR_SCFG_SNPCNFGCR_SATAWRSNP BIT22
+#define CCSR_SCFG_SNPCNFGCR_USB1RDSNP BIT21
+#define CCSR_SCFG_SNPCNFGCR_USB1WRSNP BIT20
+#define CCSR_SCFG_SNPCNFGCR_USB2RDSNP BIT15
+#define CCSR_SCFG_SNPCNFGCR_USB2WRSNP BIT16
+#define CCSR_SCFG_SNPCNFGCR_USB3RDSNP BIT13
+#define CCSR_SCFG_SNPCNFGCR_USB3WRSNP BIT14
+ UINT8 Res1a8[0x1ac-0x1a8];
+ UINT32 IntpCr;
+ UINT8 Res1b0[0x204-0x1b0];
+ UINT32 CoreSrEnCr;
+ UINT8 Res208[0x220-0x208];
+ UINT32 RvBar00;
+ UINT32 RvBar01;
+ UINT32 RvBar10;
+ UINT32 RvBar11;
+ UINT32 RvBar20;
+ UINT32 RvBar21;
+ UINT32 RvBar30;
+ UINT32 RvBar31;
+ UINT32 LpmCsr;
+ UINT8 Res244[0x400-0x244];
+ UINT32 QspIdQScr;
+ UINT32 EcgTxcMcr;
+ UINT32 SdhcIoVSelCr;
+ UINT32 RcwPMuxCr0;
+ /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+ *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+ *Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS
+ Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS*/
+#define CCSR_SCFG_RCWPMUXCRO_SELCR_USB 0x3333
+ /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS
+ *Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT
+ *Setting RCW PinMux Register bits 25-27 to select IIC4_SCL
+ Setting RCW PinMux Register bits 29-31 to select IIC4_SDA*/
+#define CCSR_SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300
+ UINT32 UsbDrvVBusSelCr;
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
+#define CCSR_SCFG_USBDRVVBUS_SELCR_USB3 0x00000003
+ UINT32 UsbPwrFaultSelCr;
+#define CCSR_SCFG_USBPWRFAULT_INACTIVE 0x00000000
+#define CCSR_SCFG_USBPWRFAULT_SHARED 0x00000001
+#define CCSR_SCFG_USBPWRFAULT_DEDICATED 0x00000002
+#define CCSR_SCFG_USBPWRFAULT_USB3_SHIFT 4
+#define CCSR_SCFG_USBPWRFAULT_USB2_SHIFT 2
+#define CCSR_SCFG_USBPWRFAULT_USB1_SHIFT 0
+ UINT32 UsbRefclkSelcr1;
+ UINT32 UsbRefclkSelcr2;
+ UINT32 UsbRefclkSelcr3;
+ UINT8 Res424[0x600-0x424];
+ UINT32 ScratchRw[4];
+ UINT8 Res610[0x680-0x610];
+ UINT32 CoreBCr;
+ UINT8 Res684[0x1000-0x684];
+ UINT32 Pex1MsiIr;
+ UINT32 Pex1MsiR;
+ UINT8 Res1008[0x2000-0x1008];
+ UINT32 Pex2;
+ UINT32 Pex2MsiR;
+ UINT8 Res2008[0x3000-0x2008];
+ UINT32 Pex3MsiIr;
+ UINT32 Pex3MsiR;
+} CCSR_SCFG;
+
+#define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
+#define USB_PHY_RX_EQ_VAL_1 0x0000
+#define USB_PHY_RX_EQ_VAL_2 0x8000
+#define USB_PHY_RX_EQ_VAL_3 0x8003
+#define USB_PHY_RX_EQ_VAL_4 0x800b
+
+/*USB_PHY_SS memory map*/
+typedef struct {
+ UINT16 IpIdcodeLo;
+ UINT16 SupIdcodeHi;
+ UINT8 Res4[0x0006-0x0004];
+ UINT16 RtuneDebug;
+ UINT16 RtuneStat;
+ UINT16 SupSsPhase;
+ UINT16 SsFreq;
+ UINT8 ResE[0x0020-0x000e];
+ UINT16 Ateovrd;
+ UINT16 MpllOvrdInLo;
+ UINT8 Res24[0x0026-0x0024];
+ UINT16 SscOvrdIn;
+ UINT8 Res28[0x002A-0x0028];
+ UINT16 LevelOvrdIn;
+ UINT8 Res2C[0x0044-0x002C];
+ UINT16 ScopeCount;
+ UINT8 Res46[0x0060-0x0046];
+ UINT16 MpllLoopCtl;
+ UINT8 Res62[0x006C-0x0062];
+ UINT16 SscClkCntrl;
+ UINT8 Res6E[0x2002-0x006E];
+ UINT16 Lane0TxOvrdInHi;
+ UINT16 Lane0TxOvrdDrvLo;
+ UINT8 Res2006[0x200C-0x2006];
+ UINT16 Lane0RxOvrdInHi;
+ UINT8 Res200E[0x2022-0x200E];
+ UINT16 Lane0TxCmWaitTimeOvrd;
+ UINT8 Res2024[0x202A-0x2024];
+ UINT16 Lane0TxLbertCtl;
+ UINT16 Lane0RxLbertCtl;
+ UINT16 Lane0RxLbertErr;
+ UINT8 Res2030[0x205A-0x2030];
+ UINT16 Lane0TxAltBlock;
+} CCSR_USB_PHY;
+
+/* Clocking */
+typedef struct {
+ struct {
+ UINT32 ClkCnCSr; /* core cluster n clock control status */
+ UINT8 Res004[0x0c];
+ UINT32 ClkcGHwAcSr; /* Clock generator n hardware accelerator */
+ UINT8 Res014[0x0c];
+ } ClkcSr[4];
+ UINT8 Res040[0x780]; /* 0x100 */
+ struct {
+ UINT32 PllCnGSr;
+ UINT8 Res804[0x1c];
+ } PllCgSr[NUM_CC_PLLS];
+ UINT8 Res840[0x1c0];
+ UINT32 ClkPCSr; /* 0xa00 Platform clock domain control/status */
+ UINT8 Resa04[0x1fc];
+ UINT32 PllPGSr; /* 0xc00 Platform PLL General Status */
+ UINT8 Resc04[0x1c];
+ UINT32 PllDGSr; /* 0xc20 DDR PLL General Status */
+ UINT8 Resc24[0x3dc];
+} CCSR_CLOCK;
+
+VOID
+GetSysInfo (
+ OUT SYS_INFO *
+ );
+
+UINT32
+EFIAPI
+GurRead (
+ IN UINTN Address
+ );
+
+#endif /* NXP_SOC_H_ */
diff --git a/Silicon/NXP/Include/DramInfo.h b/Silicon/NXP/Include/DramInfo.h
new file mode 100644
index 000000000000..a934aaeff1f5
--- /dev/null
+++ b/Silicon/NXP/Include/DramInfo.h
@@ -0,0 +1,38 @@
+/** @file
+* Header defining the structure for Dram Information
+*
+* Copyright 2019 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef DRAM_INFO_H_
+#define DRAM_INFO_H_
+
+#include <Uefi/UefiBaseType.h>
+
+#define SMC_DRAM_BANK_INFO (0xC200FF12)
+
+typedef struct {
+ UINTN BaseAddress;
+ UINTN Size;
+} DRAM_REGION_INFO;
+
+typedef struct {
+ UINT32 NumOfDrams;
+ UINT32 Reserved;
+ DRAM_REGION_INFO DramRegion[3];
+} DRAM_INFO;
+
+EFI_STATUS
+GetDramBankInfo (
+ IN OUT DRAM_INFO *DramInfo
+ );
+
+VOID
+UpdateDpaaDram (
+ IN OUT DRAM_INFO *DramInfo
+ );
+
+#endif /* DRAM_INFO_H_ */
diff --git a/Silicon/NXP/LS1043A/Include/SocSerDes.h b/Silicon/NXP/LS1043A/Include/SocSerDes.h
new file mode 100644
index 000000000000..2d1c6f10f932
--- /dev/null
+++ b/Silicon/NXP/LS1043A/Include/SocSerDes.h
@@ -0,0 +1,51 @@
+/** @file
+ The Header file of SerDes Module for LS1043A
+
+ Copyright 2017-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SOC_SERDES_H_
+#define SOC_SERDES_H_
+
+#ifdef CHASSIS2
+#include <Chassis2/LsSerDes.h>
+#endif
+
+SERDES_CONFIG SerDes1ConfigTbl[] = {
+ /* SerDes 1 */
+ {0x1555, {XfiFm1Mac9, Pcie1, Pcie2, Pcie3 } },
+ {0x2555, {Sgmii2500Fm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
+ {0x4555, {QsgmiiFm1A, Pcie1, Pcie2, Pcie3 } },
+ {0x4558, {QsgmiiFm1A, Pcie1, Pcie2, Sata } },
+ {0x1355, {XfiFm1Mac9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
+ {0x2355, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
+ {0x3335, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, Pcie3 } },
+ {0x3355, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Pcie3 } },
+ {0x3358, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, Pcie2, Sata } },
+ {0x3555, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Pcie3 } },
+ {0x3558, {SgmiiFm1Dtsec9, Pcie1, Pcie2, Sata } },
+ {0x7000, {Pcie1, Pcie1, Pcie1, Pcie1 } },
+ {0x9998, {Pcie1, Pcie2, Pcie3, Sata } },
+ {0x6058, {Pcie1, Pcie1, Pcie2, Sata } },
+ {0x1455, {XfiFm1Mac9, QsgmiiFm1A, Pcie2, Pcie3 } },
+ {0x2455, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
+ {0x2255, {Sgmii2500Fm1Dtsec9, Sgmii2500Fm1Dtsec2, Pcie2, Pcie3 } },
+ {0x3333, {SgmiiFm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
+ {0x1460, {XfiFm1Mac9, QsgmiiFm1A, Pcie3, Pcie3 } },
+ {0x2460, {Sgmii2500Fm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
+ {0x3460, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie3, Pcie3 } },
+ {0x3455, {SgmiiFm1Dtsec9, QsgmiiFm1A, Pcie2, Pcie3 } },
+ {0x9960, {Pcie1, Pcie2, Pcie3, Pcie3 } },
+ {0x2233, {Sgmii2500Fm1Dtsec9, SgmiiFm1Dtsec2, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 }},
+ {0x2533, {Sgmii2500Fm1Dtsec9, Pcie1, SgmiiFm1Dtsec5, SgmiiFm1Dtsec6 } },
+ {}
+};
+
+SERDES_CONFIG *SerDesConfigTbl[] = {
+ SerDes1ConfigTbl
+};
+
+#endif /* SOC_SERDES_H_ */
diff --git a/Silicon/NXP/Library/SocLib/NxpChassis.h b/Silicon/NXP/Library/SocLib/NxpChassis.h
new file mode 100644
index 000000000000..99f6439d8f35
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/NxpChassis.h
@@ -0,0 +1,136 @@
+/** @file
+* Header defining the Base addresses, sizes, flags etc for chassis 1
+*
+* Copyright 2017-2019 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#ifndef NXP_CHASSIS_H_
+#define NXP_CHASSIS_H_
+
+#define TP_ITYP_AV_MASK 0x00000001 /* Initiator available */
+#define TP_ITYP_TYPE_MASK(x) (((x) & 0x6) >> 1) /* Initiator Type */
+#define TP_ITYP_TYPE_ARM 0x0
+#define TP_ITYP_TYPE_PPC 0x1
+#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
+#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
+#define TP_ITYP_VERSION(x) (((x) & 0xe0) >> 5) /* Initiator Version */
+#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
+#define TP_INIT_PER_CLUSTER 4
+
+#define TY_ITYP_VERSION_A7 0x1
+#define TY_ITYP_VERSION_A53 0x2
+#define TY_ITYP_VERSION_A57 0x3
+#define TY_ITYP_VERSION_A72 0x4
+
+#define CPU_TYPE_ENTRY(N, V, NC) { .Name = #N, .SocVer = SVR_##V, .NumCores = (NC)}
+
+#define SVR_WO_E 0xFFFFFE
+#define SVR_LS1043A 0x879200
+#define SVR_LS1046A 0x870700
+#define SVR_LS2088A 0x870901
+
+#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)
+#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)
+#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
+#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
+
+#define MHZ 1000000
+
+typedef struct {
+ CHAR8 *Name;
+ UINT32 SocVer;
+ UINT32 NumCores;
+} CPU_TYPE;
+
+typedef struct {
+ UINTN CpuClk; /* CPU clock in Hz! */
+ UINTN BusClk;
+ UINTN MemClk;
+ UINTN PciClk;
+ UINTN SdhcClk;
+} SOC_CLOCK_INFO;
+
+/*
+ * Print Soc information
+ */
+VOID
+PrintSoc (
+ VOID
+ );
+
+/*
+ * Initialize Clock structure
+ */
+VOID
+ClockInit (
+ VOID
+ );
+
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+VOID
+SmmuInit (
+ VOID
+ );
+
+/*
+ * Print CPU information
+ */
+VOID
+PrintCpuInfo (
+ VOID
+ );
+
+/*
+ * Dump RCW (Reset Control Word) on console
+ */
+VOID
+PrintRCW (
+ VOID
+ );
+
+UINT32
+InitiatorType (
+ IN UINT32 Cluster,
+ IN UINTN InitId
+ );
+
+/*
+ * Return the mask for number of cores on this SOC.
+ */
+UINT32
+CpuMask (
+ VOID
+ );
+
+/*
+ * Return the number of cores on this SOC.
+ */
+UINTN
+CpuNumCores (
+ VOID
+ );
+
+/*
+ * Return the type of initiator for core/hardware accelerator for given core index.
+ */
+UINTN
+QoriqCoreToType (
+ IN UINTN Core
+ );
+
+/*
+ * Return the cluster of initiator for core/hardware accelerator for given core index.
+ */
+INT32
+QoriqCoreToCluster (
+ IN UINTN Core
+ );
+
+#endif /* NXP_CHASSIS_H_ */
diff --git a/Silicon/NXP/Library/SocLib/Chassis.c b/Silicon/NXP/Library/SocLib/Chassis.c
new file mode 100644
index 000000000000..b8a8118c5e24
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/Chassis.c
@@ -0,0 +1,495 @@
+/** @file
+ SoC specific Library containg functions to initialize various SoC components
+
+ Copyright 2017-2020 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#ifdef CHASSIS2
+#include <Chassis2/NxpSoc.h>
+#elif CHASSIS3
+#include <Chassis3/NxpSoc.h>
+#endif
+#include <Library/ArmSmcLib.h>
+#include <Library/BaseLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+#include <DramInfo.h>
+#include "NxpChassis.h"
+
+/*
+ * Structure to list available SOCs.
+ * Name, Soc Version, Number of Cores
+ */
+STATIC CPU_TYPE mCpuTypeList[] = {
+ CPU_TYPE_ENTRY (LS1043A, LS1043A, 4),
+ CPU_TYPE_ENTRY (LS1046A, LS1046A, 4),
+ CPU_TYPE_ENTRY (LS2088A, LS2088A, 8),
+};
+
+UINT32
+EFIAPI
+GurRead (
+ IN UINTN Address
+ )
+{
+ if (FixedPcdGetBool (PcdGurBigEndian)) {
+ return SwapMmioRead32 (Address);
+ } else {
+ return MmioRead32 (Address);
+ }
+}
+
+/*
+ * Return the type of initiator (core or hardware accelerator)
+ */
+UINT32
+InitiatorType (
+ IN UINT32 Cluster,
+ IN UINTN InitId
+ )
+{
+ CCSR_GUR *GurBase;
+ UINT32 Idx;
+ UINT32 Type;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ Idx = (Cluster >> (InitId * 8)) & TP_CLUSTER_INIT_MASK;
+ Type = GurRead ((UINTN)&GurBase->TpItyp[Idx]);
+
+ if (Type & TP_ITYP_AV_MASK) {
+ return Type;
+ }
+
+ return 0;
+}
+
+/*
+ * Return the mask for number of cores on this SOC.
+ */
+UINT32
+CpuMask (
+ VOID
+ )
+{
+ CCSR_GUR *GurBase;
+ UINTN ClusterIndex;
+ UINTN Count;
+ UINT32 Cluster;
+ UINT32 Type;
+ UINT32 Mask;
+ UINTN InitiatorIndex;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClusterIndex = 0;
+ Count = 0;
+ Mask = 0;
+
+ do {
+ Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+ for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+ Type = InitiatorType (Cluster, InitiatorIndex);
+ if (Type) {
+ if (TP_ITYP_TYPE_MASK (Type) == TP_ITYP_TYPE_ARM) {
+ Mask |= 1 << Count;
+ }
+ Count++;
+ }
+ }
+ ClusterIndex++;
+ } while (CHECK_CLUSTER (Cluster));
+
+ return Mask;
+}
+
+/*
+ * Return the number of cores on this SOC.
+ */
+UINTN
+CpuNumCores (
+ VOID
+ )
+{
+ UINTN Count;
+ UINTN Num;
+
+ Count = 0;
+ Num = CpuMask ();
+
+ while (Num) {
+ Count += Num & 1;
+ Num >>= 1;
+ }
+
+ return Count;
+}
+
+/*
+ * Return core's cluster
+ */
+INT32
+QoriqCoreToCluster (
+ IN UINTN Core
+ )
+{
+ CCSR_GUR *GurBase;
+ UINTN ClusterIndex;
+ UINTN Count;
+ UINT32 Cluster;
+ UINT32 Type;
+ UINTN InitiatorIndex;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClusterIndex = 0;
+ Count = 0;
+ do {
+ Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+ for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+ Type = InitiatorType (Cluster, InitiatorIndex);
+ if (Type) {
+ if (Count == Core) {
+ return ClusterIndex;
+ }
+ Count++;
+ }
+ }
+ ClusterIndex++;
+ } while (CHECK_CLUSTER (Cluster));
+
+ return -1; // cannot identify the cluster
+}
+
+/*
+ * Return the type of core i.e. A53, A57 etc of inputted
+ * core number.
+ */
+UINTN
+QoriqCoreToType (
+ IN UINTN Core
+ )
+{
+ CCSR_GUR *GurBase;
+ UINTN ClusterIndex;
+ UINTN Count;
+ UINT32 Cluster;
+ UINT32 Type;
+ UINTN InitiatorIndex;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClusterIndex = 0;
+ Count = 0;
+
+ do {
+ Cluster = GurRead ((UINTN)&GurBase->TpCluster[ClusterIndex].Lower);
+ for (InitiatorIndex = 0; InitiatorIndex < TP_INIT_PER_CLUSTER; InitiatorIndex++) {
+ Type = InitiatorType (Cluster, InitiatorIndex);
+ if (Type) {
+ if (Count == Core) {
+ return Type;
+ }
+ Count++;
+ }
+ }
+ ClusterIndex++;
+ } while (CHECK_CLUSTER (Cluster));
+
+ return EFI_NOT_FOUND; /* cannot identify the cluster */
+}
+
+STATIC
+UINTN
+CpuMaskNext (
+ IN UINTN Cpu,
+ IN UINTN Mask
+ )
+{
+ for (Cpu++; !((1 << Cpu) & Mask); Cpu++);
+
+ return Cpu;
+}
+
+/*
+ * Print CPU information
+ */
+VOID
+PrintCpuInfo (
+ VOID
+ )
+{
+ SYS_INFO SysInfo;
+ UINTN CoreIndex;
+ UINTN Core;
+ UINT32 Type;
+ UINT32 NumCpus;
+ UINT32 Mask;
+ CHAR8 *CoreName;
+
+ GetSysInfo (&SysInfo);
+ DEBUG ((DEBUG_INIT, "Clock Configuration:"));
+
+ NumCpus = CpuNumCores ();
+ Mask = CpuMask ();
+
+ for (CoreIndex = 0, Core = CpuMaskNext(-1, Mask);
+ CoreIndex < NumCpus;
+ CoreIndex++, Core = CpuMaskNext(Core, Mask))
+ {
+ if (!(CoreIndex % 3)) {
+ DEBUG ((DEBUG_INIT, "\n "));
+ }
+
+ Type = TP_ITYP_VERSION (QoriqCoreToType (Core));
+ switch (Type) {
+ case TY_ITYP_VERSION_A7:
+ CoreName = "A7";
+ break;
+ case TY_ITYP_VERSION_A53:
+ CoreName = "A53";
+ break;
+ case TY_ITYP_VERSION_A57:
+ CoreName = "A57";
+ break;
+ case TY_ITYP_VERSION_A72:
+ CoreName = "A72";
+ break;
+ default:
+ CoreName = " Unknown Core ";
+ }
+ DEBUG ((DEBUG_INIT, "CPU%d(%a):%-4d MHz ",
+ Core, CoreName, SysInfo.FreqProcessor[Core] / MHZ));
+ }
+
+ DEBUG ((DEBUG_INIT, "\n Bus: %-4d MHz ", SysInfo.FreqSystemBus / MHZ));
+ DEBUG ((DEBUG_INIT, "DDR: %-4d MT/s", SysInfo.FreqDdrBus / MHZ));
+
+ if (SysInfo.FreqFman[0] != 0) {
+ DEBUG ((DEBUG_INIT, "\n FMAN: %-4d MHz ", SysInfo.FreqFman[0] / MHZ));
+ }
+
+ DEBUG ((DEBUG_INIT, "\n"));
+}
+
+/*
+ * Return system bus frequency
+ */
+UINT64
+GetBusFrequency (
+ VOID
+ )
+{
+ SYS_INFO SocSysInfo;
+
+ GetSysInfo (&SocSysInfo);
+
+ return SocSysInfo.FreqSystemBus;
+}
+
+/*
+ * Return SDXC bus frequency
+ */
+UINT64
+GetSdxcFrequency (
+ VOID
+ )
+{
+ SYS_INFO SocSysInfo;
+
+ GetSysInfo (&SocSysInfo);
+
+ return SocSysInfo.FreqSdhc;
+}
+
+/*
+ * Print Soc information
+ */
+VOID
+PrintSoc (
+ VOID
+ )
+{
+ CHAR8 Buf[20];
+ CCSR_GUR *GurBase;
+ UINTN Count;
+ //
+ // Svr : System Version Register
+ //
+ UINTN Svr;
+ UINTN Ver;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+ Svr = GurRead ((UINTN)&GurBase->Svr);
+ Ver = SVR_SOC_VER (Svr);
+
+ for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
+ if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
+ AsciiStrCpyS (Buf, sizeof (Buf), mCpuTypeList[Count].Name);
+
+ if (IS_E_PROCESSOR (Svr)) {
+ AsciiStrCatS (Buf, sizeof (Buf), "E");
+ }
+ break;
+ }
+ }
+
+ DEBUG ((DEBUG_INFO, "SoC: %a (0x%x); Rev %d.%d\n",
+ Buf, Svr, SVR_MAJOR (Svr), SVR_MINOR (Svr)));
+
+ return;
+}
+
+/*
+ * Dump RCW (Reset Control Word) on console
+ */
+VOID
+PrintRCW (
+ VOID
+ )
+{
+ CCSR_GUR *Base;
+ UINTN Count;
+
+ Base = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+ /*
+ * Display the RCW, so that no one gets confused as to what RCW
+ * we're actually using for this boot.
+ */
+
+ DEBUG ((DEBUG_INIT, "Reset Configuration Word (RCW):"));
+ for (Count = 0; Count < ARRAY_SIZE (Base->RcwSr); Count++) {
+ UINT32 Rcw = SwapMmioRead32 ((UINTN)&Base->RcwSr[Count]);
+
+ if ((Count % 4) == 0) {
+ DEBUG ((DEBUG_INIT, "\n %08x:", Count * 4));
+ }
+
+ DEBUG ((DEBUG_INIT, " %08x", Rcw));
+ }
+
+ DEBUG ((DEBUG_INIT, "\n"));
+}
+
+/*
+ * Setup SMMU in bypass mode
+ * and also set its pagesize
+ */
+VOID
+SmmuInit (
+ VOID
+ )
+{
+ UINT32 Value;
+
+ /* set pagesize as 64K and ssmu-500 in bypass mode */
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SACR) | SACR_PAGESIZE_MASK);
+ MmioWrite32 ((UINTN)SMMU_REG_SACR, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_SCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_SCR0, Value);
+
+ Value = (MmioRead32 ((UINTN)SMMU_REG_NSCR0) | SCR0_CLIENTPD_MASK) & ~SCR0_USFCFG_MASK;
+ MmioWrite32 ((UINTN)SMMU_REG_NSCR0, Value);
+}
+
+/*
+ * Return current Soc Name form mCpuTypeList
+ */
+CHAR8 *
+GetSocName (
+ VOID
+ )
+{
+ UINT8 Count;
+ UINTN Svr;
+ UINTN Ver;
+ CCSR_GUR *GurBase;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+
+ Svr = GurRead ((UINTN)&GurBase->Svr);
+ Ver = SVR_SOC_VER (Svr);
+
+ for (Count = 0; Count < ARRAY_SIZE (mCpuTypeList); Count++) {
+ if ((mCpuTypeList[Count].SocVer & SVR_WO_E) == Ver) {
+ return (CHAR8 *)mCpuTypeList[Count].Name;
+ }
+ }
+
+ return NULL;
+}
+
+UINTN
+GetDramSize (
+ IN VOID
+ )
+{
+ ARM_SMC_ARGS ArmSmcArgs;
+
+ ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
+ ArmSmcArgs.Arg1 = -1;
+
+ ArmCallSmc (&ArmSmcArgs);
+
+ if (ArmSmcArgs.Arg0) {
+ return 0;
+ } else {
+ return ArmSmcArgs.Arg1;
+ }
+}
+
+EFI_STATUS
+GetDramBankInfo (
+ IN OUT DRAM_INFO *DramInfo
+ )
+{
+ ARM_SMC_ARGS ArmSmcArgs;
+ UINT32 I;
+ UINTN DramSize;
+
+ DramSize = GetDramSize ();
+ DEBUG ((DEBUG_INFO, "DRAM Total Size 0x%lx \n", DramSize));
+
+ // Ensure DramSize has been set
+ ASSERT (DramSize != 0);
+
+ I = 0;
+
+ do {
+ ArmSmcArgs.Arg0 = SMC_DRAM_BANK_INFO;
+ ArmSmcArgs.Arg1 = I;
+
+ ArmCallSmc (&ArmSmcArgs);
+ if (ArmSmcArgs.Arg0) {
+ if (I > 0) {
+ break;
+ } else {
+ ASSERT (ArmSmcArgs.Arg0 == 0);
+ }
+ }
+
+ DramInfo->DramRegion[I].BaseAddress = ArmSmcArgs.Arg1;
+ DramInfo->DramRegion[I].Size = ArmSmcArgs.Arg2;
+
+ DramSize -= DramInfo->DramRegion[I].Size;
+
+ DEBUG ((DEBUG_INFO, "bank[%d]: start 0x%lx, size 0x%lx\n",
+ I, DramInfo->DramRegion[I].BaseAddress, DramInfo->DramRegion[I].Size));
+
+ I++;
+ } while (DramSize);
+
+ DramInfo->NumOfDrams = I;
+
+ DEBUG ((DEBUG_INFO, "Number Of DRAM in system %d \n", DramInfo->NumOfDrams));
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/NXP/Library/SocLib/Chassis2/Soc.c b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
new file mode 100644
index 000000000000..bfb8b8cb339a
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/Chassis2/Soc.c
@@ -0,0 +1,162 @@
+/** @Soc.c
+ SoC specific Library containg functions to initialize various SoC components
+
+ Copyright 2017-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <NxpChassis.h>
+#include <Chassis2/NxpSoc.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoAccessLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PrintLib.h>
+#include <Library/SerialPortLib.h>
+
+/**
+ Calculate the frequency of various controllers and
+ populate the passed structure with frequuencies.
+
+ @param PtrSysInfo Input structure to populate with
+ frequencies.
+**/
+VOID
+GetSysInfo (
+ OUT SYS_INFO *PtrSysInfo
+ )
+{
+ CCSR_GUR *GurBase;
+ CCSR_CLOCK *ClkBase;
+ UINTN CpuIndex;
+ UINT32 TempRcw;
+ UINT32 CPllSel;
+ UINT32 CplxPll;
+ CONST UINT8 CoreCplxPll[8] = {
+ [0] = 0, /* CC1 PPL / 1 */
+ [1] = 0, /* CC1 PPL / 2 */
+ [4] = 1, /* CC2 PPL / 1 */
+ [5] = 1, /* CC2 PPL / 2 */
+ };
+
+ CONST UINT8 CoreCplxPllDivisor[8] = {
+ [0] = 1, /* CC1 PPL / 1 */
+ [1] = 2, /* CC1 PPL / 2 */
+ [4] = 1, /* CC2 PPL / 1 */
+ [5] = 2, /* CC2 PPL / 2 */
+ };
+
+ UINTN PllCount;
+ UINTN FreqCPll[NUM_CC_PLLS];
+ UINTN PllRatio[NUM_CC_PLLS];
+ UINTN SysClk;
+
+ GurBase = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ ClkBase = (VOID *)PcdGet64 (PcdClkBaseAddr);
+ SysClk = CLK_FREQ;
+
+ SetMem (PtrSysInfo, sizeof (SYS_INFO), 0);
+
+ PtrSysInfo->FreqSystemBus = SysClk;
+ PtrSysInfo->FreqDdrBus = SysClk;
+
+ //
+ // selects the platform clock:SYSCLK ratio and calculate
+ // system frequency
+ //
+ PtrSysInfo->FreqSystemBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+ CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+ CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+ //
+ // selects the DDR PLL:SYSCLK Ratio and calculate DDR frequency
+ //
+ PtrSysInfo->FreqDdrBus *= (GurRead ((UINTN)&GurBase->RcwSr[0]) >>
+ CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
+ CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+
+ for (PllCount = 0; PllCount < NUM_CC_PLLS; PllCount++) {
+ PllRatio[PllCount] = (GurRead ((UINTN)&ClkBase->PllCgSr[PllCount].PllCnGSr) >> 1) & 0xff;
+ if (PllRatio[PllCount] > 4) {
+ FreqCPll[PllCount] = SysClk * PllRatio[PllCount];
+ } else {
+ FreqCPll[PllCount] = PtrSysInfo->FreqSystemBus * PllRatio[PllCount];
+ }
+ }
+
+ //
+ // Calculate Core frequency
+ //
+ for (CpuIndex = 0; CpuIndex < MAX_CPUS; CpuIndex++) {
+ CPllSel = (GurRead ((UINTN)&ClkBase->ClkcSr[CpuIndex].ClkCnCSr) >> 27) & 0xf;
+ CplxPll = CoreCplxPll[CPllSel];
+
+ PtrSysInfo->FreqProcessor[CpuIndex] = FreqCPll[CplxPll] / CoreCplxPllDivisor[CPllSel];
+ }
+
+ //
+ // Calculate FMAN frequency
+ //
+ TempRcw = GurRead ((UINTN)&GurBase->RcwSr[7]);
+ switch ((TempRcw & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
+ case 2:
+ PtrSysInfo->FreqFman[0] = FreqCPll[0] / 2;
+ break;
+ case 3:
+ PtrSysInfo->FreqFman[0] = FreqCPll[0] / 3;
+ break;
+ case 4:
+ PtrSysInfo->FreqFman[0] = FreqCPll[0] / 4;
+ break;
+ case 5:
+ PtrSysInfo->FreqFman[0] = PtrSysInfo->FreqSystemBus;
+ break;
+ case 6:
+ PtrSysInfo->FreqFman[0] = FreqCPll[1] / 2;
+ break;
+ case 7:
+ PtrSysInfo->FreqFman[0] = FreqCPll[1] / 3;
+ break;
+ default:
+ DEBUG ((DEBUG_WARN, "Error: Unknown FMan1 clock select!\n"));
+ break;
+ }
+ PtrSysInfo->FreqSdhc = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
+ PtrSysInfo->FreqQman = PtrSysInfo->FreqSystemBus/PcdGet32 (PcdPlatformFreqDiv);
+}
+
+/**
+ Function to initialize SoC specific constructs
+ CPU Info
+ SoC Personality
+ Board Personality
+ RCW prints
+ **/
+VOID
+SocInit (
+ VOID
+ )
+{
+ SmmuInit ();
+
+ //
+ // Early init serial Port to get board information.
+ //
+ SerialPortInitialize ();
+ DEBUG ((DEBUG_INIT, "\nUEFI firmware (version %s built at %a on %a)\n",
+ (CHAR16*)PcdGetPtr (PcdFirmwareVersionString), __TIME__, __DATE__));
+
+ PrintCpuInfo ();
+
+ //
+ // Print Reset control Word
+ //
+ PrintRCW ();
+ PrintSoc ();
+
+ return;
+}
diff --git a/Silicon/NXP/Library/SocLib/SerDes.c b/Silicon/NXP/Library/SocLib/SerDes.c
new file mode 100644
index 000000000000..b9909d922138
--- /dev/null
+++ b/Silicon/NXP/Library/SocLib/SerDes.c
@@ -0,0 +1,268 @@
+/** SerDes.c
+ Provides the basic interfaces for SerDes Module
+
+ Copyright 2017-2019 NXP
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifdef CHASSIS2
+#include <Chassis2/LsSerDes.h>
+#include <Chassis2/NxpSoc.h>
+#elif CHASSIS3
+#include <Chassis3/LsSerDes.h>
+#include <Chassis3/NxpSoc.h>
+#endif
+#include <Library/DebugLib.h>
+#include <SocSerDes.h>
+#include <Uefi.h>
+
+/**
+ Function to get serdes Lane protocol corresponding to
+ serdes protocol.
+
+ @param SerDes Serdes number.
+ @param Cfg Serdes Protocol.
+ @param Lane Serdes Lane number.
+
+ @return Serdes Lane protocol.
+
+**/
+STATIC
+SERDES_PROTOCOL
+GetSerDesPrtcl (
+ IN INTN SerDes,
+ IN INTN Cfg,
+ IN INTN Lane
+ )
+{
+ SERDES_CONFIG *Config;
+
+ if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
+ return 0;
+ }
+
+ Config = SerDesConfigTbl[SerDes];
+ while (Config->Protocol) {
+ if (Config->Protocol == Cfg) {
+ return Config->SrdsLane[Lane];
+ }
+ Config++;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Function to check if inputted protocol is a valid serdes protocol.
+
+ @param SerDes Serdes number.
+ @param Prtcl Serdes Protocol to be verified.
+
+ @return EFI_INVALID_PARAMETER Input parameter in invalid.
+ @return EFI_NOT_FOUND Serdes Protocol not a valid protocol.
+ @return EFI_SUCCESS Serdes Protocol is a valid protocol.
+
+**/
+STATIC
+EFI_STATUS
+CheckSerDesPrtclValid (
+ IN INTN SerDes,
+ IN UINT32 Prtcl
+ )
+{
+ SERDES_CONFIG *Config;
+ INTN Cnt;
+
+ if (SerDes >= ARRAY_SIZE (SerDesConfigTbl)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Config = SerDesConfigTbl[SerDes];
+ while (Config->Protocol) {
+ if (Config->Protocol == Prtcl) {
+ DEBUG ((DEBUG_INFO, "Protocol: %x Matched with the one in Table\n", Prtcl));
+ break;
+ }
+ Config++;
+ }
+
+ if (!Config->Protocol) {
+ return EFI_NOT_FOUND;
+ }
+
+ for (Cnt = 0; Cnt < SRDS_MAX_LANES; Cnt++) {
+ if (Config->SrdsLane[Cnt] != None) {
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+ Function to fill serdes map information.
+
+ @param Srds Serdes number.
+ @param SerdesProtocolMask Serdes Protocol Mask.
+ @param SerdesProtocolShift Serdes Protocol shift value.
+ @param SerDesPrtclMap Pointer to Serdes Protocol map.
+
+**/
+STATIC
+VOID
+LSSerDesMap (
+ IN UINT32 Srds,
+ IN UINT32 SerdesProtocolMask,
+ IN UINT32 SerdesProtocolShift,
+ OUT UINT64 *SerDesPrtclMap
+ )
+{
+ CCSR_GUR *Gur;
+ UINT32 SrdsProt;
+ INTN Lane;
+ UINT32 Flag;
+
+ Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);
+ *SerDesPrtclMap = 0x0;
+ Flag = 0;
+
+ SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
+ SrdsProt >>= SerdesProtocolShift;
+
+ DEBUG ((DEBUG_INFO, "Using SERDES%d Protocol: %d (0x%x)\n",
+ Srds + 1, SrdsProt, SrdsProt));
+
+ if (EFI_SUCCESS != CheckSerDesPrtclValid (Srds, SrdsProt)) {
+ DEBUG ((DEBUG_ERROR, "SERDES%d[PRTCL] = 0x%x is not valid\n",
+ Srds + 1, SrdsProt));
+ Flag++;
+ }
+
+ for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
+ SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
+ if (LanePrtcl >= SerdesPrtclCount) {
+ DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
+ Flag++;
+ } else {
+ *SerDesPrtclMap |= (1u << LanePrtcl);
+ }
+ }
+
+ if (Flag) {
+ DEBUG ((DEBUG_ERROR, "Could not configure SerDes module!!\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "Successfully configured SerDes module!!\n"));
+ }
+}
+
+/**
+ Get lane protocol on provided serdes lane and execute callback function.
+
+ @param Srds Serdes number.
+ @param SerdesProtocolMask Mask to get Serdes Protocol for Srds
+ @param SerdesProtocolShift Shift value to get Serdes Protocol for Srds.
+ @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
+ @param Arg Pointer to Arguments to be passed to callback function.
+
+**/
+STATIC
+VOID
+SerDesInstanceProbeLanes (
+ IN UINT32 Srds,
+ IN UINT32 SerdesProtocolMask,
+ IN UINT32 SerdesProtocolShift,
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ )
+{
+
+ CCSR_GUR *Gur;
+ UINT32 SrdsProt;
+ INTN Lane;
+
+ Gur = (VOID *)PcdGet64 (PcdGutsBaseAddr);;
+
+ SrdsProt = GurRead ((UINTN)&Gur->RcwSr[RCWSR_INDEX]) & SerdesProtocolMask;
+ SrdsProt >>= SerdesProtocolShift;
+
+ /*
+ * Invoke callback for all lanes in the SerDes instance:
+ */
+ for (Lane = 0; Lane < SRDS_MAX_LANES; Lane++) {
+ SERDES_PROTOCOL LanePrtcl = GetSerDesPrtcl (Srds, SrdsProt, Lane);
+ if ((LanePrtcl >= SerdesPrtclCount) || (LanePrtcl < None)) {
+ DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol %d\n", LanePrtcl));
+ } else if (LanePrtcl != None) {
+ SerDesLaneProbeCallback (LanePrtcl, Arg);
+ }
+ }
+}
+
+/**
+ Probe all serdes lanes for lane protocol and execute provided callback function.
+
+ @param SerDesLaneProbeCallback Pointer Callback function to be called for Lane protocol
+ @param Arg Pointer to Arguments to be passed to callback function.
+
+**/
+VOID
+SerDesProbeLanes (
+ IN SERDES_PROBE_LANES_CALLBACK SerDesLaneProbeCallback,
+ IN VOID *Arg
+ )
+{
+ SerDesInstanceProbeLanes (Srds1,
+ RCWSR_SRDS1_PRTCL_MASK,
+ RCWSR_SRDS1_PRTCL_SHIFT,
+ SerDesLaneProbeCallback,
+ Arg);
+
+ if (PcdGetBool (PcdSerdes2Enabled)) {
+ SerDesInstanceProbeLanes (Srds2,
+ RCWSR_SRDS2_PRTCL_MASK,
+ RCWSR_SRDS2_PRTCL_SHIFT,
+ SerDesLaneProbeCallback,
+ Arg);
+ }
+}
+
+/**
+ Function to return Serdes protocol map for all serdes available on board.
+
+ @param SerDesPrtclMap Pointer to Serdes protocl map.
+
+**/
+VOID
+GetSerdesProtocolMaps (
+ OUT UINT64 *SerDesPrtclMap
+ )
+{
+ LSSerDesMap (Srds1,
+ RCWSR_SRDS1_PRTCL_MASK,
+ RCWSR_SRDS1_PRTCL_SHIFT,
+ SerDesPrtclMap);
+
+ if (PcdGetBool (PcdSerdes2Enabled)) {
+ LSSerDesMap (Srds2,
+ RCWSR_SRDS2_PRTCL_MASK,
+ RCWSR_SRDS2_PRTCL_SHIFT,
+ SerDesPrtclMap);
+ }
+
+}
+
+BOOLEAN
+IsSerDesLaneProtocolConfigured (
+ IN UINT64 SerDesPrtclMap,
+ IN SERDES_PROTOCOL Device
+ )
+{
+ if ((Device >= SerdesPrtclCount) || (Device < None)) {
+ ASSERT ((Device > None) && (Device < SerdesPrtclCount));
+ DEBUG ((DEBUG_ERROR, "Unknown SerDes lane protocol Device %d\n", Device));
+ }
+
+ return (SerDesPrtclMap & (1u << Device)) != 0 ;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
* [edk2-platforms] [PATCH v3 08/11] Silicon/NXP : Add MemoryInitPei Library
2020-01-24 22:25 ` [edk2-platforms] [PATCH v3 00/11] Add support of LS1043 SoC Meenakshi Aggarwal
2020-01-24 22:25 ` [edk2-platforms] [PATCH v3 03/11] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
@ 2020-01-24 22:25 ` Meenakshi Aggarwal
1 sibling, 0 replies; 254+ messages in thread
From: Meenakshi Aggarwal @ 2020-01-24 22:25 UTC (permalink / raw)
To: ard.biesheuvel, leif, michael.d.kinney, devel; +Cc: v.sethi, Meenakshi Aggarwal
Add MemoryInitPei Library for NXP platforms.
It retreieves DRAM information from TF-A.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
---
Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf | 48 +++++++
Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c | 140 ++++++++++++++++++++
2 files changed, 188 insertions(+)
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
new file mode 100644
index 000000000000..a5bd39415def
--- /dev/null
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.inf
@@ -0,0 +1,48 @@
+#/** @file
+#
+# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+# Copyright 2019-2020 NXP
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = ArmMemoryInitPeiLib
+ FILE_GUID = 55ddb6e0-70b5-11e0-b33e-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM DXE_DRIVER
+
+[Sources]
+ MemoryInitPeiLib.c
+
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/NXP/NxpQoriqLs.dec
+
+[LibraryClasses]
+ ArmMmuLib
+ ArmPlatformLib
+ DebugLib
+ HobLib
+ PcdLib
+
+[Guids]
+ gEfiMemoryTypeInformationGuid
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
+[Depex]
+ TRUE
diff --git a/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
new file mode 100644
index 000000000000..00af4bde1a6a
--- /dev/null
+++ b/Silicon/NXP/Library/MemoryInitPei/MemoryInitPeiLib.c
@@ -0,0 +1,140 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*
+* Copyright 2019-2020 NXP
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include <PiPei.h>
+
+#include <Library/ArmMmuLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+#include <DramInfo.h>
+
+VOID
+BuildMemoryTypeInformationHob (
+ VOID
+ );
+
+VOID
+InitMmu (
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
+ )
+{
+
+ VOID *TranslationTableBase;
+ UINTN TranslationTableSize;
+ RETURN_STATUS Status;
+
+ //Note: Because we called PeiServicesInstallPeiMemory() before
+ //to call InitMmu() the MMU Page Table resides in DRAM
+ //(even at the top of DRAM as it is the first permanent memory allocation)
+ Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n"));
+ }
+}
+
+/*++
+
+Routine Description:
+
+
+
+Arguments:
+
+ FileHandle - Handle of the file being invoked.
+ PeiServices - Describes the list of possible PEI Services.
+
+Returns:
+
+ Status - EFI_SUCCESS if the boot mode could be set
+
+--*/
+EFI_STATUS
+EFIAPI
+MemoryPeim (
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
+ IN UINT64 UefiMemorySize
+ )
+{
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
+ EFI_PEI_HOB_POINTERS NextHob;
+ BOOLEAN Found;
+ DRAM_INFO DramInfo;
+
+ // Get Virtual Memory Map from the Platform Library
+ ArmPlatformGetVirtualMemoryMap (&MemoryTable);
+
+ //
+ // Ensure MemoryTable[0].Length which is size of DRAM has been set
+ // by ArmPlatformGetVirtualMemoryMap ()
+ //
+ ASSERT (MemoryTable[0].Length != 0);
+
+ //
+ // Now, the permanent memory has been installed, we can call AllocatePages()
+ //
+ ResourceAttributes = (
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED
+ );
+
+ if (GetDramBankInfo (&DramInfo)) {
+ DEBUG ((DEBUG_ERROR, "Failed to get DRAM information, exiting...\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ while (DramInfo.NumOfDrams--) {
+ //
+ // Check if the resource for the main system memory has been declared
+ //
+ Found = FALSE;
+ NextHob.Raw = GetHobList ();
+ while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {
+ if ((NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
+ (DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress >= NextHob.ResourceDescriptor->PhysicalStart) &&
+ (NextHob.ResourceDescriptor->PhysicalStart + NextHob.ResourceDescriptor->ResourceLength <=
+ DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress + DramInfo.DramRegion[DramInfo.NumOfDrams].Size))
+ {
+ Found = TRUE;
+ break;
+ }
+ NextHob.Raw = GET_NEXT_HOB (NextHob);
+ }
+
+ if (!Found) {
+ // Reserved the memory space occupied by the firmware volume
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ DramInfo.DramRegion[DramInfo.NumOfDrams].BaseAddress,
+ DramInfo.DramRegion[DramInfo.NumOfDrams].Size
+ );
+ }
+ }
+
+ // Build Memory Allocation Hob
+ InitMmu (MemoryTable);
+
+ if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) {
+ // Optional feature that helps prevent EFI memory map fragmentation.
+ BuildMemoryTypeInformationHob ();
+ }
+
+ return EFI_SUCCESS;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 254+ messages in thread
end of thread, other threads:[~2020-01-24 16:42 UTC | newest]
Thread overview: 254+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-02-16 8:49 [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Meenakshi
2018-02-16 8:49 ` [PATCH edk2-platforms 01/39] Silicon/NXP: Add support for Big Endian Mmio APIs Meenakshi
2018-02-21 15:46 ` Leif Lindholm
2018-02-21 16:06 ` Laszlo Ersek
2018-02-21 18:58 ` Leif Lindholm
2018-02-22 4:45 ` Meenakshi Aggarwal
2018-02-22 8:34 ` Laszlo Ersek
2018-02-22 11:52 ` Leif Lindholm
2018-02-22 13:56 ` Laszlo Ersek
2018-02-23 8:40 ` Pankaj Bansal
2018-02-23 9:21 ` Laszlo Ersek
2018-02-23 9:47 ` Meenakshi Aggarwal
2018-02-23 10:17 ` Laszlo Ersek
2018-02-23 10:39 ` Udit Kumar
2018-02-23 10:59 ` Laszlo Ersek
2018-02-23 11:04 ` Pankaj Bansal
2018-02-23 11:22 ` Laszlo Ersek
2018-02-23 11:48 ` Pankaj Bansal
2018-02-23 15:17 ` Laszlo Ersek
2018-02-23 11:21 ` Udit Kumar
2018-02-23 10:25 ` Udit Kumar
2018-02-23 10:47 ` Laszlo Ersek
2018-02-23 11:48 ` Udit Kumar
2018-02-23 15:15 ` Laszlo Ersek
2018-02-28 13:19 ` Leif Lindholm
2018-02-22 4:49 ` Udit Kumar
2018-02-16 8:49 ` [PATCH edk2-platforms 02/39] Silicon/NXP : Add support for Watchdog driver Meenakshi
2018-02-16 8:49 ` [PATCH edk2-platforms 03/39] SocLib : Add support for initialization of peripherals Meenakshi
2018-04-18 15:12 ` Leif Lindholm
2018-04-18 16:38 ` Meenakshi Aggarwal
2018-04-18 18:15 ` Leif Lindholm
2018-04-19 4:59 ` Meenakshi Aggarwal
2018-02-16 8:50 ` [PATCH edk2-platforms 04/39] Silicon/NXP : Add support for DUART library Meenakshi
2018-04-18 15:15 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 05/39] Silicon/NXP: Add support for I2c driver Meenakshi
2018-04-17 16:36 ` Leif Lindholm
2018-04-23 8:21 ` Meenakshi Aggarwal
2018-04-23 8:38 ` Leif Lindholm
2018-04-23 10:34 ` Meenakshi Aggarwal
2018-04-23 13:39 ` Ard Biesheuvel
2018-04-23 15:50 ` Meenakshi Aggarwal
2018-04-23 15:53 ` Ard Biesheuvel
2018-02-16 8:50 ` [PATCH edk2-platforms 06/39] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi
2018-04-18 15:27 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 07/39] Platform/NXP: Add support for ArmPlatformLib Meenakshi
2018-04-18 15:32 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 08/39] Compilation : Add the fdf, dsc and dec files Meenakshi
2018-04-18 15:38 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 09/39] Build : Add build script and environment script Meenakshi
2018-02-21 16:02 ` Leif Lindholm
2018-02-22 4:58 ` Meenakshi Aggarwal
2018-02-16 8:50 ` [PATCH edk2-platforms 10/39] IFC : Add Header file for IFC controller Meenakshi
2018-04-18 18:31 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 11/39] LS1043/BoardLib : Add support for LS1043 BoardLib Meenakshi
2018-04-18 18:34 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 12/39] Silicon/NXP : Add support of IfcLib Meenakshi
2018-04-18 18:39 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 13/39] LS1043/FpgaLib : Add support for FpgaLib Meenakshi
2018-04-18 18:43 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 14/39] LS1043 : Enable support of FpgaLib Meenakshi
2018-04-18 18:43 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 15/39] Silicon/NXP : Add support of NorFlashLib Meenakshi
2018-04-18 19:26 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 16/39] Silicon/NXP : Add NOR driver Meenakshi
2018-04-17 16:23 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 17/39] LS1043 : Enable NOR driver for LS1043aRDB package Meenakshi
2018-04-19 9:54 ` Leif Lindholm
2018-04-19 10:14 ` Meenakshi Aggarwal
2018-02-16 8:50 ` [PATCH edk2-platforms 18/39] Silicon/NXP:Add LS1046ARDB SoCLib Support Meenakshi
2018-04-19 10:00 ` Leif Lindholm
2018-04-19 10:05 ` Meenakshi Aggarwal
2018-04-19 10:20 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 19/39] Silicon/NXP:Add support for PCF2129 Real Time Clock Library Meenakshi
2018-04-19 10:11 ` Leif Lindholm
2018-04-19 12:33 ` Meenakshi Aggarwal
2018-04-19 13:47 ` Leif Lindholm
2018-04-20 3:20 ` Meenakshi Aggarwal
2018-02-16 8:50 ` [PATCH edk2-platforms 20/39] Platform/NXP: LS1046A RDB Board Library Meenakshi
2018-04-19 13:49 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 21/39] Platform/NXP: Add ArmPlatformLib for LS1046A Meenakshi
2018-04-19 13:53 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 22/39] Platform/NXP: LS1046 RDB Board FPGA library Meenakshi
2018-04-19 14:44 ` Leif Lindholm
2018-06-04 4:10 ` Meenakshi Aggarwal
2018-06-04 9:25 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 23/39] Platform/NXP: Compilation for LS1046A RDB Board Meenakshi
2018-04-19 14:54 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 24/39] Silicon/NXP:SocLib support for initialization of peripherals Meenakshi
2018-04-19 15:20 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 25/39] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB Meenakshi
2018-04-19 15:59 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 26/39] Silicon/Maxim: DS3232 RTC Library Support Meenakshi
2018-04-19 16:02 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 27/39] Compilation : Add the fdf, dsc and dec files Meenakshi
2018-04-19 16:28 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 28/39] Platform/NXP: LS2088A RDB Board Library Meenakshi
2018-04-19 16:28 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 29/39] Platform/NXP: LS2088 RDB Board FPGA library Meenakshi
2018-04-19 16:30 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 30/39] LS2088 : Enable support of FpgaLib Meenakshi
2018-04-19 16:31 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 31/39] LS2088ARDB: Enable NOR driver and Runtime Services Meenakshi
2018-04-19 16:32 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 32/39] Silicon/NXP: Implement PciSegmentLib to support multiple RCs Meenakshi
2018-04-19 19:27 ` Leif Lindholm
2018-04-20 6:40 ` Vabhav Sharma
2018-04-20 12:41 ` Leif Lindholm
2018-04-24 12:30 ` Vabhav Sharma
2018-02-16 8:50 ` [PATCH edk2-platforms 33/39] Silicon/NXP: Implement PciHostBridgeLib support Meenakshi
2018-04-20 8:34 ` Ard Biesheuvel
2018-04-24 12:17 ` Vabhav Sharma
2018-04-20 14:54 ` Leif Lindholm
2018-04-24 12:32 ` Vabhav Sharma
2018-02-16 8:50 ` [PATCH edk2-platforms 34/39] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL Meenakshi
2018-04-20 8:40 ` Ard Biesheuvel
2018-04-24 12:26 ` Vabhav Sharma
2018-04-24 12:33 ` Ard Biesheuvel
2018-04-24 13:36 ` Vabhav Sharma
2018-04-24 14:02 ` Ard Biesheuvel
2018-04-20 15:15 ` Leif Lindholm
2018-04-24 12:40 ` Vabhav Sharma
2018-02-16 8:50 ` [PATCH edk2-platforms 35/39] Compilation: Update the fdf, dsc and dec files Meenakshi
2018-04-20 15:22 ` Leif Lindholm
2018-04-24 12:47 ` Vabhav Sharma
2018-02-16 8:50 ` [PATCH edk2-platforms 36/39] DWC3 : Add DWC3 USB controller initialization driver Meenakshi
2018-04-20 15:30 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 37/39] LS2088 : Enable support of USB controller Meenakshi
2018-04-20 15:30 ` Leif Lindholm
2018-02-16 8:50 ` [PATCH edk2-platforms 38/39] Platform/NXP:PCIe enablement for LS1046A RDB Meenakshi
2018-04-20 15:33 ` Leif Lindholm
2018-04-24 12:48 ` Vabhav Sharma
2018-02-16 8:50 ` [PATCH edk2-platforms 39/39] Platform/NXP:PCIe enablement for LS2088A RDB Meenakshi
2018-04-20 15:36 ` Leif Lindholm
2018-04-24 12:50 ` Vabhav Sharma
2018-04-17 16:44 ` [PATCH edk2-platforms 00/39] NXP: Add support of LS1043, LS1046 and LS2088 SoCs Leif Lindholm
2018-04-20 16:15 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 00/41] NXP : " Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 01/41] Silicon/NXP: Add Library to return Mmio APIs pointer Meenakshi Aggarwal
2018-12-21 19:17 ` Leif Lindholm
2018-12-26 5:00 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 02/41] Silicon/NXP : Add support for Watchdog driver Meenakshi Aggarwal
2018-12-17 17:36 ` Leif Lindholm
2019-01-29 5:32 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 03/41] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
2018-12-18 12:31 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 04/41] Silicon/NXP : Add support for DUART library Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 05/41] Silicon/NXP: Add support for I2c driver Meenakshi Aggarwal
2018-12-18 17:25 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 06/41] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 07/41] Platform/NXP: Add support for ArmPlatformLib Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 08/41] Platform/NXP: Add Platform driver for LS1043 RDB board Meenakshi Aggarwal
2018-12-18 17:47 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 09/41] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
2018-12-18 18:35 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 10/41] Readme : Add Readme.md file Meenakshi Aggarwal
2018-12-18 18:41 ` Leif Lindholm
2019-02-01 5:43 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC controller Meenakshi Aggarwal
2018-12-18 18:45 ` Leif Lindholm
2019-02-01 5:55 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 12/41] LS1043/BoardLib : Add support for LS1043 BoardLib Meenakshi Aggarwal
2018-12-18 18:50 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 13/41] Silicon/NXP : Add support of IfcLib Meenakshi Aggarwal
2018-12-19 13:25 ` Leif Lindholm
2019-02-01 6:53 ` Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 14/41] Silicon/NXP : Add support for FpgaLib Meenakshi Aggarwal
2018-12-19 17:37 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 15/41] LS1043 : Enable support of FpgaLib Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 16/41] Silicon/NXP : Add support of NorFlashLib Meenakshi Aggarwal
2018-12-19 18:13 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 17/41] Silicon/NXP : Add NOR driver Meenakshi Aggarwal
2018-12-19 18:32 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 18/41] LS1043 : Enable NOR driver for LS1043aRDB package Meenakshi Aggarwal
2018-12-19 18:33 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 19/41] Silicon/NXP:Add LS1046ARDB SoCLib Support Meenakshi Aggarwal
2018-12-19 18:41 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 20/41] Silicon/NXP:Add support for PCF2129 Real Time Clock Library Meenakshi Aggarwal
2018-12-19 18:52 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 21/41] Platform/NXP: LS1046A RDB Board Library Meenakshi Aggarwal
2018-12-19 18:54 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 22/41] Platform/NXP: Add ArmPlatformLib for LS1046A Meenakshi Aggarwal
2018-12-19 19:08 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 23/41] Platform/NXP: Add Platform driver for LS1046 RDB board Meenakshi Aggarwal
2018-12-19 22:05 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 24/41] Platform/NXP: Compilation for LS1046A RDB Board Meenakshi Aggarwal
2018-12-20 17:39 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 25/41] Silicon/NXP:SocLib support for initialization of peripherals Meenakshi Aggarwal
2018-12-21 9:22 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 26/41] Platform/NXP/LS2088aRdbPkg: ArmPlatformLib Support for LS2088ARDB Meenakshi Aggarwal
2018-12-21 9:30 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 27/41] Platform/NXP: Add Platform driver for LS2088 RDB board Meenakshi Aggarwal
2018-12-21 9:35 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 28/41] Silicon/Maxim: DS3232 RTC Library Support Meenakshi Aggarwal
2018-12-21 9:56 ` Leif Lindholm
2018-12-21 10:01 ` Ard Biesheuvel
2018-11-28 15:01 ` [PATCH edk2-platforms 29/41] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
2018-12-21 10:17 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 30/41] Platform/NXP: LS2088A RDB Board Library Meenakshi Aggarwal
2018-12-21 10:20 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 31/41] Platform/NXP: LS2088 RDB Board FPGA library Meenakshi Aggarwal
2018-12-21 10:22 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 32/41] LS2088 : Enable support of FpgaLib Meenakshi Aggarwal
2018-12-21 10:23 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 33/41] LS2088ARDB: Enable NOR driver and Runtime Services Meenakshi Aggarwal
2018-12-21 10:24 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 34/41] Silicon/NXP: Implement PciSegmentLib to support multiple RCs Meenakshi Aggarwal
2018-12-21 10:44 ` Ard Biesheuvel
2018-12-21 14:01 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 35/41] Silicon/NXP: Implement PciHostBridgeLib support Meenakshi Aggarwal
2018-12-21 10:51 ` Ard Biesheuvel
2018-12-21 18:30 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 36/41] Silicon/NXP: Implement EFI_CPU_IO2_PROTOCOL Meenakshi Aggarwal
2018-12-21 11:09 ` Ard Biesheuvel
2018-12-21 18:49 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 37/41] Compilation: Update the fdf, dsc and dec files Meenakshi Aggarwal
2018-12-21 18:51 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 38/41] DWC3 : Add DWC3 USB controller initialization driver Meenakshi Aggarwal
2018-12-21 19:03 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 39/41] LS2088 : Enable support of USB controller Meenakshi Aggarwal
2018-11-28 15:01 ` [PATCH edk2-platforms 40/41] Platform/NXP:PCIe enablement for LS1046A RDB Meenakshi Aggarwal
2018-12-21 19:05 ` Leif Lindholm
2018-11-28 15:01 ` [PATCH edk2-platforms 41/41] Platform/NXP:PCIe enablement for LS2088A RDB Meenakshi Aggarwal
2018-12-21 19:05 ` Leif Lindholm
2018-12-17 9:50 ` [PATCH edk2-platforms 00/41] NXP : Add support of LS1043, LS1046 and LS2088 SoCs Leif Lindholm
[not found] ` <1570639758-30355-1-git-send-email-meenakshi.aggarwal@nxp.com>
[not found] ` <1570639758-30355-2-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 10:17 ` [PATCH edk2-platforms 01/12] Silicon/NXP: Add Library to provide Mmio APIs with swapped data Leif Lindholm
[not found] ` <1570639758-30355-3-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 10:23 ` [PATCH edk2-platforms 02/12] Silicon/NXP: Add function to return swapped Mmio APIs pointer Leif Lindholm
[not found] ` <1570639758-30355-4-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 10:39 ` [PATCH edk2-platforms 03/12] Silicon/NXP : Add support for Watchdog driver Leif Lindholm
[not found] ` <1570639758-30355-5-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 11:17 ` [PATCH edk2-platforms 04/12] SocLib : Add support for initialization of peripherals Leif Lindholm
[not found] ` <1570639758-30355-7-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 14:51 ` [PATCH edk2-platforms 06/12] Silicon/NXP: Add support for I2c driver Leif Lindholm
[not found] ` <1570639758-30355-9-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 15:07 ` [PATCH edk2-platforms 08/12] Silicon/NXP : Add MemoryInitPei Library Leif Lindholm
[not found] ` <1570639758-30355-11-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 15:12 ` [PATCH edk2-platforms 10/12] Platform/NXP: Add Platform driver for LS1043 RDB board Leif Lindholm
[not found] ` <1570639758-30355-12-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 15:17 ` [PATCH edk2-platforms 11/12] Compilation : Add the fdf, dsc and dec files Leif Lindholm
[not found] ` <1570639758-30355-13-git-send-email-meenakshi.aggarwal@nxp.com>
2019-10-10 15:19 ` [PATCH edk2-platforms 12/12] Readme : Add Readme.md file Leif Lindholm
2019-10-10 15:27 ` [PATCH edk2-platforms 00/12] NXP : Add support of LS1043 SoC Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 00/11] " Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 01/11] Silicon/NXP: Add Library to provide Mmio APIs with swapped data Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 02/11] Silicon/NXP: Add function to return swapped Mmio APIs pointer Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 03/11] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
2019-11-26 16:43 ` Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 04/11] Silicon/NXP : Add support for DUART library Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 05/11] Silicon/NXP: Add support for I2c driver Meenakshi Aggarwal
2019-11-26 17:00 ` Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 06/11] Silicon/Maxim : Add support for DS1307 RTC library Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 07/11] Silicon/NXP : Add MemoryInitPei Library Meenakshi Aggarwal
2019-11-26 16:55 ` [edk2-devel] " Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 08/11] Platform/NXP: Add support for ArmPlatformLib Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 09/11] Platform/NXP: Add Platform driver for LS1043 RDB board Meenakshi Aggarwal
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 10/11] Compilation : Add the fdf, dsc and dec files Meenakshi Aggarwal
2019-11-26 16:56 ` [edk2-devel] " Leif Lindholm
2019-11-21 16:25 ` [edk2-platforms] [PATCH v2 11/11] Readme : Add Readme.md file Meenakshi Aggarwal
2019-11-26 16:58 ` Leif Lindholm
2020-01-24 22:25 ` [edk2-platforms] [PATCH v3 00/11] Add support of LS1043 SoC Meenakshi Aggarwal
2020-01-24 22:25 ` [edk2-platforms] [PATCH v3 03/11] SocLib : Add support for initialization of peripherals Meenakshi Aggarwal
2020-01-24 22:25 ` [edk2-platforms] [PATCH v3 08/11] Silicon/NXP : Add MemoryInitPei Library Meenakshi Aggarwal
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