From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::235; helo=mail-wr0-x235.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x235.google.com (mail-wr0-x235.google.com [IPv6:2a00:1450:400c:c0c::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AB02B21EBD1DE for ; Fri, 20 Apr 2018 08:22:57 -0700 (PDT) Received: by mail-wr0-x235.google.com with SMTP id v15-v6so5903863wrm.10 for ; Fri, 20 Apr 2018 08:22:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=YBm/VDODcbNEus24ut3ipovj6HqlXA+4bCkOVqoClGE=; b=KKBDkaek6adJzwJ7ptZ13lwY+vbj1DKigOVa7m/f/KmPLHYHqOYUqCOmzbgFZawou/ fKY1yJk3N/K8np0tioC6PJO2pyVXbTc6VTLBpn1XuzvoIkuW/f1D5k2GwSLrXTmqBXrG Y2+Cs2I0jV+Q/a26ntV+T3cOYeM/douYHLEMQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=YBm/VDODcbNEus24ut3ipovj6HqlXA+4bCkOVqoClGE=; b=Ed9KTwIl3I02wj/6K2FrAR0CV9xQhGDOYKkofjtq8w6qy8SEDefMwsTosVX0lc0Yvh fgzVqIVMrIijyW35ImSVUP/oOhywUuHZAgbbrSB1p77ZfiXVlyG13PiwsTkJleI2uWx8 rCy6ZmUoRlTWNMISEu6ac6hHVG4EfHK4ZRpqGAeXLwfJtXX9wCvfC6qVV7J0Hj5ds1Gi A5Rht0DrQJsjbonNUB3R4tIlubDkvfMmCJl9I4S70i2FaPfvMCSUnm+7BscnvzkTUrOY xT8cddyNPbwO3Mg02pXAZ/0M/Q0OQ/iBdYhetU0m4AhjoKZDGcflHfO1cKbiNw8N0jCZ llWQ== X-Gm-Message-State: ALQs6tBmf2Yaas3zPDTFJH9KmU70oMz44S9e6ZCP/R9Zwda8hLSecInx kDjX7Ap2RJDIyw3cS9j1u32UzE8PumM= X-Google-Smtp-Source: AIpwx4+rTVGlBmAm6OwribTkzyXiCeGe/tHrtmMJst1Yohz651fRuVl7ma3gboJLXl3ZwhfH6w6zVg== X-Received: by 10.28.106.22 with SMTP id f22mr2141877wmc.132.1524237776260; Fri, 20 Apr 2018 08:22:56 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id b66sm1747703wmh.24.2018.04.20.08.22.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 08:22:55 -0700 (PDT) Date: Fri, 20 Apr 2018 16:22:53 +0100 From: Leif Lindholm To: Meenakshi Cc: ard.biesheuvel@linaro.org, edk2-devel@lists.01.org, udit.kumar@nxp.com, v.sethi@nxp.com, Vabhav Message-ID: <20180420152253.zsy4aacsg6q645iq@bivouac.eciton.net> References: <1518771035-6733-1-git-send-email-meenakshi.aggarwal@nxp.com> <1518771035-6733-36-git-send-email-meenakshi.aggarwal@nxp.com> MIME-Version: 1.0 In-Reply-To: <1518771035-6733-36-git-send-email-meenakshi.aggarwal@nxp.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 35/39] Compilation: Update the fdf, dsc and dec files. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Apr 2018 15:22:59 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Feb 16, 2018 at 02:20:31PM +0530, Meenakshi wrote: > From: Meenakshi Aggarwal > > LS1043A PCIe compilation and update firmware device, > description and declaration files.Defining Embedded Package > PCD which should be at least 20 for 64K PCIe IO size required > for CPU hob during PEI phase to Add IO space post PEI phase. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Vabhav > Signed-off-by: Meenakshi Aggarwal > --- > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 16 ++++++++++++++++ > Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 9 +++++++++ > .../LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf | 2 ++ > .../LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c | 6 ++++++ > Platform/NXP/NxpQoriqLs.dsc | 7 +++++++ > Silicon/NXP/LS1043A/LS1043A.dsc | 4 ++++ > Silicon/NXP/NxpQoriqLs.dec | 10 ++++++++++ > 7 files changed, 54 insertions(+) > > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc > index b2b514e..8cbaf88 100644 > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc > @@ -42,6 +42,8 @@ > BoardLib|Platform/NXP/LS1043aRdbPkg/Library/BoardLib/BoardLib.inf > FpgaLib|Platform/NXP/LS1043aRdbPkg/Library/FpgaLib/FpgaLib.inf > NorFlashLib|Silicon/NXP/Library/NorFlashLib/NorFlashLib.inf > + PciSegmentLib|Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.inf > + PciHostBridgeLib|Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf > > [PcdsFixedAtBuild.common] > > @@ -79,6 +81,13 @@ > gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000 > gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000 > > + # > + # PCI PCDs. > + # > + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE > + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x10000 > + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x7FC > + > ################################################################################ > # > # Components Section - list of all EDK II Modules needed by this Platform > @@ -99,4 +108,11 @@ > Silicon/NXP/Drivers/I2cDxe/I2cDxe.inf > Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf > > + Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf > + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { > + > + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8010004F > + } > + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > + > ## > diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf > index 6b5b63f..7993bf1 100644 > --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf > +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf > @@ -130,6 +130,13 @@ READ_LOCK_STATUS = TRUE > INF Silicon/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf > > # > + # PCI > + # > + INF Silicon/NXP/Drivers/PciCpuIo2Dxe/PciCpuIo2Dxe.inf > + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > + > + # > # Network modules > # > INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf > @@ -154,6 +161,8 @@ READ_LOCK_STATUS = TRUE > INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf > !endif > > + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf > + I'm pretty OK with most of these random updates squashed into one file, but the TftpDynamicCommand is something I generally don't like to see included by default. Other platforms put this inside a conditional statement: !ifdef $(INCLUDE_TFTP_COMMAND) INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf !endif so that it can be included when -D INCLUDE_TFTP_COMMAND=1 is added to the build command line. But beyond that, there is no mention of this addition in the commit message. So please add a notice, or break this specific item out as a separate patch. > # > # FAT filesystem + GPT/MBR partitioning > # > diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf > index 7feac56..f2c8b66 100644 > --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf > +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf > @@ -65,3 +65,5 @@ > gNxpQoriqLsTokenSpaceGuid.PcdDram3Size > gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr > gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize > + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdRomSize > diff --git a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c > index 64c5612..1ef3292 100644 > --- a/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c > +++ b/Platform/NXP/LS1043aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c > @@ -67,6 +67,12 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdCcsrSize); > VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > > + // ROM Space > + VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdRomBaseAddr); > + VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdRomBaseAddr); > + VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdRomSize); > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + > // IFC region 1 > // > // A-009241 : Unaligned write transactions to IFC may result in corruption of data > diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc > index 5987cd6..f5bb2e9 100644 > --- a/Platform/NXP/NxpQoriqLs.dsc > +++ b/Platform/NXP/NxpQoriqLs.dsc > @@ -244,6 +244,8 @@ > > gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 > > + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|20 > + > # > # Optional feature to help prevent EFI memory map fragments > # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob > @@ -409,4 +411,9 @@ > !endif #$(NO_SHELL_PROFILES) > } > > + # > + # TFTP Shell Command > + # > + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf > + Same comment, conditional? / Leif > ## > diff --git a/Silicon/NXP/LS1043A/LS1043A.dsc b/Silicon/NXP/LS1043A/LS1043A.dsc > index a4eb117..f3220fa 100644 > --- a/Silicon/NXP/LS1043A/LS1043A.dsc > +++ b/Silicon/NXP/LS1043A/LS1043A.dsc > @@ -64,6 +64,9 @@ > gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr|0x40000000 > gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize|0x20000000 > gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x1530000 > + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|3 > + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x00000000 > + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x00100000 > > # > # Big Endian IPs > @@ -71,5 +74,6 @@ > gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE > gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE > gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE > + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|TRUE > > ## > diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec > index 3cb476d..a3508b5 100644 > --- a/Silicon/NXP/NxpQoriqLs.dec > +++ b/Silicon/NXP/NxpQoriqLs.dec > @@ -79,6 +79,16 @@ > gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0|UINT64|0x00000129 > gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012A > gNxpQoriqLsTokenSpaceGuid.PcdIfcBaseAddr|0x0|UINT64|0x0000012B > + gNxpQoriqLsTokenSpaceGuid.PcdRomBaseAddr|0x0|UINT64|0x0000012C > + gNxpQoriqLsTokenSpaceGuid.PcdRomSize|0x0|UINT64|0x0000012D > + > + # > + # PCI PCDs > + # > + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase|0x0|UINT32|0x000001D0 > + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg|0x0|UINT32|0x000001D1 > + gNxpQoriqLsTokenSpaceGuid.PcdPciDebug|FALSE|BOOLEAN|0x000001D2 > + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController|0|UINT32|0x000001D3 > > # > # IFC PCDs > -- > 1.9.1 >