From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8384F20352153 for ; Fri, 27 Apr 2018 03:58:40 -0700 (PDT) Received: by mail-wm0-x241.google.com with SMTP id a8so1926403wmg.5 for ; Fri, 27 Apr 2018 03:58:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=esMbRiMSE+id6pvI/hdJB6AvG0c6XT8YD0yNfJLyxCE=; b=QXoCj3NKhGHsKGLasiaTQSt74fNP92eI0Pm/0SLV26cYCgdUD01LF1IZmGCiDQ1wNg aqMCuHGUJakFUl0FerfUyBmwQE9wht8VOtv9sQZptIPRkczINpiaS9xqvaZ+TEP2CFAB Xgq5coleF44CNDIllXsPcCeaC9tMqweMDDDFY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=esMbRiMSE+id6pvI/hdJB6AvG0c6XT8YD0yNfJLyxCE=; b=Myu3PAkAoNkcrgM8Fc2V1uxjhrsmN6WtHic1D4AFH7L9oVdDhbTOI3YzAEBVJp+d4B L4QjqBWRoaOOsnjaVJTzKvu9KgG1wrZnCrUVvfvgZmaexAE8TlKLqmnLPwCnYpGS16ox szNtmXzlDmN1dmnfQxwU8Mm9kJvEv73lusoWL8KOLDOb4ZW9k1m8GO1V+16IF3z4Gmy1 qezFlekI9yLx7d8yjERusdkjLmse1qYYv9f/rHwKOTUqBDHRxt/0YVNQr1TxyOlWUBzI RLrkAP7lAmf07LabyCnMnROdvSIwPxVeYov27vk7QalnkFK35NdAqIJKgCkYQHxOOlMh v/mw== X-Gm-Message-State: ALQs6tC7Dxh14RKKtMHg6Di6jm4wbW4rUNUVAkwJC44Mb1hMDqqWmXhK IVa8ITRApwPaKcqeCnARKMbF9w== X-Google-Smtp-Source: AB8JxZq4TeYTcNxXOryRvN8g2b+xoYbWXJZM49iyVBA+X4tF6XzDVRVAficPS504M6uUR9tb69V0aw== X-Received: by 10.28.24.197 with SMTP id 188mr632962wmy.148.1524826718309; Fri, 27 Apr 2018 03:58:38 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id n49-v6sm1661237wrn.50.2018.04.27.03.58.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 27 Apr 2018 03:58:37 -0700 (PDT) Date: Fri, 27 Apr 2018 11:58:35 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, graeme.gregory@linaro.org, jeremy.linton@arm.com Message-ID: <20180427105835.2kkqlj5hvoxmjhvh@bivouac.eciton.net> References: <20180308131353.17389-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180308131353.17389-1-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacer: add PPTT ACPI table to describe cache topology X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Apr 2018 10:58:41 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Mar 08, 2018 at 01:13:53PM +0000, Ard Biesheuvel wrote: > Add a ACPI Processor Properties Topology Table (PPTT) to the SynQuacer > builds. This information is used by the OS to tune the scheduler. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Not my area of expertise, but looks reasonable. Reviewed-by: Leif Lindholm > --- > This produces the following topology after applying Jeremy's patches: > > $ lstopo-no-graphics > Machine (31GB) > Package L#0 + L3 L#0 (4096KB) > L2 L#0 (256KB) > L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0) > L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1) > L2 L#1 (256KB) > L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2 + PU L#2 (P#2) > L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3 + PU L#3 (P#3) > L2 L#2 (256KB) > L1d L#4 (32KB) + L1i L#4 (32KB) + Core L#4 + PU L#4 (P#4) > L1d L#5 (32KB) + L1i L#5 (32KB) + Core L#5 + PU L#5 (P#5) > L2 L#3 (256KB) > L1d L#6 (32KB) + L1i L#6 (32KB) + Core L#6 + PU L#6 (P#6) > L1d L#7 (32KB) + L1i L#7 (32KB) + Core L#7 + PU L#7 (P#7) > L2 L#4 (256KB) > L1d L#8 (32KB) + L1i L#8 (32KB) + Core L#8 + PU L#8 (P#8) > L1d L#9 (32KB) + L1i L#9 (32KB) + Core L#9 + PU L#9 (P#9) > L2 L#5 (256KB) > L1d L#10 (32KB) + L1i L#10 (32KB) + Core L#10 + PU L#10 (P#10) > L1d L#11 (32KB) + L1i L#11 (32KB) + Core L#11 + PU L#11 (P#11) > L2 L#6 (256KB) > L1d L#12 (32KB) + L1i L#12 (32KB) + Core L#12 + PU L#12 (P#12) > L1d L#13 (32KB) + L1i L#13 (32KB) + Core L#13 + PU L#13 (P#13) > L2 L#7 (256KB) > L1d L#14 (32KB) + L1i L#14 (32KB) + Core L#14 + PU L#14 (P#14) > L1d L#15 (32KB) + L1i L#15 (32KB) + Core L#15 + PU L#15 (P#15) > L2 L#8 (256KB) > L1d L#16 (32KB) + L1i L#16 (32KB) + Core L#16 + PU L#16 (P#16) > L1d L#17 (32KB) + L1i L#17 (32KB) + Core L#17 + PU L#17 (P#17) > L2 L#9 (256KB) > L1d L#18 (32KB) + L1i L#18 (32KB) + Core L#18 + PU L#18 (P#18) > L1d L#19 (32KB) + L1i L#19 (32KB) + Core L#19 + PU L#19 (P#19) > L2 L#10 (256KB) > L1d L#20 (32KB) + L1i L#20 (32KB) + Core L#20 + PU L#20 (P#20) > L1d L#21 (32KB) + L1i L#21 (32KB) + Core L#21 + PU L#21 (P#21) > L2 L#11 (256KB) > L1d L#22 (32KB) + L1i L#22 (32KB) + Core L#22 + PU L#22 (P#22) > L1d L#23 (32KB) + L1i L#23 (32KB) + Core L#23 + PU L#23 (P#23) > HostBridge L#0 > PCIBridge > PCIBridge > PCI 1b21:0612 > Block(Disk) L#0 "sda" > HostBridge L#3 > PCI 10de:128b > GPU L#1 "renderD128" > GPU L#2 "card0" > GPU L#3 "controlD64" > > Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf | 1 + > Silicon/Socionext/SynQuacer/AcpiTables/Pptt.aslc | 221 ++++++++++++++++++++ > 2 files changed, 222 insertions(+) > > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf > index bca8354d1184..afee50df5c63 100644 > --- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf > @@ -31,6 +31,7 @@ [Sources] > Iort.aslc > Madt.aslc > Mcfg.aslc > + Pptt.aslc > Spcr.aslc > > [Packages] > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Pptt.aslc b/Silicon/Socionext/SynQuacer/AcpiTables/Pptt.aslc > new file mode 100644 > index 000000000000..615f324dd37c > --- /dev/null > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Pptt.aslc > @@ -0,0 +1,221 @@ > +/** @file > + > + Copyright (c) 2018, Linaro Ltd. All rights reserved.
> + > + This program and the accompanying materials are licensed and made available > + under the terms and conditions of the BSD License which accompanies this > + distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > + > +#include > + > +#include "AcpiTables.h" > + > +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) > + > +#pragma pack(1) > +typedef struct { > + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; > + UINT32 Offset[2]; > + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; > + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; > +} SYNQUACER_PPTT_CORE; > + > +typedef struct { > + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; > + UINT32 Offset[1]; > + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; > + SYNQUACER_PPTT_CORE Cores[2]; > +} SYNQUACER_PPTT_CLUSTER; > + > +typedef struct { > + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; > + UINT32 Offset[1]; > + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; > + SYNQUACER_PPTT_CLUSTER Clusters[12]; > +} SYNQUACER_PPTT_PACKAGE; > + > +typedef struct { > + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; > + SYNQUACER_PPTT_PACKAGE Packages[1]; > +} SYNQUACER_PPTT_TABLE; > +#pragma pack() > + > +#define PPTT_CORE(pid, cid, id) { \ > + { \ > + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ > + FIELD_OFFSET (SYNQUACER_PPTT_CORE, DCache), \ > + {}, \ > + { \ > + 0, /* PhysicalPackage */ \ > + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \ > + }, \ > + FIELD_OFFSET (SYNQUACER_PPTT_TABLE, \ > + Packages[pid].Clusters[cid]), /* Parent */ \ > + 2 * (cid) + (id), /* AcpiProcessorId */ \ > + 2, /* NumberOfPrivateResources */\ > + }, { \ > + FIELD_OFFSET (SYNQUACER_PPTT_TABLE, \ > + Packages[pid].Clusters[cid].Cores[id].DCache), \ > + FIELD_OFFSET (SYNQUACER_PPTT_TABLE, \ > + Packages[pid].Clusters[cid].Cores[id].ICache), \ > + }, { \ > + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ > + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ > + {}, \ > + { \ > + 1, /* SizePropertyValid */ \ > + 1, /* NumberOfSetsValid */ \ > + 1, /* AssociativityValid */ \ > + 0, /* AllocationTypeValid */ \ > + 1, /* CacheTypeValid */ \ > + 1, /* WritePolicyValid */ \ > + 1, /* LineSizeValid */ \ > + }, \ > + 0, /* NextLevelOfCache */ \ > + SIZE_32KB, /* Size */ \ > + 128, /* NumberOfSets */ \ > + 4, /* Associativity */ \ > + { \ > + 0, /* AllocationType */ \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ > + }, \ > + 64 /* LineSize */ \ > + }, { \ > + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ > + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ > + {}, \ > + { \ > + 1, /* SizePropertyValid */ \ > + 1, /* NumberOfSetsValid */ \ > + 1, /* AssociativityValid */ \ > + 0, /* AllocationTypeValid */ \ > + 1, /* CacheTypeValid */ \ > + 1, /* WritePolicyValid */ \ > + 1, /* LineSizeValid */ \ > + }, \ > + 0, /* NextLevelOfCache */ \ > + SIZE_32KB, /* Size */ \ > + 256, /* NumberOfSets */ \ > + 2, /* Associativity */ \ > + { \ > + 0, /* AllocationType */ \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ > + }, \ > + 64 /* LineSize */ \ > + } \ > +} > + > +#define PPTT_CLUSTER(pid, cid) { \ > + { \ > + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \ > + FIELD_OFFSET (SYNQUACER_PPTT_CLUSTER, L2Cache), \ > + {}, \ > + { \ > + 0, /* PhysicalPackage */ \ > + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \ > + }, \ > + FIELD_OFFSET (SYNQUACER_PPTT_TABLE, Packages[pid]), /* Parent */ \ > + 0, /* AcpiProcessorId */ \ > + 1, /* NumberOfPrivateResources */ \ > + }, { \ > + FIELD_OFFSET (SYNQUACER_PPTT_TABLE, Packages[pid].Clusters[cid].L2Cache), \ > + }, { \ > + EFI_ACPI_6_2_PPTT_TYPE_CACHE, \ > + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \ > + {}, \ > + { \ > + 1, /* SizePropertyValid */ \ > + 1, /* NumberOfSetsValid */ \ > + 1, /* AssociativityValid */ \ > + 0, /* AllocationTypeValid */ \ > + 1, /* CacheTypeValid */ \ > + 1, /* WritePolicyValid */ \ > + 1, /* LineSizeValid */ \ > + }, \ > + 0, /* NextLevelOfCache */ \ > + SIZE_256KB, /* Size */ \ > + 256, /* NumberOfSets */ \ > + 16, /* Associativity */ \ > + { \ > + 0, /* AllocationType */ \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \ > + }, \ > + 64 /* LineSize */ \ > + }, { \ > + PPTT_CORE(pid, cid, 0), \ > + PPTT_CORE(pid, cid, 1), \ > + } \ > +} > + > +STATIC SYNQUACER_PPTT_TABLE mSynQuacerPpttTable = { > + { > + __ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, > + SYNQUACER_PPTT_TABLE, > + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION), > + }, > + { > + { > + { > + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, > + FIELD_OFFSET (SYNQUACER_PPTT_PACKAGE, L3Cache), > + {}, > + { > + 1, /* PhysicalPackage */ > + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ > + }, > + 0, /* Parent */ > + 0, /* AcpiProcessorId */ > + 1, /* NumberOfPrivateResources */ > + }, { > + FIELD_OFFSET (SYNQUACER_PPTT_TABLE, Packages[0].L3Cache), > + }, { > + EFI_ACPI_6_2_PPTT_TYPE_CACHE, > + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), > + {}, > + { > + 1, /* SizePropertyValid */ > + 1, /* NumberOfSetsValid */ > + 1, /* AssociativityValid */ > + 0, /* AllocationTypeValid */ > + 1, /* CacheTypeValid */ > + 1, /* WritePolicyValid */ > + 1, /* LineSizeValid */ > + }, > + 0, /* NextLevelOfCache */ > + SIZE_4MB, /* Size */ > + 4096, /* NumberOfSets */ > + 16, /* Associativity */ > + { > + 0, /* AllocationType */ > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, > + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, > + }, > + 64 /* LineSize */ > + }, { > + PPTT_CLUSTER (0, 0), > + PPTT_CLUSTER (0, 1), > + PPTT_CLUSTER (0, 2), > + PPTT_CLUSTER (0, 3), > + PPTT_CLUSTER (0, 4), > + PPTT_CLUSTER (0, 5), > + PPTT_CLUSTER (0, 6), > + PPTT_CLUSTER (0, 7), > + PPTT_CLUSTER (0, 8), > + PPTT_CLUSTER (0, 9), > + PPTT_CLUSTER (0, 10), > + PPTT_CLUSTER (0, 11), > + } > + } > + } > +}; > + > +VOID* CONST ReferenceAcpiTable = &mSynQuacerPpttTable; > -- > 2.15.1 >