From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 63BFB2063E31F for ; Fri, 4 May 2018 03:26:40 -0700 (PDT) Received: by mail-wm0-x241.google.com with SMTP id l1-v6so3841862wmb.2 for ; Fri, 04 May 2018 03:26:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=jzfLY/yf0/u2vWYLvJH3jiUK3wpNfluhuO6/u9UycR0=; b=CYE25a6JYaaK+2dPPcfyHnkLyc2MkiNLIcq5MXSJMk/1g7YOqCwv5qZg6rHdjYaU9g A7OWQFrEZcXJaa2k+ypu4SqCxpP1OAuUTC6pe+xwyRVFD9erct57gw//4vru7oOTx9uH 4NuAQHEIS5jMVLtEhvAmaWvdCl6Dx0X1eBWyg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=jzfLY/yf0/u2vWYLvJH3jiUK3wpNfluhuO6/u9UycR0=; b=Cel1ccZwXccDY+2t0J3HCc9SPZNQbP4evdjYdDHWVsMwCg8Xgyvx9a1OFmp4IigYlZ /fuHV3G4/HTtLYoSBUlUPOiWrcOzDWG4dPYTy1qLxO3lMtUoITJBQPet2xx2WFD8LPGp zTIYpqDrKswzi2/+Y1dkKSnh1ULIDhJKfeurPkD3IQnQ0BUI9qUowa/jZX6pkvhLg3ed PGi4WHuTKKxpyd9AwPz/yW6xFPqtNiKg9Fy7YazJN0CVwxeZHA58k39VTPwbHdvOr7Bx Wg/VgJvnLlRnC/X6LA828izKRpfiNJ1yGInem4eS/NC5pMqyhabT8ZT25dYoW2eN/aci l7sw== X-Gm-Message-State: ALQs6tBjxoPYY9ZpdeZVuTha+6tOEFtC/03czX16pAHu8triGK5GcKqV /zaS3fCawFJsmaCJ5uHl9uY2cQ== X-Google-Smtp-Source: AB8JxZqgVXChZevkPDNfLHb6zFic1PNQjVIh0ggzsp0otseGqgNbyBcq6Gu7kBIlwdTFsD7y8F0dmA== X-Received: by 10.28.229.74 with SMTP id c71mr15985150wmh.55.1525429598663; Fri, 04 May 2018 03:26:38 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id v111-v6sm16462520wrb.30.2018.05.04.03.26.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 04 May 2018 03:26:37 -0700 (PDT) Date: Fri, 4 May 2018 11:26:35 +0100 From: Leif Lindholm To: Haojian Zhuang Cc: "edk2-devel@lists.01.org" , Ard Biesheuvel Message-ID: <20180504102634.tvn2hn42qnxlf7bf@bivouac.eciton.net> References: <1520515790-29527-1-git-send-email-haojian.zhuang@linaro.org> <20180502151435.46zbhyux5vh45hh2@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH v2 edk-platforms 1/4] Platform/Hisilicon/HiKey960: add gpio platform driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 May 2018 10:26:40 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, May 04, 2018 at 11:29:33AM +0800, Haojian Zhuang wrote: > On 2 May 2018 at 23:14, Leif Lindholm wrote: > >> + { 0xe8a0b000, 0, 8 }, // GPIO0 > > > > It would not improve readability to request all of these live-coded > > values to be replaced by #defines, but barring that, could you add a > > comment header before the definition?: > > > > // { base address, gpio index, gpio count } > > > > OK > >> + { 0xe8a0c000, 8, 8 }, // GPIO1 > >> + { 0xe8a0d000, 16, 8 }, // GPIO2 > >> + { 0xe8a0e000, 24, 8 }, // GPIO3 > >> + { 0xe8a0f000, 32, 8 }, // GPIO4 > >> + { 0xe8a10000, 40, 8 }, // GPIO5 > >> + { 0xe8a11000, 48, 8 }, // GPIO6 > >> + { 0xe8a12000, 56, 8 }, // GPIO7 > >> + { 0xe8a13000, 64, 8 }, // GPIO8 > >> + { 0xe8a14000, 72, 8 }, // GPIO9 > >> + { 0xe8a15000, 80, 8 }, // GPIO10 > >> + { 0xe8a16000, 88, 8 }, // GPIO11 > >> + { 0xe8a17000, 96, 8 }, // GPIO12 > >> + { 0xe8a18000, 104, 8 }, // GPIO13 > >> + { 0xe8a19000, 112, 8 }, // GPIO14 > >> + { 0xe8a1a000, 120, 8 }, // GPIO15 > >> + { 0xe8a1b000, 128, 8 }, // GPIO16 > >> + { 0xe8a1c000, 136, 8 }, // GPIO17 > >> + { 0xff3b4000, 144, 8 }, // GPIO18 > >> + { 0xff3b5000, 152, 8 }, // GPIO19 > > > > I notice that these: > >> + { 0xe8a1f000, 160, 8 }, // GPIO20 > >> + { 0xe8a20000, 168, 8 }, // GPIO21 > > are out of order, from their base address. > > Are the names GPIO20/GPIO21 defined in the TRM? > > > > Yes, it's mentioned in the TRM. Yeah, I figured as much, but was hoping for something else :) > (https://github.com/96boards/documentation/blob/master/consumer/hikey960/hardware-docs/HiKey960_SoC_Reference_Manual.pdf) Thanks for the link - that will be useful! / Leif