From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 500FE20348632 for ; Tue, 15 May 2018 10:37:51 -0700 (PDT) Received: by mail-wr0-x243.google.com with SMTP id v60-v6so1003120wrc.7 for ; Tue, 15 May 2018 10:37:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z6UIXSs8PNpFoSJO2TkFmet98acvG2q4F3jghyfpuqA=; b=EFHtlTNGww9xbfcUUEfB4jGvmNfdwo3FSgCRwIP+Oo2h3tpDVOrxyGSJtfrgZd0Tu3 pT0vHp8i0LIaClKN6Rekh2+PkOYBYEQWDxmAwf2qsmrquZsiQ75g+tzzoMd7fDK1S8ni iqfl3X7ZIMsZrZZhTEPszPjMSstQbhDzmfQQ8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z6UIXSs8PNpFoSJO2TkFmet98acvG2q4F3jghyfpuqA=; b=DSc/YGPUW7sCYK3EfepgPkgut6Iay9B7BFzHmQ+icCXqnc8yVA/ENY/ie0bXIg3vgr 9sJIAeFmt9xU5VExweZE2GZ4+3/baoWdqnSwQtD/Dqr+x38jYWQ6QZxsAjQFHVN4i0+f JSnEwrbzpMHfGivuvmD2KHOId7MtHU7fMrMSGrRvzKJnQjPKheIqqCbq1oVDl7RzFFmQ shSYjlpLBbpLk+G80qhhsGNH7tw7We1Gteh/OuwFN1uFtaRccbpWQJzFyBhXoqCukHb9 P9Ot41A21pGkjz3W3k2aMH5f/QMZaMmBd/2oAW33h6z4pf8GKXt+cGCP379Ol3L6pExj /0Vw== X-Gm-Message-State: ALKqPwfZNY1GppgtcgJNs9P1jlapzke8ivt6UzJ+pCPdDq6jV3JYHBX4 ns3Dw9URamocG8AbcDcE2CutLWJwQL4= X-Google-Smtp-Source: AB8JxZqBavWDfpedUKoFEHCNzhi2oH8bDIpBDgl6RT27GifH39SE0OnaPLbyaiAJKv6kKngCJyP8JA== X-Received: by 2002:adf:abab:: with SMTP id s40-v6mr12033178wrc.259.1526405869581; Tue, 15 May 2018 10:37:49 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id v75-v6sm814183wrc.65.2018.05.15.10.37.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:48 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, alan@softiron.co.uk, neko@bakuhatsu.net, Ard Biesheuvel Date: Tue, 15 May 2018 19:37:34 +0200 Message-Id: <20180515173736.29639-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515173736.29639-1-ard.biesheuvel@linaro.org> References: <20180515173736.29639-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms 3/5] Silicon/AMD/Styx: remove support for the ACPI parking protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 May 2018 17:37:51 -0000 The ACPI parking protocol is a kludge to allow SOC implementations that lack EL3 support to bring up secondaries in a standardized manner. Since our UEFI implementation unconditionally relies on ARM Trusted Firmware and PSCI now, there is no point in supporting the parking protocol any longer so let's remove it. (Note also that the implementation of AmdStyxGetMpParkingBase is flawed, so it is unsure whether it has ever worked in reality) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/AMD/Styx/AcpiTables/AcpiTables.inf | 1 - Silicon/AMD/Styx/AcpiTables/Madt.c | 24 ++---------- Silicon/AMD/Styx/AmdStyx.dec | 4 -- Silicon/AMD/Styx/Common/Protocol/AmdMpBoot.h | 39 -------------------- Silicon/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h | 7 ---- Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c | 21 ----------- 6 files changed, 3 insertions(+), 93 deletions(-) diff --git a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf index bff5be4673a4..4ae64ac22665 100644 --- a/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf +++ b/Silicon/AMD/Styx/AcpiTables/AcpiTables.inf @@ -82,7 +82,6 @@ [FixedPcd] gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster - gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion gAmdStyxTokenSpaceGuid.PcdSata1PortCount [Depex] diff --git a/Silicon/AMD/Styx/AcpiTables/Madt.c b/Silicon/AMD/Styx/AcpiTables/Madt.c index 96182e790f98..43d415c8bc32 100644 --- a/Silicon/AMD/Styx/AcpiTables/Madt.c +++ b/Silicon/AMD/Styx/AcpiTables/Madt.c @@ -57,12 +57,7 @@ AMD_MP_CORE_INFO_PROTOCOL *mAmdMpCoreInfoProtocol = NULL; #define MSI_TYPER_FLAG ( 0 ) // Use TYPER register and ignore Count/Base fields #endif -#define PARKING_PROTOCOL_VERSION (FixedPcdGet32 (PcdParkingProtocolVersion)) -#define PARKED_OFFSET ( 4096 ) - #define CORES_PER_CLUSTER (FixedPcdGet32 (PcdSocCoresPerCluster)) -#define PARKED_ADDRESS(Base, ClusterId, CoreId) \ - ((Base) + (CORES_PER_CLUSTER * ClusterId + CoreId) * PARKED_OFFSET) /* Macro to populate EFI_ACPI_5_1_GIC_STRUCTURE */ @@ -73,7 +68,7 @@ AMD_MP_CORE_INFO_PROTOCOL *mAmdMpCoreInfoProtocol = NULL; CpuNum, /* UINT32 CPUInterfaceNumber */ \ (ClusterId << 8) | CoreId, /* UINT32 AcpiProcessorUid */ \ EFI_ACPI_5_1_GIC_ENABLED, /* UINT32 Flags */ \ - PARKING_PROTOCOL_VERSION, /* UINT32 ParkingProtocolVersion */ \ + 0, /* UINT32 ParkingProtocolVersion */ \ PerfInt, /* UINT32 PerformanceInterruptGsiv */ \ 0, /* UINT64 ParkedAddress */ \ GIC_BASE, /* UINT64 PhysicalBaseAddress */ \ @@ -194,8 +189,7 @@ BuildGicC ( EFI_ACPI_5_1_GIC_STRUCTURE *GicC, UINT32 CpuNum, UINT32 ClusterId, - UINT32 CoreId, - EFI_PHYSICAL_ADDRESS MpParkingBase + UINT32 CoreId ) { UINT32 MpId, PmuSpi; @@ -212,8 +206,6 @@ BuildGicC ( GicC->CPUInterfaceNumber = CpuNum; GicC->AcpiProcessorUid = MpId; GicC->Flags = EFI_ACPI_5_1_GIC_ENABLED; - GicC->ParkingProtocolVersion = PARKING_PROTOCOL_VERSION; - GicC->ParkedAddress = PARKED_ADDRESS(MpParkingBase, ClusterId, CoreId); GicC->PhysicalBaseAddress = GIC_BASE; GicC->GICV = GICV_BASE; GicC->GICH = GICH_BASE; @@ -281,8 +273,6 @@ MadtHeader ( ARM_CORE_INFO *ArmCoreInfoTable; UINTN CoreCount, CpuNum; EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS MpParkingBase; - UINTN MpParkingSize; Status = gBS->LocateProtocol ( &gAmdMpCoreInfoProtocolGuid, @@ -299,13 +289,6 @@ MadtHeader ( ASSERT (CoreCount <= NUM_CORES); ASSERT (CoreCount <= PcdGet32(PcdSocCoreCount)); - MpParkingSize = 0; - MpParkingBase = mAmdMpCoreInfoProtocol->GetMpParkingBase(&MpParkingSize); - if (MpParkingBase && MpParkingSize < (CoreCount * SIZE_4KB)) { - DEBUG ((EFI_D_ERROR, "MADT: Parking Protocol not supported.\n")); - MpParkingBase = 0; - } - GicC = (EFI_ACPI_5_1_GIC_STRUCTURE *)&AcpiMadt.GicC[0]; AcpiMadt.Header.Header.Length = sizeof (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); @@ -315,8 +298,7 @@ MadtHeader ( Status = BuildGicC (GicC, CpuNum, ArmCoreInfoTable[CpuNum].ClusterId, - ArmCoreInfoTable[CpuNum].CoreId, - MpParkingBase + ArmCoreInfoTable[CpuNum].CoreId ); ASSERT_EFI_ERROR (Status); diff --git a/Silicon/AMD/Styx/AmdStyx.dec b/Silicon/AMD/Styx/AmdStyx.dec index cffe1cafde8b..1eb1ce801e0b 100644 --- a/Silicon/AMD/Styx/AmdStyx.dec +++ b/Silicon/AMD/Styx/AmdStyx.dec @@ -28,7 +28,6 @@ [Ppis] gAmdStyxPlatInitPpiGuid = { 0xcbff429c, 0xd3e3, 0x4c50, { 0xac, 0x1a, 0x1c, 0xd2, 0xfe, 0x15, 0x1a, 0xd7 } } [Protocols] - gAmdMpBootProtocolGuid = { 0xe21eac84, 0x9fbf, 0x4808, { 0x83, 0x93, 0xe1, 0x93, 0x97, 0x23, 0x48, 0xab } } gAmdMpCoreInfoProtocolGuid = { 0x0dba25f8, 0x2da1, 0x4ec5, { 0x89, 0x5d, 0x32, 0x1e, 0xd6, 0x1e, 0x3f, 0x43 } } [Guids] @@ -101,9 +100,6 @@ [PcdsFixedAtBuild] # UEFI entry point gAmdStyxTokenSpaceGuid.PcdUefiEntryAddress|0x8000E80000|UINT64|0x000a0000 - # Parking Protocol - gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion|1|UINT32|0x000b0000 - # The original offset in memory of the NV store firmware volume, before # relocating it to a dynamically allocated buffer. We need this to correlate # flash accesses to the in-memory copy with LBAs in the actual SPI flash diff --git a/Silicon/AMD/Styx/Common/Protocol/AmdMpBoot.h b/Silicon/AMD/Styx/Common/Protocol/AmdMpBoot.h deleted file mode 100644 index 2aa4c55ccbaf..000000000000 --- a/Silicon/AMD/Styx/Common/Protocol/AmdMpBoot.h +++ /dev/null @@ -1,39 +0,0 @@ -/** @file - - Copyright (c) 2016, AMD Inc. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _AMD_MP_BOOT_H_ -#define _AMD_MP_BOOT_H_ - -extern EFI_GUID gAmdMpBootProtocolGuid; - -typedef -VOID -(EFIAPI *PARK_SECONDARY_CORE) ( - IN ARM_CORE_INFO *ArmCoreInfo, - IN EFI_PHYSICAL_ADDRESS SecondaryEntry - ); - -typedef struct _AMD_MP_BOOT_INFO { - EFI_PHYSICAL_ADDRESS MpParkingBase; - UINTN MpParkingSize; - ARM_CORE_INFO *ArmCoreInfoTable; - UINTN ArmCoreCount; -} AMD_MP_BOOT_INFO; - -typedef struct _AMD_MP_BOOT_PROTOCOL { - PARK_SECONDARY_CORE ParkSecondaryCore; - AMD_MP_BOOT_INFO *MpBootInfo; -} AMD_MP_BOOT_PROTOCOL; - -#endif // _AMD_MP_BOOT_H_ diff --git a/Silicon/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h b/Silicon/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h index 95f46e8af962..e6aa8fb1bec9 100644 --- a/Silicon/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h +++ b/Silicon/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h @@ -30,16 +30,9 @@ EFI_STATUS OUT UINT32 *PmuSpi ); -typedef -EFI_PHYSICAL_ADDRESS -(EFIAPI *GET_MP_PARKING_BASE) ( - OUT UINTN *MpParkingSize - ); - typedef struct _AMD_MP_CORE_INFO_PROTOCOL { GET_ARM_CORE_INFO_TABLE GetArmCoreInfoTable; GET_PMU_SPI_FROM_MPID GetPmuSpiFromMpId; - GET_MP_PARKING_BASE GetMpParkingBase; } AMD_MP_CORE_INFO_PROTOCOL; #endif // _AMD_MP_CORE_INFO_H_ diff --git a/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c index e713d5581925..68f97fb89148 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c +++ b/Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c @@ -29,11 +29,9 @@ #include #include -#include STATIC AMD_MP_CORE_INFO_PROTOCOL mAmdMpCoreInfoProtocol = { 0 }; -STATIC AMD_MP_BOOT_INFO mAmdMpBootInfo = { 0 }; STATIC @@ -49,12 +47,6 @@ AmdStyxGetPmuSpiFromMpId ( OUT UINT32 *PmuSpi ); -STATIC -EFI_PHYSICAL_ADDRESS -AmdStyxGetMpParkingBase ( - OUT UINTN *MpParkingSize - ); - #pragma pack(push, 1) typedef struct _PMU_INFO { @@ -101,7 +93,6 @@ PlatInitDxeEntryPoint ( // Install CoreInfo Protocol mAmdMpCoreInfoProtocol.GetArmCoreInfoTable = AmdStyxGetArmCoreInfoTable; mAmdMpCoreInfoProtocol.GetPmuSpiFromMpId = AmdStyxGetPmuSpiFromMpId; - mAmdMpCoreInfoProtocol.GetMpParkingBase = AmdStyxGetMpParkingBase; Status = gBS->InstallProtocolInterface ( &Handle, &gAmdMpCoreInfoProtocolGuid, @@ -153,15 +144,3 @@ AmdStyxGetPmuSpiFromMpId ( return EFI_INVALID_PARAMETER; } - -STATIC -EFI_PHYSICAL_ADDRESS -AmdStyxGetMpParkingBase ( - OUT UINTN *MpParkingSize - ) -{ - ASSERT (MpParkingSize != NULL); - - *MpParkingSize = mAmdMpBootInfo.MpParkingBase; - return mAmdMpBootInfo.MpParkingBase; -} -- 2.17.0