From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B7909209603D9 for ; Tue, 15 May 2018 10:37:53 -0700 (PDT) Received: by mail-wm0-x243.google.com with SMTP id f8-v6so2641502wmc.4 for ; Tue, 15 May 2018 10:37:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Jn0im5+tXL8rl51MlKrQb1X7aGSjULzplqKXrDuOk88=; b=RZDIFtGGqhQiQJpxIQ2WQtPj+pwJKeLP8WHEfwjeF8ijqcnxBArv3+7dXxJJdiitMY p0tT/WB1UAol4sV/xlPBWu7YZgGpHFm8yGT58/I34cNCH2CaEgRGI3vfiVIHwUer9T5E vmcaPoivgZ4tX63fG6S/EXbxRVa4KAchnxcBU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Jn0im5+tXL8rl51MlKrQb1X7aGSjULzplqKXrDuOk88=; b=H7wVqcklUBzKAXF2k2oGycK6SN9OXFz0bSWht9EFNkL8NQ1LjefORTgag6Y4vqkx6M ZrNTZZ4luh+eFHRZG2HstnHfD7i2TdTEKzBL72VQ4nOJcNHxygciKAqpYkjkoQJRQ0Ma 2fHWf3OXxOZCqxqCV//FJIAYJYg4q64hDlAQUFl94FjniWCGUjBixj++0pPbKdP1CuAL nD2n2TMQQj2Nwk6sxmBp6INRvzAifdvsdXKDq/UhQgEa+qjEAbzOE6Cgxe6jLvcYKvov c4hdetBRAGStpEwbAnVUmYFbzAto847yiDgRjsn3LFFlhbqjQPyoEB61Uq7ZYJPK2f8u gSbQ== X-Gm-Message-State: ALKqPwe53KcQ8y8TNwQAspVdq/xKLftSaW9tOFxQK7n/1zv/EhF8j4JQ 8g/a4nq6lOkIhmdIuZX8I+kJfMwgfZ4= X-Google-Smtp-Source: AB8JxZqbTzX5Sd+xDCqFLzNdRZw+IJYOgzImVBTyQ4mXjwvQidZIhQu9KrQqRe24JqduCqIJVbMDFQ== X-Received: by 2002:a1c:e854:: with SMTP id f81-v6mr2037602wmh.14.1526405871517; Tue, 15 May 2018 10:37:51 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id v75-v6sm814183wrc.65.2018.05.15.10.37.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 May 2018 10:37:50 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, alan@softiron.co.uk, neko@bakuhatsu.net, Ard Biesheuvel Date: Tue, 15 May 2018 19:37:35 +0200 Message-Id: <20180515173736.29639-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180515173736.29639-1-ard.biesheuvel@linaro.org> References: <20180515173736.29639-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms 4/5] Silicon/AMD/Styx: make ISCP dependency unconditional X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 May 2018 17:37:54 -0000 The Styx code can be built without relying on the ISCP, but doing so is rather pointless, and is essentially dead code because nobody ever does that. Let's just remove this feature. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 7 -- Platform/LeMaker/CelloBoard/CelloBoard.dsc | 2 - Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 7 -- Silicon/AMD/Styx/AmdStyx.dec | 3 - Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c | 120 +++++++++----------- Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf | 1 - Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c | 40 ------- Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf | 1 - Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf | 2 - Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c | 16 +-- Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf | 3 - 11 files changed, 55 insertions(+), 147 deletions(-) diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc index 26b91ca88a2c..7bc1ab937813 100644 --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc @@ -19,7 +19,6 @@ [Defines] DEFINE DO_XGBE = 1 DEFINE NUM_CORES = 8 -DEFINE DO_ISCP = 1 DEFINE DO_KCS = 1 DEFINE DO_FLASHER = FALSE DEFINE DO_CAPSULE = FALSE @@ -456,12 +455,6 @@ [PcdsFixedAtBuild.common] # gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1 -!if $(DO_ISCP) - gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE -!else - gAmdStyxTokenSpaceGuid.PcdIscpSupport|FALSE -!endif - # SMBIOS 3.0 only gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc index 80b096ba5587..1acfe7e93fad 100644 --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc @@ -431,8 +431,6 @@ [PcdsFixedAtBuild.common] # gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1 - gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE - # SMBIOS 3.0 only gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc index 8d50d78c30cd..8d0a5bdc5270 100644 --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc @@ -18,7 +18,6 @@ [Defines] DEFINE NUM_CORES = 4 -DEFINE DO_ISCP = 1 DEFINE DO_KCS = 1 DEFINE DO_FLASHER = FALSE @@ -427,12 +426,6 @@ [PcdsFixedAtBuild.common] ## ACPI (no tables < 4GB) gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 -!if $(DO_ISCP) - gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE -!else - gAmdStyxTokenSpaceGuid.PcdIscpSupport|FALSE -!endif - # SMBIOS 3.0 only gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2 diff --git a/Silicon/AMD/Styx/AmdStyx.dec b/Silicon/AMD/Styx/AmdStyx.dec index 1eb1ce801e0b..eeded93a32e2 100644 --- a/Silicon/AMD/Styx/AmdStyx.dec +++ b/Silicon/AMD/Styx/AmdStyx.dec @@ -91,9 +91,6 @@ [PcdsFixedAtBuild] gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase|0x8000000000|UINT64|0x00060001 gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize|0xE80000|UINT64|0x0006002 - # ISCP - gAmdStyxTokenSpaceGuid.PcdIscpSupport|TRUE|BOOLEAN|0x00070000 - # Cores Per cluster gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster|2|UINT32|0x00090000 diff --git a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c index 61e373406bcc..4ea1dd4b3577 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c +++ b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c @@ -140,64 +140,56 @@ PlatInitPeiEntryPoint ( mAmdCoreCount = PcdGet32 (PcdSocCoreCount); } - if (FixedPcdGetBool (PcdIscpSupport)) { - Status = PeiServicesLocatePpi (&gPeiIscpPpiGuid, 0, NULL, (VOID**)&PeiIscpPpi); - ASSERT_EFI_ERROR (Status); + Status = PeiServicesLocatePpi (&gPeiIscpPpiGuid, 0, NULL, (VOID**)&PeiIscpPpi); + ASSERT_EFI_ERROR (Status); - // Get fuse information from ISCP - Status = PeiIscpPpi->ExecuteFuseTransaction (PeiServices, &IscpFuseInfo); - ASSERT_EFI_ERROR (Status); + // Get fuse information from ISCP + Status = PeiIscpPpi->ExecuteFuseTransaction (PeiServices, &IscpFuseInfo); + ASSERT_EFI_ERROR (Status); - CpuMap = IscpFuseInfo.SocConfiguration.CpuMap; - CpuCoreCount = IscpFuseInfo.SocConfiguration.CpuCoreCount; - CpuMapSize = sizeof (IscpFuseInfo.SocConfiguration.CpuMap) * 8; + CpuMap = IscpFuseInfo.SocConfiguration.CpuMap; + CpuCoreCount = IscpFuseInfo.SocConfiguration.CpuCoreCount; + CpuMapSize = sizeof (IscpFuseInfo.SocConfiguration.CpuMap) * 8; - ASSERT (CpuMap != 0); - ASSERT (CpuCoreCount != 0); - ASSERT (CpuCoreCount <= CpuMapSize); + ASSERT (CpuMap != 0); + ASSERT (CpuCoreCount != 0); + ASSERT (CpuCoreCount <= CpuMapSize); - // Update core count based on fusing - if (mAmdCoreCount > CpuCoreCount) { - mAmdCoreCount = CpuCoreCount; - } + // Update core count based on fusing + if (mAmdCoreCount > CpuCoreCount) { + mAmdCoreCount = CpuCoreCount; } // // Update per-core information from ISCP + // Walk CPU map to enumerate active cores // - if (!FixedPcdGetBool (PcdIscpSupport)) { - DEBUG ((EFI_D_ERROR, "Warning: Could not get CPU info via ISCP, using default values.\n")); - } else { - // - // Walk CPU map to enumerate active cores - // - for (CoreNum = 0, Index = 0; CoreNum < CpuMapSize && Index < mAmdCoreCount; ++CoreNum) { - if (CpuMap & 1) { - CpuResetInfo.CoreNum = CoreNum; - Status = PeiIscpPpi->ExecuteCpuRetrieveIdTransaction ( - PeiServices, &CpuResetInfo ); - ASSERT_EFI_ERROR (Status); - ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_DISABLED); - ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_UNDEFINED); - - mAmdMpCoreInfoTable[Index].ClusterId = CpuResetInfo.CoreStatus.ClusterId; - mAmdMpCoreInfoTable[Index].CoreId = CpuResetInfo.CoreStatus.CoreId; - - DEBUG ((EFI_D_ERROR, "Core[%d]: ClusterId = %d CoreId = %d\n", - Index, mAmdMpCoreInfoTable[Index].ClusterId, - mAmdMpCoreInfoTable[Index].CoreId)); - - // Next core in Table - ++Index; - } - // Next core in Map - CpuMap >>= 1; + for (CoreNum = 0, Index = 0; CoreNum < CpuMapSize && Index < mAmdCoreCount; ++CoreNum) { + if (CpuMap & 1) { + CpuResetInfo.CoreNum = CoreNum; + Status = PeiIscpPpi->ExecuteCpuRetrieveIdTransaction ( + PeiServices, &CpuResetInfo ); + ASSERT_EFI_ERROR (Status); + ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_DISABLED); + ASSERT (CpuResetInfo.CoreStatus.Status != CPU_CORE_UNDEFINED); + + mAmdMpCoreInfoTable[Index].ClusterId = CpuResetInfo.CoreStatus.ClusterId; + mAmdMpCoreInfoTable[Index].CoreId = CpuResetInfo.CoreStatus.CoreId; + + DEBUG ((EFI_D_ERROR, "Core[%d]: ClusterId = %d CoreId = %d\n", + Index, mAmdMpCoreInfoTable[Index].ClusterId, + mAmdMpCoreInfoTable[Index].CoreId)); + + // Next core in Table + ++Index; } + // Next core in Map + CpuMap >>= 1; + } - // Update core count based on CPU map - if (mAmdCoreCount > Index) { - mAmdCoreCount = Index; - } + // Update core count based on CPU map + if (mAmdCoreCount > Index) { + mAmdCoreCount = Index; } // Update SocCoreCount on Dynamic PCD @@ -212,14 +204,12 @@ PlatInitPeiEntryPoint ( // Get SystemMemorySize from ISCP IscpMemDescriptor.Size0 = 0; - if (FixedPcdGetBool (PcdIscpSupport)) { - Status = PeiIscpPpi->ExecuteMemoryTransaction (PeiServices, &IscpMemDescriptor); - ASSERT_EFI_ERROR (Status); + Status = PeiIscpPpi->ExecuteMemoryTransaction (PeiServices, &IscpMemDescriptor); + ASSERT_EFI_ERROR (Status); - // Update SystemMemorySize on Dynamic PCD - if (IscpMemDescriptor.Size0) { - PcdSet64 (PcdSystemMemorySize, IscpMemDescriptor.Size0); - } + // Update SystemMemorySize on Dynamic PCD + if (IscpMemDescriptor.Size0) { + PcdSet64 (PcdSystemMemorySize, IscpMemDescriptor.Size0); } if (IscpMemDescriptor.Size0 == 0) { DEBUG ((EFI_D_ERROR, "Warning: Could not get SystemMemorySize via ISCP, using default value.\n")); @@ -229,19 +219,17 @@ PlatInitPeiEntryPoint ( #if DO_XGBE == 1 // Get MAC Address from ISCP - if (FixedPcdGetBool (PcdIscpSupport)) { - Status = PeiIscpPpi->ExecuteGetMacAddressTransaction ( - PeiServices, &MacAddrInfo ); - ASSERT_EFI_ERROR (Status); - - MacAddr0 = MacAddr1 = 0; - for (Index = 0; Index < 6; ++Index) { - MacAddr0 |= (UINT64)MacAddrInfo.MacAddress0[Index] << (Index * 8); - MacAddr1 |= (UINT64)MacAddrInfo.MacAddress1[Index] << (Index * 8); - } - PcdSet64 (PcdEthMacA, MacAddr0); - PcdSet64 (PcdEthMacB, MacAddr1); + Status = PeiIscpPpi->ExecuteGetMacAddressTransaction ( + PeiServices, &MacAddrInfo ); + ASSERT_EFI_ERROR (Status); + + MacAddr0 = MacAddr1 = 0; + for (Index = 0; Index < 6; ++Index) { + MacAddr0 |= (UINT64)MacAddrInfo.MacAddress0[Index] << (Index * 8); + MacAddr1 |= (UINT64)MacAddrInfo.MacAddress1[Index] << (Index * 8); } + PcdSet64 (PcdEthMacA, MacAddr0); + PcdSet64 (PcdEthMacB, MacAddr1); DEBUG ((EFI_D_ERROR, "EthMacA = 0x%lX\n", PcdGet64 (PcdEthMacA))); DEBUG ((EFI_D_ERROR, "EthMacB = 0x%lX\n", PcdGet64 (PcdEthMacB))); diff --git a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf index ccc079bebab2..b8829a4a9c3e 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf +++ b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.inf @@ -67,7 +67,6 @@ [Pcd] gAmdStyxTokenSpaceGuid.PcdEthMacB [FixedPcd] - gAmdStyxTokenSpaceGuid.PcdIscpSupport gAmdStyxTokenSpaceGuid.PcdCpuIdRegister [Depex] diff --git a/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c index 4bf9fc39942f..bcb6e020a5fd 100644 --- a/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c +++ b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c @@ -455,16 +455,7 @@ STATIC SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { 0, // ConfiguredMemoryClockSpeed; }; -#if (FixedPcdGetBool (PcdIscpSupport)) STATIC CHAR8 CONST *mMemDevInfoType17Strings[ 7 ] = {0}; -#else -STATIC CHAR8 CONST * CONST mMemDevInfoType17Strings[] = { - "OS Virtual Memory", - "malloc", - "OSV", - NULL -}; -#endif /*********************************************************************** SMBIOS data definition TYPE19 Memory Array Mapped Address Information @@ -648,7 +639,6 @@ ProcessorInfoUpdateSmbiosType4 ( VOID ) { -#if (FixedPcdGetBool (PcdIscpSupport)) ISCP_TYPE4_SMBIOS_INFO *SmbiosT4 = &mSmbiosInfo.SmbiosCpuBuffer.T4[0]; DEBUG ((EFI_D_ERROR, "Logging SmbiosType4 from ISCP.\n")); @@ -671,22 +661,6 @@ ProcessorInfoUpdateSmbiosType4 ( &SmbiosT4->T4ProcId.ProcIDMsd, sizeof(UINT32)); CopyMem (&mProcessorInfoType4.Voltage, &SmbiosT4->T4Voltage, sizeof(UINT8)); -#else - mProcessorInfoType4.ProcessorType = CentralProcessor; - mProcessorInfoType4.ProcessorFamily = ProcessorFamilyIndicatorFamily2; - mProcessorInfoType4.ProcessorFamily2 = ProcessorFamilyARM; - #ifdef ARM_CPU_AARCH64 - mProcessorInfoType4.ProcessorCharacteristics = 0x6C; - #else - mProcessorInfoType4.ProcessorCharacteristics = 0x68; - #endif - mProcessorInfoType4.MaxSpeed = PcdGet32(PcdArmArchTimerFreqInHz)/1000000; // In MHz - mProcessorInfoType4.CurrentSpeed = PcdGet32(PcdArmArchTimerFreqInHz)/1000000; // In MHz - mProcessorInfoType4.CoreCount = PcdGet32(PcdCoreCount); - mProcessorInfoType4.EnabledCoreCount = PcdGet32(PcdCoreCount); - mProcessorInfoType4.ThreadCount = PcdGet32(PcdCoreCount); - mProcessorInfoType4.ProcessorUpgrade = ProcessorUpgradeDaughterBoard; -#endif LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mProcessorInfoType4, mProcessorInfoType4Strings); } @@ -700,7 +674,6 @@ CacheInfoUpdateSmbiosType7 ( VOID ) { -#if (FixedPcdGetBool (PcdIscpSupport)) ISCP_TYPE7_SMBIOS_INFO *SmbiosT7; SMBIOS_TABLE_TYPE7 dstType7 = {{0}}; @@ -756,9 +729,6 @@ CacheInfoUpdateSmbiosType7 ( dstType7.SystemCacheType = SmbiosT7->T7SystemCacheType; dstType7.Associativity = SmbiosT7->T7Associativity; LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType7, mCacheInfoType7Strings); -#else - LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7, mCacheInfoType7Strings); -#endif } /*********************************************************************** @@ -782,7 +752,6 @@ PhyMemArrayInfoUpdateSmbiosType16 ( VOID ) { -#if (FixedPcdGetBool (PcdIscpSupport)) ISCP_TYPE16_SMBIOS_INFO *SmbiosT16 = &mSmbiosInfo.SmbiosMemBuffer.T16; DEBUG ((EFI_D_ERROR, "Logging SmbiosType16 from ISCP.\n")); @@ -791,7 +760,6 @@ PhyMemArrayInfoUpdateSmbiosType16 ( mPhyMemArrayInfoType16.Use = SmbiosT16->Use; mPhyMemArrayInfoType16.MemoryErrorCorrection = SmbiosT16->MemoryErrorCorrection; mPhyMemArrayInfoType16.NumberOfMemoryDevices = SmbiosT16->NumberOfMemoryDevices; -#endif LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mPhyMemArrayInfoType16, mPhyMemArrayInfoType16Strings); } @@ -805,7 +773,6 @@ MemDevInfoUpdatedstType17 ( VOID ) { -#if (FixedPcdGetBool (PcdIscpSupport)) SMBIOS_TABLE_TYPE17 dstType17 = {{0}}; ISCP_TYPE17_SMBIOS_INFO *srcType17; UINTN i, j, StrIndex, LastIndex; @@ -874,9 +841,6 @@ MemDevInfoUpdatedstType17 ( LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&dstType17, mMemDevInfoType17Strings); } } -#else - LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mMemDevInfoType17, mMemDevInfoType17Strings); -#endif } /*********************************************************************** @@ -888,7 +852,6 @@ MemArrMapInfoUpdateSmbiosType19 ( VOID ) { -#if (FixedPcdGetBool (PcdIscpSupport)) ISCP_TYPE19_SMBIOS_INFO *SmbiosT19 = &mSmbiosInfo.SmbiosMemBuffer.T19; DEBUG ((EFI_D_ERROR, "Logging SmbiosType19 from ISCP.\n")); @@ -899,7 +862,6 @@ MemArrMapInfoUpdateSmbiosType19 ( mMemArrMapInfoType19.PartitionWidth = SmbiosT19->PartitionWidth; mMemArrMapInfoType19.ExtendedStartingAddress = SmbiosT19->ExtStartingAddr; mMemArrMapInfoType19.ExtendedEndingAddress = SmbiosT19->ExtEndingAddr; -#endif LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mMemArrMapInfoType19, mMemArrMapInfoType19Strings); } @@ -946,7 +908,6 @@ PlatformSmbiosDriverEntryPoint ( return Status; } -#if (FixedPcdGetBool (PcdIscpSupport)) Status = gBS->LocateProtocol ( &gAmdIscpDxeProtocolGuid, NULL, @@ -966,7 +927,6 @@ PlatformSmbiosDriverEntryPoint ( DEBUG ((EFI_D_ERROR, "Failed to get SMBIOS data via ISCP")); return Status; } -#endif BIOSInfoUpdateSmbiosType0(); diff --git a/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf index 0027d79031d7..76521cbde59e 100644 --- a/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf +++ b/Silicon/AMD/Styx/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf @@ -52,7 +52,6 @@ [Guids] [FixedPcd] gArmPlatformTokenSpaceGuid.PcdCoreCount gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz - gAmdStyxTokenSpaceGuid.PcdIscpSupport [Depex] gEfiSmbiosProtocolGuid AND diff --git a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf index d17e6c26feb5..db7ce6af33d1 100644 --- a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf +++ b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.inf @@ -72,8 +72,6 @@ [FixedPcd] gAmdStyxTokenSpaceGuid.PcdTrustedFWMemoryBase gAmdStyxTokenSpaceGuid.PcdTrustedFWMemorySize - gAmdStyxTokenSpaceGuid.PcdIscpSupport - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize diff --git a/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c b/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c index 1b926242b5bb..11f398ad29e2 100644 --- a/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c +++ b/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.c @@ -60,10 +60,6 @@ LibGetTime ( ISCP_RTC_INFO RtcInfo; EFI_STATUS Status; - if (!FixedPcdGetBool (PcdIscpSupport)) { - return EFI_DEVICE_ERROR; - } - if (mRtcIscpDxeProtocol == NULL) { DEBUG((EFI_D_ERROR, "RTC: ISCP DXE Protocol is NULL!\n")); return EFI_DEVICE_ERROR; @@ -111,10 +107,6 @@ LibSetTime ( EFI_STATUS Status; ISCP_RTC_INFO RtcInfo; - if (!FixedPcdGetBool (PcdIscpSupport)) { - return EFI_DEVICE_ERROR; - } - // // Use Time, to set the time in your RTC hardware // @@ -213,10 +205,6 @@ LibRtcInitialize ( { EFI_STATUS Status; - if (!FixedPcdGetBool (PcdIscpSupport)) { - return EFI_SUCCESS; - } - // // Do some initialization if required to turn on the RTC // @@ -268,9 +256,7 @@ LibRtcVirtualNotifyEvent ( // to virtual address. After the OS transistions to calling in virtual mode, all future // runtime calls will be made in virtual mode. // - if (FixedPcdGetBool (PcdIscpSupport)) { - EfiConvertPointer (0x0, (VOID**)&mRtcIscpDxeProtocol); - } + EfiConvertPointer (0x0, (VOID**)&mRtcIscpDxeProtocol); } diff --git a/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf b/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf index cd9418c9b732..5392bd076cf0 100644 --- a/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf +++ b/Silicon/AMD/Styx/Library/RealTimeClockLib/RealTimeClockLib.inf @@ -41,9 +41,6 @@ [LibraryClasses] UefiRuntimeLib DxeServicesTableLib -[FixedPcd] - gAmdStyxTokenSpaceGuid.PcdIscpSupport - [Guids] gEfiEventVirtualAddressChangeGuid -- 2.17.0