From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=147.11.146.13; helo=mail1.windriver.com; envelope-from=bill.paul@windriver.com; receiver=edk2-devel@lists.01.org Received: from mail1.windriver.com (mail1.windriver.com [147.11.146.13]) (using TLSv1.1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 47134203B8CE6 for ; Mon, 28 May 2018 13:41:08 -0700 (PDT) Received: from ALA-HCA.corp.ad.wrs.com ([147.11.189.40]) by mail1.windriver.com (8.15.2/8.15.1) with ESMTPS id w4SKf6Dk018577 (version=TLSv1 cipher=AES128-SHA bits=128 verify=FAIL); Mon, 28 May 2018 13:41:06 -0700 (PDT) Received: from ala-wpaul-lx1.wrs.com (147.11.157.242) by ALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 28 May 2018 13:41:06 -0700 From: Bill Paul Organization: Wind River Systems To: Date: Mon, 28 May 2018 13:36:09 -0700 User-Agent: KMail/1.13.5 (Linux/2.6.32-28-generic; KDE/4.4.5; x86_64; ; ) CC: "Ni, Ruiyu" , Laszlo Ersek References: <110011b4-f9cc-9f8b-53f8-f12cfe7416b2@redhat.com> <734D49CCEBEEF84792F5B80ED585239D5BD0C8CB@SHSMSX104.ccr.corp.intel.com> In-Reply-To: <734D49CCEBEEF84792F5B80ED585239D5BD0C8CB@SHSMSX104.ccr.corp.intel.com> MIME-Version: 1.0 Message-ID: <201805281336.10118.wpaul@windriver.com> Subject: Re: PciSegmentInfoLib instances X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 May 2018 20:41:08 -0000 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Of all the gin joints in all the towns in all the world, Ni, Ruiyu had to walk into mine at 19:55 on Sunday 27 May 2018 and say: > No. There is no such instance. > > My understanding: > Segment is just to separate the PCI devices to different groups. > Each group of devices use the continuous BUS/IO/MMIO resource. > Each group has a BASE PCIE address that can be used to access PCIE > configuration in MMIO way. This makes it sound like an either/or design choice that a hardware designer can make simply for some kind of convenience, and I don't think that's the case. Segments typically indicate completely separate host/PCI interfaces. For example, I've seen older Intel boards with both 32-bit/33MHz slots and 64- bit/66MHz slots. This was not done with a bridge: each set of slots was tied to a completely separate host PCI bridge and hence each was a separate segment. This was required in order to support legacy 32-bit/33MHz devices without forcing the 64-bit/66MHz devices down to 33MHz as well. With PCIe, on platforms other than Intel, each root complex would also be a separate segment. Each root complex would have its own bus/dev/func namespace, its own configuration space access method, and its own portion of the physical address space into which to map BARs. This means that you could have two or more different devices with the same bus/dev/func identifier tuple, meaning they are not unique on a platform-wide basis. At the hardware level, PCIe may be implemented similarly on Intel too, but they hide some of the details from you. The major difference is that even in cases where you may have multiple PCIe channels, they all share the same bus/dev/func namespace so that you can pretend the bus/dev/func tuples are unique platform-wide. The case where you would need to advertise multiple segments arises where there's some technical roadblock that prevents implementing this illusion of a single namespace in a completely transparent way. In the case of the 32-bit/64-bit hybrid design I mentioned above, scanning the bus starting from bus0/dev0/func0 would only allow you to automatically discover the 32-bit devices because there was no bridge between the 32-bit and 64-bit spaces. The hardware allows you to issue configuration accesses to both spaces using the same 0xcf8/0xcfc registers, but in order to autodiscover the 64-bit devices, you needed know ahead of time to also scan starting at bus1/dev0/func0. But the only way to know to do that was to check the advertised segments in the ACPI device table and honor their starting bus numbers. > So with the above understanding, even a platform which has single segment > can be implemented as a multiple segments platform. I would speculate this might only be true on Intel. :) Intel is the only platform that creates the illusion of a single bus/dev/func namespace for multiple PCI "hoses," and it only does that for backward compatibility purposes (i.e. to make Windows happy). Without that gimmick, each segment would be a separate tree rooted at bus0/dev0/func0, and there wouldn't be much point to doing that if you only had a single root complex. -Bill > Thanks/Ray > > > -----Original Message----- > > From: edk2-devel On Behalf Of Laszlo > > Ersek > > Sent: Wednesday, May 23, 2018 3:38 PM > > To: Ni, Ruiyu > > Cc: edk2-devel-01 > > Subject: [edk2] PciSegmentInfoLib instances > > > > Hi Ray, > > > > do you know of any open source, non-Null, PciSegmentInfoLib instance? > > (Possibly outside of edk2?) > > > > More precisely, it's not the PciSegmentInfoLib instance itself that's of > > particular interest, but the hardware and the platform support code that > > offer multiple PCIe segments. > > > > Thanks > > Laszlo > > _______________________________________________ > > edk2-devel mailing list > > edk2-devel@lists.01.org > > https://lists.01.org/mailman/listinfo/edk2-devel > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel -- ============================================================================= -Bill Paul (510) 749-2329 | Senior Member of Technical Staff, wpaul@windriver.com | Master of Unix-Fu - Wind River Systems ============================================================================= "I put a dollar in a change machine. Nothing changed." - George Carlin =============================================================================