From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::233; helo=mail-wm0-x233.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x233.google.com (mail-wm0-x233.google.com [IPv6:2a00:1450:400c:c09::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8ED9F210C9985 for ; Wed, 30 May 2018 11:19:38 -0700 (PDT) Received: by mail-wm0-x233.google.com with SMTP id 18-v6so43933965wml.2 for ; Wed, 30 May 2018 11:19:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cw2vi7HLHO3WaOEBU2ul3+x4/qgdXHTLiFXzAKjeLKo=; b=fkvS55e3iwNDvHwcGzIGzXxCaPn7UWUJWNS0lM/jpwwz10cg1UgeJ7VhCVg6U9Aw7C tzj0+/Qoj0fBMcDOmpVtr/RrSJEiI2cRM7Qe9tyAknMgAgXZJmw3aLpC0+OkfqWM6+p2 BSrkzDVzBaxPNKeFuvY6lU9Vvg4jyTWT4Ip+c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cw2vi7HLHO3WaOEBU2ul3+x4/qgdXHTLiFXzAKjeLKo=; b=WnUVoryuYRZ7ExVPmxsuR2daJW/PR8kPDuBCeLOsP9VPMKR0x1FfDB9J4kdR3AvRh3 JgyVECqML781qpTTRd1LHeRnm7ADOrCl6ebDZC+012Ykz0dDK+6kQnUXt4C1m8KTab7B tVrafpWspyP9bJu7cTaNoAcb06Dqt9JHtp7n1WWb6eB1/E+YF/zvgkmJHR2owPddw1jB dGLX+mYYoQ9MNPmS5czqKGen9GyaYFt4IRD7dLo/NjBgPR1vQr6rAWvX9jcnVH+c3G6C L1bKvt3xqI3KdPy3mgtxsl/IkGcntXW8YwO/JFvIZmsnR4dErZKGY/rP3LOy+N2TFIzP LfBg== X-Gm-Message-State: ALKqPwemuDZEJ4xNvGAvSKNAFQg/c+/bxa/PjpXoQLCnp1AkQMkPqrZl pLBbaFjn36FLWTAot1uYrA4rOwdSZAk= X-Google-Smtp-Source: ADUXVKIx8vjXnOfyjPFDUgeOmLEItOaTTau+vSLd61PzssBSWA0Hlzza9U9YPoKSsDoYolT3NbCDRw== X-Received: by 2002:a1c:6952:: with SMTP id e79-v6mr2380730wmc.76.1527704376794; Wed, 30 May 2018 11:19:36 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id b105-v6sm48315705wrd.64.2018.05.30.11.19.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 11:19:36 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, masahisa.kojima@linaro.org, Ard Biesheuvel Date: Wed, 30 May 2018 20:19:28 +0200 Message-Id: <20180530181929.5066-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530181929.5066-1-ard.biesheuvel@linaro.org> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms 2/3] Silicon/Socionext/SynQuacer/Stage2Tables: add north SMMU level 3 table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 May 2018 18:19:38 -0000 Extend the static stage 2 page tables with a set of level 3 tables that describe the ECAM space in a manner that allows the north SMMU to be used to make the ECAM space appear sane to the CPUs. It is up to the secure firmware to manipulate the north SMMU page tables so that the level 2 block entries corresponding with busses #0 .. #1 in the respective config spaces of PCI0 and PCI1 are replaced with table entries pointing to the level 3 tables added by this patch. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 35 +++++++++++++++----- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S index 313ef3c56abc..af55f27bca47 100644 --- a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S +++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S @@ -20,15 +20,17 @@ * the SoC. */ -#define TT_S2_CONT_SHIFT 52 -#define TT_S2_AF (0x1 << 10) -#define TT_S2_SH_NON_SHAREABLE (0x0 << 8) -#define TT_S2_AP_RW (0x3 << 6) -#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2) -#define TT_S2_MEMATTR_MEMORY_WB (0xf << 2) -#define TT_S2_TABLE (0x3 << 0) -#define TT_S2_L3_PAGE (0x1 << 1) -#define TT_S2_VALID (0x1 << 0) +#define TT_S2_CONT_SHIFT 52 +#define TT_S2_AF (0x1 << 10) +#define TT_S2_SH_NON_SHAREABLE (0x0 << 8) +#define TT_S2_AP_RO (0x1 << 6) +#define TT_S2_AP_RW (0x3 << 6) +#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2) +#define TT_S2_MEMATTR_DEVICE_nGnRE (0x1 << 2) +#define TT_S2_MEMATTR_MEMORY_WB (0xf << 2) +#define TT_S2_TABLE (0x3 << 0) +#define TT_S2_L3_PAGE (0x1 << 1) +#define TT_S2_VALID (0x1 << 0) .altmacro .macro for, start, count, do, arg2, arg3, arg4 @@ -58,6 +60,12 @@ TT_S2_L3_PAGE | TT_S2_VALID | (\cont << TT_S2_CONT_SHIFT) .endm + .macro smmu_l3_entry, base, offset=0, ignore=0 + .quad ((\base << 12) + \offset) | TT_S2_AF | TT_S2_AP_RO | \ + TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_DEVICE_nGnRE | \ + TT_S2_L3_PAGE | TT_S2_VALID + .endm + .section ".rodata", "a", %progbits /* level 1 */ s2_mem_entry 0 /* 0x0000_0000 - 0x3fff_ffff */ @@ -86,3 +94,12 @@ 3:for 0, 8, s2_l3_entry, 0x70000000 for 0, 8, s2_l3_entry, 0x70010000 /* hide device #1 */ for 0, 496, s2_l3_entry, 0x70010000, 1 + + /* level 3 for north SMMU */ + .org 0x6000 + for 0, 8, smmu_l3_entry, 0xc00060000000 + for 0, 8, smmu_l3_entry, 0xc00060010000 /* hide device #1 */ + for 0, 496, smmu_l3_entry, 0xc00060010000 + for 0, 8, smmu_l3_entry, 0x800070000000 + for 0, 8, smmu_l3_entry, 0x800070010000 /* hide device #1 */ + for 0, 496, smmu_l3_entry, 0x800070010000 -- 2.17.0