From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::242; helo=mail-pf0-x242.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x242.google.com (mail-pf0-x242.google.com [IPv6:2607:f8b0:400e:c00::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5CE2120977888 for ; Wed, 30 May 2018 18:02:09 -0700 (PDT) Received: by mail-pf0-x242.google.com with SMTP id a14-v6so9883018pfi.1 for ; Wed, 30 May 2018 18:02:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:date:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=eIv9uC0ounwTv8NSehkCa9PUthpBdpgJEuL2EO4ny+0=; b=BpMi7yB5uB0XCmy3mh9u2H5iaP3/0ZzjtwPs/5nrwisoZyG+MjtZcP9p74owp2nnsk M1mPXShCs1CsdXdC+wo9tMj+zLDmbK3lS4H30IerHP+Ot1rjtvFJobS7e2QMRxHG+zWB A96UUGJeKEvEfndC+C9yU9m3oDzsR2VQjMyuM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:date:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=eIv9uC0ounwTv8NSehkCa9PUthpBdpgJEuL2EO4ny+0=; b=SbGsF6G/VToxe5owQkqEcBW96vGye+ONGdcAw6AKEto25CNPNRZMdeeA0Q+oPOwCvD gY/KJNvsMmnF/UrNcMtfnqTJy5RhRptkGQtcgnZ7KzrNIOVQi2uGV/yNgW8KzegHDMUm Kfloky/8RrSNENu+iOckPklXjCyfbanmvtU0BuqN4DeNygwZzhk1snFjcf8de1Morqe0 kjAuy+7/nQ6oTQNthR9U5QOAkz11uUFE+5iKd8LYCEp8yeZbu0dA3QPM401YzVA+DkZJ QmWdOKIuBwKJcL3Jpud2eO1V1cF8czhNZhfJ7xATuuV4u/x289pd2J0VLQLz0vYjDrgE Xpbg== X-Gm-Message-State: ALKqPwetUO+frKNDOljASnFEOik/ybLw5jrwLlC8IDAQHhb7eWo4W6rG s4rf0EOVXd9pDUPIQjwNojBF2CJ7GW4= X-Google-Smtp-Source: ADUXVKJh8SM5+dqrq9qkWPmOsJme4UrPTwbeD5jRlry9ow6GSootIyJsDZucg17sAJRiIZAzigZmmQ== X-Received: by 2002:a65:6101:: with SMTP id z1-v6mr3893391pgu.23.1527728527261; Wed, 30 May 2018 18:02:07 -0700 (PDT) Received: from ecs-e536.expressvpn ([45.56.152.105]) by smtp.gmail.com with ESMTPSA id x72-v6sm9199607pff.176.2018.05.30.18.02.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 18:02:06 -0700 (PDT) From: heyi.guo@linaro.org X-Google-Original-From: g00179230@ecs-e536.expressvpn Date: Thu, 31 May 2018 09:02:02 +0800 To: Ard Biesheuvel Cc: Ard Biesheuvel , Leif Lindholm , "edk2-devel@lists.01.org" , Michael D Kinney , Haojian Zhuang Message-ID: <20180531010202.GA8926@ecs-e536.expressvpn> References: <20180328010531.GA69547@SZX1000114654> <20180329002050.GB97590@SZX1000114654> <20180331013747.GA106704@SZX1000114654> <20180413020553.GB119834@SZX1000114654> <20180416135709.GA122959@SZX1000114654> <20180417012044.GA123329@SZX1000114654> <20180417014446.GB123329@SZX1000114654> MIME-Version: 1.0 In-Reply-To: <20180417014446.GB123329@SZX1000114654> User-Agent: Mutt/1.5.24 (2015-08-30) Subject: Re: [PATCH edk2-platforms 00/12] Hisilicon/D0x: Switch to generic PciHostBridge X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 May 2018 01:02:09 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ard, Have you returned from vocation? If so, could you help to continue reviewing this patch series? Thanks, Heyi On Tue, Apr 17, 2018 at 09:44:46AM +0800, Guo Heyi wrote: > BTW, there is actually a bug with ATU configuration which will cause IO access > failure, and we need to apply an additional patch (this patch is generated after > PCI host bridge patch series) as attached to fix this. > > Regards, > Heyi > > On Tue, Apr 17, 2018 at 09:20:44AM +0800, Guo Heyi wrote: > > Hi Ard, > > > > I tested mm -io on D05, for root bridge 4 with CPU IO address starting from > > 0x8_abff0000, and it worked; both mm -io 0x8abff0000 and mm 0x8abff0000 provided > > the same output. It seems there is no other limit for 64bit IO address after you > > fixed the issue in EFI shell mm command. > > > > Thanks and regards, > > > > Heyi > > > > On Mon, Apr 16, 2018 at 09:57:09PM +0800, Guo Heyi wrote: > > > Thanks, I will test mm command and let you know the result. > > > > > > Regards, > > > > > > Heyi > > > > > > On Fri, Apr 13, 2018 at 09:19:53AM +0200, Ard Biesheuvel wrote: > > > > On 13 April 2018 at 04:05, Guo Heyi wrote: > > > > > Hi Ard, > > > > > > > > > > Any comments? > > > > > > > > > > > > > Apologies for the delay. I have been travelling and am behind on email. > > > > > > > > > Anyway we can modify the code if you insist on using an intermediate CPU IO > > > > > address space. > > > > > > > > > > > > > I have not made up my mind yet, to be honest. I agree there is a > > > > certain elegance to merging both translations, but I am concerned that > > > > existing EDK2 code may deal poorly with I/O addresses that require > > > > more than 32 bits to express. > > > > > > > > Did you try the mm command in the shell for instance? As you know, I > > > > recently removed an artificial address range limit there, but I wonder > > > > if it uses 64-bit variables for I/O ports. > From guoheyi@huawei.com Tue Apr 17 09:40:07 2018 > Delivered-To: heyi.guo@linaro.org > Received: by 10.103.107.2 with SMTP id g2csp1147351vsc; > Mon, 16 Apr 2018 18:40:07 -0700 (PDT) > X-Google-Smtp-Source: AIpwx49xa2EjXi3IIuqoYaJ9ZR+KlZePkYWmAvMpJl534IXT0zWt/Jd5UHxMjyCgas2Aluws+S26 > X-Received: by 10.101.97.165 with SMTP id i5mr102113pgv.449.1523929207660; > Mon, 16 Apr 2018 18:40:07 -0700 (PDT) > ARC-Seal: i=1; a=rsa-sha256; t=1523929207; cv=none; > d=google.com; s=arc-20160816; > b=JVhwQqc2tHJH/nbb9J4Q5EAe7efNCva8XlNdyeM1AjecnvMtalXxRiIcVSIp2CTTUb > RCfB400z6ay0s7SW96MDtN0D8jezfXLZXyuMQTqYAvpXu7rxEmXGJtKblXaJ303GTvgS > kavhZQ7QawTzXzWTjokcARGeyR+mFb9aXT8JKm3jdHVM+Ibsjl0HFYSFrMNFoeyC7EqG > EPMbjEvcWolADxpywSCM0s0e4EhIVpGrhi1LgdVeATsyrb6GN8sEscVfb+t0b0gMj6XI > Nqg7mMHnKZGJ4vmkJBRV5Gx+nnQbOWKsOCp8YZcVLFs8hyqWFokYsup3wsY1YtktovxU > GQUg== > ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; > h=mime-version:message-id:date:subject:cc:to:from > :arc-authentication-results; > bh=MzafS17Rdgthy05RGe4B87hGASmPkGgjBWmjX1ExxLo=; > b=fj+XbZcdH1vGFsHllnQeTc3zRavri5L0Use7rHdCRemtfNojWbY1QJKD6tMVi213fj > J9IaKL5/Q3Uh0KLfAR848Whbuj4IiFMw1vRsT8BUvu0QjkCsdJo66ypGdQTqkysdtk2X > fdNfNTE+Dfa1du8Yx9RiFCetXrtgCjDXljVzd/JufSlKtC41HjgWjnqC2Jka4N0MOT1W > oiBtsqOCjRuVRyb5Rlf7RVstwZ7wz6jXbxj7GYkr85bUFe7LNG8HOKxJYIv1bLyOWw6q > KvttRU9MKaVex3HApPoMIIgg+sXj3QD1islzlobdLA/OaRKWXCH0fnXH/NuWnKZ7J1jO > Hl7A== > ARC-Authentication-Results: i=1; mx.google.com; > spf=pass (google.com: domain of guoheyi@huawei.com designates 45.249.212.32 as permitted sender) smtp.mailfrom=guoheyi@huawei.com > Return-Path: > Received: from huawei.com ([45.249.212.32]) > by mx.google.com with ESMTPS id t3si10564595pgt.547.2018.04.16.18.40.07 > for > (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); > Mon, 16 Apr 2018 18:40:07 -0700 (PDT) > Received-SPF: pass (google.com: domain of guoheyi@huawei.com designates 45.249.212.32 as permitted sender) client-ip=45.249.212.32; > Authentication-Results: mx.google.com; > spf=pass (google.com: domain of guoheyi@huawei.com designates 45.249.212.32 as permitted sender) smtp.mailfrom=guoheyi@huawei.com > Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.58]) > by Forcepoint Email with ESMTP id 2B03711A12683 > for ; Tue, 17 Apr 2018 09:40:04 +0800 (CST) > Received: from HGH1000039998.huawei.com (10.184.68.188) by > DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id > 14.3.361.1; Tue, 17 Apr 2018 09:39:59 +0800 > From: Heyi Guo > To: > CC: , , > > Subject: [PATCH] Hisilicon/Hi161x/PcieInit: fix address overlap > Date: Tue, 17 Apr 2018 09:35:22 +0800 > Message-ID: <1523928922-9573-1-git-send-email-guoheyi@huawei.com> > X-Mailer: git-send-email 2.8.1 > MIME-Version: 1.0 > Content-Type: text/plain > X-Originating-IP: [10.184.68.188] > X-CFilter-Loop: Reflected > Content-Length: 2888 > Lines: 55 > > From: Heyi Guo > > PCIe IO address ranges are overlapped by configuration address spaces > when we set CFG0/CFG1 address range starting from ECAM. It causes > access to IO space is routed to configuration space and returned with > wrong results. > > So we limit address space for configuration type 0 > starting from BusBase and type 1 from (BusBase + 2), to eliminate the > address range overlapping. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Heyi Guo > --- > Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c > index f2365b5..9a92fea 100644 > --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c > +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c > @@ -96,11 +96,12 @@ SetAtuConfig0RW ( > { > UINTN RbPciBase = Private->RbPciBar; > UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1; > + UINT64 MemBase = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0, 0, 0); > > > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)MemBase); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(MemBase >> 32)); > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); > @@ -124,12 +125,13 @@ SetAtuConfig1RW ( > { > UINTN RbPciBase = Private->RbPciBar; > UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1; > + UINT64 MemBase = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0); > > > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)MemBase); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(MemBase >> 32)); > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); > MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); > -- > 2.8.1 > >