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[2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id i76-v6sm1549946wmd.20.2018.05.31.02.11.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 31 May 2018 02:11:22 -0700 (PDT) Date: Thu, 31 May 2018 10:11:20 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, masahisa.kojima@linaro.org Message-ID: <20180531091120.u3oqbzskpr6rnhen@bivouac.eciton.net> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> <20180530181929.5066-2-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180530181929.5066-2-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 1/3] Silicon/SynQuacerPciHostBridgeLib: add workaround for PCIe MMIO64 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 May 2018 09:11:25 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, May 30, 2018 at 08:19:27PM +0200, Ard Biesheuvel wrote: > From: Masahisa KOJIMA > > The current revision of SC2A11 contains PCIe bus issue. > In MRd transaction, 1st/Last DW BE fields are not correctly set > by hardware. > > As a workaround, set TH bit and specify MSG_CODE in iATU. > With this setup, the value specified as MSG_CODE is set to the > 1st/Last DW BE fields and PCIe controller can emit the correct > MRd TLP header. > Same workaround was already included for MMIO32 region, > MMIO64 region also requires this workaround. > Some deivices, such as Samsong SSD 970 EVO, do not work > without this modification. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Masahisa KOJIMA Please add own S-o-b. > --- > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > index e4679543cc66..227f9a725ce8 100644 > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > @@ -359,8 +359,9 @@ PciInitControllerPost ( > RootBridge->MemAbove4G.Base, > RootBridge->MemAbove4G.Base, > RootBridge->MemAbove4G.Limit - RootBridge->MemAbove4G.Base + 1, > - IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, > - 0); > + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | > + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, > + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); Hmm ... This fix clearly needs to go in. But since this is working around a bug in first-revision silicon, should we not have something conditional here? / Leif > } > > // enable link > -- > 2.17.0 >