From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2795720D7B25D for ; Thu, 31 May 2018 02:14:42 -0700 (PDT) Received: by mail-wr0-x241.google.com with SMTP id l41-v6so32276577wre.7 for ; Thu, 31 May 2018 02:14:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=uw3foeYOjwzYm34s94YFiNcR3z7jwHpsGhgD75fl9eM=; b=H0vx79yfede8SMUgjYy0EMkyKpdaKMuSOmTDyDd72Li12c3hvbVP4Eak3Z+H/4qJy/ o6pB8eeQpunH09mhR6nS+5Qgido304fAAArvZiwaG4Y/UzZ1oNz44uuqnn5sS/873e6m yfDktpoZSg8t799NdC0HG8veQ1j8CxUwwMAkE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=uw3foeYOjwzYm34s94YFiNcR3z7jwHpsGhgD75fl9eM=; b=deAiwTQ+KXA3cQ+Y2FNqLtkjET9hNExED3tEn33OUdfZIH4wFCdJv570qlkbxjuR+C KcfR341oqS9FgZ+30TtjU8sOOp/6npxKgF7hwcSz78b18YT0FwlsY3MCDSdPGCTShLg/ fTYxkPTJ6r4DCNIlNKZME5UwR9rjt5QfxoeUYsUbDxU4XrGR6MnpHdpWAZN7LacMiHd/ ZQ1cr8Uyk8TqNPH6sn2oFV5TGU0+L2mfWkaUbn4U39uGfEQMXm3GDQ/XVrfA0lzsNjhY FaapuLDZ+Q9/KfbjzewDpexodfeOid3CTaFIq44pko4DFI32qAdtI6VBU9SC/mcpjG1I FYPg== X-Gm-Message-State: ALKqPweYFcjwH7oh2JMFxgR3O7YgsNOnwjCRPUI00k4G1oVKA1KKiWv8 9OEF2TYTm8PIcoKdLE3tPPosQw== X-Google-Smtp-Source: ADUXVKL9iykUyd7hus1CwVHFpgHF+tvDephl2BuBY8mrF3lxopNRndsnwFFFCWYIAAExqUHlOoqJXQ== X-Received: by 2002:adf:a0ea:: with SMTP id n39-v6mr4696978wrn.87.1527758080761; Thu, 31 May 2018 02:14:40 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id t46-v6sm46852708wrc.95.2018.05.31.02.14.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 31 May 2018 02:14:39 -0700 (PDT) Date: Thu, 31 May 2018 10:14:38 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, masahisa.kojima@linaro.org Message-ID: <20180531091438.wwfw2ymrhwte55hr@bivouac.eciton.net> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> <20180530181929.5066-3-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180530181929.5066-3-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 2/3] Silicon/Socionext/SynQuacer/Stage2Tables: add north SMMU level 3 table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 May 2018 09:14:42 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, May 30, 2018 at 08:19:28PM +0200, Ard Biesheuvel wrote: > Extend the static stage 2 page tables with a set of level 3 tables that > describe the ECAM space in a manner that allows the north SMMU to be used > to make the ECAM space appear sane to the CPUs. > > It is up to the secure firmware to manipulate the north SMMU page tables s/secure/EL3/ or s/secure/Secure/? With either of those: Reviewed-by: Leif Lindholm > so that the level 2 block entries corresponding with busses #0 .. #1 in > the respective config spaces of PCI0 and PCI1 are replaced with table > entries pointing to the level 3 tables added by this patch. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 35 +++++++++++++++----- > 1 file changed, 26 insertions(+), 9 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S > index 313ef3c56abc..af55f27bca47 100644 > --- a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S > +++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S > @@ -20,15 +20,17 @@ > * the SoC. > */ > > -#define TT_S2_CONT_SHIFT 52 > -#define TT_S2_AF (0x1 << 10) > -#define TT_S2_SH_NON_SHAREABLE (0x0 << 8) > -#define TT_S2_AP_RW (0x3 << 6) > -#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2) > -#define TT_S2_MEMATTR_MEMORY_WB (0xf << 2) > -#define TT_S2_TABLE (0x3 << 0) > -#define TT_S2_L3_PAGE (0x1 << 1) > -#define TT_S2_VALID (0x1 << 0) > +#define TT_S2_CONT_SHIFT 52 > +#define TT_S2_AF (0x1 << 10) > +#define TT_S2_SH_NON_SHAREABLE (0x0 << 8) > +#define TT_S2_AP_RO (0x1 << 6) > +#define TT_S2_AP_RW (0x3 << 6) > +#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2) > +#define TT_S2_MEMATTR_DEVICE_nGnRE (0x1 << 2) > +#define TT_S2_MEMATTR_MEMORY_WB (0xf << 2) > +#define TT_S2_TABLE (0x3 << 0) > +#define TT_S2_L3_PAGE (0x1 << 1) > +#define TT_S2_VALID (0x1 << 0) > > .altmacro > .macro for, start, count, do, arg2, arg3, arg4 > @@ -58,6 +60,12 @@ > TT_S2_L3_PAGE | TT_S2_VALID | (\cont << TT_S2_CONT_SHIFT) > .endm > > + .macro smmu_l3_entry, base, offset=0, ignore=0 > + .quad ((\base << 12) + \offset) | TT_S2_AF | TT_S2_AP_RO | \ > + TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_DEVICE_nGnRE | \ > + TT_S2_L3_PAGE | TT_S2_VALID > + .endm > + > .section ".rodata", "a", %progbits > /* level 1 */ > s2_mem_entry 0 /* 0x0000_0000 - 0x3fff_ffff */ > @@ -86,3 +94,12 @@ > 3:for 0, 8, s2_l3_entry, 0x70000000 > for 0, 8, s2_l3_entry, 0x70010000 /* hide device #1 */ > for 0, 496, s2_l3_entry, 0x70010000, 1 > + > + /* level 3 for north SMMU */ > + .org 0x6000 > + for 0, 8, smmu_l3_entry, 0xc00060000000 > + for 0, 8, smmu_l3_entry, 0xc00060010000 /* hide device #1 */ > + for 0, 496, smmu_l3_entry, 0xc00060010000 > + for 0, 8, smmu_l3_entry, 0x800070000000 > + for 0, 8, smmu_l3_entry, 0x800070010000 /* hide device #1 */ > + for 0, 496, smmu_l3_entry, 0x800070010000 > -- > 2.17.0 >