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From: Leif Lindholm <leif.lindholm@linaro.org>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: edk2-devel@lists.01.org, masahisa.kojima@linaro.org
Subject: Re: [PATCH edk2-platforms 3/3] Silicon/SynQuacer/AcpiTables: add NETSEC/eMMC SMMU to the IORT
Date: Thu, 31 May 2018 10:16:22 +0100	[thread overview]
Message-ID: <20180531091622.3u7dd2kjnu6fhb5w@bivouac.eciton.net> (raw)
In-Reply-To: <20180530181929.5066-4-ard.biesheuvel@linaro.org>

On Wed, May 30, 2018 at 08:19:29PM +0200, Ard Biesheuvel wrote:
> Add a description of the SMMU that sits in front of the NETSEC and
> eMMC controllers to the IORT table so that ACPI based OSes can
> utilize it.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Looks reasonable to me.
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 109 +++++++++++++++++++-
>  1 file changed, 107 insertions(+), 2 deletions(-)
> 
> diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc
> index 92c485f8006f..3f2aaa3d8858 100644
> --- a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc
> +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc
> @@ -13,6 +13,7 @@
>  **/
>  
>  #include <IndustryStandard/IoRemappingTable.h>
> +#include <Platform/MemoryMap.h>
>  
>  #include "AcpiTables.h"
>  
> @@ -29,10 +30,23 @@ typedef struct {
>    EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE        RcIdMapping;
>  } SYNQUACER_RC_NODE;
>  
> +typedef struct {
> +  EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE       Node;
> +  EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT        Context[8];
> +} SYNQUACER_SMMU_NODE;
> +
> +typedef struct {
> +  EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node;
> +  CONST CHAR8                               Name[11];
> +  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE        RcIdMapping;
> +} SYNQUACER_NC_NODE;
> +
>  typedef struct {
>    EFI_ACPI_6_0_IO_REMAPPING_TABLE           Iort;
>    SYNQUACER_ITS_NODE                        ItsNode;
>    SYNQUACER_RC_NODE                         RcNode[2];
> +  SYNQUACER_SMMU_NODE                       SmmuNode;
> +  SYNQUACER_NC_NODE                         NamedCompNode[2];
>  } SYNQUACER_IO_REMAPPING_STRUCTURE;
>  
>  #define __SYNQUACER_ID_MAPPING(In, Num, Out, Ref, Flags)    \
> @@ -49,7 +63,7 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = {
>      __ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE,
>                    SYNQUACER_IO_REMAPPING_STRUCTURE,
>                    EFI_ACPI_IO_REMAPPING_TABLE_REVISION),
> -    3,                                              // NumNodes
> +    6,                                              // NumNodes
>      sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE),        // NodeOffset
>      0                                               // Reserved
>    }, {
> @@ -94,7 +108,7 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = {
>        //
>        __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode,
>                               EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE),
> -  }, {
> +    }, {
>        // PciRcNode
>        {
>          {
> @@ -121,6 +135,97 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = {
>        __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode,
>                               EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE),
>      }
> +  }, {
> +    // NETSEC/eMMC SMMU node
> +    {
> +      {
> +        EFI_ACPI_IORT_TYPE_SMMUv1v2,
> +        sizeof(SYNQUACER_SMMU_NODE),
> +        0x0,
> +        0x0,
> +        0x0,
> +        0x0,
> +      },
> +      SYNQUACER_SCB_SMMU_BASE,
> +      SYNQUACER_SCB_SMMU_SIZE,
> +      EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500,
> +      EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK,
> +      FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE,
> +                   SMMU_NSgIrpt),
> +      0x8,
> +      sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE),
> +      0x0,
> +      0x0,
> +      228,
> +      EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL,
> +      0x0,
> +      0x0,
> +    }, {
> +      { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, },
> +      { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, },
> +      { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, },
> +      { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, },
> +      { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, },
> +      { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, },
> +      { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, },
> +      { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, },
> +    },
> +  }, {
> +    {
> +      // NETSEC named component node
> +      {
> +        {
> +          EFI_ACPI_IORT_TYPE_NAMED_COMP,
> +          sizeof(SYNQUACER_NC_NODE),
> +          0x0,
> +          0x0,
> +          0x1,
> +          FIELD_OFFSET(SYNQUACER_NC_NODE, RcIdMapping),
> +        },
> +        0x0,
> +        EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,
> +        0x0,
> +        0x0,
> +        EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |
> +        EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS,
> +        40,
> +      }, {
> +        "\\_SB_.NET0"
> +      }, {
> +        0x0,
> +        0x0,
> +        0x0,
> +        FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, SmmuNode),
> +        EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE
> +      }
> +    }, {
> +      // eMMC named component node
> +      {
> +        {
> +          EFI_ACPI_IORT_TYPE_NAMED_COMP,
> +          sizeof(SYNQUACER_NC_NODE),
> +          0x0,
> +          0x0,
> +          0x1,
> +          FIELD_OFFSET(SYNQUACER_NC_NODE, RcIdMapping),
> +        },
> +        0x0,
> +        EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,
> +        0x0,
> +        0x0,
> +        EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM |
> +        EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS,
> +        40,
> +      }, {
> +        "\\_SB_.MMC0"
> +      }, {
> +        0x0,
> +        0x0,
> +        0x0,
> +        FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, SmmuNode),
> +        EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE
> +      }
> +    }
>    }
>  };
>  
> -- 
> 2.17.0
> 


  reply	other threads:[~2018-05-31  9:16 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-30 18:19 [PATCH edk2-platforms 0/3] More SynQuacer updates Ard Biesheuvel
2018-05-30 18:19 ` [PATCH edk2-platforms 1/3] Silicon/SynQuacerPciHostBridgeLib: add workaround for PCIe MMIO64 Ard Biesheuvel
2018-05-31  9:11   ` Leif Lindholm
2018-05-31  9:17     ` Ard Biesheuvel
2018-05-31  9:46       ` Leif Lindholm
2018-05-31 10:49         ` Ard Biesheuvel
2018-05-30 18:19 ` [PATCH edk2-platforms 2/3] Silicon/Socionext/SynQuacer/Stage2Tables: add north SMMU level 3 table Ard Biesheuvel
2018-05-31  9:14   ` Leif Lindholm
2018-06-01 10:18     ` Ard Biesheuvel
2018-05-30 18:19 ` [PATCH edk2-platforms 3/3] Silicon/SynQuacer/AcpiTables: add NETSEC/eMMC SMMU to the IORT Ard Biesheuvel
2018-05-31  9:16   ` Leif Lindholm [this message]
2018-10-12 10:03     ` Ard Biesheuvel

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