From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 23DDB2096109E for ; Thu, 31 May 2018 02:16:26 -0700 (PDT) Received: by mail-wr0-x243.google.com with SMTP id d8-v6so1038680wro.4 for ; Thu, 31 May 2018 02:16:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=oPROr6u3jkxLoXj6SxE4TsJKnOWJQMjI14avFNeCluk=; b=S4eYvxVb2abGS9uxnKf/Nd1PME9U9v24NCwPimsjtc34LCnGSyPvMB2eFg2YUIt6Rw jGU5YzEUqxOmReUoxqH0SaIw9Q1du0KL8IaSnowQtuCgP+cD7C3l2ftUpr4djarUOLRq iAc9A3s71plT+b/I+nOxBPS2s6hwcGODR56yg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=oPROr6u3jkxLoXj6SxE4TsJKnOWJQMjI14avFNeCluk=; b=bUJyfPZKb2W/u/yMEfK5nY0g8R7ReEERSkK8nNrfn9JFeUWLJRRLo8ua/o2dnFxp5u R+h8y3YdEm3WAnVOueoRl36kw48qjZaEXz5lMl4sS2yOOZeVRrDI6iGSxeFpyiX+YzQF WRcbgqrerCpkS8F2ZZpFabEJXOKJlKhyln5bHjNXvZ8bfth8YiN3kby6GfUcJp5lRPoe 3rc07dD/Z8nnfFUNyyflFH3N1zl6a2IJxxqRdwNf1htQD8cpZdpSrXTBK5kNEdQAj9TQ ukvJXd6ogbGkftWM4UYohld1osbi4vkdmiF/trI1t8GmwC633pniZBai1fPD2GQ1DzMd MGJw== X-Gm-Message-State: ALKqPwdBZWU0WlxHoZvJ4d41FVLKvSVeq2Z6lONLq89wycEMZoI6JHNP 1B9U/FDleu8H/yMhCKq98PVDsg== X-Google-Smtp-Source: ADUXVKL719aQdK5tlOx1awvnxIEV5w43wHj+FCAYwWszV4pQY9GQCHiVPChL7QGd4digKXBz8+jCcA== X-Received: by 2002:adf:9b86:: with SMTP id d6-v6mr5107477wrc.240.1527758185477; Thu, 31 May 2018 02:16:25 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id l20-v6sm50178396wrf.90.2018.05.31.02.16.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 31 May 2018 02:16:24 -0700 (PDT) Date: Thu, 31 May 2018 10:16:22 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, masahisa.kojima@linaro.org Message-ID: <20180531091622.3u7dd2kjnu6fhb5w@bivouac.eciton.net> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> <20180530181929.5066-4-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180530181929.5066-4-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 3/3] Silicon/SynQuacer/AcpiTables: add NETSEC/eMMC SMMU to the IORT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 May 2018 09:16:27 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, May 30, 2018 at 08:19:29PM +0200, Ard Biesheuvel wrote: > Add a description of the SMMU that sits in front of the NETSEC and > eMMC controllers to the IORT table so that ACPI based OSes can > utilize it. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Looks reasonable to me. Reviewed-by: Leif Lindholm > --- > Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 109 +++++++++++++++++++- > 1 file changed, 107 insertions(+), 2 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc > index 92c485f8006f..3f2aaa3d8858 100644 > --- a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc > @@ -13,6 +13,7 @@ > **/ > > #include > +#include > > #include "AcpiTables.h" > > @@ -29,10 +30,23 @@ typedef struct { > EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; > } SYNQUACER_RC_NODE; > > +typedef struct { > + EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node; > + EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[8]; > +} SYNQUACER_SMMU_NODE; > + > +typedef struct { > + EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node; > + CONST CHAR8 Name[11]; > + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; > +} SYNQUACER_NC_NODE; > + > typedef struct { > EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; > SYNQUACER_ITS_NODE ItsNode; > SYNQUACER_RC_NODE RcNode[2]; > + SYNQUACER_SMMU_NODE SmmuNode; > + SYNQUACER_NC_NODE NamedCompNode[2]; > } SYNQUACER_IO_REMAPPING_STRUCTURE; > > #define __SYNQUACER_ID_MAPPING(In, Num, Out, Ref, Flags) \ > @@ -49,7 +63,7 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = { > __ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, > SYNQUACER_IO_REMAPPING_STRUCTURE, > EFI_ACPI_IO_REMAPPING_TABLE_REVISION), > - 3, // NumNodes > + 6, // NumNodes > sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset > 0 // Reserved > }, { > @@ -94,7 +108,7 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = { > // > __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, > EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE), > - }, { > + }, { > // PciRcNode > { > { > @@ -121,6 +135,97 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = { > __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, > EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE), > } > + }, { > + // NETSEC/eMMC SMMU node > + { > + { > + EFI_ACPI_IORT_TYPE_SMMUv1v2, > + sizeof(SYNQUACER_SMMU_NODE), > + 0x0, > + 0x0, > + 0x0, > + 0x0, > + }, > + SYNQUACER_SCB_SMMU_BASE, > + SYNQUACER_SCB_SMMU_SIZE, > + EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500, > + EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, > + FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, > + SMMU_NSgIrpt), > + 0x8, > + sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), > + 0x0, > + 0x0, > + 228, > + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, > + 0x0, > + 0x0, > + }, { > + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, > + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, > + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, > + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, > + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, > + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, > + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, > + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, > + }, > + }, { > + { > + // NETSEC named component node > + { > + { > + EFI_ACPI_IORT_TYPE_NAMED_COMP, > + sizeof(SYNQUACER_NC_NODE), > + 0x0, > + 0x0, > + 0x1, > + FIELD_OFFSET(SYNQUACER_NC_NODE, RcIdMapping), > + }, > + 0x0, > + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, > + 0x0, > + 0x0, > + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | > + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, > + 40, > + }, { > + "\\_SB_.NET0" > + }, { > + 0x0, > + 0x0, > + 0x0, > + FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, SmmuNode), > + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE > + } > + }, { > + // eMMC named component node > + { > + { > + EFI_ACPI_IORT_TYPE_NAMED_COMP, > + sizeof(SYNQUACER_NC_NODE), > + 0x0, > + 0x0, > + 0x1, > + FIELD_OFFSET(SYNQUACER_NC_NODE, RcIdMapping), > + }, > + 0x0, > + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, > + 0x0, > + 0x0, > + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | > + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, > + 40, > + }, { > + "\\_SB_.MMC0" > + }, { > + 0x0, > + 0x0, > + 0x0, > + FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, SmmuNode), > + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE > + } > + } > } > }; > > -- > 2.17.0 >